1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 *
24 */
25
26 #include <xf86drm.h>
27 #include "drm-uapi/nouveau_drm.h"
28 #include "util/format/u_format.h"
29 #include "util/format/u_format_s3tc.h"
30 #include "util/u_screen.h"
31
32 #include "nv_object.xml.h"
33 #include "nv_m2mf.xml.h"
34 #include "nv30/nv30-40_3d.xml.h"
35 #include "nv30/nv01_2d.xml.h"
36
37 #include "nouveau_fence.h"
38 #include "nv30/nv30_screen.h"
39 #include "nv30/nv30_context.h"
40 #include "nv30/nv30_resource.h"
41 #include "nv30/nv30_format.h"
42 #include "nv30/nv30_winsys.h"
43
44 #define RANKINE_0397_CHIPSET 0x00000003
45 #define RANKINE_0497_CHIPSET 0x000001e0
46 #define RANKINE_0697_CHIPSET 0x00000010
47 #define CURIE_4097_CHIPSET 0x00000baf
48 #define CURIE_4497_CHIPSET 0x00005450
49 #define CURIE_4497_CHIPSET6X 0x00000088
50
51 static int
nv30_screen_get_param(struct pipe_screen * pscreen,enum pipe_cap param)52 nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
53 {
54 struct nv30_screen *screen = nv30_screen(pscreen);
55 struct nouveau_object *eng3d = screen->eng3d;
56 struct nouveau_device *dev = nouveau_screen(pscreen)->device;
57
58 switch (param) {
59 /* non-boolean capabilities */
60 case PIPE_CAP_MAX_RENDER_TARGETS:
61 return (eng3d->oclass >= NV40_3D_CLASS) ? 4 : 1;
62 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
63 return 4096;
64 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
65 return 10;
66 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
67 return 13;
68 case PIPE_CAP_GLSL_FEATURE_LEVEL:
69 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
70 return 120;
71 case PIPE_CAP_ENDIANNESS:
72 return PIPE_ENDIAN_LITTLE;
73 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
74 return 16;
75 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
76 return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
77 case PIPE_CAP_MAX_VIEWPORTS:
78 return 1;
79 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
80 return 2048;
81 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
82 return 8 * 1024 * 1024;
83 case PIPE_CAP_MAX_VARYINGS:
84 return 8;
85
86 /* supported capabilities */
87 case PIPE_CAP_ANISOTROPIC_FILTER:
88 case PIPE_CAP_OCCLUSION_QUERY:
89 case PIPE_CAP_QUERY_TIME_ELAPSED:
90 case PIPE_CAP_QUERY_TIMESTAMP:
91 case PIPE_CAP_TEXTURE_SWIZZLE:
92 case PIPE_CAP_DEPTH_CLIP_DISABLE:
93 case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
94 case PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT:
95 case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
96 case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
97 case PIPE_CAP_TGSI_TEXCOORD:
98 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
99 case PIPE_CAP_CLEAR_SCISSORED:
100 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
101 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
102 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
103 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
104 case PIPE_CAP_QUERY_MEMORY_INFO:
105 return 1;
106 case PIPE_CAP_TEXTURE_TRANSFER_MODES:
107 return PIPE_TEXTURE_TRANSFER_BLIT;
108 /* nv35 capabilities */
109 case PIPE_CAP_DEPTH_BOUNDS_TEST:
110 return eng3d->oclass == NV35_3D_CLASS || eng3d->oclass >= NV40_3D_CLASS;
111 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART:
112 case PIPE_CAP_SUPPORTED_PRIM_MODES:
113 return BITFIELD_MASK(MESA_PRIM_COUNT);
114 /* nv4x capabilities */
115 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
116 case PIPE_CAP_NPOT_TEXTURES:
117 case PIPE_CAP_CONDITIONAL_RENDER:
118 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
119 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
120 case PIPE_CAP_PRIMITIVE_RESTART:
121 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
122 return (eng3d->oclass >= NV40_3D_CLASS) ? 1 : 0;
123 /* unsupported */
124 case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
125 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
126 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
127 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
128 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
129 case PIPE_CAP_INDEP_BLEND_ENABLE:
130 case PIPE_CAP_INDEP_BLEND_FUNC:
131 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
132 case PIPE_CAP_SHADER_STENCIL_EXPORT:
133 case PIPE_CAP_VS_INSTANCEID:
134 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: /* XXX: yes? */
135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
136 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
137 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
138 case PIPE_CAP_MIN_TEXEL_OFFSET:
139 case PIPE_CAP_MAX_TEXEL_OFFSET:
140 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
141 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
142 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
143 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
144 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
145 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
146 case PIPE_CAP_MAX_VERTEX_STREAMS:
147 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
148 case PIPE_CAP_TEXTURE_BARRIER:
149 case PIPE_CAP_SEAMLESS_CUBE_MAP:
150 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
151 case PIPE_CAP_CUBE_MAP_ARRAY:
152 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
153 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
154 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
155 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
156 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
157 case PIPE_CAP_START_INSTANCE:
158 case PIPE_CAP_TEXTURE_MULTISAMPLE:
159 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
160 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
161 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
162 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
163 case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
164 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
165 case PIPE_CAP_VS_LAYER_VIEWPORT:
166 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
167 case PIPE_CAP_TEXTURE_GATHER_SM5:
168 case PIPE_CAP_FAKE_SW_MSAA:
169 case PIPE_CAP_TEXTURE_QUERY_LOD:
170 case PIPE_CAP_SAMPLE_SHADING:
171 case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
172 case PIPE_CAP_VS_WINDOW_SPACE_POSITION:
173 case PIPE_CAP_USER_VERTEX_BUFFERS:
174 case PIPE_CAP_COMPUTE:
175 case PIPE_CAP_DRAW_INDIRECT:
176 case PIPE_CAP_MULTI_DRAW_INDIRECT:
177 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
178 case PIPE_CAP_FS_FINE_DERIVATIVE:
179 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
180 case PIPE_CAP_SAMPLER_VIEW_TARGET:
181 case PIPE_CAP_CLIP_HALFZ:
182 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
183 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
184 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
185 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
186 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
187 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
188 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
189 case PIPE_CAP_TEXTURE_QUERY_SAMPLES:
190 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
191 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
192 case PIPE_CAP_SHAREABLE_SHADERS:
193 case PIPE_CAP_DRAW_PARAMETERS:
194 case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
195 case PIPE_CAP_FS_POSITION_IS_SYSVAL:
196 case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
197 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
198 case PIPE_CAP_INVALIDATE_BUFFER:
199 case PIPE_CAP_GENERATE_MIPMAP:
200 case PIPE_CAP_STRING_MARKER:
201 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
202 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
203 case PIPE_CAP_QUERY_BUFFER_OBJECT:
204 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
205 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
206 case PIPE_CAP_CULL_DISTANCE:
207 case PIPE_CAP_SHADER_GROUP_VOTE:
208 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
209 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
210 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
211 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
212 case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
213 case PIPE_CAP_NATIVE_FENCE_FD:
214 case PIPE_CAP_FBFETCH:
215 case PIPE_CAP_LEGACY_MATH_RULES:
216 case PIPE_CAP_DOUBLES:
217 case PIPE_CAP_INT64:
218 case PIPE_CAP_TGSI_TEX_TXF_LZ:
219 case PIPE_CAP_SHADER_CLOCK:
220 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
221 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
222 case PIPE_CAP_SHADER_BALLOT:
223 case PIPE_CAP_TES_LAYER_VIEWPORT:
224 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
225 case PIPE_CAP_POST_DEPTH_COVERAGE:
226 case PIPE_CAP_BINDLESS_TEXTURE:
227 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
228 case PIPE_CAP_QUERY_SO_OVERFLOW:
229 case PIPE_CAP_MEMOBJ:
230 case PIPE_CAP_LOAD_CONSTBUF:
231 case PIPE_CAP_TILE_RASTER_ORDER:
232 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
233 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
234 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
235 case PIPE_CAP_CONTEXT_PRIORITY_MASK:
236 case PIPE_CAP_FENCE_SIGNAL:
237 case PIPE_CAP_CONSTBUF0_FLAGS:
238 case PIPE_CAP_PACKED_UNIFORMS:
239 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
240 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
241 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
242 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
243 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
244 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
245 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
246 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
247 case PIPE_CAP_TGSI_DIV:
248 case PIPE_CAP_IMAGE_ATOMIC_INC_WRAP:
249 case PIPE_CAP_IMAGE_STORE_FORMATTED:
250 return 0;
251
252 case PIPE_CAP_PCI_GROUP:
253 return dev->info.pci.domain;
254 case PIPE_CAP_PCI_BUS:
255 return dev->info.pci.bus;
256 case PIPE_CAP_PCI_DEVICE:
257 return dev->info.pci.dev;
258 case PIPE_CAP_PCI_FUNCTION:
259 return dev->info.pci.func;
260
261 case PIPE_CAP_MAX_GS_INVOCATIONS:
262 return 32;
263 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE_UINT:
264 return 1 << 27;
265 case PIPE_CAP_VENDOR_ID:
266 return 0x10de;
267 case PIPE_CAP_DEVICE_ID:
268 return dev->info.device_id;
269 case PIPE_CAP_ACCELERATED:
270 return 1;
271 case PIPE_CAP_VIDEO_MEMORY:
272 return dev->vram_size >> 20;
273 case PIPE_CAP_UMA:
274 return 0;
275 default:
276 return u_pipe_screen_get_param_defaults(pscreen, param);
277 }
278 }
279
280 static float
nv30_screen_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)281 nv30_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
282 {
283 struct nv30_screen *screen = nv30_screen(pscreen);
284 struct nouveau_object *eng3d = screen->eng3d;
285
286 switch (param) {
287 case PIPE_CAPF_MIN_LINE_WIDTH:
288 case PIPE_CAPF_MIN_LINE_WIDTH_AA:
289 case PIPE_CAPF_MIN_POINT_SIZE:
290 case PIPE_CAPF_MIN_POINT_SIZE_AA:
291 return 1;
292 case PIPE_CAPF_POINT_SIZE_GRANULARITY:
293 case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
294 return 0.1;
295 case PIPE_CAPF_MAX_LINE_WIDTH:
296 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
297 return 10.0;
298 case PIPE_CAPF_MAX_POINT_SIZE:
299 case PIPE_CAPF_MAX_POINT_SIZE_AA:
300 return 64.0;
301 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
302 return (eng3d->oclass >= NV40_3D_CLASS) ? 16.0 : 8.0;
303 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
304 return 15.0;
305 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
306 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
307 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
308 return 0.0;
309 default:
310 debug_printf("unknown paramf %d\n", param);
311 return 0;
312 }
313 }
314
315 static int
nv30_screen_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)316 nv30_screen_get_shader_param(struct pipe_screen *pscreen,
317 enum pipe_shader_type shader,
318 enum pipe_shader_cap param)
319 {
320 struct nv30_screen *screen = nv30_screen(pscreen);
321 struct nouveau_object *eng3d = screen->eng3d;
322
323 switch (shader) {
324 case PIPE_SHADER_VERTEX:
325 switch (param) {
326 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
327 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
328 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 256;
329 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
330 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
331 return (eng3d->oclass >= NV40_3D_CLASS) ? 512 : 0;
332 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
333 return 0;
334 case PIPE_SHADER_CAP_MAX_INPUTS:
335 case PIPE_SHADER_CAP_MAX_OUTPUTS:
336 return 16;
337 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
338 return ((eng3d->oclass >= NV40_3D_CLASS) ? (468 - 6): (256 - 6)) * sizeof(float[4]);
339 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
340 return 1;
341 case PIPE_SHADER_CAP_MAX_TEMPS:
342 return (eng3d->oclass >= NV40_3D_CLASS) ? 32 : 13;
343 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
344 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
345 return 0;
346 case PIPE_SHADER_CAP_CONT_SUPPORTED:
347 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
348 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
349 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
350 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
351 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
352 case PIPE_SHADER_CAP_SUBROUTINES:
353 case PIPE_SHADER_CAP_INTEGERS:
354 case PIPE_SHADER_CAP_INT64_ATOMICS:
355 case PIPE_SHADER_CAP_FP16:
356 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
357 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
358 case PIPE_SHADER_CAP_INT16:
359 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
360 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
361 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
362 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
363 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
364 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
365 return 0;
366 case PIPE_SHADER_CAP_SUPPORTED_IRS:
367 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
368 default:
369 debug_printf("unknown vertex shader param %d\n", param);
370 return 0;
371 }
372 break;
373 case PIPE_SHADER_FRAGMENT:
374 switch (param) {
375 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
376 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
377 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
378 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
379 return 4096;
380 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
381 return 0;
382 case PIPE_SHADER_CAP_MAX_INPUTS:
383 return 8; /* should be possible to do 10 with nv4x */
384 case PIPE_SHADER_CAP_MAX_OUTPUTS:
385 return 4;
386 case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
387 return ((eng3d->oclass >= NV40_3D_CLASS) ? 224 : 32) * sizeof(float[4]);
388 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
389 return 1;
390 case PIPE_SHADER_CAP_MAX_TEMPS:
391 return 32;
392 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
393 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
394 return 16;
395 case PIPE_SHADER_CAP_CONT_SUPPORTED:
396 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
397 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
398 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
399 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
400 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
401 case PIPE_SHADER_CAP_SUBROUTINES:
402 case PIPE_SHADER_CAP_INTEGERS:
403 case PIPE_SHADER_CAP_FP16:
404 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
405 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
406 case PIPE_SHADER_CAP_INT16:
407 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
408 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
409 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
410 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
411 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
412 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
413 return 0;
414 case PIPE_SHADER_CAP_SUPPORTED_IRS:
415 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_TGSI);
416 default:
417 debug_printf("unknown fragment shader param %d\n", param);
418 return 0;
419 }
420 break;
421 default:
422 return 0;
423 }
424 }
425
426 static bool
nv30_screen_is_format_supported(struct pipe_screen * pscreen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bindings)427 nv30_screen_is_format_supported(struct pipe_screen *pscreen,
428 enum pipe_format format,
429 enum pipe_texture_target target,
430 unsigned sample_count,
431 unsigned storage_sample_count,
432 unsigned bindings)
433 {
434 if (sample_count > nv30_screen(pscreen)->max_sample_count)
435 return false;
436
437 if (!(0x00000017 & (1 << sample_count)))
438 return false;
439
440 if (MAX2(1, sample_count) != MAX2(1, storage_sample_count))
441 return false;
442
443 /* No way to render to a swizzled 3d texture. We don't necessarily know if
444 * it's swizzled or not here, but we have to assume anyways.
445 */
446 if (target == PIPE_TEXTURE_3D && (bindings & PIPE_BIND_RENDER_TARGET))
447 return false;
448
449 /* shared is always supported */
450 bindings &= ~PIPE_BIND_SHARED;
451
452 if (bindings & PIPE_BIND_INDEX_BUFFER) {
453 if (format != PIPE_FORMAT_R8_UINT &&
454 format != PIPE_FORMAT_R16_UINT &&
455 format != PIPE_FORMAT_R32_UINT)
456 return false;
457 bindings &= ~PIPE_BIND_INDEX_BUFFER;
458 }
459
460 return (nv30_format_info(pscreen, format)->bindings & bindings) == bindings;
461 }
462
463 static const nir_shader_compiler_options nv30_base_compiler_options = {
464 .fuse_ffma32 = true,
465 .fuse_ffma64 = true,
466 .lower_bitops = true,
467 .lower_extract_byte = true,
468 .lower_extract_word = true,
469 .lower_fdiv = true,
470 .lower_fsat = true,
471 .lower_insert_byte = true,
472 .lower_insert_word = true,
473 .lower_fdph = true,
474 .lower_flrp32 = true,
475 .lower_flrp64 = true,
476 .lower_fmod = true,
477 .lower_fpow = true, /* In hardware as of nv40 FS */
478 .lower_uniforms_to_ubo = true,
479 .lower_vector_cmp = true,
480 .force_indirect_unrolling = nir_var_all,
481 .force_indirect_unrolling_sampler = true,
482 .max_unroll_iterations = 32,
483 .no_integers = true,
484
485 .use_interpolated_input_intrinsics = true,
486 .has_ddx_intrinsics = true,
487 };
488
489 static const void *
nv30_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)490 nv30_screen_get_compiler_options(struct pipe_screen *pscreen,
491 enum pipe_shader_ir ir,
492 enum pipe_shader_type shader)
493 {
494 struct nv30_screen *screen = nv30_screen(pscreen);
495 assert(ir == PIPE_SHADER_IR_NIR);
496
497 /* The FS compiler options are different between nv30 and nv40, and are set
498 * up at screen creation time.
499 */
500 if (shader == PIPE_SHADER_FRAGMENT)
501 return &screen->fs_compiler_options;
502
503 return &nv30_base_compiler_options;
504 }
505
506 static void
nv30_screen_fence_emit(struct pipe_context * pcontext,uint32_t * sequence,struct nouveau_bo * wait)507 nv30_screen_fence_emit(struct pipe_context *pcontext, uint32_t *sequence,
508 struct nouveau_bo *wait)
509 {
510 struct nv30_context *nv30 = nv30_context(pcontext);
511 struct nv30_screen *screen = nv30->screen;
512 struct nouveau_pushbuf *push = nv30->base.pushbuf;
513 struct nouveau_pushbuf_refn ref = { wait, NOUVEAU_BO_GART | NOUVEAU_BO_RDWR };
514
515 *sequence = ++screen->base.fence.sequence;
516
517 assert(PUSH_AVAIL(push) + push->rsvd_kick >= 3);
518 PUSH_DATA (push, NV30_3D_FENCE_OFFSET |
519 (2 /* size */ << 18) | (7 /* subchan */ << 13));
520 PUSH_DATA (push, 0);
521 PUSH_DATA (push, *sequence);
522
523 nouveau_pushbuf_refn(push, &ref, 1);
524 }
525
526 static uint32_t
nv30_screen_fence_update(struct pipe_screen * pscreen)527 nv30_screen_fence_update(struct pipe_screen *pscreen)
528 {
529 struct nv30_screen *screen = nv30_screen(pscreen);
530 struct nv04_notify *fence = screen->fence->data;
531 return *(uint32_t *)((char *)screen->notify->map + fence->offset);
532 }
533
534 static void
nv30_screen_destroy(struct pipe_screen * pscreen)535 nv30_screen_destroy(struct pipe_screen *pscreen)
536 {
537 struct nv30_screen *screen = nv30_screen(pscreen);
538
539 if (!nouveau_drm_screen_unref(&screen->base))
540 return;
541
542 nouveau_bo_ref(NULL, &screen->notify);
543
544 nouveau_heap_destroy(&screen->query_heap);
545 nouveau_heap_destroy(&screen->vp_exec_heap);
546 nouveau_heap_destroy(&screen->vp_data_heap);
547
548 nouveau_object_del(&screen->query);
549 nouveau_object_del(&screen->fence);
550 nouveau_object_del(&screen->ntfy);
551
552 nouveau_object_del(&screen->sifm);
553 nouveau_object_del(&screen->swzsurf);
554 nouveau_object_del(&screen->surf2d);
555 nouveau_object_del(&screen->m2mf);
556 nouveau_object_del(&screen->eng3d);
557 nouveau_object_del(&screen->null);
558
559 nouveau_screen_fini(&screen->base);
560 FREE(screen);
561 }
562
563 #define FAIL_SCREEN_INIT(str, err) \
564 do { \
565 NOUVEAU_ERR(str, err); \
566 screen->base.base.context_create = NULL; \
567 return &screen->base; \
568 } while(0)
569
570 struct nouveau_screen *
nv30_screen_create(struct nouveau_device * dev)571 nv30_screen_create(struct nouveau_device *dev)
572 {
573 struct nv30_screen *screen;
574 struct pipe_screen *pscreen;
575 struct nouveau_pushbuf *push;
576 struct nv04_fifo *fifo;
577 unsigned oclass = 0;
578 int ret, i;
579
580 switch (dev->chipset & 0xf0) {
581 case 0x30:
582 if (RANKINE_0397_CHIPSET & (1 << (dev->chipset & 0x0f)))
583 oclass = NV30_3D_CLASS;
584 else
585 if (RANKINE_0697_CHIPSET & (1 << (dev->chipset & 0x0f)))
586 oclass = NV34_3D_CLASS;
587 else
588 if (RANKINE_0497_CHIPSET & (1 << (dev->chipset & 0x0f)))
589 oclass = NV35_3D_CLASS;
590 break;
591 case 0x40:
592 if (CURIE_4097_CHIPSET & (1 << (dev->chipset & 0x0f)))
593 oclass = NV40_3D_CLASS;
594 else
595 if (CURIE_4497_CHIPSET & (1 << (dev->chipset & 0x0f)))
596 oclass = NV44_3D_CLASS;
597 break;
598 case 0x60:
599 if (CURIE_4497_CHIPSET6X & (1 << (dev->chipset & 0x0f)))
600 oclass = NV44_3D_CLASS;
601 break;
602 default:
603 break;
604 }
605
606 if (!oclass) {
607 NOUVEAU_ERR("unknown 3d class for 0x%02x\n", dev->chipset);
608 return NULL;
609 }
610
611 screen = CALLOC_STRUCT(nv30_screen);
612 if (!screen)
613 return NULL;
614
615 pscreen = &screen->base.base;
616 pscreen->destroy = nv30_screen_destroy;
617
618 /*
619 * Some modern apps try to use msaa without keeping in mind the
620 * restrictions on videomem of older cards. Resulting in dmesg saying:
621 * [ 1197.850642] nouveau E[soffice.bin[3785]] fail ttm_validate
622 * [ 1197.850648] nouveau E[soffice.bin[3785]] validating bo list
623 * [ 1197.850654] nouveau E[soffice.bin[3785]] validate: -12
624 *
625 * Because we are running out of video memory, after which the program
626 * using the msaa visual freezes, and eventually the entire system freezes.
627 *
628 * To work around this we do not allow msaa visauls by default and allow
629 * the user to override this via NV30_MAX_MSAA.
630 */
631 screen->max_sample_count = debug_get_num_option("NV30_MAX_MSAA", 0);
632 if (screen->max_sample_count > 4)
633 screen->max_sample_count = 4;
634
635 pscreen->get_param = nv30_screen_get_param;
636 pscreen->get_paramf = nv30_screen_get_paramf;
637 pscreen->get_shader_param = nv30_screen_get_shader_param;
638 pscreen->context_create = nv30_context_create;
639 pscreen->is_format_supported = nv30_screen_is_format_supported;
640 pscreen->get_compiler_options = nv30_screen_get_compiler_options;
641
642 nv30_resource_screen_init(pscreen);
643 nouveau_screen_init_vdec(&screen->base);
644
645 screen->base.fence.emit = nv30_screen_fence_emit;
646 screen->base.fence.update = nv30_screen_fence_update;
647
648 ret = nouveau_screen_init(&screen->base, dev);
649 if (ret)
650 FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
651
652 screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
653 screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
654 if (oclass == NV40_3D_CLASS) {
655 screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
656 screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
657 }
658
659 screen->fs_compiler_options = nv30_base_compiler_options;
660 screen->fs_compiler_options.lower_fsat = false;
661 if (oclass >= NV40_3D_CLASS)
662 screen->fs_compiler_options.lower_fpow = false;
663
664 fifo = screen->base.channel->data;
665 push = screen->base.pushbuf;
666 push->rsvd_kick = 16;
667
668 ret = nouveau_object_new(screen->base.channel, 0x00000000, NV01_NULL_CLASS,
669 NULL, 0, &screen->null);
670 if (ret)
671 FAIL_SCREEN_INIT("error allocating null object: %d\n", ret);
672
673 /* DMA_FENCE refuses to accept DMA objects with "adjust" filled in,
674 * this means that the address pointed at by the DMA object must
675 * be 4KiB aligned, which means this object needs to be the first
676 * one allocated on the channel.
677 */
678 ret = nouveau_object_new(screen->base.channel, 0xbeef1e00,
679 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
680 .length = 32 }, sizeof(struct nv04_notify),
681 &screen->fence);
682 if (ret)
683 FAIL_SCREEN_INIT("error allocating fence notifier: %d\n", ret);
684
685 /* DMA_NOTIFY object, we don't actually use this but M2MF fails without */
686 ret = nouveau_object_new(screen->base.channel, 0xbeef0301,
687 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
688 .length = 32 }, sizeof(struct nv04_notify),
689 &screen->ntfy);
690 if (ret)
691 FAIL_SCREEN_INIT("error allocating sync notifier: %d\n", ret);
692
693 /* DMA_QUERY, used to implement occlusion queries, we attempt to allocate
694 * the remainder of the "notifier block" assigned by the kernel for
695 * use as query objects
696 */
697 ret = nouveau_object_new(screen->base.channel, 0xbeef0351,
698 NOUVEAU_NOTIFIER_CLASS, &(struct nv04_notify) {
699 .length = 4096 - 128 }, sizeof(struct nv04_notify),
700 &screen->query);
701 if (ret)
702 FAIL_SCREEN_INIT("error allocating query notifier: %d\n", ret);
703
704 ret = nouveau_heap_init(&screen->query_heap, 0, 4096 - 128);
705 if (ret)
706 FAIL_SCREEN_INIT("error creating query heap: %d\n", ret);
707
708 list_inithead(&screen->queries);
709
710 /* Vertex program resources (code/data), currently 6 of the constant
711 * slots are reserved to implement user clipping planes
712 */
713 if (oclass < NV40_3D_CLASS) {
714 nouveau_heap_init(&screen->vp_exec_heap, 0, 256);
715 nouveau_heap_init(&screen->vp_data_heap, 6, 256 - 6);
716 } else {
717 nouveau_heap_init(&screen->vp_exec_heap, 0, 512);
718 nouveau_heap_init(&screen->vp_data_heap, 6, 468 - 6);
719 }
720
721 ret = nouveau_bo_wrap(screen->base.device, fifo->base.notify, &screen->notify);
722 if (ret == 0)
723 ret = BO_MAP(&screen->base, screen->notify, 0, screen->base.client);
724 if (ret)
725 FAIL_SCREEN_INIT("error mapping notifier memory: %d\n", ret);
726
727 ret = nouveau_object_new(screen->base.channel, 0xbeef3097, oclass,
728 NULL, 0, &screen->eng3d);
729 if (ret)
730 FAIL_SCREEN_INIT("error allocating 3d object: %d\n", ret);
731
732 BEGIN_NV04(push, NV01_SUBC(3D, OBJECT), 1);
733 PUSH_DATA (push, screen->eng3d->handle);
734 BEGIN_NV04(push, NV30_3D(DMA_NOTIFY), 13);
735 PUSH_DATA (push, screen->ntfy->handle);
736 PUSH_DATA (push, fifo->vram); /* TEXTURE0 */
737 PUSH_DATA (push, fifo->gart); /* TEXTURE1 */
738 PUSH_DATA (push, fifo->vram); /* COLOR1 */
739 PUSH_DATA (push, screen->null->handle); /* UNK190 */
740 PUSH_DATA (push, fifo->vram); /* COLOR0 */
741 PUSH_DATA (push, fifo->vram); /* ZETA */
742 PUSH_DATA (push, fifo->vram); /* VTXBUF0 */
743 PUSH_DATA (push, fifo->gart); /* VTXBUF1 */
744 PUSH_DATA (push, screen->fence->handle); /* FENCE */
745 PUSH_DATA (push, screen->query->handle); /* QUERY - intr 0x80 if nullobj */
746 PUSH_DATA (push, screen->null->handle); /* UNK1AC */
747 PUSH_DATA (push, screen->null->handle); /* UNK1B0 */
748 if (screen->eng3d->oclass < NV40_3D_CLASS) {
749 BEGIN_NV04(push, SUBC_3D(0x03b0), 1);
750 PUSH_DATA (push, 0x00100000);
751 BEGIN_NV04(push, SUBC_3D(0x1d80), 1);
752 PUSH_DATA (push, 3);
753
754 BEGIN_NV04(push, SUBC_3D(0x1e98), 1);
755 PUSH_DATA (push, 0);
756 BEGIN_NV04(push, SUBC_3D(0x17e0), 3);
757 PUSH_DATA (push, fui(0.0));
758 PUSH_DATA (push, fui(0.0));
759 PUSH_DATA (push, fui(1.0));
760 BEGIN_NV04(push, SUBC_3D(0x1f80), 16);
761 for (i = 0; i < 16; i++)
762 PUSH_DATA (push, (i == 8) ? 0x0000ffff : 0);
763
764 BEGIN_NV04(push, NV30_3D(RC_ENABLE), 1);
765 PUSH_DATA (push, 0);
766 } else {
767 BEGIN_NV04(push, NV40_3D(DMA_COLOR2), 2);
768 PUSH_DATA (push, fifo->vram);
769 PUSH_DATA (push, fifo->vram); /* COLOR3 */
770
771 BEGIN_NV04(push, SUBC_3D(0x1450), 1);
772 PUSH_DATA (push, 0x00000004);
773
774 BEGIN_NV04(push, SUBC_3D(0x1ea4), 3); /* ZCULL */
775 PUSH_DATA (push, 0x00000010);
776 PUSH_DATA (push, 0x01000100);
777 PUSH_DATA (push, 0xff800006);
778
779 /* vtxprog output routing */
780 BEGIN_NV04(push, SUBC_3D(0x1fc4), 1);
781 PUSH_DATA (push, 0x06144321);
782 BEGIN_NV04(push, SUBC_3D(0x1fc8), 2);
783 PUSH_DATA (push, 0xedcba987);
784 PUSH_DATA (push, 0x0000006f);
785 BEGIN_NV04(push, SUBC_3D(0x1fd0), 1);
786 PUSH_DATA (push, 0x00171615);
787 BEGIN_NV04(push, SUBC_3D(0x1fd4), 1);
788 PUSH_DATA (push, 0x001b1a19);
789
790 BEGIN_NV04(push, SUBC_3D(0x1ef8), 1);
791 PUSH_DATA (push, 0x0020ffff);
792 BEGIN_NV04(push, SUBC_3D(0x1d64), 1);
793 PUSH_DATA (push, 0x01d300d4);
794
795 BEGIN_NV04(push, NV40_3D(MIPMAP_ROUNDING), 1);
796 PUSH_DATA (push, NV40_3D_MIPMAP_ROUNDING_MODE_DOWN);
797 }
798
799 ret = nouveau_object_new(screen->base.channel, 0xbeef3901, NV03_M2MF_CLASS,
800 NULL, 0, &screen->m2mf);
801 if (ret)
802 FAIL_SCREEN_INIT("error allocating m2mf object: %d\n", ret);
803
804 BEGIN_NV04(push, NV01_SUBC(M2MF, OBJECT), 1);
805 PUSH_DATA (push, screen->m2mf->handle);
806 BEGIN_NV04(push, NV03_M2MF(DMA_NOTIFY), 1);
807 PUSH_DATA (push, screen->ntfy->handle);
808
809 ret = nouveau_object_new(screen->base.channel, 0xbeef6201,
810 NV10_SURFACE_2D_CLASS, NULL, 0, &screen->surf2d);
811 if (ret)
812 FAIL_SCREEN_INIT("error allocating surf2d object: %d\n", ret);
813
814 BEGIN_NV04(push, NV01_SUBC(SF2D, OBJECT), 1);
815 PUSH_DATA (push, screen->surf2d->handle);
816 BEGIN_NV04(push, NV04_SF2D(DMA_NOTIFY), 1);
817 PUSH_DATA (push, screen->ntfy->handle);
818
819 if (dev->chipset < 0x40)
820 oclass = NV30_SURFACE_SWZ_CLASS;
821 else
822 oclass = NV40_SURFACE_SWZ_CLASS;
823
824 ret = nouveau_object_new(screen->base.channel, 0xbeef5201, oclass,
825 NULL, 0, &screen->swzsurf);
826 if (ret)
827 FAIL_SCREEN_INIT("error allocating swizzled surface object: %d\n", ret);
828
829 BEGIN_NV04(push, NV01_SUBC(SSWZ, OBJECT), 1);
830 PUSH_DATA (push, screen->swzsurf->handle);
831 BEGIN_NV04(push, NV04_SSWZ(DMA_NOTIFY), 1);
832 PUSH_DATA (push, screen->ntfy->handle);
833
834 if (dev->chipset < 0x40)
835 oclass = NV30_SIFM_CLASS;
836 else
837 oclass = NV40_SIFM_CLASS;
838
839 ret = nouveau_object_new(screen->base.channel, 0xbeef7701, oclass,
840 NULL, 0, &screen->sifm);
841 if (ret)
842 FAIL_SCREEN_INIT("error allocating scaled image object: %d\n", ret);
843
844 BEGIN_NV04(push, NV01_SUBC(SIFM, OBJECT), 1);
845 PUSH_DATA (push, screen->sifm->handle);
846 BEGIN_NV04(push, NV03_SIFM(DMA_NOTIFY), 1);
847 PUSH_DATA (push, screen->ntfy->handle);
848 BEGIN_NV04(push, NV05_SIFM(COLOR_CONVERSION), 1);
849 PUSH_DATA (push, NV05_SIFM_COLOR_CONVERSION_TRUNCATE);
850 PUSH_KICK (push);
851
852 return &screen->base;
853 }
854