1 /*
2 * Copyright (c) 2018-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8
9 #include <platform_def.h>
10
11 #include <common/bl_common.h>
12 #include <common/debug.h>
13 #include <drivers/arm/ccn.h>
14 #include <drivers/arm/css/sds.h>
15 #include <lib/utils_def.h>
16 #include <plat/arm/common/plat_arm.h>
17 #include <plat/common/platform.h>
18 #include <drivers/arm/sbsa.h>
19
20 #if SPM_MM
21 #include <services/spm_mm_partition.h>
22 #endif
23
24 /*
25 * Table of regions for different BL stages to map using the MMU.
26 * This doesn't include Trusted RAM as the 'mem_layout' argument passed to
27 * arm_configure_mmu_elx() will give the available subset of that.
28 *
29 * Replace or extend the below regions as required
30 */
31 #if IMAGE_BL1
32 const mmap_region_t plat_arm_mmap[] = {
33 ARM_MAP_SHARED_RAM,
34 NRD_MAP_FLASH0_RO,
35 NRD_CSS_PERIPH_MMAP(0),
36 NRD_ROS_PERIPH_MMAP(0),
37 {0}
38 };
39 #endif
40 #if IMAGE_BL2
41 const mmap_region_t plat_arm_mmap[] = {
42 ARM_MAP_SHARED_RAM,
43 NRD_MAP_FLASH0_RO,
44 #ifdef PLAT_ARM_MEM_PROT_ADDR
45 ARM_V2M_MAP_MEM_PROTECT,
46 #endif
47 NRD_CSS_PERIPH_MMAP(0),
48 NRD_ROS_PERIPH_MMAP(0),
49 ARM_MAP_NS_DRAM1,
50 #if NRD_CHIP_COUNT > 1
51 NRD_CSS_PERIPH_MMAP(1),
52 #endif
53 #if NRD_CHIP_COUNT > 2
54 NRD_CSS_PERIPH_MMAP(2),
55 #endif
56 #if NRD_CHIP_COUNT > 3
57 NRD_CSS_PERIPH_MMAP(3),
58 #endif
59 #if ARM_BL31_IN_DRAM
60 ARM_MAP_BL31_SEC_DRAM,
61 #endif
62 #if SPM_MM
63 ARM_SP_IMAGE_MMAP,
64 #endif
65 #if TRUSTED_BOARD_BOOT && !RESET_TO_BL2
66 ARM_MAP_BL1_RW,
67 #endif
68 {0}
69 };
70 #endif
71 #if IMAGE_BL31
72 const mmap_region_t plat_arm_mmap[] = {
73 ARM_MAP_SHARED_RAM,
74 V2M_MAP_IOFPGA,
75 NRD_CSS_PERIPH_MMAP(0),
76 #ifdef PLAT_ARM_MEM_PROT_ADDR
77 ARM_V2M_MAP_MEM_PROTECT,
78 #endif
79 NRD_ROS_PERIPH_MMAP(0),
80 #if SPM_MM
81 ARM_SPM_BUF_EL3_MMAP,
82 #endif
83 {0}
84 };
85
86 #if SPM_MM && defined(IMAGE_BL31)
87 const mmap_region_t plat_arm_secure_partition_mmap[] = {
88 NRD_ROS_SECURE_SYSTEMREG_USER_MMAP,
89 NRD_ROS_SECURE_NOR2_USER_MMAP,
90 NRD_CSS_SECURE_UART_MMAP,
91 ARM_SP_IMAGE_MMAP,
92 ARM_SP_IMAGE_NS_BUF_MMAP,
93 ARM_SP_IMAGE_RW_MMAP,
94 ARM_SPM_BUF_EL0_MMAP,
95 {0}
96 };
97 #endif /* SPM_MM && defined(IMAGE_BL31) */
98 #endif
99
100 ARM_CASSERT_MMAP
101
102 #if SPM_MM && defined(IMAGE_BL31)
103 /*
104 * Boot information passed to a secure partition during initialisation. Linear
105 * indices in MP information will be filled at runtime.
106 */
107 static spm_mm_mp_info_t sp_mp_info[] = {
108 [0] = {0x81000000, 0},
109 [1] = {0x81000100, 0},
110 [2] = {0x81000200, 0},
111 [3] = {0x81000300, 0},
112 [4] = {0x81010000, 0},
113 [5] = {0x81010100, 0},
114 [6] = {0x81010200, 0},
115 [7] = {0x81010300, 0},
116 };
117
118 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = {
119 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
120 .h.version = VERSION_1,
121 .h.size = sizeof(spm_mm_boot_info_t),
122 .h.attr = 0,
123 .sp_mem_base = ARM_SP_IMAGE_BASE,
124 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
125 .sp_image_base = ARM_SP_IMAGE_BASE,
126 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
127 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
128 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
129 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
130 .sp_image_size = ARM_SP_IMAGE_SIZE,
131 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
132 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
133 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
134 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
135 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
136 .num_cpus = PLATFORM_CORE_COUNT,
137 .mp_info = &sp_mp_info[0],
138 };
139
plat_get_secure_partition_mmap(void * cookie)140 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
141 {
142 return plat_arm_secure_partition_mmap;
143 }
144
plat_get_secure_partition_boot_info(void * cookie)145 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info(
146 void *cookie)
147 {
148 return &plat_arm_secure_partition_boot_info;
149 }
150 #endif /* SPM_MM && defined(IMAGE_BL31) */
151
152 #if TRUSTED_BOARD_BOOT
plat_get_mbedtls_heap(void ** heap_addr,size_t * heap_size)153 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
154 {
155 assert(heap_addr != NULL);
156 assert(heap_size != NULL);
157
158 return arm_get_mbedtls_heap(heap_addr, heap_size);
159 }
160 #endif
161
plat_arm_secure_wdt_start(void)162 void plat_arm_secure_wdt_start(void)
163 {
164 sbsa_wdog_start(NRD_CSS_WDOG_BASE, NRD_CSS_WDOG_TIMEOUT);
165 }
166
plat_arm_secure_wdt_stop(void)167 void plat_arm_secure_wdt_stop(void)
168 {
169 sbsa_wdog_stop(NRD_CSS_WDOG_BASE);
170 }
171
172 static sds_region_desc_t nrd_sds_regions[] = {
173 { .base = PLAT_ARM_SDS_MEM_BASE },
174 };
175
plat_sds_get_regions(unsigned int * region_count)176 sds_region_desc_t *plat_sds_get_regions(unsigned int *region_count)
177 {
178 *region_count = ARRAY_SIZE(nrd_sds_regions);
179
180 return nrd_sds_regions;
181 }
182