1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #include <assert.h>
3 #include <console/console.h>
4 #include <delay.h>
5 #include <soc/addressmap.h>
6 #include <soc/mt6391.h>
7 #include <soc/pmic_wrap.h>
8 #include <types.h>
9
10 #if CONFIG(DEBUG_PMIC)
11 #define DEBUG_PMIC(level, x...) printk(level, x)
12 #else
13 #define DEBUG_PMIC(level, x...)
14 #endif
15
mt6391_configure_ca53_voltage(int uv)16 int mt6391_configure_ca53_voltage(int uv)
17 {
18 /* target voltage = 700mv + 6.25mv * buck_val */
19 u16 buck_val = (uv - 700000) / 6250;
20 u16 current_val = pwrap_read_field(PMIC_RG_VCA15_CON12, 0x7f, 0x0);
21
22 assert(buck_val < (1 << 8));
23 pwrap_write_field(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0);
24 pwrap_write_field(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0);
25
26 /* For buck delay, default slew rate is 6.25mv/0.5us */
27 if (buck_val > current_val)
28 return ((buck_val - current_val) / 2);
29 else
30 return 0;
31 }
32
mt6391_configure_vcama(enum ldo_voltage vsel)33 static void mt6391_configure_vcama(enum ldo_voltage vsel)
34 {
35 /* 2'b00: 1.5V
36 * 2'b01: 1.8V
37 * 2'b10: 2.5V
38 * 2'b11: 2.8V
39 */
40 pwrap_write_field(PMIC_RG_ANALDO_CON6, vsel - 2,
41 PMIC_RG_VCAMA_VOSEL_MASK, PMIC_RG_VCAMA_VOSEL_SHIFT);
42 pwrap_write_field(PMIC_RG_ANALDO_CON2, 1,
43 PMIC_RG_VCAMA_EN_MASK, PMIC_RG_VCAMA_EN_SHIFT);
44 }
45
mt6391_configure_ldo(enum ldo_power ldo,enum ldo_voltage vsel)46 void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel)
47 {
48 u16 addr;
49 switch (ldo) {
50 case LDO_VCAMD:
51 assert(vsel != 0);
52 if (vsel == LDO_1P22)
53 vsel = 0;
54 break;
55 case LDO_VGP2:
56 assert(vsel != 1);
57 if (vsel == LDO_1P0)
58 vsel = 1;
59 break;
60 case LDO_VGP5:
61 assert(vsel != 7);
62 if (vsel == LDO_2P0)
63 vsel = 7;
64 break;
65 case LDO_VCAMA:
66 assert(vsel > LDO_1P3 && vsel < LDO_3P0);
67 mt6391_configure_vcama(vsel);
68 return;
69 default:
70 break;
71 }
72 assert(vsel < LDO_NUM_VOLTAGES);
73
74 if (ldo == LDO_VGP6)
75 addr = PMIC_RG_DIGLDO_CON33;
76 else
77 addr = PMIC_RG_DIGLDO_CON19 + ldo * 2;
78
79 pwrap_write_field(addr, vsel, 0x7, 5);
80 pwrap_write_field(PMIC_RG_DIGLDO_CON5 + ldo * 2, 1, 1, 15);
81 }
82
mt6391_enable_reset_when_ap_resets(void)83 void mt6391_enable_reset_when_ap_resets(void)
84 {
85 /* Enable AP watchdog reset */
86 pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 0);
87 }
88
mt6391_init_setting(void)89 static void mt6391_init_setting(void)
90 {
91 /* Enable PMIC RST function (depends on main chip RST function) */
92 /*
93 * state1: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=1, RG_RST_PART_SEL=1
94 * state2: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=0, RG_RST_PART_SEL=1
95 * state3: RG_SYSRSTB_EN = 1, RG_STRUP_MAN_RST_EN=x, RG_RST_PART_SEL=0
96 */
97 pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 1);
98 pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x0, 0x1, 2);
99 pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 4);
100
101 /* Disable AP watchdog reset */
102 pwrap_write_field(PMIC_RG_TOP_RST_MISC, 0x1, 0x1, 0);
103
104 /* Enable CA15 by default for different PMIC behavior */
105 pwrap_write_field(PMIC_RG_VCA15_CON7, 0x1, 0x1, 0);
106 pwrap_write_field(PMIC_RG_VSRMCA15_CON7, 0x1, 0x1, 0);
107 pwrap_write_field(PMIC_RG_VPCA7_CON7, 0x1, 0x1, 0);
108 udelay(200); /* delay for Buck ready */
109
110 /* [3:3]: RG_PWMOC_CK_PDN; For OC protection */
111 pwrap_write_field(PMIC_RG_TOP_CKPDN, 0x0, 0x1, 3);
112 /* [9:9]: RG_SRCVOLT_HW_AUTO_EN; */
113 pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 9);
114 /* [8:8]: RG_OSC_SEL_AUTO; */
115 pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 8);
116 /* [6:6]: RG_SMPS_DIV2_SRC_AUTOFF_DIS; */
117 pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 6);
118 /* [5:5]: RG_SMPS_AUTOFF_DIS; */
119 pwrap_write_field(PMIC_RG_TOP_CKCON1, 0x1, 0x1, 5);
120 /* [7:7]: VDRM_DEG_EN; */
121 pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 7);
122 /* [6:6]: VSRMCA7_DEG_EN; */
123 pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 6);
124 /* [5:5]: VPCA7_DEG_EN; */
125 pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 5);
126 /* [4:4]: VIO18_DEG_EN; */
127 pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 4);
128 /* [3:3]: VGPU_DEG_EN; For OC protection */
129 pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 3);
130 /* [2:2]: VCORE_DEG_EN; */
131 pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 2);
132 /* [1:1]: VSRMCA15_DEG_EN; */
133 pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 1);
134 /* [0:0]: VCA15_DEG_EN; */
135 pwrap_write_field(PMIC_RG_OC_DEG_EN, 0x1, 0x1, 0);
136 /* [11:11]: RG_INT_EN_THR_H; */
137 pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 11);
138 /* [10:10]: RG_INT_EN_THR_L; */
139 pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 10);
140 /* [4:4]: RG_INT_EN_BAT_L; */
141 pwrap_write_field(PMIC_RG_INT_CON0, 0x1, 0x1, 4);
142 /* [11:11]: RG_INT_EN_VGPU; OC protection */
143 pwrap_write_field(PMIC_RG_INT_CON1, 0x1, 0x1, 11);
144 /* [8:8]: RG_INT_EN_VCA15; OC protection */
145 pwrap_write_field(PMIC_RG_INT_CON1, 0x1, 0x1, 8);
146 /* [12:0]: BUCK_RSV; for OC protection */
147 pwrap_write_field(PMIC_RG_BUCK_CON3, 0x600, 0x0FFF, 0);
148 /* [11:10]: QI_VCORE_VSLEEP; sleep mode only (0.7V) */
149 pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 10);
150 /* [7:6]: QI_VSRMCA7_VSLEEP; sleep mode only (0.85V) */
151 pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 6);
152 /* [5:4]: QI_VSRMCA15_VSLEEP; sleep mode only (0.7V) */
153 pwrap_write_field(PMIC_RG_BUCK_CON8, 0x1, 0x3, 4);
154 /* [3:2]: QI_VPCA7_VSLEEP; sleep mode only (0.85V) */
155 pwrap_write_field(PMIC_RG_BUCK_CON8, 0x0, 0x3, 2);
156 /* [1:0]: QI_VCA15_VSLEEP; sleep mode only (0.7V) */
157 pwrap_write_field(PMIC_RG_BUCK_CON8, 0x1, 0x3, 0);
158 /* [13:12]: RG_VCA15_CSL2; for OC protection */
159 pwrap_write_field(PMIC_RG_VCA15_CON1, 0x0, 0x3, 12);
160 /* [11:10]: RG_VCA15_CSL1; for OC protection */
161 pwrap_write_field(PMIC_RG_VCA15_CON1, 0x0, 0x3, 10);
162 /* [15:15]: VCA15_SFCHG_REN; soft change rising enable */
163 pwrap_write_field(PMIC_RG_VCA15_CON8, 0x1, 0x1, 15);
164 /* [14:8]: VCA15_SFCHG_RRATE; soft change rising step=0.5 */
165 pwrap_write_field(PMIC_RG_VCA15_CON8, 0x5, 0x7F, 8);
166 /* [7:7]: VCA15_SFCHG_FEN; soft change falling enable */
167 pwrap_write_field(PMIC_RG_VCA15_CON8, 0x1, 0x1, 7);
168 /* [6:0]: VCA15_SFCHG_FRATE; soft change falling step=2us */
169 pwrap_write_field(PMIC_RG_VCA15_CON8, 0x17, 0x7F, 0);
170 /* [6:0]: VCA15_VOSEL_SLEEP; sleep mode only (0.7V) */
171 pwrap_write_field(PMIC_RG_VCA15_CON11, 0x0, 0x7F, 0);
172 /* [8:8]: VCA15_VSLEEP_EN; set sleep mode reference volt */
173 pwrap_write_field(PMIC_RG_VCA15_CON18, 0x1, 0x1, 8);
174 /* [5:4]: VCA15_VOSEL_TRANS_EN; rising & falling enable */
175 pwrap_write_field(PMIC_RG_VCA15_CON18, 0x3, 0x3, 4);
176 /* [5:5]: VSRMCA15_TRACK_SLEEP_CTRL; */
177 pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 5);
178 /* [5:4]: VSRMCA15_VOSEL_SEL; */
179 pwrap_write_field(PMIC_RG_VSRMCA15_CON6, 0x0, 0x3, 4);
180 /* [15:15]: VSRMCA15_SFCHG_REN; */
181 pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 15);
182 /* [14:8]: VSRMCA15_SFCHG_RRATE; */
183 pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x5, 0x7F, 8);
184 /* [7:7]: VSRMCA15_SFCHG_FEN; */
185 pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x1, 0x1, 7);
186 /* [6:0]: VSRMCA15_SFCHG_FRATE; */
187 pwrap_write_field(PMIC_RG_VSRMCA15_CON8, 0x17, 0x7F, 0);
188 /* [6:0]: VSRMCA15_VOSEL_SLEEP; Sleep mode setting on */
189 pwrap_write_field(PMIC_RG_VSRMCA15_CON11, 0x00, 0x7F, 0);
190 /* [8:8]: VSRMCA15_VSLEEP_EN; set sleep mode reference */
191 pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x1, 0x1, 8);
192 /* [5:4]: VSRMCA15_VOSEL_TRANS_EN; rising & falling e */
193 pwrap_write_field(PMIC_RG_VSRMCA15_CON18, 0x3, 0x3, 4);
194 /* [1:1]: VCORE_VOSEL_CTRL; sleep mode voltage control fo */
195 pwrap_write_field(PMIC_RG_VCORE_CON5, 0x1, 0x1, 1);
196 /* [5:4]: VCORE_VOSEL_SEL; */
197 pwrap_write_field(PMIC_RG_VCORE_CON6, 0x0, 0x3, 4);
198 /* [15:15]: VCORE_SFCHG_REN; */
199 pwrap_write_field(PMIC_RG_VCORE_CON8, 0x1, 0x1, 15);
200 /* [14:8]: VCORE_SFCHG_RRATE; */
201 pwrap_write_field(PMIC_RG_VCORE_CON8, 0x5, 0x7F, 8);
202 /* [6:0]: VCORE_SFCHG_FRATE; */
203 pwrap_write_field(PMIC_RG_VCORE_CON8, 0x17, 0x7F, 0);
204 /* [6:0]: VCORE_VOSEL_SLEEP; Sleep mode setting only (0. */
205 pwrap_write_field(PMIC_RG_VCORE_CON11, 0x0, 0x7F, 0);
206 /* [8:8]: VCORE_VSLEEP_EN; Sleep mode HW control R2R to */
207 pwrap_write_field(PMIC_RG_VCORE_CON18, 0x1, 0x1, 8);
208 /* [5:4]: VCORE_VOSEL_TRANS_EN; Follows MT6320 VCORE set */
209 pwrap_write_field(PMIC_RG_VCORE_CON18, 0x0, 0x3, 4);
210 /* [1:0]: VCORE_TRANSTD; */
211 pwrap_write_field(PMIC_RG_VCORE_CON18, 0x3, 0x3, 0);
212 /* [9:8]: RG_VGPU_CSL; for OC protection */
213 pwrap_write_field(PMIC_RG_VGPU_CON1, 0x1, 0x3, 8);
214 /* [15:15]: VGPU_SFCHG_REN; */
215 pwrap_write_field(PMIC_RG_VGPU_CON8, 0x1, 0x1, 15);
216 /* [14:8]: VGPU_SFCHG_RRATE; */
217 pwrap_write_field(PMIC_RG_VGPU_CON8, 0x5, 0x7F, 8);
218 /* [6:0]: VGPU_SFCHG_FRATE; */
219 pwrap_write_field(PMIC_RG_VGPU_CON8, 0x17, 0x7F, 0);
220 /* [5:4]: VGPU_VOSEL_TRANS_EN; */
221 pwrap_write_field(PMIC_RG_VGPU_CON18, 0x0, 0x3, 4);
222 /* [1:0]: VGPU_TRANSTD; */
223 pwrap_write_field(PMIC_RG_VGPU_CON18, 0x3, 0x3, 0);
224 /* [5:4]: VPCA7_VOSEL_SEL; */
225 pwrap_write_field(PMIC_RG_VPCA7_CON6, 0x0, 0x3, 4);
226 /* [15:15]: VPCA7_SFCHG_REN; */
227 pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 15);
228 /* [14:8]: VPCA7_SFCHG_RRATE; */
229 pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x5, 0x7F, 8);
230 /* [7:7]: VPCA7_SFCHG_FEN; */
231 pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x1, 0x1, 7);
232 /* [6:0]: VPCA7_SFCHG_FRATE; */
233 pwrap_write_field(PMIC_RG_VPCA7_CON8, 0x17, 0x7F, 0);
234 /* [6:0]: VPCA7_VOSEL_SLEEP; */
235 pwrap_write_field(PMIC_RG_VPCA7_CON11, 0x18, 0x7F, 0);
236 /* [8:8]: VPCA7_VSLEEP_EN; */
237 pwrap_write_field(PMIC_RG_VPCA7_CON18, 0x0, 0x1, 8);
238 /* [5:4]: VPCA7_VOSEL_TRANS_EN; */
239 pwrap_write_field(PMIC_RG_VPCA7_CON18, 0x3, 0x3, 4);
240 /* [5:5]: VSRMCA7_TRACK_SLEEP_CTRL; */
241 pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 5);
242 /* [5:4]: VSRMCA7_VOSEL_SEL; */
243 pwrap_write_field(PMIC_RG_VSRMCA7_CON6, 0x0, 0x3, 4);
244 /* [15:15]: VSRMCA7_SFCHG_REN; */
245 pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 15);
246 /* [14:8]: VSRMCA7_SFCHG_RRATE; */
247 pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x5, 0x7F, 8);
248 /* [7:7]: VSRMCA7_SFCHG_FEN; */
249 pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x1, 0x1, 7);
250 /* [6:0]: VSRMCA7_SFCHG_FRATE; */
251 pwrap_write_field(PMIC_RG_VSRMCA7_CON8, 0x17, 0x7F, 0);
252 /* [6:0]: VSRMCA7_VOSEL_SLEEP; */
253 pwrap_write_field(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0);
254 /* [8:8]: VSRMCA7_VSLEEP_EN; */
255 pwrap_write_field(PMIC_RG_VSRMCA7_CON18, 0x0, 0x1, 8);
256 /* [5:4]: VSRMCA7_VOSEL_TRANS_EN; */
257 pwrap_write_field(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4);
258 /* [8:8]: VDRM_VSLEEP_EN; */
259 pwrap_write_field(PMIC_RG_VDRM_CON18, 0x1, 0x1, 8);
260 /* [2:2]: VIBR_THER_SHEN_EN; */
261 pwrap_write_field(PMIC_RG_DIGLDO_CON24, 0x1, 0x1, 2);
262 /* [5:5]: THR_HWPDN_EN; */
263 pwrap_write_field(PMIC_RG_STRUP_CON0, 0x1, 0x1, 5);
264 /* [3:3]: RG_RST_DRVSEL; */
265 pwrap_write_field(PMIC_RG_STRUP_CON2, 0x1, 0x1, 3);
266 /* [2:2]: RG_EN_DRVSEL; */
267 pwrap_write_field(PMIC_RG_STRUP_CON2, 0x1, 0x1, 2);
268 /* [1:1]: PWRBB_DEB_EN; */
269 pwrap_write_field(PMIC_RG_STRUP_CON5, 0x1, 0x1, 1);
270 /* [12:12]: VSRMCA15_PG_H2L_EN; */
271 pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 12);
272 /* [11:11]: VPCA15_PG_H2L_EN; */
273 pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 11);
274 /* [10:10]: VCORE_PG_H2L_EN; */
275 pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 10);
276 /* [9:9]: VSRMCA7_PG_H2L_EN; */
277 pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 9);
278 /* [8:8]: VPCA7_PG_H2L_EN; */
279 pwrap_write_field(PMIC_RG_STRUP_CON7, 0x1, 0x1, 8);
280 /* [1:1]: STRUP_PWROFF_PREOFF_EN; */
281 pwrap_write_field(PMIC_RG_STRUP_CON10, 0x1, 0x1, 1);
282 /* [0:0]: STRUP_PWROFF_SEQ_EN; */
283 pwrap_write_field(PMIC_RG_STRUP_CON10, 0x1, 0x1, 0);
284 /* [15:8]: RG_ADC_TRIM_CH_SEL; */
285 pwrap_write_field(PMIC_RG_AUXADC_CON14, 0xFC, 0xFF, 8);
286 /* [1:1]: FLASH_THER_SHDN_EN; */
287 pwrap_write_field(PMIC_RG_FLASH_CON0, 0x1, 0x1, 1);
288 /* [1:1]: KPLED_THER_SHDN_EN; */
289 pwrap_write_field(PMIC_RG_KPLED_CON0, 0x1, 0x1, 1);
290 /* [14:8]: VSRMCA15_VOSEL_OFFSET; set offset=100mV */
291 pwrap_write_field(PMIC_RG_VSRMCA15_CON19, 0x10, 0x7F, 8);
292 /* [6:0]: VSRMCA15_VOSEL_DELTA; set delta=0mV */
293 pwrap_write_field(PMIC_RG_VSRMCA15_CON19, 0x0, 0x7F, 0);
294 /* [14:8]: VSRMCA15_VOSEL_ON_HB; set HB=1.15V */
295 pwrap_write_field(PMIC_RG_VSRMCA15_CON20, 0x48, 0x7F, 8);
296 /* [6:0]: VSRMCA15_VOSEL_ON_LB; set LB=0.7V */
297 pwrap_write_field(PMIC_RG_VSRMCA15_CON20, 0x0, 0x7F, 0);
298 /* [6:0]: VSRMCA15_VOSEL_SLEEP_LB; set sleep LB=0.7V */
299 pwrap_write_field(PMIC_RG_VSRMCA15_CON21, 0x0, 0x7F, 0);
300 /* [14:8]: VSRMCA7_VOSEL_OFFSET; set offset=25mV */
301 pwrap_write_field(PMIC_RG_VSRMCA7_CON19, 0x4, 0x7F, 8);
302 /* [6:0]: VSRMCA7_VOSEL_DELTA; set delta=0mV */
303 pwrap_write_field(PMIC_RG_VSRMCA7_CON19, 0x0, 0x7F, 0);
304 /* [14:8]: VSRMCA7_VOSEL_ON_HB; set HB=1.275V */
305 pwrap_write_field(PMIC_RG_VSRMCA7_CON20, 0x5C, 0x7F, 8);
306 /* [6:0]: VSRMCA7_VOSEL_ON_LB; set LB=1.05000V */
307 pwrap_write_field(PMIC_RG_VSRMCA7_CON20, 0x38, 0x7F, 0);
308 /* [6:0]: VSRMCA7_VOSEL_SLEEP_LB; set sleep LB=0.85000 */
309 pwrap_write_field(PMIC_RG_VSRMCA7_CON21, 0x18, 0x7F, 0);
310 /* [1:1]: VCA15_VOSEL_CTRL, VCA15_EN_CTRL; DVS HW control */
311 pwrap_write_field(PMIC_RG_VCA15_CON5, 0x3, 0x3, 0);
312 /* [1:1]: VSRMCA15_VOSEL_CTRL, VSRAM15_EN_CTRL; */
313 pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x3, 0x3, 0);
314 /* [1:1]: VPCA7_VOSEL_CTRL; */
315 pwrap_write_field(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1);
316 /* [1:1]: VSRMCA7_VOSEL_CTRL; */
317 pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1);
318 /* [0:0]: VSRMCA7_EN_CTRL; */
319 pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x1, 0x1, 0);
320 /* [4:4]: VCA15_TRACK_ON_CTRL; DVFS tracking enable */
321 pwrap_write_field(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4);
322 /* [4:4]: VSRMCA15_TRACK_ON_CTRL; */
323 pwrap_write_field(PMIC_RG_VSRMCA15_CON5, 0x1, 0x1, 4);
324 /* [4:4]: VPCA7_TRACK_ON_CTRL; */
325 pwrap_write_field(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 4);
326 /* [4:4]: VSRMCA7_TRACK_ON_CTRL; */
327 pwrap_write_field(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 4);
328 /* [15:14]: VGPU OC; */
329 pwrap_write_field(PMIC_RG_OC_CTL1, 0x3, 0x3, 14);
330 /* [3:2]: VCA15 OC; */
331 pwrap_write_field(PMIC_RG_OC_CTL1, 0x3, 0x3, 2);
332
333 /* Set VPCA7 to 1.2V */
334 pwrap_write_field(PMIC_RG_VPCA7_CON9, 0x50, 0x7f, 0x0);
335 pwrap_write_field(PMIC_RG_VPCA7_CON10, 0x50, 0x7f, 0x0);
336 /* Set VSRMCA7 to 1.1V */
337 pwrap_write_field(PMIC_RG_VSRMCA7_CON9, 0x40, 0x7f, 0x0);
338 pwrap_write_field(PMIC_RG_VSRMCA7_CON10, 0x40, 0x7f, 0x0);
339
340 /* Enable VGP6 and set to 3.3V*/
341 pwrap_write_field(PMIC_RG_DIGLDO_CON10, 0x1, 0x1, 15);
342 pwrap_write_field(PMIC_RG_DIGLDO_CON33, 0x07, 0x07, 5);
343
344 /* Set VDRM to 1.21875V */
345 pwrap_write_field(PMIC_RG_VDRM_CON9, 0x43, 0x7F, 0);
346 pwrap_write_field(PMIC_RG_VDRM_CON10, 0x43, 0x7F, 0);
347
348 /* 26M clock amplitude adjust */
349 pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x0, 0x3, 2);
350 pwrap_write_field(PMIC_RG_DCXO_ANALOG_CON1, 0x1, 0x3, 11);
351
352 /* For low power, set VTCXO switch by SRCVOLTEN */
353 pwrap_write_field(PMIC_RG_DIGLDO_CON27, 0x0100, 0x0100, 0);
354 /* [6:5]=0(VTCXO_SRCLK_MODE_SEL) */
355 pwrap_write_field(PMIC_RG_ANALDO_CON0, 0, 0x3, 13);
356 /* [11]=0(VTCXO_ON_CTRL), */
357 pwrap_write_field(PMIC_RG_ANALDO_CON0, 1, 0x1, 11);
358 /* [10]=1(RG_VTCXO_EN), */
359 pwrap_write_field(PMIC_RG_ANALDO_CON0, 1, 0x1, 10);
360 /* [4:3]=1(RG_VTCXOTD_SEL) */
361 pwrap_write_field(PMIC_RG_ANALDO_CON0, 0x3, 0x3, 3);
362 /* For low power, VIO18 set sleep_en to HW mode */
363 pwrap_write_field(PMIC_RG_VIO18_CON18, 0x1, 0x1, 8);
364 }
365
mt6391_default_buck_voltage(void)366 static void mt6391_default_buck_voltage(void)
367 {
368 u16 reg = 0;
369 u16 buck = 0;
370 /*
371 * There are two kinds of PMIC used for MT8173 : MT6397s/MT6391.
372 *
373 * MT6397s: the default voltage of register was not suitable for
374 * MT8173, needs to apply the setting of eFuse.
375 * VPCA15/VSRMCA15/: 1.15V
376 * VCORE: 1.05V
377 *
378 * MT6391: the default voltage of register was matched for MT8173.
379 * VPAC15/VCORE/VGPU: 1.0V
380 * VSRMCA15: 1.0125V
381 */
382 reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_288_303, 0xFFFF, 0);
383
384 if ((reg & 0x01) == 0x01) {
385 /* VCORE */
386 reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_256_271, 0xF, 12);
387 buck = pwrap_read_field(PMIC_RG_VCORE_CON9, 0x7f, 0x0);
388
389 /* VCORE_VOSEL[3:6] => eFuse bit 268-271 */
390 buck = (buck & 0x07) | (reg << 3);
391 pwrap_write_field(PMIC_RG_VCORE_CON9, buck, 0x7f, 0x0);
392 pwrap_write_field(PMIC_RG_VCORE_CON10, buck, 0x7f, 0x0);
393
394 reg = pwrap_read_field(PMIC_RG_EFUSE_DOUT_272_287, 0xFFFF, 0);
395 /* VCA15 */
396 buck = 0;
397 buck = pwrap_read_field(PMIC_RG_VCA15_CON9, 0x7f, 0x0);
398 buck = (buck & 0x07) | ((reg & 0x0F) << 3);
399 pwrap_write_field(PMIC_RG_VCA15_CON9, buck, 0x7f, 0x0);
400 pwrap_write_field(PMIC_RG_VCA15_CON10, buck, 0x7f, 0x0);
401
402 /* VSAMRCA15 */
403 buck = 0;
404 buck = pwrap_read_field(PMIC_RG_VSRMCA15_CON9, 0x7f, 0x0);
405 buck = (buck & 0x07) | ((reg & 0xF0) >> 1);
406 pwrap_write_field(PMIC_RG_VSRMCA15_CON9, buck, 0x7f, 0x0);
407 pwrap_write_field(PMIC_RG_VSRMCA15_CON10, buck, 0x7f, 0x0);
408
409 /* set the power control by register(use original) */
410 pwrap_write_field(PMIC_RG_BUCK_CON3, 0x1, 0x1, 12);
411 }
412 }
413
mt6391_init(void)414 void mt6391_init(void)
415 {
416 if (pwrap_init())
417 die("ERROR - Failed to initialize pmic wrap!");
418 /* pmic initial setting */
419 mt6391_init_setting();
420
421 /* Adjust default BUCK voltage from eFuse */
422 mt6391_default_buck_voltage();
423 }
424
425 /* API of GPIO in PMIC MT6391 */
426 enum {
427 MAX_GPIO_REG_BITS = 16,
428 MAX_GPIO_MODE_PER_REG = 5,
429 GPIO_MODE_BITS = 3,
430 GPIO_PORT_OFFSET = 3,
431 GPIO_SET_OFFSET = 2,
432 GPIO_RST_OFFSET = 4,
433 MAX_MT6391_GPIO = 40
434 };
435
436 enum {
437 MT6391_GPIO_DIRECTION_IN = 0,
438 MT6391_GPIO_DIRECTION_OUT = 1,
439 };
440
441 enum {
442 MT6391_GPIO_MODE = 0,
443 };
444
pos_bit_calc(u32 pin,u16 * pos,u16 * bit)445 static void pos_bit_calc(u32 pin, u16 *pos, u16 *bit)
446 {
447 *pos = (pin / MAX_GPIO_REG_BITS) << GPIO_PORT_OFFSET;
448 *bit = pin % MAX_GPIO_REG_BITS;
449 }
450
pos_bit_calc_mode(u32 pin,u16 * pos,u16 * bit)451 static void pos_bit_calc_mode(u32 pin, u16 *pos, u16 *bit)
452 {
453 *pos = (pin / MAX_GPIO_MODE_PER_REG) << GPIO_PORT_OFFSET;
454 *bit = (pin % MAX_GPIO_MODE_PER_REG) * GPIO_MODE_BITS;
455 }
456
mt6391_gpio_set_dir(u32 pin,u32 dir)457 static s32 mt6391_gpio_set_dir(u32 pin, u32 dir)
458 {
459 u16 pos;
460 u16 bit;
461 u16 reg;
462
463 assert(pin <= MAX_MT6391_GPIO);
464
465 pos_bit_calc(pin, &pos, &bit);
466
467 if (dir == MT6391_GPIO_DIRECTION_IN)
468 reg = MT6391_GPIO_DIR_BASE + pos + GPIO_RST_OFFSET;
469 else
470 reg = MT6391_GPIO_DIR_BASE + pos + GPIO_SET_OFFSET;
471
472 if (pwrap_write(reg, 1L << bit) != 0)
473 return -1;
474
475 return 0;
476 }
477
mt6391_gpio_set_pull(u32 pin,enum mt6391_pull_enable enable,enum mt6391_pull_select select)478 void mt6391_gpio_set_pull(u32 pin, enum mt6391_pull_enable enable,
479 enum mt6391_pull_select select)
480 {
481 u16 pos;
482 u16 bit;
483 u16 en_reg, sel_reg;
484
485 assert(pin <= MAX_MT6391_GPIO);
486
487 pos_bit_calc(pin, &pos, &bit);
488
489 if (enable == MT6391_GPIO_PULL_DISABLE) {
490 en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_RST_OFFSET;
491 } else {
492 en_reg = MT6391_GPIO_PULLEN_BASE + pos + GPIO_SET_OFFSET;
493 sel_reg = (select == MT6391_GPIO_PULL_DOWN) ?
494 (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_RST_OFFSET) :
495 (MT6391_GPIO_PULLSEL_BASE + pos + GPIO_SET_OFFSET);
496 pwrap_write(sel_reg, 1L << bit);
497 }
498 pwrap_write(en_reg, 1L << bit);
499 }
500
mt6391_gpio_get(u32 pin)501 int mt6391_gpio_get(u32 pin)
502 {
503 u16 pos;
504 u16 bit;
505 u16 reg;
506 u16 data;
507
508 assert(pin <= MAX_MT6391_GPIO);
509
510 pos_bit_calc(pin, &pos, &bit);
511
512 reg = MT6391_GPIO_DIN_BASE + pos;
513 pwrap_read(reg, &data);
514
515 return (data & (1L << bit)) ? 1 : 0;
516 }
517
mt6391_gpio_set(u32 pin,int output)518 void mt6391_gpio_set(u32 pin, int output)
519 {
520 u16 pos;
521 u16 bit;
522 u16 reg;
523
524 assert(pin <= MAX_MT6391_GPIO);
525
526 pos_bit_calc(pin, &pos, &bit);
527
528 if (output == 0)
529 reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_RST_OFFSET;
530 else
531 reg = MT6391_GPIO_DOUT_BASE + pos + GPIO_SET_OFFSET;
532
533 pwrap_write(reg, 1L << bit);
534 }
535
mt6391_gpio_set_mode(u32 pin,int mode)536 void mt6391_gpio_set_mode(u32 pin, int mode)
537 {
538 u16 pos;
539 u16 bit;
540 u16 mask = (1L << GPIO_MODE_BITS) - 1;
541
542 assert(pin <= MAX_MT6391_GPIO);
543
544 pos_bit_calc_mode(pin, &pos, &bit);
545 pwrap_write_field(MT6391_GPIO_MODE_BASE + pos, mode, mask, bit);
546 }
547
mt6391_gpio_input_pulldown(u32 gpio)548 void mt6391_gpio_input_pulldown(u32 gpio)
549 {
550 mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE,
551 MT6391_GPIO_PULL_DOWN);
552 mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN);
553 mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
554 }
555
mt6391_gpio_input_pullup(u32 gpio)556 void mt6391_gpio_input_pullup(u32 gpio)
557 {
558 mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_ENABLE,
559 MT6391_GPIO_PULL_UP);
560 mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN);
561 mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
562 }
563
mt6391_gpio_input(u32 gpio)564 void mt6391_gpio_input(u32 gpio)
565 {
566 mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE,
567 MT6391_GPIO_PULL_DOWN);
568 mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_IN);
569 mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
570 }
571
mt6391_gpio_output(u32 gpio,int value)572 void mt6391_gpio_output(u32 gpio, int value)
573 {
574 mt6391_gpio_set_pull(gpio, MT6391_GPIO_PULL_DISABLE,
575 MT6391_GPIO_PULL_DOWN);
576 mt6391_gpio_set(gpio, value);
577 mt6391_gpio_set_dir(gpio, MT6391_GPIO_DIRECTION_OUT);
578 mt6391_gpio_set_mode(gpio, MT6391_GPIO_MODE);
579 }
580