xref: /btstack/port/msp432p401lp-cc256x/ti/devices/msp432p4xx/inc/msp432p401v.h (revision 5fd0122a3e19d95e11e1f3eb8a08a2b2acb2557e) 
1 /******************************************************************************
2 *
3 * Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *
9 *  Redistributions of source code must retain the above copyright
10 *  notice, this list of conditions and the following disclaimer.
11 *
12 *  Redistributions in binary form must reproduce the above copyright
13 *  notice, this list of conditions and the following disclaimer in the
14 *  documentation and/or other materials provided with the
15 *  distribution.
16 *
17 *  Neither the name of Texas Instruments Incorporated nor the names of
18 *  its contributors may be used to endorse or promote products derived
19 *  from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * MSP432P401V Register Definitions
34 *
35 * This file includes CMSIS compliant component and register definitions
36 *
37 * For legacy components the definitions that are compatible with MSP430 code,
38 * are included with msp432p401v_classic.h
39 *
40 * With CMSIS definitions, the register defines have been reformatted:
41 *     ModuleName[ModuleInstance]->RegisterName
42 *
43 * Writing to CMSIS bit fields can be done through register level
44 * or via bitband area access:
45 *  - ADC14->CTL0 |= ADC14_CTL0_ENC;
46 *  - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1;
47 *
48 * File creation date: 2018-01-26
49 *
50 ******************************************************************************/
51 
52 #ifndef __MSP432P401V_H__
53 #define __MSP432P401V_H__
54 
55 /* Use standard integer types with explicit width */
56 #include <stdint.h>
57 
58 #ifdef __cplusplus
59  extern "C" {
60 #endif
61 
62 #define __MSP432_HEADER_VERSION__ 3231
63 
64 /* Remap MSP432 intrinsics to ARM equivalents */
65 #include "msp_compatibility.h"
66 
67 #ifndef __CMSIS_CONFIG__
68 #define __CMSIS_CONFIG__
69 
70 /** @addtogroup MSP432P401V_Definitions MSP432P401V Definitions
71   This file defines all structures and symbols for MSP432P401V:
72     - components and registers
73     - peripheral base address
74     - peripheral ID
75     - Peripheral definitions
76   @{
77 */
78 
79 /******************************************************************************
80 *                Processor and Core Peripherals                               *
81 ******************************************************************************/
82 /** @addtogroup MSP432P401V_CMSIS Device CMSIS Definitions
83   Configuration of the Cortex-M4 Processor and Core Peripherals
84   @{
85 */
86 
87 /******************************************************************************
88 * CMSIS-compatible Interrupt Number Definition                                *
89 ******************************************************************************/
90 typedef enum IRQn
91 {
92   /* Cortex-M4 Processor Exceptions Numbers */
93   NonMaskableInt_IRQn         = -14,    /*  2 Non Maskable Interrupt */
94   HardFault_IRQn              = -13,    /*  3 Hard Fault Interrupt */
95   MemoryManagement_IRQn       = -12,    /*  4 Memory Management Interrupt */
96   BusFault_IRQn               = -11,    /*  5 Bus Fault Interrupt */
97   UsageFault_IRQn             = -10,    /*  6 Usage Fault Interrupt */
98   SVCall_IRQn                 = -5,     /* 11 SV Call Interrupt */
99   DebugMonitor_IRQn           = -4,     /* 12 Debug Monitor Interrupt */
100   PendSV_IRQn                 = -2,     /* 14 Pend SV Interrupt */
101   SysTick_IRQn                = -1,     /* 15 System Tick Interrupt */
102   /*  Peripheral Exceptions Numbers */
103   PSS_IRQn                    = 0,     /* 16 PSS Interrupt             */
104   CS_IRQn                     = 1,     /* 17 CS Interrupt              */
105   PCM_IRQn                    = 2,     /* 18 PCM Interrupt             */
106   WDT_A_IRQn                  = 3,     /* 19 WDT_A Interrupt           */
107   FPU_IRQn                    = 4,     /* 20 FPU Interrupt             */
108   FLCTL_A_IRQn                = 5,     /* 21 Flash Controller Interrupt*/
109   COMP_E0_IRQn                = 6,     /* 22 COMP_E0 Interrupt         */
110   COMP_E1_IRQn                = 7,     /* 23 COMP_E1 Interrupt         */
111   TA0_0_IRQn                  = 8,     /* 24 TA0_0 Interrupt           */
112   TA0_N_IRQn                  = 9,     /* 25 TA0_N Interrupt           */
113   TA1_0_IRQn                  = 10,     /* 26 TA1_0 Interrupt           */
114   TA1_N_IRQn                  = 11,     /* 27 TA1_N Interrupt           */
115   TA2_0_IRQn                  = 12,     /* 28 TA2_0 Interrupt           */
116   TA2_N_IRQn                  = 13,     /* 29 TA2_N Interrupt           */
117   RESERVED0                   = 14,     /* 30 Reserved                  */
118   RESERVED1                   = 15,     /* 31 Reserved                  */
119   EUSCIA0_IRQn                = 16,     /* 32 EUSCIA0 Interrupt         */
120   EUSCIA1_IRQn                = 17,     /* 33 EUSCIA1 Interrupt         */
121   EUSCIA2_IRQn                = 18,     /* 34 EUSCIA2 Interrupt         */
122   RESERVED2                   = 19,     /* 35 Reserved                  */
123   EUSCIB0_IRQn                = 20,     /* 36 EUSCIB0 Interrupt         */
124   RESERVED3                   = 21,     /* 37 Reserved                  */
125   EUSCIB2_IRQn                = 22,     /* 38 EUSCIB2 Interrupt         */
126   EUSCIB3_IRQn                = 23,     /* 39 EUSCIB3 Interrupt         */
127   ADC14_IRQn                  = 24,     /* 40 ADC14 Interrupt           */
128   T32_INT1_IRQn               = 25,     /* 41 T32_INT1 Interrupt        */
129   T32_INT2_IRQn               = 26,     /* 42 T32_INT2 Interrupt        */
130   T32_INTC_IRQn               = 27,     /* 43 T32_INTC Interrupt        */
131   AES256_IRQn                 = 28,     /* 44 AES256 Interrupt          */
132   RTC_C_IRQn                  = 29,     /* 45 RTC_C Interrupt           */
133   DMA_ERR_IRQn                = 30,     /* 46 DMA_ERR Interrupt         */
134   DMA_INT3_IRQn               = 31,     /* 47 DMA_INT3 Interrupt        */
135   DMA_INT2_IRQn               = 32,     /* 48 DMA_INT2 Interrupt        */
136   DMA_INT1_IRQn               = 33,     /* 49 DMA_INT1 Interrupt        */
137   DMA_INT0_IRQn               = 34,     /* 50 DMA_INT0 Interrupt        */
138   PORT1_IRQn                  = 35,     /* 51 Port1 Interrupt           */
139   PORT2_IRQn                  = 36,     /* 52 Port2 Interrupt           */
140   PORT3_IRQn                  = 37,     /* 53 Port3 Interrupt           */
141   PORT4_IRQn                  = 38,     /* 54 Port4 Interrupt           */
142   PORT5_IRQn                  = 39,     /* 55 Port5 Interrupt           */
143   PORT6_IRQn                  = 40      /* 56 Port6 Interrupt           */
144 } IRQn_Type;
145 
146 /******************************************************************************
147 * Processor and Core Peripheral Section                                       *
148 ******************************************************************************/
149 #define __CM4_REV               0x0001    /* Core revision r0p1 */
150 #define __MPU_PRESENT           1         /* MPU present or not */
151 #define __NVIC_PRIO_BITS        3         /* Number of Bits used for Prio Levels */
152 #define __Vendor_SysTickConfig  0         /* Set to 1 if different SysTick Config is used */
153 #define __FPU_PRESENT           1         /* FPU present or not */
154 
155 /******************************************************************************
156 * Available Peripherals                                                       *
157 ******************************************************************************/
158 #define __MCU_HAS_ADC14__                                                        /*!< Module ADC14 is available */
159 #define __MCU_HAS_AES256__                                                       /*!< Module AES256 is available */
160 #define __MCU_HAS_CAPTIO0__                                                      /*!< Module CAPTIO0 is available */
161 #define __MCU_HAS_CAPTIO1__                                                      /*!< Module CAPTIO1 is available */
162 #define __MCU_HAS_COMP_E0__                                                      /*!< Module COMP_E0 is available */
163 #define __MCU_HAS_COMP_E1__                                                      /*!< Module COMP_E1 is available */
164 #define __MCU_HAS_CRC32__                                                        /*!< Module CRC32 is available */
165 #define __MCU_HAS_CS__                                                           /*!< Module CS is available */
166 #define __MCU_HAS_DIO__                                                          /*!< Module DIO is available */
167 #define __MCU_HAS_DMA__                                                          /*!< Module DMA is available */
168 #define __MCU_HAS_EUSCI_A0__                                                     /*!< Module EUSCI_A0 is available */
169 #define __MCU_HAS_EUSCI_A1__                                                     /*!< Module EUSCI_A1 is available */
170 #define __MCU_HAS_EUSCI_A2__                                                     /*!< Module EUSCI_A2 is available */
171 #define __MCU_HAS_EUSCI_B0__                                                     /*!< Module EUSCI_B0 is available */
172 #define __MCU_HAS_EUSCI_B2__                                                     /*!< Module EUSCI_B2 is available */
173 #define __MCU_HAS_EUSCI_B3__                                                     /*!< Module EUSCI_B3 is available */
174 #define __MCU_HAS_FLCTL_A__                                                      /*!< Module FLCTL_A is available */
175 #define __MCU_HAS_FL_BOOTOVER_MAILBOX__                                          /*!< Module FL_BOOTOVER_MAILBOX is available */
176 #define __MCU_HAS_PCM__                                                          /*!< Module PCM is available */
177 #define __MCU_HAS_PMAP__                                                         /*!< Module PMAP is available */
178 #define __MCU_HAS_PSS__                                                          /*!< Module PSS is available */
179 #define __MCU_HAS_REF_A__                                                        /*!< Module REF_A is available */
180 #define __MCU_HAS_RSTCTL__                                                       /*!< Module RSTCTL is available */
181 #define __MCU_HAS_RTC_C__                                                        /*!< Module RTC_C is available */
182 #define __MCU_HAS_SYSCTL_A__                                                     /*!< Module SYSCTL_A is available */
183 #define __MCU_HAS_TIMER32__                                                      /*!< Module TIMER32 is available */
184 #define __MCU_HAS_TIMER_A0__                                                     /*!< Module TIMER_A0 is available */
185 #define __MCU_HAS_TIMER_A1__                                                     /*!< Module TIMER_A1 is available */
186 #define __MCU_HAS_TIMER_A2__                                                     /*!< Module TIMER_A2 is available */
187 #define __MCU_HAS_TLV__                                                          /*!< Module TLV is available */
188 #define __MCU_HAS_WDT_A__                                                        /*!< Module WDT_A is available */
189 
190 /* Definitions to show that specific ports are available */
191 
192 #define __MSP432_HAS_PORTA_R__
193 #define __MSP432_HAS_PORTB_R__
194 #define __MSP432_HAS_PORTC_R__
195 #define __MSP432_HAS_PORTD_R__
196 #define __MSP432_HAS_PORTE_R__
197 #define __MSP432_HAS_PORTJ_R__
198 
199 #define __MSP432_HAS_PORT1_R__
200 #define __MSP432_HAS_PORT2_R__
201 #define __MSP432_HAS_PORT3_R__
202 #define __MSP432_HAS_PORT4_R__
203 #define __MSP432_HAS_PORT5_R__
204 #define __MSP432_HAS_PORT6_R__
205 #define __MSP432_HAS_PORT7_R__
206 #define __MSP432_HAS_PORT8_R__
207 #define __MSP432_HAS_PORT9_R__
208 #define __MSP432_HAS_PORT10_R__
209 
210 
211 /*@}*/ /* end of group MSP432P401V_CMSIS */
212 
213 /* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */
214 #ifdef __TI_ARM__
215 /* disable the TI ULP advisor check for the core header file definitions */
216 #pragma diag_push
217 #pragma CHECK_ULP("none")
218 #include "core_cm4.h"
219 #pragma diag_pop
220 #else
221 #include "core_cm4.h"
222 #endif
223 
224 /* System Header */
225 #include "system_msp432p401v.h"
226 
227 /******************************************************************************
228 * Definition of standard bits                                                 *
229 ******************************************************************************/
230 #define BIT0                                     (uint16_t)(0x0001)
231 #define BIT1                                     (uint16_t)(0x0002)
232 #define BIT2                                     (uint16_t)(0x0004)
233 #define BIT3                                     (uint16_t)(0x0008)
234 #define BIT4                                     (uint16_t)(0x0010)
235 #define BIT5                                     (uint16_t)(0x0020)
236 #define BIT6                                     (uint16_t)(0x0040)
237 #define BIT7                                     (uint16_t)(0x0080)
238 #define BIT8                                     (uint16_t)(0x0100)
239 #define BIT9                                     (uint16_t)(0x0200)
240 #define BITA                                     (uint16_t)(0x0400)
241 #define BITB                                     (uint16_t)(0x0800)
242 #define BITC                                     (uint16_t)(0x1000)
243 #define BITD                                     (uint16_t)(0x2000)
244 #define BITE                                     (uint16_t)(0x4000)
245 #define BITF                                     (uint16_t)(0x8000)
246 #define BIT(x)                                 ((uint16_t)1 << (x))
247 
248 /******************************************************************************
249 * Device and peripheral memory map                                            *
250 ******************************************************************************/
251 /** @addtogroup MSP432P401V_MemoryMap MSP432P401V Memory Mapping
252   @{
253 */
254 
255 #define FLASH_BASE                               ((uint32_t)0x00000000)          /*!< Main Flash memory start address */
256 #define SRAM_BASE                                ((uint32_t)0x20000000)          /*!< SRAM memory start address */
257 #define PERIPH_BASE                              ((uint32_t)0x40000000)          /*!< Peripherals start address */
258 #define PERIPH_BASE2                             ((uint32_t)0xE0000000)          /*!< Peripherals start address */
259 
260 #define ADC14_BASE                            (PERIPH_BASE +0x00012000)          /*!< Base address of module ADC14 registers */
261 #define AES256_BASE                           (PERIPH_BASE +0x00003C00)          /*!< Base address of module AES256 registers */
262 #define CAPTIO0_BASE                          (PERIPH_BASE +0x00005400)          /*!< Base address of module CAPTIO0 registers */
263 #define CAPTIO1_BASE                          (PERIPH_BASE +0x00005800)          /*!< Base address of module CAPTIO1 registers */
264 #define COMP_E0_BASE                          (PERIPH_BASE +0x00003400)          /*!< Base address of module COMP_E0 registers */
265 #define COMP_E1_BASE                          (PERIPH_BASE +0x00003800)          /*!< Base address of module COMP_E1 registers */
266 #define CRC32_BASE                            (PERIPH_BASE +0x00004000)          /*!< Base address of module CRC32 registers */
267 #define CS_BASE                               (PERIPH_BASE +0x00010400)          /*!< Base address of module CS registers */
268 #define DIO_BASE                              (PERIPH_BASE +0x00004C00)          /*!< Base address of module DIO registers */
269 #define DMA_BASE                              (PERIPH_BASE +0x0000E000)          /*!< Base address of module DMA registers */
270 #define EUSCI_A0_BASE                         (PERIPH_BASE +0x00001000)          /*!< Base address of module EUSCI_A0 registers */
271 #define EUSCI_A0_SPI_BASE                     (PERIPH_BASE +0x00001000)          /*!< Base address of module EUSCI_A0 registers */
272 #define EUSCI_A1_BASE                         (PERIPH_BASE +0x00001400)          /*!< Base address of module EUSCI_A1 registers */
273 #define EUSCI_A1_SPI_BASE                     (PERIPH_BASE +0x00001400)          /*!< Base address of module EUSCI_A1 registers */
274 #define EUSCI_A2_BASE                         (PERIPH_BASE +0x00001800)          /*!< Base address of module EUSCI_A2 registers */
275 #define EUSCI_A2_SPI_BASE                     (PERIPH_BASE +0x00001800)          /*!< Base address of module EUSCI_A2 registers */
276 #define EUSCI_B0_BASE                         (PERIPH_BASE +0x00002000)          /*!< Base address of module EUSCI_B0 registers */
277 #define EUSCI_B0_SPI_BASE                     (PERIPH_BASE +0x00002000)          /*!< Base address of module EUSCI_B0 registers */
278 #define EUSCI_B2_BASE                         (PERIPH_BASE +0x00002800)          /*!< Base address of module EUSCI_B2 registers */
279 #define EUSCI_B2_SPI_BASE                     (PERIPH_BASE +0x00002800)          /*!< Base address of module EUSCI_B2 registers */
280 #define EUSCI_B3_BASE                         (PERIPH_BASE +0x00002C00)          /*!< Base address of module EUSCI_B3 registers */
281 #define EUSCI_B3_SPI_BASE                     (PERIPH_BASE +0x00002C00)          /*!< Base address of module EUSCI_B3 registers */
282 #define FLCTL_A_BASE                          (PERIPH_BASE +0x00011000)          /*!< Base address of module FLCTL_A registers */
283 #define FL_BOOTOVER_MAILBOX_BASE                 ((uint32_t)0x00200000)          /*!< Base address of module FL_BOOTOVER_MAILBOX registers */
284 #define PCM_BASE                              (PERIPH_BASE +0x00010000)          /*!< Base address of module PCM registers */
285 #define PMAP_BASE                             (PERIPH_BASE +0x00005000)          /*!< Base address of module PMAP registers */
286 #define PSS_BASE                              (PERIPH_BASE +0x00010800)          /*!< Base address of module PSS registers */
287 #define REF_A_BASE                            (PERIPH_BASE +0x00003000)          /*!< Base address of module REF_A registers */
288 #define RSTCTL_BASE                           (PERIPH_BASE2+0x00042000)          /*!< Base address of module RSTCTL registers */
289 #define RTC_C_BASE                            (PERIPH_BASE +0x00004400)          /*!< Base address of module RTC_C registers */
290 #define RTC_C_BCD_BASE                        (PERIPH_BASE +0x00004400)          /*!< Base address of module RTC_C registers */
291 #define SYSCTL_A_BASE                         (PERIPH_BASE2+0x00043000)          /*!< Base address of module SYSCTL_A registers */
292 #define TIMER32_BASE                          (PERIPH_BASE +0x0000C000)          /*!< Base address of module TIMER32 registers */
293 #define TIMER_A0_BASE                         (PERIPH_BASE +0x00000000)          /*!< Base address of module TIMER_A0 registers */
294 #define TIMER_A1_BASE                         (PERIPH_BASE +0x00000400)          /*!< Base address of module TIMER_A1 registers */
295 #define TIMER_A2_BASE                         (PERIPH_BASE +0x00000800)          /*!< Base address of module TIMER_A2 registers */
296 #define TLV_BASE                                 ((uint32_t)0x00201000)          /*!< Base address of module TLV registers */
297 #define WDT_A_BASE                            (PERIPH_BASE +0x00004800)          /*!< Base address of module WDT_A registers */
298 
299 
300 /*@}*/ /* end of group MSP432P401V_MemoryMap */
301 
302 /******************************************************************************
303 * Definitions for bit band access                                             *
304 ******************************************************************************/
305 #define BITBAND_SRAM_BASE                     ((uint32_t)(0x22000000))
306 #define BITBAND_PERI_BASE                     ((uint32_t)(0x42000000))
307 
308 /* SRAM allows 32 bit bit band access */
309 #define BITBAND_SRAM(x, b)  (*((__IO uint32_t *) (BITBAND_SRAM_BASE +  (((uint32_t)(volatile const uint32_t *)&(x)) - SRAM_BASE  )*32 + (b)*4)))
310 /* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */
311 #define BITBAND_PERI(x, b)  (*((__IO  uint8_t *) (BITBAND_PERI_BASE +  (((uint32_t)(volatile const uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4)))
312 
313 /******************************************************************************
314 * Peripheral register definitions                                             *
315 ******************************************************************************/
316 /** @addtogroup MSP432P401V_Peripherals MSP432P401V Peripherals
317   MSP432P401V Device Specific Peripheral registers structures
318   @{
319 */
320 
321 /* -------  Start of section using anonymous unions and disabling warnings  ------- */
322 #if defined (__CC_ARM)
323   #pragma push
324   #pragma anon_unions
325 #elif defined (__ICCARM__)
326   #pragma language=extended
327 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
328   #pragma clang diagnostic push
329   #pragma clang diagnostic ignored "-Wc11-extensions"
330 #elif defined (__GNUC__)
331   /* anonymous unions are enabled by default */
332 #elif defined (__TI_ARM__)
333   /* anonymous unions are enabled by default */
334 #else
335   #warning Not supported compiler type
336 #endif
337 
338 
339 /******************************************************************************
340 * ADC14 Registers
341 ******************************************************************************/
342 /** @addtogroup ADC14 MSP432P401V (ADC14)
343   @{
344 */
345 typedef struct {
346   __IO uint32_t CTL0;                                                            /*!< Control 0 Register */
347   __IO uint32_t CTL1;                                                            /*!< Control 1 Register */
348   __IO uint32_t LO0;                                                             /*!< Window Comparator Low Threshold 0 Register */
349   __IO uint32_t HI0;                                                             /*!< Window Comparator High Threshold 0 Register */
350   __IO uint32_t LO1;                                                             /*!< Window Comparator Low Threshold 1 Register */
351   __IO uint32_t HI1;                                                             /*!< Window Comparator High Threshold 1 Register */
352   __IO uint32_t MCTL[32];                                                        /*!< Conversion Memory Control Register */
353   __IO uint32_t MEM[32];                                                         /*!< Conversion Memory Register */
354        uint32_t RESERVED0[9];
355   __IO uint32_t IER0;                                                            /*!< Interrupt Enable 0 Register */
356   __IO uint32_t IER1;                                                            /*!< Interrupt Enable 1 Register */
357   __I  uint32_t IFGR0;                                                           /*!< Interrupt Flag 0 Register */
358   __I  uint32_t IFGR1;                                                           /*!< Interrupt Flag 1 Register */
359   __O  uint32_t CLRIFGR0;                                                        /*!< Clear Interrupt Flag 0 Register */
360   __IO uint32_t CLRIFGR1;                                                        /*!< Clear Interrupt Flag 1 Register */
361   __IO uint32_t IV;                                                              /*!< Interrupt Vector Register */
362 } ADC14_Type;
363 
364 /*@}*/ /* end of group ADC14 */
365 
366 
367 /******************************************************************************
368 * AES256 Registers
369 ******************************************************************************/
370 /** @addtogroup AES256 MSP432P401V (AES256)
371   @{
372 */
373 typedef struct {
374   __IO uint16_t CTL0;                                                            /*!< AES Accelerator Control Register 0 */
375   __IO uint16_t CTL1;                                                            /*!< AES Accelerator Control Register 1 */
376   __IO uint16_t STAT;                                                            /*!< AES Accelerator Status Register */
377   __O  uint16_t KEY;                                                             /*!< AES Accelerator Key Register */
378   __O  uint16_t DIN;                                                             /*!< AES Accelerator Data In Register */
379   __O  uint16_t DOUT;                                                            /*!< AES Accelerator Data Out Register */
380   __O  uint16_t XDIN;                                                            /*!< AES Accelerator XORed Data In Register */
381   __O  uint16_t XIN;                                                             /*!< AES Accelerator XORed Data In Register */
382 } AES256_Type;
383 
384 /*@}*/ /* end of group AES256 */
385 
386 
387 /******************************************************************************
388 * CAPTIO Registers
389 ******************************************************************************/
390 /** @addtogroup CAPTIO MSP432P401V (CAPTIO)
391   @{
392 */
393 typedef struct {
394        uint16_t RESERVED0[7];
395   __IO uint16_t CTL;                                                             /*!< Capacitive Touch IO x Control Register */
396 } CAPTIO_Type;
397 
398 /*@}*/ /* end of group CAPTIO */
399 
400 
401 /******************************************************************************
402 * COMP_E Registers
403 ******************************************************************************/
404 /** @addtogroup COMP_E MSP432P401V (COMP_E)
405   @{
406 */
407 typedef struct {
408   __IO uint16_t CTL0;                                                            /*!< Comparator Control Register 0 */
409   __IO uint16_t CTL1;                                                            /*!< Comparator Control Register 1 */
410   __IO uint16_t CTL2;                                                            /*!< Comparator Control Register 2 */
411   __IO uint16_t CTL3;                                                            /*!< Comparator Control Register 3 */
412        uint16_t RESERVED0[2];
413   __IO uint16_t INT;                                                             /*!< Comparator Interrupt Control Register */
414   __I  uint16_t IV;                                                              /*!< Comparator Interrupt Vector Word Register */
415 } COMP_E_Type;
416 
417 /*@}*/ /* end of group COMP_E */
418 
419 
420 /******************************************************************************
421 * CRC32 Registers
422 ******************************************************************************/
423 /** @addtogroup CRC32 MSP432P401V (CRC32)
424   @{
425 */
426 typedef struct {
427   __IO uint16_t DI32;                                                            /*!< Data Input for CRC32 Signature Computation */
428        uint16_t RESERVED0;
429   __IO uint16_t DIRB32;                                                          /*!< Data In Reverse for CRC32 Computation */
430        uint16_t RESERVED1;
431   __IO uint16_t INIRES32_LO;                                                     /*!< CRC32 Initialization and Result, lower 16 bits */
432   __IO uint16_t INIRES32_HI;                                                     /*!< CRC32 Initialization and Result, upper 16 bits */
433   __IO uint16_t RESR32_LO;                                                       /*!< CRC32 Result Reverse, lower 16 bits */
434   __IO uint16_t RESR32_HI;                                                       /*!< CRC32 Result Reverse, Upper 16 bits */
435   __IO uint16_t DI16;                                                            /*!< Data Input for CRC16 computation */
436        uint16_t RESERVED2;
437   __IO uint16_t DIRB16;                                                          /*!< CRC16 Data In Reverse */
438        uint16_t RESERVED3;
439   __IO uint16_t INIRES16;                                                        /*!< CRC16 Initialization and Result register */
440        uint16_t RESERVED4[2];
441   __IO uint16_t RESR16;                                                          /*!< CRC16 Result Reverse */
442 } CRC32_Type;
443 
444 /*@}*/ /* end of group CRC32 */
445 
446 
447 /******************************************************************************
448 * CS Registers
449 ******************************************************************************/
450 /** @addtogroup CS MSP432P401V (CS)
451   @{
452 */
453 typedef struct {
454   __IO uint32_t KEY;                                                             /*!< Key Register */
455   __IO uint32_t CTL0;                                                            /*!< Control 0 Register */
456   __IO uint32_t CTL1;                                                            /*!< Control 1 Register */
457   __IO uint32_t CTL2;                                                            /*!< Control 2 Register */
458   __IO uint32_t CTL3;                                                            /*!< Control 3 Register */
459        uint32_t RESERVED0[7];
460   __IO uint32_t CLKEN;                                                           /*!< Clock Enable Register */
461   __I  uint32_t STAT;                                                            /*!< Status Register */
462        uint32_t RESERVED1[2];
463   __IO uint32_t IE;                                                              /*!< Interrupt Enable Register */
464        uint32_t RESERVED2;
465   __I  uint32_t IFG;                                                             /*!< Interrupt Flag Register */
466        uint32_t RESERVED3;
467   __O  uint32_t CLRIFG;                                                          /*!< Clear Interrupt Flag Register */
468        uint32_t RESERVED4;
469   __O  uint32_t SETIFG;                                                          /*!< Set Interrupt Flag Register */
470        uint32_t RESERVED5;
471   __IO uint32_t DCOERCAL0;                                                       /*!< DCO External Resistor Cailbration 0 Register */
472   __IO uint32_t DCOERCAL1;                                                       /*!< DCO External Resistor Calibration 1 Register */
473 } CS_Type;
474 
475 /*@}*/ /* end of group CS */
476 
477 
478 /******************************************************************************
479 * DIO Registers
480 ******************************************************************************/
481 /** @addtogroup DIO MSP432P4111 (DIO)
482   @{
483 */
484 typedef struct {
485   union {
486     __I uint16_t IN;                                                              /*!< Port Pair Input */
487     struct {
488       __I uint8_t IN_L;                                                           /*!< Low Port Input */
489       __I uint8_t IN_H;                                                           /*!< High Port Input */
490     };
491   };
492   union {
493     __IO uint16_t OUT;                                                            /*!< Port Pair Output */
494     struct {
495       __IO uint8_t OUT_L;                                                         /*!< Low Port Output */
496       __IO uint8_t OUT_H;                                                         /*!< High Port Output */
497     };
498   };
499   union {
500     __IO uint16_t DIR;                                                            /*!< Port Pair Direction */
501     struct {
502       __IO uint8_t DIR_L;                                                         /*!< Low Port Direction */
503       __IO uint8_t DIR_H;                                                         /*!< High Port Direction */
504     };
505   };
506   union {
507     __IO uint16_t REN;                                                            /*!< Port Pair Resistor Enable */
508     struct {
509       __IO uint8_t REN_L;                                                         /*!< Low Port Resistor Enable */
510       __IO uint8_t REN_H;                                                         /*!< High Port Resistor Enable */
511     };
512   };
513   union {
514     __IO uint16_t DS;                                                             /*!< Port Pair Drive Strength */
515     struct {
516       __IO uint8_t DS_L;                                                          /*!< Low Port Drive Strength */
517       __IO uint8_t DS_H;                                                          /*!< High Port Drive Strength */
518     };
519   };
520   union {
521     __IO uint16_t SEL0;                                                           /*!< Port Pair Select 0 */
522     struct {
523       __IO uint8_t SEL0_L;                                                        /*!< Low Port Select 0 */
524       __IO uint8_t SEL0_H;                                                        /*!< High Port Select 0 */
525     };
526   };
527   union {
528     __IO uint16_t SEL1;                                                           /*!< Port Pair Select 1 */
529     struct {
530       __IO uint8_t SEL1_L;                                                        /*!< Low Port Select 1 */
531       __IO uint8_t SEL1_H;                                                        /*!< High Port Select 1 */
532     };
533   };
534   __I  uint16_t IV_L;                                                             /*!< Low Port Interrupt Vector Value */
535   uint16_t  RESERVED0[3];
536   union {
537     __IO uint16_t SELC;                                                           /*!< Port Pair Complement Select */
538     struct {
539       __IO uint8_t SELC_L;                                                        /*!< Low Port Complement Select */
540       __IO uint8_t SELC_H;                                                        /*!< High Port Complement Select */
541     };
542   };
543   union {
544     __IO uint16_t IES;                                                            /*!< Port Pair Interrupt Edge Select */
545     struct {
546       __IO uint8_t IES_L;                                                         /*!< Low Port Interrupt Edge Select */
547       __IO uint8_t IES_H;                                                         /*!< High Port Interrupt Edge Select */
548     };
549   };
550   union {
551     __IO uint16_t IE;                                                             /*!< Port Pair Interrupt Enable */
552     struct {
553       __IO uint8_t IE_L;                                                          /*!< Low Port Interrupt Enable */
554       __IO uint8_t IE_H;                                                          /*!< High Port Interrupt Enable */
555     };
556   };
557   union {
558     __IO uint16_t IFG;                                                            /*!< Port Pair Interrupt Flag */
559     struct {
560       __IO uint8_t IFG_L;                                                         /*!< Low Port Interrupt Flag */
561       __IO uint8_t IFG_H;                                                         /*!< High Port Interrupt Flag */
562     };
563   };
564   __I uint16_t IV_H;                                                              /*!< High Port Interrupt Vector Value */
565 } DIO_PORT_Interruptable_Type;
566 
567 typedef struct {
568   union {
569     __I uint16_t IN;                                                              /*!< Port Pair Input */
570     struct {
571       __I uint8_t IN_L;                                                           /*!< Low Port Input */
572       __I uint8_t IN_H;                                                           /*!< High Port Input */
573     };
574   };
575   union {
576     __IO uint16_t OUT;                                                            /*!< Port Pair Output */
577     struct {
578       __IO uint8_t OUT_L;                                                         /*!< Low Port Output */
579       __IO uint8_t OUT_H;                                                         /*!< High Port Output */
580     };
581   };
582   union {
583     __IO uint16_t DIR;                                                            /*!< Port Pair Direction */
584     struct {
585       __IO uint8_t DIR_L;                                                         /*!< Low Port Direction */
586       __IO uint8_t DIR_H;                                                         /*!< High Port Direction */
587     };
588   };
589   union {
590     __IO uint16_t REN;                                                            /*!< Port Pair Resistor Enable */
591     struct {
592       __IO uint8_t REN_L;                                                         /*!< Low Port Resistor Enable */
593       __IO uint8_t REN_H;                                                         /*!< High Port Resistor Enable */
594     };
595   };
596   union {
597     __IO uint16_t DS;                                                             /*!< Port Pair Drive Strength */
598     struct {
599       __IO uint8_t DS_L;                                                          /*!< Low Port Drive Strength */
600       __IO uint8_t DS_H;                                                          /*!< High Port Drive Strength */
601     };
602   };
603   union {
604     __IO uint16_t SEL0;                                                           /*!< Port Pair Select 0 */
605     struct {
606       __IO uint8_t SEL0_L;                                                        /*!< Low Port Select 0 */
607       __IO uint8_t SEL0_H;                                                        /*!< High Port Select 0 */
608     };
609   };
610   union {
611     __IO uint16_t SEL1;                                                           /*!< Port Pair Select 1 */
612     struct {
613       __IO uint8_t SEL1_L;                                                        /*!< Low Port Select 1 */
614       __IO uint8_t SEL1_H;                                                        /*!< High Port Select 1 */
615     };
616   };
617   uint16_t  RESERVED0[4];
618   union {
619     __IO uint16_t SELC;                                                           /*!< Port Pair Complement Select */
620     struct {
621       __IO uint8_t SELC_L;                                                        /*!< Low Port Complement Select */
622       __IO uint8_t SELC_H;                                                        /*!< High Port Complement Select */
623     };
624   };
625 } DIO_PORT_Not_Interruptable_Type;
626 
627 
628 typedef struct {
629   __I uint8_t IN;                                                                 /*!< Port Input */
630   uint8_t RESERVED0;
631   __IO uint8_t OUT;                                                               /*!< Port Output */
632   uint8_t RESERVED1;
633   __IO uint8_t DIR;                                                               /*!< Port Direction */
634   uint8_t RESERVED2;
635   __IO uint8_t REN;                                                               /*!< Port Resistor Enable */
636   uint8_t RESERVED3;
637   __IO uint8_t DS;                                                                /*!< Port Drive Strength */
638   uint8_t RESERVED4;
639   __IO uint8_t SEL0;                                                              /*!< Port Select 0 */
640   uint8_t RESERVED5;
641   __IO uint8_t SEL1;                                                              /*!< Port Select 1 */
642   uint8_t RESERVED6;
643   __I  uint16_t IV;                                                               /*!< Port Interrupt Vector Value */
644   uint8_t RESERVED7[6];
645   __IO uint8_t SELC;                                                              /*!< Port Complement Select */
646   uint8_t RESERVED8;
647   __IO uint8_t IES;                                                               /*!< Port Interrupt Edge Select */
648   uint8_t RESERVED9;
649   __IO uint8_t IE;                                                                /*!< Port Interrupt Enable */
650   uint8_t RESERVED10;
651   __IO uint8_t IFG;                                                               /*!< Port Interrupt Flag */
652   uint8_t RESERVED11;
653 } DIO_PORT_Odd_Interruptable_Type;
654 
655 typedef struct {
656   uint8_t RESERVED0;
657   __I uint8_t IN;                                                                 /*!< Port Input */
658   uint8_t RESERVED1;
659   __IO uint8_t OUT;                                                               /*!< Port Output */
660   uint8_t RESERVED2;
661   __IO uint8_t DIR;                                                               /*!< Port Direction */
662   uint8_t RESERVED3;
663   __IO uint8_t REN;                                                               /*!< Port Resistor Enable */
664   uint8_t RESERVED4;
665   __IO uint8_t DS;                                                                /*!< Port Drive Strength */
666   uint8_t RESERVED5;
667   __IO uint8_t SEL0;                                                              /*!< Port Select 0 */
668   uint8_t RESERVED6;
669   __IO uint8_t SEL1;                                                              /*!< Port Select 1 */
670   uint8_t RESERVED7[9];
671   __IO uint8_t SELC;                                                              /*!< Port Complement Select */
672   uint8_t RESERVED8;
673   __IO uint8_t IES;                                                               /*!< Port Interrupt Edge Select */
674   uint8_t RESERVED9;
675   __IO uint8_t IE;                                                                /*!< Port Interrupt Enable */
676   uint8_t RESERVED10;
677   __IO uint8_t IFG;                                                               /*!< Port Interrupt Flag */
678   __I uint16_t IV;                                                                /*!< Port Interrupt Vector Value */
679 } DIO_PORT_Even_Interruptable_Type;
680 
681 /*@}*/ /* end of group MSP432P4111_DIO */
682 
683 
684 /******************************************************************************
685 * DMA Registers
686 ******************************************************************************/
687 /** @addtogroup DMA MSP432P4111 (DMA)
688   @{
689 */
690 typedef struct {
691   __I  uint32_t DEVICE_CFG;                                                      /*!< Device Configuration Status */
692   __IO uint32_t SW_CHTRIG;                                                       /*!< Software Channel Trigger Register */
693        uint32_t RESERVED0[2];
694   __IO uint32_t CH_SRCCFG[32];                                                   /*!< Channel n Source Configuration Register */
695        uint32_t RESERVED1[28];
696   __IO uint32_t INT1_SRCCFG;                                                     /*!< Interrupt 1 Source Channel Configuration */
697   __IO uint32_t INT2_SRCCFG;                                                     /*!< Interrupt 2 Source Channel Configuration Register */
698   __IO uint32_t INT3_SRCCFG;                                                     /*!< Interrupt 3 Source Channel Configuration Register */
699        uint32_t RESERVED2;
700   __I  uint32_t INT0_SRCFLG;                                                     /*!< Interrupt 0 Source Channel Flag Register */
701   __O  uint32_t INT0_CLRFLG;                                                     /*!< Interrupt 0 Source Channel Clear Flag Register */
702 } DMA_Channel_Type;
703 
704 typedef struct {
705   __I  uint32_t STAT;                                                            /*!< Status Register */
706   __O  uint32_t CFG;                                                             /*!< Configuration Register */
707   __IO uint32_t CTLBASE;                                                         /*!< Channel Control Data Base Pointer Register */
708   __I  uint32_t ALTBASE;                                                         /*!< Channel Alternate Control Data Base Pointer Register */
709   __I  uint32_t WAITSTAT;                                                        /*!< Channel Wait on Request Status Register */
710   __O  uint32_t SWREQ;                                                           /*!< Channel Software Request Register */
711   __IO uint32_t USEBURSTSET;                                                     /*!< Channel Useburst Set Register */
712   __O  uint32_t USEBURSTCLR;                                                     /*!< Channel Useburst Clear Register */
713   __IO uint32_t REQMASKSET;                                                      /*!< Channel Request Mask Set Register */
714   __O  uint32_t REQMASKCLR;                                                      /*!< Channel Request Mask Clear Register */
715   __IO uint32_t ENASET;                                                          /*!< Channel Enable Set Register */
716   __O  uint32_t ENACLR;                                                          /*!< Channel Enable Clear Register */
717   __IO uint32_t ALTSET;                                                          /*!< Channel Primary-Alternate Set Register */
718   __O  uint32_t ALTCLR;                                                          /*!< Channel Primary-Alternate Clear Register */
719   __IO uint32_t PRIOSET;                                                         /*!< Channel Priority Set Register */
720   __O  uint32_t PRIOCLR;                                                         /*!< Channel Priority Clear Register */
721        uint32_t RESERVED4[3];
722   __IO uint32_t ERRCLR;                                                          /*!< Bus Error Clear Register */
723 } DMA_Control_Type;
724 
725 /*@}*/ /* end of group DMA */
726 
727 
728 /******************************************************************************
729 * EUSCI_A Registers
730 ******************************************************************************/
731 /** @addtogroup EUSCI_A MSP432P401V (EUSCI_A)
732   @{
733 */
734 typedef struct {
735   __IO uint16_t CTLW0;                                                           /*!< eUSCI_Ax Control Word Register 0 */
736   __IO uint16_t CTLW1;                                                           /*!< eUSCI_Ax Control Word Register 1 */
737        uint16_t RESERVED0;
738   __IO uint16_t BRW;                                                             /*!< eUSCI_Ax Baud Rate Control Word Register */
739   __IO uint16_t MCTLW;                                                           /*!< eUSCI_Ax Modulation Control Word Register */
740   __IO uint16_t STATW;                                                           /*!< eUSCI_Ax Status Register */
741   __I  uint16_t RXBUF;                                                           /*!< eUSCI_Ax Receive Buffer Register */
742   __IO uint16_t TXBUF;                                                           /*!< eUSCI_Ax Transmit Buffer Register */
743   __IO uint16_t ABCTL;                                                           /*!< eUSCI_Ax Auto Baud Rate Control Register */
744   __IO uint16_t IRCTL;                                                           /*!< eUSCI_Ax IrDA Control Word Register */
745        uint16_t RESERVED1[3];
746   __IO uint16_t IE;                                                              /*!< eUSCI_Ax Interrupt Enable Register */
747   __IO uint16_t IFG;                                                             /*!< eUSCI_Ax Interrupt Flag Register */
748   __I  uint16_t IV;                                                              /*!< eUSCI_Ax Interrupt Vector Register */
749 } EUSCI_A_Type;
750 
751 /*@}*/ /* end of group EUSCI_A */
752 
753 /** @addtogroup EUSCI_A_SPI MSP432P401V (EUSCI_A_SPI)
754   @{
755 */
756 typedef struct {
757   __IO uint16_t CTLW0;                                                           /*!< eUSCI_Ax Control Word Register 0 */
758        uint16_t RESERVED0[2];
759   __IO uint16_t BRW;                                                             /*!< eUSCI_Ax Bit Rate Control Register 1 */
760        uint16_t RESERVED1;
761   __IO uint16_t STATW;
762   __I  uint16_t RXBUF;                                                           /*!< eUSCI_Ax Receive Buffer Register */
763   __IO uint16_t TXBUF;                                                           /*!< eUSCI_Ax Transmit Buffer Register */
764        uint16_t RESERVED2[5];
765   __IO uint16_t IE;                                                              /*!< eUSCI_Ax Interrupt Enable Register */
766   __IO uint16_t IFG;                                                             /*!< eUSCI_Ax Interrupt Flag Register */
767   __I  uint16_t IV;                                                              /*!< eUSCI_Ax Interrupt Vector Register */
768 } EUSCI_A_SPI_Type;
769 
770 /*@}*/ /* end of group EUSCI_A_SPI */
771 
772 
773 /******************************************************************************
774 * EUSCI_B Registers
775 ******************************************************************************/
776 /** @addtogroup EUSCI_B MSP432P401V (EUSCI_B)
777   @{
778 */
779 typedef struct {
780   __IO uint16_t CTLW0;                                                           /*!< eUSCI_Bx Control Word Register 0 */
781   __IO uint16_t CTLW1;                                                           /*!< eUSCI_Bx Control Word Register 1 */
782        uint16_t RESERVED0;
783   __IO uint16_t BRW;                                                             /*!< eUSCI_Bx Baud Rate Control Word Register */
784   __IO uint16_t STATW;                                                           /*!< eUSCI_Bx Status Register */
785   __IO uint16_t TBCNT;                                                           /*!< eUSCI_Bx Byte Counter Threshold Register */
786   __I  uint16_t RXBUF;                                                           /*!< eUSCI_Bx Receive Buffer Register */
787   __IO uint16_t TXBUF;                                                           /*!< eUSCI_Bx Transmit Buffer Register */
788        uint16_t RESERVED1[2];
789   __IO uint16_t I2COA0;                                                          /*!< eUSCI_Bx I2C Own Address 0 Register */
790   __IO uint16_t I2COA1;                                                          /*!< eUSCI_Bx I2C Own Address 1 Register */
791   __IO uint16_t I2COA2;                                                          /*!< eUSCI_Bx I2C Own Address 2 Register */
792   __IO uint16_t I2COA3;                                                          /*!< eUSCI_Bx I2C Own Address 3 Register */
793   __I  uint16_t ADDRX;                                                           /*!< eUSCI_Bx I2C Received Address Register */
794   __IO uint16_t ADDMASK;                                                         /*!< eUSCI_Bx I2C Address Mask Register */
795   __IO uint16_t I2CSA;                                                           /*!< eUSCI_Bx I2C Slave Address Register */
796        uint16_t RESERVED2[4];
797   __IO uint16_t IE;                                                              /*!< eUSCI_Bx Interrupt Enable Register */
798   __IO uint16_t IFG;                                                             /*!< eUSCI_Bx Interrupt Flag Register */
799   __I  uint16_t IV;                                                              /*!< eUSCI_Bx Interrupt Vector Register */
800 } EUSCI_B_Type;
801 
802 /*@}*/ /* end of group EUSCI_B */
803 
804 /** @addtogroup EUSCI_B_SPI MSP432P401V (EUSCI_B_SPI)
805   @{
806 */
807 typedef struct {
808   __IO uint16_t CTLW0;                                                           /*!< eUSCI_Bx Control Word Register 0 */
809        uint16_t RESERVED0[2];
810   __IO uint16_t BRW;                                                             /*!< eUSCI_Bx Bit Rate Control Register 1 */
811   __IO uint16_t STATW;
812        uint16_t RESERVED1;
813   __I  uint16_t RXBUF;                                                           /*!< eUSCI_Bx Receive Buffer Register */
814   __IO uint16_t TXBUF;                                                           /*!< eUSCI_Bx Transmit Buffer Register */
815        uint16_t RESERVED2[13];
816   __IO uint16_t IE;                                                              /*!< eUSCI_Bx Interrupt Enable Register */
817   __IO uint16_t IFG;                                                             /*!< eUSCI_Bx Interrupt Flag Register */
818   __I  uint16_t IV;                                                              /*!< eUSCI_Bx Interrupt Vector Register */
819 } EUSCI_B_SPI_Type;
820 
821 /*@}*/ /* end of group EUSCI_B_SPI */
822 
823 
824 /******************************************************************************
825 * FLCTL_A Registers
826 ******************************************************************************/
827 /** @addtogroup FLCTL_A MSP432P401V (FLCTL_A)
828   @{
829 */
830 typedef struct {
831   __I  uint32_t POWER_STAT;                                                      /*!< Power Status Register */
832        uint32_t RESERVED0[3];
833   __IO uint32_t BANK0_RDCTL;                                                     /*!< Bank0 Read Control Register */
834   __IO uint32_t BANK1_RDCTL;                                                     /*!< Bank1 Read Control Register */
835        uint32_t RESERVED1[2];
836   __IO uint32_t RDBRST_CTLSTAT;                                                  /*!< Read Burst/Compare Control and Status Register */
837   __IO uint32_t RDBRST_STARTADDR;                                                /*!< Read Burst/Compare Start Address Register */
838   __IO uint32_t RDBRST_LEN;                                                      /*!< Read Burst/Compare Length Register */
839        uint32_t RESERVED2[4];
840   __IO uint32_t RDBRST_FAILADDR;                                                 /*!< Read Burst/Compare Fail Address Register */
841   __IO uint32_t RDBRST_FAILCNT;                                                  /*!< Read Burst/Compare Fail Count Register */
842        uint32_t RESERVED3[3];
843   __IO uint32_t PRG_CTLSTAT;                                                     /*!< Program Control and Status Register */
844   __IO uint32_t PRGBRST_CTLSTAT;                                                 /*!< Program Burst Control and Status Register */
845   __IO uint32_t PRGBRST_STARTADDR;                                               /*!< Program Burst Start Address Register */
846        uint32_t RESERVED4;
847   __IO uint32_t PRGBRST_DATA0_0;                                                 /*!< Program Burst Data0 Register0 */
848   __IO uint32_t PRGBRST_DATA0_1;                                                 /*!< Program Burst Data0 Register1 */
849   __IO uint32_t PRGBRST_DATA0_2;                                                 /*!< Program Burst Data0 Register2 */
850   __IO uint32_t PRGBRST_DATA0_3;                                                 /*!< Program Burst Data0 Register3 */
851   __IO uint32_t PRGBRST_DATA1_0;                                                 /*!< Program Burst Data1 Register0 */
852   __IO uint32_t PRGBRST_DATA1_1;                                                 /*!< Program Burst Data1 Register1 */
853   __IO uint32_t PRGBRST_DATA1_2;                                                 /*!< Program Burst Data1 Register2 */
854   __IO uint32_t PRGBRST_DATA1_3;                                                 /*!< Program Burst Data1 Register3 */
855   __IO uint32_t PRGBRST_DATA2_0;                                                 /*!< Program Burst Data2 Register0 */
856   __IO uint32_t PRGBRST_DATA2_1;                                                 /*!< Program Burst Data2 Register1 */
857   __IO uint32_t PRGBRST_DATA2_2;                                                 /*!< Program Burst Data2 Register2 */
858   __IO uint32_t PRGBRST_DATA2_3;                                                 /*!< Program Burst Data2 Register3 */
859   __IO uint32_t PRGBRST_DATA3_0;                                                 /*!< Program Burst Data3 Register0 */
860   __IO uint32_t PRGBRST_DATA3_1;                                                 /*!< Program Burst Data3 Register1 */
861   __IO uint32_t PRGBRST_DATA3_2;                                                 /*!< Program Burst Data3 Register2 */
862   __IO uint32_t PRGBRST_DATA3_3;                                                 /*!< Program Burst Data3 Register3 */
863   __IO uint32_t ERASE_CTLSTAT;                                                   /*!< Erase Control and Status Register */
864   __IO uint32_t ERASE_SECTADDR;                                                  /*!< Erase Sector Address Register */
865        uint32_t RESERVED5[2];
866   __IO uint32_t BANK0_INFO_WEPROT;                                               /*!< Information Memory Bank0 Write/Erase Protection Register */
867   __IO uint32_t BANK0_MAIN_WEPROT;                                               /*!< Main Memory Bank0 Write/Erase Protection Register */
868        uint32_t RESERVED6[2];
869   __IO uint32_t BANK1_INFO_WEPROT;                                               /*!< Information Memory Bank1 Write/Erase Protection Register */
870   __IO uint32_t BANK1_MAIN_WEPROT;                                               /*!< Main Memory Bank1 Write/Erase Protection Register */
871        uint32_t RESERVED7[2];
872   __IO uint32_t BMRK_CTLSTAT;                                                    /*!< Benchmark Control and Status Register */
873   __IO uint32_t BMRK_IFETCH;                                                     /*!< Benchmark Instruction Fetch Count Register */
874   __IO uint32_t BMRK_DREAD;                                                      /*!< Benchmark Data Read Count Register */
875   __IO uint32_t BMRK_CMP;                                                        /*!< Benchmark Count Compare Register */
876        uint32_t RESERVED8[4];
877   __IO uint32_t IFG;                                                             /*!< Interrupt Flag Register */
878   __IO uint32_t IE;                                                              /*!< Interrupt Enable Register */
879   __IO uint32_t CLRIFG;                                                          /*!< Clear Interrupt Flag Register */
880   __IO uint32_t SETIFG;                                                          /*!< Set Interrupt Flag Register */
881   __I  uint32_t READ_TIMCTL;                                                     /*!< Read Timing Control Register */
882   __I  uint32_t READMARGIN_TIMCTL;                                               /*!< Read Margin Timing Control Register */
883   __I  uint32_t PRGVER_TIMCTL;                                                   /*!< Program Verify Timing Control Register */
884   __I  uint32_t ERSVER_TIMCTL;                                                   /*!< Erase Verify Timing Control Register */
885   __I  uint32_t LKGVER_TIMCTL;                                                   /*!< Leakage Verify Timing Control Register */
886   __I  uint32_t PROGRAM_TIMCTL;                                                  /*!< Program Timing Control Register */
887   __I  uint32_t ERASE_TIMCTL;                                                    /*!< Erase Timing Control Register */
888   __I  uint32_t MASSERASE_TIMCTL;                                                /*!< Mass Erase Timing Control Register */
889   __I  uint32_t BURSTPRG_TIMCTL;                                                 /*!< Burst Program Timing Control Register */
890        uint32_t RESERVED9[55];
891   __IO uint32_t BANK0_MAIN_WEPROT0;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 0 */
892   __IO uint32_t BANK0_MAIN_WEPROT1;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 1 */
893   __IO uint32_t BANK0_MAIN_WEPROT2;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 2 */
894   __IO uint32_t BANK0_MAIN_WEPROT3;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 3 */
895   __IO uint32_t BANK0_MAIN_WEPROT4;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 4 */
896   __IO uint32_t BANK0_MAIN_WEPROT5;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 5 */
897   __IO uint32_t BANK0_MAIN_WEPROT6;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 6 */
898   __IO uint32_t BANK0_MAIN_WEPROT7;                                              /*!< Main Memory Bank0 Write/Erase Protection Register 7 */
899        uint32_t RESERVED10[8];
900   __IO uint32_t BANK1_MAIN_WEPROT0;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 0 */
901   __IO uint32_t BANK1_MAIN_WEPROT1;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 1 */
902   __IO uint32_t BANK1_MAIN_WEPROT2;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 2 */
903   __IO uint32_t BANK1_MAIN_WEPROT3;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 3 */
904   __IO uint32_t BANK1_MAIN_WEPROT4;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 4 */
905   __IO uint32_t BANK1_MAIN_WEPROT5;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 5 */
906   __IO uint32_t BANK1_MAIN_WEPROT6;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 6 */
907   __IO uint32_t BANK1_MAIN_WEPROT7;                                              /*!< Main Memory Bank1 Write/Erase Protection Register 7 */
908 } FLCTL_A_Type;
909 
910 /*@}*/ /* end of group FLCTL_A */
911 
912 
913 /******************************************************************************
914 * FL_BOOTOVER_MAILBOX Registers
915 ******************************************************************************/
916 /** @addtogroup SEC_ZONE_PARAMS MSP432P401V (FL_BOOTOVER_MAILBOX)
917   @{
918 */
919 typedef struct {
920   __IO uint32_t SEC_ZONE_SECEN;                                                  /*!< IP Protection Secure Zone Enable. */
921   __IO uint32_t SEC_ZONE_START_ADDR;                                             /*!< Start address of IP protected secure zone. */
922   __IO uint32_t SEC_ZONE_LENGTH;                                                 /*!< Length of IP protected secure zone in number of bytes. */
923   __IO uint32_t SEC_ZONE_AESINIT_VECT[4];                                        /*!< IP protected secure zone 0 AES initialization vector */
924   __IO uint32_t SEC_ZONE_SECKEYS[8];                                             /*!< AES-CBC security keys. */
925   __IO uint32_t SEC_ZONE_UNENC_PWD[4];                                           /*!< Unencrypted password for authentication. */
926   __IO uint32_t SEC_ZONE_ENCUPDATE_EN;                                           /*!< IP Protected Secure Zone Encrypted In-field Update Enable */
927   __IO uint32_t SEC_ZONE_DATA_EN;                                                /*!< IP Protected Secure Zone Data Access Enable */
928   __IO uint32_t SEC_ZONE_ACK;                                                    /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */
929        uint32_t RESERVED0[2];
930 } SEC_ZONE_PARAMS_Type;
931 
932 /*@}*/ /* end of group SEC_ZONE_PARAMS */
933 
934 /** @addtogroup SEC_ZONE_UPDATE MSP432P401V (FL_BOOTOVER_MAILBOX)
935   @{
936 */
937 typedef struct {
938   __IO uint32_t SEC_ZONE_PAYLOADADDR;                                            /*!< Start address where the payload is loaded in the device. */
939   __IO uint32_t SEC_ZONE_PAYLOADLEN;                                             /*!< Length of the payload in bytes. */
940   __IO uint32_t SEC_ZONE_UPDATE_ACK;                                             /*!< Acknowledgment for the IP Protected Secure Zone Update Command */
941        uint32_t RESERVED0;
942 } SEC_ZONE_UPDATE_Type;
943 
944 /*@}*/ /* end of group SEC_ZONE_UPDATE */
945 
946 /** @addtogroup FL_BOOTOVER_MAILBOX MSP432P401V (FL_BOOTOVER_MAILBOX)
947   @{
948 */
949 typedef struct {
950   __IO uint32_t MB_START;                                                        /*!< Flash MailBox start: 0x0115ACF6 */
951   __IO uint32_t CMD;                                                             /*!< Command for Boot override operations. */
952        uint32_t RESERVED0[2];
953   __IO uint32_t JTAG_SWD_LOCK_SECEN;                                             /*!< JTAG and SWD Lock Enable */
954   __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4];                                  /*!< JTAG and SWD lock AES initialization vector for AES-CBC */
955   __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8];                                    /*!< JTAG and SWD lock AES CBC security Keys 0-7. */
956   __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4];                                      /*!< JTAG and SWD lock unencrypted password */
957   __IO uint32_t JTAG_SWD_LOCK_ACK;                                               /*!< Acknowledgment for JTAG and SWD Lock command */
958        uint32_t RESERVED1[2];
959   SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4];
960   __IO uint32_t BSL_ENABLE;                                                      /*!< BSL Enable. */
961   __IO uint32_t BSL_START_ADDRESS;                                               /*!< Contains the pointer to the BSL function. */
962   __IO uint32_t BSL_PARAMETERS;                                                  /*!< BSL hardware invoke conifguration field. */
963        uint32_t RESERVED2[2];
964   __IO uint32_t BSL_ACK;                                                         /*!< Acknowledgment for the BSL Configuration Command */
965   __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD;                                     /*!< Start address where the payload is loaded in the device. */
966   __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN;                                     /*!< Length of the encrypted payload in bytes */
967   __IO uint32_t JTAG_SWD_LOCK_DST_ADDR;                                          /*!< Destination address where the final data needs to be stored into the device. */
968   __IO uint32_t ENC_UPDATE_ACK;                                                  /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */
969        uint32_t RESERVED3;
970   SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4];
971        uint32_t RESERVED4;
972   __IO uint32_t FACTORY_RESET_ENABLE;                                            /*!< Enable/Disable Factory Reset */
973   __IO uint32_t FACTORY_RESET_PWDEN;                                             /*!< Factory reset password enable */
974   __IO uint32_t FACTORY_RESET_PWD[4];                                            /*!< 128-bit Password for factory reset to be saved into the device. */
975   __IO uint32_t FACTORY_RESET_PARAMS_ACK;                                        /*!< Acknowledgment for the Factory Reset Params Command */
976        uint32_t RESERVED5;
977   __IO uint32_t FACTORY_RESET_PASSWORD[4];                                       /*!< 128-bit Password for factory reset. */
978   __IO uint32_t FACTORY_RESET_ACK;                                               /*!< Acknowledgment for the Factory Reset Command */
979        uint32_t RESERVED6[2];
980   __IO uint32_t MB_END;                                                          /*!< Mailbox end */
981 } FL_BOOTOVER_MAILBOX_Type;
982 
983 /*@}*/ /* end of group FL_BOOTOVER_MAILBOX */
984 
985 
986 /******************************************************************************
987 * PCM Registers
988 ******************************************************************************/
989 /** @addtogroup PCM MSP432P401V (PCM)
990   @{
991 */
992 typedef struct {
993   __IO uint32_t CTL0;                                                            /*!< Control 0 Register */
994   __IO uint32_t CTL1;                                                            /*!< Control 1 Register */
995   __IO uint32_t IE;                                                              /*!< Interrupt Enable Register */
996   __I  uint32_t IFG;                                                             /*!< Interrupt Flag Register */
997   __O  uint32_t CLRIFG;                                                          /*!< Clear Interrupt Flag Register */
998 } PCM_Type;
999 
1000 /*@}*/ /* end of group PCM */
1001 
1002 
1003 /******************************************************************************
1004 * PMAP Registers
1005 ******************************************************************************/
1006 /** @addtogroup PMAP MSP432P4111 (PMAP)
1007   @{
1008 */
1009 typedef struct {
1010   __IO uint16_t KEYID;                                                           /*!< Port Mapping Key Register */
1011   __IO uint16_t CTL;                                                             /*!< Port Mapping Control Register */
1012 } PMAP_COMMON_Type;
1013 
1014 typedef struct {
1015   union {
1016     __IO uint16_t PMAP_REGISTER[4];                                              /*!< Port Mapping Registers */
1017     struct {
1018       __IO uint8_t PMAP_REGISTER0;                                               /*!< Port Mapping Register Bit 0 */
1019       __IO uint8_t PMAP_REGISTER1;                                               /*!< Port Mapping Register Bit 1 */
1020       __IO uint8_t PMAP_REGISTER2;                                               /*!< Port Mapping Register Bit 2 */
1021       __IO uint8_t PMAP_REGISTER3;                                               /*!< Port Mapping Register Bit 3 */
1022       __IO uint8_t PMAP_REGISTER4;                                               /*!< Port Mapping Register Bit 4 */
1023       __IO uint8_t PMAP_REGISTER5;                                               /*!< Port Mapping Register Bit 5 */
1024       __IO uint8_t PMAP_REGISTER6;                                               /*!< Port Mapping Register Bit 6 */
1025       __IO uint8_t PMAP_REGISTER7;                                               /*!< Port Mapping Register Bit 7 */
1026     };
1027   };
1028 } PMAP_REGISTER_Type;
1029 
1030 /*@}*/ /* end of group PMAP */
1031 
1032 
1033 /******************************************************************************
1034 * PSS Registers
1035 ******************************************************************************/
1036 /** @addtogroup PSS MSP432P401V (PSS)
1037   @{
1038 */
1039 typedef struct {
1040   __IO uint32_t KEY;                                                             /*!< Key Register */
1041   __IO uint32_t CTL0;                                                            /*!< Control 0 Register */
1042        uint32_t RESERVED0[11];
1043   __IO uint32_t IE;                                                              /*!< Interrupt Enable Register */
1044   __I  uint32_t IFG;                                                             /*!< Interrupt Flag Register */
1045   __IO uint32_t CLRIFG;                                                          /*!< Clear Interrupt Flag Register */
1046 } PSS_Type;
1047 
1048 /*@}*/ /* end of group PSS */
1049 
1050 
1051 /******************************************************************************
1052 * REF_A Registers
1053 ******************************************************************************/
1054 /** @addtogroup REF_A MSP432P401V (REF_A)
1055   @{
1056 */
1057 typedef struct {
1058   __IO uint16_t CTL0;                                                            /*!< REF Control Register 0 */
1059 } REF_A_Type;
1060 
1061 /*@}*/ /* end of group REF_A */
1062 
1063 
1064 /******************************************************************************
1065 * RSTCTL Registers
1066 ******************************************************************************/
1067 /** @addtogroup RSTCTL MSP432P401V (RSTCTL)
1068   @{
1069 */
1070 typedef struct {
1071   __IO uint32_t RESET_REQ;                                                       /*!< Reset Request Register */
1072   __I  uint32_t HARDRESET_STAT;                                                  /*!< Hard Reset Status Register */
1073   __IO uint32_t HARDRESET_CLR;                                                   /*!< Hard Reset Status Clear Register */
1074   __IO uint32_t HARDRESET_SET;                                                   /*!< Hard Reset Status Set Register */
1075   __I  uint32_t SOFTRESET_STAT;                                                  /*!< Soft Reset Status Register */
1076   __IO uint32_t SOFTRESET_CLR;                                                   /*!< Soft Reset Status Clear Register */
1077   __IO uint32_t SOFTRESET_SET;                                                   /*!< Soft Reset Status Set Register */
1078        uint32_t RESERVED0[57];
1079   __I  uint32_t PSSRESET_STAT;                                                   /*!< PSS Reset Status Register */
1080   __IO uint32_t PSSRESET_CLR;                                                    /*!< PSS Reset Status Clear Register */
1081   __I  uint32_t PCMRESET_STAT;                                                   /*!< PCM Reset Status Register */
1082   __IO uint32_t PCMRESET_CLR;                                                    /*!< PCM Reset Status Clear Register */
1083   __I  uint32_t PINRESET_STAT;                                                   /*!< Pin Reset Status Register */
1084   __IO uint32_t PINRESET_CLR;                                                    /*!< Pin Reset Status Clear Register */
1085   __I  uint32_t REBOOTRESET_STAT;                                                /*!< Reboot Reset Status Register */
1086   __IO uint32_t REBOOTRESET_CLR;                                                 /*!< Reboot Reset Status Clear Register */
1087   __I  uint32_t CSRESET_STAT;                                                    /*!< CS Reset Status Register */
1088   __IO uint32_t CSRESET_CLR;                                                     /*!< CS Reset Status Clear Register */
1089 } RSTCTL_Type;
1090 
1091 /*@}*/ /* end of group RSTCTL */
1092 
1093 
1094 /******************************************************************************
1095 * RTC_C Registers
1096 ******************************************************************************/
1097 /** @addtogroup RTC_C MSP432P401V (RTC_C)
1098   @{
1099 */
1100 typedef struct {
1101   __IO uint16_t CTL0;                                                            /*!< RTCCTL0 Register */
1102   __IO uint16_t CTL13;                                                           /*!< RTCCTL13 Register */
1103   __IO uint16_t OCAL;                                                            /*!< RTCOCAL Register */
1104   __IO uint16_t TCMP;                                                            /*!< RTCTCMP Register */
1105   __IO uint16_t PS0CTL;                                                          /*!< Real-Time Clock Prescale Timer 0 Control Register */
1106   __IO uint16_t PS1CTL;                                                          /*!< Real-Time Clock Prescale Timer 1 Control Register */
1107   __IO uint16_t PS;                                                              /*!< Real-Time Clock Prescale Timer Counter Register */
1108   __I  uint16_t IV;                                                              /*!< Real-Time Clock Interrupt Vector Register */
1109   __IO uint16_t TIM0;                                                            /*!< RTCTIM0 Register  Hexadecimal Format */
1110   __IO uint16_t TIM1;                                                            /*!< Real-Time Clock Hour, Day of Week */
1111   __IO uint16_t DATE;                                                            /*!< RTCDATE - Hexadecimal Format */
1112   __IO uint16_t YEAR;                                                            /*!< RTCYEAR Register  Hexadecimal Format */
1113   __IO uint16_t AMINHR;                                                          /*!< RTCMINHR - Hexadecimal Format */
1114   __IO uint16_t ADOWDAY;                                                         /*!< RTCADOWDAY - Hexadecimal Format */
1115   __IO uint16_t BIN2BCD;                                                         /*!< Binary-to-BCD Conversion Register */
1116   __IO uint16_t BCD2BIN;                                                         /*!< BCD-to-Binary Conversion Register */
1117 } RTC_C_Type;
1118 
1119 /*@}*/ /* end of group RTC_C */
1120 
1121 /** @addtogroup RTC_C_BCD MSP432P401V (RTC_C_BCD)
1122   @{
1123 */
1124 typedef struct {
1125        uint16_t RESERVED0[8];
1126   __IO uint16_t TIM0;                                                            /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */
1127   __IO uint16_t TIM1;                                                            /*!< Real-Time Clock Hour, Day of Week - BCD Format */
1128   __IO uint16_t DATE;                                                            /*!< Real-Time Clock Date - BCD Format */
1129   __IO uint16_t YEAR;                                                            /*!< Real-Time Clock Year Register - BCD Format */
1130   __IO uint16_t AMINHR;                                                          /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */
1131   __IO uint16_t ADOWDAY;                                                         /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */
1132 } RTC_C_BCD_Type;
1133 
1134 /*@}*/ /* end of group RTC_C_BCD */
1135 
1136 
1137 /******************************************************************************
1138 * SYSCTL_A Registers
1139 ******************************************************************************/
1140 /** @addtogroup SYSCTL_A MSP432P4111 (SYSCTL_A)
1141   @{
1142 */
1143 typedef struct {
1144   __IO uint32_t REBOOT_CTL;                                                      /*!< Reboot Control Register */
1145   __IO uint32_t NMI_CTLSTAT;                                                     /*!< NMI Control and Status Register */
1146   __IO uint32_t WDTRESET_CTL;                                                    /*!< Watchdog Reset Control Register */
1147   __IO uint32_t PERIHALT_CTL;                                                    /*!< Peripheral Halt Control Register */
1148   __I  uint32_t SRAM_SIZE;                                                       /*!< SRAM Size Register */
1149   __I  uint32_t SRAM_NUMBANKS;                                                   /*!< SRAM Number of Banks Register */
1150   __I  uint32_t SRAM_NUMBLOCKS;                                                  /*!< SRAM Number of Blocks Register */
1151        uint32_t RESERVED0;
1152   __I  uint32_t MAINFLASH_SIZE;                                                  /*!< Flash Main Memory Size Register */
1153   __I  uint32_t INFOFLASH_SIZE;                                                  /*!< Flash Information Memory Size Register */
1154        uint32_t RESERVED1[2];
1155   __IO uint32_t DIO_GLTFLT_CTL;                                                  /*!< Digital I/O Glitch Filter Control Register */
1156        uint32_t RESERVED2[3];
1157   __IO uint32_t SECDATA_UNLOCK;                                                  /*!< IP Protected Secure Zone Data Access Unlock Register */
1158        uint32_t RESERVED3[3];
1159   __IO uint32_t SRAM_BANKEN_CTL0;                                                /*!< SRAM Bank Enable Control Register 0 */
1160   __IO uint32_t SRAM_BANKEN_CTL1;                                                /*!< SRAM Bank Enable Control Register 1 */
1161   __IO uint32_t SRAM_BANKEN_CTL2;                                                /*!< SRAM Bank Enable Control Register 2 */
1162   __IO uint32_t SRAM_BANKEN_CTL3;                                                /*!< SRAM Bank Enable Control Register 3 */
1163        uint32_t RESERVED4[4];
1164   __IO uint32_t SRAM_BLKRET_CTL0;                                                /*!< SRAM Block Retention Control Register 0 */
1165   __IO uint32_t SRAM_BLKRET_CTL1;                                                /*!< SRAM Block Retention Control Register 1 */
1166   __IO uint32_t SRAM_BLKRET_CTL2;                                                /*!< SRAM Block Retention Control Register 2 */
1167   __IO uint32_t SRAM_BLKRET_CTL3;                                                /*!< SRAM Block Retention Control Register 3 */
1168        uint32_t RESERVED5[4];
1169   __I  uint32_t SRAM_STAT;                                                       /*!< SRAM Status Register */
1170 } SYSCTL_A_Type;
1171 
1172 typedef struct {
1173   __IO uint32_t MASTER_UNLOCK;                                                   /*!< Master Unlock Register */
1174   __IO uint32_t BOOTOVER_REQ[2];                                                 /*!< Boot Override Request Register */
1175   __IO uint32_t BOOTOVER_ACK;                                                    /*!< Boot Override Acknowledge Register */
1176   __IO uint32_t RESET_REQ;                                                       /*!< Reset Request Register */
1177   __IO uint32_t RESET_STATOVER;                                                  /*!< Reset Status and Override Register */
1178        uint32_t RESERVED10[2];
1179   __I  uint32_t SYSTEM_STAT;                                                     /*!< System Status Register */
1180 } SYSCTL_A_Boot_Type;
1181 
1182 /*@}*/ /* end of group SYSCTL_A */
1183 
1184 
1185 /******************************************************************************
1186 * Timer32 Registers
1187 ******************************************************************************/
1188 /** @addtogroup Timer32 MSP432P4111 (Timer32)
1189   @{
1190 */
1191 typedef struct {
1192   __IO uint32_t LOAD;                                                            /*!< Timer Load Register */
1193   __I  uint32_t VALUE;                                                           /*!< Timer Current Value Register */
1194   __IO uint32_t CONTROL;                                                         /*!< Timer Timer Control Register */
1195   __O  uint32_t INTCLR;                                                          /*!< Timer Interrupt Clear Register */
1196   __I  uint32_t RIS;                                                             /*!< Timer Raw Interrupt Status Register */
1197   __I  uint32_t MIS;                                                             /*!< Timer Interrupt Status Register */
1198   __IO uint32_t BGLOAD;                                                          /*!< Timer Background Load Register */
1199 } Timer32_Type;
1200 
1201 /*@}*/ /* end of group Timer32 */
1202 
1203 
1204 /******************************************************************************
1205 * Timer_A Registers
1206 ******************************************************************************/
1207 /** @addtogroup Timer_A MSP432P401V (Timer_A)
1208   @{
1209 */
1210 typedef struct {
1211   __IO uint16_t CTL;                                                             /*!< TimerAx Control Register */
1212   __IO uint16_t CCTL[5];                                                         /*!< Timer_A Capture/Compare Control Register */
1213        uint16_t RESERVED0[2];
1214   __IO uint16_t R;                                                               /*!< TimerA register */
1215   __IO uint16_t CCR[5];                                                          /*!< Timer_A Capture/Compare  Register */
1216        uint16_t RESERVED1[2];
1217   __IO uint16_t EX0;                                                             /*!< TimerAx Expansion 0 Register */
1218        uint16_t RESERVED2[6];
1219   __I  uint16_t IV;                                                              /*!< TimerAx Interrupt Vector Register */
1220 } Timer_A_Type;
1221 
1222 /*@}*/ /* end of group Timer_A */
1223 
1224 
1225 /******************************************************************************
1226 * TLV Registers
1227 ******************************************************************************/
1228 /** @addtogroup TLV MSP432P401V (TLV)
1229   @{
1230 */
1231 typedef struct {
1232   __I  uint32_t TLV_CHECKSUM;                                                    /*!< TLV Checksum */
1233   __I  uint32_t DEVICE_INFO_TAG;                                                 /*!< Device Info Tag */
1234   __I  uint32_t DEVICE_INFO_LEN;                                                 /*!< Device Info Length */
1235   __I  uint32_t DEVICE_ID;                                                       /*!< Device ID */
1236   __I  uint32_t HWREV;                                                           /*!< HW Revision */
1237   __I  uint32_t BCREV;                                                           /*!< Boot Code Revision */
1238   __I  uint32_t ROM_DRVLIB_REV;                                                  /*!< ROM Driver Library Revision */
1239   __I  uint32_t DIE_REC_TAG;                                                     /*!< Die Record Tag */
1240   __I  uint32_t DIE_REC_LEN;                                                     /*!< Die Record Length */
1241   __I  uint32_t DIE_XPOS;                                                        /*!< Die X-Position */
1242   __I  uint32_t DIE_YPOS;                                                        /*!< Die Y-Position */
1243   __I  uint32_t WAFER_ID;                                                        /*!< Wafer ID */
1244   __I  uint32_t LOT_ID;                                                          /*!< Lot ID */
1245   __I  uint32_t RESERVED0;                                                       /*!< Reserved */
1246   __I  uint32_t RESERVED1;                                                       /*!< Reserved */
1247   __I  uint32_t RESERVED2;                                                       /*!< Reserved */
1248   __I  uint32_t TEST_RESULTS;                                                    /*!< Test Results */
1249   __I  uint32_t CS_CAL_TAG;                                                      /*!< Clock System Calibration Tag */
1250   __I  uint32_t CS_CAL_LEN;                                                      /*!< Clock System Calibration Length */
1251   __I  uint32_t DCOIR_FCAL_RSEL04;                                               /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */
1252   __I  uint32_t DCOIR_FCAL_RSEL5;                                                /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */
1253   __I  uint32_t RESERVED3;                                                       /*!< Reserved */
1254   __I  uint32_t RESERVED4;                                                       /*!< Reserved */
1255   __I  uint32_t RESERVED5;                                                       /*!< Reserved */
1256   __I  uint32_t RESERVED6;                                                       /*!< Reserved */
1257   __I  uint32_t DCOIR_CONSTK_RSEL04;                                             /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */
1258   __I  uint32_t DCOIR_CONSTK_RSEL5;                                              /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */
1259   __I  uint32_t DCOER_FCAL_RSEL04;                                               /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */
1260   __I  uint32_t DCOER_FCAL_RSEL5;                                                /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */
1261   __I  uint32_t RESERVED7;                                                       /*!< Reserved */
1262   __I  uint32_t RESERVED8;                                                       /*!< Reserved */
1263   __I  uint32_t RESERVED9;                                                       /*!< Reserved */
1264   __I  uint32_t RESERVED10;                                                      /*!< Reserved */
1265   __I  uint32_t DCOER_CONSTK_RSEL04;                                             /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */
1266   __I  uint32_t DCOER_CONSTK_RSEL5;                                              /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */
1267   __I  uint32_t ADC14_CAL_TAG;                                                   /*!< ADC14 Calibration Tag */
1268   __I  uint32_t ADC14_CAL_LEN;                                                   /*!< ADC14 Calibration Length */
1269   __I  uint32_t ADC_GAIN_FACTOR;                                                 /*!< ADC Gain Factor */
1270   __I  uint32_t ADC_OFFSET;                                                      /*!< ADC Offset */
1271   __I  uint32_t RESERVED11;                                                      /*!< Reserved */
1272   __I  uint32_t RESERVED12;                                                      /*!< Reserved */
1273   __I  uint32_t RESERVED13;                                                      /*!< Reserved */
1274   __I  uint32_t RESERVED14;                                                      /*!< Reserved */
1275   __I  uint32_t RESERVED15;                                                      /*!< Reserved */
1276   __I  uint32_t RESERVED16;                                                      /*!< Reserved */
1277   __I  uint32_t RESERVED17;                                                      /*!< Reserved */
1278   __I  uint32_t RESERVED18;                                                      /*!< Reserved */
1279   __I  uint32_t RESERVED19;                                                      /*!< Reserved */
1280   __I  uint32_t RESERVED20;                                                      /*!< Reserved */
1281   __I  uint32_t RESERVED21;                                                      /*!< Reserved */
1282   __I  uint32_t RESERVED22;                                                      /*!< Reserved */
1283   __I  uint32_t RESERVED23;                                                      /*!< Reserved */
1284   __I  uint32_t RESERVED24;                                                      /*!< Reserved */
1285   __I  uint32_t RESERVED25;                                                      /*!< Reserved */
1286   __I  uint32_t RESERVED26;                                                      /*!< Reserved */
1287   __I  uint32_t ADC14_REF1P2V_TS30C;                                             /*!< ADC14 1.2V Reference Temp. Sensor 30C */
1288   __I  uint32_t ADC14_REF1P2V_TS85C;                                             /*!< ADC14 1.2V Reference Temp. Sensor 85C */
1289   __I  uint32_t ADC14_REF1P45V_TS30C;                                            /*!< ADC14 1.45V Reference Temp. Sensor 30C */
1290   __I  uint32_t ADC14_REF1P45V_TS85C;                                            /*!< ADC14 1.45V Reference Temp. Sensor 85C */
1291   __I  uint32_t ADC14_REF2P5V_TS30C;                                             /*!< ADC14 2.5V Reference Temp. Sensor 30C */
1292   __I  uint32_t ADC14_REF2P5V_TS85C;                                             /*!< ADC14 2.5V Reference Temp. Sensor 85C */
1293   __I  uint32_t REF_CAL_TAG;                                                     /*!< REF Calibration Tag */
1294   __I  uint32_t REF_CAL_LEN;                                                     /*!< REF Calibration Length */
1295   __I  uint32_t REF_1P2V;                                                        /*!< REF 1.2V Reference */
1296   __I  uint32_t REF_1P45V;                                                       /*!< REF 1.45V Reference */
1297   __I  uint32_t REF_2P5V;                                                        /*!< REF 2.5V Reference */
1298   __I  uint32_t FLASH_INFO_TAG;                                                  /*!< Flash Info Tag */
1299   __I  uint32_t FLASH_INFO_LEN;                                                  /*!< Flash Info Length */
1300   __I  uint32_t FLASH_MAX_PROG_PULSES;                                           /*!< Flash Maximum Programming Pulses */
1301   __I  uint32_t FLASH_MAX_ERASE_PULSES;                                          /*!< Flash Maximum Erase Pulses */
1302   __I  uint32_t RANDOM_NUM_TAG;                                                  /*!< 128-bit Random Number Tag */
1303   __I  uint32_t RANDOM_NUM_LEN;                                                  /*!< 128-bit Random Number Length */
1304   __I  uint32_t RANDOM_NUM_1;                                                    /*!< 32-bit Random Number 1 */
1305   __I  uint32_t RANDOM_NUM_2;                                                    /*!< 32-bit Random Number 2 */
1306   __I  uint32_t RANDOM_NUM_3;                                                    /*!< 32-bit Random Number 3 */
1307   __I  uint32_t RANDOM_NUM_4;                                                    /*!< 32-bit Random Number 4 */
1308   __I  uint32_t BSL_CFG_TAG;                                                     /*!< BSL Configuration Tag */
1309   __I  uint32_t BSL_CFG_LEN;                                                     /*!< BSL Configuration Length */
1310   __I  uint32_t BSL_PERIPHIF_SEL;                                                /*!< BSL Peripheral Interface Selection */
1311   __I  uint32_t BSL_PORTIF_CFG_UART;                                             /*!< BSL Port Interface Configuration for UART */
1312   __I  uint32_t BSL_PORTIF_CFG_SPI;                                              /*!< BSL Port Interface Configuration for SPI */
1313   __I  uint32_t BSL_PORTIF_CFG_I2C;                                              /*!< BSL Port Interface Configuration for I2C */
1314   __I  uint32_t TLV_END;                                                         /*!< TLV End Word */
1315 } TLV_Type;
1316 
1317 /*@}*/ /* end of group TLV */
1318 
1319 
1320 /******************************************************************************
1321 * WDT_A Registers
1322 ******************************************************************************/
1323 /** @addtogroup WDT_A MSP432P401V (WDT_A)
1324   @{
1325 */
1326 typedef struct {
1327        uint16_t RESERVED0[6];
1328   __IO uint16_t CTL;                                                             /*!< Watchdog Timer Control Register */
1329 } WDT_A_Type;
1330 
1331 /*@}*/ /* end of group WDT_A */
1332 
1333 
1334 /* --------------------  End of section using anonymous unions  ------------------- */
1335 #if defined(__CC_ARM)
1336   #pragma pop
1337 #elif defined(__ICCARM__)
1338   /* leave anonymous unions enabled */
1339 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
1340   #pragma clang diagnostic pop
1341 #elif defined(__GNUC__)
1342   /* anonymous unions are enabled by default */
1343 #elif defined(__TI_ARM__)
1344   /* anonymous unions are enabled by default */
1345 #else
1346   #warning Not supported compiler type
1347 #endif
1348 
1349 /*@}*/ /* end of group MSP432P401V_Peripherals */
1350 
1351 /******************************************************************************
1352 * Peripheral declaration                                                      *
1353 ******************************************************************************/
1354 /** @addtogroup MSP432P401V_PeripheralDecl MSP432P401V Peripheral Declaration
1355   @{
1356 */
1357 
1358 #define ADC14                            ((ADC14_Type *) ADC14_BASE)
1359 #define AES256                           ((AES256_Type *) AES256_BASE)
1360 #define CAPTIO0                          ((CAPTIO_Type *) CAPTIO0_BASE)
1361 #define CAPTIO1                          ((CAPTIO_Type *) CAPTIO1_BASE)
1362 #define COMP_E0                          ((COMP_E_Type *) COMP_E0_BASE)
1363 #define COMP_E1                          ((COMP_E_Type *) COMP_E1_BASE)
1364 #define CRC32                            ((CRC32_Type *) CRC32_BASE)
1365 #define CS                               ((CS_Type *) CS_BASE)
1366 #define PA                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000))
1367 #define PB                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020))
1368 #define PC                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040))
1369 #define PD                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060))
1370 #define PE                               ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080))
1371 #define PJ                               ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120))
1372 #define P1                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0000))
1373 #define P2                               ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000))
1374 #define P3                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0020))
1375 #define P4                               ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020))
1376 #define P5                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0040))
1377 #define P6                               ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040))
1378 #define P7                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0060))
1379 #define P8                               ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060))
1380 #define P9                               ((DIO_PORT_Odd_Interruptable_Type*)  (DIO_BASE + 0x0080))
1381 #define P10                              ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080))
1382 #define DMA_Channel                      ((DMA_Channel_Type *) DMA_BASE)
1383 #define DMA_Control                      ((DMA_Control_Type *) (DMA_BASE + 0x1000))
1384 #define EUSCI_A0                         ((EUSCI_A_Type *) EUSCI_A0_BASE)
1385 #define EUSCI_A0_SPI                     ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE)
1386 #define EUSCI_A1                         ((EUSCI_A_Type *) EUSCI_A1_BASE)
1387 #define EUSCI_A1_SPI                     ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE)
1388 #define EUSCI_A2                         ((EUSCI_A_Type *) EUSCI_A2_BASE)
1389 #define EUSCI_A2_SPI                     ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE)
1390 #define EUSCI_B0                         ((EUSCI_B_Type *) EUSCI_B0_BASE)
1391 #define EUSCI_B0_SPI                     ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE)
1392 #define EUSCI_B2                         ((EUSCI_B_Type *) EUSCI_B2_BASE)
1393 #define EUSCI_B2_SPI                     ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE)
1394 #define EUSCI_B3                         ((EUSCI_B_Type *) EUSCI_B3_BASE)
1395 #define EUSCI_B3_SPI                     ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE)
1396 #define FLCTL_A                          ((FLCTL_A_Type *) FLCTL_A_BASE)
1397 #define FL_BOOTOVER_MAILBOX              ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE)
1398 #define PCM                              ((PCM_Type *) PCM_BASE)
1399 #define PMAP                             ((PMAP_COMMON_Type*) PMAP_BASE)
1400 #define P1MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008))
1401 #define P2MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010))
1402 #define P3MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018))
1403 #define P4MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020))
1404 #define P5MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028))
1405 #define P6MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030))
1406 #define P7MAP                            ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038))
1407 #define PSS                              ((PSS_Type *) PSS_BASE)
1408 #define REF_A                            ((REF_A_Type *) REF_A_BASE)
1409 #define RSTCTL                           ((RSTCTL_Type *) RSTCTL_BASE)
1410 #define RTC_C                            ((RTC_C_Type *) RTC_C_BASE)
1411 #define RTC_C_BCD                        ((RTC_C_BCD_Type *) RTC_C_BCD_BASE)
1412 #define SYSCTL_A                         ((SYSCTL_A_Type *) SYSCTL_A_BASE)
1413 #define SYSCTL_A_Boot                    ((SYSCTL_A_Boot_Type *) (SYSCTL_A_BASE + 0x1000))
1414 #define TIMER32_1                        ((Timer32_Type *) TIMER32_BASE)
1415 #define TIMER32_2                        ((Timer32_Type *) (TIMER32_BASE + 0x00020))
1416 #define TIMER_A0                         ((Timer_A_Type *) TIMER_A0_BASE)
1417 #define TIMER_A1                         ((Timer_A_Type *) TIMER_A1_BASE)
1418 #define TIMER_A2                         ((Timer_A_Type *) TIMER_A2_BASE)
1419 #define TLV                              ((TLV_Type *) TLV_BASE)
1420 #define WDT_A                            ((WDT_A_Type *) WDT_A_BASE)
1421 
1422 
1423 /*@}*/ /* end of group MSP432P401V_PeripheralDecl */
1424 
1425 /*@}*/ /* end of group MSP432P401V_Definitions */
1426 
1427 #endif /* __CMSIS_CONFIG__ */
1428 
1429 /******************************************************************************
1430 * Peripheral register control bits                                            *
1431 ******************************************************************************/
1432 
1433 /******************************************************************************
1434 * ADC14 Bits
1435 ******************************************************************************/
1436 /* ADC14_CTL0[SC] Bits */
1437 #define ADC14_CTL0_SC_OFS                        ( 0)                            /*!< ADC14SC Bit Offset */
1438 #define ADC14_CTL0_SC                            ((uint32_t)0x00000001)          /*!< ADC14 start conversion */
1439 /* ADC14_CTL0[ENC] Bits */
1440 #define ADC14_CTL0_ENC_OFS                       ( 1)                            /*!< ADC14ENC Bit Offset */
1441 #define ADC14_CTL0_ENC                           ((uint32_t)0x00000002)          /*!< ADC14 enable conversion */
1442 /* ADC14_CTL0[ON] Bits */
1443 #define ADC14_CTL0_ON_OFS                        ( 4)                            /*!< ADC14ON Bit Offset */
1444 #define ADC14_CTL0_ON                            ((uint32_t)0x00000010)          /*!< ADC14 on */
1445 /* ADC14_CTL0[MSC] Bits */
1446 #define ADC14_CTL0_MSC_OFS                       ( 7)                            /*!< ADC14MSC Bit Offset */
1447 #define ADC14_CTL0_MSC                           ((uint32_t)0x00000080)          /*!< ADC14 multiple sample and conversion */
1448 /* ADC14_CTL0[SHT0] Bits */
1449 #define ADC14_CTL0_SHT0_OFS                      ( 8)                            /*!< ADC14SHT0 Bit Offset */
1450 #define ADC14_CTL0_SHT0_MASK                     ((uint32_t)0x00000F00)          /*!< ADC14SHT0 Bit Mask */
1451 #define ADC14_CTL0_SHT00                         ((uint32_t)0x00000100)          /*!< SHT0 Bit 0 */
1452 #define ADC14_CTL0_SHT01                         ((uint32_t)0x00000200)          /*!< SHT0 Bit 1 */
1453 #define ADC14_CTL0_SHT02                         ((uint32_t)0x00000400)          /*!< SHT0 Bit 2 */
1454 #define ADC14_CTL0_SHT03                         ((uint32_t)0x00000800)          /*!< SHT0 Bit 3 */
1455 #define ADC14_CTL0_SHT0_0                        ((uint32_t)0x00000000)          /*!< 4 */
1456 #define ADC14_CTL0_SHT0_1                        ((uint32_t)0x00000100)          /*!< 8 */
1457 #define ADC14_CTL0_SHT0_2                        ((uint32_t)0x00000200)          /*!< 16 */
1458 #define ADC14_CTL0_SHT0_3                        ((uint32_t)0x00000300)          /*!< 32 */
1459 #define ADC14_CTL0_SHT0_4                        ((uint32_t)0x00000400)          /*!< 64 */
1460 #define ADC14_CTL0_SHT0_5                        ((uint32_t)0x00000500)          /*!< 96 */
1461 #define ADC14_CTL0_SHT0_6                        ((uint32_t)0x00000600)          /*!< 128 */
1462 #define ADC14_CTL0_SHT0_7                        ((uint32_t)0x00000700)          /*!< 192 */
1463 #define ADC14_CTL0_SHT0__4                       ((uint32_t)0x00000000)          /*!< 4 */
1464 #define ADC14_CTL0_SHT0__8                       ((uint32_t)0x00000100)          /*!< 8 */
1465 #define ADC14_CTL0_SHT0__16                      ((uint32_t)0x00000200)          /*!< 16 */
1466 #define ADC14_CTL0_SHT0__32                      ((uint32_t)0x00000300)          /*!< 32 */
1467 #define ADC14_CTL0_SHT0__64                      ((uint32_t)0x00000400)          /*!< 64 */
1468 #define ADC14_CTL0_SHT0__96                      ((uint32_t)0x00000500)          /*!< 96 */
1469 #define ADC14_CTL0_SHT0__128                     ((uint32_t)0x00000600)          /*!< 128 */
1470 #define ADC14_CTL0_SHT0__192                     ((uint32_t)0x00000700)          /*!< 192 */
1471 /* ADC14_CTL0[SHT1] Bits */
1472 #define ADC14_CTL0_SHT1_OFS                      (12)                            /*!< ADC14SHT1 Bit Offset */
1473 #define ADC14_CTL0_SHT1_MASK                     ((uint32_t)0x0000F000)          /*!< ADC14SHT1 Bit Mask */
1474 #define ADC14_CTL0_SHT10                         ((uint32_t)0x00001000)          /*!< SHT1 Bit 0 */
1475 #define ADC14_CTL0_SHT11                         ((uint32_t)0x00002000)          /*!< SHT1 Bit 1 */
1476 #define ADC14_CTL0_SHT12                         ((uint32_t)0x00004000)          /*!< SHT1 Bit 2 */
1477 #define ADC14_CTL0_SHT13                         ((uint32_t)0x00008000)          /*!< SHT1 Bit 3 */
1478 #define ADC14_CTL0_SHT1_0                        ((uint32_t)0x00000000)          /*!< 4 */
1479 #define ADC14_CTL0_SHT1_1                        ((uint32_t)0x00001000)          /*!< 8 */
1480 #define ADC14_CTL0_SHT1_2                        ((uint32_t)0x00002000)          /*!< 16 */
1481 #define ADC14_CTL0_SHT1_3                        ((uint32_t)0x00003000)          /*!< 32 */
1482 #define ADC14_CTL0_SHT1_4                        ((uint32_t)0x00004000)          /*!< 64 */
1483 #define ADC14_CTL0_SHT1_5                        ((uint32_t)0x00005000)          /*!< 96 */
1484 #define ADC14_CTL0_SHT1_6                        ((uint32_t)0x00006000)          /*!< 128 */
1485 #define ADC14_CTL0_SHT1_7                        ((uint32_t)0x00007000)          /*!< 192 */
1486 #define ADC14_CTL0_SHT1__4                       ((uint32_t)0x00000000)          /*!< 4 */
1487 #define ADC14_CTL0_SHT1__8                       ((uint32_t)0x00001000)          /*!< 8 */
1488 #define ADC14_CTL0_SHT1__16                      ((uint32_t)0x00002000)          /*!< 16 */
1489 #define ADC14_CTL0_SHT1__32                      ((uint32_t)0x00003000)          /*!< 32 */
1490 #define ADC14_CTL0_SHT1__64                      ((uint32_t)0x00004000)          /*!< 64 */
1491 #define ADC14_CTL0_SHT1__96                      ((uint32_t)0x00005000)          /*!< 96 */
1492 #define ADC14_CTL0_SHT1__128                     ((uint32_t)0x00006000)          /*!< 128 */
1493 #define ADC14_CTL0_SHT1__192                     ((uint32_t)0x00007000)          /*!< 192 */
1494 /* ADC14_CTL0[BUSY] Bits */
1495 #define ADC14_CTL0_BUSY_OFS                      (16)                            /*!< ADC14BUSY Bit Offset */
1496 #define ADC14_CTL0_BUSY                          ((uint32_t)0x00010000)          /*!< ADC14 busy */
1497 /* ADC14_CTL0[CONSEQ] Bits */
1498 #define ADC14_CTL0_CONSEQ_OFS                    (17)                            /*!< ADC14CONSEQ Bit Offset */
1499 #define ADC14_CTL0_CONSEQ_MASK                   ((uint32_t)0x00060000)          /*!< ADC14CONSEQ Bit Mask */
1500 #define ADC14_CTL0_CONSEQ0                       ((uint32_t)0x00020000)          /*!< CONSEQ Bit 0 */
1501 #define ADC14_CTL0_CONSEQ1                       ((uint32_t)0x00040000)          /*!< CONSEQ Bit 1 */
1502 #define ADC14_CTL0_CONSEQ_0                      ((uint32_t)0x00000000)          /*!< Single-channel, single-conversion */
1503 #define ADC14_CTL0_CONSEQ_1                      ((uint32_t)0x00020000)          /*!< Sequence-of-channels */
1504 #define ADC14_CTL0_CONSEQ_2                      ((uint32_t)0x00040000)          /*!< Repeat-single-channel */
1505 #define ADC14_CTL0_CONSEQ_3                      ((uint32_t)0x00060000)          /*!< Repeat-sequence-of-channels */
1506 /* ADC14_CTL0[SSEL] Bits */
1507 #define ADC14_CTL0_SSEL_OFS                      (19)                            /*!< ADC14SSEL Bit Offset */
1508 #define ADC14_CTL0_SSEL_MASK                     ((uint32_t)0x00380000)          /*!< ADC14SSEL Bit Mask */
1509 #define ADC14_CTL0_SSEL0                         ((uint32_t)0x00080000)          /*!< SSEL Bit 0 */
1510 #define ADC14_CTL0_SSEL1                         ((uint32_t)0x00100000)          /*!< SSEL Bit 1 */
1511 #define ADC14_CTL0_SSEL2                         ((uint32_t)0x00200000)          /*!< SSEL Bit 2 */
1512 #define ADC14_CTL0_SSEL_0                        ((uint32_t)0x00000000)          /*!< MODCLK */
1513 #define ADC14_CTL0_SSEL_1                        ((uint32_t)0x00080000)          /*!< SYSCLK */
1514 #define ADC14_CTL0_SSEL_2                        ((uint32_t)0x00100000)          /*!< ACLK */
1515 #define ADC14_CTL0_SSEL_3                        ((uint32_t)0x00180000)          /*!< MCLK */
1516 #define ADC14_CTL0_SSEL_4                        ((uint32_t)0x00200000)          /*!< SMCLK */
1517 #define ADC14_CTL0_SSEL_5                        ((uint32_t)0x00280000)          /*!< HSMCLK */
1518 #define ADC14_CTL0_SSEL__MODCLK                  ((uint32_t)0x00000000)          /*!< MODCLK */
1519 #define ADC14_CTL0_SSEL__SYSCLK                  ((uint32_t)0x00080000)          /*!< SYSCLK */
1520 #define ADC14_CTL0_SSEL__ACLK                    ((uint32_t)0x00100000)          /*!< ACLK */
1521 #define ADC14_CTL0_SSEL__MCLK                    ((uint32_t)0x00180000)          /*!< MCLK */
1522 #define ADC14_CTL0_SSEL__SMCLK                   ((uint32_t)0x00200000)          /*!< SMCLK */
1523 #define ADC14_CTL0_SSEL__HSMCLK                  ((uint32_t)0x00280000)          /*!< HSMCLK */
1524 /* ADC14_CTL0[DIV] Bits */
1525 #define ADC14_CTL0_DIV_OFS                       (22)                            /*!< ADC14DIV Bit Offset */
1526 #define ADC14_CTL0_DIV_MASK                      ((uint32_t)0x01C00000)          /*!< ADC14DIV Bit Mask */
1527 #define ADC14_CTL0_DIV0                          ((uint32_t)0x00400000)          /*!< DIV Bit 0 */
1528 #define ADC14_CTL0_DIV1                          ((uint32_t)0x00800000)          /*!< DIV Bit 1 */
1529 #define ADC14_CTL0_DIV2                          ((uint32_t)0x01000000)          /*!< DIV Bit 2 */
1530 #define ADC14_CTL0_DIV_0                         ((uint32_t)0x00000000)          /*!< /1 */
1531 #define ADC14_CTL0_DIV_1                         ((uint32_t)0x00400000)          /*!< /2 */
1532 #define ADC14_CTL0_DIV_2                         ((uint32_t)0x00800000)          /*!< /3 */
1533 #define ADC14_CTL0_DIV_3                         ((uint32_t)0x00C00000)          /*!< /4 */
1534 #define ADC14_CTL0_DIV_4                         ((uint32_t)0x01000000)          /*!< /5 */
1535 #define ADC14_CTL0_DIV_5                         ((uint32_t)0x01400000)          /*!< /6 */
1536 #define ADC14_CTL0_DIV_6                         ((uint32_t)0x01800000)          /*!< /7 */
1537 #define ADC14_CTL0_DIV_7                         ((uint32_t)0x01C00000)          /*!< /8 */
1538 #define ADC14_CTL0_DIV__1                        ((uint32_t)0x00000000)          /*!< /1 */
1539 #define ADC14_CTL0_DIV__2                        ((uint32_t)0x00400000)          /*!< /2 */
1540 #define ADC14_CTL0_DIV__3                        ((uint32_t)0x00800000)          /*!< /3 */
1541 #define ADC14_CTL0_DIV__4                        ((uint32_t)0x00C00000)          /*!< /4 */
1542 #define ADC14_CTL0_DIV__5                        ((uint32_t)0x01000000)          /*!< /5 */
1543 #define ADC14_CTL0_DIV__6                        ((uint32_t)0x01400000)          /*!< /6 */
1544 #define ADC14_CTL0_DIV__7                        ((uint32_t)0x01800000)          /*!< /7 */
1545 #define ADC14_CTL0_DIV__8                        ((uint32_t)0x01C00000)          /*!< /8 */
1546 /* ADC14_CTL0[ISSH] Bits */
1547 #define ADC14_CTL0_ISSH_OFS                      (25)                            /*!< ADC14ISSH Bit Offset */
1548 #define ADC14_CTL0_ISSH                          ((uint32_t)0x02000000)          /*!< ADC14 invert signal sample-and-hold */
1549 /* ADC14_CTL0[SHP] Bits */
1550 #define ADC14_CTL0_SHP_OFS                       (26)                            /*!< ADC14SHP Bit Offset */
1551 #define ADC14_CTL0_SHP                           ((uint32_t)0x04000000)          /*!< ADC14 sample-and-hold pulse-mode select */
1552 /* ADC14_CTL0[SHS] Bits */
1553 #define ADC14_CTL0_SHS_OFS                       (27)                            /*!< ADC14SHS Bit Offset */
1554 #define ADC14_CTL0_SHS_MASK                      ((uint32_t)0x38000000)          /*!< ADC14SHS Bit Mask */
1555 #define ADC14_CTL0_SHS0                          ((uint32_t)0x08000000)          /*!< SHS Bit 0 */
1556 #define ADC14_CTL0_SHS1                          ((uint32_t)0x10000000)          /*!< SHS Bit 1 */
1557 #define ADC14_CTL0_SHS2                          ((uint32_t)0x20000000)          /*!< SHS Bit 2 */
1558 #define ADC14_CTL0_SHS_0                         ((uint32_t)0x00000000)          /*!< ADC14SC bit */
1559 #define ADC14_CTL0_SHS_1                         ((uint32_t)0x08000000)          /*!< See device-specific data sheet for source */
1560 #define ADC14_CTL0_SHS_2                         ((uint32_t)0x10000000)          /*!< See device-specific data sheet for source */
1561 #define ADC14_CTL0_SHS_3                         ((uint32_t)0x18000000)          /*!< See device-specific data sheet for source */
1562 #define ADC14_CTL0_SHS_4                         ((uint32_t)0x20000000)          /*!< See device-specific data sheet for source */
1563 #define ADC14_CTL0_SHS_5                         ((uint32_t)0x28000000)          /*!< See device-specific data sheet for source */
1564 #define ADC14_CTL0_SHS_6                         ((uint32_t)0x30000000)          /*!< See device-specific data sheet for source */
1565 #define ADC14_CTL0_SHS_7                         ((uint32_t)0x38000000)          /*!< See device-specific data sheet for source */
1566 /* ADC14_CTL0[PDIV] Bits */
1567 #define ADC14_CTL0_PDIV_OFS                      (30)                            /*!< ADC14PDIV Bit Offset */
1568 #define ADC14_CTL0_PDIV_MASK                     ((uint32_t)0xC0000000)          /*!< ADC14PDIV Bit Mask */
1569 #define ADC14_CTL0_PDIV0                         ((uint32_t)0x40000000)          /*!< PDIV Bit 0 */
1570 #define ADC14_CTL0_PDIV1                         ((uint32_t)0x80000000)          /*!< PDIV Bit 1 */
1571 #define ADC14_CTL0_PDIV_0                        ((uint32_t)0x00000000)          /*!< Predivide by 1 */
1572 #define ADC14_CTL0_PDIV_1                        ((uint32_t)0x40000000)          /*!< Predivide by 4 */
1573 #define ADC14_CTL0_PDIV_2                        ((uint32_t)0x80000000)          /*!< Predivide by 32 */
1574 #define ADC14_CTL0_PDIV_3                        ((uint32_t)0xC0000000)          /*!< Predivide by 64 */
1575 #define ADC14_CTL0_PDIV__1                       ((uint32_t)0x00000000)          /*!< Predivide by 1 */
1576 #define ADC14_CTL0_PDIV__4                       ((uint32_t)0x40000000)          /*!< Predivide by 4 */
1577 #define ADC14_CTL0_PDIV__32                      ((uint32_t)0x80000000)          /*!< Predivide by 32 */
1578 #define ADC14_CTL0_PDIV__64                      ((uint32_t)0xC0000000)          /*!< Predivide by 64 */
1579 /* ADC14_CTL1[PWRMD] Bits */
1580 #define ADC14_CTL1_PWRMD_OFS                     ( 0)                            /*!< ADC14PWRMD Bit Offset */
1581 #define ADC14_CTL1_PWRMD_MASK                    ((uint32_t)0x00000003)          /*!< ADC14PWRMD Bit Mask */
1582 #define ADC14_CTL1_PWRMD0                        ((uint32_t)0x00000001)          /*!< PWRMD Bit 0 */
1583 #define ADC14_CTL1_PWRMD1                        ((uint32_t)0x00000002)          /*!< PWRMD Bit 1 */
1584 #define ADC14_CTL1_PWRMD_0                       ((uint32_t)0x00000000)          /*!< Regular power mode for use with any resolution setting. Sample rate can be  */
1585                                                                                  /* up to 1 Msps. */
1586 #define ADC14_CTL1_PWRMD_2                       ((uint32_t)0x00000002)          /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample  */
1587                                                                                  /* rate must not exceed 200 ksps. */
1588 /* ADC14_CTL1[REFBURST] Bits */
1589 #define ADC14_CTL1_REFBURST_OFS                  ( 2)                            /*!< ADC14REFBURST Bit Offset */
1590 #define ADC14_CTL1_REFBURST                      ((uint32_t)0x00000004)          /*!< ADC14 reference buffer burst */
1591 /* ADC14_CTL1[DF] Bits */
1592 #define ADC14_CTL1_DF_OFS                        ( 3)                            /*!< ADC14DF Bit Offset */
1593 #define ADC14_CTL1_DF                            ((uint32_t)0x00000008)          /*!< ADC14 data read-back format */
1594 /* ADC14_CTL1[RES] Bits */
1595 #define ADC14_CTL1_RES_OFS                       ( 4)                            /*!< ADC14RES Bit Offset */
1596 #define ADC14_CTL1_RES_MASK                      ((uint32_t)0x00000030)          /*!< ADC14RES Bit Mask */
1597 #define ADC14_CTL1_RES0                          ((uint32_t)0x00000010)          /*!< RES Bit 0 */
1598 #define ADC14_CTL1_RES1                          ((uint32_t)0x00000020)          /*!< RES Bit 1 */
1599 #define ADC14_CTL1_RES_0                         ((uint32_t)0x00000000)          /*!< 8 bit (9 clock cycle conversion time) */
1600 #define ADC14_CTL1_RES_1                         ((uint32_t)0x00000010)          /*!< 10 bit (11 clock cycle conversion time) */
1601 #define ADC14_CTL1_RES_2                         ((uint32_t)0x00000020)          /*!< 12 bit (14 clock cycle conversion time) */
1602 #define ADC14_CTL1_RES_3                         ((uint32_t)0x00000030)          /*!< 14 bit (16 clock cycle conversion time) */
1603 #define ADC14_CTL1_RES__8BIT                     ((uint32_t)0x00000000)          /*!< 8 bit (9 clock cycle conversion time) */
1604 #define ADC14_CTL1_RES__10BIT                    ((uint32_t)0x00000010)          /*!< 10 bit (11 clock cycle conversion time) */
1605 #define ADC14_CTL1_RES__12BIT                    ((uint32_t)0x00000020)          /*!< 12 bit (14 clock cycle conversion time) */
1606 #define ADC14_CTL1_RES__14BIT                    ((uint32_t)0x00000030)          /*!< 14 bit (16 clock cycle conversion time) */
1607 /* ADC14_CTL1[CSTARTADD] Bits */
1608 #define ADC14_CTL1_CSTARTADD_OFS                 (16)                            /*!< ADC14CSTARTADD Bit Offset */
1609 #define ADC14_CTL1_CSTARTADD_MASK                ((uint32_t)0x001F0000)          /*!< ADC14CSTARTADD Bit Mask */
1610 /* ADC14_CTL1[BATMAP] Bits */
1611 #define ADC14_CTL1_BATMAP_OFS                    (22)                            /*!< ADC14BATMAP Bit Offset */
1612 #define ADC14_CTL1_BATMAP                        ((uint32_t)0x00400000)          /*!< Controls 1/2 AVCC ADC input channel selection */
1613 /* ADC14_CTL1[TCMAP] Bits */
1614 #define ADC14_CTL1_TCMAP_OFS                     (23)                            /*!< ADC14TCMAP Bit Offset */
1615 #define ADC14_CTL1_TCMAP                         ((uint32_t)0x00800000)          /*!< Controls temperature sensor ADC input channel selection */
1616 /* ADC14_CTL1[CH0MAP] Bits */
1617 #define ADC14_CTL1_CH0MAP_OFS                    (24)                            /*!< ADC14CH0MAP Bit Offset */
1618 #define ADC14_CTL1_CH0MAP                        ((uint32_t)0x01000000)          /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */
1619 /* ADC14_CTL1[CH1MAP] Bits */
1620 #define ADC14_CTL1_CH1MAP_OFS                    (25)                            /*!< ADC14CH1MAP Bit Offset */
1621 #define ADC14_CTL1_CH1MAP                        ((uint32_t)0x02000000)          /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */
1622 /* ADC14_CTL1[CH2MAP] Bits */
1623 #define ADC14_CTL1_CH2MAP_OFS                    (26)                            /*!< ADC14CH2MAP Bit Offset */
1624 #define ADC14_CTL1_CH2MAP                        ((uint32_t)0x04000000)          /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */
1625 /* ADC14_CTL1[CH3MAP] Bits */
1626 #define ADC14_CTL1_CH3MAP_OFS                    (27)                            /*!< ADC14CH3MAP Bit Offset */
1627 #define ADC14_CTL1_CH3MAP                        ((uint32_t)0x08000000)          /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */
1628 /* ADC14_LO0[LO0] Bits */
1629 #define ADC14_LO0_LO0_OFS                        ( 0)                            /*!< ADC14LO0 Bit Offset */
1630 #define ADC14_LO0_LO0_MASK                       ((uint32_t)0x0000FFFF)          /*!< ADC14LO0 Bit Mask */
1631 /* ADC14_HI0[HI0] Bits */
1632 #define ADC14_HI0_HI0_OFS                        ( 0)                            /*!< ADC14HI0 Bit Offset */
1633 #define ADC14_HI0_HI0_MASK                       ((uint32_t)0x0000FFFF)          /*!< ADC14HI0 Bit Mask */
1634 /* ADC14_LO1[LO1] Bits */
1635 #define ADC14_LO1_LO1_OFS                        ( 0)                            /*!< ADC14LO1 Bit Offset */
1636 #define ADC14_LO1_LO1_MASK                       ((uint32_t)0x0000FFFF)          /*!< ADC14LO1 Bit Mask */
1637 /* ADC14_HI1[HI1] Bits */
1638 #define ADC14_HI1_HI1_OFS                        ( 0)                            /*!< ADC14HI1 Bit Offset */
1639 #define ADC14_HI1_HI1_MASK                       ((uint32_t)0x0000FFFF)          /*!< ADC14HI1 Bit Mask */
1640 /* ADC14_MCTLN[INCH] Bits */
1641 #define ADC14_MCTLN_INCH_OFS                     ( 0)                            /*!< ADC14INCH Bit Offset */
1642 #define ADC14_MCTLN_INCH_MASK                    ((uint32_t)0x0000001F)          /*!< ADC14INCH Bit Mask */
1643 #define ADC14_MCTLN_INCH0                        ((uint32_t)0x00000001)          /*!< INCH Bit 0 */
1644 #define ADC14_MCTLN_INCH1                        ((uint32_t)0x00000002)          /*!< INCH Bit 1 */
1645 #define ADC14_MCTLN_INCH2                        ((uint32_t)0x00000004)          /*!< INCH Bit 2 */
1646 #define ADC14_MCTLN_INCH3                        ((uint32_t)0x00000008)          /*!< INCH Bit 3 */
1647 #define ADC14_MCTLN_INCH4                        ((uint32_t)0x00000010)          /*!< INCH Bit 4 */
1648 #define ADC14_MCTLN_INCH_0                       ((uint32_t)0x00000000)          /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
1649 #define ADC14_MCTLN_INCH_1                       ((uint32_t)0x00000001)          /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */
1650 #define ADC14_MCTLN_INCH_2                       ((uint32_t)0x00000002)          /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
1651 #define ADC14_MCTLN_INCH_3                       ((uint32_t)0x00000003)          /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */
1652 #define ADC14_MCTLN_INCH_4                       ((uint32_t)0x00000004)          /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
1653 #define ADC14_MCTLN_INCH_5                       ((uint32_t)0x00000005)          /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */
1654 #define ADC14_MCTLN_INCH_6                       ((uint32_t)0x00000006)          /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
1655 #define ADC14_MCTLN_INCH_7                       ((uint32_t)0x00000007)          /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */
1656 #define ADC14_MCTLN_INCH_8                       ((uint32_t)0x00000008)          /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
1657 #define ADC14_MCTLN_INCH_9                       ((uint32_t)0x00000009)          /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */
1658 #define ADC14_MCTLN_INCH_10                      ((uint32_t)0x0000000A)          /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
1659 #define ADC14_MCTLN_INCH_11                      ((uint32_t)0x0000000B)          /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */
1660 #define ADC14_MCTLN_INCH_12                      ((uint32_t)0x0000000C)          /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
1661 #define ADC14_MCTLN_INCH_13                      ((uint32_t)0x0000000D)          /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */
1662 #define ADC14_MCTLN_INCH_14                      ((uint32_t)0x0000000E)          /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
1663 #define ADC14_MCTLN_INCH_15                      ((uint32_t)0x0000000F)          /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */
1664 #define ADC14_MCTLN_INCH_16                      ((uint32_t)0x00000010)          /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
1665 #define ADC14_MCTLN_INCH_17                      ((uint32_t)0x00000011)          /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */
1666 #define ADC14_MCTLN_INCH_18                      ((uint32_t)0x00000012)          /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
1667 #define ADC14_MCTLN_INCH_19                      ((uint32_t)0x00000013)          /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */
1668 #define ADC14_MCTLN_INCH_20                      ((uint32_t)0x00000014)          /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
1669 #define ADC14_MCTLN_INCH_21                      ((uint32_t)0x00000015)          /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */
1670 #define ADC14_MCTLN_INCH_22                      ((uint32_t)0x00000016)          /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
1671 #define ADC14_MCTLN_INCH_23                      ((uint32_t)0x00000017)          /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */
1672 #define ADC14_MCTLN_INCH_24                      ((uint32_t)0x00000018)          /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
1673 #define ADC14_MCTLN_INCH_25                      ((uint32_t)0x00000019)          /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */
1674 #define ADC14_MCTLN_INCH_26                      ((uint32_t)0x0000001A)          /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
1675 #define ADC14_MCTLN_INCH_27                      ((uint32_t)0x0000001B)          /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */
1676 #define ADC14_MCTLN_INCH_28                      ((uint32_t)0x0000001C)          /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
1677 #define ADC14_MCTLN_INCH_29                      ((uint32_t)0x0000001D)          /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */
1678 #define ADC14_MCTLN_INCH_30                      ((uint32_t)0x0000001E)          /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
1679 #define ADC14_MCTLN_INCH_31                      ((uint32_t)0x0000001F)          /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */
1680 /* ADC14_MCTLN[EOS] Bits */
1681 #define ADC14_MCTLN_EOS_OFS                      ( 7)                            /*!< ADC14EOS Bit Offset */
1682 #define ADC14_MCTLN_EOS                          ((uint32_t)0x00000080)          /*!< End of sequence */
1683 /* ADC14_MCTLN[VRSEL] Bits */
1684 #define ADC14_MCTLN_VRSEL_OFS                    ( 8)                            /*!< ADC14VRSEL Bit Offset */
1685 #define ADC14_MCTLN_VRSEL_MASK                   ((uint32_t)0x00000F00)          /*!< ADC14VRSEL Bit Mask */
1686 #define ADC14_MCTLN_VRSEL0                       ((uint32_t)0x00000100)          /*!< VRSEL Bit 0 */
1687 #define ADC14_MCTLN_VRSEL1                       ((uint32_t)0x00000200)          /*!< VRSEL Bit 1 */
1688 #define ADC14_MCTLN_VRSEL2                       ((uint32_t)0x00000400)          /*!< VRSEL Bit 2 */
1689 #define ADC14_MCTLN_VRSEL3                       ((uint32_t)0x00000800)          /*!< VRSEL Bit 3 */
1690 #define ADC14_MCTLN_VRSEL_0                      ((uint32_t)0x00000000)          /*!< V(R+) = AVCC, V(R-) = AVSS */
1691 #define ADC14_MCTLN_VRSEL_1                      ((uint32_t)0x00000100)          /*!< V(R+) = VREF buffered, V(R-) = AVSS */
1692 #define ADC14_MCTLN_VRSEL_14                     ((uint32_t)0x00000E00)          /*!< V(R+) = VeREF+, V(R-) = VeREF- */
1693 #define ADC14_MCTLN_VRSEL_15                     ((uint32_t)0x00000F00)          /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */
1694 /* ADC14_MCTLN[DIF] Bits */
1695 #define ADC14_MCTLN_DIF_OFS                      (13)                            /*!< ADC14DIF Bit Offset */
1696 #define ADC14_MCTLN_DIF                          ((uint32_t)0x00002000)          /*!< Differential mode */
1697 /* ADC14_MCTLN[WINC] Bits */
1698 #define ADC14_MCTLN_WINC_OFS                     (14)                            /*!< ADC14WINC Bit Offset */
1699 #define ADC14_MCTLN_WINC                         ((uint32_t)0x00004000)          /*!< Comparator window enable */
1700 /* ADC14_MCTLN[WINCTH] Bits */
1701 #define ADC14_MCTLN_WINCTH_OFS                   (15)                            /*!< ADC14WINCTH Bit Offset */
1702 #define ADC14_MCTLN_WINCTH                       ((uint32_t)0x00008000)          /*!< Window comparator threshold register selection */
1703 /* ADC14_MEMN[CONVRES] Bits */
1704 #define ADC14_MEMN_CONVRES_OFS                   ( 0)                            /*!< Conversion_Results Bit Offset */
1705 #define ADC14_MEMN_CONVRES_MASK                  ((uint32_t)0x0000FFFF)          /*!< Conversion_Results Bit Mask */
1706 /* ADC14_IER0[IE0] Bits */
1707 #define ADC14_IER0_IE0_OFS                       ( 0)                            /*!< ADC14IE0 Bit Offset */
1708 #define ADC14_IER0_IE0                           ((uint32_t)0x00000001)          /*!< Interrupt enable */
1709 /* ADC14_IER0[IE1] Bits */
1710 #define ADC14_IER0_IE1_OFS                       ( 1)                            /*!< ADC14IE1 Bit Offset */
1711 #define ADC14_IER0_IE1                           ((uint32_t)0x00000002)          /*!< Interrupt enable */
1712 /* ADC14_IER0[IE2] Bits */
1713 #define ADC14_IER0_IE2_OFS                       ( 2)                            /*!< ADC14IE2 Bit Offset */
1714 #define ADC14_IER0_IE2                           ((uint32_t)0x00000004)          /*!< Interrupt enable */
1715 /* ADC14_IER0[IE3] Bits */
1716 #define ADC14_IER0_IE3_OFS                       ( 3)                            /*!< ADC14IE3 Bit Offset */
1717 #define ADC14_IER0_IE3                           ((uint32_t)0x00000008)          /*!< Interrupt enable */
1718 /* ADC14_IER0[IE4] Bits */
1719 #define ADC14_IER0_IE4_OFS                       ( 4)                            /*!< ADC14IE4 Bit Offset */
1720 #define ADC14_IER0_IE4                           ((uint32_t)0x00000010)          /*!< Interrupt enable */
1721 /* ADC14_IER0[IE5] Bits */
1722 #define ADC14_IER0_IE5_OFS                       ( 5)                            /*!< ADC14IE5 Bit Offset */
1723 #define ADC14_IER0_IE5                           ((uint32_t)0x00000020)          /*!< Interrupt enable */
1724 /* ADC14_IER0[IE6] Bits */
1725 #define ADC14_IER0_IE6_OFS                       ( 6)                            /*!< ADC14IE6 Bit Offset */
1726 #define ADC14_IER0_IE6                           ((uint32_t)0x00000040)          /*!< Interrupt enable */
1727 /* ADC14_IER0[IE7] Bits */
1728 #define ADC14_IER0_IE7_OFS                       ( 7)                            /*!< ADC14IE7 Bit Offset */
1729 #define ADC14_IER0_IE7                           ((uint32_t)0x00000080)          /*!< Interrupt enable */
1730 /* ADC14_IER0[IE8] Bits */
1731 #define ADC14_IER0_IE8_OFS                       ( 8)                            /*!< ADC14IE8 Bit Offset */
1732 #define ADC14_IER0_IE8                           ((uint32_t)0x00000100)          /*!< Interrupt enable */
1733 /* ADC14_IER0[IE9] Bits */
1734 #define ADC14_IER0_IE9_OFS                       ( 9)                            /*!< ADC14IE9 Bit Offset */
1735 #define ADC14_IER0_IE9                           ((uint32_t)0x00000200)          /*!< Interrupt enable */
1736 /* ADC14_IER0[IE10] Bits */
1737 #define ADC14_IER0_IE10_OFS                      (10)                            /*!< ADC14IE10 Bit Offset */
1738 #define ADC14_IER0_IE10                          ((uint32_t)0x00000400)          /*!< Interrupt enable */
1739 /* ADC14_IER0[IE11] Bits */
1740 #define ADC14_IER0_IE11_OFS                      (11)                            /*!< ADC14IE11 Bit Offset */
1741 #define ADC14_IER0_IE11                          ((uint32_t)0x00000800)          /*!< Interrupt enable */
1742 /* ADC14_IER0[IE12] Bits */
1743 #define ADC14_IER0_IE12_OFS                      (12)                            /*!< ADC14IE12 Bit Offset */
1744 #define ADC14_IER0_IE12                          ((uint32_t)0x00001000)          /*!< Interrupt enable */
1745 /* ADC14_IER0[IE13] Bits */
1746 #define ADC14_IER0_IE13_OFS                      (13)                            /*!< ADC14IE13 Bit Offset */
1747 #define ADC14_IER0_IE13                          ((uint32_t)0x00002000)          /*!< Interrupt enable */
1748 /* ADC14_IER0[IE14] Bits */
1749 #define ADC14_IER0_IE14_OFS                      (14)                            /*!< ADC14IE14 Bit Offset */
1750 #define ADC14_IER0_IE14                          ((uint32_t)0x00004000)          /*!< Interrupt enable */
1751 /* ADC14_IER0[IE15] Bits */
1752 #define ADC14_IER0_IE15_OFS                      (15)                            /*!< ADC14IE15 Bit Offset */
1753 #define ADC14_IER0_IE15                          ((uint32_t)0x00008000)          /*!< Interrupt enable */
1754 /* ADC14_IER0[IE16] Bits */
1755 #define ADC14_IER0_IE16_OFS                      (16)                            /*!< ADC14IE16 Bit Offset */
1756 #define ADC14_IER0_IE16                          ((uint32_t)0x00010000)          /*!< Interrupt enable */
1757 /* ADC14_IER0[IE17] Bits */
1758 #define ADC14_IER0_IE17_OFS                      (17)                            /*!< ADC14IE17 Bit Offset */
1759 #define ADC14_IER0_IE17                          ((uint32_t)0x00020000)          /*!< Interrupt enable */
1760 /* ADC14_IER0[IE19] Bits */
1761 #define ADC14_IER0_IE19_OFS                      (19)                            /*!< ADC14IE19 Bit Offset */
1762 #define ADC14_IER0_IE19                          ((uint32_t)0x00080000)          /*!< Interrupt enable */
1763 /* ADC14_IER0[IE18] Bits */
1764 #define ADC14_IER0_IE18_OFS                      (18)                            /*!< ADC14IE18 Bit Offset */
1765 #define ADC14_IER0_IE18                          ((uint32_t)0x00040000)          /*!< Interrupt enable */
1766 /* ADC14_IER0[IE20] Bits */
1767 #define ADC14_IER0_IE20_OFS                      (20)                            /*!< ADC14IE20 Bit Offset */
1768 #define ADC14_IER0_IE20                          ((uint32_t)0x00100000)          /*!< Interrupt enable */
1769 /* ADC14_IER0[IE21] Bits */
1770 #define ADC14_IER0_IE21_OFS                      (21)                            /*!< ADC14IE21 Bit Offset */
1771 #define ADC14_IER0_IE21                          ((uint32_t)0x00200000)          /*!< Interrupt enable */
1772 /* ADC14_IER0[IE22] Bits */
1773 #define ADC14_IER0_IE22_OFS                      (22)                            /*!< ADC14IE22 Bit Offset */
1774 #define ADC14_IER0_IE22                          ((uint32_t)0x00400000)          /*!< Interrupt enable */
1775 /* ADC14_IER0[IE23] Bits */
1776 #define ADC14_IER0_IE23_OFS                      (23)                            /*!< ADC14IE23 Bit Offset */
1777 #define ADC14_IER0_IE23                          ((uint32_t)0x00800000)          /*!< Interrupt enable */
1778 /* ADC14_IER0[IE24] Bits */
1779 #define ADC14_IER0_IE24_OFS                      (24)                            /*!< ADC14IE24 Bit Offset */
1780 #define ADC14_IER0_IE24                          ((uint32_t)0x01000000)          /*!< Interrupt enable */
1781 /* ADC14_IER0[IE25] Bits */
1782 #define ADC14_IER0_IE25_OFS                      (25)                            /*!< ADC14IE25 Bit Offset */
1783 #define ADC14_IER0_IE25                          ((uint32_t)0x02000000)          /*!< Interrupt enable */
1784 /* ADC14_IER0[IE26] Bits */
1785 #define ADC14_IER0_IE26_OFS                      (26)                            /*!< ADC14IE26 Bit Offset */
1786 #define ADC14_IER0_IE26                          ((uint32_t)0x04000000)          /*!< Interrupt enable */
1787 /* ADC14_IER0[IE27] Bits */
1788 #define ADC14_IER0_IE27_OFS                      (27)                            /*!< ADC14IE27 Bit Offset */
1789 #define ADC14_IER0_IE27                          ((uint32_t)0x08000000)          /*!< Interrupt enable */
1790 /* ADC14_IER0[IE28] Bits */
1791 #define ADC14_IER0_IE28_OFS                      (28)                            /*!< ADC14IE28 Bit Offset */
1792 #define ADC14_IER0_IE28                          ((uint32_t)0x10000000)          /*!< Interrupt enable */
1793 /* ADC14_IER0[IE29] Bits */
1794 #define ADC14_IER0_IE29_OFS                      (29)                            /*!< ADC14IE29 Bit Offset */
1795 #define ADC14_IER0_IE29                          ((uint32_t)0x20000000)          /*!< Interrupt enable */
1796 /* ADC14_IER0[IE30] Bits */
1797 #define ADC14_IER0_IE30_OFS                      (30)                            /*!< ADC14IE30 Bit Offset */
1798 #define ADC14_IER0_IE30                          ((uint32_t)0x40000000)          /*!< Interrupt enable */
1799 /* ADC14_IER0[IE31] Bits */
1800 #define ADC14_IER0_IE31_OFS                      (31)                            /*!< ADC14IE31 Bit Offset */
1801 #define ADC14_IER0_IE31                          ((uint32_t)0x80000000)          /*!< Interrupt enable */
1802 /* ADC14_IER1[INIE] Bits */
1803 #define ADC14_IER1_INIE_OFS                      ( 1)                            /*!< ADC14INIE Bit Offset */
1804 #define ADC14_IER1_INIE                          ((uint32_t)0x00000002)          /*!< Interrupt enable for ADC14MEMx within comparator window */
1805 /* ADC14_IER1[LOIE] Bits */
1806 #define ADC14_IER1_LOIE_OFS                      ( 2)                            /*!< ADC14LOIE Bit Offset */
1807 #define ADC14_IER1_LOIE                          ((uint32_t)0x00000004)          /*!< Interrupt enable for ADC14MEMx below comparator window */
1808 /* ADC14_IER1[HIIE] Bits */
1809 #define ADC14_IER1_HIIE_OFS                      ( 3)                            /*!< ADC14HIIE Bit Offset */
1810 #define ADC14_IER1_HIIE                          ((uint32_t)0x00000008)          /*!< Interrupt enable for ADC14MEMx above comparator window */
1811 /* ADC14_IER1[OVIE] Bits */
1812 #define ADC14_IER1_OVIE_OFS                      ( 4)                            /*!< ADC14OVIE Bit Offset */
1813 #define ADC14_IER1_OVIE                          ((uint32_t)0x00000010)          /*!< ADC14MEMx overflow-interrupt enable */
1814 /* ADC14_IER1[TOVIE] Bits */
1815 #define ADC14_IER1_TOVIE_OFS                     ( 5)                            /*!< ADC14TOVIE Bit Offset */
1816 #define ADC14_IER1_TOVIE                         ((uint32_t)0x00000020)          /*!< ADC14 conversion-time-overflow interrupt enable */
1817 /* ADC14_IER1[RDYIE] Bits */
1818 #define ADC14_IER1_RDYIE_OFS                     ( 6)                            /*!< ADC14RDYIE Bit Offset */
1819 #define ADC14_IER1_RDYIE                         ((uint32_t)0x00000040)          /*!< ADC14 local buffered reference ready interrupt enable */
1820 /* ADC14_IFGR0[IFG0] Bits */
1821 #define ADC14_IFGR0_IFG0_OFS                     ( 0)                            /*!< ADC14IFG0 Bit Offset */
1822 #define ADC14_IFGR0_IFG0                         ((uint32_t)0x00000001)          /*!< ADC14MEM0 interrupt flag */
1823 /* ADC14_IFGR0[IFG1] Bits */
1824 #define ADC14_IFGR0_IFG1_OFS                     ( 1)                            /*!< ADC14IFG1 Bit Offset */
1825 #define ADC14_IFGR0_IFG1                         ((uint32_t)0x00000002)          /*!< ADC14MEM1 interrupt flag */
1826 /* ADC14_IFGR0[IFG2] Bits */
1827 #define ADC14_IFGR0_IFG2_OFS                     ( 2)                            /*!< ADC14IFG2 Bit Offset */
1828 #define ADC14_IFGR0_IFG2                         ((uint32_t)0x00000004)          /*!< ADC14MEM2 interrupt flag */
1829 /* ADC14_IFGR0[IFG3] Bits */
1830 #define ADC14_IFGR0_IFG3_OFS                     ( 3)                            /*!< ADC14IFG3 Bit Offset */
1831 #define ADC14_IFGR0_IFG3                         ((uint32_t)0x00000008)          /*!< ADC14MEM3 interrupt flag */
1832 /* ADC14_IFGR0[IFG4] Bits */
1833 #define ADC14_IFGR0_IFG4_OFS                     ( 4)                            /*!< ADC14IFG4 Bit Offset */
1834 #define ADC14_IFGR0_IFG4                         ((uint32_t)0x00000010)          /*!< ADC14MEM4 interrupt flag */
1835 /* ADC14_IFGR0[IFG5] Bits */
1836 #define ADC14_IFGR0_IFG5_OFS                     ( 5)                            /*!< ADC14IFG5 Bit Offset */
1837 #define ADC14_IFGR0_IFG5                         ((uint32_t)0x00000020)          /*!< ADC14MEM5 interrupt flag */
1838 /* ADC14_IFGR0[IFG6] Bits */
1839 #define ADC14_IFGR0_IFG6_OFS                     ( 6)                            /*!< ADC14IFG6 Bit Offset */
1840 #define ADC14_IFGR0_IFG6                         ((uint32_t)0x00000040)          /*!< ADC14MEM6 interrupt flag */
1841 /* ADC14_IFGR0[IFG7] Bits */
1842 #define ADC14_IFGR0_IFG7_OFS                     ( 7)                            /*!< ADC14IFG7 Bit Offset */
1843 #define ADC14_IFGR0_IFG7                         ((uint32_t)0x00000080)          /*!< ADC14MEM7 interrupt flag */
1844 /* ADC14_IFGR0[IFG8] Bits */
1845 #define ADC14_IFGR0_IFG8_OFS                     ( 8)                            /*!< ADC14IFG8 Bit Offset */
1846 #define ADC14_IFGR0_IFG8                         ((uint32_t)0x00000100)          /*!< ADC14MEM8 interrupt flag */
1847 /* ADC14_IFGR0[IFG9] Bits */
1848 #define ADC14_IFGR0_IFG9_OFS                     ( 9)                            /*!< ADC14IFG9 Bit Offset */
1849 #define ADC14_IFGR0_IFG9                         ((uint32_t)0x00000200)          /*!< ADC14MEM9 interrupt flag */
1850 /* ADC14_IFGR0[IFG10] Bits */
1851 #define ADC14_IFGR0_IFG10_OFS                    (10)                            /*!< ADC14IFG10 Bit Offset */
1852 #define ADC14_IFGR0_IFG10                        ((uint32_t)0x00000400)          /*!< ADC14MEM10 interrupt flag */
1853 /* ADC14_IFGR0[IFG11] Bits */
1854 #define ADC14_IFGR0_IFG11_OFS                    (11)                            /*!< ADC14IFG11 Bit Offset */
1855 #define ADC14_IFGR0_IFG11                        ((uint32_t)0x00000800)          /*!< ADC14MEM11 interrupt flag */
1856 /* ADC14_IFGR0[IFG12] Bits */
1857 #define ADC14_IFGR0_IFG12_OFS                    (12)                            /*!< ADC14IFG12 Bit Offset */
1858 #define ADC14_IFGR0_IFG12                        ((uint32_t)0x00001000)          /*!< ADC14MEM12 interrupt flag */
1859 /* ADC14_IFGR0[IFG13] Bits */
1860 #define ADC14_IFGR0_IFG13_OFS                    (13)                            /*!< ADC14IFG13 Bit Offset */
1861 #define ADC14_IFGR0_IFG13                        ((uint32_t)0x00002000)          /*!< ADC14MEM13 interrupt flag */
1862 /* ADC14_IFGR0[IFG14] Bits */
1863 #define ADC14_IFGR0_IFG14_OFS                    (14)                            /*!< ADC14IFG14 Bit Offset */
1864 #define ADC14_IFGR0_IFG14                        ((uint32_t)0x00004000)          /*!< ADC14MEM14 interrupt flag */
1865 /* ADC14_IFGR0[IFG15] Bits */
1866 #define ADC14_IFGR0_IFG15_OFS                    (15)                            /*!< ADC14IFG15 Bit Offset */
1867 #define ADC14_IFGR0_IFG15                        ((uint32_t)0x00008000)          /*!< ADC14MEM15 interrupt flag */
1868 /* ADC14_IFGR0[IFG16] Bits */
1869 #define ADC14_IFGR0_IFG16_OFS                    (16)                            /*!< ADC14IFG16 Bit Offset */
1870 #define ADC14_IFGR0_IFG16                        ((uint32_t)0x00010000)          /*!< ADC14MEM16 interrupt flag */
1871 /* ADC14_IFGR0[IFG17] Bits */
1872 #define ADC14_IFGR0_IFG17_OFS                    (17)                            /*!< ADC14IFG17 Bit Offset */
1873 #define ADC14_IFGR0_IFG17                        ((uint32_t)0x00020000)          /*!< ADC14MEM17 interrupt flag */
1874 /* ADC14_IFGR0[IFG18] Bits */
1875 #define ADC14_IFGR0_IFG18_OFS                    (18)                            /*!< ADC14IFG18 Bit Offset */
1876 #define ADC14_IFGR0_IFG18                        ((uint32_t)0x00040000)          /*!< ADC14MEM18 interrupt flag */
1877 /* ADC14_IFGR0[IFG19] Bits */
1878 #define ADC14_IFGR0_IFG19_OFS                    (19)                            /*!< ADC14IFG19 Bit Offset */
1879 #define ADC14_IFGR0_IFG19                        ((uint32_t)0x00080000)          /*!< ADC14MEM19 interrupt flag */
1880 /* ADC14_IFGR0[IFG20] Bits */
1881 #define ADC14_IFGR0_IFG20_OFS                    (20)                            /*!< ADC14IFG20 Bit Offset */
1882 #define ADC14_IFGR0_IFG20                        ((uint32_t)0x00100000)          /*!< ADC14MEM20 interrupt flag */
1883 /* ADC14_IFGR0[IFG21] Bits */
1884 #define ADC14_IFGR0_IFG21_OFS                    (21)                            /*!< ADC14IFG21 Bit Offset */
1885 #define ADC14_IFGR0_IFG21                        ((uint32_t)0x00200000)          /*!< ADC14MEM21 interrupt flag */
1886 /* ADC14_IFGR0[IFG22] Bits */
1887 #define ADC14_IFGR0_IFG22_OFS                    (22)                            /*!< ADC14IFG22 Bit Offset */
1888 #define ADC14_IFGR0_IFG22                        ((uint32_t)0x00400000)          /*!< ADC14MEM22 interrupt flag */
1889 /* ADC14_IFGR0[IFG23] Bits */
1890 #define ADC14_IFGR0_IFG23_OFS                    (23)                            /*!< ADC14IFG23 Bit Offset */
1891 #define ADC14_IFGR0_IFG23                        ((uint32_t)0x00800000)          /*!< ADC14MEM23 interrupt flag */
1892 /* ADC14_IFGR0[IFG24] Bits */
1893 #define ADC14_IFGR0_IFG24_OFS                    (24)                            /*!< ADC14IFG24 Bit Offset */
1894 #define ADC14_IFGR0_IFG24                        ((uint32_t)0x01000000)          /*!< ADC14MEM24 interrupt flag */
1895 /* ADC14_IFGR0[IFG25] Bits */
1896 #define ADC14_IFGR0_IFG25_OFS                    (25)                            /*!< ADC14IFG25 Bit Offset */
1897 #define ADC14_IFGR0_IFG25                        ((uint32_t)0x02000000)          /*!< ADC14MEM25 interrupt flag */
1898 /* ADC14_IFGR0[IFG26] Bits */
1899 #define ADC14_IFGR0_IFG26_OFS                    (26)                            /*!< ADC14IFG26 Bit Offset */
1900 #define ADC14_IFGR0_IFG26                        ((uint32_t)0x04000000)          /*!< ADC14MEM26 interrupt flag */
1901 /* ADC14_IFGR0[IFG27] Bits */
1902 #define ADC14_IFGR0_IFG27_OFS                    (27)                            /*!< ADC14IFG27 Bit Offset */
1903 #define ADC14_IFGR0_IFG27                        ((uint32_t)0x08000000)          /*!< ADC14MEM27 interrupt flag */
1904 /* ADC14_IFGR0[IFG28] Bits */
1905 #define ADC14_IFGR0_IFG28_OFS                    (28)                            /*!< ADC14IFG28 Bit Offset */
1906 #define ADC14_IFGR0_IFG28                        ((uint32_t)0x10000000)          /*!< ADC14MEM28 interrupt flag */
1907 /* ADC14_IFGR0[IFG29] Bits */
1908 #define ADC14_IFGR0_IFG29_OFS                    (29)                            /*!< ADC14IFG29 Bit Offset */
1909 #define ADC14_IFGR0_IFG29                        ((uint32_t)0x20000000)          /*!< ADC14MEM29 interrupt flag */
1910 /* ADC14_IFGR0[IFG30] Bits */
1911 #define ADC14_IFGR0_IFG30_OFS                    (30)                            /*!< ADC14IFG30 Bit Offset */
1912 #define ADC14_IFGR0_IFG30                        ((uint32_t)0x40000000)          /*!< ADC14MEM30 interrupt flag */
1913 /* ADC14_IFGR0[IFG31] Bits */
1914 #define ADC14_IFGR0_IFG31_OFS                    (31)                            /*!< ADC14IFG31 Bit Offset */
1915 #define ADC14_IFGR0_IFG31                        ((uint32_t)0x80000000)          /*!< ADC14MEM31 interrupt flag */
1916 /* ADC14_IFGR1[INIFG] Bits */
1917 #define ADC14_IFGR1_INIFG_OFS                    ( 1)                            /*!< ADC14INIFG Bit Offset */
1918 #define ADC14_IFGR1_INIFG                        ((uint32_t)0x00000002)          /*!< Interrupt flag for ADC14MEMx within comparator window */
1919 /* ADC14_IFGR1[LOIFG] Bits */
1920 #define ADC14_IFGR1_LOIFG_OFS                    ( 2)                            /*!< ADC14LOIFG Bit Offset */
1921 #define ADC14_IFGR1_LOIFG                        ((uint32_t)0x00000004)          /*!< Interrupt flag for ADC14MEMx below comparator window */
1922 /* ADC14_IFGR1[HIIFG] Bits */
1923 #define ADC14_IFGR1_HIIFG_OFS                    ( 3)                            /*!< ADC14HIIFG Bit Offset */
1924 #define ADC14_IFGR1_HIIFG                        ((uint32_t)0x00000008)          /*!< Interrupt flag for ADC14MEMx above comparator window */
1925 /* ADC14_IFGR1[OVIFG] Bits */
1926 #define ADC14_IFGR1_OVIFG_OFS                    ( 4)                            /*!< ADC14OVIFG Bit Offset */
1927 #define ADC14_IFGR1_OVIFG                        ((uint32_t)0x00000010)          /*!< ADC14MEMx overflow interrupt flag */
1928 /* ADC14_IFGR1[TOVIFG] Bits */
1929 #define ADC14_IFGR1_TOVIFG_OFS                   ( 5)                            /*!< ADC14TOVIFG Bit Offset */
1930 #define ADC14_IFGR1_TOVIFG                       ((uint32_t)0x00000020)          /*!< ADC14 conversion time overflow interrupt flag */
1931 /* ADC14_IFGR1[RDYIFG] Bits */
1932 #define ADC14_IFGR1_RDYIFG_OFS                   ( 6)                            /*!< ADC14RDYIFG Bit Offset */
1933 #define ADC14_IFGR1_RDYIFG                       ((uint32_t)0x00000040)          /*!< ADC14 local buffered reference ready interrupt flag */
1934 /* ADC14_CLRIFGR0[CLRIFG0] Bits */
1935 #define ADC14_CLRIFGR0_CLRIFG0_OFS               ( 0)                            /*!< CLRADC14IFG0 Bit Offset */
1936 #define ADC14_CLRIFGR0_CLRIFG0                   ((uint32_t)0x00000001)          /*!< clear ADC14IFG0 */
1937 /* ADC14_CLRIFGR0[CLRIFG1] Bits */
1938 #define ADC14_CLRIFGR0_CLRIFG1_OFS               ( 1)                            /*!< CLRADC14IFG1 Bit Offset */
1939 #define ADC14_CLRIFGR0_CLRIFG1                   ((uint32_t)0x00000002)          /*!< clear ADC14IFG1 */
1940 /* ADC14_CLRIFGR0[CLRIFG2] Bits */
1941 #define ADC14_CLRIFGR0_CLRIFG2_OFS               ( 2)                            /*!< CLRADC14IFG2 Bit Offset */
1942 #define ADC14_CLRIFGR0_CLRIFG2                   ((uint32_t)0x00000004)          /*!< clear ADC14IFG2 */
1943 /* ADC14_CLRIFGR0[CLRIFG3] Bits */
1944 #define ADC14_CLRIFGR0_CLRIFG3_OFS               ( 3)                            /*!< CLRADC14IFG3 Bit Offset */
1945 #define ADC14_CLRIFGR0_CLRIFG3                   ((uint32_t)0x00000008)          /*!< clear ADC14IFG3 */
1946 /* ADC14_CLRIFGR0[CLRIFG4] Bits */
1947 #define ADC14_CLRIFGR0_CLRIFG4_OFS               ( 4)                            /*!< CLRADC14IFG4 Bit Offset */
1948 #define ADC14_CLRIFGR0_CLRIFG4                   ((uint32_t)0x00000010)          /*!< clear ADC14IFG4 */
1949 /* ADC14_CLRIFGR0[CLRIFG5] Bits */
1950 #define ADC14_CLRIFGR0_CLRIFG5_OFS               ( 5)                            /*!< CLRADC14IFG5 Bit Offset */
1951 #define ADC14_CLRIFGR0_CLRIFG5                   ((uint32_t)0x00000020)          /*!< clear ADC14IFG5 */
1952 /* ADC14_CLRIFGR0[CLRIFG6] Bits */
1953 #define ADC14_CLRIFGR0_CLRIFG6_OFS               ( 6)                            /*!< CLRADC14IFG6 Bit Offset */
1954 #define ADC14_CLRIFGR0_CLRIFG6                   ((uint32_t)0x00000040)          /*!< clear ADC14IFG6 */
1955 /* ADC14_CLRIFGR0[CLRIFG7] Bits */
1956 #define ADC14_CLRIFGR0_CLRIFG7_OFS               ( 7)                            /*!< CLRADC14IFG7 Bit Offset */
1957 #define ADC14_CLRIFGR0_CLRIFG7                   ((uint32_t)0x00000080)          /*!< clear ADC14IFG7 */
1958 /* ADC14_CLRIFGR0[CLRIFG8] Bits */
1959 #define ADC14_CLRIFGR0_CLRIFG8_OFS               ( 8)                            /*!< CLRADC14IFG8 Bit Offset */
1960 #define ADC14_CLRIFGR0_CLRIFG8                   ((uint32_t)0x00000100)          /*!< clear ADC14IFG8 */
1961 /* ADC14_CLRIFGR0[CLRIFG9] Bits */
1962 #define ADC14_CLRIFGR0_CLRIFG9_OFS               ( 9)                            /*!< CLRADC14IFG9 Bit Offset */
1963 #define ADC14_CLRIFGR0_CLRIFG9                   ((uint32_t)0x00000200)          /*!< clear ADC14IFG9 */
1964 /* ADC14_CLRIFGR0[CLRIFG10] Bits */
1965 #define ADC14_CLRIFGR0_CLRIFG10_OFS              (10)                            /*!< CLRADC14IFG10 Bit Offset */
1966 #define ADC14_CLRIFGR0_CLRIFG10                  ((uint32_t)0x00000400)          /*!< clear ADC14IFG10 */
1967 /* ADC14_CLRIFGR0[CLRIFG11] Bits */
1968 #define ADC14_CLRIFGR0_CLRIFG11_OFS              (11)                            /*!< CLRADC14IFG11 Bit Offset */
1969 #define ADC14_CLRIFGR0_CLRIFG11                  ((uint32_t)0x00000800)          /*!< clear ADC14IFG11 */
1970 /* ADC14_CLRIFGR0[CLRIFG12] Bits */
1971 #define ADC14_CLRIFGR0_CLRIFG12_OFS              (12)                            /*!< CLRADC14IFG12 Bit Offset */
1972 #define ADC14_CLRIFGR0_CLRIFG12                  ((uint32_t)0x00001000)          /*!< clear ADC14IFG12 */
1973 /* ADC14_CLRIFGR0[CLRIFG13] Bits */
1974 #define ADC14_CLRIFGR0_CLRIFG13_OFS              (13)                            /*!< CLRADC14IFG13 Bit Offset */
1975 #define ADC14_CLRIFGR0_CLRIFG13                  ((uint32_t)0x00002000)          /*!< clear ADC14IFG13 */
1976 /* ADC14_CLRIFGR0[CLRIFG14] Bits */
1977 #define ADC14_CLRIFGR0_CLRIFG14_OFS              (14)                            /*!< CLRADC14IFG14 Bit Offset */
1978 #define ADC14_CLRIFGR0_CLRIFG14                  ((uint32_t)0x00004000)          /*!< clear ADC14IFG14 */
1979 /* ADC14_CLRIFGR0[CLRIFG15] Bits */
1980 #define ADC14_CLRIFGR0_CLRIFG15_OFS              (15)                            /*!< CLRADC14IFG15 Bit Offset */
1981 #define ADC14_CLRIFGR0_CLRIFG15                  ((uint32_t)0x00008000)          /*!< clear ADC14IFG15 */
1982 /* ADC14_CLRIFGR0[CLRIFG16] Bits */
1983 #define ADC14_CLRIFGR0_CLRIFG16_OFS              (16)                            /*!< CLRADC14IFG16 Bit Offset */
1984 #define ADC14_CLRIFGR0_CLRIFG16                  ((uint32_t)0x00010000)          /*!< clear ADC14IFG16 */
1985 /* ADC14_CLRIFGR0[CLRIFG17] Bits */
1986 #define ADC14_CLRIFGR0_CLRIFG17_OFS              (17)                            /*!< CLRADC14IFG17 Bit Offset */
1987 #define ADC14_CLRIFGR0_CLRIFG17                  ((uint32_t)0x00020000)          /*!< clear ADC14IFG17 */
1988 /* ADC14_CLRIFGR0[CLRIFG18] Bits */
1989 #define ADC14_CLRIFGR0_CLRIFG18_OFS              (18)                            /*!< CLRADC14IFG18 Bit Offset */
1990 #define ADC14_CLRIFGR0_CLRIFG18                  ((uint32_t)0x00040000)          /*!< clear ADC14IFG18 */
1991 /* ADC14_CLRIFGR0[CLRIFG19] Bits */
1992 #define ADC14_CLRIFGR0_CLRIFG19_OFS              (19)                            /*!< CLRADC14IFG19 Bit Offset */
1993 #define ADC14_CLRIFGR0_CLRIFG19                  ((uint32_t)0x00080000)          /*!< clear ADC14IFG19 */
1994 /* ADC14_CLRIFGR0[CLRIFG20] Bits */
1995 #define ADC14_CLRIFGR0_CLRIFG20_OFS              (20)                            /*!< CLRADC14IFG20 Bit Offset */
1996 #define ADC14_CLRIFGR0_CLRIFG20                  ((uint32_t)0x00100000)          /*!< clear ADC14IFG20 */
1997 /* ADC14_CLRIFGR0[CLRIFG21] Bits */
1998 #define ADC14_CLRIFGR0_CLRIFG21_OFS              (21)                            /*!< CLRADC14IFG21 Bit Offset */
1999 #define ADC14_CLRIFGR0_CLRIFG21                  ((uint32_t)0x00200000)          /*!< clear ADC14IFG21 */
2000 /* ADC14_CLRIFGR0[CLRIFG22] Bits */
2001 #define ADC14_CLRIFGR0_CLRIFG22_OFS              (22)                            /*!< CLRADC14IFG22 Bit Offset */
2002 #define ADC14_CLRIFGR0_CLRIFG22                  ((uint32_t)0x00400000)          /*!< clear ADC14IFG22 */
2003 /* ADC14_CLRIFGR0[CLRIFG23] Bits */
2004 #define ADC14_CLRIFGR0_CLRIFG23_OFS              (23)                            /*!< CLRADC14IFG23 Bit Offset */
2005 #define ADC14_CLRIFGR0_CLRIFG23                  ((uint32_t)0x00800000)          /*!< clear ADC14IFG23 */
2006 /* ADC14_CLRIFGR0[CLRIFG24] Bits */
2007 #define ADC14_CLRIFGR0_CLRIFG24_OFS              (24)                            /*!< CLRADC14IFG24 Bit Offset */
2008 #define ADC14_CLRIFGR0_CLRIFG24                  ((uint32_t)0x01000000)          /*!< clear ADC14IFG24 */
2009 /* ADC14_CLRIFGR0[CLRIFG25] Bits */
2010 #define ADC14_CLRIFGR0_CLRIFG25_OFS              (25)                            /*!< CLRADC14IFG25 Bit Offset */
2011 #define ADC14_CLRIFGR0_CLRIFG25                  ((uint32_t)0x02000000)          /*!< clear ADC14IFG25 */
2012 /* ADC14_CLRIFGR0[CLRIFG26] Bits */
2013 #define ADC14_CLRIFGR0_CLRIFG26_OFS              (26)                            /*!< CLRADC14IFG26 Bit Offset */
2014 #define ADC14_CLRIFGR0_CLRIFG26                  ((uint32_t)0x04000000)          /*!< clear ADC14IFG26 */
2015 /* ADC14_CLRIFGR0[CLRIFG27] Bits */
2016 #define ADC14_CLRIFGR0_CLRIFG27_OFS              (27)                            /*!< CLRADC14IFG27 Bit Offset */
2017 #define ADC14_CLRIFGR0_CLRIFG27                  ((uint32_t)0x08000000)          /*!< clear ADC14IFG27 */
2018 /* ADC14_CLRIFGR0[CLRIFG28] Bits */
2019 #define ADC14_CLRIFGR0_CLRIFG28_OFS              (28)                            /*!< CLRADC14IFG28 Bit Offset */
2020 #define ADC14_CLRIFGR0_CLRIFG28                  ((uint32_t)0x10000000)          /*!< clear ADC14IFG28 */
2021 /* ADC14_CLRIFGR0[CLRIFG29] Bits */
2022 #define ADC14_CLRIFGR0_CLRIFG29_OFS              (29)                            /*!< CLRADC14IFG29 Bit Offset */
2023 #define ADC14_CLRIFGR0_CLRIFG29                  ((uint32_t)0x20000000)          /*!< clear ADC14IFG29 */
2024 /* ADC14_CLRIFGR0[CLRIFG30] Bits */
2025 #define ADC14_CLRIFGR0_CLRIFG30_OFS              (30)                            /*!< CLRADC14IFG30 Bit Offset */
2026 #define ADC14_CLRIFGR0_CLRIFG30                  ((uint32_t)0x40000000)          /*!< clear ADC14IFG30 */
2027 /* ADC14_CLRIFGR0[CLRIFG31] Bits */
2028 #define ADC14_CLRIFGR0_CLRIFG31_OFS              (31)                            /*!< CLRADC14IFG31 Bit Offset */
2029 #define ADC14_CLRIFGR0_CLRIFG31                  ((uint32_t)0x80000000)          /*!< clear ADC14IFG31 */
2030 /* ADC14_CLRIFGR1[CLRINIFG] Bits */
2031 #define ADC14_CLRIFGR1_CLRINIFG_OFS              ( 1)                            /*!< CLRADC14INIFG Bit Offset */
2032 #define ADC14_CLRIFGR1_CLRINIFG                  ((uint32_t)0x00000002)          /*!< clear ADC14INIFG */
2033 /* ADC14_CLRIFGR1[CLRLOIFG] Bits */
2034 #define ADC14_CLRIFGR1_CLRLOIFG_OFS              ( 2)                            /*!< CLRADC14LOIFG Bit Offset */
2035 #define ADC14_CLRIFGR1_CLRLOIFG                  ((uint32_t)0x00000004)          /*!< clear ADC14LOIFG */
2036 /* ADC14_CLRIFGR1[CLRHIIFG] Bits */
2037 #define ADC14_CLRIFGR1_CLRHIIFG_OFS              ( 3)                            /*!< CLRADC14HIIFG Bit Offset */
2038 #define ADC14_CLRIFGR1_CLRHIIFG                  ((uint32_t)0x00000008)          /*!< clear ADC14HIIFG */
2039 /* ADC14_CLRIFGR1[CLROVIFG] Bits */
2040 #define ADC14_CLRIFGR1_CLROVIFG_OFS              ( 4)                            /*!< CLRADC14OVIFG Bit Offset */
2041 #define ADC14_CLRIFGR1_CLROVIFG                  ((uint32_t)0x00000010)          /*!< clear ADC14OVIFG */
2042 /* ADC14_CLRIFGR1[CLRTOVIFG] Bits */
2043 #define ADC14_CLRIFGR1_CLRTOVIFG_OFS             ( 5)                            /*!< CLRADC14TOVIFG Bit Offset */
2044 #define ADC14_CLRIFGR1_CLRTOVIFG                 ((uint32_t)0x00000020)          /*!< clear ADC14TOVIFG */
2045 /* ADC14_CLRIFGR1[CLRRDYIFG] Bits */
2046 #define ADC14_CLRIFGR1_CLRRDYIFG_OFS             ( 6)                            /*!< CLRADC14RDYIFG Bit Offset */
2047 #define ADC14_CLRIFGR1_CLRRDYIFG                 ((uint32_t)0x00000040)          /*!< clear ADC14RDYIFG */
2048 
2049 /******************************************************************************
2050 * AES256 Bits
2051 ******************************************************************************/
2052 /* AES256_CTL0[OP] Bits */
2053 #define AES256_CTL0_OP_OFS                       ( 0)                            /*!< AESOPx Bit Offset */
2054 #define AES256_CTL0_OP_MASK                      ((uint16_t)0x0003)              /*!< AESOPx Bit Mask */
2055 #define AES256_CTL0_OP0                          ((uint16_t)0x0001)              /*!< OP Bit 0 */
2056 #define AES256_CTL0_OP1                          ((uint16_t)0x0002)              /*!< OP Bit 1 */
2057 #define AES256_CTL0_OP_0                         ((uint16_t)0x0000)              /*!< Encryption */
2058 #define AES256_CTL0_OP_1                         ((uint16_t)0x0001)              /*!< Decryption. The provided key is the same key used for encryption */
2059 #define AES256_CTL0_OP_2                         ((uint16_t)0x0002)              /*!< Generate first round key required for decryption */
2060 #define AES256_CTL0_OP_3                         ((uint16_t)0x0003)              /*!< Decryption. The provided key is the first round key required for decryption */
2061 /* AES256_CTL0[KL] Bits */
2062 #define AES256_CTL0_KL_OFS                       ( 2)                            /*!< AESKLx Bit Offset */
2063 #define AES256_CTL0_KL_MASK                      ((uint16_t)0x000C)              /*!< AESKLx Bit Mask */
2064 #define AES256_CTL0_KL0                          ((uint16_t)0x0004)              /*!< KL Bit 0 */
2065 #define AES256_CTL0_KL1                          ((uint16_t)0x0008)              /*!< KL Bit 1 */
2066 #define AES256_CTL0_KL_0                         ((uint16_t)0x0000)              /*!< AES128. The key size is 128 bit */
2067 #define AES256_CTL0_KL_1                         ((uint16_t)0x0004)              /*!< AES192. The key size is 192 bit. */
2068 #define AES256_CTL0_KL_2                         ((uint16_t)0x0008)              /*!< AES256. The key size is 256 bit */
2069 #define AES256_CTL0_KL__128BIT                   ((uint16_t)0x0000)              /*!< AES128. The key size is 128 bit */
2070 #define AES256_CTL0_KL__192BIT                   ((uint16_t)0x0004)              /*!< AES192. The key size is 192 bit. */
2071 #define AES256_CTL0_KL__256BIT                   ((uint16_t)0x0008)              /*!< AES256. The key size is 256 bit */
2072 /* AES256_CTL0[CM] Bits */
2073 #define AES256_CTL0_CM_OFS                       ( 5)                            /*!< AESCMx Bit Offset */
2074 #define AES256_CTL0_CM_MASK                      ((uint16_t)0x0060)              /*!< AESCMx Bit Mask */
2075 #define AES256_CTL0_CM0                          ((uint16_t)0x0020)              /*!< CM Bit 0 */
2076 #define AES256_CTL0_CM1                          ((uint16_t)0x0040)              /*!< CM Bit 1 */
2077 #define AES256_CTL0_CM_0                         ((uint16_t)0x0000)              /*!< ECB */
2078 #define AES256_CTL0_CM_1                         ((uint16_t)0x0020)              /*!< CBC */
2079 #define AES256_CTL0_CM_2                         ((uint16_t)0x0040)              /*!< OFB */
2080 #define AES256_CTL0_CM_3                         ((uint16_t)0x0060)              /*!< CFB */
2081 #define AES256_CTL0_CM__ECB                      ((uint16_t)0x0000)              /*!< ECB */
2082 #define AES256_CTL0_CM__CBC                      ((uint16_t)0x0020)              /*!< CBC */
2083 #define AES256_CTL0_CM__OFB                      ((uint16_t)0x0040)              /*!< OFB */
2084 #define AES256_CTL0_CM__CFB                      ((uint16_t)0x0060)              /*!< CFB */
2085 /* AES256_CTL0[SWRST] Bits */
2086 #define AES256_CTL0_SWRST_OFS                    ( 7)                            /*!< AESSWRST Bit Offset */
2087 #define AES256_CTL0_SWRST                        ((uint16_t)0x0080)              /*!< AES software reset */
2088 /* AES256_CTL0[RDYIFG] Bits */
2089 #define AES256_CTL0_RDYIFG_OFS                   ( 8)                            /*!< AESRDYIFG Bit Offset */
2090 #define AES256_CTL0_RDYIFG                       ((uint16_t)0x0100)              /*!< AES ready interrupt flag */
2091 /* AES256_CTL0[ERRFG] Bits */
2092 #define AES256_CTL0_ERRFG_OFS                    (11)                            /*!< AESERRFG Bit Offset */
2093 #define AES256_CTL0_ERRFG                        ((uint16_t)0x0800)              /*!< AES error flag */
2094 /* AES256_CTL0[RDYIE] Bits */
2095 #define AES256_CTL0_RDYIE_OFS                    (12)                            /*!< AESRDYIE Bit Offset */
2096 #define AES256_CTL0_RDYIE                        ((uint16_t)0x1000)              /*!< AES ready interrupt enable */
2097 /* AES256_CTL0[CMEN] Bits */
2098 #define AES256_CTL0_CMEN_OFS                     (15)                            /*!< AESCMEN Bit Offset */
2099 #define AES256_CTL0_CMEN                         ((uint16_t)0x8000)              /*!< AES cipher mode enable */
2100 /* AES256_CTL1[BLKCNT] Bits */
2101 #define AES256_CTL1_BLKCNT_OFS                   ( 0)                            /*!< AESBLKCNTx Bit Offset */
2102 #define AES256_CTL1_BLKCNT_MASK                  ((uint16_t)0x00FF)              /*!< AESBLKCNTx Bit Mask */
2103 #define AES256_CTL1_BLKCNT0                      ((uint16_t)0x0001)              /*!< BLKCNT Bit 0 */
2104 #define AES256_CTL1_BLKCNT1                      ((uint16_t)0x0002)              /*!< BLKCNT Bit 1 */
2105 #define AES256_CTL1_BLKCNT2                      ((uint16_t)0x0004)              /*!< BLKCNT Bit 2 */
2106 #define AES256_CTL1_BLKCNT3                      ((uint16_t)0x0008)              /*!< BLKCNT Bit 3 */
2107 #define AES256_CTL1_BLKCNT4                      ((uint16_t)0x0010)              /*!< BLKCNT Bit 4 */
2108 #define AES256_CTL1_BLKCNT5                      ((uint16_t)0x0020)              /*!< BLKCNT Bit 5 */
2109 #define AES256_CTL1_BLKCNT6                      ((uint16_t)0x0040)              /*!< BLKCNT Bit 6 */
2110 #define AES256_CTL1_BLKCNT7                      ((uint16_t)0x0080)              /*!< BLKCNT Bit 7 */
2111 /* AES256_STAT[BUSY] Bits */
2112 #define AES256_STAT_BUSY_OFS                     ( 0)                            /*!< AESBUSY Bit Offset */
2113 #define AES256_STAT_BUSY                         ((uint16_t)0x0001)              /*!< AES accelerator module busy */
2114 /* AES256_STAT[KEYWR] Bits */
2115 #define AES256_STAT_KEYWR_OFS                    ( 1)                            /*!< AESKEYWR Bit Offset */
2116 #define AES256_STAT_KEYWR                        ((uint16_t)0x0002)              /*!< All 16 bytes written to AESAKEY */
2117 /* AES256_STAT[DINWR] Bits */
2118 #define AES256_STAT_DINWR_OFS                    ( 2)                            /*!< AESDINWR Bit Offset */
2119 #define AES256_STAT_DINWR                        ((uint16_t)0x0004)              /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */
2120 /* AES256_STAT[DOUTRD] Bits */
2121 #define AES256_STAT_DOUTRD_OFS                   ( 3)                            /*!< AESDOUTRD Bit Offset */
2122 #define AES256_STAT_DOUTRD                       ((uint16_t)0x0008)              /*!< All 16 bytes read from AESADOUT */
2123 /* AES256_STAT[KEYCNT] Bits */
2124 #define AES256_STAT_KEYCNT_OFS                   ( 4)                            /*!< AESKEYCNTx Bit Offset */
2125 #define AES256_STAT_KEYCNT_MASK                  ((uint16_t)0x00F0)              /*!< AESKEYCNTx Bit Mask */
2126 #define AES256_STAT_KEYCNT0                      ((uint16_t)0x0010)              /*!< KEYCNT Bit 0 */
2127 #define AES256_STAT_KEYCNT1                      ((uint16_t)0x0020)              /*!< KEYCNT Bit 1 */
2128 #define AES256_STAT_KEYCNT2                      ((uint16_t)0x0040)              /*!< KEYCNT Bit 2 */
2129 #define AES256_STAT_KEYCNT3                      ((uint16_t)0x0080)              /*!< KEYCNT Bit 3 */
2130 /* AES256_STAT[DINCNT] Bits */
2131 #define AES256_STAT_DINCNT_OFS                   ( 8)                            /*!< AESDINCNTx Bit Offset */
2132 #define AES256_STAT_DINCNT_MASK                  ((uint16_t)0x0F00)              /*!< AESDINCNTx Bit Mask */
2133 #define AES256_STAT_DINCNT0                      ((uint16_t)0x0100)              /*!< DINCNT Bit 0 */
2134 #define AES256_STAT_DINCNT1                      ((uint16_t)0x0200)              /*!< DINCNT Bit 1 */
2135 #define AES256_STAT_DINCNT2                      ((uint16_t)0x0400)              /*!< DINCNT Bit 2 */
2136 #define AES256_STAT_DINCNT3                      ((uint16_t)0x0800)              /*!< DINCNT Bit 3 */
2137 /* AES256_STAT[DOUTCNT] Bits */
2138 #define AES256_STAT_DOUTCNT_OFS                  (12)                            /*!< AESDOUTCNTx Bit Offset */
2139 #define AES256_STAT_DOUTCNT_MASK                 ((uint16_t)0xF000)              /*!< AESDOUTCNTx Bit Mask */
2140 #define AES256_STAT_DOUTCNT0                     ((uint16_t)0x1000)              /*!< DOUTCNT Bit 0 */
2141 #define AES256_STAT_DOUTCNT1                     ((uint16_t)0x2000)              /*!< DOUTCNT Bit 1 */
2142 #define AES256_STAT_DOUTCNT2                     ((uint16_t)0x4000)              /*!< DOUTCNT Bit 2 */
2143 #define AES256_STAT_DOUTCNT3                     ((uint16_t)0x8000)              /*!< DOUTCNT Bit 3 */
2144 /* AES256_KEY[KEY0] Bits */
2145 #define AES256_KEY_KEY0_OFS                      ( 0)                            /*!< AESKEY0x Bit Offset */
2146 #define AES256_KEY_KEY0_MASK                     ((uint16_t)0x00FF)              /*!< AESKEY0x Bit Mask */
2147 #define AES256_KEY_KEY00                         ((uint16_t)0x0001)              /*!< KEY0 Bit 0 */
2148 #define AES256_KEY_KEY01                         ((uint16_t)0x0002)              /*!< KEY0 Bit 1 */
2149 #define AES256_KEY_KEY02                         ((uint16_t)0x0004)              /*!< KEY0 Bit 2 */
2150 #define AES256_KEY_KEY03                         ((uint16_t)0x0008)              /*!< KEY0 Bit 3 */
2151 #define AES256_KEY_KEY04                         ((uint16_t)0x0010)              /*!< KEY0 Bit 4 */
2152 #define AES256_KEY_KEY05                         ((uint16_t)0x0020)              /*!< KEY0 Bit 5 */
2153 #define AES256_KEY_KEY06                         ((uint16_t)0x0040)              /*!< KEY0 Bit 6 */
2154 #define AES256_KEY_KEY07                         ((uint16_t)0x0080)              /*!< KEY0 Bit 7 */
2155 /* AES256_KEY[KEY1] Bits */
2156 #define AES256_KEY_KEY1_OFS                      ( 8)                            /*!< AESKEY1x Bit Offset */
2157 #define AES256_KEY_KEY1_MASK                     ((uint16_t)0xFF00)              /*!< AESKEY1x Bit Mask */
2158 #define AES256_KEY_KEY10                         ((uint16_t)0x0100)              /*!< KEY1 Bit 0 */
2159 #define AES256_KEY_KEY11                         ((uint16_t)0x0200)              /*!< KEY1 Bit 1 */
2160 #define AES256_KEY_KEY12                         ((uint16_t)0x0400)              /*!< KEY1 Bit 2 */
2161 #define AES256_KEY_KEY13                         ((uint16_t)0x0800)              /*!< KEY1 Bit 3 */
2162 #define AES256_KEY_KEY14                         ((uint16_t)0x1000)              /*!< KEY1 Bit 4 */
2163 #define AES256_KEY_KEY15                         ((uint16_t)0x2000)              /*!< KEY1 Bit 5 */
2164 #define AES256_KEY_KEY16                         ((uint16_t)0x4000)              /*!< KEY1 Bit 6 */
2165 #define AES256_KEY_KEY17                         ((uint16_t)0x8000)              /*!< KEY1 Bit 7 */
2166 /* AES256_DIN[DIN0] Bits */
2167 #define AES256_DIN_DIN0_OFS                      ( 0)                            /*!< AESDIN0x Bit Offset */
2168 #define AES256_DIN_DIN0_MASK                     ((uint16_t)0x00FF)              /*!< AESDIN0x Bit Mask */
2169 #define AES256_DIN_DIN00                         ((uint16_t)0x0001)              /*!< DIN0 Bit 0 */
2170 #define AES256_DIN_DIN01                         ((uint16_t)0x0002)              /*!< DIN0 Bit 1 */
2171 #define AES256_DIN_DIN02                         ((uint16_t)0x0004)              /*!< DIN0 Bit 2 */
2172 #define AES256_DIN_DIN03                         ((uint16_t)0x0008)              /*!< DIN0 Bit 3 */
2173 #define AES256_DIN_DIN04                         ((uint16_t)0x0010)              /*!< DIN0 Bit 4 */
2174 #define AES256_DIN_DIN05                         ((uint16_t)0x0020)              /*!< DIN0 Bit 5 */
2175 #define AES256_DIN_DIN06                         ((uint16_t)0x0040)              /*!< DIN0 Bit 6 */
2176 #define AES256_DIN_DIN07                         ((uint16_t)0x0080)              /*!< DIN0 Bit 7 */
2177 /* AES256_DIN[DIN1] Bits */
2178 #define AES256_DIN_DIN1_OFS                      ( 8)                            /*!< AESDIN1x Bit Offset */
2179 #define AES256_DIN_DIN1_MASK                     ((uint16_t)0xFF00)              /*!< AESDIN1x Bit Mask */
2180 #define AES256_DIN_DIN10                         ((uint16_t)0x0100)              /*!< DIN1 Bit 0 */
2181 #define AES256_DIN_DIN11                         ((uint16_t)0x0200)              /*!< DIN1 Bit 1 */
2182 #define AES256_DIN_DIN12                         ((uint16_t)0x0400)              /*!< DIN1 Bit 2 */
2183 #define AES256_DIN_DIN13                         ((uint16_t)0x0800)              /*!< DIN1 Bit 3 */
2184 #define AES256_DIN_DIN14                         ((uint16_t)0x1000)              /*!< DIN1 Bit 4 */
2185 #define AES256_DIN_DIN15                         ((uint16_t)0x2000)              /*!< DIN1 Bit 5 */
2186 #define AES256_DIN_DIN16                         ((uint16_t)0x4000)              /*!< DIN1 Bit 6 */
2187 #define AES256_DIN_DIN17                         ((uint16_t)0x8000)              /*!< DIN1 Bit 7 */
2188 /* AES256_DOUT[DOUT0] Bits */
2189 #define AES256_DOUT_DOUT0_OFS                    ( 0)                            /*!< AESDOUT0x Bit Offset */
2190 #define AES256_DOUT_DOUT0_MASK                   ((uint16_t)0x00FF)              /*!< AESDOUT0x Bit Mask */
2191 #define AES256_DOUT_DOUT00                       ((uint16_t)0x0001)              /*!< DOUT0 Bit 0 */
2192 #define AES256_DOUT_DOUT01                       ((uint16_t)0x0002)              /*!< DOUT0 Bit 1 */
2193 #define AES256_DOUT_DOUT02                       ((uint16_t)0x0004)              /*!< DOUT0 Bit 2 */
2194 #define AES256_DOUT_DOUT03                       ((uint16_t)0x0008)              /*!< DOUT0 Bit 3 */
2195 #define AES256_DOUT_DOUT04                       ((uint16_t)0x0010)              /*!< DOUT0 Bit 4 */
2196 #define AES256_DOUT_DOUT05                       ((uint16_t)0x0020)              /*!< DOUT0 Bit 5 */
2197 #define AES256_DOUT_DOUT06                       ((uint16_t)0x0040)              /*!< DOUT0 Bit 6 */
2198 #define AES256_DOUT_DOUT07                       ((uint16_t)0x0080)              /*!< DOUT0 Bit 7 */
2199 /* AES256_DOUT[DOUT1] Bits */
2200 #define AES256_DOUT_DOUT1_OFS                    ( 8)                            /*!< AESDOUT1x Bit Offset */
2201 #define AES256_DOUT_DOUT1_MASK                   ((uint16_t)0xFF00)              /*!< AESDOUT1x Bit Mask */
2202 #define AES256_DOUT_DOUT10                       ((uint16_t)0x0100)              /*!< DOUT1 Bit 0 */
2203 #define AES256_DOUT_DOUT11                       ((uint16_t)0x0200)              /*!< DOUT1 Bit 1 */
2204 #define AES256_DOUT_DOUT12                       ((uint16_t)0x0400)              /*!< DOUT1 Bit 2 */
2205 #define AES256_DOUT_DOUT13                       ((uint16_t)0x0800)              /*!< DOUT1 Bit 3 */
2206 #define AES256_DOUT_DOUT14                       ((uint16_t)0x1000)              /*!< DOUT1 Bit 4 */
2207 #define AES256_DOUT_DOUT15                       ((uint16_t)0x2000)              /*!< DOUT1 Bit 5 */
2208 #define AES256_DOUT_DOUT16                       ((uint16_t)0x4000)              /*!< DOUT1 Bit 6 */
2209 #define AES256_DOUT_DOUT17                       ((uint16_t)0x8000)              /*!< DOUT1 Bit 7 */
2210 /* AES256_XDIN[XDIN0] Bits */
2211 #define AES256_XDIN_XDIN0_OFS                    ( 0)                            /*!< AESXDIN0x Bit Offset */
2212 #define AES256_XDIN_XDIN0_MASK                   ((uint16_t)0x00FF)              /*!< AESXDIN0x Bit Mask */
2213 #define AES256_XDIN_XDIN00                       ((uint16_t)0x0001)              /*!< XDIN0 Bit 0 */
2214 #define AES256_XDIN_XDIN01                       ((uint16_t)0x0002)              /*!< XDIN0 Bit 1 */
2215 #define AES256_XDIN_XDIN02                       ((uint16_t)0x0004)              /*!< XDIN0 Bit 2 */
2216 #define AES256_XDIN_XDIN03                       ((uint16_t)0x0008)              /*!< XDIN0 Bit 3 */
2217 #define AES256_XDIN_XDIN04                       ((uint16_t)0x0010)              /*!< XDIN0 Bit 4 */
2218 #define AES256_XDIN_XDIN05                       ((uint16_t)0x0020)              /*!< XDIN0 Bit 5 */
2219 #define AES256_XDIN_XDIN06                       ((uint16_t)0x0040)              /*!< XDIN0 Bit 6 */
2220 #define AES256_XDIN_XDIN07                       ((uint16_t)0x0080)              /*!< XDIN0 Bit 7 */
2221 /* AES256_XDIN[XDIN1] Bits */
2222 #define AES256_XDIN_XDIN1_OFS                    ( 8)                            /*!< AESXDIN1x Bit Offset */
2223 #define AES256_XDIN_XDIN1_MASK                   ((uint16_t)0xFF00)              /*!< AESXDIN1x Bit Mask */
2224 #define AES256_XDIN_XDIN10                       ((uint16_t)0x0100)              /*!< XDIN1 Bit 0 */
2225 #define AES256_XDIN_XDIN11                       ((uint16_t)0x0200)              /*!< XDIN1 Bit 1 */
2226 #define AES256_XDIN_XDIN12                       ((uint16_t)0x0400)              /*!< XDIN1 Bit 2 */
2227 #define AES256_XDIN_XDIN13                       ((uint16_t)0x0800)              /*!< XDIN1 Bit 3 */
2228 #define AES256_XDIN_XDIN14                       ((uint16_t)0x1000)              /*!< XDIN1 Bit 4 */
2229 #define AES256_XDIN_XDIN15                       ((uint16_t)0x2000)              /*!< XDIN1 Bit 5 */
2230 #define AES256_XDIN_XDIN16                       ((uint16_t)0x4000)              /*!< XDIN1 Bit 6 */
2231 #define AES256_XDIN_XDIN17                       ((uint16_t)0x8000)              /*!< XDIN1 Bit 7 */
2232 /* AES256_XIN[XIN0] Bits */
2233 #define AES256_XIN_XIN0_OFS                      ( 0)                            /*!< AESXIN0x Bit Offset */
2234 #define AES256_XIN_XIN0_MASK                     ((uint16_t)0x00FF)              /*!< AESXIN0x Bit Mask */
2235 #define AES256_XIN_XIN00                         ((uint16_t)0x0001)              /*!< XIN0 Bit 0 */
2236 #define AES256_XIN_XIN01                         ((uint16_t)0x0002)              /*!< XIN0 Bit 1 */
2237 #define AES256_XIN_XIN02                         ((uint16_t)0x0004)              /*!< XIN0 Bit 2 */
2238 #define AES256_XIN_XIN03                         ((uint16_t)0x0008)              /*!< XIN0 Bit 3 */
2239 #define AES256_XIN_XIN04                         ((uint16_t)0x0010)              /*!< XIN0 Bit 4 */
2240 #define AES256_XIN_XIN05                         ((uint16_t)0x0020)              /*!< XIN0 Bit 5 */
2241 #define AES256_XIN_XIN06                         ((uint16_t)0x0040)              /*!< XIN0 Bit 6 */
2242 #define AES256_XIN_XIN07                         ((uint16_t)0x0080)              /*!< XIN0 Bit 7 */
2243 /* AES256_XIN[XIN1] Bits */
2244 #define AES256_XIN_XIN1_OFS                      ( 8)                            /*!< AESXIN1x Bit Offset */
2245 #define AES256_XIN_XIN1_MASK                     ((uint16_t)0xFF00)              /*!< AESXIN1x Bit Mask */
2246 #define AES256_XIN_XIN10                         ((uint16_t)0x0100)              /*!< XIN1 Bit 0 */
2247 #define AES256_XIN_XIN11                         ((uint16_t)0x0200)              /*!< XIN1 Bit 1 */
2248 #define AES256_XIN_XIN12                         ((uint16_t)0x0400)              /*!< XIN1 Bit 2 */
2249 #define AES256_XIN_XIN13                         ((uint16_t)0x0800)              /*!< XIN1 Bit 3 */
2250 #define AES256_XIN_XIN14                         ((uint16_t)0x1000)              /*!< XIN1 Bit 4 */
2251 #define AES256_XIN_XIN15                         ((uint16_t)0x2000)              /*!< XIN1 Bit 5 */
2252 #define AES256_XIN_XIN16                         ((uint16_t)0x4000)              /*!< XIN1 Bit 6 */
2253 #define AES256_XIN_XIN17                         ((uint16_t)0x8000)              /*!< XIN1 Bit 7 */
2254 
2255 /******************************************************************************
2256 * CAPTIO Bits
2257 ******************************************************************************/
2258 /* CAPTIO_CTL[PISEL] Bits */
2259 #define CAPTIO_CTL_PISEL_OFS                     ( 1)                            /*!< CAPTIOPISELx Bit Offset */
2260 #define CAPTIO_CTL_PISEL_MASK                    ((uint16_t)0x000E)              /*!< CAPTIOPISELx Bit Mask */
2261 #define CAPTIO_CTL_PISEL0                        ((uint16_t)0x0002)              /*!< PISEL Bit 0 */
2262 #define CAPTIO_CTL_PISEL1                        ((uint16_t)0x0004)              /*!< PISEL Bit 1 */
2263 #define CAPTIO_CTL_PISEL2                        ((uint16_t)0x0008)              /*!< PISEL Bit 2 */
2264 #define CAPTIO_CTL_PISEL_0                       ((uint16_t)0x0000)              /*!< Px.0 */
2265 #define CAPTIO_CTL_PISEL_1                       ((uint16_t)0x0002)              /*!< Px.1 */
2266 #define CAPTIO_CTL_PISEL_2                       ((uint16_t)0x0004)              /*!< Px.2 */
2267 #define CAPTIO_CTL_PISEL_3                       ((uint16_t)0x0006)              /*!< Px.3 */
2268 #define CAPTIO_CTL_PISEL_4                       ((uint16_t)0x0008)              /*!< Px.4 */
2269 #define CAPTIO_CTL_PISEL_5                       ((uint16_t)0x000A)              /*!< Px.5 */
2270 #define CAPTIO_CTL_PISEL_6                       ((uint16_t)0x000C)              /*!< Px.6 */
2271 #define CAPTIO_CTL_PISEL_7                       ((uint16_t)0x000E)              /*!< Px.7 */
2272 /* CAPTIO_CTL[POSEL] Bits */
2273 #define CAPTIO_CTL_POSEL_OFS                     ( 4)                            /*!< CAPTIOPOSELx Bit Offset */
2274 #define CAPTIO_CTL_POSEL_MASK                    ((uint16_t)0x00F0)              /*!< CAPTIOPOSELx Bit Mask */
2275 #define CAPTIO_CTL_POSEL0                        ((uint16_t)0x0010)              /*!< POSEL Bit 0 */
2276 #define CAPTIO_CTL_POSEL1                        ((uint16_t)0x0020)              /*!< POSEL Bit 1 */
2277 #define CAPTIO_CTL_POSEL2                        ((uint16_t)0x0040)              /*!< POSEL Bit 2 */
2278 #define CAPTIO_CTL_POSEL3                        ((uint16_t)0x0080)              /*!< POSEL Bit 3 */
2279 #define CAPTIO_CTL_POSEL_0                       ((uint16_t)0x0000)              /*!< Px = PJ */
2280 #define CAPTIO_CTL_POSEL_1                       ((uint16_t)0x0010)              /*!< Px = P1 */
2281 #define CAPTIO_CTL_POSEL_2                       ((uint16_t)0x0020)              /*!< Px = P2 */
2282 #define CAPTIO_CTL_POSEL_3                       ((uint16_t)0x0030)              /*!< Px = P3 */
2283 #define CAPTIO_CTL_POSEL_4                       ((uint16_t)0x0040)              /*!< Px = P4 */
2284 #define CAPTIO_CTL_POSEL_5                       ((uint16_t)0x0050)              /*!< Px = P5 */
2285 #define CAPTIO_CTL_POSEL_6                       ((uint16_t)0x0060)              /*!< Px = P6 */
2286 #define CAPTIO_CTL_POSEL_7                       ((uint16_t)0x0070)              /*!< Px = P7 */
2287 #define CAPTIO_CTL_POSEL_8                       ((uint16_t)0x0080)              /*!< Px = P8 */
2288 #define CAPTIO_CTL_POSEL_9                       ((uint16_t)0x0090)              /*!< Px = P9 */
2289 #define CAPTIO_CTL_POSEL_10                      ((uint16_t)0x00A0)              /*!< Px = P10 */
2290 #define CAPTIO_CTL_POSEL_11                      ((uint16_t)0x00B0)              /*!< Px = P11 */
2291 #define CAPTIO_CTL_POSEL_12                      ((uint16_t)0x00C0)              /*!< Px = P12 */
2292 #define CAPTIO_CTL_POSEL_13                      ((uint16_t)0x00D0)              /*!< Px = P13 */
2293 #define CAPTIO_CTL_POSEL_14                      ((uint16_t)0x00E0)              /*!< Px = P14 */
2294 #define CAPTIO_CTL_POSEL_15                      ((uint16_t)0x00F0)              /*!< Px = P15 */
2295 #define CAPTIO_CTL_POSEL__PJ                     ((uint16_t)0x0000)              /*!< Px = PJ */
2296 #define CAPTIO_CTL_POSEL__P1                     ((uint16_t)0x0010)              /*!< Px = P1 */
2297 #define CAPTIO_CTL_POSEL__P2                     ((uint16_t)0x0020)              /*!< Px = P2 */
2298 #define CAPTIO_CTL_POSEL__P3                     ((uint16_t)0x0030)              /*!< Px = P3 */
2299 #define CAPTIO_CTL_POSEL__P4                     ((uint16_t)0x0040)              /*!< Px = P4 */
2300 #define CAPTIO_CTL_POSEL__P5                     ((uint16_t)0x0050)              /*!< Px = P5 */
2301 #define CAPTIO_CTL_POSEL__P6                     ((uint16_t)0x0060)              /*!< Px = P6 */
2302 #define CAPTIO_CTL_POSEL__P7                     ((uint16_t)0x0070)              /*!< Px = P7 */
2303 #define CAPTIO_CTL_POSEL__P8                     ((uint16_t)0x0080)              /*!< Px = P8 */
2304 #define CAPTIO_CTL_POSEL__P9                     ((uint16_t)0x0090)              /*!< Px = P9 */
2305 #define CAPTIO_CTL_POSEL__P10                    ((uint16_t)0x00A0)              /*!< Px = P10 */
2306 #define CAPTIO_CTL_POSEL__P11                    ((uint16_t)0x00B0)              /*!< Px = P11 */
2307 #define CAPTIO_CTL_POSEL__P12                    ((uint16_t)0x00C0)              /*!< Px = P12 */
2308 #define CAPTIO_CTL_POSEL__P13                    ((uint16_t)0x00D0)              /*!< Px = P13 */
2309 #define CAPTIO_CTL_POSEL__P14                    ((uint16_t)0x00E0)              /*!< Px = P14 */
2310 #define CAPTIO_CTL_POSEL__P15                    ((uint16_t)0x00F0)              /*!< Px = P15 */
2311 /* CAPTIO_CTL[EN] Bits */
2312 #define CAPTIO_CTL_EN_OFS                        ( 8)                            /*!< CAPTIOEN Bit Offset */
2313 #define CAPTIO_CTL_EN                            ((uint16_t)0x0100)              /*!< Capacitive Touch IO enable */
2314 /* CAPTIO_CTL[STATE] Bits */
2315 #define CAPTIO_CTL_STATE_OFS                     ( 9)                            /*!< CAPTIOSTATE Bit Offset */
2316 #define CAPTIO_CTL_STATE                         ((uint16_t)0x0200)              /*!< Capacitive Touch IO state */
2317 
2318 /******************************************************************************
2319 * COMP_E Bits
2320 ******************************************************************************/
2321 /* COMP_E_CTL0[IPSEL] Bits */
2322 #define COMP_E_CTL0_IPSEL_OFS                    ( 0)                            /*!< CEIPSEL Bit Offset */
2323 #define COMP_E_CTL0_IPSEL_MASK                   ((uint16_t)0x000F)              /*!< CEIPSEL Bit Mask */
2324 #define COMP_E_CTL0_IPSEL0                       ((uint16_t)0x0001)              /*!< IPSEL Bit 0 */
2325 #define COMP_E_CTL0_IPSEL1                       ((uint16_t)0x0002)              /*!< IPSEL Bit 1 */
2326 #define COMP_E_CTL0_IPSEL2                       ((uint16_t)0x0004)              /*!< IPSEL Bit 2 */
2327 #define COMP_E_CTL0_IPSEL3                       ((uint16_t)0x0008)              /*!< IPSEL Bit 3 */
2328 #define COMP_E_CTL0_IPSEL_0                      ((uint16_t)0x0000)              /*!< Channel 0 selected */
2329 #define COMP_E_CTL0_IPSEL_1                      ((uint16_t)0x0001)              /*!< Channel 1 selected */
2330 #define COMP_E_CTL0_IPSEL_2                      ((uint16_t)0x0002)              /*!< Channel 2 selected */
2331 #define COMP_E_CTL0_IPSEL_3                      ((uint16_t)0x0003)              /*!< Channel 3 selected */
2332 #define COMP_E_CTL0_IPSEL_4                      ((uint16_t)0x0004)              /*!< Channel 4 selected */
2333 #define COMP_E_CTL0_IPSEL_5                      ((uint16_t)0x0005)              /*!< Channel 5 selected */
2334 #define COMP_E_CTL0_IPSEL_6                      ((uint16_t)0x0006)              /*!< Channel 6 selected */
2335 #define COMP_E_CTL0_IPSEL_7                      ((uint16_t)0x0007)              /*!< Channel 7 selected */
2336 #define COMP_E_CTL0_IPSEL_8                      ((uint16_t)0x0008)              /*!< Channel 8 selected */
2337 #define COMP_E_CTL0_IPSEL_9                      ((uint16_t)0x0009)              /*!< Channel 9 selected */
2338 #define COMP_E_CTL0_IPSEL_10                     ((uint16_t)0x000A)              /*!< Channel 10 selected */
2339 #define COMP_E_CTL0_IPSEL_11                     ((uint16_t)0x000B)              /*!< Channel 11 selected */
2340 #define COMP_E_CTL0_IPSEL_12                     ((uint16_t)0x000C)              /*!< Channel 12 selected */
2341 #define COMP_E_CTL0_IPSEL_13                     ((uint16_t)0x000D)              /*!< Channel 13 selected */
2342 #define COMP_E_CTL0_IPSEL_14                     ((uint16_t)0x000E)              /*!< Channel 14 selected */
2343 #define COMP_E_CTL0_IPSEL_15                     ((uint16_t)0x000F)              /*!< Channel 15 selected */
2344 /* COMP_E_CTL0[IPEN] Bits */
2345 #define COMP_E_CTL0_IPEN_OFS                     ( 7)                            /*!< CEIPEN Bit Offset */
2346 #define COMP_E_CTL0_IPEN                         ((uint16_t)0x0080)              /*!< Channel input enable for the V+ terminal */
2347 /* COMP_E_CTL0[IMSEL] Bits */
2348 #define COMP_E_CTL0_IMSEL_OFS                    ( 8)                            /*!< CEIMSEL Bit Offset */
2349 #define COMP_E_CTL0_IMSEL_MASK                   ((uint16_t)0x0F00)              /*!< CEIMSEL Bit Mask */
2350 #define COMP_E_CTL0_IMSEL0                       ((uint16_t)0x0100)              /*!< IMSEL Bit 0 */
2351 #define COMP_E_CTL0_IMSEL1                       ((uint16_t)0x0200)              /*!< IMSEL Bit 1 */
2352 #define COMP_E_CTL0_IMSEL2                       ((uint16_t)0x0400)              /*!< IMSEL Bit 2 */
2353 #define COMP_E_CTL0_IMSEL3                       ((uint16_t)0x0800)              /*!< IMSEL Bit 3 */
2354 #define COMP_E_CTL0_IMSEL_0                      ((uint16_t)0x0000)              /*!< Channel 0 selected */
2355 #define COMP_E_CTL0_IMSEL_1                      ((uint16_t)0x0100)              /*!< Channel 1 selected */
2356 #define COMP_E_CTL0_IMSEL_2                      ((uint16_t)0x0200)              /*!< Channel 2 selected */
2357 #define COMP_E_CTL0_IMSEL_3                      ((uint16_t)0x0300)              /*!< Channel 3 selected */
2358 #define COMP_E_CTL0_IMSEL_4                      ((uint16_t)0x0400)              /*!< Channel 4 selected */
2359 #define COMP_E_CTL0_IMSEL_5                      ((uint16_t)0x0500)              /*!< Channel 5 selected */
2360 #define COMP_E_CTL0_IMSEL_6                      ((uint16_t)0x0600)              /*!< Channel 6 selected */
2361 #define COMP_E_CTL0_IMSEL_7                      ((uint16_t)0x0700)              /*!< Channel 7 selected */
2362 #define COMP_E_CTL0_IMSEL_8                      ((uint16_t)0x0800)              /*!< Channel 8 selected */
2363 #define COMP_E_CTL0_IMSEL_9                      ((uint16_t)0x0900)              /*!< Channel 9 selected */
2364 #define COMP_E_CTL0_IMSEL_10                     ((uint16_t)0x0A00)              /*!< Channel 10 selected */
2365 #define COMP_E_CTL0_IMSEL_11                     ((uint16_t)0x0B00)              /*!< Channel 11 selected */
2366 #define COMP_E_CTL0_IMSEL_12                     ((uint16_t)0x0C00)              /*!< Channel 12 selected */
2367 #define COMP_E_CTL0_IMSEL_13                     ((uint16_t)0x0D00)              /*!< Channel 13 selected */
2368 #define COMP_E_CTL0_IMSEL_14                     ((uint16_t)0x0E00)              /*!< Channel 14 selected */
2369 #define COMP_E_CTL0_IMSEL_15                     ((uint16_t)0x0F00)              /*!< Channel 15 selected */
2370 /* COMP_E_CTL0[IMEN] Bits */
2371 #define COMP_E_CTL0_IMEN_OFS                     (15)                            /*!< CEIMEN Bit Offset */
2372 #define COMP_E_CTL0_IMEN                         ((uint16_t)0x8000)              /*!< Channel input enable for the - terminal */
2373 /* COMP_E_CTL1[OUT] Bits */
2374 #define COMP_E_CTL1_OUT_OFS                      ( 0)                            /*!< CEOUT Bit Offset */
2375 #define COMP_E_CTL1_OUT                          ((uint16_t)0x0001)              /*!< Comparator output value */
2376 /* COMP_E_CTL1[OUTPOL] Bits */
2377 #define COMP_E_CTL1_OUTPOL_OFS                   ( 1)                            /*!< CEOUTPOL Bit Offset */
2378 #define COMP_E_CTL1_OUTPOL                       ((uint16_t)0x0002)              /*!< Comparator output polarity */
2379 /* COMP_E_CTL1[F] Bits */
2380 #define COMP_E_CTL1_F_OFS                        ( 2)                            /*!< CEF Bit Offset */
2381 #define COMP_E_CTL1_F                            ((uint16_t)0x0004)              /*!< Comparator output filter */
2382 /* COMP_E_CTL1[IES] Bits */
2383 #define COMP_E_CTL1_IES_OFS                      ( 3)                            /*!< CEIES Bit Offset */
2384 #define COMP_E_CTL1_IES                          ((uint16_t)0x0008)              /*!< Interrupt edge select for CEIIFG and CEIFG */
2385 /* COMP_E_CTL1[SHORT] Bits */
2386 #define COMP_E_CTL1_SHORT_OFS                    ( 4)                            /*!< CESHORT Bit Offset */
2387 #define COMP_E_CTL1_SHORT                        ((uint16_t)0x0010)              /*!< Input short */
2388 /* COMP_E_CTL1[EX] Bits */
2389 #define COMP_E_CTL1_EX_OFS                       ( 5)                            /*!< CEEX Bit Offset */
2390 #define COMP_E_CTL1_EX                           ((uint16_t)0x0020)              /*!< Exchange */
2391 /* COMP_E_CTL1[FDLY] Bits */
2392 #define COMP_E_CTL1_FDLY_OFS                     ( 6)                            /*!< CEFDLY Bit Offset */
2393 #define COMP_E_CTL1_FDLY_MASK                    ((uint16_t)0x00C0)              /*!< CEFDLY Bit Mask */
2394 #define COMP_E_CTL1_FDLY0                        ((uint16_t)0x0040)              /*!< FDLY Bit 0 */
2395 #define COMP_E_CTL1_FDLY1                        ((uint16_t)0x0080)              /*!< FDLY Bit 1 */
2396 #define COMP_E_CTL1_FDLY_0                       ((uint16_t)0x0000)              /*!< Typical filter delay of TBD (450) ns */
2397 #define COMP_E_CTL1_FDLY_1                       ((uint16_t)0x0040)              /*!< Typical filter delay of TBD (900) ns */
2398 #define COMP_E_CTL1_FDLY_2                       ((uint16_t)0x0080)              /*!< Typical filter delay of TBD (1800) ns */
2399 #define COMP_E_CTL1_FDLY_3                       ((uint16_t)0x00C0)              /*!< Typical filter delay of TBD (3600) ns */
2400 /* COMP_E_CTL1[PWRMD] Bits */
2401 #define COMP_E_CTL1_PWRMD_OFS                    ( 8)                            /*!< CEPWRMD Bit Offset */
2402 #define COMP_E_CTL1_PWRMD_MASK                   ((uint16_t)0x0300)              /*!< CEPWRMD Bit Mask */
2403 #define COMP_E_CTL1_PWRMD0                       ((uint16_t)0x0100)              /*!< PWRMD Bit 0 */
2404 #define COMP_E_CTL1_PWRMD1                       ((uint16_t)0x0200)              /*!< PWRMD Bit 1 */
2405 #define COMP_E_CTL1_PWRMD_0                      ((uint16_t)0x0000)              /*!< High-speed mode */
2406 #define COMP_E_CTL1_PWRMD_1                      ((uint16_t)0x0100)              /*!< Normal mode */
2407 #define COMP_E_CTL1_PWRMD_2                      ((uint16_t)0x0200)              /*!< Ultra-low power mode */
2408 /* COMP_E_CTL1[ON] Bits */
2409 #define COMP_E_CTL1_ON_OFS                       (10)                            /*!< CEON Bit Offset */
2410 #define COMP_E_CTL1_ON                           ((uint16_t)0x0400)              /*!< Comparator On */
2411 /* COMP_E_CTL1[MRVL] Bits */
2412 #define COMP_E_CTL1_MRVL_OFS                     (11)                            /*!< CEMRVL Bit Offset */
2413 #define COMP_E_CTL1_MRVL                         ((uint16_t)0x0800)              /*!< This bit is valid of CEMRVS is set to 1 */
2414 /* COMP_E_CTL1[MRVS] Bits */
2415 #define COMP_E_CTL1_MRVS_OFS                     (12)                            /*!< CEMRVS Bit Offset */
2416 #define COMP_E_CTL1_MRVS                         ((uint16_t)0x1000)
2417 /* COMP_E_CTL2[REF0] Bits */
2418 #define COMP_E_CTL2_REF0_OFS                     ( 0)                            /*!< CEREF0 Bit Offset */
2419 #define COMP_E_CTL2_REF0_MASK                    ((uint16_t)0x001F)              /*!< CEREF0 Bit Mask */
2420 /* COMP_E_CTL2[RSEL] Bits */
2421 #define COMP_E_CTL2_RSEL_OFS                     ( 5)                            /*!< CERSEL Bit Offset */
2422 #define COMP_E_CTL2_RSEL                         ((uint16_t)0x0020)              /*!< Reference select */
2423 /* COMP_E_CTL2[RS] Bits */
2424 #define COMP_E_CTL2_RS_OFS                       ( 6)                            /*!< CERS Bit Offset */
2425 #define COMP_E_CTL2_RS_MASK                      ((uint16_t)0x00C0)              /*!< CERS Bit Mask */
2426 #define COMP_E_CTL2_RS0                          ((uint16_t)0x0040)              /*!< RS Bit 0 */
2427 #define COMP_E_CTL2_RS1                          ((uint16_t)0x0080)              /*!< RS Bit 1 */
2428 #define COMP_E_CTL2_RS_0                         ((uint16_t)0x0000)              /*!< No current is drawn by the reference circuitry */
2429 #define COMP_E_CTL2_RS_1                         ((uint16_t)0x0040)              /*!< VCC applied to the resistor ladder */
2430 #define COMP_E_CTL2_RS_2                         ((uint16_t)0x0080)              /*!< Shared reference voltage applied to the resistor ladder */
2431 #define COMP_E_CTL2_RS_3                         ((uint16_t)0x00C0)              /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */
2432 /* COMP_E_CTL2[REF1] Bits */
2433 #define COMP_E_CTL2_REF1_OFS                     ( 8)                            /*!< CEREF1 Bit Offset */
2434 #define COMP_E_CTL2_REF1_MASK                    ((uint16_t)0x1F00)              /*!< CEREF1 Bit Mask */
2435 /* COMP_E_CTL2[REFL] Bits */
2436 #define COMP_E_CTL2_REFL_OFS                     (13)                            /*!< CEREFL Bit Offset */
2437 #define COMP_E_CTL2_REFL_MASK                    ((uint16_t)0x6000)              /*!< CEREFL Bit Mask */
2438 #define COMP_E_CTL2_REFL0                        ((uint16_t)0x2000)              /*!< REFL Bit 0 */
2439 #define COMP_E_CTL2_REFL1                        ((uint16_t)0x4000)              /*!< REFL Bit 1 */
2440 #define COMP_E_CTL2_CEREFL_0                     ((uint16_t)0x0000)              /*!< Reference amplifier is disabled. No reference voltage is requested */
2441 #define COMP_E_CTL2_CEREFL_1                     ((uint16_t)0x2000)              /*!< 1.2 V is selected as shared reference voltage input */
2442 #define COMP_E_CTL2_CEREFL_2                     ((uint16_t)0x4000)              /*!< 2.0 V is selected as shared reference voltage input */
2443 #define COMP_E_CTL2_CEREFL_3                     ((uint16_t)0x6000)              /*!< 2.5 V is selected as shared reference voltage input */
2444 #define COMP_E_CTL2_REFL__OFF                    ((uint16_t)0x0000)              /*!< Reference amplifier is disabled. No reference voltage is requested */
2445 #define COMP_E_CTL2_REFL__1P2V                   ((uint16_t)0x2000)              /*!< 1.2 V is selected as shared reference voltage input */
2446 #define COMP_E_CTL2_REFL__2P0V                   ((uint16_t)0x4000)              /*!< 2.0 V is selected as shared reference voltage input */
2447 #define COMP_E_CTL2_REFL__2P5V                   ((uint16_t)0x6000)              /*!< 2.5 V is selected as shared reference voltage input */
2448 /* COMP_E_CTL2[REFACC] Bits */
2449 #define COMP_E_CTL2_REFACC_OFS                   (15)                            /*!< CEREFACC Bit Offset */
2450 #define COMP_E_CTL2_REFACC                       ((uint16_t)0x8000)              /*!< Reference accuracy */
2451 /* COMP_E_CTL3[PD0] Bits */
2452 #define COMP_E_CTL3_PD0_OFS                      ( 0)                            /*!< CEPD0 Bit Offset */
2453 #define COMP_E_CTL3_PD0                          ((uint16_t)0x0001)              /*!< Port disable */
2454 /* COMP_E_CTL3[PD1] Bits */
2455 #define COMP_E_CTL3_PD1_OFS                      ( 1)                            /*!< CEPD1 Bit Offset */
2456 #define COMP_E_CTL3_PD1                          ((uint16_t)0x0002)              /*!< Port disable */
2457 /* COMP_E_CTL3[PD2] Bits */
2458 #define COMP_E_CTL3_PD2_OFS                      ( 2)                            /*!< CEPD2 Bit Offset */
2459 #define COMP_E_CTL3_PD2                          ((uint16_t)0x0004)              /*!< Port disable */
2460 /* COMP_E_CTL3[PD3] Bits */
2461 #define COMP_E_CTL3_PD3_OFS                      ( 3)                            /*!< CEPD3 Bit Offset */
2462 #define COMP_E_CTL3_PD3                          ((uint16_t)0x0008)              /*!< Port disable */
2463 /* COMP_E_CTL3[PD4] Bits */
2464 #define COMP_E_CTL3_PD4_OFS                      ( 4)                            /*!< CEPD4 Bit Offset */
2465 #define COMP_E_CTL3_PD4                          ((uint16_t)0x0010)              /*!< Port disable */
2466 /* COMP_E_CTL3[PD5] Bits */
2467 #define COMP_E_CTL3_PD5_OFS                      ( 5)                            /*!< CEPD5 Bit Offset */
2468 #define COMP_E_CTL3_PD5                          ((uint16_t)0x0020)              /*!< Port disable */
2469 /* COMP_E_CTL3[PD6] Bits */
2470 #define COMP_E_CTL3_PD6_OFS                      ( 6)                            /*!< CEPD6 Bit Offset */
2471 #define COMP_E_CTL3_PD6                          ((uint16_t)0x0040)              /*!< Port disable */
2472 /* COMP_E_CTL3[PD7] Bits */
2473 #define COMP_E_CTL3_PD7_OFS                      ( 7)                            /*!< CEPD7 Bit Offset */
2474 #define COMP_E_CTL3_PD7                          ((uint16_t)0x0080)              /*!< Port disable */
2475 /* COMP_E_CTL3[PD8] Bits */
2476 #define COMP_E_CTL3_PD8_OFS                      ( 8)                            /*!< CEPD8 Bit Offset */
2477 #define COMP_E_CTL3_PD8                          ((uint16_t)0x0100)              /*!< Port disable */
2478 /* COMP_E_CTL3[PD9] Bits */
2479 #define COMP_E_CTL3_PD9_OFS                      ( 9)                            /*!< CEPD9 Bit Offset */
2480 #define COMP_E_CTL3_PD9                          ((uint16_t)0x0200)              /*!< Port disable */
2481 /* COMP_E_CTL3[PD10] Bits */
2482 #define COMP_E_CTL3_PD10_OFS                     (10)                            /*!< CEPD10 Bit Offset */
2483 #define COMP_E_CTL3_PD10                         ((uint16_t)0x0400)              /*!< Port disable */
2484 /* COMP_E_CTL3[PD11] Bits */
2485 #define COMP_E_CTL3_PD11_OFS                     (11)                            /*!< CEPD11 Bit Offset */
2486 #define COMP_E_CTL3_PD11                         ((uint16_t)0x0800)              /*!< Port disable */
2487 /* COMP_E_CTL3[PD12] Bits */
2488 #define COMP_E_CTL3_PD12_OFS                     (12)                            /*!< CEPD12 Bit Offset */
2489 #define COMP_E_CTL3_PD12                         ((uint16_t)0x1000)              /*!< Port disable */
2490 /* COMP_E_CTL3[PD13] Bits */
2491 #define COMP_E_CTL3_PD13_OFS                     (13)                            /*!< CEPD13 Bit Offset */
2492 #define COMP_E_CTL3_PD13                         ((uint16_t)0x2000)              /*!< Port disable */
2493 /* COMP_E_CTL3[PD14] Bits */
2494 #define COMP_E_CTL3_PD14_OFS                     (14)                            /*!< CEPD14 Bit Offset */
2495 #define COMP_E_CTL3_PD14                         ((uint16_t)0x4000)              /*!< Port disable */
2496 /* COMP_E_CTL3[PD15] Bits */
2497 #define COMP_E_CTL3_PD15_OFS                     (15)                            /*!< CEPD15 Bit Offset */
2498 #define COMP_E_CTL3_PD15                         ((uint16_t)0x8000)              /*!< Port disable */
2499 /* COMP_E_INT[IFG] Bits */
2500 #define COMP_E_INT_IFG_OFS                       ( 0)                            /*!< CEIFG Bit Offset */
2501 #define COMP_E_INT_IFG                           ((uint16_t)0x0001)              /*!< Comparator output interrupt flag */
2502 /* COMP_E_INT[IIFG] Bits */
2503 #define COMP_E_INT_IIFG_OFS                      ( 1)                            /*!< CEIIFG Bit Offset */
2504 #define COMP_E_INT_IIFG                          ((uint16_t)0x0002)              /*!< Comparator output inverted interrupt flag */
2505 /* COMP_E_INT[RDYIFG] Bits */
2506 #define COMP_E_INT_RDYIFG_OFS                    ( 4)                            /*!< CERDYIFG Bit Offset */
2507 #define COMP_E_INT_RDYIFG                        ((uint16_t)0x0010)              /*!< Comparator ready interrupt flag */
2508 /* COMP_E_INT[IE] Bits */
2509 #define COMP_E_INT_IE_OFS                        ( 8)                            /*!< CEIE Bit Offset */
2510 #define COMP_E_INT_IE                            ((uint16_t)0x0100)              /*!< Comparator output interrupt enable */
2511 /* COMP_E_INT[IIE] Bits */
2512 #define COMP_E_INT_IIE_OFS                       ( 9)                            /*!< CEIIE Bit Offset */
2513 #define COMP_E_INT_IIE                           ((uint16_t)0x0200)              /*!< Comparator output interrupt enable inverted polarity */
2514 /* COMP_E_INT[RDYIE] Bits */
2515 #define COMP_E_INT_RDYIE_OFS                     (12)                            /*!< CERDYIE Bit Offset */
2516 #define COMP_E_INT_RDYIE                         ((uint16_t)0x1000)              /*!< Comparator ready interrupt enable */
2517 
2518 /******************************************************************************
2519 * COREDEBUG Bits
2520 ******************************************************************************/
2521 
2522 
2523 /******************************************************************************
2524 * CRC32 Bits
2525 ******************************************************************************/
2526 
2527 /******************************************************************************
2528 * CS Bits
2529 ******************************************************************************/
2530 /* CS_KEY[KEY] Bits */
2531 #define CS_KEY_KEY_OFS                           ( 0)                            /*!< CSKEY Bit Offset */
2532 #define CS_KEY_KEY_MASK                          ((uint32_t)0x0000FFFF)          /*!< CSKEY Bit Mask */
2533 /* CS_CTL0[DCOTUNE] Bits */
2534 #define CS_CTL0_DCOTUNE_OFS                      ( 0)                            /*!< DCOTUNE Bit Offset */
2535 #define CS_CTL0_DCOTUNE_MASK                     ((uint32_t)0x000003FF)          /*!< DCOTUNE Bit Mask */
2536 /* CS_CTL0[DCORSEL] Bits */
2537 #define CS_CTL0_DCORSEL_OFS                      (16)                            /*!< DCORSEL Bit Offset */
2538 #define CS_CTL0_DCORSEL_MASK                     ((uint32_t)0x00070000)          /*!< DCORSEL Bit Mask */
2539 #define CS_CTL0_DCORSEL0                         ((uint32_t)0x00010000)          /*!< DCORSEL Bit 0 */
2540 #define CS_CTL0_DCORSEL1                         ((uint32_t)0x00020000)          /*!< DCORSEL Bit 1 */
2541 #define CS_CTL0_DCORSEL2                         ((uint32_t)0x00040000)          /*!< DCORSEL Bit 2 */
2542 #define CS_CTL0_DCORSEL_0                        ((uint32_t)0x00000000)          /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */
2543 #define CS_CTL0_DCORSEL_1                        ((uint32_t)0x00010000)          /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */
2544 #define CS_CTL0_DCORSEL_2                        ((uint32_t)0x00020000)          /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */
2545 #define CS_CTL0_DCORSEL_3                        ((uint32_t)0x00030000)          /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */
2546 #define CS_CTL0_DCORSEL_4                        ((uint32_t)0x00040000)          /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */
2547 #define CS_CTL0_DCORSEL_5                        ((uint32_t)0x00050000)          /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */
2548 /* CS_CTL0[DCORES] Bits */
2549 #define CS_CTL0_DCORES_OFS                       (22)                            /*!< DCORES Bit Offset */
2550 #define CS_CTL0_DCORES                           ((uint32_t)0x00400000)          /*!< Enables the DCO external resistor mode */
2551 /* CS_CTL0[DCOEN] Bits */
2552 #define CS_CTL0_DCOEN_OFS                        (23)                            /*!< DCOEN Bit Offset */
2553 #define CS_CTL0_DCOEN                            ((uint32_t)0x00800000)          /*!< Enables the DCO oscillator */
2554 /* CS_CTL1[SELM] Bits */
2555 #define CS_CTL1_SELM_OFS                         ( 0)                            /*!< SELM Bit Offset */
2556 #define CS_CTL1_SELM_MASK                        ((uint32_t)0x00000007)          /*!< SELM Bit Mask */
2557 #define CS_CTL1_SELM0                            ((uint32_t)0x00000001)          /*!< SELM Bit 0 */
2558 #define CS_CTL1_SELM1                            ((uint32_t)0x00000002)          /*!< SELM Bit 1 */
2559 #define CS_CTL1_SELM2                            ((uint32_t)0x00000004)          /*!< SELM Bit 2 */
2560 #define CS_CTL1_SELM_0                           ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2561 #define CS_CTL1_SELM_1                           ((uint32_t)0x00000001)
2562 #define CS_CTL1_SELM_2                           ((uint32_t)0x00000002)
2563 #define CS_CTL1_SELM_3                           ((uint32_t)0x00000003)
2564 #define CS_CTL1_SELM_4                           ((uint32_t)0x00000004)
2565 #define CS_CTL1_SELM_5                           ((uint32_t)0x00000005)          /*!< when HFXT available, otherwise DCOCLK */
2566 #define CS_CTL1_SELM_6                           ((uint32_t)0x00000006)          /*!< when HFXT2 available, otherwise DCOCLK */
2567 #define CS_CTL1_SELM__LFXTCLK                    ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2568 #define CS_CTL1_SELM__VLOCLK                     ((uint32_t)0x00000001)
2569 #define CS_CTL1_SELM__REFOCLK                    ((uint32_t)0x00000002)
2570 #define CS_CTL1_SELM__DCOCLK                     ((uint32_t)0x00000003)
2571 #define CS_CTL1_SELM__MODOSC                     ((uint32_t)0x00000004)
2572 #define CS_CTL1_SELM__HFXTCLK                    ((uint32_t)0x00000005)          /*!< when HFXT available, otherwise DCOCLK */
2573 #define CS_CTL1_SELM__HFXT2CLK                   ((uint32_t)0x00000006)          /*!< when HFXT2 available, otherwise DCOCLK */
2574 /* CS_CTL1[SELS] Bits */
2575 #define CS_CTL1_SELS_OFS                         ( 4)                            /*!< SELS Bit Offset */
2576 #define CS_CTL1_SELS_MASK                        ((uint32_t)0x00000070)          /*!< SELS Bit Mask */
2577 #define CS_CTL1_SELS0                            ((uint32_t)0x00000010)          /*!< SELS Bit 0 */
2578 #define CS_CTL1_SELS1                            ((uint32_t)0x00000020)          /*!< SELS Bit 1 */
2579 #define CS_CTL1_SELS2                            ((uint32_t)0x00000040)          /*!< SELS Bit 2 */
2580 #define CS_CTL1_SELS_0                           ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2581 #define CS_CTL1_SELS_1                           ((uint32_t)0x00000010)
2582 #define CS_CTL1_SELS_2                           ((uint32_t)0x00000020)
2583 #define CS_CTL1_SELS_3                           ((uint32_t)0x00000030)
2584 #define CS_CTL1_SELS_4                           ((uint32_t)0x00000040)
2585 #define CS_CTL1_SELS_5                           ((uint32_t)0x00000050)          /*!< when HFXT available, otherwise DCOCLK */
2586 #define CS_CTL1_SELS_6                           ((uint32_t)0x00000060)          /*!< when HFXT2 available, otherwise DCOCLK */
2587 #define CS_CTL1_SELS__LFXTCLK                    ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2588 #define CS_CTL1_SELS__VLOCLK                     ((uint32_t)0x00000010)
2589 #define CS_CTL1_SELS__REFOCLK                    ((uint32_t)0x00000020)
2590 #define CS_CTL1_SELS__DCOCLK                     ((uint32_t)0x00000030)
2591 #define CS_CTL1_SELS__MODOSC                     ((uint32_t)0x00000040)
2592 #define CS_CTL1_SELS__HFXTCLK                    ((uint32_t)0x00000050)          /*!< when HFXT available, otherwise DCOCLK */
2593 #define CS_CTL1_SELS__HFXT2CLK                   ((uint32_t)0x00000060)          /*!< when HFXT2 available, otherwise DCOCLK */
2594 /* CS_CTL1[SELA] Bits */
2595 #define CS_CTL1_SELA_OFS                         ( 8)                            /*!< SELA Bit Offset */
2596 #define CS_CTL1_SELA_MASK                        ((uint32_t)0x00000700)          /*!< SELA Bit Mask */
2597 #define CS_CTL1_SELA0                            ((uint32_t)0x00000100)          /*!< SELA Bit 0 */
2598 #define CS_CTL1_SELA1                            ((uint32_t)0x00000200)          /*!< SELA Bit 1 */
2599 #define CS_CTL1_SELA2                            ((uint32_t)0x00000400)          /*!< SELA Bit 2 */
2600 #define CS_CTL1_SELA_0                           ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2601 #define CS_CTL1_SELA_1                           ((uint32_t)0x00000100)
2602 #define CS_CTL1_SELA_2                           ((uint32_t)0x00000200)
2603 #define CS_CTL1_SELA__LFXTCLK                    ((uint32_t)0x00000000)          /*!< when LFXT available, otherwise REFOCLK */
2604 #define CS_CTL1_SELA__VLOCLK                     ((uint32_t)0x00000100)
2605 #define CS_CTL1_SELA__REFOCLK                    ((uint32_t)0x00000200)
2606 /* CS_CTL1[SELB] Bits */
2607 #define CS_CTL1_SELB_OFS                         (12)                            /*!< SELB Bit Offset */
2608 #define CS_CTL1_SELB                             ((uint32_t)0x00001000)          /*!< Selects the BCLK source */
2609 /* CS_CTL1[DIVM] Bits */
2610 #define CS_CTL1_DIVM_OFS                         (16)                            /*!< DIVM Bit Offset */
2611 #define CS_CTL1_DIVM_MASK                        ((uint32_t)0x00070000)          /*!< DIVM Bit Mask */
2612 #define CS_CTL1_DIVM0                            ((uint32_t)0x00010000)          /*!< DIVM Bit 0 */
2613 #define CS_CTL1_DIVM1                            ((uint32_t)0x00020000)          /*!< DIVM Bit 1 */
2614 #define CS_CTL1_DIVM2                            ((uint32_t)0x00040000)          /*!< DIVM Bit 2 */
2615 #define CS_CTL1_DIVM_0                           ((uint32_t)0x00000000)          /*!< f(MCLK)/1 */
2616 #define CS_CTL1_DIVM_1                           ((uint32_t)0x00010000)          /*!< f(MCLK)/2 */
2617 #define CS_CTL1_DIVM_2                           ((uint32_t)0x00020000)          /*!< f(MCLK)/4 */
2618 #define CS_CTL1_DIVM_3                           ((uint32_t)0x00030000)          /*!< f(MCLK)/8 */
2619 #define CS_CTL1_DIVM_4                           ((uint32_t)0x00040000)          /*!< f(MCLK)/16 */
2620 #define CS_CTL1_DIVM_5                           ((uint32_t)0x00050000)          /*!< f(MCLK)/32 */
2621 #define CS_CTL1_DIVM_6                           ((uint32_t)0x00060000)          /*!< f(MCLK)/64 */
2622 #define CS_CTL1_DIVM_7                           ((uint32_t)0x00070000)          /*!< f(MCLK)/128 */
2623 #define CS_CTL1_DIVM__1                          ((uint32_t)0x00000000)          /*!< f(MCLK)/1 */
2624 #define CS_CTL1_DIVM__2                          ((uint32_t)0x00010000)          /*!< f(MCLK)/2 */
2625 #define CS_CTL1_DIVM__4                          ((uint32_t)0x00020000)          /*!< f(MCLK)/4 */
2626 #define CS_CTL1_DIVM__8                          ((uint32_t)0x00030000)          /*!< f(MCLK)/8 */
2627 #define CS_CTL1_DIVM__16                         ((uint32_t)0x00040000)          /*!< f(MCLK)/16 */
2628 #define CS_CTL1_DIVM__32                         ((uint32_t)0x00050000)          /*!< f(MCLK)/32 */
2629 #define CS_CTL1_DIVM__64                         ((uint32_t)0x00060000)          /*!< f(MCLK)/64 */
2630 #define CS_CTL1_DIVM__128                        ((uint32_t)0x00070000)          /*!< f(MCLK)/128 */
2631 /* CS_CTL1[DIVHS] Bits */
2632 #define CS_CTL1_DIVHS_OFS                        (20)                            /*!< DIVHS Bit Offset */
2633 #define CS_CTL1_DIVHS_MASK                       ((uint32_t)0x00700000)          /*!< DIVHS Bit Mask */
2634 #define CS_CTL1_DIVHS0                           ((uint32_t)0x00100000)          /*!< DIVHS Bit 0 */
2635 #define CS_CTL1_DIVHS1                           ((uint32_t)0x00200000)          /*!< DIVHS Bit 1 */
2636 #define CS_CTL1_DIVHS2                           ((uint32_t)0x00400000)          /*!< DIVHS Bit 2 */
2637 #define CS_CTL1_DIVHS_0                          ((uint32_t)0x00000000)          /*!< f(HSMCLK)/1 */
2638 #define CS_CTL1_DIVHS_1                          ((uint32_t)0x00100000)          /*!< f(HSMCLK)/2 */
2639 #define CS_CTL1_DIVHS_2                          ((uint32_t)0x00200000)          /*!< f(HSMCLK)/4 */
2640 #define CS_CTL1_DIVHS_3                          ((uint32_t)0x00300000)          /*!< f(HSMCLK)/8 */
2641 #define CS_CTL1_DIVHS_4                          ((uint32_t)0x00400000)          /*!< f(HSMCLK)/16 */
2642 #define CS_CTL1_DIVHS_5                          ((uint32_t)0x00500000)          /*!< f(HSMCLK)/32 */
2643 #define CS_CTL1_DIVHS_6                          ((uint32_t)0x00600000)          /*!< f(HSMCLK)/64 */
2644 #define CS_CTL1_DIVHS_7                          ((uint32_t)0x00700000)          /*!< f(HSMCLK)/128 */
2645 #define CS_CTL1_DIVHS__1                         ((uint32_t)0x00000000)          /*!< f(HSMCLK)/1 */
2646 #define CS_CTL1_DIVHS__2                         ((uint32_t)0x00100000)          /*!< f(HSMCLK)/2 */
2647 #define CS_CTL1_DIVHS__4                         ((uint32_t)0x00200000)          /*!< f(HSMCLK)/4 */
2648 #define CS_CTL1_DIVHS__8                         ((uint32_t)0x00300000)          /*!< f(HSMCLK)/8 */
2649 #define CS_CTL1_DIVHS__16                        ((uint32_t)0x00400000)          /*!< f(HSMCLK)/16 */
2650 #define CS_CTL1_DIVHS__32                        ((uint32_t)0x00500000)          /*!< f(HSMCLK)/32 */
2651 #define CS_CTL1_DIVHS__64                        ((uint32_t)0x00600000)          /*!< f(HSMCLK)/64 */
2652 #define CS_CTL1_DIVHS__128                       ((uint32_t)0x00700000)          /*!< f(HSMCLK)/128 */
2653 /* CS_CTL1[DIVA] Bits */
2654 #define CS_CTL1_DIVA_OFS                         (24)                            /*!< DIVA Bit Offset */
2655 #define CS_CTL1_DIVA_MASK                        ((uint32_t)0x07000000)          /*!< DIVA Bit Mask */
2656 #define CS_CTL1_DIVA0                            ((uint32_t)0x01000000)          /*!< DIVA Bit 0 */
2657 #define CS_CTL1_DIVA1                            ((uint32_t)0x02000000)          /*!< DIVA Bit 1 */
2658 #define CS_CTL1_DIVA2                            ((uint32_t)0x04000000)          /*!< DIVA Bit 2 */
2659 #define CS_CTL1_DIVA_0                           ((uint32_t)0x00000000)          /*!< f(ACLK)/1 */
2660 #define CS_CTL1_DIVA_1                           ((uint32_t)0x01000000)          /*!< f(ACLK)/2 */
2661 #define CS_CTL1_DIVA_2                           ((uint32_t)0x02000000)          /*!< f(ACLK)/4 */
2662 #define CS_CTL1_DIVA_3                           ((uint32_t)0x03000000)          /*!< f(ACLK)/8 */
2663 #define CS_CTL1_DIVA_4                           ((uint32_t)0x04000000)          /*!< f(ACLK)/16 */
2664 #define CS_CTL1_DIVA_5                           ((uint32_t)0x05000000)          /*!< f(ACLK)/32 */
2665 #define CS_CTL1_DIVA_6                           ((uint32_t)0x06000000)          /*!< f(ACLK)/64 */
2666 #define CS_CTL1_DIVA_7                           ((uint32_t)0x07000000)          /*!< f(ACLK)/128 */
2667 #define CS_CTL1_DIVA__1                          ((uint32_t)0x00000000)          /*!< f(ACLK)/1 */
2668 #define CS_CTL1_DIVA__2                          ((uint32_t)0x01000000)          /*!< f(ACLK)/2 */
2669 #define CS_CTL1_DIVA__4                          ((uint32_t)0x02000000)          /*!< f(ACLK)/4 */
2670 #define CS_CTL1_DIVA__8                          ((uint32_t)0x03000000)          /*!< f(ACLK)/8 */
2671 #define CS_CTL1_DIVA__16                         ((uint32_t)0x04000000)          /*!< f(ACLK)/16 */
2672 #define CS_CTL1_DIVA__32                         ((uint32_t)0x05000000)          /*!< f(ACLK)/32 */
2673 #define CS_CTL1_DIVA__64                         ((uint32_t)0x06000000)          /*!< f(ACLK)/64 */
2674 #define CS_CTL1_DIVA__128                        ((uint32_t)0x07000000)          /*!< f(ACLK)/128 */
2675 /* CS_CTL1[DIVS] Bits */
2676 #define CS_CTL1_DIVS_OFS                         (28)                            /*!< DIVS Bit Offset */
2677 #define CS_CTL1_DIVS_MASK                        ((uint32_t)0x70000000)          /*!< DIVS Bit Mask */
2678 #define CS_CTL1_DIVS0                            ((uint32_t)0x10000000)          /*!< DIVS Bit 0 */
2679 #define CS_CTL1_DIVS1                            ((uint32_t)0x20000000)          /*!< DIVS Bit 1 */
2680 #define CS_CTL1_DIVS2                            ((uint32_t)0x40000000)          /*!< DIVS Bit 2 */
2681 #define CS_CTL1_DIVS_0                           ((uint32_t)0x00000000)          /*!< f(SMCLK)/1 */
2682 #define CS_CTL1_DIVS_1                           ((uint32_t)0x10000000)          /*!< f(SMCLK)/2 */
2683 #define CS_CTL1_DIVS_2                           ((uint32_t)0x20000000)          /*!< f(SMCLK)/4 */
2684 #define CS_CTL1_DIVS_3                           ((uint32_t)0x30000000)          /*!< f(SMCLK)/8 */
2685 #define CS_CTL1_DIVS_4                           ((uint32_t)0x40000000)          /*!< f(SMCLK)/16 */
2686 #define CS_CTL1_DIVS_5                           ((uint32_t)0x50000000)          /*!< f(SMCLK)/32 */
2687 #define CS_CTL1_DIVS_6                           ((uint32_t)0x60000000)          /*!< f(SMCLK)/64 */
2688 #define CS_CTL1_DIVS_7                           ((uint32_t)0x70000000)          /*!< f(SMCLK)/128 */
2689 #define CS_CTL1_DIVS__1                          ((uint32_t)0x00000000)          /*!< f(SMCLK)/1 */
2690 #define CS_CTL1_DIVS__2                          ((uint32_t)0x10000000)          /*!< f(SMCLK)/2 */
2691 #define CS_CTL1_DIVS__4                          ((uint32_t)0x20000000)          /*!< f(SMCLK)/4 */
2692 #define CS_CTL1_DIVS__8                          ((uint32_t)0x30000000)          /*!< f(SMCLK)/8 */
2693 #define CS_CTL1_DIVS__16                         ((uint32_t)0x40000000)          /*!< f(SMCLK)/16 */
2694 #define CS_CTL1_DIVS__32                         ((uint32_t)0x50000000)          /*!< f(SMCLK)/32 */
2695 #define CS_CTL1_DIVS__64                         ((uint32_t)0x60000000)          /*!< f(SMCLK)/64 */
2696 #define CS_CTL1_DIVS__128                        ((uint32_t)0x70000000)          /*!< f(SMCLK)/128 */
2697 /* CS_CTL2[LFXTDRIVE] Bits */
2698 #define CS_CTL2_LFXTDRIVE_OFS                    ( 0)                            /*!< LFXTDRIVE Bit Offset */
2699 #define CS_CTL2_LFXTDRIVE_MASK                   ((uint32_t)0x00000003)          /*!< LFXTDRIVE Bit Mask */
2700 #define CS_CTL2_LFXTDRIVE0                       ((uint32_t)0x00000001)          /*!< LFXTDRIVE Bit 0 */
2701 #define CS_CTL2_LFXTDRIVE1                       ((uint32_t)0x00000002)          /*!< LFXTDRIVE Bit 1 */
2702 #define CS_CTL2_LFXTDRIVE_0                      ((uint32_t)0x00000000)          /*!< Lowest drive strength and current consumption LFXT oscillator. */
2703 #define CS_CTL2_LFXTDRIVE_1                      ((uint32_t)0x00000001)          /*!< Increased drive strength LFXT oscillator. */
2704 #define CS_CTL2_LFXTDRIVE_2                      ((uint32_t)0x00000002)          /*!< Increased drive strength LFXT oscillator. */
2705 #define CS_CTL2_LFXTDRIVE_3                      ((uint32_t)0x00000003)          /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */
2706 /* CS_CTL2[LFXT_EN] Bits */
2707 #define CS_CTL2_LFXT_EN_OFS                      ( 8)                            /*!< LFXT_EN Bit Offset */
2708 #define CS_CTL2_LFXT_EN                          ((uint32_t)0x00000100)          /*!< Turns on the LFXT oscillator regardless if used as a clock resource */
2709 /* CS_CTL2[LFXTBYPASS] Bits */
2710 #define CS_CTL2_LFXTBYPASS_OFS                   ( 9)                            /*!< LFXTBYPASS Bit Offset */
2711 #define CS_CTL2_LFXTBYPASS                       ((uint32_t)0x00000200)          /*!< LFXT bypass select */
2712 /* CS_CTL2[HFXTDRIVE] Bits */
2713 #define CS_CTL2_HFXTDRIVE_OFS                    (16)                            /*!< HFXTDRIVE Bit Offset */
2714 #define CS_CTL2_HFXTDRIVE                        ((uint32_t)0x00010000)          /*!< HFXT oscillator drive selection */
2715 /* CS_CTL2[HFXTFREQ] Bits */
2716 #define CS_CTL2_HFXTFREQ_OFS                     (20)                            /*!< HFXTFREQ Bit Offset */
2717 #define CS_CTL2_HFXTFREQ_MASK                    ((uint32_t)0x00700000)          /*!< HFXTFREQ Bit Mask */
2718 #define CS_CTL2_HFXTFREQ0                        ((uint32_t)0x00100000)          /*!< HFXTFREQ Bit 0 */
2719 #define CS_CTL2_HFXTFREQ1                        ((uint32_t)0x00200000)          /*!< HFXTFREQ Bit 1 */
2720 #define CS_CTL2_HFXTFREQ2                        ((uint32_t)0x00400000)          /*!< HFXTFREQ Bit 2 */
2721 #define CS_CTL2_HFXTFREQ_0                       ((uint32_t)0x00000000)          /*!< 1 MHz to 4 MHz */
2722 #define CS_CTL2_HFXTFREQ_1                       ((uint32_t)0x00100000)          /*!< >4 MHz to 8 MHz */
2723 #define CS_CTL2_HFXTFREQ_2                       ((uint32_t)0x00200000)          /*!< >8 MHz to 16 MHz */
2724 #define CS_CTL2_HFXTFREQ_3                       ((uint32_t)0x00300000)          /*!< >16 MHz to 24 MHz */
2725 #define CS_CTL2_HFXTFREQ_4                       ((uint32_t)0x00400000)          /*!< >24 MHz to 32 MHz */
2726 #define CS_CTL2_HFXTFREQ_5                       ((uint32_t)0x00500000)          /*!< >32 MHz to 40 MHz */
2727 #define CS_CTL2_HFXTFREQ_6                       ((uint32_t)0x00600000)          /*!< >40 MHz to 48 MHz */
2728 #define CS_CTL2_HFXTFREQ_7                       ((uint32_t)0x00700000)          /*!< Reserved for future use. */
2729 /* CS_CTL2[HFXT_EN] Bits */
2730 #define CS_CTL2_HFXT_EN_OFS                      (24)                            /*!< HFXT_EN Bit Offset */
2731 #define CS_CTL2_HFXT_EN                          ((uint32_t)0x01000000)          /*!< Turns on the HFXT oscillator regardless if used as a clock resource */
2732 /* CS_CTL2[HFXTBYPASS] Bits */
2733 #define CS_CTL2_HFXTBYPASS_OFS                   (25)                            /*!< HFXTBYPASS Bit Offset */
2734 #define CS_CTL2_HFXTBYPASS                       ((uint32_t)0x02000000)          /*!< HFXT bypass select */
2735 /* CS_CTL3[FCNTLF] Bits */
2736 #define CS_CTL3_FCNTLF_OFS                       ( 0)                            /*!< FCNTLF Bit Offset */
2737 #define CS_CTL3_FCNTLF_MASK                      ((uint32_t)0x00000003)          /*!< FCNTLF Bit Mask */
2738 #define CS_CTL3_FCNTLF0                          ((uint32_t)0x00000001)          /*!< FCNTLF Bit 0 */
2739 #define CS_CTL3_FCNTLF1                          ((uint32_t)0x00000002)          /*!< FCNTLF Bit 1 */
2740 #define CS_CTL3_FCNTLF_0                         ((uint32_t)0x00000000)          /*!< 4096 cycles */
2741 #define CS_CTL3_FCNTLF_1                         ((uint32_t)0x00000001)          /*!< 8192 cycles */
2742 #define CS_CTL3_FCNTLF_2                         ((uint32_t)0x00000002)          /*!< 16384 cycles */
2743 #define CS_CTL3_FCNTLF_3                         ((uint32_t)0x00000003)          /*!< 32768 cycles */
2744 #define CS_CTL3_FCNTLF__4096                     ((uint32_t)0x00000000)          /*!< 4096 cycles */
2745 #define CS_CTL3_FCNTLF__8192                     ((uint32_t)0x00000001)          /*!< 8192 cycles */
2746 #define CS_CTL3_FCNTLF__16384                    ((uint32_t)0x00000002)          /*!< 16384 cycles */
2747 #define CS_CTL3_FCNTLF__32768                    ((uint32_t)0x00000003)          /*!< 32768 cycles */
2748 /* CS_CTL3[RFCNTLF] Bits */
2749 #define CS_CTL3_RFCNTLF_OFS                      ( 2)                            /*!< RFCNTLF Bit Offset */
2750 #define CS_CTL3_RFCNTLF                          ((uint32_t)0x00000004)          /*!< Reset start fault counter for LFXT */
2751 /* CS_CTL3[FCNTLF_EN] Bits */
2752 #define CS_CTL3_FCNTLF_EN_OFS                    ( 3)                            /*!< FCNTLF_EN Bit Offset */
2753 #define CS_CTL3_FCNTLF_EN                        ((uint32_t)0x00000008)          /*!< Enable start fault counter for LFXT */
2754 /* CS_CTL3[FCNTHF] Bits */
2755 #define CS_CTL3_FCNTHF_OFS                       ( 4)                            /*!< FCNTHF Bit Offset */
2756 #define CS_CTL3_FCNTHF_MASK                      ((uint32_t)0x00000030)          /*!< FCNTHF Bit Mask */
2757 #define CS_CTL3_FCNTHF0                          ((uint32_t)0x00000010)          /*!< FCNTHF Bit 0 */
2758 #define CS_CTL3_FCNTHF1                          ((uint32_t)0x00000020)          /*!< FCNTHF Bit 1 */
2759 #define CS_CTL3_FCNTHF_0                         ((uint32_t)0x00000000)          /*!< 2048 cycles */
2760 #define CS_CTL3_FCNTHF_1                         ((uint32_t)0x00000010)          /*!< 4096 cycles */
2761 #define CS_CTL3_FCNTHF_2                         ((uint32_t)0x00000020)          /*!< 8192 cycles */
2762 #define CS_CTL3_FCNTHF_3                         ((uint32_t)0x00000030)          /*!< 16384 cycles */
2763 #define CS_CTL3_FCNTHF__2048                     ((uint32_t)0x00000000)          /*!< 2048 cycles */
2764 #define CS_CTL3_FCNTHF__4096                     ((uint32_t)0x00000010)          /*!< 4096 cycles */
2765 #define CS_CTL3_FCNTHF__8192                     ((uint32_t)0x00000020)          /*!< 8192 cycles */
2766 #define CS_CTL3_FCNTHF__16384                    ((uint32_t)0x00000030)          /*!< 16384 cycles */
2767 /* CS_CTL3[RFCNTHF] Bits */
2768 #define CS_CTL3_RFCNTHF_OFS                      ( 6)                            /*!< RFCNTHF Bit Offset */
2769 #define CS_CTL3_RFCNTHF                          ((uint32_t)0x00000040)          /*!< Reset start fault counter for HFXT */
2770 /* CS_CTL3[FCNTHF_EN] Bits */
2771 #define CS_CTL3_FCNTHF_EN_OFS                    ( 7)                            /*!< FCNTHF_EN Bit Offset */
2772 #define CS_CTL3_FCNTHF_EN                        ((uint32_t)0x00000080)          /*!< Enable start fault counter for HFXT */
2773 /* CS_CLKEN[ACLK_EN] Bits */
2774 #define CS_CLKEN_ACLK_EN_OFS                     ( 0)                            /*!< ACLK_EN Bit Offset */
2775 #define CS_CLKEN_ACLK_EN                         ((uint32_t)0x00000001)          /*!< ACLK system clock conditional request enable */
2776 /* CS_CLKEN[MCLK_EN] Bits */
2777 #define CS_CLKEN_MCLK_EN_OFS                     ( 1)                            /*!< MCLK_EN Bit Offset */
2778 #define CS_CLKEN_MCLK_EN                         ((uint32_t)0x00000002)          /*!< MCLK system clock conditional request enable */
2779 /* CS_CLKEN[HSMCLK_EN] Bits */
2780 #define CS_CLKEN_HSMCLK_EN_OFS                   ( 2)                            /*!< HSMCLK_EN Bit Offset */
2781 #define CS_CLKEN_HSMCLK_EN                       ((uint32_t)0x00000004)          /*!< HSMCLK system clock conditional request enable */
2782 /* CS_CLKEN[SMCLK_EN] Bits */
2783 #define CS_CLKEN_SMCLK_EN_OFS                    ( 3)                            /*!< SMCLK_EN Bit Offset */
2784 #define CS_CLKEN_SMCLK_EN                        ((uint32_t)0x00000008)          /*!< SMCLK system clock conditional request enable */
2785 /* CS_CLKEN[VLO_EN] Bits */
2786 #define CS_CLKEN_VLO_EN_OFS                      ( 8)                            /*!< VLO_EN Bit Offset */
2787 #define CS_CLKEN_VLO_EN                          ((uint32_t)0x00000100)          /*!< Turns on the VLO oscillator */
2788 /* CS_CLKEN[REFO_EN] Bits */
2789 #define CS_CLKEN_REFO_EN_OFS                     ( 9)                            /*!< REFO_EN Bit Offset */
2790 #define CS_CLKEN_REFO_EN                         ((uint32_t)0x00000200)          /*!< Turns on the REFO oscillator */
2791 /* CS_CLKEN[MODOSC_EN] Bits */
2792 #define CS_CLKEN_MODOSC_EN_OFS                   (10)                            /*!< MODOSC_EN Bit Offset */
2793 #define CS_CLKEN_MODOSC_EN                       ((uint32_t)0x00000400)          /*!< Turns on the MODOSC oscillator */
2794 /* CS_CLKEN[REFOFSEL] Bits */
2795 #define CS_CLKEN_REFOFSEL_OFS                    (15)                            /*!< REFOFSEL Bit Offset */
2796 #define CS_CLKEN_REFOFSEL                        ((uint32_t)0x00008000)          /*!< Selects REFO nominal frequency */
2797 /* CS_STAT[DCO_ON] Bits */
2798 #define CS_STAT_DCO_ON_OFS                       ( 0)                            /*!< DCO_ON Bit Offset */
2799 #define CS_STAT_DCO_ON                           ((uint32_t)0x00000001)          /*!< DCO status */
2800 /* CS_STAT[DCOBIAS_ON] Bits */
2801 #define CS_STAT_DCOBIAS_ON_OFS                   ( 1)                            /*!< DCOBIAS_ON Bit Offset */
2802 #define CS_STAT_DCOBIAS_ON                       ((uint32_t)0x00000002)          /*!< DCO bias status */
2803 /* CS_STAT[HFXT_ON] Bits */
2804 #define CS_STAT_HFXT_ON_OFS                      ( 2)                            /*!< HFXT_ON Bit Offset */
2805 #define CS_STAT_HFXT_ON                          ((uint32_t)0x00000004)          /*!< HFXT status */
2806 /* CS_STAT[MODOSC_ON] Bits */
2807 #define CS_STAT_MODOSC_ON_OFS                    ( 4)                            /*!< MODOSC_ON Bit Offset */
2808 #define CS_STAT_MODOSC_ON                        ((uint32_t)0x00000010)          /*!< MODOSC status */
2809 /* CS_STAT[VLO_ON] Bits */
2810 #define CS_STAT_VLO_ON_OFS                       ( 5)                            /*!< VLO_ON Bit Offset */
2811 #define CS_STAT_VLO_ON                           ((uint32_t)0x00000020)          /*!< VLO status */
2812 /* CS_STAT[LFXT_ON] Bits */
2813 #define CS_STAT_LFXT_ON_OFS                      ( 6)                            /*!< LFXT_ON Bit Offset */
2814 #define CS_STAT_LFXT_ON                          ((uint32_t)0x00000040)          /*!< LFXT status */
2815 /* CS_STAT[REFO_ON] Bits */
2816 #define CS_STAT_REFO_ON_OFS                      ( 7)                            /*!< REFO_ON Bit Offset */
2817 #define CS_STAT_REFO_ON                          ((uint32_t)0x00000080)          /*!< REFO status */
2818 /* CS_STAT[ACLK_ON] Bits */
2819 #define CS_STAT_ACLK_ON_OFS                      (16)                            /*!< ACLK_ON Bit Offset */
2820 #define CS_STAT_ACLK_ON                          ((uint32_t)0x00010000)          /*!< ACLK system clock status */
2821 /* CS_STAT[MCLK_ON] Bits */
2822 #define CS_STAT_MCLK_ON_OFS                      (17)                            /*!< MCLK_ON Bit Offset */
2823 #define CS_STAT_MCLK_ON                          ((uint32_t)0x00020000)          /*!< MCLK system clock status */
2824 /* CS_STAT[HSMCLK_ON] Bits */
2825 #define CS_STAT_HSMCLK_ON_OFS                    (18)                            /*!< HSMCLK_ON Bit Offset */
2826 #define CS_STAT_HSMCLK_ON                        ((uint32_t)0x00040000)          /*!< HSMCLK system clock status */
2827 /* CS_STAT[SMCLK_ON] Bits */
2828 #define CS_STAT_SMCLK_ON_OFS                     (19)                            /*!< SMCLK_ON Bit Offset */
2829 #define CS_STAT_SMCLK_ON                         ((uint32_t)0x00080000)          /*!< SMCLK system clock status */
2830 /* CS_STAT[MODCLK_ON] Bits */
2831 #define CS_STAT_MODCLK_ON_OFS                    (20)                            /*!< MODCLK_ON Bit Offset */
2832 #define CS_STAT_MODCLK_ON                        ((uint32_t)0x00100000)          /*!< MODCLK system clock status */
2833 /* CS_STAT[VLOCLK_ON] Bits */
2834 #define CS_STAT_VLOCLK_ON_OFS                    (21)                            /*!< VLOCLK_ON Bit Offset */
2835 #define CS_STAT_VLOCLK_ON                        ((uint32_t)0x00200000)          /*!< VLOCLK system clock status */
2836 /* CS_STAT[LFXTCLK_ON] Bits */
2837 #define CS_STAT_LFXTCLK_ON_OFS                   (22)                            /*!< LFXTCLK_ON Bit Offset */
2838 #define CS_STAT_LFXTCLK_ON                       ((uint32_t)0x00400000)          /*!< LFXTCLK system clock status */
2839 /* CS_STAT[REFOCLK_ON] Bits */
2840 #define CS_STAT_REFOCLK_ON_OFS                   (23)                            /*!< REFOCLK_ON Bit Offset */
2841 #define CS_STAT_REFOCLK_ON                       ((uint32_t)0x00800000)          /*!< REFOCLK system clock status */
2842 /* CS_STAT[ACLK_READY] Bits */
2843 #define CS_STAT_ACLK_READY_OFS                   (24)                            /*!< ACLK_READY Bit Offset */
2844 #define CS_STAT_ACLK_READY                       ((uint32_t)0x01000000)          /*!< ACLK Ready status */
2845 /* CS_STAT[MCLK_READY] Bits */
2846 #define CS_STAT_MCLK_READY_OFS                   (25)                            /*!< MCLK_READY Bit Offset */
2847 #define CS_STAT_MCLK_READY                       ((uint32_t)0x02000000)          /*!< MCLK Ready status */
2848 /* CS_STAT[HSMCLK_READY] Bits */
2849 #define CS_STAT_HSMCLK_READY_OFS                 (26)                            /*!< HSMCLK_READY Bit Offset */
2850 #define CS_STAT_HSMCLK_READY                     ((uint32_t)0x04000000)          /*!< HSMCLK Ready status */
2851 /* CS_STAT[SMCLK_READY] Bits */
2852 #define CS_STAT_SMCLK_READY_OFS                  (27)                            /*!< SMCLK_READY Bit Offset */
2853 #define CS_STAT_SMCLK_READY                      ((uint32_t)0x08000000)          /*!< SMCLK Ready status */
2854 /* CS_STAT[BCLK_READY] Bits */
2855 #define CS_STAT_BCLK_READY_OFS                   (28)                            /*!< BCLK_READY Bit Offset */
2856 #define CS_STAT_BCLK_READY                       ((uint32_t)0x10000000)          /*!< BCLK Ready status */
2857 /* CS_IE[LFXTIE] Bits */
2858 #define CS_IE_LFXTIE_OFS                         ( 0)                            /*!< LFXTIE Bit Offset */
2859 #define CS_IE_LFXTIE                             ((uint32_t)0x00000001)          /*!< LFXT oscillator fault flag interrupt enable */
2860 /* CS_IE[HFXTIE] Bits */
2861 #define CS_IE_HFXTIE_OFS                         ( 1)                            /*!< HFXTIE Bit Offset */
2862 #define CS_IE_HFXTIE                             ((uint32_t)0x00000002)          /*!< HFXT oscillator fault flag interrupt enable */
2863 /* CS_IE[DCOR_OPNIE] Bits */
2864 #define CS_IE_DCOR_OPNIE_OFS                     ( 6)                            /*!< DCOR_OPNIE Bit Offset */
2865 #define CS_IE_DCOR_OPNIE                         ((uint32_t)0x00000040)          /*!< DCO external resistor open circuit fault flag interrupt enable. */
2866 /* CS_IE[FCNTLFIE] Bits */
2867 #define CS_IE_FCNTLFIE_OFS                       ( 8)                            /*!< FCNTLFIE Bit Offset */
2868 #define CS_IE_FCNTLFIE                           ((uint32_t)0x00000100)          /*!< Start fault counter interrupt enable LFXT */
2869 /* CS_IE[FCNTHFIE] Bits */
2870 #define CS_IE_FCNTHFIE_OFS                       ( 9)                            /*!< FCNTHFIE Bit Offset */
2871 #define CS_IE_FCNTHFIE                           ((uint32_t)0x00000200)          /*!< Start fault counter interrupt enable HFXT */
2872 /* CS_IFG[LFXTIFG] Bits */
2873 #define CS_IFG_LFXTIFG_OFS                       ( 0)                            /*!< LFXTIFG Bit Offset */
2874 #define CS_IFG_LFXTIFG                           ((uint32_t)0x00000001)          /*!< LFXT oscillator fault flag */
2875 /* CS_IFG[HFXTIFG] Bits */
2876 #define CS_IFG_HFXTIFG_OFS                       ( 1)                            /*!< HFXTIFG Bit Offset */
2877 #define CS_IFG_HFXTIFG                           ((uint32_t)0x00000002)          /*!< HFXT oscillator fault flag */
2878 /* CS_IFG[DCOR_SHTIFG] Bits */
2879 #define CS_IFG_DCOR_SHTIFG_OFS                   ( 5)                            /*!< DCOR_SHTIFG Bit Offset */
2880 #define CS_IFG_DCOR_SHTIFG                       ((uint32_t)0x00000020)          /*!< DCO external resistor short circuit fault flag. */
2881 /* CS_IFG[DCOR_OPNIFG] Bits */
2882 #define CS_IFG_DCOR_OPNIFG_OFS                   ( 6)                            /*!< DCOR_OPNIFG Bit Offset */
2883 #define CS_IFG_DCOR_OPNIFG                       ((uint32_t)0x00000040)          /*!< DCO external resistor open circuit fault flag. */
2884 /* CS_IFG[FCNTLFIFG] Bits */
2885 #define CS_IFG_FCNTLFIFG_OFS                     ( 8)                            /*!< FCNTLFIFG Bit Offset */
2886 #define CS_IFG_FCNTLFIFG                         ((uint32_t)0x00000100)          /*!< Start fault counter interrupt flag LFXT */
2887 /* CS_IFG[FCNTHFIFG] Bits */
2888 #define CS_IFG_FCNTHFIFG_OFS                     ( 9)                            /*!< FCNTHFIFG Bit Offset */
2889 #define CS_IFG_FCNTHFIFG                         ((uint32_t)0x00000200)          /*!< Start fault counter interrupt flag HFXT */
2890 /* CS_CLRIFG[CLR_LFXTIFG] Bits */
2891 #define CS_CLRIFG_CLR_LFXTIFG_OFS                ( 0)                            /*!< CLR_LFXTIFG Bit Offset */
2892 #define CS_CLRIFG_CLR_LFXTIFG                    ((uint32_t)0x00000001)          /*!< Clear LFXT oscillator fault interrupt flag */
2893 /* CS_CLRIFG[CLR_HFXTIFG] Bits */
2894 #define CS_CLRIFG_CLR_HFXTIFG_OFS                ( 1)                            /*!< CLR_HFXTIFG Bit Offset */
2895 #define CS_CLRIFG_CLR_HFXTIFG                    ((uint32_t)0x00000002)          /*!< Clear HFXT oscillator fault interrupt flag */
2896 /* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */
2897 #define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS            ( 6)                            /*!< CLR_DCOR_OPNIFG Bit Offset */
2898 #define CS_CLRIFG_CLR_DCOR_OPNIFG                ((uint32_t)0x00000040)          /*!< Clear DCO external resistor open circuit fault interrupt flag. */
2899 /* CS_CLRIFG[CLR_FCNTLFIFG] Bits */
2900 #define CS_CLRIFG_CLR_FCNTLFIFG_OFS              ( 8)                            /*!< CLR_FCNTLFIFG Bit Offset */
2901 #define CS_CLRIFG_CLR_FCNTLFIFG                  ((uint32_t)0x00000100)          /*!< Start fault counter clear interrupt flag LFXT */
2902 /* CS_CLRIFG[CLR_FCNTHFIFG] Bits */
2903 #define CS_CLRIFG_CLR_FCNTHFIFG_OFS              ( 9)                            /*!< CLR_FCNTHFIFG Bit Offset */
2904 #define CS_CLRIFG_CLR_FCNTHFIFG                  ((uint32_t)0x00000200)          /*!< Start fault counter clear interrupt flag HFXT */
2905 /* CS_SETIFG[SET_LFXTIFG] Bits */
2906 #define CS_SETIFG_SET_LFXTIFG_OFS                ( 0)                            /*!< SET_LFXTIFG Bit Offset */
2907 #define CS_SETIFG_SET_LFXTIFG                    ((uint32_t)0x00000001)          /*!< Set LFXT oscillator fault interrupt flag */
2908 /* CS_SETIFG[SET_HFXTIFG] Bits */
2909 #define CS_SETIFG_SET_HFXTIFG_OFS                ( 1)                            /*!< SET_HFXTIFG Bit Offset */
2910 #define CS_SETIFG_SET_HFXTIFG                    ((uint32_t)0x00000002)          /*!< Set HFXT oscillator fault interrupt flag */
2911 /* CS_SETIFG[SET_DCOR_OPNIFG] Bits */
2912 #define CS_SETIFG_SET_DCOR_OPNIFG_OFS            ( 6)                            /*!< SET_DCOR_OPNIFG Bit Offset */
2913 #define CS_SETIFG_SET_DCOR_OPNIFG                ((uint32_t)0x00000040)          /*!< Set DCO external resistor open circuit fault interrupt flag. */
2914 /* CS_SETIFG[SET_FCNTHFIFG] Bits */
2915 #define CS_SETIFG_SET_FCNTHFIFG_OFS              ( 9)                            /*!< SET_FCNTHFIFG Bit Offset */
2916 #define CS_SETIFG_SET_FCNTHFIFG                  ((uint32_t)0x00000200)          /*!< Start fault counter set interrupt flag HFXT */
2917 /* CS_SETIFG[SET_FCNTLFIFG] Bits */
2918 #define CS_SETIFG_SET_FCNTLFIFG_OFS              ( 8)                            /*!< SET_FCNTLFIFG Bit Offset */
2919 #define CS_SETIFG_SET_FCNTLFIFG                  ((uint32_t)0x00000100)          /*!< Start fault counter set interrupt flag LFXT */
2920 /* CS_DCOERCAL0[DCO_TCCAL] Bits */
2921 #define CS_DCOERCAL0_DCO_TCCAL_OFS               ( 0)                            /*!< DCO_TCCAL Bit Offset */
2922 #define CS_DCOERCAL0_DCO_TCCAL_MASK              ((uint32_t)0x00000003)          /*!< DCO_TCCAL Bit Mask */
2923 /* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */
2924 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS         (16)                            /*!< DCO_FCAL_RSEL04 Bit Offset */
2925 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK        ((uint32_t)0x03FF0000)          /*!< DCO_FCAL_RSEL04 Bit Mask */
2926 /* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */
2927 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS          ( 0)                            /*!< DCO_FCAL_RSEL5 Bit Offset */
2928 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK         ((uint32_t)0x000003FF)          /*!< DCO_FCAL_RSEL5 Bit Mask */
2929 /* Pre-defined bitfield values */
2930 #define CS_KEY_VAL                               ((uint32_t)0x0000695A)          /*!< CS control key value */
2931 
2932 /******************************************************************************
2933 * DIO Bits
2934 ******************************************************************************/
2935 /* DIO_IV[IV] Bits */
2936 #define DIO_PORT_IV_OFS                          ( 0)                            /*!< DIO Port IV Bit Offset */
2937 #define DIO_PORT_IV_MASK                         ((uint16_t)0x001F)              /*!< DIO Port IV Bit Mask */
2938 #define DIO_PORT_IV0                             ((uint16_t)0x0001)              /*!< DIO Port IV Bit 0 */
2939 #define DIO_PORT_IV1                             ((uint16_t)0x0002)              /*!< DIO Port IV Bit 1 */
2940 #define DIO_PORT_IV2                             ((uint16_t)0x0004)              /*!< DIO Port IV Bit 2 */
2941 #define DIO_PORT_IV3                             ((uint16_t)0x0008)              /*!< DIO Port IV Bit 3 */
2942 #define DIO_PORT_IV4                             ((uint16_t)0x0010)              /*!< DIO Port IV Bit 4 */
2943 #define DIO_PORT_IV_0                            ((uint16_t)0x0000)              /*!< No interrupt pending */
2944 #define DIO_PORT_IV_2                            ((uint16_t)0x0002)              /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt  */
2945                                                                                  /* Priority: Highest */
2946 #define DIO_PORT_IV_4                            ((uint16_t)0x0004)              /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */
2947 #define DIO_PORT_IV_6                            ((uint16_t)0x0006)              /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */
2948 #define DIO_PORT_IV_8                            ((uint16_t)0x0008)              /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */
2949 #define DIO_PORT_IV_10                           ((uint16_t)0x000A)              /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */
2950 #define DIO_PORT_IV_12                           ((uint16_t)0x000C)              /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */
2951 #define DIO_PORT_IV_14                           ((uint16_t)0x000E)              /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */
2952 #define DIO_PORT_IV_16                           ((uint16_t)0x0010)              /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt  */
2953                                                                                  /* Priority: Lowest */
2954 #define DIO_PORT_IV__NONE                        ((uint16_t)0x0000)              /*!< No interrupt pending */
2955 #define DIO_PORT_IV__IFG0                        ((uint16_t)0x0002)              /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt  */
2956                                                                                  /* Priority: Highest */
2957 #define DIO_PORT_IV__IFG1                        ((uint16_t)0x0004)              /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */
2958 #define DIO_PORT_IV__IFG2                        ((uint16_t)0x0006)              /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */
2959 #define DIO_PORT_IV__IFG3                        ((uint16_t)0x0008)              /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */
2960 #define DIO_PORT_IV__IFG4                        ((uint16_t)0x000A)              /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */
2961 #define DIO_PORT_IV__IFG5                        ((uint16_t)0x000C)              /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */
2962 #define DIO_PORT_IV__IFG6                        ((uint16_t)0x000E)              /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */
2963 #define DIO_PORT_IV__IFG7                        ((uint16_t)0x0010)              /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt  */
2964                                                                                  /* Priority: Lowest */
2965 
2966 
2967 /******************************************************************************
2968 * DMA Bits
2969 ******************************************************************************/
2970 /* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */
2971 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS      ( 0)                            /*!< NUM_DMA_CHANNELS Bit Offset */
2972 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK     ((uint32_t)0x000000FF)          /*!< NUM_DMA_CHANNELS Bit Mask */
2973 /* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */
2974 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS   ( 8)                            /*!< NUM_SRC_PER_CHANNEL Bit Offset */
2975 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK  ((uint32_t)0x0000FF00)          /*!< NUM_SRC_PER_CHANNEL Bit Mask */
2976 /* DMA_SW_CHTRIG[CH0] Bits */
2977 #define DMA_SW_CHTRIG_CH0_OFS                    ( 0)                            /*!< CH0 Bit Offset */
2978 #define DMA_SW_CHTRIG_CH0                        ((uint32_t)0x00000001)          /*!< Write 1, triggers DMA_CHANNEL0 */
2979 /* DMA_SW_CHTRIG[CH1] Bits */
2980 #define DMA_SW_CHTRIG_CH1_OFS                    ( 1)                            /*!< CH1 Bit Offset */
2981 #define DMA_SW_CHTRIG_CH1                        ((uint32_t)0x00000002)          /*!< Write 1, triggers DMA_CHANNEL1 */
2982 /* DMA_SW_CHTRIG[CH2] Bits */
2983 #define DMA_SW_CHTRIG_CH2_OFS                    ( 2)                            /*!< CH2 Bit Offset */
2984 #define DMA_SW_CHTRIG_CH2                        ((uint32_t)0x00000004)          /*!< Write 1, triggers DMA_CHANNEL2 */
2985 /* DMA_SW_CHTRIG[CH3] Bits */
2986 #define DMA_SW_CHTRIG_CH3_OFS                    ( 3)                            /*!< CH3 Bit Offset */
2987 #define DMA_SW_CHTRIG_CH3                        ((uint32_t)0x00000008)          /*!< Write 1, triggers DMA_CHANNEL3 */
2988 /* DMA_SW_CHTRIG[CH4] Bits */
2989 #define DMA_SW_CHTRIG_CH4_OFS                    ( 4)                            /*!< CH4 Bit Offset */
2990 #define DMA_SW_CHTRIG_CH4                        ((uint32_t)0x00000010)          /*!< Write 1, triggers DMA_CHANNEL4 */
2991 /* DMA_SW_CHTRIG[CH5] Bits */
2992 #define DMA_SW_CHTRIG_CH5_OFS                    ( 5)                            /*!< CH5 Bit Offset */
2993 #define DMA_SW_CHTRIG_CH5                        ((uint32_t)0x00000020)          /*!< Write 1, triggers DMA_CHANNEL5 */
2994 /* DMA_SW_CHTRIG[CH6] Bits */
2995 #define DMA_SW_CHTRIG_CH6_OFS                    ( 6)                            /*!< CH6 Bit Offset */
2996 #define DMA_SW_CHTRIG_CH6                        ((uint32_t)0x00000040)          /*!< Write 1, triggers DMA_CHANNEL6 */
2997 /* DMA_SW_CHTRIG[CH7] Bits */
2998 #define DMA_SW_CHTRIG_CH7_OFS                    ( 7)                            /*!< CH7 Bit Offset */
2999 #define DMA_SW_CHTRIG_CH7                        ((uint32_t)0x00000080)          /*!< Write 1, triggers DMA_CHANNEL7 */
3000 /* DMA_SW_CHTRIG[CH8] Bits */
3001 #define DMA_SW_CHTRIG_CH8_OFS                    ( 8)                            /*!< CH8 Bit Offset */
3002 #define DMA_SW_CHTRIG_CH8                        ((uint32_t)0x00000100)          /*!< Write 1, triggers DMA_CHANNEL8 */
3003 /* DMA_SW_CHTRIG[CH9] Bits */
3004 #define DMA_SW_CHTRIG_CH9_OFS                    ( 9)                            /*!< CH9 Bit Offset */
3005 #define DMA_SW_CHTRIG_CH9                        ((uint32_t)0x00000200)          /*!< Write 1, triggers DMA_CHANNEL9 */
3006 /* DMA_SW_CHTRIG[CH10] Bits */
3007 #define DMA_SW_CHTRIG_CH10_OFS                   (10)                            /*!< CH10 Bit Offset */
3008 #define DMA_SW_CHTRIG_CH10                       ((uint32_t)0x00000400)          /*!< Write 1, triggers DMA_CHANNEL10 */
3009 /* DMA_SW_CHTRIG[CH11] Bits */
3010 #define DMA_SW_CHTRIG_CH11_OFS                   (11)                            /*!< CH11 Bit Offset */
3011 #define DMA_SW_CHTRIG_CH11                       ((uint32_t)0x00000800)          /*!< Write 1, triggers DMA_CHANNEL11 */
3012 /* DMA_SW_CHTRIG[CH12] Bits */
3013 #define DMA_SW_CHTRIG_CH12_OFS                   (12)                            /*!< CH12 Bit Offset */
3014 #define DMA_SW_CHTRIG_CH12                       ((uint32_t)0x00001000)          /*!< Write 1, triggers DMA_CHANNEL12 */
3015 /* DMA_SW_CHTRIG[CH13] Bits */
3016 #define DMA_SW_CHTRIG_CH13_OFS                   (13)                            /*!< CH13 Bit Offset */
3017 #define DMA_SW_CHTRIG_CH13                       ((uint32_t)0x00002000)          /*!< Write 1, triggers DMA_CHANNEL13 */
3018 /* DMA_SW_CHTRIG[CH14] Bits */
3019 #define DMA_SW_CHTRIG_CH14_OFS                   (14)                            /*!< CH14 Bit Offset */
3020 #define DMA_SW_CHTRIG_CH14                       ((uint32_t)0x00004000)          /*!< Write 1, triggers DMA_CHANNEL14 */
3021 /* DMA_SW_CHTRIG[CH15] Bits */
3022 #define DMA_SW_CHTRIG_CH15_OFS                   (15)                            /*!< CH15 Bit Offset */
3023 #define DMA_SW_CHTRIG_CH15                       ((uint32_t)0x00008000)          /*!< Write 1, triggers DMA_CHANNEL15 */
3024 /* DMA_SW_CHTRIG[CH16] Bits */
3025 #define DMA_SW_CHTRIG_CH16_OFS                   (16)                            /*!< CH16 Bit Offset */
3026 #define DMA_SW_CHTRIG_CH16                       ((uint32_t)0x00010000)          /*!< Write 1, triggers DMA_CHANNEL16 */
3027 /* DMA_SW_CHTRIG[CH17] Bits */
3028 #define DMA_SW_CHTRIG_CH17_OFS                   (17)                            /*!< CH17 Bit Offset */
3029 #define DMA_SW_CHTRIG_CH17                       ((uint32_t)0x00020000)          /*!< Write 1, triggers DMA_CHANNEL17 */
3030 /* DMA_SW_CHTRIG[CH18] Bits */
3031 #define DMA_SW_CHTRIG_CH18_OFS                   (18)                            /*!< CH18 Bit Offset */
3032 #define DMA_SW_CHTRIG_CH18                       ((uint32_t)0x00040000)          /*!< Write 1, triggers DMA_CHANNEL18 */
3033 /* DMA_SW_CHTRIG[CH19] Bits */
3034 #define DMA_SW_CHTRIG_CH19_OFS                   (19)                            /*!< CH19 Bit Offset */
3035 #define DMA_SW_CHTRIG_CH19                       ((uint32_t)0x00080000)          /*!< Write 1, triggers DMA_CHANNEL19 */
3036 /* DMA_SW_CHTRIG[CH20] Bits */
3037 #define DMA_SW_CHTRIG_CH20_OFS                   (20)                            /*!< CH20 Bit Offset */
3038 #define DMA_SW_CHTRIG_CH20                       ((uint32_t)0x00100000)          /*!< Write 1, triggers DMA_CHANNEL20 */
3039 /* DMA_SW_CHTRIG[CH21] Bits */
3040 #define DMA_SW_CHTRIG_CH21_OFS                   (21)                            /*!< CH21 Bit Offset */
3041 #define DMA_SW_CHTRIG_CH21                       ((uint32_t)0x00200000)          /*!< Write 1, triggers DMA_CHANNEL21 */
3042 /* DMA_SW_CHTRIG[CH22] Bits */
3043 #define DMA_SW_CHTRIG_CH22_OFS                   (22)                            /*!< CH22 Bit Offset */
3044 #define DMA_SW_CHTRIG_CH22                       ((uint32_t)0x00400000)          /*!< Write 1, triggers DMA_CHANNEL22 */
3045 /* DMA_SW_CHTRIG[CH23] Bits */
3046 #define DMA_SW_CHTRIG_CH23_OFS                   (23)                            /*!< CH23 Bit Offset */
3047 #define DMA_SW_CHTRIG_CH23                       ((uint32_t)0x00800000)          /*!< Write 1, triggers DMA_CHANNEL23 */
3048 /* DMA_SW_CHTRIG[CH24] Bits */
3049 #define DMA_SW_CHTRIG_CH24_OFS                   (24)                            /*!< CH24 Bit Offset */
3050 #define DMA_SW_CHTRIG_CH24                       ((uint32_t)0x01000000)          /*!< Write 1, triggers DMA_CHANNEL24 */
3051 /* DMA_SW_CHTRIG[CH25] Bits */
3052 #define DMA_SW_CHTRIG_CH25_OFS                   (25)                            /*!< CH25 Bit Offset */
3053 #define DMA_SW_CHTRIG_CH25                       ((uint32_t)0x02000000)          /*!< Write 1, triggers DMA_CHANNEL25 */
3054 /* DMA_SW_CHTRIG[CH26] Bits */
3055 #define DMA_SW_CHTRIG_CH26_OFS                   (26)                            /*!< CH26 Bit Offset */
3056 #define DMA_SW_CHTRIG_CH26                       ((uint32_t)0x04000000)          /*!< Write 1, triggers DMA_CHANNEL26 */
3057 /* DMA_SW_CHTRIG[CH27] Bits */
3058 #define DMA_SW_CHTRIG_CH27_OFS                   (27)                            /*!< CH27 Bit Offset */
3059 #define DMA_SW_CHTRIG_CH27                       ((uint32_t)0x08000000)          /*!< Write 1, triggers DMA_CHANNEL27 */
3060 /* DMA_SW_CHTRIG[CH28] Bits */
3061 #define DMA_SW_CHTRIG_CH28_OFS                   (28)                            /*!< CH28 Bit Offset */
3062 #define DMA_SW_CHTRIG_CH28                       ((uint32_t)0x10000000)          /*!< Write 1, triggers DMA_CHANNEL28 */
3063 /* DMA_SW_CHTRIG[CH29] Bits */
3064 #define DMA_SW_CHTRIG_CH29_OFS                   (29)                            /*!< CH29 Bit Offset */
3065 #define DMA_SW_CHTRIG_CH29                       ((uint32_t)0x20000000)          /*!< Write 1, triggers DMA_CHANNEL29 */
3066 /* DMA_SW_CHTRIG[CH30] Bits */
3067 #define DMA_SW_CHTRIG_CH30_OFS                   (30)                            /*!< CH30 Bit Offset */
3068 #define DMA_SW_CHTRIG_CH30                       ((uint32_t)0x40000000)          /*!< Write 1, triggers DMA_CHANNEL30 */
3069 /* DMA_SW_CHTRIG[CH31] Bits */
3070 #define DMA_SW_CHTRIG_CH31_OFS                   (31)                            /*!< CH31 Bit Offset */
3071 #define DMA_SW_CHTRIG_CH31                       ((uint32_t)0x80000000)          /*!< Write 1, triggers DMA_CHANNEL31 */
3072 /* DMA_CHN_SRCCFG[DMA_SRC] Bits */
3073 #define DMA_CHN_SRCCFG_DMA_SRC_OFS               ( 0)                            /*!< DMA_SRC Bit Offset */
3074 #define DMA_CHN_SRCCFG_DMA_SRC_MASK              ((uint32_t)0x000000FF)          /*!< DMA_SRC Bit Mask */
3075 /* DMA_INT1_SRCCFG[INT_SRC] Bits */
3076 #define DMA_INT1_SRCCFG_INT_SRC_OFS              ( 0)                            /*!< INT_SRC Bit Offset */
3077 #define DMA_INT1_SRCCFG_INT_SRC_MASK             ((uint32_t)0x0000001F)          /*!< INT_SRC Bit Mask */
3078 /* DMA_INT1_SRCCFG[EN] Bits */
3079 #define DMA_INT1_SRCCFG_EN_OFS                   ( 5)                            /*!< EN Bit Offset */
3080 #define DMA_INT1_SRCCFG_EN                       ((uint32_t)0x00000020)          /*!< Enables DMA_INT1 mapping */
3081 /* DMA_INT2_SRCCFG[INT_SRC] Bits */
3082 #define DMA_INT2_SRCCFG_INT_SRC_OFS              ( 0)                            /*!< INT_SRC Bit Offset */
3083 #define DMA_INT2_SRCCFG_INT_SRC_MASK             ((uint32_t)0x0000001F)          /*!< INT_SRC Bit Mask */
3084 /* DMA_INT2_SRCCFG[EN] Bits */
3085 #define DMA_INT2_SRCCFG_EN_OFS                   ( 5)                            /*!< EN Bit Offset */
3086 #define DMA_INT2_SRCCFG_EN                       ((uint32_t)0x00000020)          /*!< Enables DMA_INT2 mapping */
3087 /* DMA_INT3_SRCCFG[INT_SRC] Bits */
3088 #define DMA_INT3_SRCCFG_INT_SRC_OFS              ( 0)                            /*!< INT_SRC Bit Offset */
3089 #define DMA_INT3_SRCCFG_INT_SRC_MASK             ((uint32_t)0x0000001F)          /*!< INT_SRC Bit Mask */
3090 /* DMA_INT3_SRCCFG[EN] Bits */
3091 #define DMA_INT3_SRCCFG_EN_OFS                   ( 5)                            /*!< EN Bit Offset */
3092 #define DMA_INT3_SRCCFG_EN                       ((uint32_t)0x00000020)          /*!< Enables DMA_INT3 mapping */
3093 /* DMA_INT0_SRCFLG[CH0] Bits */
3094 #define DMA_INT0_SRCFLG_CH0_OFS                  ( 0)                            /*!< CH0 Bit Offset */
3095 #define DMA_INT0_SRCFLG_CH0                      ((uint32_t)0x00000001)          /*!< Channel 0 was the source of DMA_INT0 */
3096 /* DMA_INT0_SRCFLG[CH1] Bits */
3097 #define DMA_INT0_SRCFLG_CH1_OFS                  ( 1)                            /*!< CH1 Bit Offset */
3098 #define DMA_INT0_SRCFLG_CH1                      ((uint32_t)0x00000002)          /*!< Channel 1 was the source of DMA_INT0 */
3099 /* DMA_INT0_SRCFLG[CH2] Bits */
3100 #define DMA_INT0_SRCFLG_CH2_OFS                  ( 2)                            /*!< CH2 Bit Offset */
3101 #define DMA_INT0_SRCFLG_CH2                      ((uint32_t)0x00000004)          /*!< Channel 2 was the source of DMA_INT0 */
3102 /* DMA_INT0_SRCFLG[CH3] Bits */
3103 #define DMA_INT0_SRCFLG_CH3_OFS                  ( 3)                            /*!< CH3 Bit Offset */
3104 #define DMA_INT0_SRCFLG_CH3                      ((uint32_t)0x00000008)          /*!< Channel 3 was the source of DMA_INT0 */
3105 /* DMA_INT0_SRCFLG[CH4] Bits */
3106 #define DMA_INT0_SRCFLG_CH4_OFS                  ( 4)                            /*!< CH4 Bit Offset */
3107 #define DMA_INT0_SRCFLG_CH4                      ((uint32_t)0x00000010)          /*!< Channel 4 was the source of DMA_INT0 */
3108 /* DMA_INT0_SRCFLG[CH5] Bits */
3109 #define DMA_INT0_SRCFLG_CH5_OFS                  ( 5)                            /*!< CH5 Bit Offset */
3110 #define DMA_INT0_SRCFLG_CH5                      ((uint32_t)0x00000020)          /*!< Channel 5 was the source of DMA_INT0 */
3111 /* DMA_INT0_SRCFLG[CH6] Bits */
3112 #define DMA_INT0_SRCFLG_CH6_OFS                  ( 6)                            /*!< CH6 Bit Offset */
3113 #define DMA_INT0_SRCFLG_CH6                      ((uint32_t)0x00000040)          /*!< Channel 6 was the source of DMA_INT0 */
3114 /* DMA_INT0_SRCFLG[CH7] Bits */
3115 #define DMA_INT0_SRCFLG_CH7_OFS                  ( 7)                            /*!< CH7 Bit Offset */
3116 #define DMA_INT0_SRCFLG_CH7                      ((uint32_t)0x00000080)          /*!< Channel 7 was the source of DMA_INT0 */
3117 /* DMA_INT0_SRCFLG[CH8] Bits */
3118 #define DMA_INT0_SRCFLG_CH8_OFS                  ( 8)                            /*!< CH8 Bit Offset */
3119 #define DMA_INT0_SRCFLG_CH8                      ((uint32_t)0x00000100)          /*!< Channel 8 was the source of DMA_INT0 */
3120 /* DMA_INT0_SRCFLG[CH9] Bits */
3121 #define DMA_INT0_SRCFLG_CH9_OFS                  ( 9)                            /*!< CH9 Bit Offset */
3122 #define DMA_INT0_SRCFLG_CH9                      ((uint32_t)0x00000200)          /*!< Channel 9 was the source of DMA_INT0 */
3123 /* DMA_INT0_SRCFLG[CH10] Bits */
3124 #define DMA_INT0_SRCFLG_CH10_OFS                 (10)                            /*!< CH10 Bit Offset */
3125 #define DMA_INT0_SRCFLG_CH10                     ((uint32_t)0x00000400)          /*!< Channel 10 was the source of DMA_INT0 */
3126 /* DMA_INT0_SRCFLG[CH11] Bits */
3127 #define DMA_INT0_SRCFLG_CH11_OFS                 (11)                            /*!< CH11 Bit Offset */
3128 #define DMA_INT0_SRCFLG_CH11                     ((uint32_t)0x00000800)          /*!< Channel 11 was the source of DMA_INT0 */
3129 /* DMA_INT0_SRCFLG[CH12] Bits */
3130 #define DMA_INT0_SRCFLG_CH12_OFS                 (12)                            /*!< CH12 Bit Offset */
3131 #define DMA_INT0_SRCFLG_CH12                     ((uint32_t)0x00001000)          /*!< Channel 12 was the source of DMA_INT0 */
3132 /* DMA_INT0_SRCFLG[CH13] Bits */
3133 #define DMA_INT0_SRCFLG_CH13_OFS                 (13)                            /*!< CH13 Bit Offset */
3134 #define DMA_INT0_SRCFLG_CH13                     ((uint32_t)0x00002000)          /*!< Channel 13 was the source of DMA_INT0 */
3135 /* DMA_INT0_SRCFLG[CH14] Bits */
3136 #define DMA_INT0_SRCFLG_CH14_OFS                 (14)                            /*!< CH14 Bit Offset */
3137 #define DMA_INT0_SRCFLG_CH14                     ((uint32_t)0x00004000)          /*!< Channel 14 was the source of DMA_INT0 */
3138 /* DMA_INT0_SRCFLG[CH15] Bits */
3139 #define DMA_INT0_SRCFLG_CH15_OFS                 (15)                            /*!< CH15 Bit Offset */
3140 #define DMA_INT0_SRCFLG_CH15                     ((uint32_t)0x00008000)          /*!< Channel 15 was the source of DMA_INT0 */
3141 /* DMA_INT0_SRCFLG[CH16] Bits */
3142 #define DMA_INT0_SRCFLG_CH16_OFS                 (16)                            /*!< CH16 Bit Offset */
3143 #define DMA_INT0_SRCFLG_CH16                     ((uint32_t)0x00010000)          /*!< Channel 16 was the source of DMA_INT0 */
3144 /* DMA_INT0_SRCFLG[CH17] Bits */
3145 #define DMA_INT0_SRCFLG_CH17_OFS                 (17)                            /*!< CH17 Bit Offset */
3146 #define DMA_INT0_SRCFLG_CH17                     ((uint32_t)0x00020000)          /*!< Channel 17 was the source of DMA_INT0 */
3147 /* DMA_INT0_SRCFLG[CH18] Bits */
3148 #define DMA_INT0_SRCFLG_CH18_OFS                 (18)                            /*!< CH18 Bit Offset */
3149 #define DMA_INT0_SRCFLG_CH18                     ((uint32_t)0x00040000)          /*!< Channel 18 was the source of DMA_INT0 */
3150 /* DMA_INT0_SRCFLG[CH19] Bits */
3151 #define DMA_INT0_SRCFLG_CH19_OFS                 (19)                            /*!< CH19 Bit Offset */
3152 #define DMA_INT0_SRCFLG_CH19                     ((uint32_t)0x00080000)          /*!< Channel 19 was the source of DMA_INT0 */
3153 /* DMA_INT0_SRCFLG[CH20] Bits */
3154 #define DMA_INT0_SRCFLG_CH20_OFS                 (20)                            /*!< CH20 Bit Offset */
3155 #define DMA_INT0_SRCFLG_CH20                     ((uint32_t)0x00100000)          /*!< Channel 20 was the source of DMA_INT0 */
3156 /* DMA_INT0_SRCFLG[CH21] Bits */
3157 #define DMA_INT0_SRCFLG_CH21_OFS                 (21)                            /*!< CH21 Bit Offset */
3158 #define DMA_INT0_SRCFLG_CH21                     ((uint32_t)0x00200000)          /*!< Channel 21 was the source of DMA_INT0 */
3159 /* DMA_INT0_SRCFLG[CH22] Bits */
3160 #define DMA_INT0_SRCFLG_CH22_OFS                 (22)                            /*!< CH22 Bit Offset */
3161 #define DMA_INT0_SRCFLG_CH22                     ((uint32_t)0x00400000)          /*!< Channel 22 was the source of DMA_INT0 */
3162 /* DMA_INT0_SRCFLG[CH23] Bits */
3163 #define DMA_INT0_SRCFLG_CH23_OFS                 (23)                            /*!< CH23 Bit Offset */
3164 #define DMA_INT0_SRCFLG_CH23                     ((uint32_t)0x00800000)          /*!< Channel 23 was the source of DMA_INT0 */
3165 /* DMA_INT0_SRCFLG[CH24] Bits */
3166 #define DMA_INT0_SRCFLG_CH24_OFS                 (24)                            /*!< CH24 Bit Offset */
3167 #define DMA_INT0_SRCFLG_CH24                     ((uint32_t)0x01000000)          /*!< Channel 24 was the source of DMA_INT0 */
3168 /* DMA_INT0_SRCFLG[CH25] Bits */
3169 #define DMA_INT0_SRCFLG_CH25_OFS                 (25)                            /*!< CH25 Bit Offset */
3170 #define DMA_INT0_SRCFLG_CH25                     ((uint32_t)0x02000000)          /*!< Channel 25 was the source of DMA_INT0 */
3171 /* DMA_INT0_SRCFLG[CH26] Bits */
3172 #define DMA_INT0_SRCFLG_CH26_OFS                 (26)                            /*!< CH26 Bit Offset */
3173 #define DMA_INT0_SRCFLG_CH26                     ((uint32_t)0x04000000)          /*!< Channel 26 was the source of DMA_INT0 */
3174 /* DMA_INT0_SRCFLG[CH27] Bits */
3175 #define DMA_INT0_SRCFLG_CH27_OFS                 (27)                            /*!< CH27 Bit Offset */
3176 #define DMA_INT0_SRCFLG_CH27                     ((uint32_t)0x08000000)          /*!< Channel 27 was the source of DMA_INT0 */
3177 /* DMA_INT0_SRCFLG[CH28] Bits */
3178 #define DMA_INT0_SRCFLG_CH28_OFS                 (28)                            /*!< CH28 Bit Offset */
3179 #define DMA_INT0_SRCFLG_CH28                     ((uint32_t)0x10000000)          /*!< Channel 28 was the source of DMA_INT0 */
3180 /* DMA_INT0_SRCFLG[CH29] Bits */
3181 #define DMA_INT0_SRCFLG_CH29_OFS                 (29)                            /*!< CH29 Bit Offset */
3182 #define DMA_INT0_SRCFLG_CH29                     ((uint32_t)0x20000000)          /*!< Channel 29 was the source of DMA_INT0 */
3183 /* DMA_INT0_SRCFLG[CH30] Bits */
3184 #define DMA_INT0_SRCFLG_CH30_OFS                 (30)                            /*!< CH30 Bit Offset */
3185 #define DMA_INT0_SRCFLG_CH30                     ((uint32_t)0x40000000)          /*!< Channel 30 was the source of DMA_INT0 */
3186 /* DMA_INT0_SRCFLG[CH31] Bits */
3187 #define DMA_INT0_SRCFLG_CH31_OFS                 (31)                            /*!< CH31 Bit Offset */
3188 #define DMA_INT0_SRCFLG_CH31                     ((uint32_t)0x80000000)          /*!< Channel 31 was the source of DMA_INT0 */
3189 /* DMA_INT0_CLRFLG[CH0] Bits */
3190 #define DMA_INT0_CLRFLG_CH0_OFS                  ( 0)                            /*!< CH0 Bit Offset */
3191 #define DMA_INT0_CLRFLG_CH0                      ((uint32_t)0x00000001)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3192 /* DMA_INT0_CLRFLG[CH1] Bits */
3193 #define DMA_INT0_CLRFLG_CH1_OFS                  ( 1)                            /*!< CH1 Bit Offset */
3194 #define DMA_INT0_CLRFLG_CH1                      ((uint32_t)0x00000002)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3195 /* DMA_INT0_CLRFLG[CH2] Bits */
3196 #define DMA_INT0_CLRFLG_CH2_OFS                  ( 2)                            /*!< CH2 Bit Offset */
3197 #define DMA_INT0_CLRFLG_CH2                      ((uint32_t)0x00000004)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3198 /* DMA_INT0_CLRFLG[CH3] Bits */
3199 #define DMA_INT0_CLRFLG_CH3_OFS                  ( 3)                            /*!< CH3 Bit Offset */
3200 #define DMA_INT0_CLRFLG_CH3                      ((uint32_t)0x00000008)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3201 /* DMA_INT0_CLRFLG[CH4] Bits */
3202 #define DMA_INT0_CLRFLG_CH4_OFS                  ( 4)                            /*!< CH4 Bit Offset */
3203 #define DMA_INT0_CLRFLG_CH4                      ((uint32_t)0x00000010)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3204 /* DMA_INT0_CLRFLG[CH5] Bits */
3205 #define DMA_INT0_CLRFLG_CH5_OFS                  ( 5)                            /*!< CH5 Bit Offset */
3206 #define DMA_INT0_CLRFLG_CH5                      ((uint32_t)0x00000020)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3207 /* DMA_INT0_CLRFLG[CH6] Bits */
3208 #define DMA_INT0_CLRFLG_CH6_OFS                  ( 6)                            /*!< CH6 Bit Offset */
3209 #define DMA_INT0_CLRFLG_CH6                      ((uint32_t)0x00000040)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3210 /* DMA_INT0_CLRFLG[CH7] Bits */
3211 #define DMA_INT0_CLRFLG_CH7_OFS                  ( 7)                            /*!< CH7 Bit Offset */
3212 #define DMA_INT0_CLRFLG_CH7                      ((uint32_t)0x00000080)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3213 /* DMA_INT0_CLRFLG[CH8] Bits */
3214 #define DMA_INT0_CLRFLG_CH8_OFS                  ( 8)                            /*!< CH8 Bit Offset */
3215 #define DMA_INT0_CLRFLG_CH8                      ((uint32_t)0x00000100)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3216 /* DMA_INT0_CLRFLG[CH9] Bits */
3217 #define DMA_INT0_CLRFLG_CH9_OFS                  ( 9)                            /*!< CH9 Bit Offset */
3218 #define DMA_INT0_CLRFLG_CH9                      ((uint32_t)0x00000200)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3219 /* DMA_INT0_CLRFLG[CH10] Bits */
3220 #define DMA_INT0_CLRFLG_CH10_OFS                 (10)                            /*!< CH10 Bit Offset */
3221 #define DMA_INT0_CLRFLG_CH10                     ((uint32_t)0x00000400)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3222 /* DMA_INT0_CLRFLG[CH11] Bits */
3223 #define DMA_INT0_CLRFLG_CH11_OFS                 (11)                            /*!< CH11 Bit Offset */
3224 #define DMA_INT0_CLRFLG_CH11                     ((uint32_t)0x00000800)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3225 /* DMA_INT0_CLRFLG[CH12] Bits */
3226 #define DMA_INT0_CLRFLG_CH12_OFS                 (12)                            /*!< CH12 Bit Offset */
3227 #define DMA_INT0_CLRFLG_CH12                     ((uint32_t)0x00001000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3228 /* DMA_INT0_CLRFLG[CH13] Bits */
3229 #define DMA_INT0_CLRFLG_CH13_OFS                 (13)                            /*!< CH13 Bit Offset */
3230 #define DMA_INT0_CLRFLG_CH13                     ((uint32_t)0x00002000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3231 /* DMA_INT0_CLRFLG[CH14] Bits */
3232 #define DMA_INT0_CLRFLG_CH14_OFS                 (14)                            /*!< CH14 Bit Offset */
3233 #define DMA_INT0_CLRFLG_CH14                     ((uint32_t)0x00004000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3234 /* DMA_INT0_CLRFLG[CH15] Bits */
3235 #define DMA_INT0_CLRFLG_CH15_OFS                 (15)                            /*!< CH15 Bit Offset */
3236 #define DMA_INT0_CLRFLG_CH15                     ((uint32_t)0x00008000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3237 /* DMA_INT0_CLRFLG[CH16] Bits */
3238 #define DMA_INT0_CLRFLG_CH16_OFS                 (16)                            /*!< CH16 Bit Offset */
3239 #define DMA_INT0_CLRFLG_CH16                     ((uint32_t)0x00010000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3240 /* DMA_INT0_CLRFLG[CH17] Bits */
3241 #define DMA_INT0_CLRFLG_CH17_OFS                 (17)                            /*!< CH17 Bit Offset */
3242 #define DMA_INT0_CLRFLG_CH17                     ((uint32_t)0x00020000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3243 /* DMA_INT0_CLRFLG[CH18] Bits */
3244 #define DMA_INT0_CLRFLG_CH18_OFS                 (18)                            /*!< CH18 Bit Offset */
3245 #define DMA_INT0_CLRFLG_CH18                     ((uint32_t)0x00040000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3246 /* DMA_INT0_CLRFLG[CH19] Bits */
3247 #define DMA_INT0_CLRFLG_CH19_OFS                 (19)                            /*!< CH19 Bit Offset */
3248 #define DMA_INT0_CLRFLG_CH19                     ((uint32_t)0x00080000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3249 /* DMA_INT0_CLRFLG[CH20] Bits */
3250 #define DMA_INT0_CLRFLG_CH20_OFS                 (20)                            /*!< CH20 Bit Offset */
3251 #define DMA_INT0_CLRFLG_CH20                     ((uint32_t)0x00100000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3252 /* DMA_INT0_CLRFLG[CH21] Bits */
3253 #define DMA_INT0_CLRFLG_CH21_OFS                 (21)                            /*!< CH21 Bit Offset */
3254 #define DMA_INT0_CLRFLG_CH21                     ((uint32_t)0x00200000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3255 /* DMA_INT0_CLRFLG[CH22] Bits */
3256 #define DMA_INT0_CLRFLG_CH22_OFS                 (22)                            /*!< CH22 Bit Offset */
3257 #define DMA_INT0_CLRFLG_CH22                     ((uint32_t)0x00400000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3258 /* DMA_INT0_CLRFLG[CH23] Bits */
3259 #define DMA_INT0_CLRFLG_CH23_OFS                 (23)                            /*!< CH23 Bit Offset */
3260 #define DMA_INT0_CLRFLG_CH23                     ((uint32_t)0x00800000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3261 /* DMA_INT0_CLRFLG[CH24] Bits */
3262 #define DMA_INT0_CLRFLG_CH24_OFS                 (24)                            /*!< CH24 Bit Offset */
3263 #define DMA_INT0_CLRFLG_CH24                     ((uint32_t)0x01000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3264 /* DMA_INT0_CLRFLG[CH25] Bits */
3265 #define DMA_INT0_CLRFLG_CH25_OFS                 (25)                            /*!< CH25 Bit Offset */
3266 #define DMA_INT0_CLRFLG_CH25                     ((uint32_t)0x02000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3267 /* DMA_INT0_CLRFLG[CH26] Bits */
3268 #define DMA_INT0_CLRFLG_CH26_OFS                 (26)                            /*!< CH26 Bit Offset */
3269 #define DMA_INT0_CLRFLG_CH26                     ((uint32_t)0x04000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3270 /* DMA_INT0_CLRFLG[CH27] Bits */
3271 #define DMA_INT0_CLRFLG_CH27_OFS                 (27)                            /*!< CH27 Bit Offset */
3272 #define DMA_INT0_CLRFLG_CH27                     ((uint32_t)0x08000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3273 /* DMA_INT0_CLRFLG[CH28] Bits */
3274 #define DMA_INT0_CLRFLG_CH28_OFS                 (28)                            /*!< CH28 Bit Offset */
3275 #define DMA_INT0_CLRFLG_CH28                     ((uint32_t)0x10000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3276 /* DMA_INT0_CLRFLG[CH29] Bits */
3277 #define DMA_INT0_CLRFLG_CH29_OFS                 (29)                            /*!< CH29 Bit Offset */
3278 #define DMA_INT0_CLRFLG_CH29                     ((uint32_t)0x20000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3279 /* DMA_INT0_CLRFLG[CH30] Bits */
3280 #define DMA_INT0_CLRFLG_CH30_OFS                 (30)                            /*!< CH30 Bit Offset */
3281 #define DMA_INT0_CLRFLG_CH30                     ((uint32_t)0x40000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3282 /* DMA_INT0_CLRFLG[CH31] Bits */
3283 #define DMA_INT0_CLRFLG_CH31_OFS                 (31)                            /*!< CH31 Bit Offset */
3284 #define DMA_INT0_CLRFLG_CH31                     ((uint32_t)0x80000000)          /*!< Clear corresponding DMA_INT0_SRCFLG_REG */
3285 /* DMA_STAT[MASTEN] Bits */
3286 #define DMA_STAT_MASTEN_OFS                      ( 0)                            /*!< MASTEN Bit Offset */
3287 #define DMA_STAT_MASTEN                          ((uint32_t)0x00000001)
3288 /* DMA_STAT[STATE] Bits */
3289 #define DMA_STAT_STATE_OFS                       ( 4)                            /*!< STATE Bit Offset */
3290 #define DMA_STAT_STATE_MASK                      ((uint32_t)0x000000F0)          /*!< STATE Bit Mask */
3291 #define DMA_STAT_STATE0                          ((uint32_t)0x00000010)          /*!< STATE Bit 0 */
3292 #define DMA_STAT_STATE1                          ((uint32_t)0x00000020)          /*!< STATE Bit 1 */
3293 #define DMA_STAT_STATE2                          ((uint32_t)0x00000040)          /*!< STATE Bit 2 */
3294 #define DMA_STAT_STATE3                          ((uint32_t)0x00000080)          /*!< STATE Bit 3 */
3295 #define DMA_STAT_STATE_0                         ((uint32_t)0x00000000)          /*!< idle */
3296 #define DMA_STAT_STATE_1                         ((uint32_t)0x00000010)          /*!< reading channel controller data */
3297 #define DMA_STAT_STATE_2                         ((uint32_t)0x00000020)          /*!< reading source data end pointer */
3298 #define DMA_STAT_STATE_3                         ((uint32_t)0x00000030)          /*!< reading destination data end pointer */
3299 #define DMA_STAT_STATE_4                         ((uint32_t)0x00000040)          /*!< reading source data */
3300 #define DMA_STAT_STATE_5                         ((uint32_t)0x00000050)          /*!< writing destination data */
3301 #define DMA_STAT_STATE_6                         ((uint32_t)0x00000060)          /*!< waiting for DMA request to clear */
3302 #define DMA_STAT_STATE_7                         ((uint32_t)0x00000070)          /*!< writing channel controller data */
3303 #define DMA_STAT_STATE_8                         ((uint32_t)0x00000080)          /*!< stalled */
3304 #define DMA_STAT_STATE_9                         ((uint32_t)0x00000090)          /*!< done */
3305 #define DMA_STAT_STATE_10                        ((uint32_t)0x000000A0)          /*!< peripheral scatter-gather transition */
3306 #define DMA_STAT_STATE_11                        ((uint32_t)0x000000B0)          /*!< Reserved */
3307 #define DMA_STAT_STATE_12                        ((uint32_t)0x000000C0)          /*!< Reserved */
3308 #define DMA_STAT_STATE_13                        ((uint32_t)0x000000D0)          /*!< Reserved */
3309 #define DMA_STAT_STATE_14                        ((uint32_t)0x000000E0)          /*!< Reserved */
3310 #define DMA_STAT_STATE_15                        ((uint32_t)0x000000F0)          /*!< Reserved */
3311 /* DMA_STAT[DMACHANS] Bits */
3312 #define DMA_STAT_DMACHANS_OFS                    (16)                            /*!< DMACHANS Bit Offset */
3313 #define DMA_STAT_DMACHANS_MASK                   ((uint32_t)0x001F0000)          /*!< DMACHANS Bit Mask */
3314 #define DMA_STAT_DMACHANS0                       ((uint32_t)0x00010000)          /*!< DMACHANS Bit 0 */
3315 #define DMA_STAT_DMACHANS1                       ((uint32_t)0x00020000)          /*!< DMACHANS Bit 1 */
3316 #define DMA_STAT_DMACHANS2                       ((uint32_t)0x00040000)          /*!< DMACHANS Bit 2 */
3317 #define DMA_STAT_DMACHANS3                       ((uint32_t)0x00080000)          /*!< DMACHANS Bit 3 */
3318 #define DMA_STAT_DMACHANS4                       ((uint32_t)0x00100000)          /*!< DMACHANS Bit 4 */
3319 #define DMA_STAT_DMACHANS_0                      ((uint32_t)0x00000000)          /*!< Controller configured to use 1 DMA channel */
3320 #define DMA_STAT_DMACHANS_1                      ((uint32_t)0x00010000)          /*!< Controller configured to use 2 DMA channels */
3321 #define DMA_STAT_DMACHANS_30                     ((uint32_t)0x001E0000)          /*!< Controller configured to use 31 DMA channels */
3322 #define DMA_STAT_DMACHANS_31                     ((uint32_t)0x001F0000)          /*!< Controller configured to use 32 DMA channels */
3323 /* DMA_STAT[TESTSTAT] Bits */
3324 #define DMA_STAT_TESTSTAT_OFS                    (28)                            /*!< TESTSTAT Bit Offset */
3325 #define DMA_STAT_TESTSTAT_MASK                   ((uint32_t)0xF0000000)          /*!< TESTSTAT Bit Mask */
3326 #define DMA_STAT_TESTSTAT0                       ((uint32_t)0x10000000)          /*!< TESTSTAT Bit 0 */
3327 #define DMA_STAT_TESTSTAT1                       ((uint32_t)0x20000000)          /*!< TESTSTAT Bit 1 */
3328 #define DMA_STAT_TESTSTAT2                       ((uint32_t)0x40000000)          /*!< TESTSTAT Bit 2 */
3329 #define DMA_STAT_TESTSTAT3                       ((uint32_t)0x80000000)          /*!< TESTSTAT Bit 3 */
3330 #define DMA_STAT_TESTSTAT_0                      ((uint32_t)0x00000000)          /*!< Controller does not include the integration test logic */
3331 #define DMA_STAT_TESTSTAT_1                      ((uint32_t)0x10000000)          /*!< Controller includes the integration test logic */
3332 /* DMA_CFG[MASTEN] Bits */
3333 #define DMA_CFG_MASTEN_OFS                       ( 0)                            /*!< MASTEN Bit Offset */
3334 #define DMA_CFG_MASTEN                           ((uint32_t)0x00000001)
3335 /* DMA_CFG[CHPROTCTRL] Bits */
3336 #define DMA_CFG_CHPROTCTRL_OFS                   ( 5)                            /*!< CHPROTCTRL Bit Offset */
3337 #define DMA_CFG_CHPROTCTRL_MASK                  ((uint32_t)0x000000E0)          /*!< CHPROTCTRL Bit Mask */
3338 /* DMA_CTLBASE[ADDR] Bits */
3339 #define DMA_CTLBASE_ADDR_OFS                     ( 5)                            /*!< ADDR Bit Offset */
3340 #define DMA_CTLBASE_ADDR_MASK                    ((uint32_t)0xFFFFFFE0)          /*!< ADDR Bit Mask */
3341 /* DMA_ERRCLR[ERRCLR] Bits */
3342 #define DMA_ERRCLR_ERRCLR_OFS                    ( 0)                            /*!< ERRCLR Bit Offset */
3343 #define DMA_ERRCLR_ERRCLR                        ((uint32_t)0x00000001)
3344 /* DMA channel definitions and memory structure alignment */
3345 #define __MCU_NUM_DMA_CHANNELS__                8
3346 #define DMA_CHANNEL_CONTROL_STRUCT_SIZE         0x10
3347 #define DMA_CONTROL_MEMORY_ALIGNMENT            (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE)
3348 
3349 /* UDMA_STAT Control Bits */
3350 #define UDMA_STAT_DMACHANS_M                    ((uint32_t)0x001F0000)           /*!< Available uDMA Channels Minus 1 */
3351 #define UDMA_STAT_STATE_M                       ((uint32_t)0x000000F0)           /*!< Control State Machine Status */
3352 #define UDMA_STAT_STATE_IDLE                    ((uint32_t)0x00000000)           /*!< Idle */
3353 #define UDMA_STAT_STATE_RD_CTRL                 ((uint32_t)0x00000010)           /*!< Reading channel controller data */
3354 #define UDMA_STAT_STATE_RD_SRCENDP              ((uint32_t)0x00000020)           /*!< Reading source end pointer */
3355 #define UDMA_STAT_STATE_RD_DSTENDP              ((uint32_t)0x00000030)           /*!< Reading destination end pointer */
3356 #define UDMA_STAT_STATE_RD_SRCDAT               ((uint32_t)0x00000040)           /*!< Reading source data */
3357 #define UDMA_STAT_STATE_WR_DSTDAT               ((uint32_t)0x00000050)           /*!< Writing destination data */
3358 #define UDMA_STAT_STATE_WAIT                    ((uint32_t)0x00000060)           /*!< Waiting for uDMA request to clear */
3359 #define UDMA_STAT_STATE_WR_CTRL                 ((uint32_t)0x00000070)           /*!< Writing channel controller data */
3360 #define UDMA_STAT_STATE_STALL                   ((uint32_t)0x00000080)           /*!< Stalled */
3361 #define UDMA_STAT_STATE_DONE                    ((uint32_t)0x00000090)           /*!< Done */
3362 #define UDMA_STAT_STATE_UNDEF                   ((uint32_t)0x000000A0)           /*!< Undefined */
3363 #define UDMA_STAT_MASTEN                        ((uint32_t)0x00000001)           /*!< Master Enable Status */
3364 #define UDMA_STAT_DMACHANS_S                    (16)
3365 
3366 /* UDMA_CFG Control Bits */
3367 #define UDMA_CFG_MASTEN                         ((uint32_t)0x00000001)           /*!< Controller Master Enable */
3368 
3369 /* UDMA_CTLBASE Control Bits */
3370 #define UDMA_CTLBASE_ADDR_M                     ((uint32_t)0xFFFFFC00)           /*!< Channel Control Base Address */
3371 #define UDMA_CTLBASE_ADDR_S                     (10)
3372 
3373 /* UDMA_ALTBASE Control Bits */
3374 #define UDMA_ALTBASE_ADDR_M                     ((uint32_t)0xFFFFFFFF)           /*!< Alternate Channel Address Pointer */
3375 #define UDMA_ALTBASE_ADDR_S                     ( 0)
3376 
3377 /* UDMA_WAITSTAT Control Bits */
3378 #define UDMA_WAITSTAT_WAITREQ_M                 ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Wait Status */
3379 
3380 /* UDMA_SWREQ Control Bits */
3381 #define UDMA_SWREQ_M                            ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Software Request */
3382 
3383 /* UDMA_USEBURSTSET Control Bits */
3384 #define UDMA_USEBURSTSET_SET_M                  ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Useburst Set */
3385 
3386 /* UDMA_USEBURSTCLR Control Bits */
3387 #define UDMA_USEBURSTCLR_CLR_M                  ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Useburst Clear */
3388 
3389 /* UDMA_REQMASKSET Control Bits */
3390 #define UDMA_REQMASKSET_SET_M                   ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Request Mask Set */
3391 
3392 /* UDMA_REQMASKCLR Control Bits */
3393 #define UDMA_REQMASKCLR_CLR_M                   ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Request Mask Clear */
3394 
3395 /* UDMA_ENASET Control Bits */
3396 #define UDMA_ENASET_SET_M                       ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Enable Set */
3397 
3398 /* UDMA_ENACLR Control Bits */
3399 #define UDMA_ENACLR_CLR_M                       ((uint32_t)0xFFFFFFFF)           /*!< Clear Channel [n] Enable Clear */
3400 
3401 /* UDMA_ALTSET Control Bits */
3402 #define UDMA_ALTSET_SET_M                       ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Alternate Set */
3403 
3404 /* UDMA_ALTCLR Control Bits */
3405 #define UDMA_ALTCLR_CLR_M                       ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Alternate Clear */
3406 
3407 /* UDMA_PRIOSET Control Bits */
3408 #define UDMA_PRIOSET_SET_M                      ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Priority Set */
3409 
3410 /* UDMA_PRIOCLR Control Bits */
3411 #define UDMA_PRIOCLR_CLR_M                      ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Priority Clear */
3412 
3413 /* UDMA_ERRCLR Control Bits */
3414 #define UDMA_ERRCLR_ERRCLR                      ((uint32_t)0x00000001)           /*!< uDMA Bus Error Status */
3415 
3416 /* UDMA_CHASGN Control Bits */
3417 #define UDMA_CHASGN_M                           ((uint32_t)0xFFFFFFFF)           /*!< Channel [n] Assignment Select */
3418 #define UDMA_CHASGN_PRIMARY                     ((uint32_t)0x00000000)           /*!< Use the primary channel assignment */
3419 #define UDMA_CHASGN_SECONDARY                   ((uint32_t)0x00000001)           /*!< Use the secondary channel assignment */
3420 
3421 /* Micro Direct Memory Access (uDMA) offsets */
3422 #define UDMA_O_SRCENDP                          ((uint32_t)0x00000000)           /*!< DMA Channel Source Address End Pointer */
3423 #define UDMA_O_DSTENDP                          ((uint32_t)0x00000004)           /*!< DMA Channel Destination Address End Pointer */
3424 #define UDMA_O_CHCTL                            ((uint32_t)0x00000008)           /*!< DMA Channel Control Word */
3425 
3426 /* UDMA_O_SRCENDP Control Bits */
3427 #define UDMA_SRCENDP_ADDR_M                     ((uint32_t)0xFFFFFFFF)           /*!< Source Address End Pointer */
3428 #define UDMA_SRCENDP_ADDR_S                     ( 0)
3429 
3430 /* UDMA_O_DSTENDP Control Bits */
3431 #define UDMA_DSTENDP_ADDR_M                     ((uint32_t)0xFFFFFFFF)           /*!< Destination Address End Pointer */
3432 #define UDMA_DSTENDP_ADDR_S                     ( 0)
3433 
3434 /* UDMA_O_CHCTL Control Bits */
3435 #define UDMA_CHCTL_DSTINC_M                     ((uint32_t)0xC0000000)           /*!< Destination Address Increment */
3436 #define UDMA_CHCTL_DSTINC_8                     ((uint32_t)0x00000000)           /*!< Byte */
3437 #define UDMA_CHCTL_DSTINC_16                    ((uint32_t)0x40000000)           /*!< Half-word */
3438 #define UDMA_CHCTL_DSTINC_32                    ((uint32_t)0x80000000)           /*!< Word */
3439 #define UDMA_CHCTL_DSTINC_NONE                  ((uint32_t)0xC0000000)           /*!< No increment */
3440 #define UDMA_CHCTL_DSTSIZE_M                    ((uint32_t)0x30000000)           /*!< Destination Data Size */
3441 #define UDMA_CHCTL_DSTSIZE_8                    ((uint32_t)0x00000000)           /*!< Byte */
3442 #define UDMA_CHCTL_DSTSIZE_16                   ((uint32_t)0x10000000)           /*!< Half-word */
3443 #define UDMA_CHCTL_DSTSIZE_32                   ((uint32_t)0x20000000)           /*!< Word */
3444 #define UDMA_CHCTL_SRCINC_M                     ((uint32_t)0x0C000000)           /*!< Source Address Increment */
3445 #define UDMA_CHCTL_SRCINC_8                     ((uint32_t)0x00000000)           /*!< Byte */
3446 #define UDMA_CHCTL_SRCINC_16                    ((uint32_t)0x04000000)           /*!< Half-word */
3447 #define UDMA_CHCTL_SRCINC_32                    ((uint32_t)0x08000000)           /*!< Word */
3448 #define UDMA_CHCTL_SRCINC_NONE                  ((uint32_t)0x0C000000)           /*!< No increment */
3449 #define UDMA_CHCTL_SRCSIZE_M                    ((uint32_t)0x03000000)           /*!< Source Data Size */
3450 #define UDMA_CHCTL_SRCSIZE_8                    ((uint32_t)0x00000000)           /*!< Byte */
3451 #define UDMA_CHCTL_SRCSIZE_16                   ((uint32_t)0x01000000)           /*!< Half-word */
3452 #define UDMA_CHCTL_SRCSIZE_32                   ((uint32_t)0x02000000)           /*!< Word */
3453 #define UDMA_CHCTL_ARBSIZE_M                    ((uint32_t)0x0003C000)           /*!< Arbitration Size */
3454 #define UDMA_CHCTL_ARBSIZE_1                    ((uint32_t)0x00000000)           /*!< 1 Transfer */
3455 #define UDMA_CHCTL_ARBSIZE_2                    ((uint32_t)0x00004000)           /*!< 2 Transfers */
3456 #define UDMA_CHCTL_ARBSIZE_4                    ((uint32_t)0x00008000)           /*!< 4 Transfers */
3457 #define UDMA_CHCTL_ARBSIZE_8                    ((uint32_t)0x0000C000)           /*!< 8 Transfers */
3458 #define UDMA_CHCTL_ARBSIZE_16                   ((uint32_t)0x00010000)           /*!< 16 Transfers */
3459 #define UDMA_CHCTL_ARBSIZE_32                   ((uint32_t)0x00014000)           /*!< 32 Transfers */
3460 #define UDMA_CHCTL_ARBSIZE_64                   ((uint32_t)0x00018000)           /*!< 64 Transfers */
3461 #define UDMA_CHCTL_ARBSIZE_128                  ((uint32_t)0x0001C000)           /*!< 128 Transfers */
3462 #define UDMA_CHCTL_ARBSIZE_256                  ((uint32_t)0x00020000)           /*!< 256 Transfers */
3463 #define UDMA_CHCTL_ARBSIZE_512                  ((uint32_t)0x00024000)           /*!< 512 Transfers */
3464 #define UDMA_CHCTL_ARBSIZE_1024                 ((uint32_t)0x00028000)           /*!< 1024 Transfers */
3465 #define UDMA_CHCTL_XFERSIZE_M                   ((uint32_t)0x00003FF0)           /*!< Transfer Size (minus 1) */
3466 #define UDMA_CHCTL_NXTUSEBURST                  ((uint32_t)0x00000008)           /*!< Next Useburst */
3467 #define UDMA_CHCTL_XFERMODE_M                   ((uint32_t)0x00000007)           /*!< uDMA Transfer Mode */
3468 #define UDMA_CHCTL_XFERMODE_STOP                ((uint32_t)0x00000000)           /*!< Stop */
3469 #define UDMA_CHCTL_XFERMODE_BASIC               ((uint32_t)0x00000001)           /*!< Basic */
3470 #define UDMA_CHCTL_XFERMODE_AUTO                ((uint32_t)0x00000002)           /*!< Auto-Request */
3471 #define UDMA_CHCTL_XFERMODE_PINGPONG            ((uint32_t)0x00000003)           /*!< Ping-Pong */
3472 #define UDMA_CHCTL_XFERMODE_MEM_SG              ((uint32_t)0x00000004)           /*!< Memory Scatter-Gather */
3473 #define UDMA_CHCTL_XFERMODE_MEM_SGA             ((uint32_t)0x00000005)           /*!< Alternate Memory Scatter-Gather */
3474 #define UDMA_CHCTL_XFERMODE_PER_SG              ((uint32_t)0x00000006)           /*!< Peripheral Scatter-Gather */
3475 #define UDMA_CHCTL_XFERMODE_PER_SGA             ((uint32_t)0x00000007)           /*!< Alternate Peripheral Scatter-Gather */
3476 
3477 #define UDMA_CHCTL_XFERSIZE_S                   ( 4)
3478 
3479 
3480 /******************************************************************************
3481 * DWT Bits
3482 ******************************************************************************/
3483 
3484 
3485 /******************************************************************************
3486 * EUSCI_A Bits
3487 ******************************************************************************/
3488 /* EUSCI_A_CTLW0[SWRST] Bits */
3489 #define EUSCI_A_CTLW0_SWRST_OFS                  ( 0)                            /*!< UCSWRST Bit Offset */
3490 #define EUSCI_A_CTLW0_SWRST                      ((uint16_t)0x0001)              /*!< Software reset enable */
3491 /* EUSCI_A_CTLW0[TXBRK] Bits */
3492 #define EUSCI_A_CTLW0_TXBRK_OFS                  ( 1)                            /*!< UCTXBRK Bit Offset */
3493 #define EUSCI_A_CTLW0_TXBRK                      ((uint16_t)0x0002)              /*!< Transmit break */
3494 /* EUSCI_A_CTLW0[TXADDR] Bits */
3495 #define EUSCI_A_CTLW0_TXADDR_OFS                 ( 2)                            /*!< UCTXADDR Bit Offset */
3496 #define EUSCI_A_CTLW0_TXADDR                     ((uint16_t)0x0004)              /*!< Transmit address */
3497 /* EUSCI_A_CTLW0[DORM] Bits */
3498 #define EUSCI_A_CTLW0_DORM_OFS                   ( 3)                            /*!< UCDORM Bit Offset */
3499 #define EUSCI_A_CTLW0_DORM                       ((uint16_t)0x0008)              /*!< Dormant */
3500 /* EUSCI_A_CTLW0[BRKIE] Bits */
3501 #define EUSCI_A_CTLW0_BRKIE_OFS                  ( 4)                            /*!< UCBRKIE Bit Offset */
3502 #define EUSCI_A_CTLW0_BRKIE                      ((uint16_t)0x0010)              /*!< Receive break character interrupt enable */
3503 /* EUSCI_A_CTLW0[RXEIE] Bits */
3504 #define EUSCI_A_CTLW0_RXEIE_OFS                  ( 5)                            /*!< UCRXEIE Bit Offset */
3505 #define EUSCI_A_CTLW0_RXEIE                      ((uint16_t)0x0020)              /*!< Receive erroneous-character interrupt enable */
3506 /* EUSCI_A_CTLW0[SSEL] Bits */
3507 #define EUSCI_A_CTLW0_SSEL_OFS                   ( 6)                            /*!< UCSSEL Bit Offset */
3508 #define EUSCI_A_CTLW0_SSEL_MASK                  ((uint16_t)0x00C0)              /*!< UCSSEL Bit Mask */
3509 #define EUSCI_A_CTLW0_SSEL0                      ((uint16_t)0x0040)              /*!< SSEL Bit 0 */
3510 #define EUSCI_A_CTLW0_SSEL1                      ((uint16_t)0x0080)              /*!< SSEL Bit 1 */
3511 #define EUSCI_A_CTLW0_UCSSEL_0                   ((uint16_t)0x0000)              /*!< UCLK */
3512 #define EUSCI_A_CTLW0_UCSSEL_1                   ((uint16_t)0x0040)              /*!< ACLK */
3513 #define EUSCI_A_CTLW0_UCSSEL_2                   ((uint16_t)0x0080)              /*!< SMCLK */
3514 #define EUSCI_A_CTLW0_SSEL__UCLK                 ((uint16_t)0x0000)              /*!< UCLK */
3515 #define EUSCI_A_CTLW0_SSEL__ACLK                 ((uint16_t)0x0040)              /*!< ACLK */
3516 #define EUSCI_A_CTLW0_SSEL__SMCLK                ((uint16_t)0x0080)              /*!< SMCLK */
3517 /* EUSCI_A_CTLW0[SYNC] Bits */
3518 #define EUSCI_A_CTLW0_SYNC_OFS                   ( 8)                            /*!< UCSYNC Bit Offset */
3519 #define EUSCI_A_CTLW0_SYNC                       ((uint16_t)0x0100)              /*!< Synchronous mode enable */
3520 /* EUSCI_A_CTLW0[MODE] Bits */
3521 #define EUSCI_A_CTLW0_MODE_OFS                   ( 9)                            /*!< UCMODE Bit Offset */
3522 #define EUSCI_A_CTLW0_MODE_MASK                  ((uint16_t)0x0600)              /*!< UCMODE Bit Mask */
3523 #define EUSCI_A_CTLW0_MODE0                      ((uint16_t)0x0200)              /*!< MODE Bit 0 */
3524 #define EUSCI_A_CTLW0_MODE1                      ((uint16_t)0x0400)              /*!< MODE Bit 1 */
3525 #define EUSCI_A_CTLW0_MODE_0                     ((uint16_t)0x0000)              /*!< UART mode */
3526 #define EUSCI_A_CTLW0_MODE_1                     ((uint16_t)0x0200)              /*!< Idle-line multiprocessor mode */
3527 #define EUSCI_A_CTLW0_MODE_2                     ((uint16_t)0x0400)              /*!< Address-bit multiprocessor mode */
3528 #define EUSCI_A_CTLW0_MODE_3                     ((uint16_t)0x0600)              /*!< UART mode with automatic baud-rate detection */
3529 /* EUSCI_A_CTLW0[SPB] Bits */
3530 #define EUSCI_A_CTLW0_SPB_OFS                    (11)                            /*!< UCSPB Bit Offset */
3531 #define EUSCI_A_CTLW0_SPB                        ((uint16_t)0x0800)              /*!< Stop bit select */
3532 /* EUSCI_A_CTLW0[SEVENBIT] Bits */
3533 #define EUSCI_A_CTLW0_SEVENBIT_OFS               (12)                            /*!< UC7BIT Bit Offset */
3534 #define EUSCI_A_CTLW0_SEVENBIT                   ((uint16_t)0x1000)              /*!< Character length */
3535 /* EUSCI_A_CTLW0[MSB] Bits */
3536 #define EUSCI_A_CTLW0_MSB_OFS                    (13)                            /*!< UCMSB Bit Offset */
3537 #define EUSCI_A_CTLW0_MSB                        ((uint16_t)0x2000)              /*!< MSB first select */
3538 /* EUSCI_A_CTLW0[PAR] Bits */
3539 #define EUSCI_A_CTLW0_PAR_OFS                    (14)                            /*!< UCPAR Bit Offset */
3540 #define EUSCI_A_CTLW0_PAR                        ((uint16_t)0x4000)              /*!< Parity select */
3541 /* EUSCI_A_CTLW0[PEN] Bits */
3542 #define EUSCI_A_CTLW0_PEN_OFS                    (15)                            /*!< UCPEN Bit Offset */
3543 #define EUSCI_A_CTLW0_PEN                        ((uint16_t)0x8000)              /*!< Parity enable */
3544 /* EUSCI_A_CTLW0[STEM] Bits */
3545 #define EUSCI_A_CTLW0_STEM_OFS                   ( 1)                            /*!< UCSTEM Bit Offset */
3546 #define EUSCI_A_CTLW0_STEM                       ((uint16_t)0x0002)              /*!< STE mode select in master mode. */
3547 /* EUSCI_A_CTLW0[MST] Bits */
3548 #define EUSCI_A_CTLW0_MST_OFS                    (11)                            /*!< UCMST Bit Offset */
3549 #define EUSCI_A_CTLW0_MST                        ((uint16_t)0x0800)              /*!< Master mode select */
3550 /* EUSCI_A_CTLW0[CKPL] Bits */
3551 #define EUSCI_A_CTLW0_CKPL_OFS                   (14)                            /*!< UCCKPL Bit Offset */
3552 #define EUSCI_A_CTLW0_CKPL                       ((uint16_t)0x4000)              /*!< Clock polarity select */
3553 /* EUSCI_A_CTLW0[CKPH] Bits */
3554 #define EUSCI_A_CTLW0_CKPH_OFS                   (15)                            /*!< UCCKPH Bit Offset */
3555 #define EUSCI_A_CTLW0_CKPH                       ((uint16_t)0x8000)              /*!< Clock phase select */
3556 /* EUSCI_A_CTLW1[GLIT] Bits */
3557 #define EUSCI_A_CTLW1_GLIT_OFS                   ( 0)                            /*!< UCGLIT Bit Offset */
3558 #define EUSCI_A_CTLW1_GLIT_MASK                  ((uint16_t)0x0003)              /*!< UCGLIT Bit Mask */
3559 #define EUSCI_A_CTLW1_GLIT0                      ((uint16_t)0x0001)              /*!< GLIT Bit 0 */
3560 #define EUSCI_A_CTLW1_GLIT1                      ((uint16_t)0x0002)              /*!< GLIT Bit 1 */
3561 #define EUSCI_A_CTLW1_GLIT_0                     ((uint16_t)0x0000)              /*!< Approximately 2 ns (equivalent of 1 delay element) */
3562 #define EUSCI_A_CTLW1_GLIT_1                     ((uint16_t)0x0001)              /*!< Approximately 50 ns */
3563 #define EUSCI_A_CTLW1_GLIT_2                     ((uint16_t)0x0002)              /*!< Approximately 100 ns */
3564 #define EUSCI_A_CTLW1_GLIT_3                     ((uint16_t)0x0003)              /*!< Approximately 200 ns */
3565 /* EUSCI_A_MCTLW[OS16] Bits */
3566 #define EUSCI_A_MCTLW_OS16_OFS                   ( 0)                            /*!< UCOS16 Bit Offset */
3567 #define EUSCI_A_MCTLW_OS16                       ((uint16_t)0x0001)              /*!< Oversampling mode enabled */
3568 /* EUSCI_A_MCTLW[BRF] Bits */
3569 #define EUSCI_A_MCTLW_BRF_OFS                    ( 4)                            /*!< UCBRF Bit Offset */
3570 #define EUSCI_A_MCTLW_BRF_MASK                   ((uint16_t)0x00F0)              /*!< UCBRF Bit Mask */
3571 /* EUSCI_A_MCTLW[BRS] Bits */
3572 #define EUSCI_A_MCTLW_BRS_OFS                    ( 8)                            /*!< UCBRS Bit Offset */
3573 #define EUSCI_A_MCTLW_BRS_MASK                   ((uint16_t)0xFF00)              /*!< UCBRS Bit Mask */
3574 /* EUSCI_A_STATW[BUSY] Bits */
3575 #define EUSCI_A_STATW_BUSY_OFS                   ( 0)                            /*!< UCBUSY Bit Offset */
3576 #define EUSCI_A_STATW_BUSY                       ((uint16_t)0x0001)              /*!< eUSCI_A busy */
3577 /* EUSCI_A_STATW[ADDR_IDLE] Bits */
3578 #define EUSCI_A_STATW_ADDR_IDLE_OFS              ( 1)                            /*!< UCADDR_UCIDLE Bit Offset */
3579 #define EUSCI_A_STATW_ADDR_IDLE                  ((uint16_t)0x0002)              /*!< Address received / Idle line detected */
3580 /* EUSCI_A_STATW[RXERR] Bits */
3581 #define EUSCI_A_STATW_RXERR_OFS                  ( 2)                            /*!< UCRXERR Bit Offset */
3582 #define EUSCI_A_STATW_RXERR                      ((uint16_t)0x0004)              /*!< Receive error flag */
3583 /* EUSCI_A_STATW[BRK] Bits */
3584 #define EUSCI_A_STATW_BRK_OFS                    ( 3)                            /*!< UCBRK Bit Offset */
3585 #define EUSCI_A_STATW_BRK                        ((uint16_t)0x0008)              /*!< Break detect flag */
3586 /* EUSCI_A_STATW[PE] Bits */
3587 #define EUSCI_A_STATW_PE_OFS                     ( 4)                            /*!< UCPE Bit Offset */
3588 #define EUSCI_A_STATW_PE                         ((uint16_t)0x0010)
3589 /* EUSCI_A_STATW[OE] Bits */
3590 #define EUSCI_A_STATW_OE_OFS                     ( 5)                            /*!< UCOE Bit Offset */
3591 #define EUSCI_A_STATW_OE                         ((uint16_t)0x0020)              /*!< Overrun error flag */
3592 /* EUSCI_A_STATW[FE] Bits */
3593 #define EUSCI_A_STATW_FE_OFS                     ( 6)                            /*!< UCFE Bit Offset */
3594 #define EUSCI_A_STATW_FE                         ((uint16_t)0x0040)              /*!< Framing error flag */
3595 /* EUSCI_A_STATW[LISTEN] Bits */
3596 #define EUSCI_A_STATW_LISTEN_OFS                 ( 7)                            /*!< UCLISTEN Bit Offset */
3597 #define EUSCI_A_STATW_LISTEN                     ((uint16_t)0x0080)              /*!< Listen enable */
3598 /* EUSCI_A_STATW[SPI_BUSY] Bits */
3599 #define EUSCI_A_STATW_SPI_BUSY_OFS               ( 0)                            /*!< UCBUSY Bit Offset */
3600 #define EUSCI_A_STATW_SPI_BUSY                   ((uint16_t)0x0001)              /*!< eUSCI_A busy */
3601 /* EUSCI_A_RXBUF[RXBUF] Bits */
3602 #define EUSCI_A_RXBUF_RXBUF_OFS                  ( 0)                            /*!< UCRXBUF Bit Offset */
3603 #define EUSCI_A_RXBUF_RXBUF_MASK                 ((uint16_t)0x00FF)              /*!< UCRXBUF Bit Mask */
3604 /* EUSCI_A_TXBUF[TXBUF] Bits */
3605 #define EUSCI_A_TXBUF_TXBUF_OFS                  ( 0)                            /*!< UCTXBUF Bit Offset */
3606 #define EUSCI_A_TXBUF_TXBUF_MASK                 ((uint16_t)0x00FF)              /*!< UCTXBUF Bit Mask */
3607 /* EUSCI_A_ABCTL[ABDEN] Bits */
3608 #define EUSCI_A_ABCTL_ABDEN_OFS                  ( 0)                            /*!< UCABDEN Bit Offset */
3609 #define EUSCI_A_ABCTL_ABDEN                      ((uint16_t)0x0001)              /*!< Automatic baud-rate detect enable */
3610 /* EUSCI_A_ABCTL[BTOE] Bits */
3611 #define EUSCI_A_ABCTL_BTOE_OFS                   ( 2)                            /*!< UCBTOE Bit Offset */
3612 #define EUSCI_A_ABCTL_BTOE                       ((uint16_t)0x0004)              /*!< Break time out error */
3613 /* EUSCI_A_ABCTL[STOE] Bits */
3614 #define EUSCI_A_ABCTL_STOE_OFS                   ( 3)                            /*!< UCSTOE Bit Offset */
3615 #define EUSCI_A_ABCTL_STOE                       ((uint16_t)0x0008)              /*!< Synch field time out error */
3616 /* EUSCI_A_ABCTL[DELIM] Bits */
3617 #define EUSCI_A_ABCTL_DELIM_OFS                  ( 4)                            /*!< UCDELIM Bit Offset */
3618 #define EUSCI_A_ABCTL_DELIM_MASK                 ((uint16_t)0x0030)              /*!< UCDELIM Bit Mask */
3619 #define EUSCI_A_ABCTL_DELIM0                     ((uint16_t)0x0010)              /*!< DELIM Bit 0 */
3620 #define EUSCI_A_ABCTL_DELIM1                     ((uint16_t)0x0020)              /*!< DELIM Bit 1 */
3621 #define EUSCI_A_ABCTL_DELIM_0                    ((uint16_t)0x0000)              /*!< 1 bit time */
3622 #define EUSCI_A_ABCTL_DELIM_1                    ((uint16_t)0x0010)              /*!< 2 bit times */
3623 #define EUSCI_A_ABCTL_DELIM_2                    ((uint16_t)0x0020)              /*!< 3 bit times */
3624 #define EUSCI_A_ABCTL_DELIM_3                    ((uint16_t)0x0030)              /*!< 4 bit times */
3625 /* EUSCI_A_IRCTL[IREN] Bits */
3626 #define EUSCI_A_IRCTL_IREN_OFS                   ( 0)                            /*!< UCIREN Bit Offset */
3627 #define EUSCI_A_IRCTL_IREN                       ((uint16_t)0x0001)              /*!< IrDA encoder/decoder enable */
3628 /* EUSCI_A_IRCTL[IRTXCLK] Bits */
3629 #define EUSCI_A_IRCTL_IRTXCLK_OFS                ( 1)                            /*!< UCIRTXCLK Bit Offset */
3630 #define EUSCI_A_IRCTL_IRTXCLK                    ((uint16_t)0x0002)              /*!< IrDA transmit pulse clock select */
3631 /* EUSCI_A_IRCTL[IRTXPL] Bits */
3632 #define EUSCI_A_IRCTL_IRTXPL_OFS                 ( 2)                            /*!< UCIRTXPL Bit Offset */
3633 #define EUSCI_A_IRCTL_IRTXPL_MASK                ((uint16_t)0x00FC)              /*!< UCIRTXPL Bit Mask */
3634 /* EUSCI_A_IRCTL[IRRXFE] Bits */
3635 #define EUSCI_A_IRCTL_IRRXFE_OFS                 ( 8)                            /*!< UCIRRXFE Bit Offset */
3636 #define EUSCI_A_IRCTL_IRRXFE                     ((uint16_t)0x0100)              /*!< IrDA receive filter enabled */
3637 /* EUSCI_A_IRCTL[IRRXPL] Bits */
3638 #define EUSCI_A_IRCTL_IRRXPL_OFS                 ( 9)                            /*!< UCIRRXPL Bit Offset */
3639 #define EUSCI_A_IRCTL_IRRXPL                     ((uint16_t)0x0200)              /*!< IrDA receive input UCAxRXD polarity */
3640 /* EUSCI_A_IRCTL[IRRXFL] Bits */
3641 #define EUSCI_A_IRCTL_IRRXFL_OFS                 (10)                            /*!< UCIRRXFL Bit Offset */
3642 #define EUSCI_A_IRCTL_IRRXFL_MASK                ((uint16_t)0x3C00)              /*!< UCIRRXFL Bit Mask */
3643 /* EUSCI_A_IE[RXIE] Bits */
3644 #define EUSCI_A_IE_RXIE_OFS                      ( 0)                            /*!< UCRXIE Bit Offset */
3645 #define EUSCI_A_IE_RXIE                          ((uint16_t)0x0001)              /*!< Receive interrupt enable */
3646 /* EUSCI_A_IE[TXIE] Bits */
3647 #define EUSCI_A_IE_TXIE_OFS                      ( 1)                            /*!< UCTXIE Bit Offset */
3648 #define EUSCI_A_IE_TXIE                          ((uint16_t)0x0002)              /*!< Transmit interrupt enable */
3649 /* EUSCI_A_IE[STTIE] Bits */
3650 #define EUSCI_A_IE_STTIE_OFS                     ( 2)                            /*!< UCSTTIE Bit Offset */
3651 #define EUSCI_A_IE_STTIE                         ((uint16_t)0x0004)              /*!< Start bit interrupt enable */
3652 /* EUSCI_A_IE[TXCPTIE] Bits */
3653 #define EUSCI_A_IE_TXCPTIE_OFS                   ( 3)                            /*!< UCTXCPTIE Bit Offset */
3654 #define EUSCI_A_IE_TXCPTIE                       ((uint16_t)0x0008)              /*!< Transmit complete interrupt enable */
3655 /* EUSCI_A_IFG[RXIFG] Bits */
3656 #define EUSCI_A_IFG_RXIFG_OFS                    ( 0)                            /*!< UCRXIFG Bit Offset */
3657 #define EUSCI_A_IFG_RXIFG                        ((uint16_t)0x0001)              /*!< Receive interrupt flag */
3658 /* EUSCI_A_IFG[TXIFG] Bits */
3659 #define EUSCI_A_IFG_TXIFG_OFS                    ( 1)                            /*!< UCTXIFG Bit Offset */
3660 #define EUSCI_A_IFG_TXIFG                        ((uint16_t)0x0002)              /*!< Transmit interrupt flag */
3661 /* EUSCI_A_IFG[STTIFG] Bits */
3662 #define EUSCI_A_IFG_STTIFG_OFS                   ( 2)                            /*!< UCSTTIFG Bit Offset */
3663 #define EUSCI_A_IFG_STTIFG                       ((uint16_t)0x0004)              /*!< Start bit interrupt flag */
3664 /* EUSCI_A_IFG[TXCPTIFG] Bits */
3665 #define EUSCI_A_IFG_TXCPTIFG_OFS                 ( 3)                            /*!< UCTXCPTIFG Bit Offset */
3666 #define EUSCI_A_IFG_TXCPTIFG                     ((uint16_t)0x0008)              /*!< Transmit ready interrupt enable */
3667 /* legacy definitions for backward compatibility to version 2100 */
3668 #define EUSCI_A__RXIE_OFS                        EUSCI_A_IE_RXIE_OFS             /*!< UCRXIE Bit Offset */
3669 #define EUSCI_A__RXIE                            EUSCI_A_IE_RXIE                 /*!< Receive interrupt enable */
3670 #define EUSCI_A__TXIE_OFS                        EUSCI_A_IE_TXIE_OFS             /*!< UCTXIE Bit Offset */
3671 #define EUSCI_A__TXIE                            EUSCI_A_IE_TXIE                 /*!< Transmit interrupt enable */
3672 
3673 
3674 /******************************************************************************
3675 * EUSCI_B Bits
3676 ******************************************************************************/
3677 /* EUSCI_B_CTLW0[SWRST] Bits */
3678 #define EUSCI_B_CTLW0_SWRST_OFS                  ( 0)                            /*!< UCSWRST Bit Offset */
3679 #define EUSCI_B_CTLW0_SWRST                      ((uint16_t)0x0001)              /*!< Software reset enable */
3680 /* EUSCI_B_CTLW0[TXSTT] Bits */
3681 #define EUSCI_B_CTLW0_TXSTT_OFS                  ( 1)                            /*!< UCTXSTT Bit Offset */
3682 #define EUSCI_B_CTLW0_TXSTT                      ((uint16_t)0x0002)              /*!< Transmit START condition in master mode */
3683 /* EUSCI_B_CTLW0[TXSTP] Bits */
3684 #define EUSCI_B_CTLW0_TXSTP_OFS                  ( 2)                            /*!< UCTXSTP Bit Offset */
3685 #define EUSCI_B_CTLW0_TXSTP                      ((uint16_t)0x0004)              /*!< Transmit STOP condition in master mode */
3686 /* EUSCI_B_CTLW0[TXNACK] Bits */
3687 #define EUSCI_B_CTLW0_TXNACK_OFS                 ( 3)                            /*!< UCTXNACK Bit Offset */
3688 #define EUSCI_B_CTLW0_TXNACK                     ((uint16_t)0x0008)              /*!< Transmit a NACK */
3689 /* EUSCI_B_CTLW0[TR] Bits */
3690 #define EUSCI_B_CTLW0_TR_OFS                     ( 4)                            /*!< UCTR Bit Offset */
3691 #define EUSCI_B_CTLW0_TR                         ((uint16_t)0x0010)              /*!< Transmitter/receiver */
3692 /* EUSCI_B_CTLW0[TXACK] Bits */
3693 #define EUSCI_B_CTLW0_TXACK_OFS                  ( 5)                            /*!< UCTXACK Bit Offset */
3694 #define EUSCI_B_CTLW0_TXACK                      ((uint16_t)0x0020)              /*!< Transmit ACK condition in slave mode */
3695 /* EUSCI_B_CTLW0[SSEL] Bits */
3696 #define EUSCI_B_CTLW0_SSEL_OFS                   ( 6)                            /*!< UCSSEL Bit Offset */
3697 #define EUSCI_B_CTLW0_SSEL_MASK                  ((uint16_t)0x00C0)              /*!< UCSSEL Bit Mask */
3698 #define EUSCI_B_CTLW0_SSEL0                      ((uint16_t)0x0040)              /*!< SSEL Bit 0 */
3699 #define EUSCI_B_CTLW0_SSEL1                      ((uint16_t)0x0080)              /*!< SSEL Bit 1 */
3700 #define EUSCI_B_CTLW0_UCSSEL_0                   ((uint16_t)0x0000)              /*!< UCLKI */
3701 #define EUSCI_B_CTLW0_UCSSEL_1                   ((uint16_t)0x0040)              /*!< ACLK */
3702 #define EUSCI_B_CTLW0_UCSSEL_2                   ((uint16_t)0x0080)              /*!< SMCLK */
3703 #define EUSCI_B_CTLW0_UCSSEL_3                   ((uint16_t)0x00C0)              /*!< SMCLK */
3704 #define EUSCI_B_CTLW0_SSEL__UCLKI                ((uint16_t)0x0000)              /*!< UCLKI */
3705 #define EUSCI_B_CTLW0_SSEL__ACLK                 ((uint16_t)0x0040)              /*!< ACLK */
3706 #define EUSCI_B_CTLW0_SSEL__SMCLK                ((uint16_t)0x0080)              /*!< SMCLK */
3707 /* EUSCI_B_CTLW0[SYNC] Bits */
3708 #define EUSCI_B_CTLW0_SYNC_OFS                   ( 8)                            /*!< UCSYNC Bit Offset */
3709 #define EUSCI_B_CTLW0_SYNC                       ((uint16_t)0x0100)              /*!< Synchronous mode enable */
3710 /* EUSCI_B_CTLW0[MODE] Bits */
3711 #define EUSCI_B_CTLW0_MODE_OFS                   ( 9)                            /*!< UCMODE Bit Offset */
3712 #define EUSCI_B_CTLW0_MODE_MASK                  ((uint16_t)0x0600)              /*!< UCMODE Bit Mask */
3713 #define EUSCI_B_CTLW0_MODE0                      ((uint16_t)0x0200)              /*!< MODE Bit 0 */
3714 #define EUSCI_B_CTLW0_MODE1                      ((uint16_t)0x0400)              /*!< MODE Bit 1 */
3715 #define EUSCI_B_CTLW0_MODE_0                     ((uint16_t)0x0000)              /*!< 3-pin SPI */
3716 #define EUSCI_B_CTLW0_MODE_1                     ((uint16_t)0x0200)              /*!< 4-pin SPI (master or slave enabled if STE = 1) */
3717 #define EUSCI_B_CTLW0_MODE_2                     ((uint16_t)0x0400)              /*!< 4-pin SPI (master or slave enabled if STE = 0) */
3718 #define EUSCI_B_CTLW0_MODE_3                     ((uint16_t)0x0600)              /*!< I2C mode */
3719 /* EUSCI_B_CTLW0[MST] Bits */
3720 #define EUSCI_B_CTLW0_MST_OFS                    (11)                            /*!< UCMST Bit Offset */
3721 #define EUSCI_B_CTLW0_MST                        ((uint16_t)0x0800)              /*!< Master mode select */
3722 /* EUSCI_B_CTLW0[MM] Bits */
3723 #define EUSCI_B_CTLW0_MM_OFS                     (13)                            /*!< UCMM Bit Offset */
3724 #define EUSCI_B_CTLW0_MM                         ((uint16_t)0x2000)              /*!< Multi-master environment select */
3725 /* EUSCI_B_CTLW0[SLA10] Bits */
3726 #define EUSCI_B_CTLW0_SLA10_OFS                  (14)                            /*!< UCSLA10 Bit Offset */
3727 #define EUSCI_B_CTLW0_SLA10                      ((uint16_t)0x4000)              /*!< Slave addressing mode select */
3728 /* EUSCI_B_CTLW0[A10] Bits */
3729 #define EUSCI_B_CTLW0_A10_OFS                    (15)                            /*!< UCA10 Bit Offset */
3730 #define EUSCI_B_CTLW0_A10                        ((uint16_t)0x8000)              /*!< Own addressing mode select */
3731 /* EUSCI_B_CTLW0[STEM] Bits */
3732 #define EUSCI_B_CTLW0_STEM_OFS                   ( 1)                            /*!< UCSTEM Bit Offset */
3733 #define EUSCI_B_CTLW0_STEM                       ((uint16_t)0x0002)              /*!< STE mode select in master mode. */
3734 /* EUSCI_B_CTLW0[SEVENBIT] Bits */
3735 #define EUSCI_B_CTLW0_SEVENBIT_OFS               (12)                            /*!< UC7BIT Bit Offset */
3736 #define EUSCI_B_CTLW0_SEVENBIT                   ((uint16_t)0x1000)              /*!< Character length */
3737 /* EUSCI_B_CTLW0[MSB] Bits */
3738 #define EUSCI_B_CTLW0_MSB_OFS                    (13)                            /*!< UCMSB Bit Offset */
3739 #define EUSCI_B_CTLW0_MSB                        ((uint16_t)0x2000)              /*!< MSB first select */
3740 /* EUSCI_B_CTLW0[CKPL] Bits */
3741 #define EUSCI_B_CTLW0_CKPL_OFS                   (14)                            /*!< UCCKPL Bit Offset */
3742 #define EUSCI_B_CTLW0_CKPL                       ((uint16_t)0x4000)              /*!< Clock polarity select */
3743 /* EUSCI_B_CTLW0[CKPH] Bits */
3744 #define EUSCI_B_CTLW0_CKPH_OFS                   (15)                            /*!< UCCKPH Bit Offset */
3745 #define EUSCI_B_CTLW0_CKPH                       ((uint16_t)0x8000)              /*!< Clock phase select */
3746 /* EUSCI_B_CTLW1[GLIT] Bits */
3747 #define EUSCI_B_CTLW1_GLIT_OFS                   ( 0)                            /*!< UCGLIT Bit Offset */
3748 #define EUSCI_B_CTLW1_GLIT_MASK                  ((uint16_t)0x0003)              /*!< UCGLIT Bit Mask */
3749 #define EUSCI_B_CTLW1_GLIT0                      ((uint16_t)0x0001)              /*!< GLIT Bit 0 */
3750 #define EUSCI_B_CTLW1_GLIT1                      ((uint16_t)0x0002)              /*!< GLIT Bit 1 */
3751 #define EUSCI_B_CTLW1_GLIT_0                     ((uint16_t)0x0000)              /*!< 50 ns */
3752 #define EUSCI_B_CTLW1_GLIT_1                     ((uint16_t)0x0001)              /*!< 25 ns */
3753 #define EUSCI_B_CTLW1_GLIT_2                     ((uint16_t)0x0002)              /*!< 12.5 ns */
3754 #define EUSCI_B_CTLW1_GLIT_3                     ((uint16_t)0x0003)              /*!< 6.25 ns */
3755 /* EUSCI_B_CTLW1[ASTP] Bits */
3756 #define EUSCI_B_CTLW1_ASTP_OFS                   ( 2)                            /*!< UCASTP Bit Offset */
3757 #define EUSCI_B_CTLW1_ASTP_MASK                  ((uint16_t)0x000C)              /*!< UCASTP Bit Mask */
3758 #define EUSCI_B_CTLW1_ASTP0                      ((uint16_t)0x0004)              /*!< ASTP Bit 0 */
3759 #define EUSCI_B_CTLW1_ASTP1                      ((uint16_t)0x0008)              /*!< ASTP Bit 1 */
3760 #define EUSCI_B_CTLW1_ASTP_0                     ((uint16_t)0x0000)              /*!< No automatic STOP generation. The STOP condition is generated after the user  */
3761                                                                                  /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */
3762 #define EUSCI_B_CTLW1_ASTP_1                     ((uint16_t)0x0004)              /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in  */
3763                                                                                  /* UCBxTBCNT */
3764 #define EUSCI_B_CTLW1_ASTP_2                     ((uint16_t)0x0008)              /*!< A STOP condition is generated automatically after the byte counter value  */
3765                                                                                  /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */
3766                                                                                  /* threshold */
3767 /* EUSCI_B_CTLW1[SWACK] Bits */
3768 #define EUSCI_B_CTLW1_SWACK_OFS                  ( 4)                            /*!< UCSWACK Bit Offset */
3769 #define EUSCI_B_CTLW1_SWACK                      ((uint16_t)0x0010)              /*!< SW or HW ACK control */
3770 /* EUSCI_B_CTLW1[STPNACK] Bits */
3771 #define EUSCI_B_CTLW1_STPNACK_OFS                ( 5)                            /*!< UCSTPNACK Bit Offset */
3772 #define EUSCI_B_CTLW1_STPNACK                    ((uint16_t)0x0020)              /*!< ACK all master bytes */
3773 /* EUSCI_B_CTLW1[CLTO] Bits */
3774 #define EUSCI_B_CTLW1_CLTO_OFS                   ( 6)                            /*!< UCCLTO Bit Offset */
3775 #define EUSCI_B_CTLW1_CLTO_MASK                  ((uint16_t)0x00C0)              /*!< UCCLTO Bit Mask */
3776 #define EUSCI_B_CTLW1_CLTO0                      ((uint16_t)0x0040)              /*!< CLTO Bit 0 */
3777 #define EUSCI_B_CTLW1_CLTO1                      ((uint16_t)0x0080)              /*!< CLTO Bit 1 */
3778 #define EUSCI_B_CTLW1_CLTO_0                     ((uint16_t)0x0000)              /*!< Disable clock low timeout counter */
3779 #define EUSCI_B_CTLW1_CLTO_1                     ((uint16_t)0x0040)              /*!< 135 000 SYSCLK cycles (approximately 28 ms) */
3780 #define EUSCI_B_CTLW1_CLTO_2                     ((uint16_t)0x0080)              /*!< 150 000 SYSCLK cycles (approximately 31 ms) */
3781 #define EUSCI_B_CTLW1_CLTO_3                     ((uint16_t)0x00C0)              /*!< 165 000 SYSCLK cycles (approximately 34 ms) */
3782 /* EUSCI_B_CTLW1[ETXINT] Bits */
3783 #define EUSCI_B_CTLW1_ETXINT_OFS                 ( 8)                            /*!< UCETXINT Bit Offset */
3784 #define EUSCI_B_CTLW1_ETXINT                     ((uint16_t)0x0100)              /*!< Early UCTXIFG0 */
3785 /* EUSCI_B_STATW[BBUSY] Bits */
3786 #define EUSCI_B_STATW_BBUSY_OFS                  ( 4)                            /*!< UCBBUSY Bit Offset */
3787 #define EUSCI_B_STATW_BBUSY                      ((uint16_t)0x0010)              /*!< Bus busy */
3788 /* EUSCI_B_STATW[GC] Bits */
3789 #define EUSCI_B_STATW_GC_OFS                     ( 5)                            /*!< UCGC Bit Offset */
3790 #define EUSCI_B_STATW_GC                         ((uint16_t)0x0020)              /*!< General call address received */
3791 /* EUSCI_B_STATW[SCLLOW] Bits */
3792 #define EUSCI_B_STATW_SCLLOW_OFS                 ( 6)                            /*!< UCSCLLOW Bit Offset */
3793 #define EUSCI_B_STATW_SCLLOW                     ((uint16_t)0x0040)              /*!< SCL low */
3794 /* EUSCI_B_STATW[BCNT] Bits */
3795 #define EUSCI_B_STATW_BCNT_OFS                   ( 8)                            /*!< UCBCNT Bit Offset */
3796 #define EUSCI_B_STATW_BCNT_MASK                  ((uint16_t)0xFF00)              /*!< UCBCNT Bit Mask */
3797 /* EUSCI_B_STATW[SPI_BUSY] Bits */
3798 #define EUSCI_B_STATW_SPI_BUSY_OFS               ( 0)                            /*!< UCBUSY Bit Offset */
3799 #define EUSCI_B_STATW_SPI_BUSY                   ((uint16_t)0x0001)              /*!< eUSCI_B busy */
3800 /* EUSCI_B_STATW[OE] Bits */
3801 #define EUSCI_B_STATW_OE_OFS                     ( 5)                            /*!< UCOE Bit Offset */
3802 #define EUSCI_B_STATW_OE                         ((uint16_t)0x0020)              /*!< Overrun error flag */
3803 /* EUSCI_B_STATW[FE] Bits */
3804 #define EUSCI_B_STATW_FE_OFS                     ( 6)                            /*!< UCFE Bit Offset */
3805 #define EUSCI_B_STATW_FE                         ((uint16_t)0x0040)              /*!< Framing error flag */
3806 /* EUSCI_B_STATW[LISTEN] Bits */
3807 #define EUSCI_B_STATW_LISTEN_OFS                 ( 7)                            /*!< UCLISTEN Bit Offset */
3808 #define EUSCI_B_STATW_LISTEN                     ((uint16_t)0x0080)              /*!< Listen enable */
3809 /* EUSCI_B_TBCNT[TBCNT] Bits */
3810 #define EUSCI_B_TBCNT_TBCNT_OFS                  ( 0)                            /*!< UCTBCNT Bit Offset */
3811 #define EUSCI_B_TBCNT_TBCNT_MASK                 ((uint16_t)0x00FF)              /*!< UCTBCNT Bit Mask */
3812 /* EUSCI_B_RXBUF[RXBUF] Bits */
3813 #define EUSCI_B_RXBUF_RXBUF_OFS                  ( 0)                            /*!< UCRXBUF Bit Offset */
3814 #define EUSCI_B_RXBUF_RXBUF_MASK                 ((uint16_t)0x00FF)              /*!< UCRXBUF Bit Mask */
3815 /* EUSCI_B_TXBUF[TXBUF] Bits */
3816 #define EUSCI_B_TXBUF_TXBUF_OFS                  ( 0)                            /*!< UCTXBUF Bit Offset */
3817 #define EUSCI_B_TXBUF_TXBUF_MASK                 ((uint16_t)0x00FF)              /*!< UCTXBUF Bit Mask */
3818 /* EUSCI_B_I2COA0[I2COA0] Bits */
3819 #define EUSCI_B_I2COA0_I2COA0_OFS                ( 0)                            /*!< I2COA0 Bit Offset */
3820 #define EUSCI_B_I2COA0_I2COA0_MASK               ((uint16_t)0x03FF)              /*!< I2COA0 Bit Mask */
3821 /* EUSCI_B_I2COA0[OAEN] Bits */
3822 #define EUSCI_B_I2COA0_OAEN_OFS                  (10)                            /*!< UCOAEN Bit Offset */
3823 #define EUSCI_B_I2COA0_OAEN                      ((uint16_t)0x0400)              /*!< Own Address enable register */
3824 /* EUSCI_B_I2COA0[GCEN] Bits */
3825 #define EUSCI_B_I2COA0_GCEN_OFS                  (15)                            /*!< UCGCEN Bit Offset */
3826 #define EUSCI_B_I2COA0_GCEN                      ((uint16_t)0x8000)              /*!< General call response enable */
3827 /* EUSCI_B_I2COA1[I2COA1] Bits */
3828 #define EUSCI_B_I2COA1_I2COA1_OFS                ( 0)                            /*!< I2COA1 Bit Offset */
3829 #define EUSCI_B_I2COA1_I2COA1_MASK               ((uint16_t)0x03FF)              /*!< I2COA1 Bit Mask */
3830 /* EUSCI_B_I2COA1[OAEN] Bits */
3831 #define EUSCI_B_I2COA1_OAEN_OFS                  (10)                            /*!< UCOAEN Bit Offset */
3832 #define EUSCI_B_I2COA1_OAEN                      ((uint16_t)0x0400)              /*!< Own Address enable register */
3833 /* EUSCI_B_I2COA2[I2COA2] Bits */
3834 #define EUSCI_B_I2COA2_I2COA2_OFS                ( 0)                            /*!< I2COA2 Bit Offset */
3835 #define EUSCI_B_I2COA2_I2COA2_MASK               ((uint16_t)0x03FF)              /*!< I2COA2 Bit Mask */
3836 /* EUSCI_B_I2COA2[OAEN] Bits */
3837 #define EUSCI_B_I2COA2_OAEN_OFS                  (10)                            /*!< UCOAEN Bit Offset */
3838 #define EUSCI_B_I2COA2_OAEN                      ((uint16_t)0x0400)              /*!< Own Address enable register */
3839 /* EUSCI_B_I2COA3[I2COA3] Bits */
3840 #define EUSCI_B_I2COA3_I2COA3_OFS                ( 0)                            /*!< I2COA3 Bit Offset */
3841 #define EUSCI_B_I2COA3_I2COA3_MASK               ((uint16_t)0x03FF)              /*!< I2COA3 Bit Mask */
3842 /* EUSCI_B_I2COA3[OAEN] Bits */
3843 #define EUSCI_B_I2COA3_OAEN_OFS                  (10)                            /*!< UCOAEN Bit Offset */
3844 #define EUSCI_B_I2COA3_OAEN                      ((uint16_t)0x0400)              /*!< Own Address enable register */
3845 /* EUSCI_B_ADDRX[ADDRX] Bits */
3846 #define EUSCI_B_ADDRX_ADDRX_OFS                  ( 0)                            /*!< ADDRX Bit Offset */
3847 #define EUSCI_B_ADDRX_ADDRX_MASK                 ((uint16_t)0x03FF)              /*!< ADDRX Bit Mask */
3848 #define EUSCI_B_ADDRX_ADDRX0                     ((uint16_t)0x0001)              /*!< ADDRX Bit 0 */
3849 #define EUSCI_B_ADDRX_ADDRX1                     ((uint16_t)0x0002)              /*!< ADDRX Bit 1 */
3850 #define EUSCI_B_ADDRX_ADDRX2                     ((uint16_t)0x0004)              /*!< ADDRX Bit 2 */
3851 #define EUSCI_B_ADDRX_ADDRX3                     ((uint16_t)0x0008)              /*!< ADDRX Bit 3 */
3852 #define EUSCI_B_ADDRX_ADDRX4                     ((uint16_t)0x0010)              /*!< ADDRX Bit 4 */
3853 #define EUSCI_B_ADDRX_ADDRX5                     ((uint16_t)0x0020)              /*!< ADDRX Bit 5 */
3854 #define EUSCI_B_ADDRX_ADDRX6                     ((uint16_t)0x0040)              /*!< ADDRX Bit 6 */
3855 #define EUSCI_B_ADDRX_ADDRX7                     ((uint16_t)0x0080)              /*!< ADDRX Bit 7 */
3856 #define EUSCI_B_ADDRX_ADDRX8                     ((uint16_t)0x0100)              /*!< ADDRX Bit 8 */
3857 #define EUSCI_B_ADDRX_ADDRX9                     ((uint16_t)0x0200)              /*!< ADDRX Bit 9 */
3858 /* EUSCI_B_ADDMASK[ADDMASK] Bits */
3859 #define EUSCI_B_ADDMASK_ADDMASK_OFS              ( 0)                            /*!< ADDMASK Bit Offset */
3860 #define EUSCI_B_ADDMASK_ADDMASK_MASK             ((uint16_t)0x03FF)              /*!< ADDMASK Bit Mask */
3861 /* EUSCI_B_I2CSA[I2CSA] Bits */
3862 #define EUSCI_B_I2CSA_I2CSA_OFS                  ( 0)                            /*!< I2CSA Bit Offset */
3863 #define EUSCI_B_I2CSA_I2CSA_MASK                 ((uint16_t)0x03FF)              /*!< I2CSA Bit Mask */
3864 /* EUSCI_B_IE[RXIE0] Bits */
3865 #define EUSCI_B_IE_RXIE0_OFS                     ( 0)                            /*!< UCRXIE0 Bit Offset */
3866 #define EUSCI_B_IE_RXIE0                         ((uint16_t)0x0001)              /*!< Receive interrupt enable 0 */
3867 /* EUSCI_B_IE[TXIE0] Bits */
3868 #define EUSCI_B_IE_TXIE0_OFS                     ( 1)                            /*!< UCTXIE0 Bit Offset */
3869 #define EUSCI_B_IE_TXIE0                         ((uint16_t)0x0002)              /*!< Transmit interrupt enable 0 */
3870 /* EUSCI_B_IE[STTIE] Bits */
3871 #define EUSCI_B_IE_STTIE_OFS                     ( 2)                            /*!< UCSTTIE Bit Offset */
3872 #define EUSCI_B_IE_STTIE                         ((uint16_t)0x0004)              /*!< START condition interrupt enable */
3873 /* EUSCI_B_IE[STPIE] Bits */
3874 #define EUSCI_B_IE_STPIE_OFS                     ( 3)                            /*!< UCSTPIE Bit Offset */
3875 #define EUSCI_B_IE_STPIE                         ((uint16_t)0x0008)              /*!< STOP condition interrupt enable */
3876 /* EUSCI_B_IE[ALIE] Bits */
3877 #define EUSCI_B_IE_ALIE_OFS                      ( 4)                            /*!< UCALIE Bit Offset */
3878 #define EUSCI_B_IE_ALIE                          ((uint16_t)0x0010)              /*!< Arbitration lost interrupt enable */
3879 /* EUSCI_B_IE[NACKIE] Bits */
3880 #define EUSCI_B_IE_NACKIE_OFS                    ( 5)                            /*!< UCNACKIE Bit Offset */
3881 #define EUSCI_B_IE_NACKIE                        ((uint16_t)0x0020)              /*!< Not-acknowledge interrupt enable */
3882 /* EUSCI_B_IE[BCNTIE] Bits */
3883 #define EUSCI_B_IE_BCNTIE_OFS                    ( 6)                            /*!< UCBCNTIE Bit Offset */
3884 #define EUSCI_B_IE_BCNTIE                        ((uint16_t)0x0040)              /*!< Byte counter interrupt enable */
3885 /* EUSCI_B_IE[CLTOIE] Bits */
3886 #define EUSCI_B_IE_CLTOIE_OFS                    ( 7)                            /*!< UCCLTOIE Bit Offset */
3887 #define EUSCI_B_IE_CLTOIE                        ((uint16_t)0x0080)              /*!< Clock low timeout interrupt enable */
3888 /* EUSCI_B_IE[RXIE1] Bits */
3889 #define EUSCI_B_IE_RXIE1_OFS                     ( 8)                            /*!< UCRXIE1 Bit Offset */
3890 #define EUSCI_B_IE_RXIE1                         ((uint16_t)0x0100)              /*!< Receive interrupt enable 1 */
3891 /* EUSCI_B_IE[TXIE1] Bits */
3892 #define EUSCI_B_IE_TXIE1_OFS                     ( 9)                            /*!< UCTXIE1 Bit Offset */
3893 #define EUSCI_B_IE_TXIE1                         ((uint16_t)0x0200)              /*!< Transmit interrupt enable 1 */
3894 /* EUSCI_B_IE[RXIE2] Bits */
3895 #define EUSCI_B_IE_RXIE2_OFS                     (10)                            /*!< UCRXIE2 Bit Offset */
3896 #define EUSCI_B_IE_RXIE2                         ((uint16_t)0x0400)              /*!< Receive interrupt enable 2 */
3897 /* EUSCI_B_IE[TXIE2] Bits */
3898 #define EUSCI_B_IE_TXIE2_OFS                     (11)                            /*!< UCTXIE2 Bit Offset */
3899 #define EUSCI_B_IE_TXIE2                         ((uint16_t)0x0800)              /*!< Transmit interrupt enable 2 */
3900 /* EUSCI_B_IE[RXIE3] Bits */
3901 #define EUSCI_B_IE_RXIE3_OFS                     (12)                            /*!< UCRXIE3 Bit Offset */
3902 #define EUSCI_B_IE_RXIE3                         ((uint16_t)0x1000)              /*!< Receive interrupt enable 3 */
3903 /* EUSCI_B_IE[TXIE3] Bits */
3904 #define EUSCI_B_IE_TXIE3_OFS                     (13)                            /*!< UCTXIE3 Bit Offset */
3905 #define EUSCI_B_IE_TXIE3                         ((uint16_t)0x2000)              /*!< Transmit interrupt enable 3 */
3906 /* EUSCI_B_IE[BIT9IE] Bits */
3907 #define EUSCI_B_IE_BIT9IE_OFS                    (14)                            /*!< UCBIT9IE Bit Offset */
3908 #define EUSCI_B_IE_BIT9IE                        ((uint16_t)0x4000)              /*!< Bit position 9 interrupt enable */
3909 /* EUSCI_B_IE[RXIE] Bits */
3910 #define EUSCI_B_IE_RXIE_OFS                      ( 0)                            /*!< UCRXIE Bit Offset */
3911 #define EUSCI_B_IE_RXIE                          ((uint16_t)0x0001)              /*!< Receive interrupt enable */
3912 /* EUSCI_B_IE[TXIE] Bits */
3913 #define EUSCI_B_IE_TXIE_OFS                      ( 1)                            /*!< UCTXIE Bit Offset */
3914 #define EUSCI_B_IE_TXIE                          ((uint16_t)0x0002)              /*!< Transmit interrupt enable */
3915 /* EUSCI_B_IFG[RXIFG0] Bits */
3916 #define EUSCI_B_IFG_RXIFG0_OFS                   ( 0)                            /*!< UCRXIFG0 Bit Offset */
3917 #define EUSCI_B_IFG_RXIFG0                       ((uint16_t)0x0001)              /*!< eUSCI_B receive interrupt flag 0 */
3918 /* EUSCI_B_IFG[TXIFG0] Bits */
3919 #define EUSCI_B_IFG_TXIFG0_OFS                   ( 1)                            /*!< UCTXIFG0 Bit Offset */
3920 #define EUSCI_B_IFG_TXIFG0                       ((uint16_t)0x0002)              /*!< eUSCI_B transmit interrupt flag 0 */
3921 /* EUSCI_B_IFG[STTIFG] Bits */
3922 #define EUSCI_B_IFG_STTIFG_OFS                   ( 2)                            /*!< UCSTTIFG Bit Offset */
3923 #define EUSCI_B_IFG_STTIFG                       ((uint16_t)0x0004)              /*!< START condition interrupt flag */
3924 /* EUSCI_B_IFG[STPIFG] Bits */
3925 #define EUSCI_B_IFG_STPIFG_OFS                   ( 3)                            /*!< UCSTPIFG Bit Offset */
3926 #define EUSCI_B_IFG_STPIFG                       ((uint16_t)0x0008)              /*!< STOP condition interrupt flag */
3927 /* EUSCI_B_IFG[ALIFG] Bits */
3928 #define EUSCI_B_IFG_ALIFG_OFS                    ( 4)                            /*!< UCALIFG Bit Offset */
3929 #define EUSCI_B_IFG_ALIFG                        ((uint16_t)0x0010)              /*!< Arbitration lost interrupt flag */
3930 /* EUSCI_B_IFG[NACKIFG] Bits */
3931 #define EUSCI_B_IFG_NACKIFG_OFS                  ( 5)                            /*!< UCNACKIFG Bit Offset */
3932 #define EUSCI_B_IFG_NACKIFG                      ((uint16_t)0x0020)              /*!< Not-acknowledge received interrupt flag */
3933 /* EUSCI_B_IFG[BCNTIFG] Bits */
3934 #define EUSCI_B_IFG_BCNTIFG_OFS                  ( 6)                            /*!< UCBCNTIFG Bit Offset */
3935 #define EUSCI_B_IFG_BCNTIFG                      ((uint16_t)0x0040)              /*!< Byte counter interrupt flag */
3936 /* EUSCI_B_IFG[CLTOIFG] Bits */
3937 #define EUSCI_B_IFG_CLTOIFG_OFS                  ( 7)                            /*!< UCCLTOIFG Bit Offset */
3938 #define EUSCI_B_IFG_CLTOIFG                      ((uint16_t)0x0080)              /*!< Clock low timeout interrupt flag */
3939 /* EUSCI_B_IFG[RXIFG1] Bits */
3940 #define EUSCI_B_IFG_RXIFG1_OFS                   ( 8)                            /*!< UCRXIFG1 Bit Offset */
3941 #define EUSCI_B_IFG_RXIFG1                       ((uint16_t)0x0100)              /*!< eUSCI_B receive interrupt flag 1 */
3942 /* EUSCI_B_IFG[TXIFG1] Bits */
3943 #define EUSCI_B_IFG_TXIFG1_OFS                   ( 9)                            /*!< UCTXIFG1 Bit Offset */
3944 #define EUSCI_B_IFG_TXIFG1                       ((uint16_t)0x0200)              /*!< eUSCI_B transmit interrupt flag 1 */
3945 /* EUSCI_B_IFG[RXIFG2] Bits */
3946 #define EUSCI_B_IFG_RXIFG2_OFS                   (10)                            /*!< UCRXIFG2 Bit Offset */
3947 #define EUSCI_B_IFG_RXIFG2                       ((uint16_t)0x0400)              /*!< eUSCI_B receive interrupt flag 2 */
3948 /* EUSCI_B_IFG[TXIFG2] Bits */
3949 #define EUSCI_B_IFG_TXIFG2_OFS                   (11)                            /*!< UCTXIFG2 Bit Offset */
3950 #define EUSCI_B_IFG_TXIFG2                       ((uint16_t)0x0800)              /*!< eUSCI_B transmit interrupt flag 2 */
3951 /* EUSCI_B_IFG[RXIFG3] Bits */
3952 #define EUSCI_B_IFG_RXIFG3_OFS                   (12)                            /*!< UCRXIFG3 Bit Offset */
3953 #define EUSCI_B_IFG_RXIFG3                       ((uint16_t)0x1000)              /*!< eUSCI_B receive interrupt flag 3 */
3954 /* EUSCI_B_IFG[TXIFG3] Bits */
3955 #define EUSCI_B_IFG_TXIFG3_OFS                   (13)                            /*!< UCTXIFG3 Bit Offset */
3956 #define EUSCI_B_IFG_TXIFG3                       ((uint16_t)0x2000)              /*!< eUSCI_B transmit interrupt flag 3 */
3957 /* EUSCI_B_IFG[BIT9IFG] Bits */
3958 #define EUSCI_B_IFG_BIT9IFG_OFS                  (14)                            /*!< UCBIT9IFG Bit Offset */
3959 #define EUSCI_B_IFG_BIT9IFG                      ((uint16_t)0x4000)              /*!< Bit position 9 interrupt flag */
3960 /* EUSCI_B_IFG[RXIFG] Bits */
3961 #define EUSCI_B_IFG_RXIFG_OFS                    ( 0)                            /*!< UCRXIFG Bit Offset */
3962 #define EUSCI_B_IFG_RXIFG                        ((uint16_t)0x0001)              /*!< Receive interrupt flag */
3963 /* EUSCI_B_IFG[TXIFG] Bits */
3964 #define EUSCI_B_IFG_TXIFG_OFS                    ( 1)                            /*!< UCTXIFG Bit Offset */
3965 #define EUSCI_B_IFG_TXIFG                        ((uint16_t)0x0002)              /*!< Transmit interrupt flag */
3966 /* legacy definitions for backward compatibility to version 2100 */
3967 #define EUSCI_B__RXIE_OFS                        EUSCI_B_IE_RXIE_OFS             /*!< UCRXIE Bit Offset */
3968 #define EUSCI_B__RXIE                            EUSCI_B_IE_RXIE                 /*!< Receive interrupt enable */
3969 #define EUSCI_B__TXIE_OFS                        EUSCI_B_IE_TXIE_OFS             /*!< UCTXIE Bit Offset */
3970 #define EUSCI_B__TXIE                            EUSCI_B_IE_TXIE                 /*!< Transmit interrupt enable */
3971 
3972 
3973 /******************************************************************************
3974 * FLCTL_A Bits
3975 ******************************************************************************/
3976 /* FLCTL_A_POWER_STAT[PSTAT] Bits */
3977 #define FLCTL_A_POWER_STAT_PSTAT_OFS             ( 0)                            /*!< PSTAT Bit Offset */
3978 #define FLCTL_A_POWER_STAT_PSTAT_MASK            ((uint32_t)0x00000007)          /*!< PSTAT Bit Mask */
3979 #define FLCTL_A_POWER_STAT_PSTAT0                ((uint32_t)0x00000001)          /*!< PSTAT Bit 0 */
3980 #define FLCTL_A_POWER_STAT_PSTAT1                ((uint32_t)0x00000002)          /*!< PSTAT Bit 1 */
3981 #define FLCTL_A_POWER_STAT_PSTAT2                ((uint32_t)0x00000004)          /*!< PSTAT Bit 2 */
3982 #define FLCTL_A_POWER_STAT_PSTAT_0               ((uint32_t)0x00000000)          /*!< Flash IP in power-down mode */
3983 #define FLCTL_A_POWER_STAT_PSTAT_1               ((uint32_t)0x00000001)          /*!< Flash IP Vdd domain power-up in progress */
3984 #define FLCTL_A_POWER_STAT_PSTAT_2               ((uint32_t)0x00000002)          /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */
3985 #define FLCTL_A_POWER_STAT_PSTAT_3               ((uint32_t)0x00000003)          /*!< Flash IP SAFE_LV check in progress */
3986 #define FLCTL_A_POWER_STAT_PSTAT_4               ((uint32_t)0x00000004)          /*!< Flash IP Active */
3987 #define FLCTL_A_POWER_STAT_PSTAT_5               ((uint32_t)0x00000005)          /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */
3988 #define FLCTL_A_POWER_STAT_PSTAT_6               ((uint32_t)0x00000006)          /*!< Flash IP in Standby mode */
3989 #define FLCTL_A_POWER_STAT_PSTAT_7               ((uint32_t)0x00000007)          /*!< Flash IP in Current mirror boost state */
3990 /* FLCTL_A_POWER_STAT[LDOSTAT] Bits */
3991 #define FLCTL_A_POWER_STAT_LDOSTAT_OFS           ( 3)                            /*!< LDOSTAT Bit Offset */
3992 #define FLCTL_A_POWER_STAT_LDOSTAT               ((uint32_t)0x00000008)          /*!< PSS FLDO GOOD status */
3993 /* FLCTL_A_POWER_STAT[VREFSTAT] Bits */
3994 #define FLCTL_A_POWER_STAT_VREFSTAT_OFS          ( 4)                            /*!< VREFSTAT Bit Offset */
3995 #define FLCTL_A_POWER_STAT_VREFSTAT              ((uint32_t)0x00000010)          /*!< PSS VREF stable status */
3996 /* FLCTL_A_POWER_STAT[IREFSTAT] Bits */
3997 #define FLCTL_A_POWER_STAT_IREFSTAT_OFS          ( 5)                            /*!< IREFSTAT Bit Offset */
3998 #define FLCTL_A_POWER_STAT_IREFSTAT              ((uint32_t)0x00000020)          /*!< PSS IREF stable status */
3999 /* FLCTL_A_POWER_STAT[TRIMSTAT] Bits */
4000 #define FLCTL_A_POWER_STAT_TRIMSTAT_OFS          ( 6)                            /*!< TRIMSTAT Bit Offset */
4001 #define FLCTL_A_POWER_STAT_TRIMSTAT              ((uint32_t)0x00000040)          /*!< PSS trim done status */
4002 /* FLCTL_A_POWER_STAT[RD_2T] Bits */
4003 #define FLCTL_A_POWER_STAT_RD_2T_OFS             ( 7)                            /*!< RD_2T Bit Offset */
4004 #define FLCTL_A_POWER_STAT_RD_2T                 ((uint32_t)0x00000080)          /*!< Indicates if Flash is being accessed in 2T mode */
4005 /* FLCTL_A_BANK0_RDCTL[RD_MODE] Bits */
4006 #define FLCTL_A_BANK0_RDCTL_RD_MODE_OFS          ( 0)                            /*!< RD_MODE Bit Offset */
4007 #define FLCTL_A_BANK0_RDCTL_RD_MODE_MASK         ((uint32_t)0x0000000F)          /*!< RD_MODE Bit Mask */
4008 #define FLCTL_A_BANK0_RDCTL_RD_MODE0             ((uint32_t)0x00000001)          /*!< RD_MODE Bit 0 */
4009 #define FLCTL_A_BANK0_RDCTL_RD_MODE1             ((uint32_t)0x00000002)          /*!< RD_MODE Bit 1 */
4010 #define FLCTL_A_BANK0_RDCTL_RD_MODE2             ((uint32_t)0x00000004)          /*!< RD_MODE Bit 2 */
4011 #define FLCTL_A_BANK0_RDCTL_RD_MODE3             ((uint32_t)0x00000008)          /*!< RD_MODE Bit 3 */
4012 #define FLCTL_A_BANK0_RDCTL_RD_MODE_0            ((uint32_t)0x00000000)          /*!< Normal read mode */
4013 #define FLCTL_A_BANK0_RDCTL_RD_MODE_1            ((uint32_t)0x00000001)          /*!< Read Margin 0 */
4014 #define FLCTL_A_BANK0_RDCTL_RD_MODE_2            ((uint32_t)0x00000002)          /*!< Read Margin 1 */
4015 #define FLCTL_A_BANK0_RDCTL_RD_MODE_3            ((uint32_t)0x00000003)          /*!< Program Verify */
4016 #define FLCTL_A_BANK0_RDCTL_RD_MODE_4            ((uint32_t)0x00000004)          /*!< Erase Verify */
4017 #define FLCTL_A_BANK0_RDCTL_RD_MODE_5            ((uint32_t)0x00000005)          /*!< Leakage Verify */
4018 #define FLCTL_A_BANK0_RDCTL_RD_MODE_9            ((uint32_t)0x00000009)          /*!< Read Margin 0B */
4019 #define FLCTL_A_BANK0_RDCTL_RD_MODE_10           ((uint32_t)0x0000000A)          /*!< Read Margin 1B */
4020 /* FLCTL_A_BANK0_RDCTL[BUFI] Bits */
4021 #define FLCTL_A_BANK0_RDCTL_BUFI_OFS             ( 4)                            /*!< BUFI Bit Offset */
4022 #define FLCTL_A_BANK0_RDCTL_BUFI                 ((uint32_t)0x00000010)          /*!< Enables read buffering feature for instruction fetches to this Bank */
4023 /* FLCTL_A_BANK0_RDCTL[BUFD] Bits */
4024 #define FLCTL_A_BANK0_RDCTL_BUFD_OFS             ( 5)                            /*!< BUFD Bit Offset */
4025 #define FLCTL_A_BANK0_RDCTL_BUFD                 ((uint32_t)0x00000020)          /*!< Enables read buffering feature for data reads to this Bank */
4026 /* FLCTL_A_BANK0_RDCTL[WAIT] Bits */
4027 #define FLCTL_A_BANK0_RDCTL_WAIT_OFS             (12)                            /*!< WAIT Bit Offset */
4028 #define FLCTL_A_BANK0_RDCTL_WAIT_MASK            ((uint32_t)0x0000F000)          /*!< WAIT Bit Mask */
4029 #define FLCTL_A_BANK0_RDCTL_WAIT0                ((uint32_t)0x00001000)          /*!< WAIT Bit 0 */
4030 #define FLCTL_A_BANK0_RDCTL_WAIT1                ((uint32_t)0x00002000)          /*!< WAIT Bit 1 */
4031 #define FLCTL_A_BANK0_RDCTL_WAIT2                ((uint32_t)0x00004000)          /*!< WAIT Bit 2 */
4032 #define FLCTL_A_BANK0_RDCTL_WAIT3                ((uint32_t)0x00008000)          /*!< WAIT Bit 3 */
4033 #define FLCTL_A_BANK0_RDCTL_WAIT_0               ((uint32_t)0x00000000)          /*!< 0 wait states */
4034 #define FLCTL_A_BANK0_RDCTL_WAIT_1               ((uint32_t)0x00001000)          /*!< 1 wait states */
4035 #define FLCTL_A_BANK0_RDCTL_WAIT_2               ((uint32_t)0x00002000)          /*!< 2 wait states */
4036 #define FLCTL_A_BANK0_RDCTL_WAIT_3               ((uint32_t)0x00003000)          /*!< 3 wait states */
4037 #define FLCTL_A_BANK0_RDCTL_WAIT_4               ((uint32_t)0x00004000)          /*!< 4 wait states */
4038 #define FLCTL_A_BANK0_RDCTL_WAIT_5               ((uint32_t)0x00005000)          /*!< 5 wait states */
4039 #define FLCTL_A_BANK0_RDCTL_WAIT_6               ((uint32_t)0x00006000)          /*!< 6 wait states */
4040 #define FLCTL_A_BANK0_RDCTL_WAIT_7               ((uint32_t)0x00007000)          /*!< 7 wait states */
4041 #define FLCTL_A_BANK0_RDCTL_WAIT_8               ((uint32_t)0x00008000)          /*!< 8 wait states */
4042 #define FLCTL_A_BANK0_RDCTL_WAIT_9               ((uint32_t)0x00009000)          /*!< 9 wait states */
4043 #define FLCTL_A_BANK0_RDCTL_WAIT_10              ((uint32_t)0x0000A000)          /*!< 10 wait states */
4044 #define FLCTL_A_BANK0_RDCTL_WAIT_11              ((uint32_t)0x0000B000)          /*!< 11 wait states */
4045 #define FLCTL_A_BANK0_RDCTL_WAIT_12              ((uint32_t)0x0000C000)          /*!< 12 wait states */
4046 #define FLCTL_A_BANK0_RDCTL_WAIT_13              ((uint32_t)0x0000D000)          /*!< 13 wait states */
4047 #define FLCTL_A_BANK0_RDCTL_WAIT_14              ((uint32_t)0x0000E000)          /*!< 14 wait states */
4048 #define FLCTL_A_BANK0_RDCTL_WAIT_15              ((uint32_t)0x0000F000)          /*!< 15 wait states */
4049 /* FLCTL_A_BANK0_RDCTL[RD_MODE_STATUS] Bits */
4050 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_OFS   (16)                            /*!< RD_MODE_STATUS Bit Offset */
4051 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_MASK  ((uint32_t)0x000F0000)          /*!< RD_MODE_STATUS Bit Mask */
4052 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS0      ((uint32_t)0x00010000)          /*!< RD_MODE_STATUS Bit 0 */
4053 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS1      ((uint32_t)0x00020000)          /*!< RD_MODE_STATUS Bit 1 */
4054 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS2      ((uint32_t)0x00040000)          /*!< RD_MODE_STATUS Bit 2 */
4055 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS3      ((uint32_t)0x00080000)          /*!< RD_MODE_STATUS Bit 3 */
4056 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_0     ((uint32_t)0x00000000)          /*!< Normal read mode */
4057 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_1     ((uint32_t)0x00010000)          /*!< Read Margin 0 */
4058 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_2     ((uint32_t)0x00020000)          /*!< Read Margin 1 */
4059 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_3     ((uint32_t)0x00030000)          /*!< Program Verify */
4060 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_4     ((uint32_t)0x00040000)          /*!< Erase Verify */
4061 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_5     ((uint32_t)0x00050000)          /*!< Leakage Verify */
4062 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_9     ((uint32_t)0x00090000)          /*!< Read Margin 0B */
4063 #define FLCTL_A_BANK0_RDCTL_RD_MODE_STATUS_10    ((uint32_t)0x000A0000)          /*!< Read Margin 1B */
4064 /* FLCTL_A_BANK1_RDCTL[RD_MODE] Bits */
4065 #define FLCTL_A_BANK1_RDCTL_RD_MODE_OFS          ( 0)                            /*!< RD_MODE Bit Offset */
4066 #define FLCTL_A_BANK1_RDCTL_RD_MODE_MASK         ((uint32_t)0x0000000F)          /*!< RD_MODE Bit Mask */
4067 #define FLCTL_A_BANK1_RDCTL_RD_MODE0             ((uint32_t)0x00000001)          /*!< RD_MODE Bit 0 */
4068 #define FLCTL_A_BANK1_RDCTL_RD_MODE1             ((uint32_t)0x00000002)          /*!< RD_MODE Bit 1 */
4069 #define FLCTL_A_BANK1_RDCTL_RD_MODE2             ((uint32_t)0x00000004)          /*!< RD_MODE Bit 2 */
4070 #define FLCTL_A_BANK1_RDCTL_RD_MODE3             ((uint32_t)0x00000008)          /*!< RD_MODE Bit 3 */
4071 #define FLCTL_A_BANK1_RDCTL_RD_MODE_0            ((uint32_t)0x00000000)          /*!< Normal read mode */
4072 #define FLCTL_A_BANK1_RDCTL_RD_MODE_1            ((uint32_t)0x00000001)          /*!< Read Margin 0 */
4073 #define FLCTL_A_BANK1_RDCTL_RD_MODE_2            ((uint32_t)0x00000002)          /*!< Read Margin 1 */
4074 #define FLCTL_A_BANK1_RDCTL_RD_MODE_3            ((uint32_t)0x00000003)          /*!< Program Verify */
4075 #define FLCTL_A_BANK1_RDCTL_RD_MODE_4            ((uint32_t)0x00000004)          /*!< Erase Verify */
4076 #define FLCTL_A_BANK1_RDCTL_RD_MODE_5            ((uint32_t)0x00000005)          /*!< Leakage Verify */
4077 #define FLCTL_A_BANK1_RDCTL_RD_MODE_9            ((uint32_t)0x00000009)          /*!< Read Margin 0B */
4078 #define FLCTL_A_BANK1_RDCTL_RD_MODE_10           ((uint32_t)0x0000000A)          /*!< Read Margin 1B */
4079 /* FLCTL_A_BANK1_RDCTL[BUFI] Bits */
4080 #define FLCTL_A_BANK1_RDCTL_BUFI_OFS             ( 4)                            /*!< BUFI Bit Offset */
4081 #define FLCTL_A_BANK1_RDCTL_BUFI                 ((uint32_t)0x00000010)          /*!< Enables read buffering feature for instruction fetches to this Bank */
4082 /* FLCTL_A_BANK1_RDCTL[BUFD] Bits */
4083 #define FLCTL_A_BANK1_RDCTL_BUFD_OFS             ( 5)                            /*!< BUFD Bit Offset */
4084 #define FLCTL_A_BANK1_RDCTL_BUFD                 ((uint32_t)0x00000020)          /*!< Enables read buffering feature for data reads to this Bank */
4085 /* FLCTL_A_BANK1_RDCTL[RD_MODE_STATUS] Bits */
4086 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_OFS   (16)                            /*!< RD_MODE_STATUS Bit Offset */
4087 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_MASK  ((uint32_t)0x000F0000)          /*!< RD_MODE_STATUS Bit Mask */
4088 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS0      ((uint32_t)0x00010000)          /*!< RD_MODE_STATUS Bit 0 */
4089 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS1      ((uint32_t)0x00020000)          /*!< RD_MODE_STATUS Bit 1 */
4090 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS2      ((uint32_t)0x00040000)          /*!< RD_MODE_STATUS Bit 2 */
4091 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS3      ((uint32_t)0x00080000)          /*!< RD_MODE_STATUS Bit 3 */
4092 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_0     ((uint32_t)0x00000000)          /*!< Normal read mode */
4093 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_1     ((uint32_t)0x00010000)          /*!< Read Margin 0 */
4094 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_2     ((uint32_t)0x00020000)          /*!< Read Margin 1 */
4095 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_3     ((uint32_t)0x00030000)          /*!< Program Verify */
4096 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_4     ((uint32_t)0x00040000)          /*!< Erase Verify */
4097 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_5     ((uint32_t)0x00050000)          /*!< Leakage Verify */
4098 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_9     ((uint32_t)0x00090000)          /*!< Read Margin 0B */
4099 #define FLCTL_A_BANK1_RDCTL_RD_MODE_STATUS_10    ((uint32_t)0x000A0000)          /*!< Read Margin 1B */
4100 /* FLCTL_A_BANK1_RDCTL[WAIT] Bits */
4101 #define FLCTL_A_BANK1_RDCTL_WAIT_OFS             (12)                            /*!< WAIT Bit Offset */
4102 #define FLCTL_A_BANK1_RDCTL_WAIT_MASK            ((uint32_t)0x0000F000)          /*!< WAIT Bit Mask */
4103 #define FLCTL_A_BANK1_RDCTL_WAIT0                ((uint32_t)0x00001000)          /*!< WAIT Bit 0 */
4104 #define FLCTL_A_BANK1_RDCTL_WAIT1                ((uint32_t)0x00002000)          /*!< WAIT Bit 1 */
4105 #define FLCTL_A_BANK1_RDCTL_WAIT2                ((uint32_t)0x00004000)          /*!< WAIT Bit 2 */
4106 #define FLCTL_A_BANK1_RDCTL_WAIT3                ((uint32_t)0x00008000)          /*!< WAIT Bit 3 */
4107 #define FLCTL_A_BANK1_RDCTL_WAIT_0               ((uint32_t)0x00000000)          /*!< 0 wait states */
4108 #define FLCTL_A_BANK1_RDCTL_WAIT_1               ((uint32_t)0x00001000)          /*!< 1 wait states */
4109 #define FLCTL_A_BANK1_RDCTL_WAIT_2               ((uint32_t)0x00002000)          /*!< 2 wait states */
4110 #define FLCTL_A_BANK1_RDCTL_WAIT_3               ((uint32_t)0x00003000)          /*!< 3 wait states */
4111 #define FLCTL_A_BANK1_RDCTL_WAIT_4               ((uint32_t)0x00004000)          /*!< 4 wait states */
4112 #define FLCTL_A_BANK1_RDCTL_WAIT_5               ((uint32_t)0x00005000)          /*!< 5 wait states */
4113 #define FLCTL_A_BANK1_RDCTL_WAIT_6               ((uint32_t)0x00006000)          /*!< 6 wait states */
4114 #define FLCTL_A_BANK1_RDCTL_WAIT_7               ((uint32_t)0x00007000)          /*!< 7 wait states */
4115 #define FLCTL_A_BANK1_RDCTL_WAIT_8               ((uint32_t)0x00008000)          /*!< 8 wait states */
4116 #define FLCTL_A_BANK1_RDCTL_WAIT_9               ((uint32_t)0x00009000)          /*!< 9 wait states */
4117 #define FLCTL_A_BANK1_RDCTL_WAIT_10              ((uint32_t)0x0000A000)          /*!< 10 wait states */
4118 #define FLCTL_A_BANK1_RDCTL_WAIT_11              ((uint32_t)0x0000B000)          /*!< 11 wait states */
4119 #define FLCTL_A_BANK1_RDCTL_WAIT_12              ((uint32_t)0x0000C000)          /*!< 12 wait states */
4120 #define FLCTL_A_BANK1_RDCTL_WAIT_13              ((uint32_t)0x0000D000)          /*!< 13 wait states */
4121 #define FLCTL_A_BANK1_RDCTL_WAIT_14              ((uint32_t)0x0000E000)          /*!< 14 wait states */
4122 #define FLCTL_A_BANK1_RDCTL_WAIT_15              ((uint32_t)0x0000F000)          /*!< 15 wait states */
4123 /* FLCTL_A_RDBRST_CTLSTAT[START] Bits */
4124 #define FLCTL_A_RDBRST_CTLSTAT_START_OFS         ( 0)                            /*!< START Bit Offset */
4125 #define FLCTL_A_RDBRST_CTLSTAT_START             ((uint32_t)0x00000001)          /*!< Start of burst/compare operation */
4126 /* FLCTL_A_RDBRST_CTLSTAT[MEM_TYPE] Bits */
4127 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_OFS      ( 1)                            /*!< MEM_TYPE Bit Offset */
4128 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_MASK     ((uint32_t)0x00000006)          /*!< MEM_TYPE Bit Mask */
4129 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE0         ((uint32_t)0x00000002)          /*!< MEM_TYPE Bit 0 */
4130 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE1         ((uint32_t)0x00000004)          /*!< MEM_TYPE Bit 1 */
4131 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_0        ((uint32_t)0x00000000)          /*!< Main Memory */
4132 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_1        ((uint32_t)0x00000002)          /*!< Information Memory */
4133 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_2        ((uint32_t)0x00000004)          /*!< Reserved */
4134 #define FLCTL_A_RDBRST_CTLSTAT_MEM_TYPE_3        ((uint32_t)0x00000006)          /*!< Engineering Memory */
4135 /* FLCTL_A_RDBRST_CTLSTAT[STOP_FAIL] Bits */
4136 #define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL_OFS     ( 3)                            /*!< STOP_FAIL Bit Offset */
4137 #define FLCTL_A_RDBRST_CTLSTAT_STOP_FAIL         ((uint32_t)0x00000008)          /*!< Terminate burst/compare operation */
4138 /* FLCTL_A_RDBRST_CTLSTAT[DATA_CMP] Bits */
4139 #define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP_OFS      ( 4)                            /*!< DATA_CMP Bit Offset */
4140 #define FLCTL_A_RDBRST_CTLSTAT_DATA_CMP          ((uint32_t)0x00000010)          /*!< Data pattern used for comparison against memory read data */
4141 /* FLCTL_A_RDBRST_CTLSTAT[TEST_EN] Bits */
4142 #define FLCTL_A_RDBRST_CTLSTAT_TEST_EN_OFS       ( 6)                            /*!< TEST_EN Bit Offset */
4143 #define FLCTL_A_RDBRST_CTLSTAT_TEST_EN           ((uint32_t)0x00000040)          /*!< Enable comparison against test data compare registers */
4144 /* FLCTL_A_RDBRST_CTLSTAT[BRST_STAT] Bits */
4145 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_OFS     (16)                            /*!< BRST_STAT Bit Offset */
4146 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_MASK    ((uint32_t)0x00030000)          /*!< BRST_STAT Bit Mask */
4147 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT0        ((uint32_t)0x00010000)          /*!< BRST_STAT Bit 0 */
4148 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT1        ((uint32_t)0x00020000)          /*!< BRST_STAT Bit 1 */
4149 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_0       ((uint32_t)0x00000000)          /*!< Idle */
4150 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_1       ((uint32_t)0x00010000)          /*!< Burst/Compare START bit written, but operation pending */
4151 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_2       ((uint32_t)0x00020000)          /*!< Burst/Compare in progress */
4152 #define FLCTL_A_RDBRST_CTLSTAT_BRST_STAT_3       ((uint32_t)0x00030000)          /*!< Burst complete (status of completed burst remains in this state unless  */
4153                                                                                  /* explicitly cleared by SW) */
4154 /* FLCTL_A_RDBRST_CTLSTAT[CMP_ERR] Bits */
4155 #define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR_OFS       (18)                            /*!< CMP_ERR Bit Offset */
4156 #define FLCTL_A_RDBRST_CTLSTAT_CMP_ERR           ((uint32_t)0x00040000)          /*!< Burst/Compare Operation encountered atleast one data */
4157 /* FLCTL_A_RDBRST_CTLSTAT[ADDR_ERR] Bits */
4158 #define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR_OFS      (19)                            /*!< ADDR_ERR Bit Offset */
4159 #define FLCTL_A_RDBRST_CTLSTAT_ADDR_ERR          ((uint32_t)0x00080000)          /*!< Burst/Compare Operation was terminated due to access to */
4160 /* FLCTL_A_RDBRST_CTLSTAT[CLR_STAT] Bits */
4161 #define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT_OFS      (23)                            /*!< CLR_STAT Bit Offset */
4162 #define FLCTL_A_RDBRST_CTLSTAT_CLR_STAT          ((uint32_t)0x00800000)          /*!< Clear status bits 19-16 of this register */
4163 /* FLCTL_A_RDBRST_STARTADDR[START_ADDRESS] Bits */
4164 #define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0)                            /*!< START_ADDRESS Bit Offset */
4165 #define FLCTL_A_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF)          /*!< START_ADDRESS Bit Mask */
4166 /* FLCTL_A_RDBRST_LEN[BURST_LENGTH] Bits */
4167 #define FLCTL_A_RDBRST_LEN_BURST_LENGTH_OFS      ( 0)                            /*!< BURST_LENGTH Bit Offset */
4168 #define FLCTL_A_RDBRST_LEN_BURST_LENGTH_MASK     ((uint32_t)0x001FFFFF)          /*!< BURST_LENGTH Bit Mask */
4169 /* FLCTL_A_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */
4170 #define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0)                            /*!< FAIL_ADDRESS Bit Offset */
4171 #define FLCTL_A_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF)          /*!< FAIL_ADDRESS Bit Mask */
4172 /* FLCTL_A_RDBRST_FAILCNT[FAIL_COUNT] Bits */
4173 #define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_OFS    ( 0)                            /*!< FAIL_COUNT Bit Offset */
4174 #define FLCTL_A_RDBRST_FAILCNT_FAIL_COUNT_MASK   ((uint32_t)0x0001FFFF)          /*!< FAIL_COUNT Bit Mask */
4175 /* FLCTL_A_PRG_CTLSTAT[ENABLE] Bits */
4176 #define FLCTL_A_PRG_CTLSTAT_ENABLE_OFS           ( 0)                            /*!< ENABLE Bit Offset */
4177 #define FLCTL_A_PRG_CTLSTAT_ENABLE               ((uint32_t)0x00000001)          /*!< Master control for all word program operations */
4178 /* FLCTL_A_PRG_CTLSTAT[MODE] Bits */
4179 #define FLCTL_A_PRG_CTLSTAT_MODE_OFS             ( 1)                            /*!< MODE Bit Offset */
4180 #define FLCTL_A_PRG_CTLSTAT_MODE                 ((uint32_t)0x00000002)          /*!< Write mode */
4181 /* FLCTL_A_PRG_CTLSTAT[VER_PRE] Bits */
4182 #define FLCTL_A_PRG_CTLSTAT_VER_PRE_OFS          ( 2)                            /*!< VER_PRE Bit Offset */
4183 #define FLCTL_A_PRG_CTLSTAT_VER_PRE              ((uint32_t)0x00000004)          /*!< Controls automatic pre program verify operations */
4184 /* FLCTL_A_PRG_CTLSTAT[VER_PST] Bits */
4185 #define FLCTL_A_PRG_CTLSTAT_VER_PST_OFS          ( 3)                            /*!< VER_PST Bit Offset */
4186 #define FLCTL_A_PRG_CTLSTAT_VER_PST              ((uint32_t)0x00000008)          /*!< Controls automatic post program verify operations */
4187 /* FLCTL_A_PRG_CTLSTAT[STATUS] Bits */
4188 #define FLCTL_A_PRG_CTLSTAT_STATUS_OFS           (16)                            /*!< STATUS Bit Offset */
4189 #define FLCTL_A_PRG_CTLSTAT_STATUS_MASK          ((uint32_t)0x00030000)          /*!< STATUS Bit Mask */
4190 #define FLCTL_A_PRG_CTLSTAT_STATUS0              ((uint32_t)0x00010000)          /*!< STATUS Bit 0 */
4191 #define FLCTL_A_PRG_CTLSTAT_STATUS1              ((uint32_t)0x00020000)          /*!< STATUS Bit 1 */
4192 #define FLCTL_A_PRG_CTLSTAT_STATUS_0             ((uint32_t)0x00000000)          /*!< Idle (no program operation currently active) */
4193 #define FLCTL_A_PRG_CTLSTAT_STATUS_1             ((uint32_t)0x00010000)          /*!< Single word program operation triggered, but pending */
4194 #define FLCTL_A_PRG_CTLSTAT_STATUS_2             ((uint32_t)0x00020000)          /*!< Single word program in progress */
4195 #define FLCTL_A_PRG_CTLSTAT_STATUS_3             ((uint32_t)0x00030000)          /*!< Reserved (Idle) */
4196 /* FLCTL_A_PRG_CTLSTAT[BNK_ACT] Bits */
4197 #define FLCTL_A_PRG_CTLSTAT_BNK_ACT_OFS          (18)                            /*!< BNK_ACT Bit Offset */
4198 #define FLCTL_A_PRG_CTLSTAT_BNK_ACT              ((uint32_t)0x00040000)          /*!< Bank active */
4199 /* FLCTL_A_PRGBRST_CTLSTAT[START] Bits */
4200 #define FLCTL_A_PRGBRST_CTLSTAT_START_OFS        ( 0)                            /*!< START Bit Offset */
4201 #define FLCTL_A_PRGBRST_CTLSTAT_START            ((uint32_t)0x00000001)          /*!< Trigger start of burst program operation */
4202 /* FLCTL_A_PRGBRST_CTLSTAT[TYPE] Bits */
4203 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_OFS         ( 1)                            /*!< TYPE Bit Offset */
4204 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_MASK        ((uint32_t)0x00000006)          /*!< TYPE Bit Mask */
4205 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE0            ((uint32_t)0x00000002)          /*!< TYPE Bit 0 */
4206 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE1            ((uint32_t)0x00000004)          /*!< TYPE Bit 1 */
4207 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_0           ((uint32_t)0x00000000)          /*!< Main Memory */
4208 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_1           ((uint32_t)0x00000002)          /*!< Information Memory */
4209 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_2           ((uint32_t)0x00000004)          /*!< Reserved */
4210 #define FLCTL_A_PRGBRST_CTLSTAT_TYPE_3           ((uint32_t)0x00000006)          /*!< Engineering Memory */
4211 /* FLCTL_A_PRGBRST_CTLSTAT[LEN] Bits */
4212 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_OFS          ( 3)                            /*!< LEN Bit Offset */
4213 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_MASK         ((uint32_t)0x00000038)          /*!< LEN Bit Mask */
4214 #define FLCTL_A_PRGBRST_CTLSTAT_LEN0             ((uint32_t)0x00000008)          /*!< LEN Bit 0 */
4215 #define FLCTL_A_PRGBRST_CTLSTAT_LEN1             ((uint32_t)0x00000010)          /*!< LEN Bit 1 */
4216 #define FLCTL_A_PRGBRST_CTLSTAT_LEN2             ((uint32_t)0x00000020)          /*!< LEN Bit 2 */
4217 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_0            ((uint32_t)0x00000000)          /*!< No burst operation */
4218 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_1            ((uint32_t)0x00000008)          /*!< 1 word burst of 128 bits, starting with address in the  */
4219                                                                                  /* FLCTL_PRGBRST_STARTADDR Register */
4220 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_2            ((uint32_t)0x00000010)          /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR  */
4221                                                                                  /* Register */
4222 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_3            ((uint32_t)0x00000018)          /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR  */
4223                                                                                  /* Register */
4224 #define FLCTL_A_PRGBRST_CTLSTAT_LEN_4            ((uint32_t)0x00000020)          /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR  */
4225                                                                                  /* Register */
4226 /* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PRE] Bits */
4227 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE_OFS     ( 6)                            /*!< AUTO_PRE Bit Offset */
4228 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PRE         ((uint32_t)0x00000040)          /*!< Auto-Verify operation before the Burst Program */
4229 /* FLCTL_A_PRGBRST_CTLSTAT[AUTO_PST] Bits */
4230 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST_OFS     ( 7)                            /*!< AUTO_PST Bit Offset */
4231 #define FLCTL_A_PRGBRST_CTLSTAT_AUTO_PST         ((uint32_t)0x00000080)          /*!< Auto-Verify operation after the Burst Program */
4232 /* FLCTL_A_PRGBRST_CTLSTAT[BURST_STATUS] Bits */
4233 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16)                            /*!< BURST_STATUS Bit Offset */
4234 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000)          /*!< BURST_STATUS Bit Mask */
4235 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS0    ((uint32_t)0x00010000)          /*!< BURST_STATUS Bit 0 */
4236 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS1    ((uint32_t)0x00020000)          /*!< BURST_STATUS Bit 1 */
4237 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS2    ((uint32_t)0x00040000)          /*!< BURST_STATUS Bit 2 */
4238 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_0   ((uint32_t)0x00000000)          /*!< Idle (Burst not active) */
4239 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_1   ((uint32_t)0x00010000)          /*!< Burst program started but pending */
4240 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_2   ((uint32_t)0x00020000)          /*!< Burst active, with 1st 128 bit word being written into Flash */
4241 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_3   ((uint32_t)0x00030000)          /*!< Burst active, with 2nd 128 bit word being written into Flash */
4242 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_4   ((uint32_t)0x00040000)          /*!< Burst active, with 3rd 128 bit word being written into Flash */
4243 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_5   ((uint32_t)0x00050000)          /*!< Burst active, with 4th 128 bit word being written into Flash */
4244 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_6   ((uint32_t)0x00060000)          /*!< Reserved (Idle) */
4245 #define FLCTL_A_PRGBRST_CTLSTAT_BURST_STATUS_7   ((uint32_t)0x00070000)          /*!< Burst Complete (status of completed burst remains in this state unless  */
4246                                                                                  /* explicitly cleared by SW) */
4247 /* FLCTL_A_PRGBRST_CTLSTAT[PRE_ERR] Bits */
4248 #define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR_OFS      (19)                            /*!< PRE_ERR Bit Offset */
4249 #define FLCTL_A_PRGBRST_CTLSTAT_PRE_ERR          ((uint32_t)0x00080000)          /*!< Burst Operation encountered preprogram auto-verify errors */
4250 /* FLCTL_A_PRGBRST_CTLSTAT[PST_ERR] Bits */
4251 #define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR_OFS      (20)                            /*!< PST_ERR Bit Offset */
4252 #define FLCTL_A_PRGBRST_CTLSTAT_PST_ERR          ((uint32_t)0x00100000)          /*!< Burst Operation encountered postprogram auto-verify errors */
4253 /* FLCTL_A_PRGBRST_CTLSTAT[ADDR_ERR] Bits */
4254 #define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR_OFS     (21)                            /*!< ADDR_ERR Bit Offset */
4255 #define FLCTL_A_PRGBRST_CTLSTAT_ADDR_ERR         ((uint32_t)0x00200000)          /*!< Burst Operation was terminated due to attempted program of reserved memory */
4256 /* FLCTL_A_PRGBRST_CTLSTAT[CLR_STAT] Bits */
4257 #define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT_OFS     (23)                            /*!< CLR_STAT Bit Offset */
4258 #define FLCTL_A_PRGBRST_CTLSTAT_CLR_STAT         ((uint32_t)0x00800000)          /*!< Clear status bits 21-16 of this register */
4259 /* FLCTL_A_PRGBRST_STARTADDR[START_ADDRESS] Bits */
4260 #define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0)                            /*!< START_ADDRESS Bit Offset */
4261 #define FLCTL_A_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF)          /*!< START_ADDRESS Bit Mask */
4262 /* FLCTL_A_ERASE_CTLSTAT[START] Bits */
4263 #define FLCTL_A_ERASE_CTLSTAT_START_OFS          ( 0)                            /*!< START Bit Offset */
4264 #define FLCTL_A_ERASE_CTLSTAT_START              ((uint32_t)0x00000001)          /*!< Start of Erase operation */
4265 /* FLCTL_A_ERASE_CTLSTAT[MODE] Bits */
4266 #define FLCTL_A_ERASE_CTLSTAT_MODE_OFS           ( 1)                            /*!< MODE Bit Offset */
4267 #define FLCTL_A_ERASE_CTLSTAT_MODE               ((uint32_t)0x00000002)          /*!< Erase mode selected by application */
4268 /* FLCTL_A_ERASE_CTLSTAT[TYPE] Bits */
4269 #define FLCTL_A_ERASE_CTLSTAT_TYPE_OFS           ( 2)                            /*!< TYPE Bit Offset */
4270 #define FLCTL_A_ERASE_CTLSTAT_TYPE_MASK          ((uint32_t)0x0000000C)          /*!< TYPE Bit Mask */
4271 #define FLCTL_A_ERASE_CTLSTAT_TYPE0              ((uint32_t)0x00000004)          /*!< TYPE Bit 0 */
4272 #define FLCTL_A_ERASE_CTLSTAT_TYPE1              ((uint32_t)0x00000008)          /*!< TYPE Bit 1 */
4273 #define FLCTL_A_ERASE_CTLSTAT_TYPE_0             ((uint32_t)0x00000000)          /*!< Main Memory */
4274 #define FLCTL_A_ERASE_CTLSTAT_TYPE_1             ((uint32_t)0x00000004)          /*!< Information Memory */
4275 #define FLCTL_A_ERASE_CTLSTAT_TYPE_2             ((uint32_t)0x00000008)          /*!< Reserved */
4276 #define FLCTL_A_ERASE_CTLSTAT_TYPE_3             ((uint32_t)0x0000000C)          /*!< Engineering Memory */
4277 /* FLCTL_A_ERASE_CTLSTAT[STATUS] Bits */
4278 #define FLCTL_A_ERASE_CTLSTAT_STATUS_OFS         (16)                            /*!< STATUS Bit Offset */
4279 #define FLCTL_A_ERASE_CTLSTAT_STATUS_MASK        ((uint32_t)0x00030000)          /*!< STATUS Bit Mask */
4280 #define FLCTL_A_ERASE_CTLSTAT_STATUS0            ((uint32_t)0x00010000)          /*!< STATUS Bit 0 */
4281 #define FLCTL_A_ERASE_CTLSTAT_STATUS1            ((uint32_t)0x00020000)          /*!< STATUS Bit 1 */
4282 #define FLCTL_A_ERASE_CTLSTAT_STATUS_0           ((uint32_t)0x00000000)          /*!< Idle (no program operation currently active) */
4283 #define FLCTL_A_ERASE_CTLSTAT_STATUS_1           ((uint32_t)0x00010000)          /*!< Erase operation triggered to START but pending */
4284 #define FLCTL_A_ERASE_CTLSTAT_STATUS_2           ((uint32_t)0x00020000)          /*!< Erase operation in progress */
4285 #define FLCTL_A_ERASE_CTLSTAT_STATUS_3           ((uint32_t)0x00030000)          /*!< Erase operation completed (status of completed erase remains in this state  */
4286                                                                                  /* unless explicitly cleared by SW) */
4287 /* FLCTL_A_ERASE_CTLSTAT[ADDR_ERR] Bits */
4288 #define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR_OFS       (18)                            /*!< ADDR_ERR Bit Offset */
4289 #define FLCTL_A_ERASE_CTLSTAT_ADDR_ERR           ((uint32_t)0x00040000)          /*!< Erase Operation was terminated due to attempted erase of reserved memory  */
4290                                                                                  /* address */
4291 /* FLCTL_A_ERASE_CTLSTAT[CLR_STAT] Bits */
4292 #define FLCTL_A_ERASE_CTLSTAT_CLR_STAT_OFS       (19)                            /*!< CLR_STAT Bit Offset */
4293 #define FLCTL_A_ERASE_CTLSTAT_CLR_STAT           ((uint32_t)0x00080000)          /*!< Clear status bits 18-16 of this register */
4294 /* FLCTL_A_ERASE_SECTADDR[SECT_ADDRESS] Bits */
4295 #define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_OFS  ( 0)                            /*!< SECT_ADDRESS Bit Offset */
4296 #define FLCTL_A_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF)          /*!< SECT_ADDRESS Bit Mask */
4297 /* FLCTL_A_BANK0_INFO_WEPROT[PROT0] Bits */
4298 #define FLCTL_A_BANK0_INFO_WEPROT_PROT0_OFS      ( 0)                            /*!< PROT0 Bit Offset */
4299 #define FLCTL_A_BANK0_INFO_WEPROT_PROT0          ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
4300 /* FLCTL_A_BANK0_INFO_WEPROT[PROT1] Bits */
4301 #define FLCTL_A_BANK0_INFO_WEPROT_PROT1_OFS      ( 1)                            /*!< PROT1 Bit Offset */
4302 #define FLCTL_A_BANK0_INFO_WEPROT_PROT1          ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
4303 /* FLCTL_A_BANK0_INFO_WEPROT[PROT2] Bits */
4304 #define FLCTL_A_BANK0_INFO_WEPROT_PROT2_OFS      ( 2)                            /*!< PROT2 Bit Offset */
4305 #define FLCTL_A_BANK0_INFO_WEPROT_PROT2          ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
4306 /* FLCTL_A_BANK0_INFO_WEPROT[PROT3] Bits */
4307 #define FLCTL_A_BANK0_INFO_WEPROT_PROT3_OFS      ( 3)                            /*!< PROT3 Bit Offset */
4308 #define FLCTL_A_BANK0_INFO_WEPROT_PROT3          ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
4309 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT0] Bits */
4310 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT0_OFS      ( 0)                            /*!< PROT0 Bit Offset */
4311 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT0          ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
4312 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT1] Bits */
4313 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT1_OFS      ( 1)                            /*!< PROT1 Bit Offset */
4314 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT1          ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
4315 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT2] Bits */
4316 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT2_OFS      ( 2)                            /*!< PROT2 Bit Offset */
4317 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT2          ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
4318 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT3] Bits */
4319 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT3_OFS      ( 3)                            /*!< PROT3 Bit Offset */
4320 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT3          ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
4321 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT4] Bits */
4322 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT4_OFS      ( 4)                            /*!< PROT4 Bit Offset */
4323 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT4          ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase */
4324 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT5] Bits */
4325 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT5_OFS      ( 5)                            /*!< PROT5 Bit Offset */
4326 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT5          ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase */
4327 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT6] Bits */
4328 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT6_OFS      ( 6)                            /*!< PROT6 Bit Offset */
4329 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT6          ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase */
4330 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT7] Bits */
4331 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT7_OFS      ( 7)                            /*!< PROT7 Bit Offset */
4332 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT7          ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase */
4333 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT8] Bits */
4334 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT8_OFS      ( 8)                            /*!< PROT8 Bit Offset */
4335 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT8          ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase */
4336 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT9] Bits */
4337 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT9_OFS      ( 9)                            /*!< PROT9 Bit Offset */
4338 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT9          ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase */
4339 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT10] Bits */
4340 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT10_OFS     (10)                            /*!< PROT10 Bit Offset */
4341 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT10         ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase */
4342 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT11] Bits */
4343 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT11_OFS     (11)                            /*!< PROT11 Bit Offset */
4344 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT11         ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase */
4345 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT12] Bits */
4346 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT12_OFS     (12)                            /*!< PROT12 Bit Offset */
4347 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT12         ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase */
4348 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT13] Bits */
4349 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT13_OFS     (13)                            /*!< PROT13 Bit Offset */
4350 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT13         ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase */
4351 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT14] Bits */
4352 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT14_OFS     (14)                            /*!< PROT14 Bit Offset */
4353 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT14         ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase */
4354 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT15] Bits */
4355 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT15_OFS     (15)                            /*!< PROT15 Bit Offset */
4356 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT15         ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase */
4357 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT16] Bits */
4358 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT16_OFS     (16)                            /*!< PROT16 Bit Offset */
4359 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT16         ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase */
4360 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT17] Bits */
4361 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT17_OFS     (17)                            /*!< PROT17 Bit Offset */
4362 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT17         ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase */
4363 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT18] Bits */
4364 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT18_OFS     (18)                            /*!< PROT18 Bit Offset */
4365 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT18         ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase */
4366 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT19] Bits */
4367 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT19_OFS     (19)                            /*!< PROT19 Bit Offset */
4368 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT19         ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase */
4369 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT20] Bits */
4370 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT20_OFS     (20)                            /*!< PROT20 Bit Offset */
4371 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT20         ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase */
4372 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT21] Bits */
4373 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT21_OFS     (21)                            /*!< PROT21 Bit Offset */
4374 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT21         ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase */
4375 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT22] Bits */
4376 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT22_OFS     (22)                            /*!< PROT22 Bit Offset */
4377 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT22         ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase */
4378 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT23] Bits */
4379 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT23_OFS     (23)                            /*!< PROT23 Bit Offset */
4380 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT23         ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase */
4381 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT24] Bits */
4382 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT24_OFS     (24)                            /*!< PROT24 Bit Offset */
4383 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT24         ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase */
4384 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT25] Bits */
4385 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT25_OFS     (25)                            /*!< PROT25 Bit Offset */
4386 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT25         ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase */
4387 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT26] Bits */
4388 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT26_OFS     (26)                            /*!< PROT26 Bit Offset */
4389 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT26         ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase */
4390 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT27] Bits */
4391 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT27_OFS     (27)                            /*!< PROT27 Bit Offset */
4392 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT27         ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase */
4393 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT28] Bits */
4394 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT28_OFS     (28)                            /*!< PROT28 Bit Offset */
4395 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT28         ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase */
4396 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT29] Bits */
4397 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT29_OFS     (29)                            /*!< PROT29 Bit Offset */
4398 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT29         ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase */
4399 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT30] Bits */
4400 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT30_OFS     (30)                            /*!< PROT30 Bit Offset */
4401 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT30         ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase */
4402 /* FLCTL_A_BANK0_MAIN_WEPROT[PROT31] Bits */
4403 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT31_OFS     (31)                            /*!< PROT31 Bit Offset */
4404 #define FLCTL_A_BANK0_MAIN_WEPROT_PROT31         ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase */
4405 /* FLCTL_A_BANK1_INFO_WEPROT[PROT0] Bits */
4406 #define FLCTL_A_BANK1_INFO_WEPROT_PROT0_OFS      ( 0)                            /*!< PROT0 Bit Offset */
4407 #define FLCTL_A_BANK1_INFO_WEPROT_PROT0          ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase operations */
4408 /* FLCTL_A_BANK1_INFO_WEPROT[PROT1] Bits */
4409 #define FLCTL_A_BANK1_INFO_WEPROT_PROT1_OFS      ( 1)                            /*!< PROT1 Bit Offset */
4410 #define FLCTL_A_BANK1_INFO_WEPROT_PROT1          ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase operations */
4411 /* FLCTL_A_BANK1_INFO_WEPROT[PROT2] Bits */
4412 #define FLCTL_A_BANK1_INFO_WEPROT_PROT2_OFS      ( 2)                            /*!< PROT2 Bit Offset */
4413 #define FLCTL_A_BANK1_INFO_WEPROT_PROT2          ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
4414 /* FLCTL_A_BANK1_INFO_WEPROT[PROT3] Bits */
4415 #define FLCTL_A_BANK1_INFO_WEPROT_PROT3_OFS      ( 3)                            /*!< PROT3 Bit Offset */
4416 #define FLCTL_A_BANK1_INFO_WEPROT_PROT3          ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
4417 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT0] Bits */
4418 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT0_OFS      ( 0)                            /*!< PROT0 Bit Offset */
4419 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT0          ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase operations */
4420 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT1] Bits */
4421 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT1_OFS      ( 1)                            /*!< PROT1 Bit Offset */
4422 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT1          ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase operations */
4423 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT2] Bits */
4424 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT2_OFS      ( 2)                            /*!< PROT2 Bit Offset */
4425 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT2          ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase operations */
4426 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT3] Bits */
4427 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT3_OFS      ( 3)                            /*!< PROT3 Bit Offset */
4428 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT3          ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase operations */
4429 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT4] Bits */
4430 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT4_OFS      ( 4)                            /*!< PROT4 Bit Offset */
4431 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT4          ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase operations */
4432 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT5] Bits */
4433 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT5_OFS      ( 5)                            /*!< PROT5 Bit Offset */
4434 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT5          ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase operations */
4435 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT6] Bits */
4436 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT6_OFS      ( 6)                            /*!< PROT6 Bit Offset */
4437 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT6          ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase operations */
4438 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT7] Bits */
4439 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT7_OFS      ( 7)                            /*!< PROT7 Bit Offset */
4440 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT7          ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase operations */
4441 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT8] Bits */
4442 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT8_OFS      ( 8)                            /*!< PROT8 Bit Offset */
4443 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT8          ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase operations */
4444 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT9] Bits */
4445 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT9_OFS      ( 9)                            /*!< PROT9 Bit Offset */
4446 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT9          ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase operations */
4447 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT10] Bits */
4448 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT10_OFS     (10)                            /*!< PROT10 Bit Offset */
4449 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT10         ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase operations */
4450 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT11] Bits */
4451 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT11_OFS     (11)                            /*!< PROT11 Bit Offset */
4452 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT11         ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase operations */
4453 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT12] Bits */
4454 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT12_OFS     (12)                            /*!< PROT12 Bit Offset */
4455 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT12         ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase operations */
4456 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT13] Bits */
4457 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT13_OFS     (13)                            /*!< PROT13 Bit Offset */
4458 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT13         ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase operations */
4459 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT14] Bits */
4460 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT14_OFS     (14)                            /*!< PROT14 Bit Offset */
4461 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT14         ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase operations */
4462 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT15] Bits */
4463 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT15_OFS     (15)                            /*!< PROT15 Bit Offset */
4464 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT15         ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase operations */
4465 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT16] Bits */
4466 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT16_OFS     (16)                            /*!< PROT16 Bit Offset */
4467 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT16         ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase operations */
4468 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT17] Bits */
4469 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT17_OFS     (17)                            /*!< PROT17 Bit Offset */
4470 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT17         ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase operations */
4471 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT18] Bits */
4472 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT18_OFS     (18)                            /*!< PROT18 Bit Offset */
4473 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT18         ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase operations */
4474 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT19] Bits */
4475 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT19_OFS     (19)                            /*!< PROT19 Bit Offset */
4476 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT19         ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase operations */
4477 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT20] Bits */
4478 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT20_OFS     (20)                            /*!< PROT20 Bit Offset */
4479 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT20         ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase operations */
4480 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT21] Bits */
4481 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT21_OFS     (21)                            /*!< PROT21 Bit Offset */
4482 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT21         ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase operations */
4483 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT22] Bits */
4484 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT22_OFS     (22)                            /*!< PROT22 Bit Offset */
4485 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT22         ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase operations */
4486 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT23] Bits */
4487 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT23_OFS     (23)                            /*!< PROT23 Bit Offset */
4488 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT23         ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase operations */
4489 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT24] Bits */
4490 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT24_OFS     (24)                            /*!< PROT24 Bit Offset */
4491 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT24         ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase operations */
4492 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT25] Bits */
4493 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT25_OFS     (25)                            /*!< PROT25 Bit Offset */
4494 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT25         ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase operations */
4495 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT26] Bits */
4496 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT26_OFS     (26)                            /*!< PROT26 Bit Offset */
4497 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT26         ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase operations */
4498 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT27] Bits */
4499 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT27_OFS     (27)                            /*!< PROT27 Bit Offset */
4500 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT27         ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase operations */
4501 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT28] Bits */
4502 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT28_OFS     (28)                            /*!< PROT28 Bit Offset */
4503 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT28         ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase operations */
4504 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT29] Bits */
4505 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT29_OFS     (29)                            /*!< PROT29 Bit Offset */
4506 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT29         ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase operations */
4507 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT30] Bits */
4508 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT30_OFS     (30)                            /*!< PROT30 Bit Offset */
4509 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT30         ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase operations */
4510 /* FLCTL_A_BANK1_MAIN_WEPROT[PROT31] Bits */
4511 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT31_OFS     (31)                            /*!< PROT31 Bit Offset */
4512 #define FLCTL_A_BANK1_MAIN_WEPROT_PROT31         ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase operations */
4513 /* FLCTL_A_BMRK_CTLSTAT[I_BMRK] Bits */
4514 #define FLCTL_A_BMRK_CTLSTAT_I_BMRK_OFS          ( 0)                            /*!< I_BMRK Bit Offset */
4515 #define FLCTL_A_BMRK_CTLSTAT_I_BMRK              ((uint32_t)0x00000001)
4516 /* FLCTL_A_BMRK_CTLSTAT[D_BMRK] Bits */
4517 #define FLCTL_A_BMRK_CTLSTAT_D_BMRK_OFS          ( 1)                            /*!< D_BMRK Bit Offset */
4518 #define FLCTL_A_BMRK_CTLSTAT_D_BMRK              ((uint32_t)0x00000002)
4519 /* FLCTL_A_BMRK_CTLSTAT[CMP_EN] Bits */
4520 #define FLCTL_A_BMRK_CTLSTAT_CMP_EN_OFS          ( 2)                            /*!< CMP_EN Bit Offset */
4521 #define FLCTL_A_BMRK_CTLSTAT_CMP_EN              ((uint32_t)0x00000004)
4522 /* FLCTL_A_BMRK_CTLSTAT[CMP_SEL] Bits */
4523 #define FLCTL_A_BMRK_CTLSTAT_CMP_SEL_OFS         ( 3)                            /*!< CMP_SEL Bit Offset */
4524 #define FLCTL_A_BMRK_CTLSTAT_CMP_SEL             ((uint32_t)0x00000008)
4525 /* FLCTL_A_IFG[RDBRST] Bits */
4526 #define FLCTL_A_IFG_RDBRST_OFS                   ( 0)                            /*!< RDBRST Bit Offset */
4527 #define FLCTL_A_IFG_RDBRST                       ((uint32_t)0x00000001)
4528 /* FLCTL_A_IFG[AVPRE] Bits */
4529 #define FLCTL_A_IFG_AVPRE_OFS                    ( 1)                            /*!< AVPRE Bit Offset */
4530 #define FLCTL_A_IFG_AVPRE                        ((uint32_t)0x00000002)
4531 /* FLCTL_A_IFG[AVPST] Bits */
4532 #define FLCTL_A_IFG_AVPST_OFS                    ( 2)                            /*!< AVPST Bit Offset */
4533 #define FLCTL_A_IFG_AVPST                        ((uint32_t)0x00000004)
4534 /* FLCTL_A_IFG[PRG] Bits */
4535 #define FLCTL_A_IFG_PRG_OFS                      ( 3)                            /*!< PRG Bit Offset */
4536 #define FLCTL_A_IFG_PRG                          ((uint32_t)0x00000008)
4537 /* FLCTL_A_IFG[PRGB] Bits */
4538 #define FLCTL_A_IFG_PRGB_OFS                     ( 4)                            /*!< PRGB Bit Offset */
4539 #define FLCTL_A_IFG_PRGB                         ((uint32_t)0x00000010)
4540 /* FLCTL_A_IFG[ERASE] Bits */
4541 #define FLCTL_A_IFG_ERASE_OFS                    ( 5)                            /*!< ERASE Bit Offset */
4542 #define FLCTL_A_IFG_ERASE                        ((uint32_t)0x00000020)
4543 /* FLCTL_A_IFG[BMRK] Bits */
4544 #define FLCTL_A_IFG_BMRK_OFS                     ( 8)                            /*!< BMRK Bit Offset */
4545 #define FLCTL_A_IFG_BMRK                         ((uint32_t)0x00000100)
4546 /* FLCTL_A_IFG[PRG_ERR] Bits */
4547 #define FLCTL_A_IFG_PRG_ERR_OFS                  ( 9)                            /*!< PRG_ERR Bit Offset */
4548 #define FLCTL_A_IFG_PRG_ERR                      ((uint32_t)0x00000200)
4549 /* FLCTL_A_IE[RDBRST] Bits */
4550 #define FLCTL_A_IE_RDBRST_OFS                    ( 0)                            /*!< RDBRST Bit Offset */
4551 #define FLCTL_A_IE_RDBRST                        ((uint32_t)0x00000001)
4552 /* FLCTL_A_IE[AVPRE] Bits */
4553 #define FLCTL_A_IE_AVPRE_OFS                     ( 1)                            /*!< AVPRE Bit Offset */
4554 #define FLCTL_A_IE_AVPRE                         ((uint32_t)0x00000002)
4555 /* FLCTL_A_IE[AVPST] Bits */
4556 #define FLCTL_A_IE_AVPST_OFS                     ( 2)                            /*!< AVPST Bit Offset */
4557 #define FLCTL_A_IE_AVPST                         ((uint32_t)0x00000004)
4558 /* FLCTL_A_IE[PRG] Bits */
4559 #define FLCTL_A_IE_PRG_OFS                       ( 3)                            /*!< PRG Bit Offset */
4560 #define FLCTL_A_IE_PRG                           ((uint32_t)0x00000008)
4561 /* FLCTL_A_IE[PRGB] Bits */
4562 #define FLCTL_A_IE_PRGB_OFS                      ( 4)                            /*!< PRGB Bit Offset */
4563 #define FLCTL_A_IE_PRGB                          ((uint32_t)0x00000010)
4564 /* FLCTL_A_IE[ERASE] Bits */
4565 #define FLCTL_A_IE_ERASE_OFS                     ( 5)                            /*!< ERASE Bit Offset */
4566 #define FLCTL_A_IE_ERASE                         ((uint32_t)0x00000020)
4567 /* FLCTL_A_IE[BMRK] Bits */
4568 #define FLCTL_A_IE_BMRK_OFS                      ( 8)                            /*!< BMRK Bit Offset */
4569 #define FLCTL_A_IE_BMRK                          ((uint32_t)0x00000100)
4570 /* FLCTL_A_IE[PRG_ERR] Bits */
4571 #define FLCTL_A_IE_PRG_ERR_OFS                   ( 9)                            /*!< PRG_ERR Bit Offset */
4572 #define FLCTL_A_IE_PRG_ERR                       ((uint32_t)0x00000200)
4573 /* FLCTL_A_CLRIFG[RDBRST] Bits */
4574 #define FLCTL_A_CLRIFG_RDBRST_OFS                ( 0)                            /*!< RDBRST Bit Offset */
4575 #define FLCTL_A_CLRIFG_RDBRST                    ((uint32_t)0x00000001)
4576 /* FLCTL_A_CLRIFG[AVPRE] Bits */
4577 #define FLCTL_A_CLRIFG_AVPRE_OFS                 ( 1)                            /*!< AVPRE Bit Offset */
4578 #define FLCTL_A_CLRIFG_AVPRE                     ((uint32_t)0x00000002)
4579 /* FLCTL_A_CLRIFG[AVPST] Bits */
4580 #define FLCTL_A_CLRIFG_AVPST_OFS                 ( 2)                            /*!< AVPST Bit Offset */
4581 #define FLCTL_A_CLRIFG_AVPST                     ((uint32_t)0x00000004)
4582 /* FLCTL_A_CLRIFG[PRG] Bits */
4583 #define FLCTL_A_CLRIFG_PRG_OFS                   ( 3)                            /*!< PRG Bit Offset */
4584 #define FLCTL_A_CLRIFG_PRG                       ((uint32_t)0x00000008)
4585 /* FLCTL_A_CLRIFG[PRGB] Bits */
4586 #define FLCTL_A_CLRIFG_PRGB_OFS                  ( 4)                            /*!< PRGB Bit Offset */
4587 #define FLCTL_A_CLRIFG_PRGB                      ((uint32_t)0x00000010)
4588 /* FLCTL_A_CLRIFG[ERASE] Bits */
4589 #define FLCTL_A_CLRIFG_ERASE_OFS                 ( 5)                            /*!< ERASE Bit Offset */
4590 #define FLCTL_A_CLRIFG_ERASE                     ((uint32_t)0x00000020)
4591 /* FLCTL_A_CLRIFG[BMRK] Bits */
4592 #define FLCTL_A_CLRIFG_BMRK_OFS                  ( 8)                            /*!< BMRK Bit Offset */
4593 #define FLCTL_A_CLRIFG_BMRK                      ((uint32_t)0x00000100)
4594 /* FLCTL_A_CLRIFG[PRG_ERR] Bits */
4595 #define FLCTL_A_CLRIFG_PRG_ERR_OFS               ( 9)                            /*!< PRG_ERR Bit Offset */
4596 #define FLCTL_A_CLRIFG_PRG_ERR                   ((uint32_t)0x00000200)
4597 /* FLCTL_A_SETIFG[RDBRST] Bits */
4598 #define FLCTL_A_SETIFG_RDBRST_OFS                ( 0)                            /*!< RDBRST Bit Offset */
4599 #define FLCTL_A_SETIFG_RDBRST                    ((uint32_t)0x00000001)
4600 /* FLCTL_A_SETIFG[AVPRE] Bits */
4601 #define FLCTL_A_SETIFG_AVPRE_OFS                 ( 1)                            /*!< AVPRE Bit Offset */
4602 #define FLCTL_A_SETIFG_AVPRE                     ((uint32_t)0x00000002)
4603 /* FLCTL_A_SETIFG[AVPST] Bits */
4604 #define FLCTL_A_SETIFG_AVPST_OFS                 ( 2)                            /*!< AVPST Bit Offset */
4605 #define FLCTL_A_SETIFG_AVPST                     ((uint32_t)0x00000004)
4606 /* FLCTL_A_SETIFG[PRG] Bits */
4607 #define FLCTL_A_SETIFG_PRG_OFS                   ( 3)                            /*!< PRG Bit Offset */
4608 #define FLCTL_A_SETIFG_PRG                       ((uint32_t)0x00000008)
4609 /* FLCTL_A_SETIFG[PRGB] Bits */
4610 #define FLCTL_A_SETIFG_PRGB_OFS                  ( 4)                            /*!< PRGB Bit Offset */
4611 #define FLCTL_A_SETIFG_PRGB                      ((uint32_t)0x00000010)
4612 /* FLCTL_A_SETIFG[ERASE] Bits */
4613 #define FLCTL_A_SETIFG_ERASE_OFS                 ( 5)                            /*!< ERASE Bit Offset */
4614 #define FLCTL_A_SETIFG_ERASE                     ((uint32_t)0x00000020)
4615 /* FLCTL_A_SETIFG[BMRK] Bits */
4616 #define FLCTL_A_SETIFG_BMRK_OFS                  ( 8)                            /*!< BMRK Bit Offset */
4617 #define FLCTL_A_SETIFG_BMRK                      ((uint32_t)0x00000100)
4618 /* FLCTL_A_SETIFG[PRG_ERR] Bits */
4619 #define FLCTL_A_SETIFG_PRG_ERR_OFS               ( 9)                            /*!< PRG_ERR Bit Offset */
4620 #define FLCTL_A_SETIFG_PRG_ERR                   ((uint32_t)0x00000200)
4621 /* FLCTL_A_READ_TIMCTL[SETUP] Bits */
4622 #define FLCTL_A_READ_TIMCTL_SETUP_OFS            ( 0)                            /*!< SETUP Bit Offset */
4623 #define FLCTL_A_READ_TIMCTL_SETUP_MASK           ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
4624 /* FLCTL_A_READ_TIMCTL[IREF_BOOST1] Bits */
4625 #define FLCTL_A_READ_TIMCTL_IREF_BOOST1_OFS      (12)                            /*!< IREF_BOOST1 Bit Offset */
4626 #define FLCTL_A_READ_TIMCTL_IREF_BOOST1_MASK     ((uint32_t)0x0000F000)          /*!< IREF_BOOST1 Bit Mask */
4627 /* FLCTL_A_READ_TIMCTL[SETUP_LONG] Bits */
4628 #define FLCTL_A_READ_TIMCTL_SETUP_LONG_OFS       (16)                            /*!< SETUP_LONG Bit Offset */
4629 #define FLCTL_A_READ_TIMCTL_SETUP_LONG_MASK      ((uint32_t)0x00FF0000)          /*!< SETUP_LONG Bit Mask */
4630 /* FLCTL_A_READMARGIN_TIMCTL[SETUP] Bits */
4631 #define FLCTL_A_READMARGIN_TIMCTL_SETUP_OFS      ( 0)                            /*!< SETUP Bit Offset */
4632 #define FLCTL_A_READMARGIN_TIMCTL_SETUP_MASK     ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
4633 /* FLCTL_A_PRGVER_TIMCTL[SETUP] Bits */
4634 #define FLCTL_A_PRGVER_TIMCTL_SETUP_OFS          ( 0)                            /*!< SETUP Bit Offset */
4635 #define FLCTL_A_PRGVER_TIMCTL_SETUP_MASK         ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
4636 /* FLCTL_A_PRGVER_TIMCTL[ACTIVE] Bits */
4637 #define FLCTL_A_PRGVER_TIMCTL_ACTIVE_OFS         ( 8)                            /*!< ACTIVE Bit Offset */
4638 #define FLCTL_A_PRGVER_TIMCTL_ACTIVE_MASK        ((uint32_t)0x00000F00)          /*!< ACTIVE Bit Mask */
4639 /* FLCTL_A_PRGVER_TIMCTL[HOLD] Bits */
4640 #define FLCTL_A_PRGVER_TIMCTL_HOLD_OFS           (12)                            /*!< HOLD Bit Offset */
4641 #define FLCTL_A_PRGVER_TIMCTL_HOLD_MASK          ((uint32_t)0x0000F000)          /*!< HOLD Bit Mask */
4642 /* FLCTL_A_ERSVER_TIMCTL[SETUP] Bits */
4643 #define FLCTL_A_ERSVER_TIMCTL_SETUP_OFS          ( 0)                            /*!< SETUP Bit Offset */
4644 #define FLCTL_A_ERSVER_TIMCTL_SETUP_MASK         ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
4645 /* FLCTL_A_LKGVER_TIMCTL[SETUP] Bits */
4646 #define FLCTL_A_LKGVER_TIMCTL_SETUP_OFS          ( 0)                            /*!< SETUP Bit Offset */
4647 #define FLCTL_A_LKGVER_TIMCTL_SETUP_MASK         ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
4648 /* FLCTL_A_PROGRAM_TIMCTL[SETUP] Bits */
4649 #define FLCTL_A_PROGRAM_TIMCTL_SETUP_OFS         ( 0)                            /*!< SETUP Bit Offset */
4650 #define FLCTL_A_PROGRAM_TIMCTL_SETUP_MASK        ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
4651 /* FLCTL_A_PROGRAM_TIMCTL[ACTIVE] Bits */
4652 #define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_OFS        ( 8)                            /*!< ACTIVE Bit Offset */
4653 #define FLCTL_A_PROGRAM_TIMCTL_ACTIVE_MASK       ((uint32_t)0x0FFFFF00)          /*!< ACTIVE Bit Mask */
4654 /* FLCTL_A_PROGRAM_TIMCTL[HOLD] Bits */
4655 #define FLCTL_A_PROGRAM_TIMCTL_HOLD_OFS          (28)                            /*!< HOLD Bit Offset */
4656 #define FLCTL_A_PROGRAM_TIMCTL_HOLD_MASK         ((uint32_t)0xF0000000)          /*!< HOLD Bit Mask */
4657 /* FLCTL_A_ERASE_TIMCTL[SETUP] Bits */
4658 #define FLCTL_A_ERASE_TIMCTL_SETUP_OFS           ( 0)                            /*!< SETUP Bit Offset */
4659 #define FLCTL_A_ERASE_TIMCTL_SETUP_MASK          ((uint32_t)0x000000FF)          /*!< SETUP Bit Mask */
4660 /* FLCTL_A_ERASE_TIMCTL[ACTIVE] Bits */
4661 #define FLCTL_A_ERASE_TIMCTL_ACTIVE_OFS          ( 8)                            /*!< ACTIVE Bit Offset */
4662 #define FLCTL_A_ERASE_TIMCTL_ACTIVE_MASK         ((uint32_t)0x0FFFFF00)          /*!< ACTIVE Bit Mask */
4663 /* FLCTL_A_ERASE_TIMCTL[HOLD] Bits */
4664 #define FLCTL_A_ERASE_TIMCTL_HOLD_OFS            (28)                            /*!< HOLD Bit Offset */
4665 #define FLCTL_A_ERASE_TIMCTL_HOLD_MASK           ((uint32_t)0xF0000000)          /*!< HOLD Bit Mask */
4666 /* FLCTL_A_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */
4667 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0)                            /*!< BOOST_ACTIVE Bit Offset */
4668 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF)          /*!< BOOST_ACTIVE Bit Mask */
4669 /* FLCTL_A_MASSERASE_TIMCTL[BOOST_HOLD] Bits */
4670 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_OFS  ( 8)                            /*!< BOOST_HOLD Bit Offset */
4671 #define FLCTL_A_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00)          /*!< BOOST_HOLD Bit Mask */
4672 /* FLCTL_A_BURSTPRG_TIMCTL[ACTIVE] Bits */
4673 #define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_OFS       ( 8)                            /*!< ACTIVE Bit Offset */
4674 #define FLCTL_A_BURSTPRG_TIMCTL_ACTIVE_MASK      ((uint32_t)0x0FFFFF00)          /*!< ACTIVE Bit Mask */
4675 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT0] Bits */
4676 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0_OFS     ( 0)                            /*!< PROT0 Bit Offset */
4677 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT0         ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
4678 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT1] Bits */
4679 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1_OFS     ( 1)                            /*!< PROT1 Bit Offset */
4680 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT1         ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
4681 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT2] Bits */
4682 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2_OFS     ( 2)                            /*!< PROT2 Bit Offset */
4683 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT2         ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
4684 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT3] Bits */
4685 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3_OFS     ( 3)                            /*!< PROT3 Bit Offset */
4686 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT3         ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
4687 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT4] Bits */
4688 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4_OFS     ( 4)                            /*!< PROT4 Bit Offset */
4689 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT4         ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase */
4690 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT5] Bits */
4691 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5_OFS     ( 5)                            /*!< PROT5 Bit Offset */
4692 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT5         ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase */
4693 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT6] Bits */
4694 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6_OFS     ( 6)                            /*!< PROT6 Bit Offset */
4695 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT6         ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase */
4696 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT7] Bits */
4697 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7_OFS     ( 7)                            /*!< PROT7 Bit Offset */
4698 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT7         ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase */
4699 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT8] Bits */
4700 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8_OFS     ( 8)                            /*!< PROT8 Bit Offset */
4701 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT8         ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase */
4702 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT9] Bits */
4703 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9_OFS     ( 9)                            /*!< PROT9 Bit Offset */
4704 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT9         ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase */
4705 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT10] Bits */
4706 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10_OFS    (10)                            /*!< PROT10 Bit Offset */
4707 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT10        ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase */
4708 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT11] Bits */
4709 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11_OFS    (11)                            /*!< PROT11 Bit Offset */
4710 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT11        ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase */
4711 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT12] Bits */
4712 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12_OFS    (12)                            /*!< PROT12 Bit Offset */
4713 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT12        ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase */
4714 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT13] Bits */
4715 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13_OFS    (13)                            /*!< PROT13 Bit Offset */
4716 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT13        ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase */
4717 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT14] Bits */
4718 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14_OFS    (14)                            /*!< PROT14 Bit Offset */
4719 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT14        ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase */
4720 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT15] Bits */
4721 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15_OFS    (15)                            /*!< PROT15 Bit Offset */
4722 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT15        ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase */
4723 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT16] Bits */
4724 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16_OFS    (16)                            /*!< PROT16 Bit Offset */
4725 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT16        ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase */
4726 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT17] Bits */
4727 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17_OFS    (17)                            /*!< PROT17 Bit Offset */
4728 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT17        ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase */
4729 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT18] Bits */
4730 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18_OFS    (18)                            /*!< PROT18 Bit Offset */
4731 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT18        ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase */
4732 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT19] Bits */
4733 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19_OFS    (19)                            /*!< PROT19 Bit Offset */
4734 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT19        ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase */
4735 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT20] Bits */
4736 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20_OFS    (20)                            /*!< PROT20 Bit Offset */
4737 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT20        ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase */
4738 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT21] Bits */
4739 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21_OFS    (21)                            /*!< PROT21 Bit Offset */
4740 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT21        ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase */
4741 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT22] Bits */
4742 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22_OFS    (22)                            /*!< PROT22 Bit Offset */
4743 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT22        ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase */
4744 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT23] Bits */
4745 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23_OFS    (23)                            /*!< PROT23 Bit Offset */
4746 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT23        ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase */
4747 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT24] Bits */
4748 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24_OFS    (24)                            /*!< PROT24 Bit Offset */
4749 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT24        ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase */
4750 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT25] Bits */
4751 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25_OFS    (25)                            /*!< PROT25 Bit Offset */
4752 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT25        ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase */
4753 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT26] Bits */
4754 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26_OFS    (26)                            /*!< PROT26 Bit Offset */
4755 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT26        ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase */
4756 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT27] Bits */
4757 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27_OFS    (27)                            /*!< PROT27 Bit Offset */
4758 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT27        ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase */
4759 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT28] Bits */
4760 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28_OFS    (28)                            /*!< PROT28 Bit Offset */
4761 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT28        ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase */
4762 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT29] Bits */
4763 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29_OFS    (29)                            /*!< PROT29 Bit Offset */
4764 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT29        ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase */
4765 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT30] Bits */
4766 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30_OFS    (30)                            /*!< PROT30 Bit Offset */
4767 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT30        ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase */
4768 /* FLCTL_A_BANK0_MAIN_WEPROT0[PROT31] Bits */
4769 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31_OFS    (31)                            /*!< PROT31 Bit Offset */
4770 #define FLCTL_A_BANK0_MAIN_WEPROT0_PROT31        ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase */
4771 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT32] Bits */
4772 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32_OFS    ( 0)                            /*!< PROT32 Bit Offset */
4773 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT32        ((uint32_t)0x00000001)          /*!< Protects Sector 32 from program or erase */
4774 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT33] Bits */
4775 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33_OFS    ( 1)                            /*!< PROT33 Bit Offset */
4776 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT33        ((uint32_t)0x00000002)          /*!< Protects Sector 33 from program or erase */
4777 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT34] Bits */
4778 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34_OFS    ( 2)                            /*!< PROT34 Bit Offset */
4779 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT34        ((uint32_t)0x00000004)          /*!< Protects Sector 34 from program or erase */
4780 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT35] Bits */
4781 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35_OFS    ( 3)                            /*!< PROT35 Bit Offset */
4782 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT35        ((uint32_t)0x00000008)          /*!< Protects Sector 35 from program or erase */
4783 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT36] Bits */
4784 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36_OFS    ( 4)                            /*!< PROT36 Bit Offset */
4785 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT36        ((uint32_t)0x00000010)          /*!< Protects Sector 36 from program or erase */
4786 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT37] Bits */
4787 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37_OFS    ( 5)                            /*!< PROT37 Bit Offset */
4788 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT37        ((uint32_t)0x00000020)          /*!< Protects Sector 37 from program or erase */
4789 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT38] Bits */
4790 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38_OFS    ( 6)                            /*!< PROT38 Bit Offset */
4791 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT38        ((uint32_t)0x00000040)          /*!< Protects Sector 38 from program or erase */
4792 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT39] Bits */
4793 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39_OFS    ( 7)                            /*!< PROT39 Bit Offset */
4794 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT39        ((uint32_t)0x00000080)          /*!< Protects Sector 39 from program or erase */
4795 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT40] Bits */
4796 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40_OFS    ( 8)                            /*!< PROT40 Bit Offset */
4797 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT40        ((uint32_t)0x00000100)          /*!< Protects Sector 40 from program or erase */
4798 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT41] Bits */
4799 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41_OFS    ( 9)                            /*!< PROT41 Bit Offset */
4800 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT41        ((uint32_t)0x00000200)          /*!< Protects Sector 41 from program or erase */
4801 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT42] Bits */
4802 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42_OFS    (10)                            /*!< PROT42 Bit Offset */
4803 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT42        ((uint32_t)0x00000400)          /*!< Protects Sector 42 from program or erase */
4804 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT43] Bits */
4805 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43_OFS    (11)                            /*!< PROT43 Bit Offset */
4806 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT43        ((uint32_t)0x00000800)          /*!< Protects Sector 43 from program or erase */
4807 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT44] Bits */
4808 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44_OFS    (12)                            /*!< PROT44 Bit Offset */
4809 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT44        ((uint32_t)0x00001000)          /*!< Protects Sector 44 from program or erase */
4810 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT45] Bits */
4811 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45_OFS    (13)                            /*!< PROT45 Bit Offset */
4812 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT45        ((uint32_t)0x00002000)          /*!< Protects Sector 45 from program or erase */
4813 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT46] Bits */
4814 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46_OFS    (14)                            /*!< PROT46 Bit Offset */
4815 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT46        ((uint32_t)0x00004000)          /*!< Protects Sector 46 from program or erase */
4816 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT47] Bits */
4817 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47_OFS    (15)                            /*!< PROT47 Bit Offset */
4818 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT47        ((uint32_t)0x00008000)          /*!< Protects Sector 47 from program or erase */
4819 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT48] Bits */
4820 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48_OFS    (16)                            /*!< PROT48 Bit Offset */
4821 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT48        ((uint32_t)0x00010000)          /*!< Protects Sector 48 from program or erase */
4822 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT49] Bits */
4823 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49_OFS    (17)                            /*!< PROT49 Bit Offset */
4824 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT49        ((uint32_t)0x00020000)          /*!< Protects Sector 49 from program or erase */
4825 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT50] Bits */
4826 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50_OFS    (18)                            /*!< PROT50 Bit Offset */
4827 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT50        ((uint32_t)0x00040000)          /*!< Protects Sector 50 from program or erase */
4828 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT51] Bits */
4829 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51_OFS    (19)                            /*!< PROT51 Bit Offset */
4830 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT51        ((uint32_t)0x00080000)          /*!< Protects Sector 51 from program or erase */
4831 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT52] Bits */
4832 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52_OFS    (20)                            /*!< PROT52 Bit Offset */
4833 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT52        ((uint32_t)0x00100000)          /*!< Protects Sector 52 from program or erase */
4834 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT53] Bits */
4835 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53_OFS    (21)                            /*!< PROT53 Bit Offset */
4836 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT53        ((uint32_t)0x00200000)          /*!< Protects Sector 53 from program or erase */
4837 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT54] Bits */
4838 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54_OFS    (22)                            /*!< PROT54 Bit Offset */
4839 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT54        ((uint32_t)0x00400000)          /*!< Protects Sector 54 from program or erase */
4840 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT55] Bits */
4841 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55_OFS    (23)                            /*!< PROT55 Bit Offset */
4842 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT55        ((uint32_t)0x00800000)          /*!< Protects Sector 55 from program or erase */
4843 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT56] Bits */
4844 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56_OFS    (24)                            /*!< PROT56 Bit Offset */
4845 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT56        ((uint32_t)0x01000000)          /*!< Protects Sector 56 from program or erase */
4846 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT57] Bits */
4847 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57_OFS    (25)                            /*!< PROT57 Bit Offset */
4848 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT57        ((uint32_t)0x02000000)          /*!< Protects Sector 57 from program or erase */
4849 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT58] Bits */
4850 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58_OFS    (26)                            /*!< PROT58 Bit Offset */
4851 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT58        ((uint32_t)0x04000000)          /*!< Protects Sector 58 from program or erase */
4852 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT59] Bits */
4853 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59_OFS    (27)                            /*!< PROT59 Bit Offset */
4854 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT59        ((uint32_t)0x08000000)          /*!< Protects Sector 59 from program or erase */
4855 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT60] Bits */
4856 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60_OFS    (28)                            /*!< PROT60 Bit Offset */
4857 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT60        ((uint32_t)0x10000000)          /*!< Protects Sector 60 from program or erase */
4858 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT61] Bits */
4859 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61_OFS    (29)                            /*!< PROT61 Bit Offset */
4860 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT61        ((uint32_t)0x20000000)          /*!< Protects Sector 61 from program or erase */
4861 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT62] Bits */
4862 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62_OFS    (30)                            /*!< PROT62 Bit Offset */
4863 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT62        ((uint32_t)0x40000000)          /*!< Protects Sector 62 from program or erase */
4864 /* FLCTL_A_BANK0_MAIN_WEPROT1[PROT63] Bits */
4865 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63_OFS    (31)                            /*!< PROT63 Bit Offset */
4866 #define FLCTL_A_BANK0_MAIN_WEPROT1_PROT63        ((uint32_t)0x80000000)          /*!< Protects Sector 63 from program or erase */
4867 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT64] Bits */
4868 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64_OFS    ( 0)                            /*!< PROT64 Bit Offset */
4869 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT64        ((uint32_t)0x00000001)          /*!< Protects Sector 64 from program or erase */
4870 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT65] Bits */
4871 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65_OFS    ( 1)                            /*!< PROT65 Bit Offset */
4872 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT65        ((uint32_t)0x00000002)          /*!< Protects Sector 65 from program or erase */
4873 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT66] Bits */
4874 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66_OFS    ( 2)                            /*!< PROT66 Bit Offset */
4875 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT66        ((uint32_t)0x00000004)          /*!< Protects Sector 66 from program or erase */
4876 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT67] Bits */
4877 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67_OFS    ( 3)                            /*!< PROT67 Bit Offset */
4878 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT67        ((uint32_t)0x00000008)          /*!< Protects Sector 67 from program or erase */
4879 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT68] Bits */
4880 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68_OFS    ( 4)                            /*!< PROT68 Bit Offset */
4881 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT68        ((uint32_t)0x00000010)          /*!< Protects Sector 68 from program or erase */
4882 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT69] Bits */
4883 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69_OFS    ( 5)                            /*!< PROT69 Bit Offset */
4884 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT69        ((uint32_t)0x00000020)          /*!< Protects Sector 69 from program or erase */
4885 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT70] Bits */
4886 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70_OFS    ( 6)                            /*!< PROT70 Bit Offset */
4887 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT70        ((uint32_t)0x00000040)          /*!< Protects Sector 70 from program or erase */
4888 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT71] Bits */
4889 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71_OFS    ( 7)                            /*!< PROT71 Bit Offset */
4890 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT71        ((uint32_t)0x00000080)          /*!< Protects Sector 71 from program or erase */
4891 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT72] Bits */
4892 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72_OFS    ( 8)                            /*!< PROT72 Bit Offset */
4893 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT72        ((uint32_t)0x00000100)          /*!< Protects Sector 72 from program or erase */
4894 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT73] Bits */
4895 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73_OFS    ( 9)                            /*!< PROT73 Bit Offset */
4896 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT73        ((uint32_t)0x00000200)          /*!< Protects Sector 73 from program or erase */
4897 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT74] Bits */
4898 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74_OFS    (10)                            /*!< PROT74 Bit Offset */
4899 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT74        ((uint32_t)0x00000400)          /*!< Protects Sector 74 from program or erase */
4900 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT75] Bits */
4901 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75_OFS    (11)                            /*!< PROT75 Bit Offset */
4902 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT75        ((uint32_t)0x00000800)          /*!< Protects Sector 75 from program or erase */
4903 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT76] Bits */
4904 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76_OFS    (12)                            /*!< PROT76 Bit Offset */
4905 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT76        ((uint32_t)0x00001000)          /*!< Protects Sector 76 from program or erase */
4906 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT77] Bits */
4907 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77_OFS    (13)                            /*!< PROT77 Bit Offset */
4908 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT77        ((uint32_t)0x00002000)          /*!< Protects Sector 77 from program or erase */
4909 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT78] Bits */
4910 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78_OFS    (14)                            /*!< PROT78 Bit Offset */
4911 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT78        ((uint32_t)0x00004000)          /*!< Protects Sector 78 from program or erase */
4912 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT79] Bits */
4913 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79_OFS    (15)                            /*!< PROT79 Bit Offset */
4914 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT79        ((uint32_t)0x00008000)          /*!< Protects Sector 79 from program or erase */
4915 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT80] Bits */
4916 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80_OFS    (16)                            /*!< PROT80 Bit Offset */
4917 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT80        ((uint32_t)0x00010000)          /*!< Protects Sector 80 from program or erase */
4918 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT81] Bits */
4919 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81_OFS    (17)                            /*!< PROT81 Bit Offset */
4920 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT81        ((uint32_t)0x00020000)          /*!< Protects Sector 81 from program or erase */
4921 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT82] Bits */
4922 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82_OFS    (18)                            /*!< PROT82 Bit Offset */
4923 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT82        ((uint32_t)0x00040000)          /*!< Protects Sector 82 from program or erase */
4924 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT83] Bits */
4925 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83_OFS    (19)                            /*!< PROT83 Bit Offset */
4926 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT83        ((uint32_t)0x00080000)          /*!< Protects Sector 83 from program or erase */
4927 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT84] Bits */
4928 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84_OFS    (20)                            /*!< PROT84 Bit Offset */
4929 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT84        ((uint32_t)0x00100000)          /*!< Protects Sector 84 from program or erase */
4930 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT85] Bits */
4931 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85_OFS    (21)                            /*!< PROT85 Bit Offset */
4932 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT85        ((uint32_t)0x00200000)          /*!< Protects Sector 85 from program or erase */
4933 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT86] Bits */
4934 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86_OFS    (22)                            /*!< PROT86 Bit Offset */
4935 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT86        ((uint32_t)0x00400000)          /*!< Protects Sector 86 from program or erase */
4936 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT87] Bits */
4937 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87_OFS    (23)                            /*!< PROT87 Bit Offset */
4938 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT87        ((uint32_t)0x00800000)          /*!< Protects Sector 87 from program or erase */
4939 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT88] Bits */
4940 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88_OFS    (24)                            /*!< PROT88 Bit Offset */
4941 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT88        ((uint32_t)0x01000000)          /*!< Protects Sector 88 from program or erase */
4942 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT89] Bits */
4943 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89_OFS    (25)                            /*!< PROT89 Bit Offset */
4944 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT89        ((uint32_t)0x02000000)          /*!< Protects Sector 89 from program or erase */
4945 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT90] Bits */
4946 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90_OFS    (26)                            /*!< PROT90 Bit Offset */
4947 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT90        ((uint32_t)0x04000000)          /*!< Protects Sector 90 from program or erase */
4948 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT91] Bits */
4949 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91_OFS    (27)                            /*!< PROT91 Bit Offset */
4950 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT91        ((uint32_t)0x08000000)          /*!< Protects Sector 91 from program or erase */
4951 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT92] Bits */
4952 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92_OFS    (28)                            /*!< PROT92 Bit Offset */
4953 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT92        ((uint32_t)0x10000000)          /*!< Protects Sector 92 from program or erase */
4954 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT93] Bits */
4955 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93_OFS    (29)                            /*!< PROT93 Bit Offset */
4956 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT93        ((uint32_t)0x20000000)          /*!< Protects Sector 93 from program or erase */
4957 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT94] Bits */
4958 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94_OFS    (30)                            /*!< PROT94 Bit Offset */
4959 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT94        ((uint32_t)0x40000000)          /*!< Protects Sector 94 from program or erase */
4960 /* FLCTL_A_BANK0_MAIN_WEPROT2[PROT95] Bits */
4961 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95_OFS    (31)                            /*!< PROT95 Bit Offset */
4962 #define FLCTL_A_BANK0_MAIN_WEPROT2_PROT95        ((uint32_t)0x80000000)          /*!< Protects Sector 95 from program or erase */
4963 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT96] Bits */
4964 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96_OFS    ( 0)                            /*!< PROT96 Bit Offset */
4965 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT96        ((uint32_t)0x00000001)          /*!< Protects Sector 96 from program or erase */
4966 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT97] Bits */
4967 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97_OFS    ( 1)                            /*!< PROT97 Bit Offset */
4968 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT97        ((uint32_t)0x00000002)          /*!< Protects Sector 97 from program or erase */
4969 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT98] Bits */
4970 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98_OFS    ( 2)                            /*!< PROT98 Bit Offset */
4971 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT98        ((uint32_t)0x00000004)          /*!< Protects Sector 98 from program or erase */
4972 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT99] Bits */
4973 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99_OFS    ( 3)                            /*!< PROT99 Bit Offset */
4974 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT99        ((uint32_t)0x00000008)          /*!< Protects Sector 99 from program or erase */
4975 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT100] Bits */
4976 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100_OFS   ( 4)                            /*!< PROT100 Bit Offset */
4977 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT100       ((uint32_t)0x00000010)          /*!< Protects Sector 100 from program or erase */
4978 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT101] Bits */
4979 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101_OFS   ( 5)                            /*!< PROT101 Bit Offset */
4980 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT101       ((uint32_t)0x00000020)          /*!< Protects Sector 101 from program or erase */
4981 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT102] Bits */
4982 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102_OFS   ( 6)                            /*!< PROT102 Bit Offset */
4983 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT102       ((uint32_t)0x00000040)          /*!< Protects Sector 102 from program or erase */
4984 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT103] Bits */
4985 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103_OFS   ( 7)                            /*!< PROT103 Bit Offset */
4986 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT103       ((uint32_t)0x00000080)          /*!< Protects Sector 103 from program or erase */
4987 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT104] Bits */
4988 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104_OFS   ( 8)                            /*!< PROT104 Bit Offset */
4989 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT104       ((uint32_t)0x00000100)          /*!< Protects Sector 104 from program or erase */
4990 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT105] Bits */
4991 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105_OFS   ( 9)                            /*!< PROT105 Bit Offset */
4992 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT105       ((uint32_t)0x00000200)          /*!< Protects Sector 105 from program or erase */
4993 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT106] Bits */
4994 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106_OFS   (10)                            /*!< PROT106 Bit Offset */
4995 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT106       ((uint32_t)0x00000400)          /*!< Protects Sector 106 from program or erase */
4996 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT107] Bits */
4997 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107_OFS   (11)                            /*!< PROT107 Bit Offset */
4998 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT107       ((uint32_t)0x00000800)          /*!< Protects Sector 107 from program or erase */
4999 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT108] Bits */
5000 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108_OFS   (12)                            /*!< PROT108 Bit Offset */
5001 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT108       ((uint32_t)0x00001000)          /*!< Protects Sector 108 from program or erase */
5002 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT109] Bits */
5003 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109_OFS   (13)                            /*!< PROT109 Bit Offset */
5004 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT109       ((uint32_t)0x00002000)          /*!< Protects Sector 109 from program or erase */
5005 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT110] Bits */
5006 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110_OFS   (14)                            /*!< PROT110 Bit Offset */
5007 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT110       ((uint32_t)0x00004000)          /*!< Protects Sector 110 from program or erase */
5008 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT111] Bits */
5009 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111_OFS   (15)                            /*!< PROT111 Bit Offset */
5010 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT111       ((uint32_t)0x00008000)          /*!< Protects Sector 111 from program or erase */
5011 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT112] Bits */
5012 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112_OFS   (16)                            /*!< PROT112 Bit Offset */
5013 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT112       ((uint32_t)0x00010000)          /*!< Protects Sector 112 from program or erase */
5014 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT113] Bits */
5015 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113_OFS   (17)                            /*!< PROT113 Bit Offset */
5016 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT113       ((uint32_t)0x00020000)          /*!< Protects Sector 113 from program or erase */
5017 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT114] Bits */
5018 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114_OFS   (18)                            /*!< PROT114 Bit Offset */
5019 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT114       ((uint32_t)0x00040000)          /*!< Protects Sector 114 from program or erase */
5020 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT115] Bits */
5021 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115_OFS   (19)                            /*!< PROT115 Bit Offset */
5022 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT115       ((uint32_t)0x00080000)          /*!< Protects Sector 115 from program or erase */
5023 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT116] Bits */
5024 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116_OFS   (20)                            /*!< PROT116 Bit Offset */
5025 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT116       ((uint32_t)0x00100000)          /*!< Protects Sector 116 from program or erase */
5026 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT117] Bits */
5027 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117_OFS   (21)                            /*!< PROT117 Bit Offset */
5028 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT117       ((uint32_t)0x00200000)          /*!< Protects Sector 117 from program or erase */
5029 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT118] Bits */
5030 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118_OFS   (22)                            /*!< PROT118 Bit Offset */
5031 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT118       ((uint32_t)0x00400000)          /*!< Protects Sector 118 from program or erase */
5032 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT119] Bits */
5033 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119_OFS   (23)                            /*!< PROT119 Bit Offset */
5034 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT119       ((uint32_t)0x00800000)          /*!< Protects Sector 119 from program or erase */
5035 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT120] Bits */
5036 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120_OFS   (24)                            /*!< PROT120 Bit Offset */
5037 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT120       ((uint32_t)0x01000000)          /*!< Protects Sector 120 from program or erase */
5038 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT121] Bits */
5039 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121_OFS   (25)                            /*!< PROT121 Bit Offset */
5040 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT121       ((uint32_t)0x02000000)          /*!< Protects Sector 121 from program or erase */
5041 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT122] Bits */
5042 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122_OFS   (26)                            /*!< PROT122 Bit Offset */
5043 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT122       ((uint32_t)0x04000000)          /*!< Protects Sector 122 from program or erase */
5044 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT123] Bits */
5045 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123_OFS   (27)                            /*!< PROT123 Bit Offset */
5046 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT123       ((uint32_t)0x08000000)          /*!< Protects Sector 123 from program or erase */
5047 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT124] Bits */
5048 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124_OFS   (28)                            /*!< PROT124 Bit Offset */
5049 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT124       ((uint32_t)0x10000000)          /*!< Protects Sector 124 from program or erase */
5050 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT125] Bits */
5051 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125_OFS   (29)                            /*!< PROT125 Bit Offset */
5052 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT125       ((uint32_t)0x20000000)          /*!< Protects Sector 125 from program or erase */
5053 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT126] Bits */
5054 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126_OFS   (30)                            /*!< PROT126 Bit Offset */
5055 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT126       ((uint32_t)0x40000000)          /*!< Protects Sector 126 from program or erase */
5056 /* FLCTL_A_BANK0_MAIN_WEPROT3[PROT127] Bits */
5057 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127_OFS   (31)                            /*!< PROT127 Bit Offset */
5058 #define FLCTL_A_BANK0_MAIN_WEPROT3_PROT127       ((uint32_t)0x80000000)          /*!< Protects Sector 127 from program or erase */
5059 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT128] Bits */
5060 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128_OFS   ( 0)                            /*!< PROT128 Bit Offset */
5061 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT128       ((uint32_t)0x00000001)          /*!< Protects Sector 128 from program or erase */
5062 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT129] Bits */
5063 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129_OFS   ( 1)                            /*!< PROT129 Bit Offset */
5064 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT129       ((uint32_t)0x00000002)          /*!< Protects Sector 129 from program or erase */
5065 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT130] Bits */
5066 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130_OFS   ( 2)                            /*!< PROT130 Bit Offset */
5067 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT130       ((uint32_t)0x00000004)          /*!< Protects Sector 130 from program or erase */
5068 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT131] Bits */
5069 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131_OFS   ( 3)                            /*!< PROT131 Bit Offset */
5070 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT131       ((uint32_t)0x00000008)          /*!< Protects Sector 131 from program or erase */
5071 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT132] Bits */
5072 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132_OFS   ( 4)                            /*!< PROT132 Bit Offset */
5073 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT132       ((uint32_t)0x00000010)          /*!< Protects Sector 132 from program or erase */
5074 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT133] Bits */
5075 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133_OFS   ( 5)                            /*!< PROT133 Bit Offset */
5076 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT133       ((uint32_t)0x00000020)          /*!< Protects Sector 133 from program or erase */
5077 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT134] Bits */
5078 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134_OFS   ( 6)                            /*!< PROT134 Bit Offset */
5079 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT134       ((uint32_t)0x00000040)          /*!< Protects Sector 134 from program or erase */
5080 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT135] Bits */
5081 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135_OFS   ( 7)                            /*!< PROT135 Bit Offset */
5082 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT135       ((uint32_t)0x00000080)          /*!< Protects Sector 135 from program or erase */
5083 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT136] Bits */
5084 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136_OFS   ( 8)                            /*!< PROT136 Bit Offset */
5085 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT136       ((uint32_t)0x00000100)          /*!< Protects Sector 136 from program or erase */
5086 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT137] Bits */
5087 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137_OFS   ( 9)                            /*!< PROT137 Bit Offset */
5088 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT137       ((uint32_t)0x00000200)          /*!< Protects Sector 137 from program or erase */
5089 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT138] Bits */
5090 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138_OFS   (10)                            /*!< PROT138 Bit Offset */
5091 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT138       ((uint32_t)0x00000400)          /*!< Protects Sector 138 from program or erase */
5092 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT139] Bits */
5093 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139_OFS   (11)                            /*!< PROT139 Bit Offset */
5094 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT139       ((uint32_t)0x00000800)          /*!< Protects Sector 139 from program or erase */
5095 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT140] Bits */
5096 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140_OFS   (12)                            /*!< PROT140 Bit Offset */
5097 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT140       ((uint32_t)0x00001000)          /*!< Protects Sector 140 from program or erase */
5098 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT141] Bits */
5099 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141_OFS   (13)                            /*!< PROT141 Bit Offset */
5100 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT141       ((uint32_t)0x00002000)          /*!< Protects Sector 141 from program or erase */
5101 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT142] Bits */
5102 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142_OFS   (14)                            /*!< PROT142 Bit Offset */
5103 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT142       ((uint32_t)0x00004000)          /*!< Protects Sector 142 from program or erase */
5104 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT143] Bits */
5105 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143_OFS   (15)                            /*!< PROT143 Bit Offset */
5106 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT143       ((uint32_t)0x00008000)          /*!< Protects Sector 143 from program or erase */
5107 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT144] Bits */
5108 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144_OFS   (16)                            /*!< PROT144 Bit Offset */
5109 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT144       ((uint32_t)0x00010000)          /*!< Protects Sector 144 from program or erase */
5110 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT145] Bits */
5111 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145_OFS   (17)                            /*!< PROT145 Bit Offset */
5112 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT145       ((uint32_t)0x00020000)          /*!< Protects Sector 145 from program or erase */
5113 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT146] Bits */
5114 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146_OFS   (18)                            /*!< PROT146 Bit Offset */
5115 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT146       ((uint32_t)0x00040000)          /*!< Protects Sector 146 from program or erase */
5116 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT147] Bits */
5117 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147_OFS   (19)                            /*!< PROT147 Bit Offset */
5118 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT147       ((uint32_t)0x00080000)          /*!< Protects Sector 147 from program or erase */
5119 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT148] Bits */
5120 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148_OFS   (20)                            /*!< PROT148 Bit Offset */
5121 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT148       ((uint32_t)0x00100000)          /*!< Protects Sector 148 from program or erase */
5122 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT149] Bits */
5123 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149_OFS   (21)                            /*!< PROT149 Bit Offset */
5124 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT149       ((uint32_t)0x00200000)          /*!< Protects Sector 149 from program or erase */
5125 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT150] Bits */
5126 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150_OFS   (22)                            /*!< PROT150 Bit Offset */
5127 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT150       ((uint32_t)0x00400000)          /*!< Protects Sector 150 from program or erase */
5128 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT151] Bits */
5129 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151_OFS   (23)                            /*!< PROT151 Bit Offset */
5130 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT151       ((uint32_t)0x00800000)          /*!< Protects Sector 151 from program or erase */
5131 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT152] Bits */
5132 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152_OFS   (24)                            /*!< PROT152 Bit Offset */
5133 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT152       ((uint32_t)0x01000000)          /*!< Protects Sector 152 from program or erase */
5134 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT153] Bits */
5135 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153_OFS   (25)                            /*!< PROT153 Bit Offset */
5136 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT153       ((uint32_t)0x02000000)          /*!< Protects Sector 153 from program or erase */
5137 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT154] Bits */
5138 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154_OFS   (26)                            /*!< PROT154 Bit Offset */
5139 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT154       ((uint32_t)0x04000000)          /*!< Protects Sector 154 from program or erase */
5140 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT155] Bits */
5141 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155_OFS   (27)                            /*!< PROT155 Bit Offset */
5142 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT155       ((uint32_t)0x08000000)          /*!< Protects Sector 155 from program or erase */
5143 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT156] Bits */
5144 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156_OFS   (28)                            /*!< PROT156 Bit Offset */
5145 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT156       ((uint32_t)0x10000000)          /*!< Protects Sector 156 from program or erase */
5146 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT157] Bits */
5147 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157_OFS   (29)                            /*!< PROT157 Bit Offset */
5148 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT157       ((uint32_t)0x20000000)          /*!< Protects Sector 157 from program or erase */
5149 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT158] Bits */
5150 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158_OFS   (30)                            /*!< PROT158 Bit Offset */
5151 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT158       ((uint32_t)0x40000000)          /*!< Protects Sector 158 from program or erase */
5152 /* FLCTL_A_BANK0_MAIN_WEPROT4[PROT159] Bits */
5153 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159_OFS   (31)                            /*!< PROT159 Bit Offset */
5154 #define FLCTL_A_BANK0_MAIN_WEPROT4_PROT159       ((uint32_t)0x80000000)          /*!< Protects Sector 159 from program or erase */
5155 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT160] Bits */
5156 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160_OFS   ( 0)                            /*!< PROT160 Bit Offset */
5157 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT160       ((uint32_t)0x00000001)          /*!< Protects Sector 160 from program or erase */
5158 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT161] Bits */
5159 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161_OFS   ( 1)                            /*!< PROT161 Bit Offset */
5160 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT161       ((uint32_t)0x00000002)          /*!< Protects Sector 161 from program or erase */
5161 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT162] Bits */
5162 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162_OFS   ( 2)                            /*!< PROT162 Bit Offset */
5163 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT162       ((uint32_t)0x00000004)          /*!< Protects Sector 162 from program or erase */
5164 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT163] Bits */
5165 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163_OFS   ( 3)                            /*!< PROT163 Bit Offset */
5166 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT163       ((uint32_t)0x00000008)          /*!< Protects Sector 163 from program or erase */
5167 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT164] Bits */
5168 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164_OFS   ( 4)                            /*!< PROT164 Bit Offset */
5169 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT164       ((uint32_t)0x00000010)          /*!< Protects Sector 164 from program or erase */
5170 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT165] Bits */
5171 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165_OFS   ( 5)                            /*!< PROT165 Bit Offset */
5172 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT165       ((uint32_t)0x00000020)          /*!< Protects Sector 165 from program or erase */
5173 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT166] Bits */
5174 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166_OFS   ( 6)                            /*!< PROT166 Bit Offset */
5175 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT166       ((uint32_t)0x00000040)          /*!< Protects Sector 166 from program or erase */
5176 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT167] Bits */
5177 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167_OFS   ( 7)                            /*!< PROT167 Bit Offset */
5178 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT167       ((uint32_t)0x00000080)          /*!< Protects Sector 167 from program or erase */
5179 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT168] Bits */
5180 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168_OFS   ( 8)                            /*!< PROT168 Bit Offset */
5181 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT168       ((uint32_t)0x00000100)          /*!< Protects Sector 168 from program or erase */
5182 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT169] Bits */
5183 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169_OFS   ( 9)                            /*!< PROT169 Bit Offset */
5184 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT169       ((uint32_t)0x00000200)          /*!< Protects Sector 169 from program or erase */
5185 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT170] Bits */
5186 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170_OFS   (10)                            /*!< PROT170 Bit Offset */
5187 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT170       ((uint32_t)0x00000400)          /*!< Protects Sector 170 from program or erase */
5188 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT171] Bits */
5189 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171_OFS   (11)                            /*!< PROT171 Bit Offset */
5190 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT171       ((uint32_t)0x00000800)          /*!< Protects Sector 171 from program or erase */
5191 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT172] Bits */
5192 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172_OFS   (12)                            /*!< PROT172 Bit Offset */
5193 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT172       ((uint32_t)0x00001000)          /*!< Protects Sector 172 from program or erase */
5194 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT173] Bits */
5195 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173_OFS   (13)                            /*!< PROT173 Bit Offset */
5196 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT173       ((uint32_t)0x00002000)          /*!< Protects Sector 173 from program or erase */
5197 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT174] Bits */
5198 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174_OFS   (14)                            /*!< PROT174 Bit Offset */
5199 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT174       ((uint32_t)0x00004000)          /*!< Protects Sector 174 from program or erase */
5200 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT175] Bits */
5201 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175_OFS   (15)                            /*!< PROT175 Bit Offset */
5202 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT175       ((uint32_t)0x00008000)          /*!< Protects Sector 175 from program or erase */
5203 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT176] Bits */
5204 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176_OFS   (16)                            /*!< PROT176 Bit Offset */
5205 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT176       ((uint32_t)0x00010000)          /*!< Protects Sector 176 from program or erase */
5206 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT177] Bits */
5207 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177_OFS   (17)                            /*!< PROT177 Bit Offset */
5208 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT177       ((uint32_t)0x00020000)          /*!< Protects Sector 177 from program or erase */
5209 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT178] Bits */
5210 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178_OFS   (18)                            /*!< PROT178 Bit Offset */
5211 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT178       ((uint32_t)0x00040000)          /*!< Protects Sector 178 from program or erase */
5212 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT179] Bits */
5213 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179_OFS   (19)                            /*!< PROT179 Bit Offset */
5214 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT179       ((uint32_t)0x00080000)          /*!< Protects Sector 179 from program or erase */
5215 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT180] Bits */
5216 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180_OFS   (20)                            /*!< PROT180 Bit Offset */
5217 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT180       ((uint32_t)0x00100000)          /*!< Protects Sector 180 from program or erase */
5218 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT181] Bits */
5219 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181_OFS   (21)                            /*!< PROT181 Bit Offset */
5220 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT181       ((uint32_t)0x00200000)          /*!< Protects Sector 181 from program or erase */
5221 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT182] Bits */
5222 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182_OFS   (22)                            /*!< PROT182 Bit Offset */
5223 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT182       ((uint32_t)0x00400000)          /*!< Protects Sector 182 from program or erase */
5224 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT183] Bits */
5225 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183_OFS   (23)                            /*!< PROT183 Bit Offset */
5226 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT183       ((uint32_t)0x00800000)          /*!< Protects Sector 183 from program or erase */
5227 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT184] Bits */
5228 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184_OFS   (24)                            /*!< PROT184 Bit Offset */
5229 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT184       ((uint32_t)0x01000000)          /*!< Protects Sector 184 from program or erase */
5230 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT185] Bits */
5231 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185_OFS   (25)                            /*!< PROT185 Bit Offset */
5232 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT185       ((uint32_t)0x02000000)          /*!< Protects Sector 185 from program or erase */
5233 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT186] Bits */
5234 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186_OFS   (26)                            /*!< PROT186 Bit Offset */
5235 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT186       ((uint32_t)0x04000000)          /*!< Protects Sector 186 from program or erase */
5236 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT187] Bits */
5237 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187_OFS   (27)                            /*!< PROT187 Bit Offset */
5238 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT187       ((uint32_t)0x08000000)          /*!< Protects Sector 187 from program or erase */
5239 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT188] Bits */
5240 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188_OFS   (28)                            /*!< PROT188 Bit Offset */
5241 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT188       ((uint32_t)0x10000000)          /*!< Protects Sector 188 from program or erase */
5242 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT189] Bits */
5243 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189_OFS   (29)                            /*!< PROT189 Bit Offset */
5244 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT189       ((uint32_t)0x20000000)          /*!< Protects Sector 189 from program or erase */
5245 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT190] Bits */
5246 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190_OFS   (30)                            /*!< PROT190 Bit Offset */
5247 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT190       ((uint32_t)0x40000000)          /*!< Protects Sector 190 from program or erase */
5248 /* FLCTL_A_BANK0_MAIN_WEPROT5[PROT191] Bits */
5249 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191_OFS   (31)                            /*!< PROT191 Bit Offset */
5250 #define FLCTL_A_BANK0_MAIN_WEPROT5_PROT191       ((uint32_t)0x80000000)          /*!< Protects Sector 191 from program or erase */
5251 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT192] Bits */
5252 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192_OFS   ( 0)                            /*!< PROT192 Bit Offset */
5253 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT192       ((uint32_t)0x00000001)          /*!< Protects Sector 192 from program or erase */
5254 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT193] Bits */
5255 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193_OFS   ( 1)                            /*!< PROT193 Bit Offset */
5256 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT193       ((uint32_t)0x00000002)          /*!< Protects Sector 193 from program or erase */
5257 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT194] Bits */
5258 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194_OFS   ( 2)                            /*!< PROT194 Bit Offset */
5259 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT194       ((uint32_t)0x00000004)          /*!< Protects Sector 194 from program or erase */
5260 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT195] Bits */
5261 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195_OFS   ( 3)                            /*!< PROT195 Bit Offset */
5262 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT195       ((uint32_t)0x00000008)          /*!< Protects Sector 195 from program or erase */
5263 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT196] Bits */
5264 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196_OFS   ( 4)                            /*!< PROT196 Bit Offset */
5265 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT196       ((uint32_t)0x00000010)          /*!< Protects Sector 196 from program or erase */
5266 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT197] Bits */
5267 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197_OFS   ( 5)                            /*!< PROT197 Bit Offset */
5268 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT197       ((uint32_t)0x00000020)          /*!< Protects Sector 197 from program or erase */
5269 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT198] Bits */
5270 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198_OFS   ( 6)                            /*!< PROT198 Bit Offset */
5271 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT198       ((uint32_t)0x00000040)          /*!< Protects Sector 198 from program or erase */
5272 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT199] Bits */
5273 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199_OFS   ( 7)                            /*!< PROT199 Bit Offset */
5274 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT199       ((uint32_t)0x00000080)          /*!< Protects Sector 199 from program or erase */
5275 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT200] Bits */
5276 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200_OFS   ( 8)                            /*!< PROT200 Bit Offset */
5277 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT200       ((uint32_t)0x00000100)          /*!< Protects Sector 200 from program or erase */
5278 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT201] Bits */
5279 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201_OFS   ( 9)                            /*!< PROT201 Bit Offset */
5280 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT201       ((uint32_t)0x00000200)          /*!< Protects Sector 201 from program or erase */
5281 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT202] Bits */
5282 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202_OFS   (10)                            /*!< PROT202 Bit Offset */
5283 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT202       ((uint32_t)0x00000400)          /*!< Protects Sector 202 from program or erase */
5284 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT203] Bits */
5285 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203_OFS   (11)                            /*!< PROT203 Bit Offset */
5286 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT203       ((uint32_t)0x00000800)          /*!< Protects Sector 203 from program or erase */
5287 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT204] Bits */
5288 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204_OFS   (12)                            /*!< PROT204 Bit Offset */
5289 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT204       ((uint32_t)0x00001000)          /*!< Protects Sector 204 from program or erase */
5290 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT205] Bits */
5291 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205_OFS   (13)                            /*!< PROT205 Bit Offset */
5292 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT205       ((uint32_t)0x00002000)          /*!< Protects Sector 205 from program or erase */
5293 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT206] Bits */
5294 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206_OFS   (14)                            /*!< PROT206 Bit Offset */
5295 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT206       ((uint32_t)0x00004000)          /*!< Protects Sector 206 from program or erase */
5296 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT207] Bits */
5297 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207_OFS   (15)                            /*!< PROT207 Bit Offset */
5298 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT207       ((uint32_t)0x00008000)          /*!< Protects Sector 207 from program or erase */
5299 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT208] Bits */
5300 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208_OFS   (16)                            /*!< PROT208 Bit Offset */
5301 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT208       ((uint32_t)0x00010000)          /*!< Protects Sector 208 from program or erase */
5302 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT209] Bits */
5303 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209_OFS   (17)                            /*!< PROT209 Bit Offset */
5304 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT209       ((uint32_t)0x00020000)          /*!< Protects Sector 209 from program or erase */
5305 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT210] Bits */
5306 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210_OFS   (18)                            /*!< PROT210 Bit Offset */
5307 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT210       ((uint32_t)0x00040000)          /*!< Protects Sector 210 from program or erase */
5308 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT211] Bits */
5309 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211_OFS   (19)                            /*!< PROT211 Bit Offset */
5310 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT211       ((uint32_t)0x00080000)          /*!< Protects Sector 211 from program or erase */
5311 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT212] Bits */
5312 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212_OFS   (20)                            /*!< PROT212 Bit Offset */
5313 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT212       ((uint32_t)0x00100000)          /*!< Protects Sector 212 from program or erase */
5314 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT213] Bits */
5315 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213_OFS   (21)                            /*!< PROT213 Bit Offset */
5316 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT213       ((uint32_t)0x00200000)          /*!< Protects Sector 213 from program or erase */
5317 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT214] Bits */
5318 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214_OFS   (22)                            /*!< PROT214 Bit Offset */
5319 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT214       ((uint32_t)0x00400000)          /*!< Protects Sector 214 from program or erase */
5320 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT215] Bits */
5321 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215_OFS   (23)                            /*!< PROT215 Bit Offset */
5322 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT215       ((uint32_t)0x00800000)          /*!< Protects Sector 215 from program or erase */
5323 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT216] Bits */
5324 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216_OFS   (24)                            /*!< PROT216 Bit Offset */
5325 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT216       ((uint32_t)0x01000000)          /*!< Protects Sector 216 from program or erase */
5326 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT217] Bits */
5327 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217_OFS   (25)                            /*!< PROT217 Bit Offset */
5328 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT217       ((uint32_t)0x02000000)          /*!< Protects Sector 217 from program or erase */
5329 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT218] Bits */
5330 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218_OFS   (26)                            /*!< PROT218 Bit Offset */
5331 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT218       ((uint32_t)0x04000000)          /*!< Protects Sector 218 from program or erase */
5332 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT219] Bits */
5333 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219_OFS   (27)                            /*!< PROT219 Bit Offset */
5334 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT219       ((uint32_t)0x08000000)          /*!< Protects Sector 219 from program or erase */
5335 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT220] Bits */
5336 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220_OFS   (28)                            /*!< PROT220 Bit Offset */
5337 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT220       ((uint32_t)0x10000000)          /*!< Protects Sector 220 from program or erase */
5338 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT221] Bits */
5339 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221_OFS   (29)                            /*!< PROT221 Bit Offset */
5340 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT221       ((uint32_t)0x20000000)          /*!< Protects Sector 221 from program or erase */
5341 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT222] Bits */
5342 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222_OFS   (30)                            /*!< PROT222 Bit Offset */
5343 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT222       ((uint32_t)0x40000000)          /*!< Protects Sector 222 from program or erase */
5344 /* FLCTL_A_BANK0_MAIN_WEPROT6[PROT223] Bits */
5345 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223_OFS   (31)                            /*!< PROT223 Bit Offset */
5346 #define FLCTL_A_BANK0_MAIN_WEPROT6_PROT223       ((uint32_t)0x80000000)          /*!< Protects Sector 223 from program or erase */
5347 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT224] Bits */
5348 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224_OFS   ( 0)                            /*!< PROT224 Bit Offset */
5349 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT224       ((uint32_t)0x00000001)          /*!< Protects Sector 224 from program or erase */
5350 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT225] Bits */
5351 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225_OFS   ( 1)                            /*!< PROT225 Bit Offset */
5352 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT225       ((uint32_t)0x00000002)          /*!< Protects Sector 225 from program or erase */
5353 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT226] Bits */
5354 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226_OFS   ( 2)                            /*!< PROT226 Bit Offset */
5355 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT226       ((uint32_t)0x00000004)          /*!< Protects Sector 226 from program or erase */
5356 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT227] Bits */
5357 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227_OFS   ( 3)                            /*!< PROT227 Bit Offset */
5358 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT227       ((uint32_t)0x00000008)          /*!< Protects Sector 227 from program or erase */
5359 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT228] Bits */
5360 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228_OFS   ( 4)                            /*!< PROT228 Bit Offset */
5361 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT228       ((uint32_t)0x00000010)          /*!< Protects Sector 228 from program or erase */
5362 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT229] Bits */
5363 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229_OFS   ( 5)                            /*!< PROT229 Bit Offset */
5364 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT229       ((uint32_t)0x00000020)          /*!< Protects Sector 229 from program or erase */
5365 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT230] Bits */
5366 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230_OFS   ( 6)                            /*!< PROT230 Bit Offset */
5367 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT230       ((uint32_t)0x00000040)          /*!< Protects Sector 230 from program or erase */
5368 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT231] Bits */
5369 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231_OFS   ( 7)                            /*!< PROT231 Bit Offset */
5370 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT231       ((uint32_t)0x00000080)          /*!< Protects Sector 231 from program or erase */
5371 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT232] Bits */
5372 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232_OFS   ( 8)                            /*!< PROT232 Bit Offset */
5373 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT232       ((uint32_t)0x00000100)          /*!< Protects Sector 232 from program or erase */
5374 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT233] Bits */
5375 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233_OFS   ( 9)                            /*!< PROT233 Bit Offset */
5376 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT233       ((uint32_t)0x00000200)          /*!< Protects Sector 233 from program or erase */
5377 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT234] Bits */
5378 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234_OFS   (10)                            /*!< PROT234 Bit Offset */
5379 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT234       ((uint32_t)0x00000400)          /*!< Protects Sector 234 from program or erase */
5380 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT235] Bits */
5381 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235_OFS   (11)                            /*!< PROT235 Bit Offset */
5382 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT235       ((uint32_t)0x00000800)          /*!< Protects Sector 235 from program or erase */
5383 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT236] Bits */
5384 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236_OFS   (12)                            /*!< PROT236 Bit Offset */
5385 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT236       ((uint32_t)0x00001000)          /*!< Protects Sector 236 from program or erase */
5386 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT237] Bits */
5387 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237_OFS   (13)                            /*!< PROT237 Bit Offset */
5388 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT237       ((uint32_t)0x00002000)          /*!< Protects Sector 237 from program or erase */
5389 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT238] Bits */
5390 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238_OFS   (14)                            /*!< PROT238 Bit Offset */
5391 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT238       ((uint32_t)0x00004000)          /*!< Protects Sector 238 from program or erase */
5392 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT239] Bits */
5393 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239_OFS   (15)                            /*!< PROT239 Bit Offset */
5394 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT239       ((uint32_t)0x00008000)          /*!< Protects Sector 239 from program or erase */
5395 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT240] Bits */
5396 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240_OFS   (16)                            /*!< PROT240 Bit Offset */
5397 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT240       ((uint32_t)0x00010000)          /*!< Protects Sector 240 from program or erase */
5398 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT241] Bits */
5399 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241_OFS   (17)                            /*!< PROT241 Bit Offset */
5400 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT241       ((uint32_t)0x00020000)          /*!< Protects Sector 241 from program or erase */
5401 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT242] Bits */
5402 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242_OFS   (18)                            /*!< PROT242 Bit Offset */
5403 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT242       ((uint32_t)0x00040000)          /*!< Protects Sector 242 from program or erase */
5404 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT243] Bits */
5405 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243_OFS   (19)                            /*!< PROT243 Bit Offset */
5406 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT243       ((uint32_t)0x00080000)          /*!< Protects Sector 243 from program or erase */
5407 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT244] Bits */
5408 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244_OFS   (20)                            /*!< PROT244 Bit Offset */
5409 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT244       ((uint32_t)0x00100000)          /*!< Protects Sector 244 from program or erase */
5410 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT245] Bits */
5411 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245_OFS   (21)                            /*!< PROT245 Bit Offset */
5412 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT245       ((uint32_t)0x00200000)          /*!< Protects Sector 245 from program or erase */
5413 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT246] Bits */
5414 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246_OFS   (22)                            /*!< PROT246 Bit Offset */
5415 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT246       ((uint32_t)0x00400000)          /*!< Protects Sector 246 from program or erase */
5416 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT247] Bits */
5417 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247_OFS   (23)                            /*!< PROT247 Bit Offset */
5418 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT247       ((uint32_t)0x00800000)          /*!< Protects Sector 247 from program or erase */
5419 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT248] Bits */
5420 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248_OFS   (24)                            /*!< PROT248 Bit Offset */
5421 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT248       ((uint32_t)0x01000000)          /*!< Protects Sector 248 from program or erase */
5422 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT249] Bits */
5423 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249_OFS   (25)                            /*!< PROT249 Bit Offset */
5424 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT249       ((uint32_t)0x02000000)          /*!< Protects Sector 249 from program or erase */
5425 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT250] Bits */
5426 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250_OFS   (26)                            /*!< PROT250 Bit Offset */
5427 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT250       ((uint32_t)0x04000000)          /*!< Protects Sector 250 from program or erase */
5428 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT251] Bits */
5429 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251_OFS   (27)                            /*!< PROT251 Bit Offset */
5430 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT251       ((uint32_t)0x08000000)          /*!< Protects Sector 251 from program or erase */
5431 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT252] Bits */
5432 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252_OFS   (28)                            /*!< PROT252 Bit Offset */
5433 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT252       ((uint32_t)0x10000000)          /*!< Protects Sector 252 from program or erase */
5434 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT253] Bits */
5435 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253_OFS   (29)                            /*!< PROT253 Bit Offset */
5436 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT253       ((uint32_t)0x20000000)          /*!< Protects Sector 253 from program or erase */
5437 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT254] Bits */
5438 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254_OFS   (30)                            /*!< PROT254 Bit Offset */
5439 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT254       ((uint32_t)0x40000000)          /*!< Protects Sector 254 from program or erase */
5440 /* FLCTL_A_BANK0_MAIN_WEPROT7[PROT255] Bits */
5441 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255_OFS   (31)                            /*!< PROT255 Bit Offset */
5442 #define FLCTL_A_BANK0_MAIN_WEPROT7_PROT255       ((uint32_t)0x80000000)          /*!< Protects Sector 255 from program or erase */
5443 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT0] Bits */
5444 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0_OFS     ( 0)                            /*!< PROT0 Bit Offset */
5445 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT0         ((uint32_t)0x00000001)          /*!< Protects Sector 0 from program or erase */
5446 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT1] Bits */
5447 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1_OFS     ( 1)                            /*!< PROT1 Bit Offset */
5448 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT1         ((uint32_t)0x00000002)          /*!< Protects Sector 1 from program or erase */
5449 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT2] Bits */
5450 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2_OFS     ( 2)                            /*!< PROT2 Bit Offset */
5451 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT2         ((uint32_t)0x00000004)          /*!< Protects Sector 2 from program or erase */
5452 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT3] Bits */
5453 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3_OFS     ( 3)                            /*!< PROT3 Bit Offset */
5454 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT3         ((uint32_t)0x00000008)          /*!< Protects Sector 3 from program or erase */
5455 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT4] Bits */
5456 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4_OFS     ( 4)                            /*!< PROT4 Bit Offset */
5457 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT4         ((uint32_t)0x00000010)          /*!< Protects Sector 4 from program or erase */
5458 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT5] Bits */
5459 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5_OFS     ( 5)                            /*!< PROT5 Bit Offset */
5460 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT5         ((uint32_t)0x00000020)          /*!< Protects Sector 5 from program or erase */
5461 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT6] Bits */
5462 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6_OFS     ( 6)                            /*!< PROT6 Bit Offset */
5463 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT6         ((uint32_t)0x00000040)          /*!< Protects Sector 6 from program or erase */
5464 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT7] Bits */
5465 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7_OFS     ( 7)                            /*!< PROT7 Bit Offset */
5466 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT7         ((uint32_t)0x00000080)          /*!< Protects Sector 7 from program or erase */
5467 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT8] Bits */
5468 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8_OFS     ( 8)                            /*!< PROT8 Bit Offset */
5469 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT8         ((uint32_t)0x00000100)          /*!< Protects Sector 8 from program or erase */
5470 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT9] Bits */
5471 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9_OFS     ( 9)                            /*!< PROT9 Bit Offset */
5472 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT9         ((uint32_t)0x00000200)          /*!< Protects Sector 9 from program or erase */
5473 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT10] Bits */
5474 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10_OFS    (10)                            /*!< PROT10 Bit Offset */
5475 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT10        ((uint32_t)0x00000400)          /*!< Protects Sector 10 from program or erase */
5476 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT11] Bits */
5477 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11_OFS    (11)                            /*!< PROT11 Bit Offset */
5478 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT11        ((uint32_t)0x00000800)          /*!< Protects Sector 11 from program or erase */
5479 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT12] Bits */
5480 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12_OFS    (12)                            /*!< PROT12 Bit Offset */
5481 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT12        ((uint32_t)0x00001000)          /*!< Protects Sector 12 from program or erase */
5482 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT13] Bits */
5483 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13_OFS    (13)                            /*!< PROT13 Bit Offset */
5484 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT13        ((uint32_t)0x00002000)          /*!< Protects Sector 13 from program or erase */
5485 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT14] Bits */
5486 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14_OFS    (14)                            /*!< PROT14 Bit Offset */
5487 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT14        ((uint32_t)0x00004000)          /*!< Protects Sector 14 from program or erase */
5488 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT15] Bits */
5489 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15_OFS    (15)                            /*!< PROT15 Bit Offset */
5490 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT15        ((uint32_t)0x00008000)          /*!< Protects Sector 15 from program or erase */
5491 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT16] Bits */
5492 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16_OFS    (16)                            /*!< PROT16 Bit Offset */
5493 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT16        ((uint32_t)0x00010000)          /*!< Protects Sector 16 from program or erase */
5494 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT17] Bits */
5495 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17_OFS    (17)                            /*!< PROT17 Bit Offset */
5496 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT17        ((uint32_t)0x00020000)          /*!< Protects Sector 17 from program or erase */
5497 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT18] Bits */
5498 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18_OFS    (18)                            /*!< PROT18 Bit Offset */
5499 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT18        ((uint32_t)0x00040000)          /*!< Protects Sector 18 from program or erase */
5500 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT19] Bits */
5501 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19_OFS    (19)                            /*!< PROT19 Bit Offset */
5502 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT19        ((uint32_t)0x00080000)          /*!< Protects Sector 19 from program or erase */
5503 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT20] Bits */
5504 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20_OFS    (20)                            /*!< PROT20 Bit Offset */
5505 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT20        ((uint32_t)0x00100000)          /*!< Protects Sector 20 from program or erase */
5506 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT21] Bits */
5507 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21_OFS    (21)                            /*!< PROT21 Bit Offset */
5508 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT21        ((uint32_t)0x00200000)          /*!< Protects Sector 21 from program or erase */
5509 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT22] Bits */
5510 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22_OFS    (22)                            /*!< PROT22 Bit Offset */
5511 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT22        ((uint32_t)0x00400000)          /*!< Protects Sector 22 from program or erase */
5512 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT23] Bits */
5513 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23_OFS    (23)                            /*!< PROT23 Bit Offset */
5514 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT23        ((uint32_t)0x00800000)          /*!< Protects Sector 23 from program or erase */
5515 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT24] Bits */
5516 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24_OFS    (24)                            /*!< PROT24 Bit Offset */
5517 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT24        ((uint32_t)0x01000000)          /*!< Protects Sector 24 from program or erase */
5518 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT25] Bits */
5519 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25_OFS    (25)                            /*!< PROT25 Bit Offset */
5520 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT25        ((uint32_t)0x02000000)          /*!< Protects Sector 25 from program or erase */
5521 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT26] Bits */
5522 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26_OFS    (26)                            /*!< PROT26 Bit Offset */
5523 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT26        ((uint32_t)0x04000000)          /*!< Protects Sector 26 from program or erase */
5524 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT27] Bits */
5525 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27_OFS    (27)                            /*!< PROT27 Bit Offset */
5526 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT27        ((uint32_t)0x08000000)          /*!< Protects Sector 27 from program or erase */
5527 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT28] Bits */
5528 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28_OFS    (28)                            /*!< PROT28 Bit Offset */
5529 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT28        ((uint32_t)0x10000000)          /*!< Protects Sector 28 from program or erase */
5530 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT29] Bits */
5531 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29_OFS    (29)                            /*!< PROT29 Bit Offset */
5532 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT29        ((uint32_t)0x20000000)          /*!< Protects Sector 29 from program or erase */
5533 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT30] Bits */
5534 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30_OFS    (30)                            /*!< PROT30 Bit Offset */
5535 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT30        ((uint32_t)0x40000000)          /*!< Protects Sector 30 from program or erase */
5536 /* FLCTL_A_BANK1_MAIN_WEPROT0[PROT31] Bits */
5537 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31_OFS    (31)                            /*!< PROT31 Bit Offset */
5538 #define FLCTL_A_BANK1_MAIN_WEPROT0_PROT31        ((uint32_t)0x80000000)          /*!< Protects Sector 31 from program or erase */
5539 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT32] Bits */
5540 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32_OFS    ( 0)                            /*!< PROT32 Bit Offset */
5541 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT32        ((uint32_t)0x00000001)          /*!< Protects Sector 32 from program or erase */
5542 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT33] Bits */
5543 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33_OFS    ( 1)                            /*!< PROT33 Bit Offset */
5544 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT33        ((uint32_t)0x00000002)          /*!< Protects Sector 33 from program or erase */
5545 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT34] Bits */
5546 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34_OFS    ( 2)                            /*!< PROT34 Bit Offset */
5547 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT34        ((uint32_t)0x00000004)          /*!< Protects Sector 34 from program or erase */
5548 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT35] Bits */
5549 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35_OFS    ( 3)                            /*!< PROT35 Bit Offset */
5550 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT35        ((uint32_t)0x00000008)          /*!< Protects Sector 35 from program or erase */
5551 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT36] Bits */
5552 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36_OFS    ( 4)                            /*!< PROT36 Bit Offset */
5553 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT36        ((uint32_t)0x00000010)          /*!< Protects Sector 36 from program or erase */
5554 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT37] Bits */
5555 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37_OFS    ( 5)                            /*!< PROT37 Bit Offset */
5556 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT37        ((uint32_t)0x00000020)          /*!< Protects Sector 37 from program or erase */
5557 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT38] Bits */
5558 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38_OFS    ( 6)                            /*!< PROT38 Bit Offset */
5559 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT38        ((uint32_t)0x00000040)          /*!< Protects Sector 38 from program or erase */
5560 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT39] Bits */
5561 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39_OFS    ( 7)                            /*!< PROT39 Bit Offset */
5562 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT39        ((uint32_t)0x00000080)          /*!< Protects Sector 39 from program or erase */
5563 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT40] Bits */
5564 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40_OFS    ( 8)                            /*!< PROT40 Bit Offset */
5565 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT40        ((uint32_t)0x00000100)          /*!< Protects Sector 40 from program or erase */
5566 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT41] Bits */
5567 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41_OFS    ( 9)                            /*!< PROT41 Bit Offset */
5568 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT41        ((uint32_t)0x00000200)          /*!< Protects Sector 41 from program or erase */
5569 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT42] Bits */
5570 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42_OFS    (10)                            /*!< PROT42 Bit Offset */
5571 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT42        ((uint32_t)0x00000400)          /*!< Protects Sector 42 from program or erase */
5572 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT43] Bits */
5573 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43_OFS    (11)                            /*!< PROT43 Bit Offset */
5574 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT43        ((uint32_t)0x00000800)          /*!< Protects Sector 43 from program or erase */
5575 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT44] Bits */
5576 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44_OFS    (12)                            /*!< PROT44 Bit Offset */
5577 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT44        ((uint32_t)0x00001000)          /*!< Protects Sector 44 from program or erase */
5578 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT45] Bits */
5579 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45_OFS    (13)                            /*!< PROT45 Bit Offset */
5580 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT45        ((uint32_t)0x00002000)          /*!< Protects Sector 45 from program or erase */
5581 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT46] Bits */
5582 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46_OFS    (14)                            /*!< PROT46 Bit Offset */
5583 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT46        ((uint32_t)0x00004000)          /*!< Protects Sector 46 from program or erase */
5584 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT47] Bits */
5585 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47_OFS    (15)                            /*!< PROT47 Bit Offset */
5586 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT47        ((uint32_t)0x00008000)          /*!< Protects Sector 47 from program or erase */
5587 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT48] Bits */
5588 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48_OFS    (16)                            /*!< PROT48 Bit Offset */
5589 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT48        ((uint32_t)0x00010000)          /*!< Protects Sector 48 from program or erase */
5590 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT49] Bits */
5591 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49_OFS    (17)                            /*!< PROT49 Bit Offset */
5592 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT49        ((uint32_t)0x00020000)          /*!< Protects Sector 49 from program or erase */
5593 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT50] Bits */
5594 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50_OFS    (18)                            /*!< PROT50 Bit Offset */
5595 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT50        ((uint32_t)0x00040000)          /*!< Protects Sector 50 from program or erase */
5596 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT51] Bits */
5597 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51_OFS    (19)                            /*!< PROT51 Bit Offset */
5598 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT51        ((uint32_t)0x00080000)          /*!< Protects Sector 51 from program or erase */
5599 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT52] Bits */
5600 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52_OFS    (20)                            /*!< PROT52 Bit Offset */
5601 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT52        ((uint32_t)0x00100000)          /*!< Protects Sector 52 from program or erase */
5602 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT53] Bits */
5603 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53_OFS    (21)                            /*!< PROT53 Bit Offset */
5604 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT53        ((uint32_t)0x00200000)          /*!< Protects Sector 53 from program or erase */
5605 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT54] Bits */
5606 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54_OFS    (22)                            /*!< PROT54 Bit Offset */
5607 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT54        ((uint32_t)0x00400000)          /*!< Protects Sector 54 from program or erase */
5608 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT55] Bits */
5609 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55_OFS    (23)                            /*!< PROT55 Bit Offset */
5610 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT55        ((uint32_t)0x00800000)          /*!< Protects Sector 55 from program or erase */
5611 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT56] Bits */
5612 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56_OFS    (24)                            /*!< PROT56 Bit Offset */
5613 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT56        ((uint32_t)0x01000000)          /*!< Protects Sector 56 from program or erase */
5614 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT57] Bits */
5615 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57_OFS    (25)                            /*!< PROT57 Bit Offset */
5616 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT57        ((uint32_t)0x02000000)          /*!< Protects Sector 57 from program or erase */
5617 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT58] Bits */
5618 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58_OFS    (26)                            /*!< PROT58 Bit Offset */
5619 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT58        ((uint32_t)0x04000000)          /*!< Protects Sector 58 from program or erase */
5620 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT59] Bits */
5621 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59_OFS    (27)                            /*!< PROT59 Bit Offset */
5622 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT59        ((uint32_t)0x08000000)          /*!< Protects Sector 59 from program or erase */
5623 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT60] Bits */
5624 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60_OFS    (28)                            /*!< PROT60 Bit Offset */
5625 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT60        ((uint32_t)0x10000000)          /*!< Protects Sector 60 from program or erase */
5626 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT61] Bits */
5627 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61_OFS    (29)                            /*!< PROT61 Bit Offset */
5628 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT61        ((uint32_t)0x20000000)          /*!< Protects Sector 61 from program or erase */
5629 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT62] Bits */
5630 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62_OFS    (30)                            /*!< PROT62 Bit Offset */
5631 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT62        ((uint32_t)0x40000000)          /*!< Protects Sector 62 from program or erase */
5632 /* FLCTL_A_BANK1_MAIN_WEPROT1[PROT63] Bits */
5633 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63_OFS    (31)                            /*!< PROT63 Bit Offset */
5634 #define FLCTL_A_BANK1_MAIN_WEPROT1_PROT63        ((uint32_t)0x80000000)          /*!< Protects Sector 63 from program or erase */
5635 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT64] Bits */
5636 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64_OFS    ( 0)                            /*!< PROT64 Bit Offset */
5637 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT64        ((uint32_t)0x00000001)          /*!< Protects Sector 64 from program or erase */
5638 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT65] Bits */
5639 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65_OFS    ( 1)                            /*!< PROT65 Bit Offset */
5640 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT65        ((uint32_t)0x00000002)          /*!< Protects Sector 65 from program or erase */
5641 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT66] Bits */
5642 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66_OFS    ( 2)                            /*!< PROT66 Bit Offset */
5643 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT66        ((uint32_t)0x00000004)          /*!< Protects Sector 66 from program or erase */
5644 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT67] Bits */
5645 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67_OFS    ( 3)                            /*!< PROT67 Bit Offset */
5646 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT67        ((uint32_t)0x00000008)          /*!< Protects Sector 67 from program or erase */
5647 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT68] Bits */
5648 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68_OFS    ( 4)                            /*!< PROT68 Bit Offset */
5649 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT68        ((uint32_t)0x00000010)          /*!< Protects Sector 68 from program or erase */
5650 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT69] Bits */
5651 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69_OFS    ( 5)                            /*!< PROT69 Bit Offset */
5652 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT69        ((uint32_t)0x00000020)          /*!< Protects Sector 69 from program or erase */
5653 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT70] Bits */
5654 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70_OFS    ( 6)                            /*!< PROT70 Bit Offset */
5655 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT70        ((uint32_t)0x00000040)          /*!< Protects Sector 70 from program or erase */
5656 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT71] Bits */
5657 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71_OFS    ( 7)                            /*!< PROT71 Bit Offset */
5658 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT71        ((uint32_t)0x00000080)          /*!< Protects Sector 71 from program or erase */
5659 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT72] Bits */
5660 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72_OFS    ( 8)                            /*!< PROT72 Bit Offset */
5661 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT72        ((uint32_t)0x00000100)          /*!< Protects Sector 72 from program or erase */
5662 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT73] Bits */
5663 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73_OFS    ( 9)                            /*!< PROT73 Bit Offset */
5664 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT73        ((uint32_t)0x00000200)          /*!< Protects Sector 73 from program or erase */
5665 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT74] Bits */
5666 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74_OFS    (10)                            /*!< PROT74 Bit Offset */
5667 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT74        ((uint32_t)0x00000400)          /*!< Protects Sector 74 from program or erase */
5668 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT75] Bits */
5669 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75_OFS    (11)                            /*!< PROT75 Bit Offset */
5670 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT75        ((uint32_t)0x00000800)          /*!< Protects Sector 75 from program or erase */
5671 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT76] Bits */
5672 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76_OFS    (12)                            /*!< PROT76 Bit Offset */
5673 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT76        ((uint32_t)0x00001000)          /*!< Protects Sector 76 from program or erase */
5674 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT77] Bits */
5675 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77_OFS    (13)                            /*!< PROT77 Bit Offset */
5676 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT77        ((uint32_t)0x00002000)          /*!< Protects Sector 77 from program or erase */
5677 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT78] Bits */
5678 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78_OFS    (14)                            /*!< PROT78 Bit Offset */
5679 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT78        ((uint32_t)0x00004000)          /*!< Protects Sector 78 from program or erase */
5680 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT79] Bits */
5681 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79_OFS    (15)                            /*!< PROT79 Bit Offset */
5682 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT79        ((uint32_t)0x00008000)          /*!< Protects Sector 79 from program or erase */
5683 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT80] Bits */
5684 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80_OFS    (16)                            /*!< PROT80 Bit Offset */
5685 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT80        ((uint32_t)0x00010000)          /*!< Protects Sector 80 from program or erase */
5686 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT81] Bits */
5687 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81_OFS    (17)                            /*!< PROT81 Bit Offset */
5688 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT81        ((uint32_t)0x00020000)          /*!< Protects Sector 81 from program or erase */
5689 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT82] Bits */
5690 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82_OFS    (18)                            /*!< PROT82 Bit Offset */
5691 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT82        ((uint32_t)0x00040000)          /*!< Protects Sector 82 from program or erase */
5692 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT83] Bits */
5693 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83_OFS    (19)                            /*!< PROT83 Bit Offset */
5694 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT83        ((uint32_t)0x00080000)          /*!< Protects Sector 83 from program or erase */
5695 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT84] Bits */
5696 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84_OFS    (20)                            /*!< PROT84 Bit Offset */
5697 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT84        ((uint32_t)0x00100000)          /*!< Protects Sector 84 from program or erase */
5698 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT85] Bits */
5699 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85_OFS    (21)                            /*!< PROT85 Bit Offset */
5700 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT85        ((uint32_t)0x00200000)          /*!< Protects Sector 85 from program or erase */
5701 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT86] Bits */
5702 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86_OFS    (22)                            /*!< PROT86 Bit Offset */
5703 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT86        ((uint32_t)0x00400000)          /*!< Protects Sector 86 from program or erase */
5704 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT87] Bits */
5705 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87_OFS    (23)                            /*!< PROT87 Bit Offset */
5706 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT87        ((uint32_t)0x00800000)          /*!< Protects Sector 87 from program or erase */
5707 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT88] Bits */
5708 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88_OFS    (24)                            /*!< PROT88 Bit Offset */
5709 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT88        ((uint32_t)0x01000000)          /*!< Protects Sector 88 from program or erase */
5710 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT89] Bits */
5711 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89_OFS    (25)                            /*!< PROT89 Bit Offset */
5712 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT89        ((uint32_t)0x02000000)          /*!< Protects Sector 89 from program or erase */
5713 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT90] Bits */
5714 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90_OFS    (26)                            /*!< PROT90 Bit Offset */
5715 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT90        ((uint32_t)0x04000000)          /*!< Protects Sector 90 from program or erase */
5716 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT91] Bits */
5717 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91_OFS    (27)                            /*!< PROT91 Bit Offset */
5718 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT91        ((uint32_t)0x08000000)          /*!< Protects Sector 91 from program or erase */
5719 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT92] Bits */
5720 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92_OFS    (28)                            /*!< PROT92 Bit Offset */
5721 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT92        ((uint32_t)0x10000000)          /*!< Protects Sector 92 from program or erase */
5722 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT93] Bits */
5723 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93_OFS    (29)                            /*!< PROT93 Bit Offset */
5724 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT93        ((uint32_t)0x20000000)          /*!< Protects Sector 93 from program or erase */
5725 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT94] Bits */
5726 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94_OFS    (30)                            /*!< PROT94 Bit Offset */
5727 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT94        ((uint32_t)0x40000000)          /*!< Protects Sector 94 from program or erase */
5728 /* FLCTL_A_BANK1_MAIN_WEPROT2[PROT95] Bits */
5729 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95_OFS    (31)                            /*!< PROT95 Bit Offset */
5730 #define FLCTL_A_BANK1_MAIN_WEPROT2_PROT95        ((uint32_t)0x80000000)          /*!< Protects Sector 95 from program or erase */
5731 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT96] Bits */
5732 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96_OFS    ( 0)                            /*!< PROT96 Bit Offset */
5733 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT96        ((uint32_t)0x00000001)          /*!< Protects Sector 96 from program or erase */
5734 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT97] Bits */
5735 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97_OFS    ( 1)                            /*!< PROT97 Bit Offset */
5736 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT97        ((uint32_t)0x00000002)          /*!< Protects Sector 97 from program or erase */
5737 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT98] Bits */
5738 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98_OFS    ( 2)                            /*!< PROT98 Bit Offset */
5739 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT98        ((uint32_t)0x00000004)          /*!< Protects Sector 98 from program or erase */
5740 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT99] Bits */
5741 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99_OFS    ( 3)                            /*!< PROT99 Bit Offset */
5742 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT99        ((uint32_t)0x00000008)          /*!< Protects Sector 99 from program or erase */
5743 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT100] Bits */
5744 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100_OFS   ( 4)                            /*!< PROT100 Bit Offset */
5745 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT100       ((uint32_t)0x00000010)          /*!< Protects Sector 100 from program or erase */
5746 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT101] Bits */
5747 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101_OFS   ( 5)                            /*!< PROT101 Bit Offset */
5748 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT101       ((uint32_t)0x00000020)          /*!< Protects Sector 101 from program or erase */
5749 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT102] Bits */
5750 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102_OFS   ( 6)                            /*!< PROT102 Bit Offset */
5751 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT102       ((uint32_t)0x00000040)          /*!< Protects Sector 102 from program or erase */
5752 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT103] Bits */
5753 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103_OFS   ( 7)                            /*!< PROT103 Bit Offset */
5754 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT103       ((uint32_t)0x00000080)          /*!< Protects Sector 103 from program or erase */
5755 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT104] Bits */
5756 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104_OFS   ( 8)                            /*!< PROT104 Bit Offset */
5757 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT104       ((uint32_t)0x00000100)          /*!< Protects Sector 104 from program or erase */
5758 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT105] Bits */
5759 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105_OFS   ( 9)                            /*!< PROT105 Bit Offset */
5760 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT105       ((uint32_t)0x00000200)          /*!< Protects Sector 105 from program or erase */
5761 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT106] Bits */
5762 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106_OFS   (10)                            /*!< PROT106 Bit Offset */
5763 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT106       ((uint32_t)0x00000400)          /*!< Protects Sector 106 from program or erase */
5764 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT107] Bits */
5765 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107_OFS   (11)                            /*!< PROT107 Bit Offset */
5766 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT107       ((uint32_t)0x00000800)          /*!< Protects Sector 107 from program or erase */
5767 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT108] Bits */
5768 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108_OFS   (12)                            /*!< PROT108 Bit Offset */
5769 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT108       ((uint32_t)0x00001000)          /*!< Protects Sector 108 from program or erase */
5770 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT109] Bits */
5771 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109_OFS   (13)                            /*!< PROT109 Bit Offset */
5772 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT109       ((uint32_t)0x00002000)          /*!< Protects Sector 109 from program or erase */
5773 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT110] Bits */
5774 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110_OFS   (14)                            /*!< PROT110 Bit Offset */
5775 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT110       ((uint32_t)0x00004000)          /*!< Protects Sector 110 from program or erase */
5776 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT111] Bits */
5777 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111_OFS   (15)                            /*!< PROT111 Bit Offset */
5778 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT111       ((uint32_t)0x00008000)          /*!< Protects Sector 111 from program or erase */
5779 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT112] Bits */
5780 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112_OFS   (16)                            /*!< PROT112 Bit Offset */
5781 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT112       ((uint32_t)0x00010000)          /*!< Protects Sector 112 from program or erase */
5782 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT113] Bits */
5783 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113_OFS   (17)                            /*!< PROT113 Bit Offset */
5784 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT113       ((uint32_t)0x00020000)          /*!< Protects Sector 113 from program or erase */
5785 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT114] Bits */
5786 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114_OFS   (18)                            /*!< PROT114 Bit Offset */
5787 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT114       ((uint32_t)0x00040000)          /*!< Protects Sector 114 from program or erase */
5788 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT115] Bits */
5789 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115_OFS   (19)                            /*!< PROT115 Bit Offset */
5790 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT115       ((uint32_t)0x00080000)          /*!< Protects Sector 115 from program or erase */
5791 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT116] Bits */
5792 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116_OFS   (20)                            /*!< PROT116 Bit Offset */
5793 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT116       ((uint32_t)0x00100000)          /*!< Protects Sector 116 from program or erase */
5794 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT117] Bits */
5795 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117_OFS   (21)                            /*!< PROT117 Bit Offset */
5796 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT117       ((uint32_t)0x00200000)          /*!< Protects Sector 117 from program or erase */
5797 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT118] Bits */
5798 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118_OFS   (22)                            /*!< PROT118 Bit Offset */
5799 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT118       ((uint32_t)0x00400000)          /*!< Protects Sector 118 from program or erase */
5800 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT119] Bits */
5801 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119_OFS   (23)                            /*!< PROT119 Bit Offset */
5802 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT119       ((uint32_t)0x00800000)          /*!< Protects Sector 119 from program or erase */
5803 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT120] Bits */
5804 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120_OFS   (24)                            /*!< PROT120 Bit Offset */
5805 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT120       ((uint32_t)0x01000000)          /*!< Protects Sector 120 from program or erase */
5806 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT121] Bits */
5807 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121_OFS   (25)                            /*!< PROT121 Bit Offset */
5808 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT121       ((uint32_t)0x02000000)          /*!< Protects Sector 121 from program or erase */
5809 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT122] Bits */
5810 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122_OFS   (26)                            /*!< PROT122 Bit Offset */
5811 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT122       ((uint32_t)0x04000000)          /*!< Protects Sector 122 from program or erase */
5812 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT123] Bits */
5813 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123_OFS   (27)                            /*!< PROT123 Bit Offset */
5814 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT123       ((uint32_t)0x08000000)          /*!< Protects Sector 123 from program or erase */
5815 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT124] Bits */
5816 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124_OFS   (28)                            /*!< PROT124 Bit Offset */
5817 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT124       ((uint32_t)0x10000000)          /*!< Protects Sector 124 from program or erase */
5818 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT125] Bits */
5819 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125_OFS   (29)                            /*!< PROT125 Bit Offset */
5820 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT125       ((uint32_t)0x20000000)          /*!< Protects Sector 125 from program or erase */
5821 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT126] Bits */
5822 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126_OFS   (30)                            /*!< PROT126 Bit Offset */
5823 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT126       ((uint32_t)0x40000000)          /*!< Protects Sector 126 from program or erase */
5824 /* FLCTL_A_BANK1_MAIN_WEPROT3[PROT127] Bits */
5825 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127_OFS   (31)                            /*!< PROT127 Bit Offset */
5826 #define FLCTL_A_BANK1_MAIN_WEPROT3_PROT127       ((uint32_t)0x80000000)          /*!< Protects Sector 127 from program or erase */
5827 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT128] Bits */
5828 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128_OFS   ( 0)                            /*!< PROT128 Bit Offset */
5829 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT128       ((uint32_t)0x00000001)          /*!< Protects Sector 128 from program or erase */
5830 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT129] Bits */
5831 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129_OFS   ( 1)                            /*!< PROT129 Bit Offset */
5832 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT129       ((uint32_t)0x00000002)          /*!< Protects Sector 129 from program or erase */
5833 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT130] Bits */
5834 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130_OFS   ( 2)                            /*!< PROT130 Bit Offset */
5835 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT130       ((uint32_t)0x00000004)          /*!< Protects Sector 130 from program or erase */
5836 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT131] Bits */
5837 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131_OFS   ( 3)                            /*!< PROT131 Bit Offset */
5838 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT131       ((uint32_t)0x00000008)          /*!< Protects Sector 131 from program or erase */
5839 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT132] Bits */
5840 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132_OFS   ( 4)                            /*!< PROT132 Bit Offset */
5841 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT132       ((uint32_t)0x00000010)          /*!< Protects Sector 132 from program or erase */
5842 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT133] Bits */
5843 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133_OFS   ( 5)                            /*!< PROT133 Bit Offset */
5844 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT133       ((uint32_t)0x00000020)          /*!< Protects Sector 133 from program or erase */
5845 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT134] Bits */
5846 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134_OFS   ( 6)                            /*!< PROT134 Bit Offset */
5847 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT134       ((uint32_t)0x00000040)          /*!< Protects Sector 134 from program or erase */
5848 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT135] Bits */
5849 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135_OFS   ( 7)                            /*!< PROT135 Bit Offset */
5850 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT135       ((uint32_t)0x00000080)          /*!< Protects Sector 135 from program or erase */
5851 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT136] Bits */
5852 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136_OFS   ( 8)                            /*!< PROT136 Bit Offset */
5853 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT136       ((uint32_t)0x00000100)          /*!< Protects Sector 136 from program or erase */
5854 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT137] Bits */
5855 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137_OFS   ( 9)                            /*!< PROT137 Bit Offset */
5856 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT137       ((uint32_t)0x00000200)          /*!< Protects Sector 137 from program or erase */
5857 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT138] Bits */
5858 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138_OFS   (10)                            /*!< PROT138 Bit Offset */
5859 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT138       ((uint32_t)0x00000400)          /*!< Protects Sector 138 from program or erase */
5860 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT139] Bits */
5861 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139_OFS   (11)                            /*!< PROT139 Bit Offset */
5862 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT139       ((uint32_t)0x00000800)          /*!< Protects Sector 139 from program or erase */
5863 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT140] Bits */
5864 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140_OFS   (12)                            /*!< PROT140 Bit Offset */
5865 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT140       ((uint32_t)0x00001000)          /*!< Protects Sector 140 from program or erase */
5866 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT141] Bits */
5867 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141_OFS   (13)                            /*!< PROT141 Bit Offset */
5868 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT141       ((uint32_t)0x00002000)          /*!< Protects Sector 141 from program or erase */
5869 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT142] Bits */
5870 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142_OFS   (14)                            /*!< PROT142 Bit Offset */
5871 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT142       ((uint32_t)0x00004000)          /*!< Protects Sector 142 from program or erase */
5872 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT143] Bits */
5873 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143_OFS   (15)                            /*!< PROT143 Bit Offset */
5874 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT143       ((uint32_t)0x00008000)          /*!< Protects Sector 143 from program or erase */
5875 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT144] Bits */
5876 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144_OFS   (16)                            /*!< PROT144 Bit Offset */
5877 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT144       ((uint32_t)0x00010000)          /*!< Protects Sector 144 from program or erase */
5878 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT145] Bits */
5879 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145_OFS   (17)                            /*!< PROT145 Bit Offset */
5880 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT145       ((uint32_t)0x00020000)          /*!< Protects Sector 145 from program or erase */
5881 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT146] Bits */
5882 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146_OFS   (18)                            /*!< PROT146 Bit Offset */
5883 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT146       ((uint32_t)0x00040000)          /*!< Protects Sector 146 from program or erase */
5884 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT147] Bits */
5885 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147_OFS   (19)                            /*!< PROT147 Bit Offset */
5886 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT147       ((uint32_t)0x00080000)          /*!< Protects Sector 147 from program or erase */
5887 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT148] Bits */
5888 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148_OFS   (20)                            /*!< PROT148 Bit Offset */
5889 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT148       ((uint32_t)0x00100000)          /*!< Protects Sector 148 from program or erase */
5890 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT149] Bits */
5891 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149_OFS   (21)                            /*!< PROT149 Bit Offset */
5892 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT149       ((uint32_t)0x00200000)          /*!< Protects Sector 149 from program or erase */
5893 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT150] Bits */
5894 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150_OFS   (22)                            /*!< PROT150 Bit Offset */
5895 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT150       ((uint32_t)0x00400000)          /*!< Protects Sector 150 from program or erase */
5896 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT151] Bits */
5897 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151_OFS   (23)                            /*!< PROT151 Bit Offset */
5898 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT151       ((uint32_t)0x00800000)          /*!< Protects Sector 151 from program or erase */
5899 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT152] Bits */
5900 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152_OFS   (24)                            /*!< PROT152 Bit Offset */
5901 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT152       ((uint32_t)0x01000000)          /*!< Protects Sector 152 from program or erase */
5902 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT153] Bits */
5903 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153_OFS   (25)                            /*!< PROT153 Bit Offset */
5904 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT153       ((uint32_t)0x02000000)          /*!< Protects Sector 153 from program or erase */
5905 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT154] Bits */
5906 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154_OFS   (26)                            /*!< PROT154 Bit Offset */
5907 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT154       ((uint32_t)0x04000000)          /*!< Protects Sector 154 from program or erase */
5908 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT155] Bits */
5909 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155_OFS   (27)                            /*!< PROT155 Bit Offset */
5910 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT155       ((uint32_t)0x08000000)          /*!< Protects Sector 155 from program or erase */
5911 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT156] Bits */
5912 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156_OFS   (28)                            /*!< PROT156 Bit Offset */
5913 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT156       ((uint32_t)0x10000000)          /*!< Protects Sector 156 from program or erase */
5914 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT157] Bits */
5915 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157_OFS   (29)                            /*!< PROT157 Bit Offset */
5916 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT157       ((uint32_t)0x20000000)          /*!< Protects Sector 157 from program or erase */
5917 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT158] Bits */
5918 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158_OFS   (30)                            /*!< PROT158 Bit Offset */
5919 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT158       ((uint32_t)0x40000000)          /*!< Protects Sector 158 from program or erase */
5920 /* FLCTL_A_BANK1_MAIN_WEPROT4[PROT159] Bits */
5921 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159_OFS   (31)                            /*!< PROT159 Bit Offset */
5922 #define FLCTL_A_BANK1_MAIN_WEPROT4_PROT159       ((uint32_t)0x80000000)          /*!< Protects Sector 159 from program or erase */
5923 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT160] Bits */
5924 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160_OFS   ( 0)                            /*!< PROT160 Bit Offset */
5925 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT160       ((uint32_t)0x00000001)          /*!< Protects Sector 160 from program or erase */
5926 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT161] Bits */
5927 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161_OFS   ( 1)                            /*!< PROT161 Bit Offset */
5928 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT161       ((uint32_t)0x00000002)          /*!< Protects Sector 161 from program or erase */
5929 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT162] Bits */
5930 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162_OFS   ( 2)                            /*!< PROT162 Bit Offset */
5931 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT162       ((uint32_t)0x00000004)          /*!< Protects Sector 162 from program or erase */
5932 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT163] Bits */
5933 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163_OFS   ( 3)                            /*!< PROT163 Bit Offset */
5934 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT163       ((uint32_t)0x00000008)          /*!< Protects Sector 163 from program or erase */
5935 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT164] Bits */
5936 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164_OFS   ( 4)                            /*!< PROT164 Bit Offset */
5937 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT164       ((uint32_t)0x00000010)          /*!< Protects Sector 164 from program or erase */
5938 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT165] Bits */
5939 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165_OFS   ( 5)                            /*!< PROT165 Bit Offset */
5940 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT165       ((uint32_t)0x00000020)          /*!< Protects Sector 165 from program or erase */
5941 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT166] Bits */
5942 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166_OFS   ( 6)                            /*!< PROT166 Bit Offset */
5943 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT166       ((uint32_t)0x00000040)          /*!< Protects Sector 166 from program or erase */
5944 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT167] Bits */
5945 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167_OFS   ( 7)                            /*!< PROT167 Bit Offset */
5946 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT167       ((uint32_t)0x00000080)          /*!< Protects Sector 167 from program or erase */
5947 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT168] Bits */
5948 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168_OFS   ( 8)                            /*!< PROT168 Bit Offset */
5949 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT168       ((uint32_t)0x00000100)          /*!< Protects Sector 168 from program or erase */
5950 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT169] Bits */
5951 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169_OFS   ( 9)                            /*!< PROT169 Bit Offset */
5952 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT169       ((uint32_t)0x00000200)          /*!< Protects Sector 169 from program or erase */
5953 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT170] Bits */
5954 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170_OFS   (10)                            /*!< PROT170 Bit Offset */
5955 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT170       ((uint32_t)0x00000400)          /*!< Protects Sector 170 from program or erase */
5956 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT171] Bits */
5957 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171_OFS   (11)                            /*!< PROT171 Bit Offset */
5958 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT171       ((uint32_t)0x00000800)          /*!< Protects Sector 171 from program or erase */
5959 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT172] Bits */
5960 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172_OFS   (12)                            /*!< PROT172 Bit Offset */
5961 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT172       ((uint32_t)0x00001000)          /*!< Protects Sector 172 from program or erase */
5962 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT173] Bits */
5963 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173_OFS   (13)                            /*!< PROT173 Bit Offset */
5964 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT173       ((uint32_t)0x00002000)          /*!< Protects Sector 173 from program or erase */
5965 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT174] Bits */
5966 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174_OFS   (14)                            /*!< PROT174 Bit Offset */
5967 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT174       ((uint32_t)0x00004000)          /*!< Protects Sector 174 from program or erase */
5968 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT175] Bits */
5969 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175_OFS   (15)                            /*!< PROT175 Bit Offset */
5970 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT175       ((uint32_t)0x00008000)          /*!< Protects Sector 175 from program or erase */
5971 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT176] Bits */
5972 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176_OFS   (16)                            /*!< PROT176 Bit Offset */
5973 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT176       ((uint32_t)0x00010000)          /*!< Protects Sector 176 from program or erase */
5974 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT177] Bits */
5975 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177_OFS   (17)                            /*!< PROT177 Bit Offset */
5976 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT177       ((uint32_t)0x00020000)          /*!< Protects Sector 177 from program or erase */
5977 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT178] Bits */
5978 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178_OFS   (18)                            /*!< PROT178 Bit Offset */
5979 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT178       ((uint32_t)0x00040000)          /*!< Protects Sector 178 from program or erase */
5980 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT179] Bits */
5981 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179_OFS   (19)                            /*!< PROT179 Bit Offset */
5982 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT179       ((uint32_t)0x00080000)          /*!< Protects Sector 179 from program or erase */
5983 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT180] Bits */
5984 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180_OFS   (20)                            /*!< PROT180 Bit Offset */
5985 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT180       ((uint32_t)0x00100000)          /*!< Protects Sector 180 from program or erase */
5986 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT181] Bits */
5987 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181_OFS   (21)                            /*!< PROT181 Bit Offset */
5988 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT181       ((uint32_t)0x00200000)          /*!< Protects Sector 181 from program or erase */
5989 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT182] Bits */
5990 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182_OFS   (22)                            /*!< PROT182 Bit Offset */
5991 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT182       ((uint32_t)0x00400000)          /*!< Protects Sector 182 from program or erase */
5992 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT183] Bits */
5993 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183_OFS   (23)                            /*!< PROT183 Bit Offset */
5994 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT183       ((uint32_t)0x00800000)          /*!< Protects Sector 183 from program or erase */
5995 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT184] Bits */
5996 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184_OFS   (24)                            /*!< PROT184 Bit Offset */
5997 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT184       ((uint32_t)0x01000000)          /*!< Protects Sector 184 from program or erase */
5998 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT185] Bits */
5999 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185_OFS   (25)                            /*!< PROT185 Bit Offset */
6000 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT185       ((uint32_t)0x02000000)          /*!< Protects Sector 185 from program or erase */
6001 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT186] Bits */
6002 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186_OFS   (26)                            /*!< PROT186 Bit Offset */
6003 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT186       ((uint32_t)0x04000000)          /*!< Protects Sector 186 from program or erase */
6004 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT187] Bits */
6005 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187_OFS   (27)                            /*!< PROT187 Bit Offset */
6006 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT187       ((uint32_t)0x08000000)          /*!< Protects Sector 187 from program or erase */
6007 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT188] Bits */
6008 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188_OFS   (28)                            /*!< PROT188 Bit Offset */
6009 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT188       ((uint32_t)0x10000000)          /*!< Protects Sector 188 from program or erase */
6010 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT189] Bits */
6011 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189_OFS   (29)                            /*!< PROT189 Bit Offset */
6012 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT189       ((uint32_t)0x20000000)          /*!< Protects Sector 189 from program or erase */
6013 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT190] Bits */
6014 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190_OFS   (30)                            /*!< PROT190 Bit Offset */
6015 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT190       ((uint32_t)0x40000000)          /*!< Protects Sector 190 from program or erase */
6016 /* FLCTL_A_BANK1_MAIN_WEPROT5[PROT191] Bits */
6017 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191_OFS   (31)                            /*!< PROT191 Bit Offset */
6018 #define FLCTL_A_BANK1_MAIN_WEPROT5_PROT191       ((uint32_t)0x80000000)          /*!< Protects Sector 191 from program or erase */
6019 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT192] Bits */
6020 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192_OFS   ( 0)                            /*!< PROT192 Bit Offset */
6021 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT192       ((uint32_t)0x00000001)          /*!< Protects Sector 192 from program or erase */
6022 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT193] Bits */
6023 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193_OFS   ( 1)                            /*!< PROT193 Bit Offset */
6024 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT193       ((uint32_t)0x00000002)          /*!< Protects Sector 193 from program or erase */
6025 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT194] Bits */
6026 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194_OFS   ( 2)                            /*!< PROT194 Bit Offset */
6027 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT194       ((uint32_t)0x00000004)          /*!< Protects Sector 194 from program or erase */
6028 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT195] Bits */
6029 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195_OFS   ( 3)                            /*!< PROT195 Bit Offset */
6030 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT195       ((uint32_t)0x00000008)          /*!< Protects Sector 195 from program or erase */
6031 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT196] Bits */
6032 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196_OFS   ( 4)                            /*!< PROT196 Bit Offset */
6033 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT196       ((uint32_t)0x00000010)          /*!< Protects Sector 196 from program or erase */
6034 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT197] Bits */
6035 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197_OFS   ( 5)                            /*!< PROT197 Bit Offset */
6036 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT197       ((uint32_t)0x00000020)          /*!< Protects Sector 197 from program or erase */
6037 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT198] Bits */
6038 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198_OFS   ( 6)                            /*!< PROT198 Bit Offset */
6039 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT198       ((uint32_t)0x00000040)          /*!< Protects Sector 198 from program or erase */
6040 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT199] Bits */
6041 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199_OFS   ( 7)                            /*!< PROT199 Bit Offset */
6042 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT199       ((uint32_t)0x00000080)          /*!< Protects Sector 199 from program or erase */
6043 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT200] Bits */
6044 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200_OFS   ( 8)                            /*!< PROT200 Bit Offset */
6045 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT200       ((uint32_t)0x00000100)          /*!< Protects Sector 200 from program or erase */
6046 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT201] Bits */
6047 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201_OFS   ( 9)                            /*!< PROT201 Bit Offset */
6048 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT201       ((uint32_t)0x00000200)          /*!< Protects Sector 201 from program or erase */
6049 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT202] Bits */
6050 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202_OFS   (10)                            /*!< PROT202 Bit Offset */
6051 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT202       ((uint32_t)0x00000400)          /*!< Protects Sector 202 from program or erase */
6052 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT203] Bits */
6053 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203_OFS   (11)                            /*!< PROT203 Bit Offset */
6054 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT203       ((uint32_t)0x00000800)          /*!< Protects Sector 203 from program or erase */
6055 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT204] Bits */
6056 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204_OFS   (12)                            /*!< PROT204 Bit Offset */
6057 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT204       ((uint32_t)0x00001000)          /*!< Protects Sector 204 from program or erase */
6058 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT205] Bits */
6059 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205_OFS   (13)                            /*!< PROT205 Bit Offset */
6060 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT205       ((uint32_t)0x00002000)          /*!< Protects Sector 205 from program or erase */
6061 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT206] Bits */
6062 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206_OFS   (14)                            /*!< PROT206 Bit Offset */
6063 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT206       ((uint32_t)0x00004000)          /*!< Protects Sector 206 from program or erase */
6064 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT207] Bits */
6065 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207_OFS   (15)                            /*!< PROT207 Bit Offset */
6066 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT207       ((uint32_t)0x00008000)          /*!< Protects Sector 207 from program or erase */
6067 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT208] Bits */
6068 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208_OFS   (16)                            /*!< PROT208 Bit Offset */
6069 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT208       ((uint32_t)0x00010000)          /*!< Protects Sector 208 from program or erase */
6070 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT209] Bits */
6071 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209_OFS   (17)                            /*!< PROT209 Bit Offset */
6072 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT209       ((uint32_t)0x00020000)          /*!< Protects Sector 209 from program or erase */
6073 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT210] Bits */
6074 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210_OFS   (18)                            /*!< PROT210 Bit Offset */
6075 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT210       ((uint32_t)0x00040000)          /*!< Protects Sector 210 from program or erase */
6076 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT211] Bits */
6077 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211_OFS   (19)                            /*!< PROT211 Bit Offset */
6078 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT211       ((uint32_t)0x00080000)          /*!< Protects Sector 211 from program or erase */
6079 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT212] Bits */
6080 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212_OFS   (20)                            /*!< PROT212 Bit Offset */
6081 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT212       ((uint32_t)0x00100000)          /*!< Protects Sector 212 from program or erase */
6082 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT213] Bits */
6083 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213_OFS   (21)                            /*!< PROT213 Bit Offset */
6084 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT213       ((uint32_t)0x00200000)          /*!< Protects Sector 213 from program or erase */
6085 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT214] Bits */
6086 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214_OFS   (22)                            /*!< PROT214 Bit Offset */
6087 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT214       ((uint32_t)0x00400000)          /*!< Protects Sector 214 from program or erase */
6088 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT215] Bits */
6089 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215_OFS   (23)                            /*!< PROT215 Bit Offset */
6090 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT215       ((uint32_t)0x00800000)          /*!< Protects Sector 215 from program or erase */
6091 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT216] Bits */
6092 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216_OFS   (24)                            /*!< PROT216 Bit Offset */
6093 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT216       ((uint32_t)0x01000000)          /*!< Protects Sector 216 from program or erase */
6094 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT217] Bits */
6095 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217_OFS   (25)                            /*!< PROT217 Bit Offset */
6096 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT217       ((uint32_t)0x02000000)          /*!< Protects Sector 217 from program or erase */
6097 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT218] Bits */
6098 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218_OFS   (26)                            /*!< PROT218 Bit Offset */
6099 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT218       ((uint32_t)0x04000000)          /*!< Protects Sector 218 from program or erase */
6100 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT219] Bits */
6101 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219_OFS   (27)                            /*!< PROT219 Bit Offset */
6102 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT219       ((uint32_t)0x08000000)          /*!< Protects Sector 219 from program or erase */
6103 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT220] Bits */
6104 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220_OFS   (28)                            /*!< PROT220 Bit Offset */
6105 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT220       ((uint32_t)0x10000000)          /*!< Protects Sector 220 from program or erase */
6106 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT221] Bits */
6107 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221_OFS   (29)                            /*!< PROT221 Bit Offset */
6108 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT221       ((uint32_t)0x20000000)          /*!< Protects Sector 221 from program or erase */
6109 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT222] Bits */
6110 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222_OFS   (30)                            /*!< PROT222 Bit Offset */
6111 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT222       ((uint32_t)0x40000000)          /*!< Protects Sector 222 from program or erase */
6112 /* FLCTL_A_BANK1_MAIN_WEPROT6[PROT223] Bits */
6113 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223_OFS   (31)                            /*!< PROT223 Bit Offset */
6114 #define FLCTL_A_BANK1_MAIN_WEPROT6_PROT223       ((uint32_t)0x80000000)          /*!< Protects Sector 223 from program or erase */
6115 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT224] Bits */
6116 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224_OFS   ( 0)                            /*!< PROT224 Bit Offset */
6117 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT224       ((uint32_t)0x00000001)          /*!< Protects Sector 224 from program or erase */
6118 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT225] Bits */
6119 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225_OFS   ( 1)                            /*!< PROT225 Bit Offset */
6120 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT225       ((uint32_t)0x00000002)          /*!< Protects Sector 225 from program or erase */
6121 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT226] Bits */
6122 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226_OFS   ( 2)                            /*!< PROT226 Bit Offset */
6123 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT226       ((uint32_t)0x00000004)          /*!< Protects Sector 226 from program or erase */
6124 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT227] Bits */
6125 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227_OFS   ( 3)                            /*!< PROT227 Bit Offset */
6126 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT227       ((uint32_t)0x00000008)          /*!< Protects Sector 227 from program or erase */
6127 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT228] Bits */
6128 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228_OFS   ( 4)                            /*!< PROT228 Bit Offset */
6129 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT228       ((uint32_t)0x00000010)          /*!< Protects Sector 228 from program or erase */
6130 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT229] Bits */
6131 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229_OFS   ( 5)                            /*!< PROT229 Bit Offset */
6132 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT229       ((uint32_t)0x00000020)          /*!< Protects Sector 229 from program or erase */
6133 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT230] Bits */
6134 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230_OFS   ( 6)                            /*!< PROT230 Bit Offset */
6135 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT230       ((uint32_t)0x00000040)          /*!< Protects Sector 230 from program or erase */
6136 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT231] Bits */
6137 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231_OFS   ( 7)                            /*!< PROT231 Bit Offset */
6138 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT231       ((uint32_t)0x00000080)          /*!< Protects Sector 231 from program or erase */
6139 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT232] Bits */
6140 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232_OFS   ( 8)                            /*!< PROT232 Bit Offset */
6141 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT232       ((uint32_t)0x00000100)          /*!< Protects Sector 232 from program or erase */
6142 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT233] Bits */
6143 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233_OFS   ( 9)                            /*!< PROT233 Bit Offset */
6144 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT233       ((uint32_t)0x00000200)          /*!< Protects Sector 233 from program or erase */
6145 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT234] Bits */
6146 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234_OFS   (10)                            /*!< PROT234 Bit Offset */
6147 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT234       ((uint32_t)0x00000400)          /*!< Protects Sector 234 from program or erase */
6148 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT235] Bits */
6149 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235_OFS   (11)                            /*!< PROT235 Bit Offset */
6150 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT235       ((uint32_t)0x00000800)          /*!< Protects Sector 235 from program or erase */
6151 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT236] Bits */
6152 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236_OFS   (12)                            /*!< PROT236 Bit Offset */
6153 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT236       ((uint32_t)0x00001000)          /*!< Protects Sector 236 from program or erase */
6154 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT237] Bits */
6155 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237_OFS   (13)                            /*!< PROT237 Bit Offset */
6156 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT237       ((uint32_t)0x00002000)          /*!< Protects Sector 237 from program or erase */
6157 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT238] Bits */
6158 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238_OFS   (14)                            /*!< PROT238 Bit Offset */
6159 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT238       ((uint32_t)0x00004000)          /*!< Protects Sector 238 from program or erase */
6160 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT239] Bits */
6161 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239_OFS   (15)                            /*!< PROT239 Bit Offset */
6162 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT239       ((uint32_t)0x00008000)          /*!< Protects Sector 239 from program or erase */
6163 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT240] Bits */
6164 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240_OFS   (16)                            /*!< PROT240 Bit Offset */
6165 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT240       ((uint32_t)0x00010000)          /*!< Protects Sector 240 from program or erase */
6166 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT241] Bits */
6167 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241_OFS   (17)                            /*!< PROT241 Bit Offset */
6168 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT241       ((uint32_t)0x00020000)          /*!< Protects Sector 241 from program or erase */
6169 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT242] Bits */
6170 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242_OFS   (18)                            /*!< PROT242 Bit Offset */
6171 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT242       ((uint32_t)0x00040000)          /*!< Protects Sector 242 from program or erase */
6172 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT243] Bits */
6173 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243_OFS   (19)                            /*!< PROT243 Bit Offset */
6174 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT243       ((uint32_t)0x00080000)          /*!< Protects Sector 243 from program or erase */
6175 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT244] Bits */
6176 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244_OFS   (20)                            /*!< PROT244 Bit Offset */
6177 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT244       ((uint32_t)0x00100000)          /*!< Protects Sector 244 from program or erase */
6178 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT245] Bits */
6179 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245_OFS   (21)                            /*!< PROT245 Bit Offset */
6180 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT245       ((uint32_t)0x00200000)          /*!< Protects Sector 245 from program or erase */
6181 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT246] Bits */
6182 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246_OFS   (22)                            /*!< PROT246 Bit Offset */
6183 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT246       ((uint32_t)0x00400000)          /*!< Protects Sector 246 from program or erase */
6184 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT247] Bits */
6185 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247_OFS   (23)                            /*!< PROT247 Bit Offset */
6186 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT247       ((uint32_t)0x00800000)          /*!< Protects Sector 247 from program or erase */
6187 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT248] Bits */
6188 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248_OFS   (24)                            /*!< PROT248 Bit Offset */
6189 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT248       ((uint32_t)0x01000000)          /*!< Protects Sector 248 from program or erase */
6190 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT249] Bits */
6191 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249_OFS   (25)                            /*!< PROT249 Bit Offset */
6192 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT249       ((uint32_t)0x02000000)          /*!< Protects Sector 249 from program or erase */
6193 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT250] Bits */
6194 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250_OFS   (26)                            /*!< PROT250 Bit Offset */
6195 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT250       ((uint32_t)0x04000000)          /*!< Protects Sector 250 from program or erase */
6196 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT251] Bits */
6197 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251_OFS   (27)                            /*!< PROT251 Bit Offset */
6198 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT251       ((uint32_t)0x08000000)          /*!< Protects Sector 251 from program or erase */
6199 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT252] Bits */
6200 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252_OFS   (28)                            /*!< PROT252 Bit Offset */
6201 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT252       ((uint32_t)0x10000000)          /*!< Protects Sector 252 from program or erase */
6202 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT253] Bits */
6203 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253_OFS   (29)                            /*!< PROT253 Bit Offset */
6204 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT253       ((uint32_t)0x20000000)          /*!< Protects Sector 253 from program or erase */
6205 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT254] Bits */
6206 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254_OFS   (30)                            /*!< PROT254 Bit Offset */
6207 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT254       ((uint32_t)0x40000000)          /*!< Protects Sector 254 from program or erase */
6208 /* FLCTL_A_BANK1_MAIN_WEPROT7[PROT255] Bits */
6209 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255_OFS   (31)                            /*!< PROT255 Bit Offset */
6210 #define FLCTL_A_BANK1_MAIN_WEPROT7_PROT255       ((uint32_t)0x80000000)          /*!< Protects Sector 255 from program or erase */
6211 
6212 /******************************************************************************
6213 * FL_BOOTOVER_MAILBOX Bits
6214 ******************************************************************************/
6215 
6216 /******************************************************************************
6217 * FPB Bits
6218 ******************************************************************************/
6219 
6220 
6221 /******************************************************************************
6222 * FPU Bits
6223 ******************************************************************************/
6224 
6225 
6226 /******************************************************************************
6227 * ITM Bits
6228 ******************************************************************************/
6229 
6230 
6231 /******************************************************************************
6232 * MPU Bits
6233 ******************************************************************************/
6234 
6235 /* Pre-defined bitfield values */
6236 
6237 /*  MPU_RASR_SIZE Bitfield Bits */
6238 #define MPU_RASR_SIZE__32B                       ((uint32_t)0x00000008)          /*!< 32B */
6239 #define MPU_RASR_SIZE__64B                       ((uint32_t)0x0000000A)          /*!< 64B */
6240 #define MPU_RASR_SIZE__128B                      ((uint32_t)0x0000000C)          /*!< 128B */
6241 #define MPU_RASR_SIZE__256B                      ((uint32_t)0x0000000E)          /*!< 256B */
6242 #define MPU_RASR_SIZE__512B                      ((uint32_t)0x00000010)          /*!< 512B */
6243 #define MPU_RASR_SIZE__1K                        ((uint32_t)0x00000012)          /*!< 1KB */
6244 #define MPU_RASR_SIZE__2K                        ((uint32_t)0x00000014)          /*!< 2KB */
6245 #define MPU_RASR_SIZE__4K                        ((uint32_t)0x00000016)          /*!< 4KB */
6246 #define MPU_RASR_SIZE__8K                        ((uint32_t)0x00000018)          /*!< 8KB */
6247 #define MPU_RASR_SIZE__16K                       ((uint32_t)0x0000001A)          /*!< 16KB */
6248 #define MPU_RASR_SIZE__32K                       ((uint32_t)0x0000001C)          /*!< 32KB */
6249 #define MPU_RASR_SIZE__64K                       ((uint32_t)0x0000001E)          /*!< 64KB */
6250 #define MPU_RASR_SIZE__128K                      ((uint32_t)0x00000020)          /*!< 128KB */
6251 #define MPU_RASR_SIZE__256K                      ((uint32_t)0x00000022)          /*!< 256KB */
6252 #define MPU_RASR_SIZE__512K                      ((uint32_t)0x00000024)          /*!< 512KB */
6253 #define MPU_RASR_SIZE__1M                        ((uint32_t)0x00000026)          /*!< 1MB */
6254 #define MPU_RASR_SIZE__2M                        ((uint32_t)0x00000028)          /*!< 2MB */
6255 #define MPU_RASR_SIZE__4M                        ((uint32_t)0x0000002A)          /*!< 4MB */
6256 #define MPU_RASR_SIZE__8M                        ((uint32_t)0x0000002C)          /*!< 8MB */
6257 #define MPU_RASR_SIZE__16M                       ((uint32_t)0x0000002E)          /*!< 16MB */
6258 #define MPU_RASR_SIZE__32M                       ((uint32_t)0x00000030)          /*!< 32MB */
6259 #define MPU_RASR_SIZE__64M                       ((uint32_t)0x00000032)          /*!< 64MB */
6260 #define MPU_RASR_SIZE__128M                      ((uint32_t)0x00000034)          /*!< 128MB */
6261 #define MPU_RASR_SIZE__256M                      ((uint32_t)0x00000036)          /*!< 256MB */
6262 #define MPU_RASR_SIZE__512M                      ((uint32_t)0x00000038)          /*!< 512MB */
6263 #define MPU_RASR_SIZE__1G                        ((uint32_t)0x0000003A)          /*!< 1GB */
6264 #define MPU_RASR_SIZE__2G                        ((uint32_t)0x0000003C)          /*!< 2GB */
6265 #define MPU_RASR_SIZE__4G                        ((uint32_t)0x0000003E)          /*!< 4GB */
6266 
6267 /*  MPU_RASR_AP Bitfield Bits */
6268 #define MPU_RASR_AP_PRV_NO_USR_NO                ((uint32_t)0x00000000)          /*!< Privileged permissions: No access. User permissions: No access. */
6269 #define MPU_RASR_AP_PRV_RW_USR_NO                ((uint32_t)0x01000000)          /*!< Privileged permissions: Read-write. User permissions: No access. */
6270 #define MPU_RASR_AP_PRV_RW_USR_RO                ((uint32_t)0x02000000)          /*!< Privileged permissions: Read-write. User permissions: Read-only. */
6271 #define MPU_RASR_AP_PRV_RW_USR_RW                ((uint32_t)0x03000000)          /*!< Privileged permissions: Read-write. User permissions: Read-write. */
6272 #define MPU_RASR_AP_PRV_RO_USR_NO                ((uint32_t)0x05000000)          /*!< Privileged permissions: Read-only. User permissions: No access. */
6273 #define MPU_RASR_AP_PRV_RO_USR_RO                ((uint32_t)0x06000000)          /*!< Privileged permissions: Read-only. User permissions: Read-only. */
6274 
6275 /* MPU_RASR_XN Bitfield Bits */
6276 #define MPU_RASR_AP_EXEC                         ((uint32_t)0x00000000)          /*!< Instruction access enabled */
6277 #define MPU_RASR_AP_NOEXEC                       ((uint32_t)0x10000000)          /*!< Instruction access disabled */
6278 
6279 
6280 /******************************************************************************
6281 * NVIC Bits
6282 ******************************************************************************/
6283 
6284 /* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */
6285 #define NVIC_IPR0_PRI_0_OFS                      ( 0)                            /*!< PRI_0 Offset */
6286 #define NVIC_IPR0_PRI_0_M                        ((uint32_t)0x000000ff)          /*  */
6287 /* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */
6288 #define NVIC_IPR0_PRI_1_OFS                      ( 8)                            /*!< PRI_1 Offset */
6289 #define NVIC_IPR0_PRI_1_M                        ((uint32_t)0x0000ff00)          /*  */
6290 /* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */
6291 #define NVIC_IPR0_PRI_2_OFS                      (16)                            /*!< PRI_2 Offset */
6292 #define NVIC_IPR0_PRI_2_M                        ((uint32_t)0x00ff0000)          /*  */
6293 /* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */
6294 #define NVIC_IPR0_PRI_3_OFS                      (24)                            /*!< PRI_3 Offset */
6295 #define NVIC_IPR0_PRI_3_M                        ((uint32_t)0xff000000)          /*  */
6296 /* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */
6297 #define NVIC_IPR1_PRI_4_OFS                      ( 0)                            /*!< PRI_4 Offset */
6298 #define NVIC_IPR1_PRI_4_M                        ((uint32_t)0x000000ff)          /*  */
6299 /* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */
6300 #define NVIC_IPR1_PRI_5_OFS                      ( 8)                            /*!< PRI_5 Offset */
6301 #define NVIC_IPR1_PRI_5_M                        ((uint32_t)0x0000ff00)          /*  */
6302 /* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */
6303 #define NVIC_IPR1_PRI_6_OFS                      (16)                            /*!< PRI_6 Offset */
6304 #define NVIC_IPR1_PRI_6_M                        ((uint32_t)0x00ff0000)          /*  */
6305 /* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */
6306 #define NVIC_IPR1_PRI_7_OFS                      (24)                            /*!< PRI_7 Offset */
6307 #define NVIC_IPR1_PRI_7_M                        ((uint32_t)0xff000000)          /*  */
6308 /* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */
6309 #define NVIC_IPR2_PRI_8_OFS                      ( 0)                            /*!< PRI_8 Offset */
6310 #define NVIC_IPR2_PRI_8_M                        ((uint32_t)0x000000ff)          /*  */
6311 /* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */
6312 #define NVIC_IPR2_PRI_9_OFS                      ( 8)                            /*!< PRI_9 Offset */
6313 #define NVIC_IPR2_PRI_9_M                        ((uint32_t)0x0000ff00)          /*  */
6314 /* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */
6315 #define NVIC_IPR2_PRI_10_OFS                     (16)                            /*!< PRI_10 Offset */
6316 #define NVIC_IPR2_PRI_10_M                       ((uint32_t)0x00ff0000)          /*  */
6317 /* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */
6318 #define NVIC_IPR2_PRI_11_OFS                     (24)                            /*!< PRI_11 Offset */
6319 #define NVIC_IPR2_PRI_11_M                       ((uint32_t)0xff000000)          /*  */
6320 /* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */
6321 #define NVIC_IPR3_PRI_12_OFS                     ( 0)                            /*!< PRI_12 Offset */
6322 #define NVIC_IPR3_PRI_12_M                       ((uint32_t)0x000000ff)          /*  */
6323 /* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */
6324 #define NVIC_IPR3_PRI_13_OFS                     ( 8)                            /*!< PRI_13 Offset */
6325 #define NVIC_IPR3_PRI_13_M                       ((uint32_t)0x0000ff00)          /*  */
6326 /* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */
6327 #define NVIC_IPR3_PRI_14_OFS                     (16)                            /*!< PRI_14 Offset */
6328 #define NVIC_IPR3_PRI_14_M                       ((uint32_t)0x00ff0000)          /*  */
6329 /* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */
6330 #define NVIC_IPR3_PRI_15_OFS                     (24)                            /*!< PRI_15 Offset */
6331 #define NVIC_IPR3_PRI_15_M                       ((uint32_t)0xff000000)          /*  */
6332 /* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */
6333 #define NVIC_IPR4_PRI_16_OFS                     ( 0)                            /*!< PRI_16 Offset */
6334 #define NVIC_IPR4_PRI_16_M                       ((uint32_t)0x000000ff)          /*  */
6335 /* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */
6336 #define NVIC_IPR4_PRI_17_OFS                     ( 8)                            /*!< PRI_17 Offset */
6337 #define NVIC_IPR4_PRI_17_M                       ((uint32_t)0x0000ff00)          /*  */
6338 /* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */
6339 #define NVIC_IPR4_PRI_18_OFS                     (16)                            /*!< PRI_18 Offset */
6340 #define NVIC_IPR4_PRI_18_M                       ((uint32_t)0x00ff0000)          /*  */
6341 /* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */
6342 #define NVIC_IPR4_PRI_19_OFS                     (24)                            /*!< PRI_19 Offset */
6343 #define NVIC_IPR4_PRI_19_M                       ((uint32_t)0xff000000)          /*  */
6344 /* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */
6345 #define NVIC_IPR5_PRI_20_OFS                     ( 0)                            /*!< PRI_20 Offset */
6346 #define NVIC_IPR5_PRI_20_M                       ((uint32_t)0x000000ff)          /*  */
6347 /* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */
6348 #define NVIC_IPR5_PRI_21_OFS                     ( 8)                            /*!< PRI_21 Offset */
6349 #define NVIC_IPR5_PRI_21_M                       ((uint32_t)0x0000ff00)          /*  */
6350 /* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */
6351 #define NVIC_IPR5_PRI_22_OFS                     (16)                            /*!< PRI_22 Offset */
6352 #define NVIC_IPR5_PRI_22_M                       ((uint32_t)0x00ff0000)          /*  */
6353 /* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */
6354 #define NVIC_IPR5_PRI_23_OFS                     (24)                            /*!< PRI_23 Offset */
6355 #define NVIC_IPR5_PRI_23_M                       ((uint32_t)0xff000000)          /*  */
6356 /* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */
6357 #define NVIC_IPR6_PRI_24_OFS                     ( 0)                            /*!< PRI_24 Offset */
6358 #define NVIC_IPR6_PRI_24_M                       ((uint32_t)0x000000ff)          /*  */
6359 /* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */
6360 #define NVIC_IPR6_PRI_25_OFS                     ( 8)                            /*!< PRI_25 Offset */
6361 #define NVIC_IPR6_PRI_25_M                       ((uint32_t)0x0000ff00)          /*  */
6362 /* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */
6363 #define NVIC_IPR6_PRI_26_OFS                     (16)                            /*!< PRI_26 Offset */
6364 #define NVIC_IPR6_PRI_26_M                       ((uint32_t)0x00ff0000)          /*  */
6365 /* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */
6366 #define NVIC_IPR6_PRI_27_OFS                     (24)                            /*!< PRI_27 Offset */
6367 #define NVIC_IPR6_PRI_27_M                       ((uint32_t)0xff000000)          /*  */
6368 /* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */
6369 #define NVIC_IPR7_PRI_28_OFS                     ( 0)                            /*!< PRI_28 Offset */
6370 #define NVIC_IPR7_PRI_28_M                       ((uint32_t)0x000000ff)          /*  */
6371 /* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */
6372 #define NVIC_IPR7_PRI_29_OFS                     ( 8)                            /*!< PRI_29 Offset */
6373 #define NVIC_IPR7_PRI_29_M                       ((uint32_t)0x0000ff00)          /*  */
6374 /* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */
6375 #define NVIC_IPR7_PRI_30_OFS                     (16)                            /*!< PRI_30 Offset */
6376 #define NVIC_IPR7_PRI_30_M                       ((uint32_t)0x00ff0000)          /*  */
6377 /* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */
6378 #define NVIC_IPR7_PRI_31_OFS                     (24)                            /*!< PRI_31 Offset */
6379 #define NVIC_IPR7_PRI_31_M                       ((uint32_t)0xff000000)          /*  */
6380 /* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */
6381 #define NVIC_IPR8_PRI_32_OFS                     ( 0)                            /*!< PRI_32 Offset */
6382 #define NVIC_IPR8_PRI_32_M                       ((uint32_t)0x000000ff)          /*  */
6383 /* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */
6384 #define NVIC_IPR8_PRI_33_OFS                     ( 8)                            /*!< PRI_33 Offset */
6385 #define NVIC_IPR8_PRI_33_M                       ((uint32_t)0x0000ff00)          /*  */
6386 /* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */
6387 #define NVIC_IPR8_PRI_34_OFS                     (16)                            /*!< PRI_34 Offset */
6388 #define NVIC_IPR8_PRI_34_M                       ((uint32_t)0x00ff0000)          /*  */
6389 /* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */
6390 #define NVIC_IPR8_PRI_35_OFS                     (24)                            /*!< PRI_35 Offset */
6391 #define NVIC_IPR8_PRI_35_M                       ((uint32_t)0xff000000)          /*  */
6392 /* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */
6393 #define NVIC_IPR9_PRI_36_OFS                     ( 0)                            /*!< PRI_36 Offset */
6394 #define NVIC_IPR9_PRI_36_M                       ((uint32_t)0x000000ff)          /*  */
6395 /* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */
6396 #define NVIC_IPR9_PRI_37_OFS                     ( 8)                            /*!< PRI_37 Offset */
6397 #define NVIC_IPR9_PRI_37_M                       ((uint32_t)0x0000ff00)          /*  */
6398 /* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */
6399 #define NVIC_IPR9_PRI_38_OFS                     (16)                            /*!< PRI_38 Offset */
6400 #define NVIC_IPR9_PRI_38_M                       ((uint32_t)0x00ff0000)          /*  */
6401 /* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */
6402 #define NVIC_IPR9_PRI_39_OFS                     (24)                            /*!< PRI_39 Offset */
6403 #define NVIC_IPR9_PRI_39_M                       ((uint32_t)0xff000000)          /*  */
6404 /* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */
6405 #define NVIC_IPR10_PRI_40_OFS                    ( 0)                            /*!< PRI_40 Offset */
6406 #define NVIC_IPR10_PRI_40_M                      ((uint32_t)0x000000ff)          /*  */
6407 /* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */
6408 #define NVIC_IPR10_PRI_41_OFS                    ( 8)                            /*!< PRI_41 Offset */
6409 #define NVIC_IPR10_PRI_41_M                      ((uint32_t)0x0000ff00)          /*  */
6410 /* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */
6411 #define NVIC_IPR10_PRI_42_OFS                    (16)                            /*!< PRI_42 Offset */
6412 #define NVIC_IPR10_PRI_42_M                      ((uint32_t)0x00ff0000)          /*  */
6413 /* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */
6414 #define NVIC_IPR10_PRI_43_OFS                    (24)                            /*!< PRI_43 Offset */
6415 #define NVIC_IPR10_PRI_43_M                      ((uint32_t)0xff000000)          /*  */
6416 /* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */
6417 #define NVIC_IPR11_PRI_44_OFS                    ( 0)                            /*!< PRI_44 Offset */
6418 #define NVIC_IPR11_PRI_44_M                      ((uint32_t)0x000000ff)          /*  */
6419 /* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */
6420 #define NVIC_IPR11_PRI_45_OFS                    ( 8)                            /*!< PRI_45 Offset */
6421 #define NVIC_IPR11_PRI_45_M                      ((uint32_t)0x0000ff00)          /*  */
6422 /* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */
6423 #define NVIC_IPR11_PRI_46_OFS                    (16)                            /*!< PRI_46 Offset */
6424 #define NVIC_IPR11_PRI_46_M                      ((uint32_t)0x00ff0000)          /*  */
6425 /* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */
6426 #define NVIC_IPR11_PRI_47_OFS                    (24)                            /*!< PRI_47 Offset */
6427 #define NVIC_IPR11_PRI_47_M                      ((uint32_t)0xff000000)          /*  */
6428 /* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */
6429 #define NVIC_IPR12_PRI_48_OFS                    ( 0)                            /*!< PRI_48 Offset */
6430 #define NVIC_IPR12_PRI_48_M                      ((uint32_t)0x000000ff)          /*  */
6431 /* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */
6432 #define NVIC_IPR12_PRI_49_OFS                    ( 8)                            /*!< PRI_49 Offset */
6433 #define NVIC_IPR12_PRI_49_M                      ((uint32_t)0x0000ff00)          /*  */
6434 /* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */
6435 #define NVIC_IPR12_PRI_50_OFS                    (16)                            /*!< PRI_50 Offset */
6436 #define NVIC_IPR12_PRI_50_M                      ((uint32_t)0x00ff0000)          /*  */
6437 /* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */
6438 #define NVIC_IPR12_PRI_51_OFS                    (24)                            /*!< PRI_51 Offset */
6439 #define NVIC_IPR12_PRI_51_M                      ((uint32_t)0xff000000)          /*  */
6440 /* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */
6441 #define NVIC_IPR13_PRI_52_OFS                    ( 0)                            /*!< PRI_52 Offset */
6442 #define NVIC_IPR13_PRI_52_M                      ((uint32_t)0x000000ff)          /*  */
6443 /* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */
6444 #define NVIC_IPR13_PRI_53_OFS                    ( 8)                            /*!< PRI_53 Offset */
6445 #define NVIC_IPR13_PRI_53_M                      ((uint32_t)0x0000ff00)          /*  */
6446 /* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */
6447 #define NVIC_IPR13_PRI_54_OFS                    (16)                            /*!< PRI_54 Offset */
6448 #define NVIC_IPR13_PRI_54_M                      ((uint32_t)0x00ff0000)          /*  */
6449 /* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */
6450 #define NVIC_IPR13_PRI_55_OFS                    (24)                            /*!< PRI_55 Offset */
6451 #define NVIC_IPR13_PRI_55_M                      ((uint32_t)0xff000000)          /*  */
6452 /* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */
6453 #define NVIC_IPR14_PRI_56_OFS                    ( 0)                            /*!< PRI_56 Offset */
6454 #define NVIC_IPR14_PRI_56_M                      ((uint32_t)0x000000ff)          /*  */
6455 /* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */
6456 #define NVIC_IPR14_PRI_57_OFS                    ( 8)                            /*!< PRI_57 Offset */
6457 #define NVIC_IPR14_PRI_57_M                      ((uint32_t)0x0000ff00)          /*  */
6458 /* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */
6459 #define NVIC_IPR14_PRI_58_OFS                    (16)                            /*!< PRI_58 Offset */
6460 #define NVIC_IPR14_PRI_58_M                      ((uint32_t)0x00ff0000)          /*  */
6461 /* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */
6462 #define NVIC_IPR14_PRI_59_OFS                    (24)                            /*!< PRI_59 Offset */
6463 #define NVIC_IPR14_PRI_59_M                      ((uint32_t)0xff000000)          /*  */
6464 /* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */
6465 #define NVIC_IPR15_PRI_60_OFS                    ( 0)                            /*!< PRI_60 Offset */
6466 #define NVIC_IPR15_PRI_60_M                      ((uint32_t)0x000000ff)          /*  */
6467 /* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */
6468 #define NVIC_IPR15_PRI_61_OFS                    ( 8)                            /*!< PRI_61 Offset */
6469 #define NVIC_IPR15_PRI_61_M                      ((uint32_t)0x0000ff00)          /*  */
6470 /* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */
6471 #define NVIC_IPR15_PRI_62_OFS                    (16)                            /*!< PRI_62 Offset */
6472 #define NVIC_IPR15_PRI_62_M                      ((uint32_t)0x00ff0000)          /*  */
6473 /* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */
6474 #define NVIC_IPR15_PRI_63_OFS                    (24)                            /*!< PRI_63 Offset */
6475 #define NVIC_IPR15_PRI_63_M                      ((uint32_t)0xff000000)          /*  */
6476 
6477 
6478 /******************************************************************************
6479 * PCM Bits
6480 ******************************************************************************/
6481 /* PCM_CTL0[AMR] Bits */
6482 #define PCM_CTL0_AMR_OFS                         ( 0)                            /*!< AMR Bit Offset */
6483 #define PCM_CTL0_AMR_MASK                        ((uint32_t)0x0000000F)          /*!< AMR Bit Mask */
6484 #define PCM_CTL0_AMR0                            ((uint32_t)0x00000001)          /*!< AMR Bit 0 */
6485 #define PCM_CTL0_AMR1                            ((uint32_t)0x00000002)          /*!< AMR Bit 1 */
6486 #define PCM_CTL0_AMR2                            ((uint32_t)0x00000004)          /*!< AMR Bit 2 */
6487 #define PCM_CTL0_AMR3                            ((uint32_t)0x00000008)          /*!< AMR Bit 3 */
6488 #define PCM_CTL0_AMR_0                           ((uint32_t)0x00000000)          /*!< LDO based Active Mode at Core voltage setting 0. */
6489 #define PCM_CTL0_AMR_1                           ((uint32_t)0x00000001)          /*!< LDO based Active Mode at Core voltage setting 1. */
6490 #define PCM_CTL0_AMR_4                           ((uint32_t)0x00000004)          /*!< DC-DC based Active Mode at Core voltage setting 0. */
6491 #define PCM_CTL0_AMR_5                           ((uint32_t)0x00000005)          /*!< DC-DC based Active Mode at Core voltage setting 1. */
6492 #define PCM_CTL0_AMR_8                           ((uint32_t)0x00000008)          /*!< Low-Frequency Active Mode at Core voltage setting 0. */
6493 #define PCM_CTL0_AMR_9                           ((uint32_t)0x00000009)          /*!< Low-Frequency Active Mode at Core voltage setting 1. */
6494 #define PCM_CTL0_AMR__AM_LDO_VCORE0              ((uint32_t)0x00000000)          /*!< LDO based Active Mode at Core voltage setting 0. */
6495 #define PCM_CTL0_AMR__AM_LDO_VCORE1              ((uint32_t)0x00000001)          /*!< LDO based Active Mode at Core voltage setting 1. */
6496 #define PCM_CTL0_AMR__AM_DCDC_VCORE0             ((uint32_t)0x00000004)          /*!< DC-DC based Active Mode at Core voltage setting 0. */
6497 #define PCM_CTL0_AMR__AM_DCDC_VCORE1             ((uint32_t)0x00000005)          /*!< DC-DC based Active Mode at Core voltage setting 1. */
6498 #define PCM_CTL0_AMR__AM_LF_VCORE0               ((uint32_t)0x00000008)          /*!< Low-Frequency Active Mode at Core voltage setting 0. */
6499 #define PCM_CTL0_AMR__AM_LF_VCORE1               ((uint32_t)0x00000009)          /*!< Low-Frequency Active Mode at Core voltage setting 1. */
6500 /* PCM_CTL0[LPMR] Bits */
6501 #define PCM_CTL0_LPMR_OFS                        ( 4)                            /*!< LPMR Bit Offset */
6502 #define PCM_CTL0_LPMR_MASK                       ((uint32_t)0x000000F0)          /*!< LPMR Bit Mask */
6503 #define PCM_CTL0_LPMR0                           ((uint32_t)0x00000010)          /*!< LPMR Bit 0 */
6504 #define PCM_CTL0_LPMR1                           ((uint32_t)0x00000020)          /*!< LPMR Bit 1 */
6505 #define PCM_CTL0_LPMR2                           ((uint32_t)0x00000040)          /*!< LPMR Bit 2 */
6506 #define PCM_CTL0_LPMR3                           ((uint32_t)0x00000080)          /*!< LPMR Bit 3 */
6507 #define PCM_CTL0_LPMR_0                          ((uint32_t)0x00000000)          /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is  */
6508                                                                                  /* entered. */
6509 #define PCM_CTL0_LPMR_10                         ((uint32_t)0x000000A0)          /*!< LPM3.5. Core voltage setting 0. */
6510 #define PCM_CTL0_LPMR_12                         ((uint32_t)0x000000C0)          /*!< LPM4.5 */
6511 #define PCM_CTL0_LPMR__LPM3                      ((uint32_t)0x00000000)          /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is  */
6512                                                                                  /* entered. */
6513 #define PCM_CTL0_LPMR__LPM35                     ((uint32_t)0x000000A0)          /*!< LPM3.5. Core voltage setting 0. */
6514 #define PCM_CTL0_LPMR__LPM45                     ((uint32_t)0x000000C0)          /*!< LPM4.5 */
6515 /* PCM_CTL0[CPM] Bits */
6516 #define PCM_CTL0_CPM_OFS                         ( 8)                            /*!< CPM Bit Offset */
6517 #define PCM_CTL0_CPM_MASK                        ((uint32_t)0x00003F00)          /*!< CPM Bit Mask */
6518 #define PCM_CTL0_CPM0                            ((uint32_t)0x00000100)          /*!< CPM Bit 0 */
6519 #define PCM_CTL0_CPM1                            ((uint32_t)0x00000200)          /*!< CPM Bit 1 */
6520 #define PCM_CTL0_CPM2                            ((uint32_t)0x00000400)          /*!< CPM Bit 2 */
6521 #define PCM_CTL0_CPM3                            ((uint32_t)0x00000800)          /*!< CPM Bit 3 */
6522 #define PCM_CTL0_CPM4                            ((uint32_t)0x00001000)          /*!< CPM Bit 4 */
6523 #define PCM_CTL0_CPM5                            ((uint32_t)0x00002000)          /*!< CPM Bit 5 */
6524 #define PCM_CTL0_CPM_0                           ((uint32_t)0x00000000)          /*!< LDO based Active Mode at Core voltage setting 0. */
6525 #define PCM_CTL0_CPM_1                           ((uint32_t)0x00000100)          /*!< LDO based Active Mode at Core voltage setting 1. */
6526 #define PCM_CTL0_CPM_4                           ((uint32_t)0x00000400)          /*!< DC-DC based Active Mode at Core voltage setting 0. */
6527 #define PCM_CTL0_CPM_5                           ((uint32_t)0x00000500)          /*!< DC-DC based Active Mode at Core voltage setting 1. */
6528 #define PCM_CTL0_CPM_8                           ((uint32_t)0x00000800)          /*!< Low-Frequency Active Mode at Core voltage setting 0. */
6529 #define PCM_CTL0_CPM_9                           ((uint32_t)0x00000900)          /*!< Low-Frequency Active Mode at Core voltage setting 1. */
6530 #define PCM_CTL0_CPM_16                          ((uint32_t)0x00001000)          /*!< LDO based LPM0 at Core voltage setting 0. */
6531 #define PCM_CTL0_CPM_17                          ((uint32_t)0x00001100)          /*!< LDO based LPM0 at Core voltage setting 1. */
6532 #define PCM_CTL0_CPM_20                          ((uint32_t)0x00001400)          /*!< DC-DC based LPM0 at Core voltage setting 0. */
6533 #define PCM_CTL0_CPM_21                          ((uint32_t)0x00001500)          /*!< DC-DC based LPM0 at Core voltage setting 1. */
6534 #define PCM_CTL0_CPM_24                          ((uint32_t)0x00001800)          /*!< Low-Frequency LPM0 at Core voltage setting 0. */
6535 #define PCM_CTL0_CPM_25                          ((uint32_t)0x00001900)          /*!< Low-Frequency LPM0 at Core voltage setting 1. */
6536 #define PCM_CTL0_CPM_32                          ((uint32_t)0x00002000)          /*!< LPM3 */
6537 #define PCM_CTL0_CPM__AM_LDO_VCORE0              ((uint32_t)0x00000000)          /*!< LDO based Active Mode at Core voltage setting 0. */
6538 #define PCM_CTL0_CPM__AM_LDO_VCORE1              ((uint32_t)0x00000100)          /*!< LDO based Active Mode at Core voltage setting 1. */
6539 #define PCM_CTL0_CPM__AM_DCDC_VCORE0             ((uint32_t)0x00000400)          /*!< DC-DC based Active Mode at Core voltage setting 0. */
6540 #define PCM_CTL0_CPM__AM_DCDC_VCORE1             ((uint32_t)0x00000500)          /*!< DC-DC based Active Mode at Core voltage setting 1. */
6541 #define PCM_CTL0_CPM__AM_LF_VCORE0               ((uint32_t)0x00000800)          /*!< Low-Frequency Active Mode at Core voltage setting 0. */
6542 #define PCM_CTL0_CPM__AM_LF_VCORE1               ((uint32_t)0x00000900)          /*!< Low-Frequency Active Mode at Core voltage setting 1. */
6543 #define PCM_CTL0_CPM__LPM0_LDO_VCORE0            ((uint32_t)0x00001000)          /*!< LDO based LPM0 at Core voltage setting 0. */
6544 #define PCM_CTL0_CPM__LPM0_LDO_VCORE1            ((uint32_t)0x00001100)          /*!< LDO based LPM0 at Core voltage setting 1. */
6545 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE0           ((uint32_t)0x00001400)          /*!< DC-DC based LPM0 at Core voltage setting 0. */
6546 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE1           ((uint32_t)0x00001500)          /*!< DC-DC based LPM0 at Core voltage setting 1. */
6547 #define PCM_CTL0_CPM__LPM0_LF_VCORE0             ((uint32_t)0x00001800)          /*!< Low-Frequency LPM0 at Core voltage setting 0. */
6548 #define PCM_CTL0_CPM__LPM0_LF_VCORE1             ((uint32_t)0x00001900)          /*!< Low-Frequency LPM0 at Core voltage setting 1. */
6549 #define PCM_CTL0_CPM__LPM3                       ((uint32_t)0x00002000)          /*!< LPM3 */
6550 /* PCM_CTL0[KEY] Bits */
6551 #define PCM_CTL0_KEY_OFS                         (16)                            /*!< PCMKEY Bit Offset */
6552 #define PCM_CTL0_KEY_MASK                        ((uint32_t)0xFFFF0000)          /*!< PCMKEY Bit Mask */
6553 /* PCM_CTL1[LOCKLPM5] Bits */
6554 #define PCM_CTL1_LOCKLPM5_OFS                    ( 0)                            /*!< LOCKLPM5 Bit Offset */
6555 #define PCM_CTL1_LOCKLPM5                        ((uint32_t)0x00000001)          /*!< Lock LPM5 */
6556 /* PCM_CTL1[LOCKBKUP] Bits */
6557 #define PCM_CTL1_LOCKBKUP_OFS                    ( 1)                            /*!< LOCKBKUP Bit Offset */
6558 #define PCM_CTL1_LOCKBKUP                        ((uint32_t)0x00000002)          /*!< Lock Backup */
6559 /* PCM_CTL1[FORCE_LPM_ENTRY] Bits */
6560 #define PCM_CTL1_FORCE_LPM_ENTRY_OFS             ( 2)                            /*!< FORCE_LPM_ENTRY Bit Offset */
6561 #define PCM_CTL1_FORCE_LPM_ENTRY                 ((uint32_t)0x00000004)          /*!< Force LPM entry */
6562 /* PCM_CTL1[PMR_BUSY] Bits */
6563 #define PCM_CTL1_PMR_BUSY_OFS                    ( 8)                            /*!< PMR_BUSY Bit Offset */
6564 #define PCM_CTL1_PMR_BUSY                        ((uint32_t)0x00000100)          /*!< Power mode request busy flag */
6565 /* PCM_CTL1[KEY] Bits */
6566 #define PCM_CTL1_KEY_OFS                         (16)                            /*!< PCMKEY Bit Offset */
6567 #define PCM_CTL1_KEY_MASK                        ((uint32_t)0xFFFF0000)          /*!< PCMKEY Bit Mask */
6568 /* PCM_IE[LPM_INVALID_TR_IE] Bits */
6569 #define PCM_IE_LPM_INVALID_TR_IE_OFS             ( 0)                            /*!< LPM_INVALID_TR_IE Bit Offset */
6570 #define PCM_IE_LPM_INVALID_TR_IE                 ((uint32_t)0x00000001)          /*!< LPM invalid transition interrupt enable */
6571 /* PCM_IE[LPM_INVALID_CLK_IE] Bits */
6572 #define PCM_IE_LPM_INVALID_CLK_IE_OFS            ( 1)                            /*!< LPM_INVALID_CLK_IE Bit Offset */
6573 #define PCM_IE_LPM_INVALID_CLK_IE                ((uint32_t)0x00000002)          /*!< LPM invalid clock interrupt enable */
6574 /* PCM_IE[AM_INVALID_TR_IE] Bits */
6575 #define PCM_IE_AM_INVALID_TR_IE_OFS              ( 2)                            /*!< AM_INVALID_TR_IE Bit Offset */
6576 #define PCM_IE_AM_INVALID_TR_IE                  ((uint32_t)0x00000004)          /*!< Active mode invalid transition interrupt enable */
6577 /* PCM_IE[DCDC_ERROR_IE] Bits */
6578 #define PCM_IE_DCDC_ERROR_IE_OFS                 ( 6)                            /*!< DCDC_ERROR_IE Bit Offset */
6579 #define PCM_IE_DCDC_ERROR_IE                     ((uint32_t)0x00000040)          /*!< DC-DC error interrupt enable */
6580 /* PCM_IFG[LPM_INVALID_TR_IFG] Bits */
6581 #define PCM_IFG_LPM_INVALID_TR_IFG_OFS           ( 0)                            /*!< LPM_INVALID_TR_IFG Bit Offset */
6582 #define PCM_IFG_LPM_INVALID_TR_IFG               ((uint32_t)0x00000001)          /*!< LPM invalid transition flag */
6583 /* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */
6584 #define PCM_IFG_LPM_INVALID_CLK_IFG_OFS          ( 1)                            /*!< LPM_INVALID_CLK_IFG Bit Offset */
6585 #define PCM_IFG_LPM_INVALID_CLK_IFG              ((uint32_t)0x00000002)          /*!< LPM invalid clock flag */
6586 /* PCM_IFG[AM_INVALID_TR_IFG] Bits */
6587 #define PCM_IFG_AM_INVALID_TR_IFG_OFS            ( 2)                            /*!< AM_INVALID_TR_IFG Bit Offset */
6588 #define PCM_IFG_AM_INVALID_TR_IFG                ((uint32_t)0x00000004)          /*!< Active mode invalid transition flag */
6589 /* PCM_IFG[DCDC_ERROR_IFG] Bits */
6590 #define PCM_IFG_DCDC_ERROR_IFG_OFS               ( 6)                            /*!< DCDC_ERROR_IFG Bit Offset */
6591 #define PCM_IFG_DCDC_ERROR_IFG                   ((uint32_t)0x00000040)          /*!< DC-DC error flag */
6592 /* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */
6593 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS    ( 0)                            /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */
6594 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG        ((uint32_t)0x00000001)          /*!< Clear LPM invalid transition flag */
6595 /* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */
6596 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS   ( 1)                            /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */
6597 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG       ((uint32_t)0x00000002)          /*!< Clear LPM invalid clock flag */
6598 /* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */
6599 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS     ( 2)                            /*!< CLR_AM_INVALID_TR_IFG Bit Offset */
6600 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG         ((uint32_t)0x00000004)          /*!< Clear active mode invalid transition flag */
6601 /* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */
6602 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS        ( 6)                            /*!< CLR_DCDC_ERROR_IFG Bit Offset */
6603 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG            ((uint32_t)0x00000040)          /*!< Clear DC-DC error flag */
6604 /* Pre-defined bitfield values */
6605 #define PCM_CTL0_KEY_VAL                         ((uint32_t)0x695A0000)          /*!< PCM key value */
6606 #define PCM_CTL1_KEY_VAL                         ((uint32_t)0x695A0000)          /*!< PCM key value */
6607 
6608 
6609 /******************************************************************************
6610 * PMAP Bits
6611 ******************************************************************************/
6612 /* PMAP_CTL[LOCKED] Bits */
6613 #define PMAP_CTL_LOCKED_OFS                      ( 0)                            /*!< PMAPLOCKED Bit Offset */
6614 #define PMAP_CTL_LOCKED                          ((uint16_t)0x0001)              /*!< Port mapping lock bit */
6615 /* PMAP_CTL[PRECFG] Bits */
6616 #define PMAP_CTL_PRECFG_OFS                      ( 1)                            /*!< PMAPRECFG Bit Offset */
6617 #define PMAP_CTL_PRECFG                          ((uint16_t)0x0002)              /*!< Port mapping reconfiguration control bit */
6618 /* Pre-defined bitfield values */
6619 #define PMAP_NONE                                            0
6620 #define PMAP_UCA0CLK                                         1
6621 #define PMAP_UCA0RXD                                         2
6622 #define PMAP_UCA0SOMI                                        2
6623 #define PMAP_UCA0TXD                                         3
6624 #define PMAP_UCA0SIMO                                        3
6625 #define PMAP_UCB0CLK                                         4
6626 #define PMAP_UCB0SDA                                         5
6627 #define PMAP_UCB0SIMO                                        5
6628 #define PMAP_UCB0SCL                                         6
6629 #define PMAP_UCB0SOMI                                        6
6630 #define PMAP_UCA1STE                                         7
6631 #define PMAP_UCA1CLK                                         8
6632 #define PMAP_UCA1RXD                                         9
6633 #define PMAP_UCA1SOMI                                        9
6634 #define PMAP_UCA1TXD                                         10
6635 #define PMAP_UCA1SIMO                                        10
6636 #define PMAP_UCA2STE                                         11
6637 #define PMAP_UCA2CLK                                         12
6638 #define PMAP_UCA2RXD                                         13
6639 #define PMAP_UCA2SOMI                                        13
6640 #define PMAP_UCA2TXD                                         14
6641 #define PMAP_UCA2SIMO                                        14
6642 #define PMAP_UCB2STE                                         15
6643 #define PMAP_UCB2CLK                                         16
6644 #define PMAP_UCB2SDA                                         17
6645 #define PMAP_UCB2SIMO                                        17
6646 #define PMAP_UCB2SCL                                         18
6647 #define PMAP_UCB2SOMI                                        18
6648 #define PMAP_TA0CCR0A                                        19
6649 #define PMAP_TA0CCR1A                                        20
6650 #define PMAP_TA0CCR2A                                        21
6651 #define PMAP_TA0CCR3A                                        22
6652 #define PMAP_TA0CCR4A                                        23
6653 #define PMAP_TA1CCR1A                                        24
6654 #define PMAP_TA1CCR2A                                        25
6655 #define PMAP_TA1CCR3A                                        26
6656 #define PMAP_TA1CCR4A                                        27
6657 #define PMAP_TA0CLK                                          28
6658 #define PMAP_CE0OUT                                          28
6659 #define PMAP_TA1CLK                                          29
6660 #define PMAP_CE1OUT                                          29
6661 #define PMAP_DMAE0                                           30
6662 #define PMAP_SMCLK                                           30
6663 #define PMAP_ANALOG                                          31
6664 
6665 #define PMAP_KEYID_VAL                           ((uint16_t)0x2D52)              /*!< Port Mapping Key */
6666 
6667 
6668 /******************************************************************************
6669 * PSS Bits
6670 ******************************************************************************/
6671 /* PSS_KEY[KEY] Bits */
6672 #define PSS_KEY_KEY_OFS                          ( 0)                            /*!< PSSKEY Bit Offset */
6673 #define PSS_KEY_KEY_MASK                         ((uint32_t)0x0000FFFF)          /*!< PSSKEY Bit Mask */
6674 /* PSS_CTL0[SVSMHOFF] Bits */
6675 #define PSS_CTL0_SVSMHOFF_OFS                    ( 0)                            /*!< SVSMHOFF Bit Offset */
6676 #define PSS_CTL0_SVSMHOFF                        ((uint32_t)0x00000001)          /*!< SVSM high-side off */
6677 /* PSS_CTL0[SVSMHLP] Bits */
6678 #define PSS_CTL0_SVSMHLP_OFS                     ( 1)                            /*!< SVSMHLP Bit Offset */
6679 #define PSS_CTL0_SVSMHLP                         ((uint32_t)0x00000002)          /*!< SVSM high-side low power normal performance mode */
6680 /* PSS_CTL0[SVSMHS] Bits */
6681 #define PSS_CTL0_SVSMHS_OFS                      ( 2)                            /*!< SVSMHS Bit Offset */
6682 #define PSS_CTL0_SVSMHS                          ((uint32_t)0x00000004)          /*!< Supply supervisor or monitor selection for the high-side */
6683 /* PSS_CTL0[SVSMHTH] Bits */
6684 #define PSS_CTL0_SVSMHTH_OFS                     ( 3)                            /*!< SVSMHTH Bit Offset */
6685 #define PSS_CTL0_SVSMHTH_MASK                    ((uint32_t)0x00000038)          /*!< SVSMHTH Bit Mask */
6686 /* PSS_CTL0[SVMHOE] Bits */
6687 #define PSS_CTL0_SVMHOE_OFS                      ( 6)                            /*!< SVMHOE Bit Offset */
6688 #define PSS_CTL0_SVMHOE                          ((uint32_t)0x00000040)          /*!< SVSM high-side output enable */
6689 /* PSS_CTL0[SVMHOUTPOLAL] Bits */
6690 #define PSS_CTL0_SVMHOUTPOLAL_OFS                ( 7)                            /*!< SVMHOUTPOLAL Bit Offset */
6691 #define PSS_CTL0_SVMHOUTPOLAL                    ((uint32_t)0x00000080)          /*!< SVMHOUT pin polarity active low */
6692 /* PSS_CTL0[DCDC_FORCE] Bits */
6693 #define PSS_CTL0_DCDC_FORCE_OFS                  (10)                            /*!< DCDC_FORCE Bit Offset */
6694 #define PSS_CTL0_DCDC_FORCE                      ((uint32_t)0x00000400)          /*!< Force DC-DC regulator operation */
6695 /* PSS_CTL0[VCORETRAN] Bits */
6696 #define PSS_CTL0_VCORETRAN_OFS                   (12)                            /*!< VCORETRAN Bit Offset */
6697 #define PSS_CTL0_VCORETRAN_MASK                  ((uint32_t)0x00003000)          /*!< VCORETRAN Bit Mask */
6698 #define PSS_CTL0_VCORETRAN0                      ((uint32_t)0x00001000)          /*!< VCORETRAN Bit 0 */
6699 #define PSS_CTL0_VCORETRAN1                      ((uint32_t)0x00002000)          /*!< VCORETRAN Bit 1 */
6700 #define PSS_CTL0_VCORETRAN_0                     ((uint32_t)0x00000000)          /*!< 32 s / 100 mV */
6701 #define PSS_CTL0_VCORETRAN_1                     ((uint32_t)0x00001000)          /*!< 64 s / 100 mV */
6702 #define PSS_CTL0_VCORETRAN_2                     ((uint32_t)0x00002000)          /*!< 128 s / 100 mV (default) */
6703 #define PSS_CTL0_VCORETRAN_3                     ((uint32_t)0x00003000)          /*!< 256 s / 100 mV */
6704 #define PSS_CTL0_VCORETRAN__32                   ((uint32_t)0x00000000)          /*!< 32 s / 100 mV */
6705 #define PSS_CTL0_VCORETRAN__64                   ((uint32_t)0x00001000)          /*!< 64 s / 100 mV */
6706 #define PSS_CTL0_VCORETRAN__128                  ((uint32_t)0x00002000)          /*!< 128 s / 100 mV (default) */
6707 #define PSS_CTL0_VCORETRAN__256                  ((uint32_t)0x00003000)          /*!< 256 s / 100 mV */
6708 /* PSS_IE[SVSMHIE] Bits */
6709 #define PSS_IE_SVSMHIE_OFS                       ( 1)                            /*!< SVSMHIE Bit Offset */
6710 #define PSS_IE_SVSMHIE                           ((uint32_t)0x00000002)          /*!< High-side SVSM interrupt enable */
6711 /* PSS_IFG[SVSMHIFG] Bits */
6712 #define PSS_IFG_SVSMHIFG_OFS                     ( 1)                            /*!< SVSMHIFG Bit Offset */
6713 #define PSS_IFG_SVSMHIFG                         ((uint32_t)0x00000002)          /*!< High-side SVSM interrupt flag */
6714 /* PSS_CLRIFG[CLRSVSMHIFG] Bits */
6715 #define PSS_CLRIFG_CLRSVSMHIFG_OFS               ( 1)                            /*!< CLRSVSMHIFG Bit Offset */
6716 #define PSS_CLRIFG_CLRSVSMHIFG                   ((uint32_t)0x00000002)          /*!< SVSMH clear interrupt flag */
6717 /* Pre-defined bitfield values */
6718 #define PSS_KEY_KEY_VAL                           ((uint32_t)0x0000695A)          /*!< PSS control key value */
6719 
6720 
6721 /******************************************************************************
6722 * REF_A Bits
6723 ******************************************************************************/
6724 /* REF_A_CTL0[ON] Bits */
6725 #define REF_A_CTL0_ON_OFS                        ( 0)                            /*!< REFON Bit Offset */
6726 #define REF_A_CTL0_ON                            ((uint16_t)0x0001)              /*!< Reference enable */
6727 /* REF_A_CTL0[OUT] Bits */
6728 #define REF_A_CTL0_OUT_OFS                       ( 1)                            /*!< REFOUT Bit Offset */
6729 #define REF_A_CTL0_OUT                           ((uint16_t)0x0002)              /*!< Reference output buffer */
6730 /* REF_A_CTL0[TCOFF] Bits */
6731 #define REF_A_CTL0_TCOFF_OFS                     ( 3)                            /*!< REFTCOFF Bit Offset */
6732 #define REF_A_CTL0_TCOFF                         ((uint16_t)0x0008)              /*!< Temperature sensor disabled */
6733 /* REF_A_CTL0[VSEL] Bits */
6734 #define REF_A_CTL0_VSEL_OFS                      ( 4)                            /*!< REFVSEL Bit Offset */
6735 #define REF_A_CTL0_VSEL_MASK                     ((uint16_t)0x0030)              /*!< REFVSEL Bit Mask */
6736 #define REF_A_CTL0_VSEL0                         ((uint16_t)0x0010)              /*!< VSEL Bit 0 */
6737 #define REF_A_CTL0_VSEL1                         ((uint16_t)0x0020)              /*!< VSEL Bit 1 */
6738 #define REF_A_CTL0_VSEL_0                        ((uint16_t)0x0000)              /*!< 1.2 V available when reference requested or REFON = 1 */
6739 #define REF_A_CTL0_VSEL_1                        ((uint16_t)0x0010)              /*!< 1.45 V available when reference requested or REFON = 1 */
6740 #define REF_A_CTL0_VSEL_3                        ((uint16_t)0x0030)              /*!< 2.5 V available when reference requested or REFON = 1 */
6741 /* REF_A_CTL0[GENOT] Bits */
6742 #define REF_A_CTL0_GENOT_OFS                     ( 6)                            /*!< REFGENOT Bit Offset */
6743 #define REF_A_CTL0_GENOT                         ((uint16_t)0x0040)              /*!< Reference generator one-time trigger */
6744 /* REF_A_CTL0[BGOT] Bits */
6745 #define REF_A_CTL0_BGOT_OFS                      ( 7)                            /*!< REFBGOT Bit Offset */
6746 #define REF_A_CTL0_BGOT                          ((uint16_t)0x0080)              /*!< Bandgap and bandgap buffer one-time trigger */
6747 /* REF_A_CTL0[GENACT] Bits */
6748 #define REF_A_CTL0_GENACT_OFS                    ( 8)                            /*!< REFGENACT Bit Offset */
6749 #define REF_A_CTL0_GENACT                        ((uint16_t)0x0100)              /*!< Reference generator active */
6750 /* REF_A_CTL0[BGACT] Bits */
6751 #define REF_A_CTL0_BGACT_OFS                     ( 9)                            /*!< REFBGACT Bit Offset */
6752 #define REF_A_CTL0_BGACT                         ((uint16_t)0x0200)              /*!< Reference bandgap active */
6753 /* REF_A_CTL0[GENBUSY] Bits */
6754 #define REF_A_CTL0_GENBUSY_OFS                   (10)                            /*!< REFGENBUSY Bit Offset */
6755 #define REF_A_CTL0_GENBUSY                       ((uint16_t)0x0400)              /*!< Reference generator busy */
6756 /* REF_A_CTL0[BGMODE] Bits */
6757 #define REF_A_CTL0_BGMODE_OFS                    (11)                            /*!< BGMODE Bit Offset */
6758 #define REF_A_CTL0_BGMODE                        ((uint16_t)0x0800)              /*!< Bandgap mode */
6759 /* REF_A_CTL0[GENRDY] Bits */
6760 #define REF_A_CTL0_GENRDY_OFS                    (12)                            /*!< REFGENRDY Bit Offset */
6761 #define REF_A_CTL0_GENRDY                        ((uint16_t)0x1000)              /*!< Variable reference voltage ready status */
6762 /* REF_A_CTL0[BGRDY] Bits */
6763 #define REF_A_CTL0_BGRDY_OFS                     (13)                            /*!< REFBGRDY Bit Offset */
6764 #define REF_A_CTL0_BGRDY                         ((uint16_t)0x2000)              /*!< Buffered bandgap voltage ready status */
6765 
6766 /******************************************************************************
6767 * RSTCTL Bits
6768 ******************************************************************************/
6769 /* RSTCTL_RESET_REQ[SOFT_REQ] Bits */
6770 #define RSTCTL_RESET_REQ_SOFT_REQ_OFS            ( 0)                            /*!< SOFT_REQ Bit Offset */
6771 #define RSTCTL_RESET_REQ_SOFT_REQ                ((uint32_t)0x00000001)          /*!< Soft Reset request */
6772 /* RSTCTL_RESET_REQ[HARD_REQ] Bits */
6773 #define RSTCTL_RESET_REQ_HARD_REQ_OFS            ( 1)                            /*!< HARD_REQ Bit Offset */
6774 #define RSTCTL_RESET_REQ_HARD_REQ                ((uint32_t)0x00000002)          /*!< Hard Reset request */
6775 /* RSTCTL_RESET_REQ[RSTKEY] Bits */
6776 #define RSTCTL_RESET_REQ_RSTKEY_OFS              ( 8)                            /*!< RSTKEY Bit Offset */
6777 #define RSTCTL_RESET_REQ_RSTKEY_MASK             ((uint32_t)0x0000FF00)          /*!< RSTKEY Bit Mask */
6778 /* RSTCTL_HARDRESET_STAT[SRC0] Bits */
6779 #define RSTCTL_HARDRESET_STAT_SRC0_OFS           ( 0)                            /*!< SRC0 Bit Offset */
6780 #define RSTCTL_HARDRESET_STAT_SRC0               ((uint32_t)0x00000001)          /*!< Indicates that SRC0 was the source of the Hard Reset */
6781 /* RSTCTL_HARDRESET_STAT[SRC1] Bits */
6782 #define RSTCTL_HARDRESET_STAT_SRC1_OFS           ( 1)                            /*!< SRC1 Bit Offset */
6783 #define RSTCTL_HARDRESET_STAT_SRC1               ((uint32_t)0x00000002)          /*!< Indicates that SRC1 was the source of the Hard Reset */
6784 /* RSTCTL_HARDRESET_STAT[SRC2] Bits */
6785 #define RSTCTL_HARDRESET_STAT_SRC2_OFS           ( 2)                            /*!< SRC2 Bit Offset */
6786 #define RSTCTL_HARDRESET_STAT_SRC2               ((uint32_t)0x00000004)          /*!< Indicates that SRC2 was the source of the Hard Reset */
6787 /* RSTCTL_HARDRESET_STAT[SRC3] Bits */
6788 #define RSTCTL_HARDRESET_STAT_SRC3_OFS           ( 3)                            /*!< SRC3 Bit Offset */
6789 #define RSTCTL_HARDRESET_STAT_SRC3               ((uint32_t)0x00000008)          /*!< Indicates that SRC3 was the source of the Hard Reset */
6790 /* RSTCTL_HARDRESET_STAT[SRC4] Bits */
6791 #define RSTCTL_HARDRESET_STAT_SRC4_OFS           ( 4)                            /*!< SRC4 Bit Offset */
6792 #define RSTCTL_HARDRESET_STAT_SRC4               ((uint32_t)0x00000010)          /*!< Indicates that SRC4 was the source of the Hard Reset */
6793 /* RSTCTL_HARDRESET_STAT[SRC5] Bits */
6794 #define RSTCTL_HARDRESET_STAT_SRC5_OFS           ( 5)                            /*!< SRC5 Bit Offset */
6795 #define RSTCTL_HARDRESET_STAT_SRC5               ((uint32_t)0x00000020)          /*!< Indicates that SRC5 was the source of the Hard Reset */
6796 /* RSTCTL_HARDRESET_STAT[SRC6] Bits */
6797 #define RSTCTL_HARDRESET_STAT_SRC6_OFS           ( 6)                            /*!< SRC6 Bit Offset */
6798 #define RSTCTL_HARDRESET_STAT_SRC6               ((uint32_t)0x00000040)          /*!< Indicates that SRC6 was the source of the Hard Reset */
6799 /* RSTCTL_HARDRESET_STAT[SRC7] Bits */
6800 #define RSTCTL_HARDRESET_STAT_SRC7_OFS           ( 7)                            /*!< SRC7 Bit Offset */
6801 #define RSTCTL_HARDRESET_STAT_SRC7               ((uint32_t)0x00000080)          /*!< Indicates that SRC7 was the source of the Hard Reset */
6802 /* RSTCTL_HARDRESET_STAT[SRC8] Bits */
6803 #define RSTCTL_HARDRESET_STAT_SRC8_OFS           ( 8)                            /*!< SRC8 Bit Offset */
6804 #define RSTCTL_HARDRESET_STAT_SRC8               ((uint32_t)0x00000100)          /*!< Indicates that SRC8 was the source of the Hard Reset */
6805 /* RSTCTL_HARDRESET_STAT[SRC9] Bits */
6806 #define RSTCTL_HARDRESET_STAT_SRC9_OFS           ( 9)                            /*!< SRC9 Bit Offset */
6807 #define RSTCTL_HARDRESET_STAT_SRC9               ((uint32_t)0x00000200)          /*!< Indicates that SRC9 was the source of the Hard Reset */
6808 /* RSTCTL_HARDRESET_STAT[SRC10] Bits */
6809 #define RSTCTL_HARDRESET_STAT_SRC10_OFS          (10)                            /*!< SRC10 Bit Offset */
6810 #define RSTCTL_HARDRESET_STAT_SRC10              ((uint32_t)0x00000400)          /*!< Indicates that SRC10 was the source of the Hard Reset */
6811 /* RSTCTL_HARDRESET_STAT[SRC11] Bits */
6812 #define RSTCTL_HARDRESET_STAT_SRC11_OFS          (11)                            /*!< SRC11 Bit Offset */
6813 #define RSTCTL_HARDRESET_STAT_SRC11              ((uint32_t)0x00000800)          /*!< Indicates that SRC11 was the source of the Hard Reset */
6814 /* RSTCTL_HARDRESET_STAT[SRC12] Bits */
6815 #define RSTCTL_HARDRESET_STAT_SRC12_OFS          (12)                            /*!< SRC12 Bit Offset */
6816 #define RSTCTL_HARDRESET_STAT_SRC12              ((uint32_t)0x00001000)          /*!< Indicates that SRC12 was the source of the Hard Reset */
6817 /* RSTCTL_HARDRESET_STAT[SRC13] Bits */
6818 #define RSTCTL_HARDRESET_STAT_SRC13_OFS          (13)                            /*!< SRC13 Bit Offset */
6819 #define RSTCTL_HARDRESET_STAT_SRC13              ((uint32_t)0x00002000)          /*!< Indicates that SRC13 was the source of the Hard Reset */
6820 /* RSTCTL_HARDRESET_STAT[SRC14] Bits */
6821 #define RSTCTL_HARDRESET_STAT_SRC14_OFS          (14)                            /*!< SRC14 Bit Offset */
6822 #define RSTCTL_HARDRESET_STAT_SRC14              ((uint32_t)0x00004000)          /*!< Indicates that SRC14 was the source of the Hard Reset */
6823 /* RSTCTL_HARDRESET_STAT[SRC15] Bits */
6824 #define RSTCTL_HARDRESET_STAT_SRC15_OFS          (15)                            /*!< SRC15 Bit Offset */
6825 #define RSTCTL_HARDRESET_STAT_SRC15              ((uint32_t)0x00008000)          /*!< Indicates that SRC15 was the source of the Hard Reset */
6826 /* RSTCTL_HARDRESET_CLR[SRC0] Bits */
6827 #define RSTCTL_HARDRESET_CLR_SRC0_OFS            ( 0)                            /*!< SRC0 Bit Offset */
6828 #define RSTCTL_HARDRESET_CLR_SRC0                ((uint32_t)0x00000001)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6829 /* RSTCTL_HARDRESET_CLR[SRC1] Bits */
6830 #define RSTCTL_HARDRESET_CLR_SRC1_OFS            ( 1)                            /*!< SRC1 Bit Offset */
6831 #define RSTCTL_HARDRESET_CLR_SRC1                ((uint32_t)0x00000002)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6832 /* RSTCTL_HARDRESET_CLR[SRC2] Bits */
6833 #define RSTCTL_HARDRESET_CLR_SRC2_OFS            ( 2)                            /*!< SRC2 Bit Offset */
6834 #define RSTCTL_HARDRESET_CLR_SRC2                ((uint32_t)0x00000004)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6835 /* RSTCTL_HARDRESET_CLR[SRC3] Bits */
6836 #define RSTCTL_HARDRESET_CLR_SRC3_OFS            ( 3)                            /*!< SRC3 Bit Offset */
6837 #define RSTCTL_HARDRESET_CLR_SRC3                ((uint32_t)0x00000008)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6838 /* RSTCTL_HARDRESET_CLR[SRC4] Bits */
6839 #define RSTCTL_HARDRESET_CLR_SRC4_OFS            ( 4)                            /*!< SRC4 Bit Offset */
6840 #define RSTCTL_HARDRESET_CLR_SRC4                ((uint32_t)0x00000010)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6841 /* RSTCTL_HARDRESET_CLR[SRC5] Bits */
6842 #define RSTCTL_HARDRESET_CLR_SRC5_OFS            ( 5)                            /*!< SRC5 Bit Offset */
6843 #define RSTCTL_HARDRESET_CLR_SRC5                ((uint32_t)0x00000020)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6844 /* RSTCTL_HARDRESET_CLR[SRC6] Bits */
6845 #define RSTCTL_HARDRESET_CLR_SRC6_OFS            ( 6)                            /*!< SRC6 Bit Offset */
6846 #define RSTCTL_HARDRESET_CLR_SRC6                ((uint32_t)0x00000040)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6847 /* RSTCTL_HARDRESET_CLR[SRC7] Bits */
6848 #define RSTCTL_HARDRESET_CLR_SRC7_OFS            ( 7)                            /*!< SRC7 Bit Offset */
6849 #define RSTCTL_HARDRESET_CLR_SRC7                ((uint32_t)0x00000080)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6850 /* RSTCTL_HARDRESET_CLR[SRC8] Bits */
6851 #define RSTCTL_HARDRESET_CLR_SRC8_OFS            ( 8)                            /*!< SRC8 Bit Offset */
6852 #define RSTCTL_HARDRESET_CLR_SRC8                ((uint32_t)0x00000100)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6853 /* RSTCTL_HARDRESET_CLR[SRC9] Bits */
6854 #define RSTCTL_HARDRESET_CLR_SRC9_OFS            ( 9)                            /*!< SRC9 Bit Offset */
6855 #define RSTCTL_HARDRESET_CLR_SRC9                ((uint32_t)0x00000200)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6856 /* RSTCTL_HARDRESET_CLR[SRC10] Bits */
6857 #define RSTCTL_HARDRESET_CLR_SRC10_OFS           (10)                            /*!< SRC10 Bit Offset */
6858 #define RSTCTL_HARDRESET_CLR_SRC10               ((uint32_t)0x00000400)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6859 /* RSTCTL_HARDRESET_CLR[SRC11] Bits */
6860 #define RSTCTL_HARDRESET_CLR_SRC11_OFS           (11)                            /*!< SRC11 Bit Offset */
6861 #define RSTCTL_HARDRESET_CLR_SRC11               ((uint32_t)0x00000800)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6862 /* RSTCTL_HARDRESET_CLR[SRC12] Bits */
6863 #define RSTCTL_HARDRESET_CLR_SRC12_OFS           (12)                            /*!< SRC12 Bit Offset */
6864 #define RSTCTL_HARDRESET_CLR_SRC12               ((uint32_t)0x00001000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6865 /* RSTCTL_HARDRESET_CLR[SRC13] Bits */
6866 #define RSTCTL_HARDRESET_CLR_SRC13_OFS           (13)                            /*!< SRC13 Bit Offset */
6867 #define RSTCTL_HARDRESET_CLR_SRC13               ((uint32_t)0x00002000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6868 /* RSTCTL_HARDRESET_CLR[SRC14] Bits */
6869 #define RSTCTL_HARDRESET_CLR_SRC14_OFS           (14)                            /*!< SRC14 Bit Offset */
6870 #define RSTCTL_HARDRESET_CLR_SRC14               ((uint32_t)0x00004000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */
6871 /* RSTCTL_HARDRESET_CLR[SRC15] Bits */
6872 #define RSTCTL_HARDRESET_CLR_SRC15_OFS           (15)                            /*!< SRC15 Bit Offset */
6873 #define RSTCTL_HARDRESET_CLR_SRC15               ((uint32_t)0x00008000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */
6874 /* RSTCTL_HARDRESET_SET[SRC0] Bits */
6875 #define RSTCTL_HARDRESET_SET_SRC0_OFS            ( 0)                            /*!< SRC0 Bit Offset */
6876 #define RSTCTL_HARDRESET_SET_SRC0                ((uint32_t)0x00000001)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6877                                                                                  /* initiates a Hard Reset) */
6878 /* RSTCTL_HARDRESET_SET[SRC1] Bits */
6879 #define RSTCTL_HARDRESET_SET_SRC1_OFS            ( 1)                            /*!< SRC1 Bit Offset */
6880 #define RSTCTL_HARDRESET_SET_SRC1                ((uint32_t)0x00000002)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6881                                                                                  /* initiates a Hard Reset) */
6882 /* RSTCTL_HARDRESET_SET[SRC2] Bits */
6883 #define RSTCTL_HARDRESET_SET_SRC2_OFS            ( 2)                            /*!< SRC2 Bit Offset */
6884 #define RSTCTL_HARDRESET_SET_SRC2                ((uint32_t)0x00000004)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6885                                                                                  /* initiates a Hard Reset) */
6886 /* RSTCTL_HARDRESET_SET[SRC3] Bits */
6887 #define RSTCTL_HARDRESET_SET_SRC3_OFS            ( 3)                            /*!< SRC3 Bit Offset */
6888 #define RSTCTL_HARDRESET_SET_SRC3                ((uint32_t)0x00000008)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6889                                                                                  /* initiates a Hard Reset) */
6890 /* RSTCTL_HARDRESET_SET[SRC4] Bits */
6891 #define RSTCTL_HARDRESET_SET_SRC4_OFS            ( 4)                            /*!< SRC4 Bit Offset */
6892 #define RSTCTL_HARDRESET_SET_SRC4                ((uint32_t)0x00000010)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6893                                                                                  /* initiates a Hard Reset) */
6894 /* RSTCTL_HARDRESET_SET[SRC5] Bits */
6895 #define RSTCTL_HARDRESET_SET_SRC5_OFS            ( 5)                            /*!< SRC5 Bit Offset */
6896 #define RSTCTL_HARDRESET_SET_SRC5                ((uint32_t)0x00000020)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6897                                                                                  /* initiates a Hard Reset) */
6898 /* RSTCTL_HARDRESET_SET[SRC6] Bits */
6899 #define RSTCTL_HARDRESET_SET_SRC6_OFS            ( 6)                            /*!< SRC6 Bit Offset */
6900 #define RSTCTL_HARDRESET_SET_SRC6                ((uint32_t)0x00000040)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6901                                                                                  /* initiates a Hard Reset) */
6902 /* RSTCTL_HARDRESET_SET[SRC7] Bits */
6903 #define RSTCTL_HARDRESET_SET_SRC7_OFS            ( 7)                            /*!< SRC7 Bit Offset */
6904 #define RSTCTL_HARDRESET_SET_SRC7                ((uint32_t)0x00000080)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6905                                                                                  /* initiates a Hard Reset) */
6906 /* RSTCTL_HARDRESET_SET[SRC8] Bits */
6907 #define RSTCTL_HARDRESET_SET_SRC8_OFS            ( 8)                            /*!< SRC8 Bit Offset */
6908 #define RSTCTL_HARDRESET_SET_SRC8                ((uint32_t)0x00000100)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6909                                                                                  /* initiates a Hard Reset) */
6910 /* RSTCTL_HARDRESET_SET[SRC9] Bits */
6911 #define RSTCTL_HARDRESET_SET_SRC9_OFS            ( 9)                            /*!< SRC9 Bit Offset */
6912 #define RSTCTL_HARDRESET_SET_SRC9                ((uint32_t)0x00000200)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6913                                                                                  /* initiates a Hard Reset) */
6914 /* RSTCTL_HARDRESET_SET[SRC10] Bits */
6915 #define RSTCTL_HARDRESET_SET_SRC10_OFS           (10)                            /*!< SRC10 Bit Offset */
6916 #define RSTCTL_HARDRESET_SET_SRC10               ((uint32_t)0x00000400)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6917                                                                                  /* initiates a Hard Reset) */
6918 /* RSTCTL_HARDRESET_SET[SRC11] Bits */
6919 #define RSTCTL_HARDRESET_SET_SRC11_OFS           (11)                            /*!< SRC11 Bit Offset */
6920 #define RSTCTL_HARDRESET_SET_SRC11               ((uint32_t)0x00000800)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6921                                                                                  /* initiates a Hard Reset) */
6922 /* RSTCTL_HARDRESET_SET[SRC12] Bits */
6923 #define RSTCTL_HARDRESET_SET_SRC12_OFS           (12)                            /*!< SRC12 Bit Offset */
6924 #define RSTCTL_HARDRESET_SET_SRC12               ((uint32_t)0x00001000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6925                                                                                  /* initiates a Hard Reset) */
6926 /* RSTCTL_HARDRESET_SET[SRC13] Bits */
6927 #define RSTCTL_HARDRESET_SET_SRC13_OFS           (13)                            /*!< SRC13 Bit Offset */
6928 #define RSTCTL_HARDRESET_SET_SRC13               ((uint32_t)0x00002000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6929                                                                                  /* initiates a Hard Reset) */
6930 /* RSTCTL_HARDRESET_SET[SRC14] Bits */
6931 #define RSTCTL_HARDRESET_SET_SRC14_OFS           (14)                            /*!< SRC14 Bit Offset */
6932 #define RSTCTL_HARDRESET_SET_SRC14               ((uint32_t)0x00004000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6933                                                                                  /* initiates a Hard Reset) */
6934 /* RSTCTL_HARDRESET_SET[SRC15] Bits */
6935 #define RSTCTL_HARDRESET_SET_SRC15_OFS           (15)                            /*!< SRC15 Bit Offset */
6936 #define RSTCTL_HARDRESET_SET_SRC15               ((uint32_t)0x00008000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and  */
6937                                                                                  /* initiates a Hard Reset) */
6938 /* RSTCTL_SOFTRESET_STAT[SRC0] Bits */
6939 #define RSTCTL_SOFTRESET_STAT_SRC0_OFS           ( 0)                            /*!< SRC0 Bit Offset */
6940 #define RSTCTL_SOFTRESET_STAT_SRC0               ((uint32_t)0x00000001)          /*!< If 1, indicates that SRC0 was the source of the Soft Reset */
6941 /* RSTCTL_SOFTRESET_STAT[SRC1] Bits */
6942 #define RSTCTL_SOFTRESET_STAT_SRC1_OFS           ( 1)                            /*!< SRC1 Bit Offset */
6943 #define RSTCTL_SOFTRESET_STAT_SRC1               ((uint32_t)0x00000002)          /*!< If 1, indicates that SRC1 was the source of the Soft Reset */
6944 /* RSTCTL_SOFTRESET_STAT[SRC2] Bits */
6945 #define RSTCTL_SOFTRESET_STAT_SRC2_OFS           ( 2)                            /*!< SRC2 Bit Offset */
6946 #define RSTCTL_SOFTRESET_STAT_SRC2               ((uint32_t)0x00000004)          /*!< If 1, indicates that SRC2 was the source of the Soft Reset */
6947 /* RSTCTL_SOFTRESET_STAT[SRC3] Bits */
6948 #define RSTCTL_SOFTRESET_STAT_SRC3_OFS           ( 3)                            /*!< SRC3 Bit Offset */
6949 #define RSTCTL_SOFTRESET_STAT_SRC3               ((uint32_t)0x00000008)          /*!< If 1, indicates that SRC3 was the source of the Soft Reset */
6950 /* RSTCTL_SOFTRESET_STAT[SRC4] Bits */
6951 #define RSTCTL_SOFTRESET_STAT_SRC4_OFS           ( 4)                            /*!< SRC4 Bit Offset */
6952 #define RSTCTL_SOFTRESET_STAT_SRC4               ((uint32_t)0x00000010)          /*!< If 1, indicates that SRC4 was the source of the Soft Reset */
6953 /* RSTCTL_SOFTRESET_STAT[SRC5] Bits */
6954 #define RSTCTL_SOFTRESET_STAT_SRC5_OFS           ( 5)                            /*!< SRC5 Bit Offset */
6955 #define RSTCTL_SOFTRESET_STAT_SRC5               ((uint32_t)0x00000020)          /*!< If 1, indicates that SRC5 was the source of the Soft Reset */
6956 /* RSTCTL_SOFTRESET_STAT[SRC6] Bits */
6957 #define RSTCTL_SOFTRESET_STAT_SRC6_OFS           ( 6)                            /*!< SRC6 Bit Offset */
6958 #define RSTCTL_SOFTRESET_STAT_SRC6               ((uint32_t)0x00000040)          /*!< If 1, indicates that SRC6 was the source of the Soft Reset */
6959 /* RSTCTL_SOFTRESET_STAT[SRC7] Bits */
6960 #define RSTCTL_SOFTRESET_STAT_SRC7_OFS           ( 7)                            /*!< SRC7 Bit Offset */
6961 #define RSTCTL_SOFTRESET_STAT_SRC7               ((uint32_t)0x00000080)          /*!< If 1, indicates that SRC7 was the source of the Soft Reset */
6962 /* RSTCTL_SOFTRESET_STAT[SRC8] Bits */
6963 #define RSTCTL_SOFTRESET_STAT_SRC8_OFS           ( 8)                            /*!< SRC8 Bit Offset */
6964 #define RSTCTL_SOFTRESET_STAT_SRC8               ((uint32_t)0x00000100)          /*!< If 1, indicates that SRC8 was the source of the Soft Reset */
6965 /* RSTCTL_SOFTRESET_STAT[SRC9] Bits */
6966 #define RSTCTL_SOFTRESET_STAT_SRC9_OFS           ( 9)                            /*!< SRC9 Bit Offset */
6967 #define RSTCTL_SOFTRESET_STAT_SRC9               ((uint32_t)0x00000200)          /*!< If 1, indicates that SRC9 was the source of the Soft Reset */
6968 /* RSTCTL_SOFTRESET_STAT[SRC10] Bits */
6969 #define RSTCTL_SOFTRESET_STAT_SRC10_OFS          (10)                            /*!< SRC10 Bit Offset */
6970 #define RSTCTL_SOFTRESET_STAT_SRC10              ((uint32_t)0x00000400)          /*!< If 1, indicates that SRC10 was the source of the Soft Reset */
6971 /* RSTCTL_SOFTRESET_STAT[SRC11] Bits */
6972 #define RSTCTL_SOFTRESET_STAT_SRC11_OFS          (11)                            /*!< SRC11 Bit Offset */
6973 #define RSTCTL_SOFTRESET_STAT_SRC11              ((uint32_t)0x00000800)          /*!< If 1, indicates that SRC11 was the source of the Soft Reset */
6974 /* RSTCTL_SOFTRESET_STAT[SRC12] Bits */
6975 #define RSTCTL_SOFTRESET_STAT_SRC12_OFS          (12)                            /*!< SRC12 Bit Offset */
6976 #define RSTCTL_SOFTRESET_STAT_SRC12              ((uint32_t)0x00001000)          /*!< If 1, indicates that SRC12 was the source of the Soft Reset */
6977 /* RSTCTL_SOFTRESET_STAT[SRC13] Bits */
6978 #define RSTCTL_SOFTRESET_STAT_SRC13_OFS          (13)                            /*!< SRC13 Bit Offset */
6979 #define RSTCTL_SOFTRESET_STAT_SRC13              ((uint32_t)0x00002000)          /*!< If 1, indicates that SRC13 was the source of the Soft Reset */
6980 /* RSTCTL_SOFTRESET_STAT[SRC14] Bits */
6981 #define RSTCTL_SOFTRESET_STAT_SRC14_OFS          (14)                            /*!< SRC14 Bit Offset */
6982 #define RSTCTL_SOFTRESET_STAT_SRC14              ((uint32_t)0x00004000)          /*!< If 1, indicates that SRC14 was the source of the Soft Reset */
6983 /* RSTCTL_SOFTRESET_STAT[SRC15] Bits */
6984 #define RSTCTL_SOFTRESET_STAT_SRC15_OFS          (15)                            /*!< SRC15 Bit Offset */
6985 #define RSTCTL_SOFTRESET_STAT_SRC15              ((uint32_t)0x00008000)          /*!< If 1, indicates that SRC15 was the source of the Soft Reset */
6986 /* RSTCTL_SOFTRESET_CLR[SRC0] Bits */
6987 #define RSTCTL_SOFTRESET_CLR_SRC0_OFS            ( 0)                            /*!< SRC0 Bit Offset */
6988 #define RSTCTL_SOFTRESET_CLR_SRC0                ((uint32_t)0x00000001)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
6989 /* RSTCTL_SOFTRESET_CLR[SRC1] Bits */
6990 #define RSTCTL_SOFTRESET_CLR_SRC1_OFS            ( 1)                            /*!< SRC1 Bit Offset */
6991 #define RSTCTL_SOFTRESET_CLR_SRC1                ((uint32_t)0x00000002)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
6992 /* RSTCTL_SOFTRESET_CLR[SRC2] Bits */
6993 #define RSTCTL_SOFTRESET_CLR_SRC2_OFS            ( 2)                            /*!< SRC2 Bit Offset */
6994 #define RSTCTL_SOFTRESET_CLR_SRC2                ((uint32_t)0x00000004)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
6995 /* RSTCTL_SOFTRESET_CLR[SRC3] Bits */
6996 #define RSTCTL_SOFTRESET_CLR_SRC3_OFS            ( 3)                            /*!< SRC3 Bit Offset */
6997 #define RSTCTL_SOFTRESET_CLR_SRC3                ((uint32_t)0x00000008)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
6998 /* RSTCTL_SOFTRESET_CLR[SRC4] Bits */
6999 #define RSTCTL_SOFTRESET_CLR_SRC4_OFS            ( 4)                            /*!< SRC4 Bit Offset */
7000 #define RSTCTL_SOFTRESET_CLR_SRC4                ((uint32_t)0x00000010)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7001 /* RSTCTL_SOFTRESET_CLR[SRC5] Bits */
7002 #define RSTCTL_SOFTRESET_CLR_SRC5_OFS            ( 5)                            /*!< SRC5 Bit Offset */
7003 #define RSTCTL_SOFTRESET_CLR_SRC5                ((uint32_t)0x00000020)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7004 /* RSTCTL_SOFTRESET_CLR[SRC6] Bits */
7005 #define RSTCTL_SOFTRESET_CLR_SRC6_OFS            ( 6)                            /*!< SRC6 Bit Offset */
7006 #define RSTCTL_SOFTRESET_CLR_SRC6                ((uint32_t)0x00000040)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7007 /* RSTCTL_SOFTRESET_CLR[SRC7] Bits */
7008 #define RSTCTL_SOFTRESET_CLR_SRC7_OFS            ( 7)                            /*!< SRC7 Bit Offset */
7009 #define RSTCTL_SOFTRESET_CLR_SRC7                ((uint32_t)0x00000080)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7010 /* RSTCTL_SOFTRESET_CLR[SRC8] Bits */
7011 #define RSTCTL_SOFTRESET_CLR_SRC8_OFS            ( 8)                            /*!< SRC8 Bit Offset */
7012 #define RSTCTL_SOFTRESET_CLR_SRC8                ((uint32_t)0x00000100)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7013 /* RSTCTL_SOFTRESET_CLR[SRC9] Bits */
7014 #define RSTCTL_SOFTRESET_CLR_SRC9_OFS            ( 9)                            /*!< SRC9 Bit Offset */
7015 #define RSTCTL_SOFTRESET_CLR_SRC9                ((uint32_t)0x00000200)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7016 /* RSTCTL_SOFTRESET_CLR[SRC10] Bits */
7017 #define RSTCTL_SOFTRESET_CLR_SRC10_OFS           (10)                            /*!< SRC10 Bit Offset */
7018 #define RSTCTL_SOFTRESET_CLR_SRC10               ((uint32_t)0x00000400)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7019 /* RSTCTL_SOFTRESET_CLR[SRC11] Bits */
7020 #define RSTCTL_SOFTRESET_CLR_SRC11_OFS           (11)                            /*!< SRC11 Bit Offset */
7021 #define RSTCTL_SOFTRESET_CLR_SRC11               ((uint32_t)0x00000800)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7022 /* RSTCTL_SOFTRESET_CLR[SRC12] Bits */
7023 #define RSTCTL_SOFTRESET_CLR_SRC12_OFS           (12)                            /*!< SRC12 Bit Offset */
7024 #define RSTCTL_SOFTRESET_CLR_SRC12               ((uint32_t)0x00001000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7025 /* RSTCTL_SOFTRESET_CLR[SRC13] Bits */
7026 #define RSTCTL_SOFTRESET_CLR_SRC13_OFS           (13)                            /*!< SRC13 Bit Offset */
7027 #define RSTCTL_SOFTRESET_CLR_SRC13               ((uint32_t)0x00002000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7028 /* RSTCTL_SOFTRESET_CLR[SRC14] Bits */
7029 #define RSTCTL_SOFTRESET_CLR_SRC14_OFS           (14)                            /*!< SRC14 Bit Offset */
7030 #define RSTCTL_SOFTRESET_CLR_SRC14               ((uint32_t)0x00004000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7031 /* RSTCTL_SOFTRESET_CLR[SRC15] Bits */
7032 #define RSTCTL_SOFTRESET_CLR_SRC15_OFS           (15)                            /*!< SRC15 Bit Offset */
7033 #define RSTCTL_SOFTRESET_CLR_SRC15               ((uint32_t)0x00008000)          /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */
7034 /* RSTCTL_SOFTRESET_SET[SRC0] Bits */
7035 #define RSTCTL_SOFTRESET_SET_SRC0_OFS            ( 0)                            /*!< SRC0 Bit Offset */
7036 #define RSTCTL_SOFTRESET_SET_SRC0                ((uint32_t)0x00000001)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7037                                                                                  /* initiates a Soft Reset) */
7038 /* RSTCTL_SOFTRESET_SET[SRC1] Bits */
7039 #define RSTCTL_SOFTRESET_SET_SRC1_OFS            ( 1)                            /*!< SRC1 Bit Offset */
7040 #define RSTCTL_SOFTRESET_SET_SRC1                ((uint32_t)0x00000002)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7041                                                                                  /* initiates a Soft Reset) */
7042 /* RSTCTL_SOFTRESET_SET[SRC2] Bits */
7043 #define RSTCTL_SOFTRESET_SET_SRC2_OFS            ( 2)                            /*!< SRC2 Bit Offset */
7044 #define RSTCTL_SOFTRESET_SET_SRC2                ((uint32_t)0x00000004)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7045                                                                                  /* initiates a Soft Reset) */
7046 /* RSTCTL_SOFTRESET_SET[SRC3] Bits */
7047 #define RSTCTL_SOFTRESET_SET_SRC3_OFS            ( 3)                            /*!< SRC3 Bit Offset */
7048 #define RSTCTL_SOFTRESET_SET_SRC3                ((uint32_t)0x00000008)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7049                                                                                  /* initiates a Soft Reset) */
7050 /* RSTCTL_SOFTRESET_SET[SRC4] Bits */
7051 #define RSTCTL_SOFTRESET_SET_SRC4_OFS            ( 4)                            /*!< SRC4 Bit Offset */
7052 #define RSTCTL_SOFTRESET_SET_SRC4                ((uint32_t)0x00000010)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7053                                                                                  /* initiates a Soft Reset) */
7054 /* RSTCTL_SOFTRESET_SET[SRC5] Bits */
7055 #define RSTCTL_SOFTRESET_SET_SRC5_OFS            ( 5)                            /*!< SRC5 Bit Offset */
7056 #define RSTCTL_SOFTRESET_SET_SRC5                ((uint32_t)0x00000020)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7057                                                                                  /* initiates a Soft Reset) */
7058 /* RSTCTL_SOFTRESET_SET[SRC6] Bits */
7059 #define RSTCTL_SOFTRESET_SET_SRC6_OFS            ( 6)                            /*!< SRC6 Bit Offset */
7060 #define RSTCTL_SOFTRESET_SET_SRC6                ((uint32_t)0x00000040)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7061                                                                                  /* initiates a Soft Reset) */
7062 /* RSTCTL_SOFTRESET_SET[SRC7] Bits */
7063 #define RSTCTL_SOFTRESET_SET_SRC7_OFS            ( 7)                            /*!< SRC7 Bit Offset */
7064 #define RSTCTL_SOFTRESET_SET_SRC7                ((uint32_t)0x00000080)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7065                                                                                  /* initiates a Soft Reset) */
7066 /* RSTCTL_SOFTRESET_SET[SRC8] Bits */
7067 #define RSTCTL_SOFTRESET_SET_SRC8_OFS            ( 8)                            /*!< SRC8 Bit Offset */
7068 #define RSTCTL_SOFTRESET_SET_SRC8                ((uint32_t)0x00000100)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7069                                                                                  /* initiates a Soft Reset) */
7070 /* RSTCTL_SOFTRESET_SET[SRC9] Bits */
7071 #define RSTCTL_SOFTRESET_SET_SRC9_OFS            ( 9)                            /*!< SRC9 Bit Offset */
7072 #define RSTCTL_SOFTRESET_SET_SRC9                ((uint32_t)0x00000200)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7073                                                                                  /* initiates a Soft Reset) */
7074 /* RSTCTL_SOFTRESET_SET[SRC10] Bits */
7075 #define RSTCTL_SOFTRESET_SET_SRC10_OFS           (10)                            /*!< SRC10 Bit Offset */
7076 #define RSTCTL_SOFTRESET_SET_SRC10               ((uint32_t)0x00000400)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7077                                                                                  /* initiates a Soft Reset) */
7078 /* RSTCTL_SOFTRESET_SET[SRC11] Bits */
7079 #define RSTCTL_SOFTRESET_SET_SRC11_OFS           (11)                            /*!< SRC11 Bit Offset */
7080 #define RSTCTL_SOFTRESET_SET_SRC11               ((uint32_t)0x00000800)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7081                                                                                  /* initiates a Soft Reset) */
7082 /* RSTCTL_SOFTRESET_SET[SRC12] Bits */
7083 #define RSTCTL_SOFTRESET_SET_SRC12_OFS           (12)                            /*!< SRC12 Bit Offset */
7084 #define RSTCTL_SOFTRESET_SET_SRC12               ((uint32_t)0x00001000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7085                                                                                  /* initiates a Soft Reset) */
7086 /* RSTCTL_SOFTRESET_SET[SRC13] Bits */
7087 #define RSTCTL_SOFTRESET_SET_SRC13_OFS           (13)                            /*!< SRC13 Bit Offset */
7088 #define RSTCTL_SOFTRESET_SET_SRC13               ((uint32_t)0x00002000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7089                                                                                  /* initiates a Soft Reset) */
7090 /* RSTCTL_SOFTRESET_SET[SRC14] Bits */
7091 #define RSTCTL_SOFTRESET_SET_SRC14_OFS           (14)                            /*!< SRC14 Bit Offset */
7092 #define RSTCTL_SOFTRESET_SET_SRC14               ((uint32_t)0x00004000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7093                                                                                  /* initiates a Soft Reset) */
7094 /* RSTCTL_SOFTRESET_SET[SRC15] Bits */
7095 #define RSTCTL_SOFTRESET_SET_SRC15_OFS           (15)                            /*!< SRC15 Bit Offset */
7096 #define RSTCTL_SOFTRESET_SET_SRC15               ((uint32_t)0x00008000)          /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and  */
7097                                                                                  /* initiates a Soft Reset) */
7098 /* RSTCTL_PSSRESET_STAT[SVSMH] Bits */
7099 #define RSTCTL_PSSRESET_STAT_SVSMH_OFS           ( 1)                            /*!< SVSMH Bit Offset */
7100 #define RSTCTL_PSSRESET_STAT_SVSMH               ((uint32_t)0x00000002)          /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */
7101 /* RSTCTL_PSSRESET_STAT[BGREF] Bits */
7102 #define RSTCTL_PSSRESET_STAT_BGREF_OFS           ( 2)                            /*!< BGREF Bit Offset */
7103 #define RSTCTL_PSSRESET_STAT_BGREF               ((uint32_t)0x00000004)          /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */
7104 /* RSTCTL_PSSRESET_STAT[VCCDET] Bits */
7105 #define RSTCTL_PSSRESET_STAT_VCCDET_OFS          ( 3)                            /*!< VCCDET Bit Offset */
7106 #define RSTCTL_PSSRESET_STAT_VCCDET              ((uint32_t)0x00000008)          /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */
7107 /* RSTCTL_PSSRESET_CLR[CLR] Bits */
7108 #define RSTCTL_PSSRESET_CLR_CLR_OFS              ( 0)                            /*!< CLR Bit Offset */
7109 #define RSTCTL_PSSRESET_CLR_CLR                  ((uint32_t)0x00000001)          /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */
7110 /* RSTCTL_PCMRESET_STAT[LPM35] Bits */
7111 #define RSTCTL_PCMRESET_STAT_LPM35_OFS           ( 0)                            /*!< LPM35 Bit Offset */
7112 #define RSTCTL_PCMRESET_STAT_LPM35               ((uint32_t)0x00000001)          /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */
7113 /* RSTCTL_PCMRESET_STAT[LPM45] Bits */
7114 #define RSTCTL_PCMRESET_STAT_LPM45_OFS           ( 1)                            /*!< LPM45 Bit Offset */
7115 #define RSTCTL_PCMRESET_STAT_LPM45               ((uint32_t)0x00000002)          /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */
7116 /* RSTCTL_PCMRESET_CLR[CLR] Bits */
7117 #define RSTCTL_PCMRESET_CLR_CLR_OFS              ( 0)                            /*!< CLR Bit Offset */
7118 #define RSTCTL_PCMRESET_CLR_CLR                  ((uint32_t)0x00000001)          /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */
7119 /* RSTCTL_PINRESET_STAT[RSTNMI] Bits */
7120 #define RSTCTL_PINRESET_STAT_RSTNMI_OFS          ( 0)                            /*!< RSTNMI Bit Offset */
7121 #define RSTCTL_PINRESET_STAT_RSTNMI              ((uint32_t)0x00000001)          /*!< POR was caused by RSTn/NMI pin based reset event */
7122 /* RSTCTL_PINRESET_CLR[CLR] Bits */
7123 #define RSTCTL_PINRESET_CLR_CLR_OFS              ( 0)                            /*!< CLR Bit Offset */
7124 #define RSTCTL_PINRESET_CLR_CLR                  ((uint32_t)0x00000001)          /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */
7125 /* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */
7126 #define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS       ( 0)                            /*!< REBOOT Bit Offset */
7127 #define RSTCTL_REBOOTRESET_STAT_REBOOT           ((uint32_t)0x00000001)          /*!< Indicates if Reboot reset was caused by the SYSCTL module. */
7128 /* RSTCTL_REBOOTRESET_CLR[CLR] Bits */
7129 #define RSTCTL_REBOOTRESET_CLR_CLR_OFS           ( 0)                            /*!< CLR Bit Offset */
7130 #define RSTCTL_REBOOTRESET_CLR_CLR               ((uint32_t)0x00000001)          /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */
7131 /* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */
7132 #define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS         ( 0)                            /*!< DCOR_SHT Bit Offset */
7133 #define RSTCTL_CSRESET_STAT_DCOR_SHT             ((uint32_t)0x00000001)          /*!< Indicates if POR was caused by DCO short circuit fault in the external  */
7134                                                                                  /* resistor mode */
7135 /* RSTCTL_CSRESET_CLR[CLR] Bits */
7136 #define RSTCTL_CSRESET_CLR_CLR_OFS               ( 0)                            /*!< CLR Bit Offset */
7137 #define RSTCTL_CSRESET_CLR_CLR                   ((uint32_t)0x00000001)          /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as  */
7138                                                                                  /* DCOR_SHTIFG flag in CSIFG register of clock system */
7139 /* Pre-defined bitfield values */
7140 #define RSTCTL_RESETREQ_RSTKEY_VAL                 ((uint32_t)0x00006900)          /*!< Key value to enable writes to bits 1-0 */
7141 
7142 
7143 /******************************************************************************
7144 * RTC_C Bits
7145 ******************************************************************************/
7146 /* RTC_C_CTL0[RDYIFG] Bits */
7147 #define RTC_C_CTL0_RDYIFG_OFS                    ( 0)                            /*!< RTCRDYIFG Bit Offset */
7148 #define RTC_C_CTL0_RDYIFG                        ((uint16_t)0x0001)              /*!< Real-time clock ready interrupt flag */
7149 /* RTC_C_CTL0[AIFG] Bits */
7150 #define RTC_C_CTL0_AIFG_OFS                      ( 1)                            /*!< RTCAIFG Bit Offset */
7151 #define RTC_C_CTL0_AIFG                          ((uint16_t)0x0002)              /*!< Real-time clock alarm interrupt flag */
7152 /* RTC_C_CTL0[TEVIFG] Bits */
7153 #define RTC_C_CTL0_TEVIFG_OFS                    ( 2)                            /*!< RTCTEVIFG Bit Offset */
7154 #define RTC_C_CTL0_TEVIFG                        ((uint16_t)0x0004)              /*!< Real-time clock time event interrupt flag */
7155 /* RTC_C_CTL0[OFIFG] Bits */
7156 #define RTC_C_CTL0_OFIFG_OFS                     ( 3)                            /*!< RTCOFIFG Bit Offset */
7157 #define RTC_C_CTL0_OFIFG                         ((uint16_t)0x0008)              /*!< 32-kHz crystal oscillator fault interrupt flag */
7158 /* RTC_C_CTL0[RDYIE] Bits */
7159 #define RTC_C_CTL0_RDYIE_OFS                     ( 4)                            /*!< RTCRDYIE Bit Offset */
7160 #define RTC_C_CTL0_RDYIE                         ((uint16_t)0x0010)              /*!< Real-time clock ready interrupt enable */
7161 /* RTC_C_CTL0[AIE] Bits */
7162 #define RTC_C_CTL0_AIE_OFS                       ( 5)                            /*!< RTCAIE Bit Offset */
7163 #define RTC_C_CTL0_AIE                           ((uint16_t)0x0020)              /*!< Real-time clock alarm interrupt enable */
7164 /* RTC_C_CTL0[TEVIE] Bits */
7165 #define RTC_C_CTL0_TEVIE_OFS                     ( 6)                            /*!< RTCTEVIE Bit Offset */
7166 #define RTC_C_CTL0_TEVIE                         ((uint16_t)0x0040)              /*!< Real-time clock time event interrupt enable */
7167 /* RTC_C_CTL0[OFIE] Bits */
7168 #define RTC_C_CTL0_OFIE_OFS                      ( 7)                            /*!< RTCOFIE Bit Offset */
7169 #define RTC_C_CTL0_OFIE                          ((uint16_t)0x0080)              /*!< 32-kHz crystal oscillator fault interrupt enable */
7170 /* RTC_C_CTL0[KEY] Bits */
7171 #define RTC_C_CTL0_KEY_OFS                       ( 8)                            /*!< RTCKEY Bit Offset */
7172 #define RTC_C_CTL0_KEY_MASK                      ((uint16_t)0xFF00)              /*!< RTCKEY Bit Mask */
7173 /* RTC_C_CTL13[TEV] Bits */
7174 #define RTC_C_CTL13_TEV_OFS                      ( 0)                            /*!< RTCTEV Bit Offset */
7175 #define RTC_C_CTL13_TEV_MASK                     ((uint16_t)0x0003)              /*!< RTCTEV Bit Mask */
7176 #define RTC_C_CTL13_TEV0                         ((uint16_t)0x0001)              /*!< TEV Bit 0 */
7177 #define RTC_C_CTL13_TEV1                         ((uint16_t)0x0002)              /*!< TEV Bit 1 */
7178 #define RTC_C_CTL13_TEV_0                        ((uint16_t)0x0000)              /*!< Minute changed */
7179 #define RTC_C_CTL13_TEV_1                        ((uint16_t)0x0001)              /*!< Hour changed */
7180 #define RTC_C_CTL13_TEV_2                        ((uint16_t)0x0002)              /*!< Every day at midnight (00:00) */
7181 #define RTC_C_CTL13_TEV_3                        ((uint16_t)0x0003)              /*!< Every day at noon (12:00) */
7182 /* RTC_C_CTL13[SSEL] Bits */
7183 #define RTC_C_CTL13_SSEL_OFS                     ( 2)                            /*!< RTCSSEL Bit Offset */
7184 #define RTC_C_CTL13_SSEL_MASK                    ((uint16_t)0x000C)              /*!< RTCSSEL Bit Mask */
7185 #define RTC_C_CTL13_SSEL0                        ((uint16_t)0x0004)              /*!< SSEL Bit 0 */
7186 #define RTC_C_CTL13_SSEL1                        ((uint16_t)0x0008)              /*!< SSEL Bit 1 */
7187 #define RTC_C_CTL13_SSEL_0                       ((uint16_t)0x0000)              /*!< BCLK */
7188 #define RTC_C_CTL13_SSEL__BCLK                   ((uint16_t)0x0000)              /*!< BCLK */
7189 /* RTC_C_CTL13[RDY] Bits */
7190 #define RTC_C_CTL13_RDY_OFS                      ( 4)                            /*!< RTCRDY Bit Offset */
7191 #define RTC_C_CTL13_RDY                          ((uint16_t)0x0010)              /*!< Real-time clock ready */
7192 /* RTC_C_CTL13[MODE] Bits */
7193 #define RTC_C_CTL13_MODE_OFS                     ( 5)                            /*!< RTCMODE Bit Offset */
7194 #define RTC_C_CTL13_MODE                         ((uint16_t)0x0020)
7195 /* RTC_C_CTL13[HOLD] Bits */
7196 #define RTC_C_CTL13_HOLD_OFS                     ( 6)                            /*!< RTCHOLD Bit Offset */
7197 #define RTC_C_CTL13_HOLD                         ((uint16_t)0x0040)              /*!< Real-time clock hold */
7198 /* RTC_C_CTL13[BCD] Bits */
7199 #define RTC_C_CTL13_BCD_OFS                      ( 7)                            /*!< RTCBCD Bit Offset */
7200 #define RTC_C_CTL13_BCD                          ((uint16_t)0x0080)              /*!< Real-time clock BCD select */
7201 /* RTC_C_CTL13[CALF] Bits */
7202 #define RTC_C_CTL13_CALF_OFS                     ( 8)                            /*!< RTCCALF Bit Offset */
7203 #define RTC_C_CTL13_CALF_MASK                    ((uint16_t)0x0300)              /*!< RTCCALF Bit Mask */
7204 #define RTC_C_CTL13_CALF0                        ((uint16_t)0x0100)              /*!< CALF Bit 0 */
7205 #define RTC_C_CTL13_CALF1                        ((uint16_t)0x0200)              /*!< CALF Bit 1 */
7206 #define RTC_C_CTL13_CALF_0                       ((uint16_t)0x0000)              /*!< No frequency output to RTCCLK pin */
7207 #define RTC_C_CTL13_CALF_1                       ((uint16_t)0x0100)              /*!< 512 Hz */
7208 #define RTC_C_CTL13_CALF_2                       ((uint16_t)0x0200)              /*!< 256 Hz */
7209 #define RTC_C_CTL13_CALF_3                       ((uint16_t)0x0300)              /*!< 1 Hz */
7210 #define RTC_C_CTL13_CALF__NONE                   ((uint16_t)0x0000)              /*!< No frequency output to RTCCLK pin */
7211 #define RTC_C_CTL13_CALF__512                    ((uint16_t)0x0100)              /*!< 512 Hz */
7212 #define RTC_C_CTL13_CALF__256                    ((uint16_t)0x0200)              /*!< 256 Hz */
7213 #define RTC_C_CTL13_CALF__1                      ((uint16_t)0x0300)              /*!< 1 Hz */
7214 /* RTC_C_OCAL[OCAL] Bits */
7215 #define RTC_C_OCAL_OCAL_OFS                      ( 0)                            /*!< RTCOCAL Bit Offset */
7216 #define RTC_C_OCAL_OCAL_MASK                     ((uint16_t)0x00FF)              /*!< RTCOCAL Bit Mask */
7217 /* RTC_C_OCAL[OCALS] Bits */
7218 #define RTC_C_OCAL_OCALS_OFS                     (15)                            /*!< RTCOCALS Bit Offset */
7219 #define RTC_C_OCAL_OCALS                         ((uint16_t)0x8000)              /*!< Real-time clock offset error calibration sign */
7220 /* RTC_C_TCMP[TCMPx] Bits */
7221 #define RTC_C_TCMP_TCMPX_OFS                     ( 0)                            /*!< RTCTCMP Bit Offset */
7222 #define RTC_C_TCMP_TCMPX_MASK                    ((uint16_t)0x00FF)              /*!< RTCTCMP Bit Mask */
7223 /* RTC_C_TCMP[TCOK] Bits */
7224 #define RTC_C_TCMP_TCOK_OFS                      (13)                            /*!< RTCTCOK Bit Offset */
7225 #define RTC_C_TCMP_TCOK                          ((uint16_t)0x2000)              /*!< Real-time clock temperature compensation write OK */
7226 /* RTC_C_TCMP[TCRDY] Bits */
7227 #define RTC_C_TCMP_TCRDY_OFS                     (14)                            /*!< RTCTCRDY Bit Offset */
7228 #define RTC_C_TCMP_TCRDY                         ((uint16_t)0x4000)              /*!< Real-time clock temperature compensation ready */
7229 /* RTC_C_TCMP[TCMPS] Bits */
7230 #define RTC_C_TCMP_TCMPS_OFS                     (15)                            /*!< RTCTCMPS Bit Offset */
7231 #define RTC_C_TCMP_TCMPS                         ((uint16_t)0x8000)              /*!< Real-time clock temperature compensation sign */
7232 /* RTC_C_PS0CTL[RT0PSIFG] Bits */
7233 #define RTC_C_PS0CTL_RT0PSIFG_OFS                ( 0)                            /*!< RT0PSIFG Bit Offset */
7234 #define RTC_C_PS0CTL_RT0PSIFG                    ((uint16_t)0x0001)              /*!< Prescale timer 0 interrupt flag */
7235 /* RTC_C_PS0CTL[RT0PSIE] Bits */
7236 #define RTC_C_PS0CTL_RT0PSIE_OFS                 ( 1)                            /*!< RT0PSIE Bit Offset */
7237 #define RTC_C_PS0CTL_RT0PSIE                     ((uint16_t)0x0002)              /*!< Prescale timer 0 interrupt enable */
7238 /* RTC_C_PS0CTL[RT0IP] Bits */
7239 #define RTC_C_PS0CTL_RT0IP_OFS                   ( 2)                            /*!< RT0IP Bit Offset */
7240 #define RTC_C_PS0CTL_RT0IP_MASK                  ((uint16_t)0x001C)              /*!< RT0IP Bit Mask */
7241 #define RTC_C_PS0CTL_RT0IP0                      ((uint16_t)0x0004)              /*!< RT0IP Bit 0 */
7242 #define RTC_C_PS0CTL_RT0IP1                      ((uint16_t)0x0008)              /*!< RT0IP Bit 1 */
7243 #define RTC_C_PS0CTL_RT0IP2                      ((uint16_t)0x0010)              /*!< RT0IP Bit 2 */
7244 #define RTC_C_PS0CTL_RT0IP_0                     ((uint16_t)0x0000)              /*!< Divide by 2 */
7245 #define RTC_C_PS0CTL_RT0IP_1                     ((uint16_t)0x0004)              /*!< Divide by 4 */
7246 #define RTC_C_PS0CTL_RT0IP_2                     ((uint16_t)0x0008)              /*!< Divide by 8 */
7247 #define RTC_C_PS0CTL_RT0IP_3                     ((uint16_t)0x000C)              /*!< Divide by 16 */
7248 #define RTC_C_PS0CTL_RT0IP_4                     ((uint16_t)0x0010)              /*!< Divide by 32 */
7249 #define RTC_C_PS0CTL_RT0IP_5                     ((uint16_t)0x0014)              /*!< Divide by 64 */
7250 #define RTC_C_PS0CTL_RT0IP_6                     ((uint16_t)0x0018)              /*!< Divide by 128 */
7251 #define RTC_C_PS0CTL_RT0IP_7                     ((uint16_t)0x001C)              /*!< Divide by 256 */
7252 #define RTC_C_PS0CTL_RT0IP__2                    ((uint16_t)0x0000)              /*!< Divide by 2 */
7253 #define RTC_C_PS0CTL_RT0IP__4                    ((uint16_t)0x0004)              /*!< Divide by 4 */
7254 #define RTC_C_PS0CTL_RT0IP__8                    ((uint16_t)0x0008)              /*!< Divide by 8 */
7255 #define RTC_C_PS0CTL_RT0IP__16                   ((uint16_t)0x000C)              /*!< Divide by 16 */
7256 #define RTC_C_PS0CTL_RT0IP__32                   ((uint16_t)0x0010)              /*!< Divide by 32 */
7257 #define RTC_C_PS0CTL_RT0IP__64                   ((uint16_t)0x0014)              /*!< Divide by 64 */
7258 #define RTC_C_PS0CTL_RT0IP__128                  ((uint16_t)0x0018)              /*!< Divide by 128 */
7259 #define RTC_C_PS0CTL_RT0IP__256                  ((uint16_t)0x001C)              /*!< Divide by 256 */
7260 /* RTC_C_PS1CTL[RT1PSIFG] Bits */
7261 #define RTC_C_PS1CTL_RT1PSIFG_OFS                ( 0)                            /*!< RT1PSIFG Bit Offset */
7262 #define RTC_C_PS1CTL_RT1PSIFG                    ((uint16_t)0x0001)              /*!< Prescale timer 1 interrupt flag */
7263 /* RTC_C_PS1CTL[RT1PSIE] Bits */
7264 #define RTC_C_PS1CTL_RT1PSIE_OFS                 ( 1)                            /*!< RT1PSIE Bit Offset */
7265 #define RTC_C_PS1CTL_RT1PSIE                     ((uint16_t)0x0002)              /*!< Prescale timer 1 interrupt enable */
7266 /* RTC_C_PS1CTL[RT1IP] Bits */
7267 #define RTC_C_PS1CTL_RT1IP_OFS                   ( 2)                            /*!< RT1IP Bit Offset */
7268 #define RTC_C_PS1CTL_RT1IP_MASK                  ((uint16_t)0x001C)              /*!< RT1IP Bit Mask */
7269 #define RTC_C_PS1CTL_RT1IP0                      ((uint16_t)0x0004)              /*!< RT1IP Bit 0 */
7270 #define RTC_C_PS1CTL_RT1IP1                      ((uint16_t)0x0008)              /*!< RT1IP Bit 1 */
7271 #define RTC_C_PS1CTL_RT1IP2                      ((uint16_t)0x0010)              /*!< RT1IP Bit 2 */
7272 #define RTC_C_PS1CTL_RT1IP_0                     ((uint16_t)0x0000)              /*!< Divide by 2 */
7273 #define RTC_C_PS1CTL_RT1IP_1                     ((uint16_t)0x0004)              /*!< Divide by 4 */
7274 #define RTC_C_PS1CTL_RT1IP_2                     ((uint16_t)0x0008)              /*!< Divide by 8 */
7275 #define RTC_C_PS1CTL_RT1IP_3                     ((uint16_t)0x000C)              /*!< Divide by 16 */
7276 #define RTC_C_PS1CTL_RT1IP_4                     ((uint16_t)0x0010)              /*!< Divide by 32 */
7277 #define RTC_C_PS1CTL_RT1IP_5                     ((uint16_t)0x0014)              /*!< Divide by 64 */
7278 #define RTC_C_PS1CTL_RT1IP_6                     ((uint16_t)0x0018)              /*!< Divide by 128 */
7279 #define RTC_C_PS1CTL_RT1IP_7                     ((uint16_t)0x001C)              /*!< Divide by 256 */
7280 #define RTC_C_PS1CTL_RT1IP__2                    ((uint16_t)0x0000)              /*!< Divide by 2 */
7281 #define RTC_C_PS1CTL_RT1IP__4                    ((uint16_t)0x0004)              /*!< Divide by 4 */
7282 #define RTC_C_PS1CTL_RT1IP__8                    ((uint16_t)0x0008)              /*!< Divide by 8 */
7283 #define RTC_C_PS1CTL_RT1IP__16                   ((uint16_t)0x000C)              /*!< Divide by 16 */
7284 #define RTC_C_PS1CTL_RT1IP__32                   ((uint16_t)0x0010)              /*!< Divide by 32 */
7285 #define RTC_C_PS1CTL_RT1IP__64                   ((uint16_t)0x0014)              /*!< Divide by 64 */
7286 #define RTC_C_PS1CTL_RT1IP__128                  ((uint16_t)0x0018)              /*!< Divide by 128 */
7287 #define RTC_C_PS1CTL_RT1IP__256                  ((uint16_t)0x001C)              /*!< Divide by 256 */
7288 /* RTC_C_PS[RT0PS] Bits */
7289 #define RTC_C_PS_RT0PS_OFS                       ( 0)                            /*!< RT0PS Bit Offset */
7290 #define RTC_C_PS_RT0PS_MASK                      ((uint16_t)0x00FF)              /*!< RT0PS Bit Mask */
7291 /* RTC_C_PS[RT1PS] Bits */
7292 #define RTC_C_PS_RT1PS_OFS                       ( 8)                            /*!< RT1PS Bit Offset */
7293 #define RTC_C_PS_RT1PS_MASK                      ((uint16_t)0xFF00)              /*!< RT1PS Bit Mask */
7294 /* RTC_C_TIM0[SEC] Bits */
7295 #define RTC_C_TIM0_SEC_OFS                       ( 0)                            /*!< Seconds Bit Offset */
7296 #define RTC_C_TIM0_SEC_MASK                      ((uint16_t)0x003F)              /*!< Seconds Bit Mask */
7297 /* RTC_C_TIM0[MIN] Bits */
7298 #define RTC_C_TIM0_MIN_OFS                       ( 8)                            /*!< Minutes Bit Offset */
7299 #define RTC_C_TIM0_MIN_MASK                      ((uint16_t)0x3F00)              /*!< Minutes Bit Mask */
7300 /* RTC_C_TIM0[SEC_LD] Bits */
7301 #define RTC_C_TIM0_SEC_LD_OFS                    ( 0)                            /*!< SecondsLowDigit Bit Offset */
7302 #define RTC_C_TIM0_SEC_LD_MASK                   ((uint16_t)0x000F)              /*!< SecondsLowDigit Bit Mask */
7303 /* RTC_C_TIM0[SEC_HD] Bits */
7304 #define RTC_C_TIM0_SEC_HD_OFS                    ( 4)                            /*!< SecondsHighDigit Bit Offset */
7305 #define RTC_C_TIM0_SEC_HD_MASK                   ((uint16_t)0x0070)              /*!< SecondsHighDigit Bit Mask */
7306 /* RTC_C_TIM0[MIN_LD] Bits */
7307 #define RTC_C_TIM0_MIN_LD_OFS                    ( 8)                            /*!< MinutesLowDigit Bit Offset */
7308 #define RTC_C_TIM0_MIN_LD_MASK                   ((uint16_t)0x0F00)              /*!< MinutesLowDigit Bit Mask */
7309 /* RTC_C_TIM0[MIN_HD] Bits */
7310 #define RTC_C_TIM0_MIN_HD_OFS                    (12)                            /*!< MinutesHighDigit Bit Offset */
7311 #define RTC_C_TIM0_MIN_HD_MASK                   ((uint16_t)0x7000)              /*!< MinutesHighDigit Bit Mask */
7312 /* RTC_C_TIM1[HOUR] Bits */
7313 #define RTC_C_TIM1_HOUR_OFS                      ( 0)                            /*!< Hours Bit Offset */
7314 #define RTC_C_TIM1_HOUR_MASK                     ((uint16_t)0x001F)              /*!< Hours Bit Mask */
7315 /* RTC_C_TIM1[DOW] Bits */
7316 #define RTC_C_TIM1_DOW_OFS                       ( 8)                            /*!< DayofWeek Bit Offset */
7317 #define RTC_C_TIM1_DOW_MASK                      ((uint16_t)0x0700)              /*!< DayofWeek Bit Mask */
7318 /* RTC_C_TIM1[HOUR_LD] Bits */
7319 #define RTC_C_TIM1_HOUR_LD_OFS                   ( 0)                            /*!< HoursLowDigit Bit Offset */
7320 #define RTC_C_TIM1_HOUR_LD_MASK                  ((uint16_t)0x000F)              /*!< HoursLowDigit Bit Mask */
7321 /* RTC_C_TIM1[HOUR_HD] Bits */
7322 #define RTC_C_TIM1_HOUR_HD_OFS                   ( 4)                            /*!< HoursHighDigit Bit Offset */
7323 #define RTC_C_TIM1_HOUR_HD_MASK                  ((uint16_t)0x0030)              /*!< HoursHighDigit Bit Mask */
7324 /* RTC_C_DATE[DAY] Bits */
7325 #define RTC_C_DATE_DAY_OFS                       ( 0)                            /*!< Day Bit Offset */
7326 #define RTC_C_DATE_DAY_MASK                      ((uint16_t)0x001F)              /*!< Day Bit Mask */
7327 /* RTC_C_DATE[MON] Bits */
7328 #define RTC_C_DATE_MON_OFS                       ( 8)                            /*!< Month Bit Offset */
7329 #define RTC_C_DATE_MON_MASK                      ((uint16_t)0x0F00)              /*!< Month Bit Mask */
7330 /* RTC_C_DATE[DAY_LD] Bits */
7331 #define RTC_C_DATE_DAY_LD_OFS                    ( 0)                            /*!< DayLowDigit Bit Offset */
7332 #define RTC_C_DATE_DAY_LD_MASK                   ((uint16_t)0x000F)              /*!< DayLowDigit Bit Mask */
7333 /* RTC_C_DATE[DAY_HD] Bits */
7334 #define RTC_C_DATE_DAY_HD_OFS                    ( 4)                            /*!< DayHighDigit Bit Offset */
7335 #define RTC_C_DATE_DAY_HD_MASK                   ((uint16_t)0x0030)              /*!< DayHighDigit Bit Mask */
7336 /* RTC_C_DATE[MON_LD] Bits */
7337 #define RTC_C_DATE_MON_LD_OFS                    ( 8)                            /*!< MonthLowDigit Bit Offset */
7338 #define RTC_C_DATE_MON_LD_MASK                   ((uint16_t)0x0F00)              /*!< MonthLowDigit Bit Mask */
7339 /* RTC_C_DATE[MON_HD] Bits */
7340 #define RTC_C_DATE_MON_HD_OFS                    (12)                            /*!< MonthHighDigit Bit Offset */
7341 #define RTC_C_DATE_MON_HD                        ((uint16_t)0x1000)              /*!< Month  high digit (0 or 1) */
7342 /* RTC_C_YEAR[YEAR_LB] Bits */
7343 #define RTC_C_YEAR_YEAR_LB_OFS                   ( 0)                            /*!< YearLowByte Bit Offset */
7344 #define RTC_C_YEAR_YEAR_LB_MASK                  ((uint16_t)0x00FF)              /*!< YearLowByte Bit Mask */
7345 /* RTC_C_YEAR[YEAR_HB] Bits */
7346 #define RTC_C_YEAR_YEAR_HB_OFS                   ( 8)                            /*!< YearHighByte Bit Offset */
7347 #define RTC_C_YEAR_YEAR_HB_MASK                  ((uint16_t)0x0F00)              /*!< YearHighByte Bit Mask */
7348 /* RTC_C_YEAR[YEAR] Bits */
7349 #define RTC_C_YEAR_YEAR_OFS                      ( 0)                            /*!< Year Bit Offset */
7350 #define RTC_C_YEAR_YEAR_MASK                     ((uint16_t)0x000F)              /*!< Year Bit Mask */
7351 /* RTC_C_YEAR[DEC] Bits */
7352 #define RTC_C_YEAR_DEC_OFS                       ( 4)                            /*!< Decade Bit Offset */
7353 #define RTC_C_YEAR_DEC_MASK                      ((uint16_t)0x00F0)              /*!< Decade Bit Mask */
7354 /* RTC_C_YEAR[CENT_LD] Bits */
7355 #define RTC_C_YEAR_CENT_LD_OFS                   ( 8)                            /*!< CenturyLowDigit Bit Offset */
7356 #define RTC_C_YEAR_CENT_LD_MASK                  ((uint16_t)0x0F00)              /*!< CenturyLowDigit Bit Mask */
7357 /* RTC_C_YEAR[CENT_HD] Bits */
7358 #define RTC_C_YEAR_CENT_HD_OFS                   (12)                            /*!< CenturyHighDigit Bit Offset */
7359 #define RTC_C_YEAR_CENT_HD_MASK                  ((uint16_t)0x7000)              /*!< CenturyHighDigit Bit Mask */
7360 /* RTC_C_AMINHR[MIN] Bits */
7361 #define RTC_C_AMINHR_MIN_OFS                     ( 0)                            /*!< Minutes Bit Offset */
7362 #define RTC_C_AMINHR_MIN_MASK                    ((uint16_t)0x003F)              /*!< Minutes Bit Mask */
7363 /* RTC_C_AMINHR[MINAE] Bits */
7364 #define RTC_C_AMINHR_MINAE_OFS                   ( 7)                            /*!< MINAE Bit Offset */
7365 #define RTC_C_AMINHR_MINAE                       ((uint16_t)0x0080)              /*!< Alarm enable */
7366 /* RTC_C_AMINHR[HOUR] Bits */
7367 #define RTC_C_AMINHR_HOUR_OFS                    ( 8)                            /*!< Hours Bit Offset */
7368 #define RTC_C_AMINHR_HOUR_MASK                   ((uint16_t)0x1F00)              /*!< Hours Bit Mask */
7369 /* RTC_C_AMINHR[HOURAE] Bits */
7370 #define RTC_C_AMINHR_HOURAE_OFS                  (15)                            /*!< HOURAE Bit Offset */
7371 #define RTC_C_AMINHR_HOURAE                      ((uint16_t)0x8000)              /*!< Alarm enable */
7372 /* RTC_C_AMINHR[MIN_LD] Bits */
7373 #define RTC_C_AMINHR_MIN_LD_OFS                  ( 0)                            /*!< MinutesLowDigit Bit Offset */
7374 #define RTC_C_AMINHR_MIN_LD_MASK                 ((uint16_t)0x000F)              /*!< MinutesLowDigit Bit Mask */
7375 /* RTC_C_AMINHR[MIN_HD] Bits */
7376 #define RTC_C_AMINHR_MIN_HD_OFS                  ( 4)                            /*!< MinutesHighDigit Bit Offset */
7377 #define RTC_C_AMINHR_MIN_HD_MASK                 ((uint16_t)0x0070)              /*!< MinutesHighDigit Bit Mask */
7378 /* RTC_C_AMINHR[HOUR_LD] Bits */
7379 #define RTC_C_AMINHR_HOUR_LD_OFS                 ( 8)                            /*!< HoursLowDigit Bit Offset */
7380 #define RTC_C_AMINHR_HOUR_LD_MASK                ((uint16_t)0x0F00)              /*!< HoursLowDigit Bit Mask */
7381 /* RTC_C_AMINHR[HOUR_HD] Bits */
7382 #define RTC_C_AMINHR_HOUR_HD_OFS                 (12)                            /*!< HoursHighDigit Bit Offset */
7383 #define RTC_C_AMINHR_HOUR_HD_MASK                ((uint16_t)0x3000)              /*!< HoursHighDigit Bit Mask */
7384 /* RTC_C_ADOWDAY[DOW] Bits */
7385 #define RTC_C_ADOWDAY_DOW_OFS                    ( 0)                            /*!< DayofWeek Bit Offset */
7386 #define RTC_C_ADOWDAY_DOW_MASK                   ((uint16_t)0x0007)              /*!< DayofWeek Bit Mask */
7387 /* RTC_C_ADOWDAY[DOWAE] Bits */
7388 #define RTC_C_ADOWDAY_DOWAE_OFS                  ( 7)                            /*!< DOWAE Bit Offset */
7389 #define RTC_C_ADOWDAY_DOWAE                      ((uint16_t)0x0080)              /*!< Alarm enable */
7390 /* RTC_C_ADOWDAY[DAY] Bits */
7391 #define RTC_C_ADOWDAY_DAY_OFS                    ( 8)                            /*!< DayofMonth Bit Offset */
7392 #define RTC_C_ADOWDAY_DAY_MASK                   ((uint16_t)0x1F00)              /*!< DayofMonth Bit Mask */
7393 /* RTC_C_ADOWDAY[DAYAE] Bits */
7394 #define RTC_C_ADOWDAY_DAYAE_OFS                  (15)                            /*!< DAYAE Bit Offset */
7395 #define RTC_C_ADOWDAY_DAYAE                      ((uint16_t)0x8000)              /*!< Alarm enable */
7396 /* RTC_C_ADOWDAY[DAY_LD] Bits */
7397 #define RTC_C_ADOWDAY_DAY_LD_OFS                 ( 8)                            /*!< DayLowDigit Bit Offset */
7398 #define RTC_C_ADOWDAY_DAY_LD_MASK                ((uint16_t)0x0F00)              /*!< DayLowDigit Bit Mask */
7399 /* RTC_C_ADOWDAY[DAY_HD] Bits */
7400 #define RTC_C_ADOWDAY_DAY_HD_OFS                 (12)                            /*!< DayHighDigit Bit Offset */
7401 #define RTC_C_ADOWDAY_DAY_HD_MASK                ((uint16_t)0x3000)              /*!< DayHighDigit Bit Mask */
7402 /* Pre-defined bitfield values */
7403 #define RTC_C_KEY                                 ((uint16_t)0xA500)              /*!< RTC_C Key Value for RTC_C write access */
7404 #define RTC_C_KEY_H                               ((uint16_t)0x00A5)              /*!< RTC_C Key Value for RTC_C write access */
7405 #define RTC_C_KEY_VAL                             ((uint16_t)0xA500)              /*!< RTC_C Key Value for RTC_C write access */
7406 
7407 
7408 /******************************************************************************
7409 * SCB Bits
7410 ******************************************************************************/
7411 /* SCB_PFR0[STATE0] Bits */
7412 #define SCB_PFR0_STATE0_OFS                      ( 0)                            /*!< STATE0 Bit Offset */
7413 #define SCB_PFR0_STATE0_MASK                     ((uint32_t)0x0000000F)          /*!< STATE0 Bit Mask */
7414 #define SCB_PFR0_STATE00                         ((uint32_t)0x00000001)          /*!< STATE0 Bit 0 */
7415 #define SCB_PFR0_STATE01                         ((uint32_t)0x00000002)          /*!< STATE0 Bit 1 */
7416 #define SCB_PFR0_STATE02                         ((uint32_t)0x00000004)          /*!< STATE0 Bit 2 */
7417 #define SCB_PFR0_STATE03                         ((uint32_t)0x00000008)          /*!< STATE0 Bit 3 */
7418 #define SCB_PFR0_STATE0_0                        ((uint32_t)0x00000000)          /*!< no ARM encoding */
7419 #define SCB_PFR0_STATE0_1                        ((uint32_t)0x00000001)          /*!< N/A */
7420 /* SCB_PFR0[STATE1] Bits */
7421 #define SCB_PFR0_STATE1_OFS                      ( 4)                            /*!< STATE1 Bit Offset */
7422 #define SCB_PFR0_STATE1_MASK                     ((uint32_t)0x000000F0)          /*!< STATE1 Bit Mask */
7423 #define SCB_PFR0_STATE10                         ((uint32_t)0x00000010)          /*!< STATE1 Bit 0 */
7424 #define SCB_PFR0_STATE11                         ((uint32_t)0x00000020)          /*!< STATE1 Bit 1 */
7425 #define SCB_PFR0_STATE12                         ((uint32_t)0x00000040)          /*!< STATE1 Bit 2 */
7426 #define SCB_PFR0_STATE13                         ((uint32_t)0x00000080)          /*!< STATE1 Bit 3 */
7427 #define SCB_PFR0_STATE1_0                        ((uint32_t)0x00000000)          /*!< N/A */
7428 #define SCB_PFR0_STATE1_1                        ((uint32_t)0x00000010)          /*!< N/A */
7429 #define SCB_PFR0_STATE1_2                        ((uint32_t)0x00000020)          /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL  */
7430                                                                                  /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */
7431                                                                                  /* can be added using the appropriate instruction attribute, but other 32-bit */
7432                                                                                  /* basic instructions cannot.) */
7433 #define SCB_PFR0_STATE1_3                        ((uint32_t)0x00000030)          /*!< Thumb-2 encoding with all Thumb-2 basic instructions */
7434 /* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */
7435 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8)                            /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */
7436 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */
7437 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */
7438 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */
7439 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */
7440 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800)          /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */
7441 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000)          /*!< not supported */
7442 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200)          /*!< two-stack support */
7443 /* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */
7444 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20)                            /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */
7445 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */
7446 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0    ((uint32_t)0x00100000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */
7447 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1    ((uint32_t)0x00200000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */
7448 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2    ((uint32_t)0x00400000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */
7449 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3    ((uint32_t)0x00800000)          /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */
7450 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0   ((uint32_t)0x00000000)          /*!< not supported */
7451 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1   ((uint32_t)0x00100000)          /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */
7452 /* SCB_MMFR0[PMSA_SUPPORT] Bits */
7453 #define SCB_MMFR0_PMSA_SUPPORT_OFS               ( 4)                            /*!< PMSA_SUPPORT Bit Offset */
7454 #define SCB_MMFR0_PMSA_SUPPORT_MASK              ((uint32_t)0x000000F0)          /*!< PMSA_SUPPORT Bit Mask */
7455 #define SCB_MMFR0_PMSA_SUPPORT0                  ((uint32_t)0x00000010)          /*!< PMSA_SUPPORT Bit 0 */
7456 #define SCB_MMFR0_PMSA_SUPPORT1                  ((uint32_t)0x00000020)          /*!< PMSA_SUPPORT Bit 1 */
7457 #define SCB_MMFR0_PMSA_SUPPORT2                  ((uint32_t)0x00000040)          /*!< PMSA_SUPPORT Bit 2 */
7458 #define SCB_MMFR0_PMSA_SUPPORT3                  ((uint32_t)0x00000080)          /*!< PMSA_SUPPORT Bit 3 */
7459 #define SCB_MMFR0_PMSA_SUPPORT_0                 ((uint32_t)0x00000000)          /*!< not supported */
7460 #define SCB_MMFR0_PMSA_SUPPORT_1                 ((uint32_t)0x00000010)          /*!< IMPLEMENTATION DEFINED (N/A) */
7461 #define SCB_MMFR0_PMSA_SUPPORT_2                 ((uint32_t)0x00000020)          /*!< PMSA base (features as defined for ARMv6) (N/A) */
7462 #define SCB_MMFR0_PMSA_SUPPORT_3                 ((uint32_t)0x00000030)          /*!< PMSAv7 (base plus subregion support) */
7463 /* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */
7464 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS    ( 8)                            /*!< CACHE_COHERENCE_SUPPORT Bit Offset */
7465 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK   ((uint32_t)0x00000F00)          /*!< CACHE_COHERENCE_SUPPORT Bit Mask */
7466 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0       ((uint32_t)0x00000100)          /*!< CACHE_COHERENCE_SUPPORT Bit 0 */
7467 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1       ((uint32_t)0x00000200)          /*!< CACHE_COHERENCE_SUPPORT Bit 1 */
7468 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2       ((uint32_t)0x00000400)          /*!< CACHE_COHERENCE_SUPPORT Bit 2 */
7469 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3       ((uint32_t)0x00000800)          /*!< CACHE_COHERENCE_SUPPORT Bit 3 */
7470 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0      ((uint32_t)0x00000000)          /*!< no shared support */
7471 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1      ((uint32_t)0x00000100)          /*!< partial-inner-shared coherency (coherency amongst some - but not all - of  */
7472                                                                                  /* the entities within an inner-coherent domain) */
7473 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2      ((uint32_t)0x00000200)          /*!< full-inner-shared coherency (coherency amongst all of the entities within an  */
7474                                                                                  /* inner-coherent domain) */
7475 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3      ((uint32_t)0x00000300)          /*!< full coherency (coherency amongst all of the entities) */
7476 /* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */
7477 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12)                            /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */
7478 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */
7479 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0    ((uint32_t)0x00001000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */
7480 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1    ((uint32_t)0x00002000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */
7481 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2    ((uint32_t)0x00004000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */
7482 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3    ((uint32_t)0x00008000)          /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */
7483 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0   ((uint32_t)0x00000000)          /*!< Outer non-sharable not supported */
7484 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1   ((uint32_t)0x00001000)          /*!< Outer sharable supported */
7485 /* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */
7486 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS  (20)                            /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */
7487 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000)          /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */
7488 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0     ((uint32_t)0x00100000)          /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */
7489 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1     ((uint32_t)0x00200000)          /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */
7490 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2     ((uint32_t)0x00400000)          /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */
7491 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3     ((uint32_t)0x00800000)          /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */
7492 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0    ((uint32_t)0x00000000)          /*!< not supported */
7493 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1    ((uint32_t)0x00100000)          /*!< Auxiliary control register */
7494 /* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */
7495 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24)                            /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */
7496 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */
7497 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0   ((uint32_t)0x01000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */
7498 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1   ((uint32_t)0x02000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */
7499 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2   ((uint32_t)0x04000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */
7500 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3   ((uint32_t)0x08000000)          /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */
7501 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0  ((uint32_t)0x00000000)          /*!< not supported */
7502 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1  ((uint32_t)0x01000000)          /*!< wait for interrupt supported */
7503 /* SCB_ISAR0[BITCOUNT_INSTRS] Bits */
7504 #define SCB_ISAR0_BITCOUNT_INSTRS_OFS            ( 4)                            /*!< BITCOUNT_INSTRS Bit Offset */
7505 #define SCB_ISAR0_BITCOUNT_INSTRS_MASK           ((uint32_t)0x000000F0)          /*!< BITCOUNT_INSTRS Bit Mask */
7506 #define SCB_ISAR0_BITCOUNT_INSTRS0               ((uint32_t)0x00000010)          /*!< BITCOUNT_INSTRS Bit 0 */
7507 #define SCB_ISAR0_BITCOUNT_INSTRS1               ((uint32_t)0x00000020)          /*!< BITCOUNT_INSTRS Bit 1 */
7508 #define SCB_ISAR0_BITCOUNT_INSTRS2               ((uint32_t)0x00000040)          /*!< BITCOUNT_INSTRS Bit 2 */
7509 #define SCB_ISAR0_BITCOUNT_INSTRS3               ((uint32_t)0x00000080)          /*!< BITCOUNT_INSTRS Bit 3 */
7510 #define SCB_ISAR0_BITCOUNT_INSTRS_0              ((uint32_t)0x00000000)          /*!< no bit-counting instructions present */
7511 #define SCB_ISAR0_BITCOUNT_INSTRS_1              ((uint32_t)0x00000010)          /*!< adds CLZ */
7512 /* SCB_ISAR0[BITFIELD_INSTRS] Bits */
7513 #define SCB_ISAR0_BITFIELD_INSTRS_OFS            ( 8)                            /*!< BITFIELD_INSTRS Bit Offset */
7514 #define SCB_ISAR0_BITFIELD_INSTRS_MASK           ((uint32_t)0x00000F00)          /*!< BITFIELD_INSTRS Bit Mask */
7515 #define SCB_ISAR0_BITFIELD_INSTRS0               ((uint32_t)0x00000100)          /*!< BITFIELD_INSTRS Bit 0 */
7516 #define SCB_ISAR0_BITFIELD_INSTRS1               ((uint32_t)0x00000200)          /*!< BITFIELD_INSTRS Bit 1 */
7517 #define SCB_ISAR0_BITFIELD_INSTRS2               ((uint32_t)0x00000400)          /*!< BITFIELD_INSTRS Bit 2 */
7518 #define SCB_ISAR0_BITFIELD_INSTRS3               ((uint32_t)0x00000800)          /*!< BITFIELD_INSTRS Bit 3 */
7519 #define SCB_ISAR0_BITFIELD_INSTRS_0              ((uint32_t)0x00000000)          /*!< no bitfield instructions present */
7520 #define SCB_ISAR0_BITFIELD_INSTRS_1              ((uint32_t)0x00000100)          /*!< adds BFC, BFI, SBFX, UBFX */
7521 /* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */
7522 #define SCB_ISAR0_CMPBRANCH_INSTRS_OFS           (12)                            /*!< CMPBRANCH_INSTRS Bit Offset */
7523 #define SCB_ISAR0_CMPBRANCH_INSTRS_MASK          ((uint32_t)0x0000F000)          /*!< CMPBRANCH_INSTRS Bit Mask */
7524 #define SCB_ISAR0_CMPBRANCH_INSTRS0              ((uint32_t)0x00001000)          /*!< CMPBRANCH_INSTRS Bit 0 */
7525 #define SCB_ISAR0_CMPBRANCH_INSTRS1              ((uint32_t)0x00002000)          /*!< CMPBRANCH_INSTRS Bit 1 */
7526 #define SCB_ISAR0_CMPBRANCH_INSTRS2              ((uint32_t)0x00004000)          /*!< CMPBRANCH_INSTRS Bit 2 */
7527 #define SCB_ISAR0_CMPBRANCH_INSTRS3              ((uint32_t)0x00008000)          /*!< CMPBRANCH_INSTRS Bit 3 */
7528 #define SCB_ISAR0_CMPBRANCH_INSTRS_0             ((uint32_t)0x00000000)          /*!< no combined compare-and-branch instructions present */
7529 #define SCB_ISAR0_CMPBRANCH_INSTRS_1             ((uint32_t)0x00001000)          /*!< adds CB{N}Z */
7530 /* SCB_ISAR0[COPROC_INSTRS] Bits */
7531 #define SCB_ISAR0_COPROC_INSTRS_OFS              (16)                            /*!< COPROC_INSTRS Bit Offset */
7532 #define SCB_ISAR0_COPROC_INSTRS_MASK             ((uint32_t)0x000F0000)          /*!< COPROC_INSTRS Bit Mask */
7533 #define SCB_ISAR0_COPROC_INSTRS0                 ((uint32_t)0x00010000)          /*!< COPROC_INSTRS Bit 0 */
7534 #define SCB_ISAR0_COPROC_INSTRS1                 ((uint32_t)0x00020000)          /*!< COPROC_INSTRS Bit 1 */
7535 #define SCB_ISAR0_COPROC_INSTRS2                 ((uint32_t)0x00040000)          /*!< COPROC_INSTRS Bit 2 */
7536 #define SCB_ISAR0_COPROC_INSTRS3                 ((uint32_t)0x00080000)          /*!< COPROC_INSTRS Bit 3 */
7537 #define SCB_ISAR0_COPROC_INSTRS_0                ((uint32_t)0x00000000)          /*!< no coprocessor support, other than for separately attributed architectures  */
7538                                                                                  /* such as CP15 or VFP */
7539 #define SCB_ISAR0_COPROC_INSTRS_1                ((uint32_t)0x00010000)          /*!< adds generic CDP, LDC, MCR, MRC, STC */
7540 #define SCB_ISAR0_COPROC_INSTRS_2                ((uint32_t)0x00020000)          /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */
7541 #define SCB_ISAR0_COPROC_INSTRS_3                ((uint32_t)0x00030000)          /*!< adds generic MCRR, MRRC */
7542 #define SCB_ISAR0_COPROC_INSTRS_4                ((uint32_t)0x00040000)          /*!< adds generic MCRR2, MRRC2 */
7543 /* SCB_ISAR0[DEBUG_INSTRS] Bits */
7544 #define SCB_ISAR0_DEBUG_INSTRS_OFS               (20)                            /*!< DEBUG_INSTRS Bit Offset */
7545 #define SCB_ISAR0_DEBUG_INSTRS_MASK              ((uint32_t)0x00F00000)          /*!< DEBUG_INSTRS Bit Mask */
7546 #define SCB_ISAR0_DEBUG_INSTRS0                  ((uint32_t)0x00100000)          /*!< DEBUG_INSTRS Bit 0 */
7547 #define SCB_ISAR0_DEBUG_INSTRS1                  ((uint32_t)0x00200000)          /*!< DEBUG_INSTRS Bit 1 */
7548 #define SCB_ISAR0_DEBUG_INSTRS2                  ((uint32_t)0x00400000)          /*!< DEBUG_INSTRS Bit 2 */
7549 #define SCB_ISAR0_DEBUG_INSTRS3                  ((uint32_t)0x00800000)          /*!< DEBUG_INSTRS Bit 3 */
7550 #define SCB_ISAR0_DEBUG_INSTRS_0                 ((uint32_t)0x00000000)          /*!< no debug instructions present */
7551 #define SCB_ISAR0_DEBUG_INSTRS_1                 ((uint32_t)0x00100000)          /*!< adds BKPT */
7552 /* SCB_ISAR0[DIVIDE_INSTRS] Bits */
7553 #define SCB_ISAR0_DIVIDE_INSTRS_OFS              (24)                            /*!< DIVIDE_INSTRS Bit Offset */
7554 #define SCB_ISAR0_DIVIDE_INSTRS_MASK             ((uint32_t)0x0F000000)          /*!< DIVIDE_INSTRS Bit Mask */
7555 #define SCB_ISAR0_DIVIDE_INSTRS0                 ((uint32_t)0x01000000)          /*!< DIVIDE_INSTRS Bit 0 */
7556 #define SCB_ISAR0_DIVIDE_INSTRS1                 ((uint32_t)0x02000000)          /*!< DIVIDE_INSTRS Bit 1 */
7557 #define SCB_ISAR0_DIVIDE_INSTRS2                 ((uint32_t)0x04000000)          /*!< DIVIDE_INSTRS Bit 2 */
7558 #define SCB_ISAR0_DIVIDE_INSTRS3                 ((uint32_t)0x08000000)          /*!< DIVIDE_INSTRS Bit 3 */
7559 #define SCB_ISAR0_DIVIDE_INSTRS_0                ((uint32_t)0x00000000)          /*!< no divide instructions present */
7560 #define SCB_ISAR0_DIVIDE_INSTRS_1                ((uint32_t)0x01000000)          /*!< adds SDIV, UDIV (v1 quotient only result) */
7561 /* SCB_ISAR1[ETEND_INSRS] Bits */
7562 #define SCB_ISAR1_ETEND_INSRS_OFS                (12)                            /*!< EXTEND_INSRS Bit Offset */
7563 #define SCB_ISAR1_ETEND_INSRS_MASK               ((uint32_t)0x0000F000)          /*!< EXTEND_INSRS Bit Mask */
7564 #define SCB_ISAR1_ETEND_INSRS0                   ((uint32_t)0x00001000)          /*!< ETEND_INSRS Bit 0 */
7565 #define SCB_ISAR1_ETEND_INSRS1                   ((uint32_t)0x00002000)          /*!< ETEND_INSRS Bit 1 */
7566 #define SCB_ISAR1_ETEND_INSRS2                   ((uint32_t)0x00004000)          /*!< ETEND_INSRS Bit 2 */
7567 #define SCB_ISAR1_ETEND_INSRS3                   ((uint32_t)0x00008000)          /*!< ETEND_INSRS Bit 3 */
7568 #define SCB_ISAR1_ETEND_INSRS_0                  ((uint32_t)0x00000000)          /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */
7569 #define SCB_ISAR1_ETEND_INSRS_1                  ((uint32_t)0x00001000)          /*!< adds SXTB, SXTH, UXTB, UXTH */
7570 #define SCB_ISAR1_ETEND_INSRS_2                  ((uint32_t)0x00002000)          /*!< N/A */
7571 /* SCB_ISAR1[IFTHEN_INSTRS] Bits */
7572 #define SCB_ISAR1_IFTHEN_INSTRS_OFS              (16)                            /*!< IFTHEN_INSTRS Bit Offset */
7573 #define SCB_ISAR1_IFTHEN_INSTRS_MASK             ((uint32_t)0x000F0000)          /*!< IFTHEN_INSTRS Bit Mask */
7574 #define SCB_ISAR1_IFTHEN_INSTRS0                 ((uint32_t)0x00010000)          /*!< IFTHEN_INSTRS Bit 0 */
7575 #define SCB_ISAR1_IFTHEN_INSTRS1                 ((uint32_t)0x00020000)          /*!< IFTHEN_INSTRS Bit 1 */
7576 #define SCB_ISAR1_IFTHEN_INSTRS2                 ((uint32_t)0x00040000)          /*!< IFTHEN_INSTRS Bit 2 */
7577 #define SCB_ISAR1_IFTHEN_INSTRS3                 ((uint32_t)0x00080000)          /*!< IFTHEN_INSTRS Bit 3 */
7578 #define SCB_ISAR1_IFTHEN_INSTRS_0                ((uint32_t)0x00000000)          /*!< IT instructions not present */
7579 #define SCB_ISAR1_IFTHEN_INSTRS_1                ((uint32_t)0x00010000)          /*!< adds IT instructions (and IT bits in PSRs) */
7580 /* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */
7581 #define SCB_ISAR1_IMMEDIATE_INSTRS_OFS           (20)                            /*!< IMMEDIATE_INSTRS Bit Offset */
7582 #define SCB_ISAR1_IMMEDIATE_INSTRS_MASK          ((uint32_t)0x00F00000)          /*!< IMMEDIATE_INSTRS Bit Mask */
7583 #define SCB_ISAR1_IMMEDIATE_INSTRS0              ((uint32_t)0x00100000)          /*!< IMMEDIATE_INSTRS Bit 0 */
7584 #define SCB_ISAR1_IMMEDIATE_INSTRS1              ((uint32_t)0x00200000)          /*!< IMMEDIATE_INSTRS Bit 1 */
7585 #define SCB_ISAR1_IMMEDIATE_INSTRS2              ((uint32_t)0x00400000)          /*!< IMMEDIATE_INSTRS Bit 2 */
7586 #define SCB_ISAR1_IMMEDIATE_INSTRS3              ((uint32_t)0x00800000)          /*!< IMMEDIATE_INSTRS Bit 3 */
7587 #define SCB_ISAR1_IMMEDIATE_INSTRS_0             ((uint32_t)0x00000000)          /*!< no special immediate-generating instructions present */
7588 #define SCB_ISAR1_IMMEDIATE_INSTRS_1             ((uint32_t)0x00100000)          /*!< adds ADDW, MOVW, MOVT, SUBW */
7589 /* SCB_ISAR1[INTERWORK_INSTRS] Bits */
7590 #define SCB_ISAR1_INTERWORK_INSTRS_OFS           (24)                            /*!< INTERWORK_INSTRS Bit Offset */
7591 #define SCB_ISAR1_INTERWORK_INSTRS_MASK          ((uint32_t)0x0F000000)          /*!< INTERWORK_INSTRS Bit Mask */
7592 #define SCB_ISAR1_INTERWORK_INSTRS0              ((uint32_t)0x01000000)          /*!< INTERWORK_INSTRS Bit 0 */
7593 #define SCB_ISAR1_INTERWORK_INSTRS1              ((uint32_t)0x02000000)          /*!< INTERWORK_INSTRS Bit 1 */
7594 #define SCB_ISAR1_INTERWORK_INSTRS2              ((uint32_t)0x04000000)          /*!< INTERWORK_INSTRS Bit 2 */
7595 #define SCB_ISAR1_INTERWORK_INSTRS3              ((uint32_t)0x08000000)          /*!< INTERWORK_INSTRS Bit 3 */
7596 #define SCB_ISAR1_INTERWORK_INSTRS_0             ((uint32_t)0x00000000)          /*!< no interworking instructions supported */
7597 #define SCB_ISAR1_INTERWORK_INSTRS_1             ((uint32_t)0x01000000)          /*!< adds BX (and T bit in PSRs) */
7598 #define SCB_ISAR1_INTERWORK_INSTRS_2             ((uint32_t)0x02000000)          /*!< adds BLX, and PC loads have BX-like behavior */
7599 #define SCB_ISAR1_INTERWORK_INSTRS_3             ((uint32_t)0x03000000)          /*!< N/A */
7600 /* SCB_ISAR2[LOADSTORE_INSTRS] Bits */
7601 #define SCB_ISAR2_LOADSTORE_INSTRS_OFS           ( 0)                            /*!< LOADSTORE_INSTRS Bit Offset */
7602 #define SCB_ISAR2_LOADSTORE_INSTRS_MASK          ((uint32_t)0x0000000F)          /*!< LOADSTORE_INSTRS Bit Mask */
7603 #define SCB_ISAR2_LOADSTORE_INSTRS0              ((uint32_t)0x00000001)          /*!< LOADSTORE_INSTRS Bit 0 */
7604 #define SCB_ISAR2_LOADSTORE_INSTRS1              ((uint32_t)0x00000002)          /*!< LOADSTORE_INSTRS Bit 1 */
7605 #define SCB_ISAR2_LOADSTORE_INSTRS2              ((uint32_t)0x00000004)          /*!< LOADSTORE_INSTRS Bit 2 */
7606 #define SCB_ISAR2_LOADSTORE_INSTRS3              ((uint32_t)0x00000008)          /*!< LOADSTORE_INSTRS Bit 3 */
7607 #define SCB_ISAR2_LOADSTORE_INSTRS_0             ((uint32_t)0x00000000)          /*!< no additional normal load/store instructions present */
7608 #define SCB_ISAR2_LOADSTORE_INSTRS_1             ((uint32_t)0x00000001)          /*!< adds LDRD/STRD */
7609 /* SCB_ISAR2[MEMHINT_INSTRS] Bits */
7610 #define SCB_ISAR2_MEMHINT_INSTRS_OFS             ( 4)                            /*!< MEMHINT_INSTRS Bit Offset */
7611 #define SCB_ISAR2_MEMHINT_INSTRS_MASK            ((uint32_t)0x000000F0)          /*!< MEMHINT_INSTRS Bit Mask */
7612 #define SCB_ISAR2_MEMHINT_INSTRS0                ((uint32_t)0x00000010)          /*!< MEMHINT_INSTRS Bit 0 */
7613 #define SCB_ISAR2_MEMHINT_INSTRS1                ((uint32_t)0x00000020)          /*!< MEMHINT_INSTRS Bit 1 */
7614 #define SCB_ISAR2_MEMHINT_INSTRS2                ((uint32_t)0x00000040)          /*!< MEMHINT_INSTRS Bit 2 */
7615 #define SCB_ISAR2_MEMHINT_INSTRS3                ((uint32_t)0x00000080)          /*!< MEMHINT_INSTRS Bit 3 */
7616 #define SCB_ISAR2_MEMHINT_INSTRS_0               ((uint32_t)0x00000000)          /*!< no memory hint instructions presen */
7617 #define SCB_ISAR2_MEMHINT_INSTRS_1               ((uint32_t)0x00000010)          /*!< adds PLD */
7618 #define SCB_ISAR2_MEMHINT_INSTRS_2               ((uint32_t)0x00000020)          /*!< adds PLD (ie a repeat on value 1) */
7619 #define SCB_ISAR2_MEMHINT_INSTRS_3               ((uint32_t)0x00000030)          /*!< adds PLI */
7620 /* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */
7621 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS      ( 8)                            /*!< MULTIACCESSINT_INSTRS Bit Offset */
7622 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK     ((uint32_t)0x00000F00)          /*!< MULTIACCESSINT_INSTRS Bit Mask */
7623 #define SCB_ISAR2_MULTIACCESSINT_INSTRS0         ((uint32_t)0x00000100)          /*!< MULTIACCESSINT_INSTRS Bit 0 */
7624 #define SCB_ISAR2_MULTIACCESSINT_INSTRS1         ((uint32_t)0x00000200)          /*!< MULTIACCESSINT_INSTRS Bit 1 */
7625 #define SCB_ISAR2_MULTIACCESSINT_INSTRS2         ((uint32_t)0x00000400)          /*!< MULTIACCESSINT_INSTRS Bit 2 */
7626 #define SCB_ISAR2_MULTIACCESSINT_INSTRS3         ((uint32_t)0x00000800)          /*!< MULTIACCESSINT_INSTRS Bit 3 */
7627 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_0        ((uint32_t)0x00000000)          /*!< the (LDM/STM) instructions are non-interruptible */
7628 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_1        ((uint32_t)0x00000100)          /*!< the (LDM/STM) instructions are restartable */
7629 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_2        ((uint32_t)0x00000200)          /*!< the (LDM/STM) instructions are continuable */
7630 /* SCB_ISAR2[MULT_INSTRS] Bits */
7631 #define SCB_ISAR2_MULT_INSTRS_OFS                (12)                            /*!< MULT_INSTRS Bit Offset */
7632 #define SCB_ISAR2_MULT_INSTRS_MASK               ((uint32_t)0x0000F000)          /*!< MULT_INSTRS Bit Mask */
7633 #define SCB_ISAR2_MULT_INSTRS0                   ((uint32_t)0x00001000)          /*!< MULT_INSTRS Bit 0 */
7634 #define SCB_ISAR2_MULT_INSTRS1                   ((uint32_t)0x00002000)          /*!< MULT_INSTRS Bit 1 */
7635 #define SCB_ISAR2_MULT_INSTRS2                   ((uint32_t)0x00004000)          /*!< MULT_INSTRS Bit 2 */
7636 #define SCB_ISAR2_MULT_INSTRS3                   ((uint32_t)0x00008000)          /*!< MULT_INSTRS Bit 3 */
7637 #define SCB_ISAR2_MULT_INSTRS_0                  ((uint32_t)0x00000000)          /*!< only MUL present */
7638 #define SCB_ISAR2_MULT_INSTRS_1                  ((uint32_t)0x00001000)          /*!< adds MLA */
7639 #define SCB_ISAR2_MULT_INSTRS_2                  ((uint32_t)0x00002000)          /*!< adds MLS */
7640 /* SCB_ISAR2[MULTS_INSTRS] Bits */
7641 #define SCB_ISAR2_MULTS_INSTRS_OFS               (16)                            /*!< MULTS_INSTRS Bit Offset */
7642 #define SCB_ISAR2_MULTS_INSTRS_MASK              ((uint32_t)0x000F0000)          /*!< MULTS_INSTRS Bit Mask */
7643 #define SCB_ISAR2_MULTS_INSTRS0                  ((uint32_t)0x00010000)          /*!< MULTS_INSTRS Bit 0 */
7644 #define SCB_ISAR2_MULTS_INSTRS1                  ((uint32_t)0x00020000)          /*!< MULTS_INSTRS Bit 1 */
7645 #define SCB_ISAR2_MULTS_INSTRS2                  ((uint32_t)0x00040000)          /*!< MULTS_INSTRS Bit 2 */
7646 #define SCB_ISAR2_MULTS_INSTRS3                  ((uint32_t)0x00080000)          /*!< MULTS_INSTRS Bit 3 */
7647 #define SCB_ISAR2_MULTS_INSTRS_0                 ((uint32_t)0x00000000)          /*!< no signed multiply instructions present */
7648 #define SCB_ISAR2_MULTS_INSTRS_1                 ((uint32_t)0x00010000)          /*!< adds SMULL, SMLAL */
7649 #define SCB_ISAR2_MULTS_INSTRS_2                 ((uint32_t)0x00020000)          /*!< N/A */
7650 #define SCB_ISAR2_MULTS_INSTRS_3                 ((uint32_t)0x00030000)          /*!< N/A */
7651 /* SCB_ISAR2[MULTU_INSTRS] Bits */
7652 #define SCB_ISAR2_MULTU_INSTRS_OFS               (20)                            /*!< MULTU_INSTRS Bit Offset */
7653 #define SCB_ISAR2_MULTU_INSTRS_MASK              ((uint32_t)0x00F00000)          /*!< MULTU_INSTRS Bit Mask */
7654 #define SCB_ISAR2_MULTU_INSTRS0                  ((uint32_t)0x00100000)          /*!< MULTU_INSTRS Bit 0 */
7655 #define SCB_ISAR2_MULTU_INSTRS1                  ((uint32_t)0x00200000)          /*!< MULTU_INSTRS Bit 1 */
7656 #define SCB_ISAR2_MULTU_INSTRS2                  ((uint32_t)0x00400000)          /*!< MULTU_INSTRS Bit 2 */
7657 #define SCB_ISAR2_MULTU_INSTRS3                  ((uint32_t)0x00800000)          /*!< MULTU_INSTRS Bit 3 */
7658 #define SCB_ISAR2_MULTU_INSTRS_0                 ((uint32_t)0x00000000)          /*!< no unsigned multiply instructions present */
7659 #define SCB_ISAR2_MULTU_INSTRS_1                 ((uint32_t)0x00100000)          /*!< adds UMULL, UMLAL */
7660 #define SCB_ISAR2_MULTU_INSTRS_2                 ((uint32_t)0x00200000)          /*!< N/A */
7661 /* SCB_ISAR2[REVERSAL_INSTRS] Bits */
7662 #define SCB_ISAR2_REVERSAL_INSTRS_OFS            (28)                            /*!< REVERSAL_INSTRS Bit Offset */
7663 #define SCB_ISAR2_REVERSAL_INSTRS_MASK           ((uint32_t)0xF0000000)          /*!< REVERSAL_INSTRS Bit Mask */
7664 #define SCB_ISAR2_REVERSAL_INSTRS0               ((uint32_t)0x10000000)          /*!< REVERSAL_INSTRS Bit 0 */
7665 #define SCB_ISAR2_REVERSAL_INSTRS1               ((uint32_t)0x20000000)          /*!< REVERSAL_INSTRS Bit 1 */
7666 #define SCB_ISAR2_REVERSAL_INSTRS2               ((uint32_t)0x40000000)          /*!< REVERSAL_INSTRS Bit 2 */
7667 #define SCB_ISAR2_REVERSAL_INSTRS3               ((uint32_t)0x80000000)          /*!< REVERSAL_INSTRS Bit 3 */
7668 #define SCB_ISAR2_REVERSAL_INSTRS_0              ((uint32_t)0x00000000)          /*!< no reversal instructions present */
7669 #define SCB_ISAR2_REVERSAL_INSTRS_1              ((uint32_t)0x10000000)          /*!< adds REV, REV16, REVSH */
7670 #define SCB_ISAR2_REVERSAL_INSTRS_2              ((uint32_t)0x20000000)          /*!< adds RBIT */
7671 /* SCB_ISAR3[SATRUATE_INSTRS] Bits */
7672 #define SCB_ISAR3_SATRUATE_INSTRS_OFS            ( 0)                            /*!< SATRUATE_INSTRS Bit Offset */
7673 #define SCB_ISAR3_SATRUATE_INSTRS_MASK           ((uint32_t)0x0000000F)          /*!< SATRUATE_INSTRS Bit Mask */
7674 #define SCB_ISAR3_SATRUATE_INSTRS0               ((uint32_t)0x00000001)          /*!< SATRUATE_INSTRS Bit 0 */
7675 #define SCB_ISAR3_SATRUATE_INSTRS1               ((uint32_t)0x00000002)          /*!< SATRUATE_INSTRS Bit 1 */
7676 #define SCB_ISAR3_SATRUATE_INSTRS2               ((uint32_t)0x00000004)          /*!< SATRUATE_INSTRS Bit 2 */
7677 #define SCB_ISAR3_SATRUATE_INSTRS3               ((uint32_t)0x00000008)          /*!< SATRUATE_INSTRS Bit 3 */
7678 #define SCB_ISAR3_SATRUATE_INSTRS_0              ((uint32_t)0x00000000)          /*!< no non-SIMD saturate instructions present */
7679 #define SCB_ISAR3_SATRUATE_INSTRS_1              ((uint32_t)0x00000001)          /*!< N/A */
7680 /* SCB_ISAR3[SIMD_INSTRS] Bits */
7681 #define SCB_ISAR3_SIMD_INSTRS_OFS                ( 4)                            /*!< SIMD_INSTRS Bit Offset */
7682 #define SCB_ISAR3_SIMD_INSTRS_MASK               ((uint32_t)0x000000F0)          /*!< SIMD_INSTRS Bit Mask */
7683 #define SCB_ISAR3_SIMD_INSTRS0                   ((uint32_t)0x00000010)          /*!< SIMD_INSTRS Bit 0 */
7684 #define SCB_ISAR3_SIMD_INSTRS1                   ((uint32_t)0x00000020)          /*!< SIMD_INSTRS Bit 1 */
7685 #define SCB_ISAR3_SIMD_INSTRS2                   ((uint32_t)0x00000040)          /*!< SIMD_INSTRS Bit 2 */
7686 #define SCB_ISAR3_SIMD_INSTRS3                   ((uint32_t)0x00000080)          /*!< SIMD_INSTRS Bit 3 */
7687 #define SCB_ISAR3_SIMD_INSTRS_0                  ((uint32_t)0x00000000)          /*!< no SIMD instructions present */
7688 #define SCB_ISAR3_SIMD_INSTRS_1                  ((uint32_t)0x00000010)          /*!< adds SSAT, USAT (and the Q flag in the PSRs) */
7689 #define SCB_ISAR3_SIMD_INSTRS_3                  ((uint32_t)0x00000030)          /*!< N/A */
7690 /* SCB_ISAR3[SVC_INSTRS] Bits */
7691 #define SCB_ISAR3_SVC_INSTRS_OFS                 ( 8)                            /*!< SVC_INSTRS Bit Offset */
7692 #define SCB_ISAR3_SVC_INSTRS_MASK                ((uint32_t)0x00000F00)          /*!< SVC_INSTRS Bit Mask */
7693 #define SCB_ISAR3_SVC_INSTRS0                    ((uint32_t)0x00000100)          /*!< SVC_INSTRS Bit 0 */
7694 #define SCB_ISAR3_SVC_INSTRS1                    ((uint32_t)0x00000200)          /*!< SVC_INSTRS Bit 1 */
7695 #define SCB_ISAR3_SVC_INSTRS2                    ((uint32_t)0x00000400)          /*!< SVC_INSTRS Bit 2 */
7696 #define SCB_ISAR3_SVC_INSTRS3                    ((uint32_t)0x00000800)          /*!< SVC_INSTRS Bit 3 */
7697 #define SCB_ISAR3_SVC_INSTRS_0                   ((uint32_t)0x00000000)          /*!< no SVC (SWI) instructions present */
7698 #define SCB_ISAR3_SVC_INSTRS_1                   ((uint32_t)0x00000100)          /*!< adds SVC (SWI) */
7699 /* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */
7700 #define SCB_ISAR3_SYNCPRIM_INSTRS_OFS            (12)                            /*!< SYNCPRIM_INSTRS Bit Offset */
7701 #define SCB_ISAR3_SYNCPRIM_INSTRS_MASK           ((uint32_t)0x0000F000)          /*!< SYNCPRIM_INSTRS Bit Mask */
7702 #define SCB_ISAR3_SYNCPRIM_INSTRS0               ((uint32_t)0x00001000)          /*!< SYNCPRIM_INSTRS Bit 0 */
7703 #define SCB_ISAR3_SYNCPRIM_INSTRS1               ((uint32_t)0x00002000)          /*!< SYNCPRIM_INSTRS Bit 1 */
7704 #define SCB_ISAR3_SYNCPRIM_INSTRS2               ((uint32_t)0x00004000)          /*!< SYNCPRIM_INSTRS Bit 2 */
7705 #define SCB_ISAR3_SYNCPRIM_INSTRS3               ((uint32_t)0x00008000)          /*!< SYNCPRIM_INSTRS Bit 3 */
7706 #define SCB_ISAR3_SYNCPRIM_INSTRS_0              ((uint32_t)0x00000000)          /*!< no synchronization primitives present */
7707 #define SCB_ISAR3_SYNCPRIM_INSTRS_1              ((uint32_t)0x00001000)          /*!< adds LDREX, STREX */
7708 #define SCB_ISAR3_SYNCPRIM_INSTRS_2              ((uint32_t)0x00002000)          /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */
7709 /* SCB_ISAR3[TABBRANCH_INSTRS] Bits */
7710 #define SCB_ISAR3_TABBRANCH_INSTRS_OFS           (16)                            /*!< TABBRANCH_INSTRS Bit Offset */
7711 #define SCB_ISAR3_TABBRANCH_INSTRS_MASK          ((uint32_t)0x000F0000)          /*!< TABBRANCH_INSTRS Bit Mask */
7712 #define SCB_ISAR3_TABBRANCH_INSTRS0              ((uint32_t)0x00010000)          /*!< TABBRANCH_INSTRS Bit 0 */
7713 #define SCB_ISAR3_TABBRANCH_INSTRS1              ((uint32_t)0x00020000)          /*!< TABBRANCH_INSTRS Bit 1 */
7714 #define SCB_ISAR3_TABBRANCH_INSTRS2              ((uint32_t)0x00040000)          /*!< TABBRANCH_INSTRS Bit 2 */
7715 #define SCB_ISAR3_TABBRANCH_INSTRS3              ((uint32_t)0x00080000)          /*!< TABBRANCH_INSTRS Bit 3 */
7716 #define SCB_ISAR3_TABBRANCH_INSTRS_0             ((uint32_t)0x00000000)          /*!< no table-branch instructions present */
7717 #define SCB_ISAR3_TABBRANCH_INSTRS_1             ((uint32_t)0x00010000)          /*!< adds TBB, TBH */
7718 /* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */
7719 #define SCB_ISAR3_THUMBCOPY_INSTRS_OFS           (20)                            /*!< THUMBCOPY_INSTRS Bit Offset */
7720 #define SCB_ISAR3_THUMBCOPY_INSTRS_MASK          ((uint32_t)0x00F00000)          /*!< THUMBCOPY_INSTRS Bit Mask */
7721 #define SCB_ISAR3_THUMBCOPY_INSTRS0              ((uint32_t)0x00100000)          /*!< THUMBCOPY_INSTRS Bit 0 */
7722 #define SCB_ISAR3_THUMBCOPY_INSTRS1              ((uint32_t)0x00200000)          /*!< THUMBCOPY_INSTRS Bit 1 */
7723 #define SCB_ISAR3_THUMBCOPY_INSTRS2              ((uint32_t)0x00400000)          /*!< THUMBCOPY_INSTRS Bit 2 */
7724 #define SCB_ISAR3_THUMBCOPY_INSTRS3              ((uint32_t)0x00800000)          /*!< THUMBCOPY_INSTRS Bit 3 */
7725 #define SCB_ISAR3_THUMBCOPY_INSTRS_0             ((uint32_t)0x00000000)          /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */
7726 #define SCB_ISAR3_THUMBCOPY_INSTRS_1             ((uint32_t)0x00100000)          /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */
7727 /* SCB_ISAR3[TRUENOP_INSTRS] Bits */
7728 #define SCB_ISAR3_TRUENOP_INSTRS_OFS             (24)                            /*!< TRUENOP_INSTRS Bit Offset */
7729 #define SCB_ISAR3_TRUENOP_INSTRS_MASK            ((uint32_t)0x0F000000)          /*!< TRUENOP_INSTRS Bit Mask */
7730 #define SCB_ISAR3_TRUENOP_INSTRS0                ((uint32_t)0x01000000)          /*!< TRUENOP_INSTRS Bit 0 */
7731 #define SCB_ISAR3_TRUENOP_INSTRS1                ((uint32_t)0x02000000)          /*!< TRUENOP_INSTRS Bit 1 */
7732 #define SCB_ISAR3_TRUENOP_INSTRS2                ((uint32_t)0x04000000)          /*!< TRUENOP_INSTRS Bit 2 */
7733 #define SCB_ISAR3_TRUENOP_INSTRS3                ((uint32_t)0x08000000)          /*!< TRUENOP_INSTRS Bit 3 */
7734 #define SCB_ISAR3_TRUENOP_INSTRS_0               ((uint32_t)0x00000000)          /*!< true NOP instructions not present - that is, NOP instructions with no  */
7735                                                                                  /* register dependencies */
7736 #define SCB_ISAR3_TRUENOP_INSTRS_1               ((uint32_t)0x01000000)          /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */
7737 /* SCB_ISAR4[UNPRIV_INSTRS] Bits */
7738 #define SCB_ISAR4_UNPRIV_INSTRS_OFS              ( 0)                            /*!< UNPRIV_INSTRS Bit Offset */
7739 #define SCB_ISAR4_UNPRIV_INSTRS_MASK             ((uint32_t)0x0000000F)          /*!< UNPRIV_INSTRS Bit Mask */
7740 #define SCB_ISAR4_UNPRIV_INSTRS0                 ((uint32_t)0x00000001)          /*!< UNPRIV_INSTRS Bit 0 */
7741 #define SCB_ISAR4_UNPRIV_INSTRS1                 ((uint32_t)0x00000002)          /*!< UNPRIV_INSTRS Bit 1 */
7742 #define SCB_ISAR4_UNPRIV_INSTRS2                 ((uint32_t)0x00000004)          /*!< UNPRIV_INSTRS Bit 2 */
7743 #define SCB_ISAR4_UNPRIV_INSTRS3                 ((uint32_t)0x00000008)          /*!< UNPRIV_INSTRS Bit 3 */
7744 #define SCB_ISAR4_UNPRIV_INSTRS_0                ((uint32_t)0x00000000)          /*!< no "T variant" instructions exist */
7745 #define SCB_ISAR4_UNPRIV_INSTRS_1                ((uint32_t)0x00000001)          /*!< adds LDRBT, LDRT, STRBT, STRT */
7746 #define SCB_ISAR4_UNPRIV_INSTRS_2                ((uint32_t)0x00000002)          /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */
7747 /* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */
7748 #define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS          ( 4)                            /*!< WITHSHIFTS_INSTRS Bit Offset */
7749 #define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK         ((uint32_t)0x000000F0)          /*!< WITHSHIFTS_INSTRS Bit Mask */
7750 #define SCB_ISAR4_WITHSHIFTS_INSTRS0             ((uint32_t)0x00000010)          /*!< WITHSHIFTS_INSTRS Bit 0 */
7751 #define SCB_ISAR4_WITHSHIFTS_INSTRS1             ((uint32_t)0x00000020)          /*!< WITHSHIFTS_INSTRS Bit 1 */
7752 #define SCB_ISAR4_WITHSHIFTS_INSTRS2             ((uint32_t)0x00000040)          /*!< WITHSHIFTS_INSTRS Bit 2 */
7753 #define SCB_ISAR4_WITHSHIFTS_INSTRS3             ((uint32_t)0x00000080)          /*!< WITHSHIFTS_INSTRS Bit 3 */
7754 #define SCB_ISAR4_WITHSHIFTS_INSTRS_0            ((uint32_t)0x00000000)          /*!< non-zero shifts only support MOV and shift instructions (see notes) */
7755 #define SCB_ISAR4_WITHSHIFTS_INSTRS_1            ((uint32_t)0x00000010)          /*!< shifts of loads/stores over the range LSL 0-3 */
7756 #define SCB_ISAR4_WITHSHIFTS_INSTRS_3            ((uint32_t)0x00000030)          /*!< adds other constant shift options. */
7757 #define SCB_ISAR4_WITHSHIFTS_INSTRS_4            ((uint32_t)0x00000040)          /*!< adds register-controlled shift options. */
7758 /* SCB_ISAR4[WRITEBACK_INSTRS] Bits */
7759 #define SCB_ISAR4_WRITEBACK_INSTRS_OFS           ( 8)                            /*!< WRITEBACK_INSTRS Bit Offset */
7760 #define SCB_ISAR4_WRITEBACK_INSTRS_MASK          ((uint32_t)0x00000F00)          /*!< WRITEBACK_INSTRS Bit Mask */
7761 #define SCB_ISAR4_WRITEBACK_INSTRS0              ((uint32_t)0x00000100)          /*!< WRITEBACK_INSTRS Bit 0 */
7762 #define SCB_ISAR4_WRITEBACK_INSTRS1              ((uint32_t)0x00000200)          /*!< WRITEBACK_INSTRS Bit 1 */
7763 #define SCB_ISAR4_WRITEBACK_INSTRS2              ((uint32_t)0x00000400)          /*!< WRITEBACK_INSTRS Bit 2 */
7764 #define SCB_ISAR4_WRITEBACK_INSTRS3              ((uint32_t)0x00000800)          /*!< WRITEBACK_INSTRS Bit 3 */
7765 #define SCB_ISAR4_WRITEBACK_INSTRS_0             ((uint32_t)0x00000000)          /*!< only non-writeback addressing modes present, except that  */
7766                                                                                  /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */
7767 #define SCB_ISAR4_WRITEBACK_INSTRS_1             ((uint32_t)0x00000100)          /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */
7768 /* SCB_ISAR4[BARRIER_INSTRS] Bits */
7769 #define SCB_ISAR4_BARRIER_INSTRS_OFS             (16)                            /*!< BARRIER_INSTRS Bit Offset */
7770 #define SCB_ISAR4_BARRIER_INSTRS_MASK            ((uint32_t)0x000F0000)          /*!< BARRIER_INSTRS Bit Mask */
7771 #define SCB_ISAR4_BARRIER_INSTRS0                ((uint32_t)0x00010000)          /*!< BARRIER_INSTRS Bit 0 */
7772 #define SCB_ISAR4_BARRIER_INSTRS1                ((uint32_t)0x00020000)          /*!< BARRIER_INSTRS Bit 1 */
7773 #define SCB_ISAR4_BARRIER_INSTRS2                ((uint32_t)0x00040000)          /*!< BARRIER_INSTRS Bit 2 */
7774 #define SCB_ISAR4_BARRIER_INSTRS3                ((uint32_t)0x00080000)          /*!< BARRIER_INSTRS Bit 3 */
7775 #define SCB_ISAR4_BARRIER_INSTRS_0               ((uint32_t)0x00000000)          /*!< no barrier instructions supported */
7776 #define SCB_ISAR4_BARRIER_INSTRS_1               ((uint32_t)0x00010000)          /*!< adds DMB, DSB, ISB barrier instructions */
7777 /* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */
7778 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS       (20)                            /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */
7779 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK      ((uint32_t)0x00F00000)          /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */
7780 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0          ((uint32_t)0x00100000)          /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */
7781 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1          ((uint32_t)0x00200000)          /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */
7782 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2          ((uint32_t)0x00400000)          /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */
7783 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3          ((uint32_t)0x00800000)          /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */
7784 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0         ((uint32_t)0x00000000)          /*!< no additional support */
7785 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3         ((uint32_t)0x00300000)          /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */
7786 /* SCB_ISAR4[PSR_M_INSTRS] Bits */
7787 #define SCB_ISAR4_PSR_M_INSTRS_OFS               (24)                            /*!< PSR_M_INSTRS Bit Offset */
7788 #define SCB_ISAR4_PSR_M_INSTRS_MASK              ((uint32_t)0x0F000000)          /*!< PSR_M_INSTRS Bit Mask */
7789 #define SCB_ISAR4_PSR_M_INSTRS0                  ((uint32_t)0x01000000)          /*!< PSR_M_INSTRS Bit 0 */
7790 #define SCB_ISAR4_PSR_M_INSTRS1                  ((uint32_t)0x02000000)          /*!< PSR_M_INSTRS Bit 1 */
7791 #define SCB_ISAR4_PSR_M_INSTRS2                  ((uint32_t)0x04000000)          /*!< PSR_M_INSTRS Bit 2 */
7792 #define SCB_ISAR4_PSR_M_INSTRS3                  ((uint32_t)0x08000000)          /*!< PSR_M_INSTRS Bit 3 */
7793 #define SCB_ISAR4_PSR_M_INSTRS_0                 ((uint32_t)0x00000000)          /*!< instructions not present */
7794 #define SCB_ISAR4_PSR_M_INSTRS_1                 ((uint32_t)0x01000000)          /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */
7795 /* SCB_CPACR[CP11] Bits */
7796 #define SCB_CPACR_CP11_OFS                       (22)                            /*!< CP11 Bit Offset */
7797 #define SCB_CPACR_CP11_MASK                      ((uint32_t)0x00C00000)          /*!< CP11 Bit Mask */
7798 /* SCB_CPACR[CP10] Bits */
7799 #define SCB_CPACR_CP10_OFS                       (20)                            /*!< CP10 Bit Offset */
7800 #define SCB_CPACR_CP10_MASK                      ((uint32_t)0x00300000)          /*!< CP10 Bit Mask */
7801 /* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */
7802 #define SCB_SHPR1_PRI_4_OFS                      ( 0)                            /*!< PRI_4 Offset */
7803 #define SCB_SHPR1_PRI_4_M                        ((uint32_t)0x000000ff)          /*  */
7804 /* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */
7805 #define SCB_SHPR1_PRI_5_OFS                      ( 8)                            /*!< PRI_5 Offset */
7806 #define SCB_SHPR1_PRI_5_M                        ((uint32_t)0x0000ff00)          /*  */
7807 /* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */
7808 #define SCB_SHPR1_PRI_6_OFS                      (16)                            /*!< PRI_6 Offset */
7809 #define SCB_SHPR1_PRI_6_M                        ((uint32_t)0x00ff0000)          /*  */
7810 /* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */
7811 #define SCB_SHPR1_PRI_7_OFS                      (24)                            /*!< PRI_7 Offset */
7812 #define SCB_SHPR1_PRI_7_M                        ((uint32_t)0xff000000)          /*  */
7813 /* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */
7814 #define SCB_SHPR2_PRI_8_OFS                      ( 0)                            /*!< PRI_8 Offset */
7815 #define SCB_SHPR2_PRI_8_M                        ((uint32_t)0x000000ff)          /*  */
7816 /* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */
7817 #define SCB_SHPR2_PRI_9_OFS                      ( 8)                            /*!< PRI_9 Offset */
7818 #define SCB_SHPR2_PRI_9_M                        ((uint32_t)0x0000ff00)          /*  */
7819 /* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */
7820 #define SCB_SHPR2_PRI_10_OFS                     (16)                            /*!< PRI_10 Offset */
7821 #define SCB_SHPR2_PRI_10_M                       ((uint32_t)0x00ff0000)          /*  */
7822 /* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */
7823 #define SCB_SHPR2_PRI_11_OFS                     (24)                            /*!< PRI_11 Offset */
7824 #define SCB_SHPR2_PRI_11_M                       ((uint32_t)0xff000000)          /*  */
7825 /* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */
7826 #define SCB_SHPR3_PRI_12_OFS                     ( 0)                            /*!< PRI_12 Offset */
7827 #define SCB_SHPR3_PRI_12_M                       ((uint32_t)0x000000ff)          /*  */
7828 /* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */
7829 #define SCB_SHPR3_PRI_13_OFS                     ( 8)                            /*!< PRI_13 Offset */
7830 #define SCB_SHPR3_PRI_13_M                       ((uint32_t)0x0000ff00)          /*  */
7831 /* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */
7832 #define SCB_SHPR3_PRI_14_OFS                     (16)                            /*!< PRI_14 Offset */
7833 #define SCB_SHPR3_PRI_14_M                       ((uint32_t)0x00ff0000)          /*  */
7834 /* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */
7835 #define SCB_SHPR3_PRI_15_OFS                     (24)                            /*!< PRI_15 Offset */
7836 #define SCB_SHPR3_PRI_15_M                       ((uint32_t)0xff000000)          /*  */
7837 
7838 /* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */
7839 #define SCB_CFSR_IACCVIOL_OFS                    ( 0)                            /*!< IACCVIOL Offset */
7840 #define SCB_CFSR_IACCVIOL                        ((uint32_t)0x00000001)          /*  */
7841 /* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */
7842 #define SCB_CFSR_DACCVIOL_OFS                    ( 1)                            /*!< DACCVIOL Offset */
7843 #define SCB_CFSR_DACCVIOL                        ((uint32_t)0x00000002)          /*  */
7844 /* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */
7845 #define SCB_CFSR_MUNSTKERR_OFS                   ( 3)                            /*!< MUNSTKERR Offset */
7846 #define SCB_CFSR_MUNSTKERR                       ((uint32_t)0x00000008)          /*  */
7847 /* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */
7848 #define SCB_CFSR_MSTKERR_OFS                     ( 4)                            /*!< MSTKERR Offset */
7849 #define SCB_CFSR_MSTKERR                         ((uint32_t)0x00000010)          /*  */
7850 /* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */
7851 #define SCB_CFSR_MMARVALID_OFS                   ( 7)                            /*!< MMARVALID Offset */
7852 #define SCB_CFSR_MMARVALID                       ((uint32_t)0x00000080)          /*  */
7853 /* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */
7854 #define SCB_CFSR_IBUSERR_OFS                     ( 8)                            /*!< IBUSERR Offset */
7855 #define SCB_CFSR_IBUSERR                         ((uint32_t)0x00000100)          /*  */
7856 /* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */
7857 #define SCB_CFSR_PRECISERR_OFS                   ( 9)                            /*!< PRECISERR Offset */
7858 #define SCB_CFSR_PRECISERR                       ((uint32_t)0x00000200)          /*  */
7859 /* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */
7860 #define SCB_CFSR_IMPRECISERR_OFS                 (10)                            /*!< IMPRECISERR Offset */
7861 #define SCB_CFSR_IMPRECISERR                     ((uint32_t)0x00000400)          /*  */
7862 /* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */
7863 #define SCB_CFSR_UNSTKERR_OFS                    (11)                            /*!< UNSTKERR Offset */
7864 #define SCB_CFSR_UNSTKERR                        ((uint32_t)0x00000800)          /*  */
7865 /* SCB_CFSR[SCB_CFSR_STKERR] Bits */
7866 #define SCB_CFSR_STKERR_OFS                      (12)                            /*!< STKERR Offset */
7867 #define SCB_CFSR_STKERR                          ((uint32_t)0x00001000)          /*  */
7868 /* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */
7869 #define SCB_CFSR_BFARVALID_OFS                   (15)                            /*!< BFARVALID Offset */
7870 #define SCB_CFSR_BFARVALID                       ((uint32_t)0x00008000)          /*  */
7871 /* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */
7872 #define SCB_CFSR_UNDEFINSTR_OFS                  (16)                            /*!< UNDEFINSTR Offset */
7873 #define SCB_CFSR_UNDEFINSTR                      ((uint32_t)0x00010000)          /*  */
7874 /* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */
7875 #define SCB_CFSR_INVSTATE_OFS                    (17)                            /*!< INVSTATE Offset */
7876 #define SCB_CFSR_INVSTATE                        ((uint32_t)0x00020000)          /*  */
7877 /* SCB_CFSR[SCB_CFSR_INVPC] Bits */
7878 #define SCB_CFSR_INVPC_OFS                       (18)                            /*!< INVPC Offset */
7879 #define SCB_CFSR_INVPC                           ((uint32_t)0x00040000)          /*  */
7880 /* SCB_CFSR[SCB_CFSR_NOCP] Bits */
7881 #define SCB_CFSR_NOCP_OFS                        (19)                            /*!< NOCP Offset */
7882 #define SCB_CFSR_NOCP                            ((uint32_t)0x00080000)          /*  */
7883 /* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */
7884 #define SCB_CFSR_UNALIGNED_OFS                   (24)                            /*!< UNALIGNED Offset */
7885 #define SCB_CFSR_UNALIGNED                       ((uint32_t)0x01000000)          /*  */
7886 /* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */
7887 #define SCB_CFSR_DIVBYZERO_OFS                   (25)                            /*!< DIVBYZERO Offset */
7888 #define SCB_CFSR_DIVBYZERO                       ((uint32_t)0x02000000)          /*  */
7889 /* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */
7890 #define SCB_CFSR_MLSPERR_OFS                     ( 5)                            /*!< MLSPERR Offset */
7891 #define SCB_CFSR_MLSPERR                         ((uint32_t)0x00000020)          /*  */
7892 /* SCB_CFSR[SCB_CFSR_LSPERR] Bits */
7893 #define SCB_CFSR_LSPERR_OFS                      (13)                            /*!< LSPERR Offset */
7894 #define SCB_CFSR_LSPERR                          ((uint32_t)0x00002000)          /*  */
7895 
7896 
7897 /******************************************************************************
7898 * SCNSCB Bits
7899 ******************************************************************************/
7900 
7901 
7902 /******************************************************************************
7903 * SYSCTL_A Bits
7904 ******************************************************************************/
7905 /* SYSCTL_A_REBOOT_CTL[REBOOT] Bits */
7906 #define SYSCTL_A_REBOOT_CTL_REBOOT_OFS           ( 0)                            /*!< REBOOT Bit Offset */
7907 #define SYSCTL_A_REBOOT_CTL_REBOOT               ((uint32_t)0x00000001)          /*!< Write 1 initiates a Reboot of the device */
7908 /* SYSCTL_A_REBOOT_CTL[WKEY] Bits */
7909 #define SYSCTL_A_REBOOT_CTL_WKEY_OFS             ( 8)                            /*!< WKEY Bit Offset */
7910 #define SYSCTL_A_REBOOT_CTL_WKEY_MASK            ((uint32_t)0x0000FF00)          /*!< WKEY Bit Mask */
7911 /* SYSCTL_A_NMI_CTLSTAT[CS_SRC] Bits */
7912 #define SYSCTL_A_NMI_CTLSTAT_CS_SRC_OFS          ( 0)                            /*!< CS_SRC Bit Offset */
7913 #define SYSCTL_A_NMI_CTLSTAT_CS_SRC              ((uint32_t)0x00000001)          /*!< CS interrupt as a source of NMI */
7914 /* SYSCTL_A_NMI_CTLSTAT[PSS_SRC] Bits */
7915 #define SYSCTL_A_NMI_CTLSTAT_PSS_SRC_OFS         ( 1)                            /*!< PSS_SRC Bit Offset */
7916 #define SYSCTL_A_NMI_CTLSTAT_PSS_SRC             ((uint32_t)0x00000002)          /*!< PSS interrupt as a source of NMI */
7917 /* SYSCTL_A_NMI_CTLSTAT[PCM_SRC] Bits */
7918 #define SYSCTL_A_NMI_CTLSTAT_PCM_SRC_OFS         ( 2)                            /*!< PCM_SRC Bit Offset */
7919 #define SYSCTL_A_NMI_CTLSTAT_PCM_SRC             ((uint32_t)0x00000004)          /*!< PCM interrupt as a source of NMI */
7920 /* SYSCTL_A_NMI_CTLSTAT[PIN_SRC] Bits */
7921 #define SYSCTL_A_NMI_CTLSTAT_PIN_SRC_OFS         ( 3)                            /*!< PIN_SRC Bit Offset */
7922 #define SYSCTL_A_NMI_CTLSTAT_PIN_SRC             ((uint32_t)0x00000008)
7923 /* SYSCTL_A_NMI_CTLSTAT[CS_FLG] Bits */
7924 #define SYSCTL_A_NMI_CTLSTAT_CS_FLG_OFS          (16)                            /*!< CS_FLG Bit Offset */
7925 #define SYSCTL_A_NMI_CTLSTAT_CS_FLG              ((uint32_t)0x00010000)          /*!< CS interrupt was the source of NMI */
7926 /* SYSCTL_A_NMI_CTLSTAT[PSS_FLG] Bits */
7927 #define SYSCTL_A_NMI_CTLSTAT_PSS_FLG_OFS         (17)                            /*!< PSS_FLG Bit Offset */
7928 #define SYSCTL_A_NMI_CTLSTAT_PSS_FLG             ((uint32_t)0x00020000)          /*!< PSS interrupt was the source of NMI */
7929 /* SYSCTL_A_NMI_CTLSTAT[PCM_FLG] Bits */
7930 #define SYSCTL_A_NMI_CTLSTAT_PCM_FLG_OFS         (18)                            /*!< PCM_FLG Bit Offset */
7931 #define SYSCTL_A_NMI_CTLSTAT_PCM_FLG             ((uint32_t)0x00040000)          /*!< PCM interrupt was the source of NMI */
7932 /* SYSCTL_A_NMI_CTLSTAT[PIN_FLG] Bits */
7933 #define SYSCTL_A_NMI_CTLSTAT_PIN_FLG_OFS         (19)                            /*!< PIN_FLG Bit Offset */
7934 #define SYSCTL_A_NMI_CTLSTAT_PIN_FLG             ((uint32_t)0x00080000)          /*!< RSTn/NMI pin was the source of NMI */
7935 /* SYSCTL_A_WDTRESET_CTL[TIMEOUT] Bits */
7936 #define SYSCTL_A_WDTRESET_CTL_TIMEOUT_OFS        ( 0)                            /*!< TIMEOUT Bit Offset */
7937 #define SYSCTL_A_WDTRESET_CTL_TIMEOUT            ((uint32_t)0x00000001)          /*!< WDT timeout reset type */
7938 /* SYSCTL_A_WDTRESET_CTL[VIOLATION] Bits */
7939 #define SYSCTL_A_WDTRESET_CTL_VIOLATION_OFS      ( 1)                            /*!< VIOLATION Bit Offset */
7940 #define SYSCTL_A_WDTRESET_CTL_VIOLATION          ((uint32_t)0x00000002)          /*!< WDT password violation reset type */
7941 /* SYSCTL_A_PERIHALT_CTL[HALT_T16_0] Bits */
7942 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_0_OFS     ( 0)                            /*!< HALT_T16_0 Bit Offset */
7943 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_0         ((uint32_t)0x00000001)          /*!< Freezes IP operation when CPU is halted */
7944 /* SYSCTL_A_PERIHALT_CTL[HALT_T16_1] Bits */
7945 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_1_OFS     ( 1)                            /*!< HALT_T16_1 Bit Offset */
7946 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_1         ((uint32_t)0x00000002)          /*!< Freezes IP operation when CPU is halted */
7947 /* SYSCTL_A_PERIHALT_CTL[HALT_T16_2] Bits */
7948 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_2_OFS     ( 2)                            /*!< HALT_T16_2 Bit Offset */
7949 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_2         ((uint32_t)0x00000004)          /*!< Freezes IP operation when CPU is halted */
7950 /* SYSCTL_A_PERIHALT_CTL[HALT_T16_3] Bits */
7951 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_3_OFS     ( 3)                            /*!< HALT_T16_3 Bit Offset */
7952 #define SYSCTL_A_PERIHALT_CTL_HALT_T16_3         ((uint32_t)0x00000008)          /*!< Freezes IP operation when CPU is halted */
7953 /* SYSCTL_A_PERIHALT_CTL[HALT_T32_0] Bits */
7954 #define SYSCTL_A_PERIHALT_CTL_HALT_T32_0_OFS     ( 4)                            /*!< HALT_T32_0 Bit Offset */
7955 #define SYSCTL_A_PERIHALT_CTL_HALT_T32_0         ((uint32_t)0x00000010)          /*!< Freezes IP operation when CPU is halted */
7956 /* SYSCTL_A_PERIHALT_CTL[HALT_eUA0] Bits */
7957 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA0_OFS      ( 5)                            /*!< HALT_eUA0 Bit Offset */
7958 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA0          ((uint32_t)0x00000020)          /*!< Freezes IP operation when CPU is halted */
7959 /* SYSCTL_A_PERIHALT_CTL[HALT_eUA1] Bits */
7960 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA1_OFS      ( 6)                            /*!< HALT_eUA1 Bit Offset */
7961 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA1          ((uint32_t)0x00000040)          /*!< Freezes IP operation when CPU is halted */
7962 /* SYSCTL_A_PERIHALT_CTL[HALT_eUA2] Bits */
7963 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA2_OFS      ( 7)                            /*!< HALT_eUA2 Bit Offset */
7964 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA2          ((uint32_t)0x00000080)          /*!< Freezes IP operation when CPU is halted */
7965 /* SYSCTL_A_PERIHALT_CTL[HALT_eUA3] Bits */
7966 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA3_OFS      ( 8)                            /*!< HALT_eUA3 Bit Offset */
7967 #define SYSCTL_A_PERIHALT_CTL_HALT_EUA3          ((uint32_t)0x00000100)          /*!< Freezes IP operation when CPU is halted */
7968 /* SYSCTL_A_PERIHALT_CTL[HALT_eUB0] Bits */
7969 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB0_OFS      ( 9)                            /*!< HALT_eUB0 Bit Offset */
7970 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB0          ((uint32_t)0x00000200)          /*!< Freezes IP operation when CPU is halted */
7971 /* SYSCTL_A_PERIHALT_CTL[HALT_eUB1] Bits */
7972 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB1_OFS      (10)                            /*!< HALT_eUB1 Bit Offset */
7973 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB1          ((uint32_t)0x00000400)          /*!< Freezes IP operation when CPU is halted */
7974 /* SYSCTL_A_PERIHALT_CTL[HALT_eUB2] Bits */
7975 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB2_OFS      (11)                            /*!< HALT_eUB2 Bit Offset */
7976 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB2          ((uint32_t)0x00000800)          /*!< Freezes IP operation when CPU is halted */
7977 /* SYSCTL_A_PERIHALT_CTL[HALT_eUB3] Bits */
7978 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB3_OFS      (12)                            /*!< HALT_eUB3 Bit Offset */
7979 #define SYSCTL_A_PERIHALT_CTL_HALT_EUB3          ((uint32_t)0x00001000)          /*!< Freezes IP operation when CPU is halted */
7980 /* SYSCTL_A_PERIHALT_CTL[HALT_ADC] Bits */
7981 #define SYSCTL_A_PERIHALT_CTL_HALT_ADC_OFS       (13)                            /*!< HALT_ADC Bit Offset */
7982 #define SYSCTL_A_PERIHALT_CTL_HALT_ADC           ((uint32_t)0x00002000)          /*!< Freezes IP operation when CPU is halted */
7983 /* SYSCTL_A_PERIHALT_CTL[HALT_WDT] Bits */
7984 #define SYSCTL_A_PERIHALT_CTL_HALT_WDT_OFS       (14)                            /*!< HALT_WDT Bit Offset */
7985 #define SYSCTL_A_PERIHALT_CTL_HALT_WDT           ((uint32_t)0x00004000)          /*!< Freezes IP operation when CPU is halted */
7986 /* SYSCTL_A_PERIHALT_CTL[HALT_DMA] Bits */
7987 #define SYSCTL_A_PERIHALT_CTL_HALT_DMA_OFS       (15)                            /*!< HALT_DMA Bit Offset */
7988 #define SYSCTL_A_PERIHALT_CTL_HALT_DMA           ((uint32_t)0x00008000)          /*!< Freezes IP operation when CPU is halted */
7989 /* SYSCTL_A_PERIHALT_CTL[HALT_LCD] Bits */
7990 #define SYSCTL_A_PERIHALT_CTL_HALT_LCD_OFS       (16)                            /*!< HALT_LCD Bit Offset */
7991 #define SYSCTL_A_PERIHALT_CTL_HALT_LCD           ((uint32_t)0x00010000)          /*!< Freezes IP operation when CPU is halted */
7992 /* SYSCTL_A_DIO_GLTFLT_CTL[GLTCH_EN] Bits */
7993 #define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN_OFS     ( 0)                            /*!< GLTCH_EN Bit Offset */
7994 #define SYSCTL_A_DIO_GLTFLT_CTL_GLTCH_EN         ((uint32_t)0x00000001)          /*!< Glitch filter enable */
7995 /* SYSCTL_A_SECDATA_UNLOCK[UNLKEY] Bits */
7996 #define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_OFS       ( 0)                            /*!< UNLKEY Bit Offset */
7997 #define SYSCTL_A_SECDATA_UNLOCK_UNLKEY_MASK      ((uint32_t)0x0000FFFF)          /*!< UNLKEY Bit Mask */
7998 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK0_EN] Bits */
7999 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN_OFS    ( 0)                            /*!< BNK0_EN Bit Offset */
8000 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK0_EN        ((uint32_t)0x00000001)          /*!< When 1, enables Bank0 of the SRAM */
8001 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK1_EN] Bits */
8002 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN_OFS    ( 1)                            /*!< BNK1_EN Bit Offset */
8003 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK1_EN        ((uint32_t)0x00000002)          /*!< When 1, enables Bank1 of the SRAM */
8004 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK2_EN] Bits */
8005 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN_OFS    ( 2)                            /*!< BNK2_EN Bit Offset */
8006 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK2_EN        ((uint32_t)0x00000004)          /*!< When 1, enables Bank2 of the SRAM */
8007 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK3_EN] Bits */
8008 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN_OFS    ( 3)                            /*!< BNK3_EN Bit Offset */
8009 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK3_EN        ((uint32_t)0x00000008)          /*!< When 1, enables Bank3 of the SRAM */
8010 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK4_EN] Bits */
8011 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN_OFS    ( 4)                            /*!< BNK4_EN Bit Offset */
8012 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK4_EN        ((uint32_t)0x00000010)          /*!< When 1, enables Bank4 of the SRAM */
8013 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK5_EN] Bits */
8014 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN_OFS    ( 5)                            /*!< BNK5_EN Bit Offset */
8015 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK5_EN        ((uint32_t)0x00000020)          /*!< When 1, enables Bank5 of the SRAM */
8016 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK6_EN] Bits */
8017 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN_OFS    ( 6)                            /*!< BNK6_EN Bit Offset */
8018 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK6_EN        ((uint32_t)0x00000040)          /*!< When 1, enables Bank6 of the SRAM */
8019 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK7_EN] Bits */
8020 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN_OFS    ( 7)                            /*!< BNK7_EN Bit Offset */
8021 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK7_EN        ((uint32_t)0x00000080)          /*!< When 1, enables Bank7 of the SRAM */
8022 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK8_EN] Bits */
8023 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN_OFS    ( 8)                            /*!< BNK8_EN Bit Offset */
8024 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK8_EN        ((uint32_t)0x00000100)          /*!< When 1, enables Bank8 of the SRAM */
8025 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK9_EN] Bits */
8026 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN_OFS    ( 9)                            /*!< BNK9_EN Bit Offset */
8027 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK9_EN        ((uint32_t)0x00000200)          /*!< When 1, enables Bank9 of the SRAM */
8028 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK10_EN] Bits */
8029 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN_OFS   (10)                            /*!< BNK10_EN Bit Offset */
8030 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK10_EN       ((uint32_t)0x00000400)          /*!< When 1, enables Bank10 of the SRAM */
8031 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK11_EN] Bits */
8032 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN_OFS   (11)                            /*!< BNK11_EN Bit Offset */
8033 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK11_EN       ((uint32_t)0x00000800)          /*!< When 1, enables Bank11 of the SRAM */
8034 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK12_EN] Bits */
8035 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN_OFS   (12)                            /*!< BNK12_EN Bit Offset */
8036 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK12_EN       ((uint32_t)0x00001000)          /*!< When 1, enables Bank12 of the SRAM */
8037 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK13_EN] Bits */
8038 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN_OFS   (13)                            /*!< BNK13_EN Bit Offset */
8039 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK13_EN       ((uint32_t)0x00002000)          /*!< When 1, enables Bank13 of the SRAM */
8040 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK14_EN] Bits */
8041 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN_OFS   (14)                            /*!< BNK14_EN Bit Offset */
8042 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK14_EN       ((uint32_t)0x00004000)          /*!< When 1, enables Bank14 of the SRAM */
8043 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK15_EN] Bits */
8044 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN_OFS   (15)                            /*!< BNK15_EN Bit Offset */
8045 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK15_EN       ((uint32_t)0x00008000)          /*!< When 1, enables Bank15 of the SRAM */
8046 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK16_EN] Bits */
8047 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN_OFS   (16)                            /*!< BNK16_EN Bit Offset */
8048 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK16_EN       ((uint32_t)0x00010000)          /*!< When 1, enables Bank16 of the SRAM */
8049 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK17_EN] Bits */
8050 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN_OFS   (17)                            /*!< BNK17_EN Bit Offset */
8051 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK17_EN       ((uint32_t)0x00020000)          /*!< When 1, enables Bank17 of the SRAM */
8052 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK18_EN] Bits */
8053 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN_OFS   (18)                            /*!< BNK18_EN Bit Offset */
8054 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK18_EN       ((uint32_t)0x00040000)          /*!< When 1, enables Bank18 of the SRAM */
8055 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK19_EN] Bits */
8056 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN_OFS   (19)                            /*!< BNK19_EN Bit Offset */
8057 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK19_EN       ((uint32_t)0x00080000)          /*!< When 1, enables Bank19 of the SRAM */
8058 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK20_EN] Bits */
8059 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN_OFS   (20)                            /*!< BNK20_EN Bit Offset */
8060 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK20_EN       ((uint32_t)0x00100000)          /*!< When 1, enables Bank20 of the SRAM */
8061 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK21_EN] Bits */
8062 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN_OFS   (21)                            /*!< BNK21_EN Bit Offset */
8063 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK21_EN       ((uint32_t)0x00200000)          /*!< When 1, enables Bank21 of the SRAM */
8064 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK22_EN] Bits */
8065 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN_OFS   (22)                            /*!< BNK22_EN Bit Offset */
8066 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK22_EN       ((uint32_t)0x00400000)          /*!< When 1, enables Bank22 of the SRAM */
8067 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK23_EN] Bits */
8068 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN_OFS   (23)                            /*!< BNK23_EN Bit Offset */
8069 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK23_EN       ((uint32_t)0x00800000)          /*!< When 1, enables Bank23 of the SRAM */
8070 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK24_EN] Bits */
8071 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN_OFS   (24)                            /*!< BNK24_EN Bit Offset */
8072 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK24_EN       ((uint32_t)0x01000000)          /*!< When 1, enables Bank24 of the SRAM */
8073 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK25_EN] Bits */
8074 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN_OFS   (25)                            /*!< BNK25_EN Bit Offset */
8075 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK25_EN       ((uint32_t)0x02000000)          /*!< When 1, enables Bank25 of the SRAM */
8076 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK26_EN] Bits */
8077 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN_OFS   (26)                            /*!< BNK26_EN Bit Offset */
8078 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK26_EN       ((uint32_t)0x04000000)          /*!< When 1, enables Bank26 of the SRAM */
8079 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK27_EN] Bits */
8080 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN_OFS   (27)                            /*!< BNK27_EN Bit Offset */
8081 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK27_EN       ((uint32_t)0x08000000)          /*!< When 1, enables Bank27 of the SRAM */
8082 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK28_EN] Bits */
8083 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN_OFS   (28)                            /*!< BNK28_EN Bit Offset */
8084 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK28_EN       ((uint32_t)0x10000000)          /*!< When 1, enables Bank28 of the SRAM */
8085 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK29_EN] Bits */
8086 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN_OFS   (29)                            /*!< BNK29_EN Bit Offset */
8087 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK29_EN       ((uint32_t)0x20000000)          /*!< When 1, enables Bank29 of the SRAM */
8088 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK30_EN] Bits */
8089 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN_OFS   (30)                            /*!< BNK30_EN Bit Offset */
8090 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK30_EN       ((uint32_t)0x40000000)          /*!< When 1, enables Bank30 of the SRAM */
8091 /* SYSCTL_A_SRAM_BANKEN_CTL0[BNK31_EN] Bits */
8092 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN_OFS   (31)                            /*!< BNK31_EN Bit Offset */
8093 #define SYSCTL_A_SRAM_BANKEN_CTL0_BNK31_EN       ((uint32_t)0x80000000)          /*!< When 1, enables Bank31 of the SRAM */
8094 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK32_EN] Bits */
8095 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN_OFS   ( 0)                            /*!< BNK32_EN Bit Offset */
8096 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK32_EN       ((uint32_t)0x00000001)          /*!< When 1, enables Bank32 of the SRAM */
8097 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK33_EN] Bits */
8098 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN_OFS   ( 1)                            /*!< BNK33_EN Bit Offset */
8099 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK33_EN       ((uint32_t)0x00000002)          /*!< When 1, enables Bank33 of the SRAM */
8100 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK34_EN] Bits */
8101 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN_OFS   ( 2)                            /*!< BNK34_EN Bit Offset */
8102 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK34_EN       ((uint32_t)0x00000004)          /*!< When 1, enables Bank34 of the SRAM */
8103 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK35_EN] Bits */
8104 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN_OFS   ( 3)                            /*!< BNK35_EN Bit Offset */
8105 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK35_EN       ((uint32_t)0x00000008)          /*!< When 1, enables Bank35 of the SRAM */
8106 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK36_EN] Bits */
8107 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN_OFS   ( 4)                            /*!< BNK36_EN Bit Offset */
8108 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK36_EN       ((uint32_t)0x00000010)          /*!< When 1, enables Bank36 of the SRAM */
8109 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK37_EN] Bits */
8110 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN_OFS   ( 5)                            /*!< BNK37_EN Bit Offset */
8111 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK37_EN       ((uint32_t)0x00000020)          /*!< When 1, enables Bank37 of the SRAM */
8112 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK38_EN] Bits */
8113 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN_OFS   ( 6)                            /*!< BNK38_EN Bit Offset */
8114 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK38_EN       ((uint32_t)0x00000040)          /*!< When 1, enables Bank38 of the SRAM */
8115 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK39_EN] Bits */
8116 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN_OFS   ( 7)                            /*!< BNK39_EN Bit Offset */
8117 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK39_EN       ((uint32_t)0x00000080)          /*!< When 1, enables Bank39 of the SRAM */
8118 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK40_EN] Bits */
8119 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN_OFS   ( 8)                            /*!< BNK40_EN Bit Offset */
8120 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK40_EN       ((uint32_t)0x00000100)          /*!< When 1, enables Bank40 of the SRAM */
8121 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK41_EN] Bits */
8122 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN_OFS   ( 9)                            /*!< BNK41_EN Bit Offset */
8123 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK41_EN       ((uint32_t)0x00000200)          /*!< When 1, enables Bank41 of the SRAM */
8124 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK42_EN] Bits */
8125 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN_OFS   (10)                            /*!< BNK42_EN Bit Offset */
8126 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK42_EN       ((uint32_t)0x00000400)          /*!< When 1, enables Bank42 of the SRAM */
8127 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK43_EN] Bits */
8128 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN_OFS   (11)                            /*!< BNK43_EN Bit Offset */
8129 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK43_EN       ((uint32_t)0x00000800)          /*!< When 1, enables Bank43 of the SRAM */
8130 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK44_EN] Bits */
8131 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN_OFS   (12)                            /*!< BNK44_EN Bit Offset */
8132 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK44_EN       ((uint32_t)0x00001000)          /*!< When 1, enables Bank44 of the SRAM */
8133 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK45_EN] Bits */
8134 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN_OFS   (13)                            /*!< BNK45_EN Bit Offset */
8135 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK45_EN       ((uint32_t)0x00002000)          /*!< When 1, enables Bank45 of the SRAM */
8136 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK46_EN] Bits */
8137 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN_OFS   (14)                            /*!< BNK46_EN Bit Offset */
8138 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK46_EN       ((uint32_t)0x00004000)          /*!< When 1, enables Bank46 of the SRAM */
8139 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK47_EN] Bits */
8140 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN_OFS   (15)                            /*!< BNK47_EN Bit Offset */
8141 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK47_EN       ((uint32_t)0x00008000)          /*!< When 1, enables Bank47 of the SRAM */
8142 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK48_EN] Bits */
8143 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN_OFS   (16)                            /*!< BNK48_EN Bit Offset */
8144 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK48_EN       ((uint32_t)0x00010000)          /*!< When 1, enables Bank48 of the SRAM */
8145 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK49_EN] Bits */
8146 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN_OFS   (17)                            /*!< BNK49_EN Bit Offset */
8147 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK49_EN       ((uint32_t)0x00020000)          /*!< When 1, enables Bank49 of the SRAM */
8148 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK50_EN] Bits */
8149 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN_OFS   (18)                            /*!< BNK50_EN Bit Offset */
8150 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK50_EN       ((uint32_t)0x00040000)          /*!< When 1, enables Bank50 of the SRAM */
8151 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK51_EN] Bits */
8152 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN_OFS   (19)                            /*!< BNK51_EN Bit Offset */
8153 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK51_EN       ((uint32_t)0x00080000)          /*!< When 1, enables Bank51 of the SRAM */
8154 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK52_EN] Bits */
8155 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN_OFS   (20)                            /*!< BNK52_EN Bit Offset */
8156 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK52_EN       ((uint32_t)0x00100000)          /*!< When 1, enables Bank52 of the SRAM */
8157 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK53_EN] Bits */
8158 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN_OFS   (21)                            /*!< BNK53_EN Bit Offset */
8159 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK53_EN       ((uint32_t)0x00200000)          /*!< When 1, enables Bank53 of the SRAM */
8160 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK54_EN] Bits */
8161 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN_OFS   (22)                            /*!< BNK54_EN Bit Offset */
8162 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK54_EN       ((uint32_t)0x00400000)          /*!< When 1, enables Bank54 of the SRAM */
8163 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK55_EN] Bits */
8164 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN_OFS   (23)                            /*!< BNK55_EN Bit Offset */
8165 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK55_EN       ((uint32_t)0x00800000)          /*!< When 1, enables Bank55 of the SRAM */
8166 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK56_EN] Bits */
8167 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN_OFS   (24)                            /*!< BNK56_EN Bit Offset */
8168 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK56_EN       ((uint32_t)0x01000000)          /*!< When 1, enables Bank56 of the SRAM */
8169 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK57_EN] Bits */
8170 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN_OFS   (25)                            /*!< BNK57_EN Bit Offset */
8171 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK57_EN       ((uint32_t)0x02000000)          /*!< When 1, enables Bank57 of the SRAM */
8172 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK58_EN] Bits */
8173 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN_OFS   (26)                            /*!< BNK58_EN Bit Offset */
8174 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK58_EN       ((uint32_t)0x04000000)          /*!< When 1, enables Bank58 of the SRAM */
8175 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK59_EN] Bits */
8176 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN_OFS   (27)                            /*!< BNK59_EN Bit Offset */
8177 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK59_EN       ((uint32_t)0x08000000)          /*!< When 1, enables Bank59 of the SRAM */
8178 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK60_EN] Bits */
8179 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN_OFS   (28)                            /*!< BNK60_EN Bit Offset */
8180 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK60_EN       ((uint32_t)0x10000000)          /*!< When 1, enables Bank60 of the SRAM */
8181 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK61_EN] Bits */
8182 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN_OFS   (29)                            /*!< BNK61_EN Bit Offset */
8183 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK61_EN       ((uint32_t)0x20000000)          /*!< When 1, enables Bank61 of the SRAM */
8184 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK62_EN] Bits */
8185 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN_OFS   (30)                            /*!< BNK62_EN Bit Offset */
8186 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK62_EN       ((uint32_t)0x40000000)          /*!< When 1, enables Bank62 of the SRAM */
8187 /* SYSCTL_A_SRAM_BANKEN_CTL1[BNK63_EN] Bits */
8188 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN_OFS   (31)                            /*!< BNK63_EN Bit Offset */
8189 #define SYSCTL_A_SRAM_BANKEN_CTL1_BNK63_EN       ((uint32_t)0x80000000)          /*!< When 1, enables Bank63 of the SRAM */
8190 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK64_EN] Bits */
8191 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN_OFS   ( 0)                            /*!< BNK64_EN Bit Offset */
8192 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK64_EN       ((uint32_t)0x00000001)          /*!< When 1, enables Bank64 of the SRAM */
8193 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK65_EN] Bits */
8194 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN_OFS   ( 1)                            /*!< BNK65_EN Bit Offset */
8195 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK65_EN       ((uint32_t)0x00000002)          /*!< When 1, enables Bank65 of the SRAM */
8196 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK66_EN] Bits */
8197 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN_OFS   ( 2)                            /*!< BNK66_EN Bit Offset */
8198 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK66_EN       ((uint32_t)0x00000004)          /*!< When 1, enables Bank66 of the SRAM */
8199 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK67_EN] Bits */
8200 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN_OFS   ( 3)                            /*!< BNK67_EN Bit Offset */
8201 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK67_EN       ((uint32_t)0x00000008)          /*!< When 1, enables Bank67 of the SRAM */
8202 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK68_EN] Bits */
8203 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN_OFS   ( 4)                            /*!< BNK68_EN Bit Offset */
8204 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK68_EN       ((uint32_t)0x00000010)          /*!< When 1, enables Bank68 of the SRAM */
8205 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK69_EN] Bits */
8206 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN_OFS   ( 5)                            /*!< BNK69_EN Bit Offset */
8207 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK69_EN       ((uint32_t)0x00000020)          /*!< When 1, enables Bank69 of the SRAM */
8208 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK70_EN] Bits */
8209 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN_OFS   ( 6)                            /*!< BNK70_EN Bit Offset */
8210 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK70_EN       ((uint32_t)0x00000040)          /*!< When 1, enables Bank70 of the SRAM */
8211 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK71_EN] Bits */
8212 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN_OFS   ( 7)                            /*!< BNK71_EN Bit Offset */
8213 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK71_EN       ((uint32_t)0x00000080)          /*!< When 1, enables Bank71 of the SRAM */
8214 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK72_EN] Bits */
8215 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN_OFS   ( 8)                            /*!< BNK72_EN Bit Offset */
8216 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK72_EN       ((uint32_t)0x00000100)          /*!< When 1, enables Bank72 of the SRAM */
8217 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK73_EN] Bits */
8218 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN_OFS   ( 9)                            /*!< BNK73_EN Bit Offset */
8219 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK73_EN       ((uint32_t)0x00000200)          /*!< When 1, enables Bank73 of the SRAM */
8220 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK74_EN] Bits */
8221 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN_OFS   (10)                            /*!< BNK74_EN Bit Offset */
8222 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK74_EN       ((uint32_t)0x00000400)          /*!< When 1, enables Bank74 of the SRAM */
8223 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK75_EN] Bits */
8224 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN_OFS   (11)                            /*!< BNK75_EN Bit Offset */
8225 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK75_EN       ((uint32_t)0x00000800)          /*!< When 1, enables Bank75 of the SRAM */
8226 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK76_EN] Bits */
8227 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN_OFS   (12)                            /*!< BNK76_EN Bit Offset */
8228 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK76_EN       ((uint32_t)0x00001000)          /*!< When 1, enables Bank76 of the SRAM */
8229 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK77_EN] Bits */
8230 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN_OFS   (13)                            /*!< BNK77_EN Bit Offset */
8231 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK77_EN       ((uint32_t)0x00002000)          /*!< When 1, enables Bank77 of the SRAM */
8232 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK78_EN] Bits */
8233 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN_OFS   (14)                            /*!< BNK78_EN Bit Offset */
8234 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK78_EN       ((uint32_t)0x00004000)          /*!< When 1, enables Bank78 of the SRAM */
8235 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK79_EN] Bits */
8236 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN_OFS   (15)                            /*!< BNK79_EN Bit Offset */
8237 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK79_EN       ((uint32_t)0x00008000)          /*!< When 1, enables Bank79 of the SRAM */
8238 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK80_EN] Bits */
8239 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN_OFS   (16)                            /*!< BNK80_EN Bit Offset */
8240 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK80_EN       ((uint32_t)0x00010000)          /*!< When 1, enables Bank80 of the SRAM */
8241 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK81_EN] Bits */
8242 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN_OFS   (17)                            /*!< BNK81_EN Bit Offset */
8243 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK81_EN       ((uint32_t)0x00020000)          /*!< When 1, enables Bank81 of the SRAM */
8244 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK82_EN] Bits */
8245 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN_OFS   (18)                            /*!< BNK82_EN Bit Offset */
8246 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK82_EN       ((uint32_t)0x00040000)          /*!< When 1, enables Bank82 of the SRAM */
8247 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK83_EN] Bits */
8248 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN_OFS   (19)                            /*!< BNK83_EN Bit Offset */
8249 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK83_EN       ((uint32_t)0x00080000)          /*!< When 1, enables Bank83 of the SRAM */
8250 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK84_EN] Bits */
8251 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN_OFS   (20)                            /*!< BNK84_EN Bit Offset */
8252 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK84_EN       ((uint32_t)0x00100000)          /*!< When 1, enables Bank84 of the SRAM */
8253 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK85_EN] Bits */
8254 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN_OFS   (21)                            /*!< BNK85_EN Bit Offset */
8255 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK85_EN       ((uint32_t)0x00200000)          /*!< When 1, enables Bank85 of the SRAM */
8256 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK86_EN] Bits */
8257 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN_OFS   (22)                            /*!< BNK86_EN Bit Offset */
8258 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK86_EN       ((uint32_t)0x00400000)          /*!< When 1, enables Bank86 of the SRAM */
8259 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK87_EN] Bits */
8260 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN_OFS   (23)                            /*!< BNK87_EN Bit Offset */
8261 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK87_EN       ((uint32_t)0x00800000)          /*!< When 1, enables Bank87 of the SRAM */
8262 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK88_EN] Bits */
8263 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN_OFS   (24)                            /*!< BNK88_EN Bit Offset */
8264 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK88_EN       ((uint32_t)0x01000000)          /*!< When 1, enables Bank88 of the SRAM */
8265 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK89_EN] Bits */
8266 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN_OFS   (25)                            /*!< BNK89_EN Bit Offset */
8267 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK89_EN       ((uint32_t)0x02000000)          /*!< When 1, enables Bank89 of the SRAM */
8268 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK90_EN] Bits */
8269 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN_OFS   (26)                            /*!< BNK90_EN Bit Offset */
8270 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK90_EN       ((uint32_t)0x04000000)          /*!< When 1, enables Bank90 of the SRAM */
8271 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK91_EN] Bits */
8272 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN_OFS   (27)                            /*!< BNK91_EN Bit Offset */
8273 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK91_EN       ((uint32_t)0x08000000)          /*!< When 1, enables Bank91 of the SRAM */
8274 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK92_EN] Bits */
8275 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN_OFS   (28)                            /*!< BNK92_EN Bit Offset */
8276 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK92_EN       ((uint32_t)0x10000000)          /*!< When 1, enables Bank92 of the SRAM */
8277 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK93_EN] Bits */
8278 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN_OFS   (29)                            /*!< BNK93_EN Bit Offset */
8279 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK93_EN       ((uint32_t)0x20000000)          /*!< When 1, enables Bank93 of the SRAM */
8280 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK94_EN] Bits */
8281 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN_OFS   (30)                            /*!< BNK94_EN Bit Offset */
8282 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK94_EN       ((uint32_t)0x40000000)          /*!< When 1, enables Bank94 of the SRAM */
8283 /* SYSCTL_A_SRAM_BANKEN_CTL2[BNK95_EN] Bits */
8284 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN_OFS   (31)                            /*!< BNK95_EN Bit Offset */
8285 #define SYSCTL_A_SRAM_BANKEN_CTL2_BNK95_EN       ((uint32_t)0x80000000)          /*!< When 1, enables Bank95 of the SRAM */
8286 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK96_EN] Bits */
8287 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN_OFS   ( 0)                            /*!< BNK96_EN Bit Offset */
8288 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK96_EN       ((uint32_t)0x00000001)          /*!< When 1, enables Bank96 of the SRAM */
8289 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK97_EN] Bits */
8290 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN_OFS   ( 1)                            /*!< BNK97_EN Bit Offset */
8291 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK97_EN       ((uint32_t)0x00000002)          /*!< When 1, enables Bank97 of the SRAM */
8292 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK98_EN] Bits */
8293 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN_OFS   ( 2)                            /*!< BNK98_EN Bit Offset */
8294 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK98_EN       ((uint32_t)0x00000004)          /*!< When 1, enables Bank98 of the SRAM */
8295 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK99_EN] Bits */
8296 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN_OFS   ( 3)                            /*!< BNK99_EN Bit Offset */
8297 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK99_EN       ((uint32_t)0x00000008)          /*!< When 1, enables Bank99 of the SRAM */
8298 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK100_EN] Bits */
8299 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN_OFS  ( 4)                            /*!< BNK100_EN Bit Offset */
8300 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK100_EN      ((uint32_t)0x00000010)          /*!< When 1, enables Bank100 of the SRAM */
8301 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK101_EN] Bits */
8302 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN_OFS  ( 5)                            /*!< BNK101_EN Bit Offset */
8303 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK101_EN      ((uint32_t)0x00000020)          /*!< When 1, enables Bank101 of the SRAM */
8304 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK102_EN] Bits */
8305 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN_OFS  ( 6)                            /*!< BNK102_EN Bit Offset */
8306 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK102_EN      ((uint32_t)0x00000040)          /*!< When 1, enables Bank102 of the SRAM */
8307 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK103_EN] Bits */
8308 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN_OFS  ( 7)                            /*!< BNK103_EN Bit Offset */
8309 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK103_EN      ((uint32_t)0x00000080)          /*!< When 1, enables Bank103 of the SRAM */
8310 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK104_EN] Bits */
8311 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN_OFS  ( 8)                            /*!< BNK104_EN Bit Offset */
8312 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK104_EN      ((uint32_t)0x00000100)          /*!< When 1, enables Bank104 of the SRAM */
8313 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK105_EN] Bits */
8314 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN_OFS  ( 9)                            /*!< BNK105_EN Bit Offset */
8315 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK105_EN      ((uint32_t)0x00000200)          /*!< When 1, enables Bank105 of the SRAM */
8316 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK106_EN] Bits */
8317 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN_OFS  (10)                            /*!< BNK106_EN Bit Offset */
8318 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK106_EN      ((uint32_t)0x00000400)          /*!< When 1, enables Bank106 of the SRAM */
8319 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK107_EN] Bits */
8320 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN_OFS  (11)                            /*!< BNK107_EN Bit Offset */
8321 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK107_EN      ((uint32_t)0x00000800)          /*!< When 1, enables Bank107 of the SRAM */
8322 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK108_EN] Bits */
8323 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN_OFS  (12)                            /*!< BNK108_EN Bit Offset */
8324 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK108_EN      ((uint32_t)0x00001000)          /*!< When 1, enables Bank108 of the SRAM */
8325 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK109_EN] Bits */
8326 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN_OFS  (13)                            /*!< BNK109_EN Bit Offset */
8327 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK109_EN      ((uint32_t)0x00002000)          /*!< When 1, enables Bank109 of the SRAM */
8328 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK110_EN] Bits */
8329 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN_OFS  (14)                            /*!< BNK110_EN Bit Offset */
8330 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK110_EN      ((uint32_t)0x00004000)          /*!< When 1, enables Bank110 of the SRAM */
8331 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK111_EN] Bits */
8332 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN_OFS  (15)                            /*!< BNK111_EN Bit Offset */
8333 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK111_EN      ((uint32_t)0x00008000)          /*!< When 1, enables Bank111 of the SRAM */
8334 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK112_EN] Bits */
8335 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN_OFS  (16)                            /*!< BNK112_EN Bit Offset */
8336 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK112_EN      ((uint32_t)0x00010000)          /*!< When 1, enables Bank112 of the SRAM */
8337 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK113_EN] Bits */
8338 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN_OFS  (17)                            /*!< BNK113_EN Bit Offset */
8339 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK113_EN      ((uint32_t)0x00020000)          /*!< When 1, enables Bank113 of the SRAM */
8340 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK114_EN] Bits */
8341 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN_OFS  (18)                            /*!< BNK114_EN Bit Offset */
8342 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK114_EN      ((uint32_t)0x00040000)          /*!< When 1, enables Bank114 of the SRAM */
8343 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK115_EN] Bits */
8344 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN_OFS  (19)                            /*!< BNK115_EN Bit Offset */
8345 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK115_EN      ((uint32_t)0x00080000)          /*!< When 1, enables Bank115 of the SRAM */
8346 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK116_EN] Bits */
8347 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN_OFS  (20)                            /*!< BNK116_EN Bit Offset */
8348 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK116_EN      ((uint32_t)0x00100000)          /*!< When 1, enables Bank116 of the SRAM */
8349 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK117_EN] Bits */
8350 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN_OFS  (21)                            /*!< BNK117_EN Bit Offset */
8351 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK117_EN      ((uint32_t)0x00200000)          /*!< When 1, enables Bank117 of the SRAM */
8352 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK118_EN] Bits */
8353 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN_OFS  (22)                            /*!< BNK118_EN Bit Offset */
8354 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK118_EN      ((uint32_t)0x00400000)          /*!< When 1, enables Bank118 of the SRAM */
8355 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK119_EN] Bits */
8356 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN_OFS  (23)                            /*!< BNK119_EN Bit Offset */
8357 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK119_EN      ((uint32_t)0x00800000)          /*!< When 1, enables Bank119 of the SRAM */
8358 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK120_EN] Bits */
8359 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN_OFS  (24)                            /*!< BNK120_EN Bit Offset */
8360 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK120_EN      ((uint32_t)0x01000000)          /*!< When 1, enables Bank120 of the SRAM */
8361 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK121_EN] Bits */
8362 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN_OFS  (25)                            /*!< BNK121_EN Bit Offset */
8363 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK121_EN      ((uint32_t)0x02000000)          /*!< When 1, enables Bank121 of the SRAM */
8364 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK122_EN] Bits */
8365 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN_OFS  (26)                            /*!< BNK122_EN Bit Offset */
8366 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK122_EN      ((uint32_t)0x04000000)          /*!< When 1, enables Bank122 of the SRAM */
8367 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK123_EN] Bits */
8368 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN_OFS  (27)                            /*!< BNK123_EN Bit Offset */
8369 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK123_EN      ((uint32_t)0x08000000)          /*!< When 1, enables Bank123 of the SRAM */
8370 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK124_EN] Bits */
8371 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN_OFS  (28)                            /*!< BNK124_EN Bit Offset */
8372 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK124_EN      ((uint32_t)0x10000000)          /*!< When 1, enables Bank124 of the SRAM */
8373 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK125_EN] Bits */
8374 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN_OFS  (29)                            /*!< BNK125_EN Bit Offset */
8375 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK125_EN      ((uint32_t)0x20000000)          /*!< When 1, enables Bank125 of the SRAM */
8376 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK126_EN] Bits */
8377 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN_OFS  (30)                            /*!< BNK126_EN Bit Offset */
8378 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK126_EN      ((uint32_t)0x40000000)          /*!< When 1, enables Bank126 of the SRAM */
8379 /* SYSCTL_A_SRAM_BANKEN_CTL3[BNK127_EN] Bits */
8380 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN_OFS  (31)                            /*!< BNK127_EN Bit Offset */
8381 #define SYSCTL_A_SRAM_BANKEN_CTL3_BNK127_EN      ((uint32_t)0x80000000)          /*!< When 1, enables Bank127 of the SRAM */
8382 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK0_EN] Bits */
8383 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN_OFS    ( 0)                            /*!< BLK0_EN Bit Offset */
8384 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK0_EN        ((uint32_t)0x00000001)          /*!< Block0 is always retained in LPM3, LPM4 and LPM3.5 modes of operation */
8385 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK1_EN] Bits */
8386 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN_OFS    ( 1)                            /*!< BLK1_EN Bit Offset */
8387 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK1_EN        ((uint32_t)0x00000002)          /*!< When 1, Block1 of the SRAM is retained in LPM3 and LPM4 */
8388 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK2_EN] Bits */
8389 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN_OFS    ( 2)                            /*!< BLK2_EN Bit Offset */
8390 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK2_EN        ((uint32_t)0x00000004)          /*!< When 1, Block2 of the SRAM is retained in LPM3 and LPM4 */
8391 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK3_EN] Bits */
8392 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN_OFS    ( 3)                            /*!< BLK3_EN Bit Offset */
8393 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK3_EN        ((uint32_t)0x00000008)          /*!< When 1, Block3 of the SRAM is retained in LPM3 and LPM4 */
8394 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK4_EN] Bits */
8395 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN_OFS    ( 4)                            /*!< BLK4_EN Bit Offset */
8396 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK4_EN        ((uint32_t)0x00000010)          /*!< When 1, Block4 of the SRAM is retained in LPM3 and LPM4 */
8397 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK5_EN] Bits */
8398 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN_OFS    ( 5)                            /*!< BLK5_EN Bit Offset */
8399 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK5_EN        ((uint32_t)0x00000020)          /*!< When 1, Block5 of the SRAM is retained in LPM3 and LPM4 */
8400 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK6_EN] Bits */
8401 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN_OFS    ( 6)                            /*!< BLK6_EN Bit Offset */
8402 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK6_EN        ((uint32_t)0x00000040)          /*!< When 1, Block6 of the SRAM is retained in LPM3 and LPM4 */
8403 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK7_EN] Bits */
8404 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN_OFS    ( 7)                            /*!< BLK7_EN Bit Offset */
8405 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK7_EN        ((uint32_t)0x00000080)          /*!< When 1, Block7 of the SRAM is retained in LPM3 and LPM4 */
8406 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK8_EN] Bits */
8407 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN_OFS    ( 8)                            /*!< BLK8_EN Bit Offset */
8408 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK8_EN        ((uint32_t)0x00000100)          /*!< When 1, Block8 of the SRAM is retained in LPM3 and LPM4 */
8409 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK9_EN] Bits */
8410 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN_OFS    ( 9)                            /*!< BLK9_EN Bit Offset */
8411 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK9_EN        ((uint32_t)0x00000200)          /*!< When 1, Block9 of the SRAM is retained in LPM3 and LPM4 */
8412 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK10_EN] Bits */
8413 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN_OFS   (10)                            /*!< BLK10_EN Bit Offset */
8414 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK10_EN       ((uint32_t)0x00000400)          /*!< When 1, Block10 of the SRAM is retained in LPM3 and LPM4 */
8415 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK11_EN] Bits */
8416 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN_OFS   (11)                            /*!< BLK11_EN Bit Offset */
8417 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK11_EN       ((uint32_t)0x00000800)          /*!< When 1, Block11 of the SRAM is retained in LPM3 and LPM4 */
8418 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK12_EN] Bits */
8419 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN_OFS   (12)                            /*!< BLK12_EN Bit Offset */
8420 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK12_EN       ((uint32_t)0x00001000)          /*!< When 1, Block12 of the SRAM is retained in LPM3 and LPM4 */
8421 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK13_EN] Bits */
8422 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN_OFS   (13)                            /*!< BLK13_EN Bit Offset */
8423 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK13_EN       ((uint32_t)0x00002000)          /*!< When 1, Block13 of the SRAM is retained in LPM3 and LPM4 */
8424 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK14_EN] Bits */
8425 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN_OFS   (14)                            /*!< BLK14_EN Bit Offset */
8426 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK14_EN       ((uint32_t)0x00004000)          /*!< When 1, Block14 of the SRAM is retained in LPM3 and LPM4 */
8427 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK15_EN] Bits */
8428 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN_OFS   (15)                            /*!< BLK15_EN Bit Offset */
8429 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK15_EN       ((uint32_t)0x00008000)          /*!< When 1, Block15 of the SRAM is retained in LPM3 and LPM4 */
8430 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK16_EN] Bits */
8431 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN_OFS   (16)                            /*!< BLK16_EN Bit Offset */
8432 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK16_EN       ((uint32_t)0x00010000)          /*!< When 1, Block16 of the SRAM is retained in LPM3 and LPM4 */
8433 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK17_EN] Bits */
8434 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN_OFS   (17)                            /*!< BLK17_EN Bit Offset */
8435 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK17_EN       ((uint32_t)0x00020000)          /*!< When 1, Block17 of the SRAM is retained in LPM3 and LPM4 */
8436 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK18_EN] Bits */
8437 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN_OFS   (18)                            /*!< BLK18_EN Bit Offset */
8438 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK18_EN       ((uint32_t)0x00040000)          /*!< When 1, Block18 of the SRAM is retained in LPM3 and LPM4 */
8439 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK19_EN] Bits */
8440 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN_OFS   (19)                            /*!< BLK19_EN Bit Offset */
8441 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK19_EN       ((uint32_t)0x00080000)          /*!< When 1, Block19 of the SRAM is retained in LPM3 and LPM4 */
8442 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK20_EN] Bits */
8443 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN_OFS   (20)                            /*!< BLK20_EN Bit Offset */
8444 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK20_EN       ((uint32_t)0x00100000)          /*!< When 1, Block20 of the SRAM is retained in LPM3 and LPM4 */
8445 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK21_EN] Bits */
8446 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN_OFS   (21)                            /*!< BLK21_EN Bit Offset */
8447 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK21_EN       ((uint32_t)0x00200000)          /*!< When 1, Block21 of the SRAM is retained in LPM3 and LPM4 */
8448 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK22_EN] Bits */
8449 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN_OFS   (22)                            /*!< BLK22_EN Bit Offset */
8450 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK22_EN       ((uint32_t)0x00400000)          /*!< When 1, Block22 of the SRAM is retained in LPM3 and LPM4 */
8451 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK23_EN] Bits */
8452 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN_OFS   (23)                            /*!< BLK23_EN Bit Offset */
8453 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK23_EN       ((uint32_t)0x00800000)          /*!< When 1, Block23 of the SRAM is retained in LPM3 and LPM4 */
8454 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK24_EN] Bits */
8455 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN_OFS   (24)                            /*!< BLK24_EN Bit Offset */
8456 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK24_EN       ((uint32_t)0x01000000)          /*!< When 1, Block24 of the SRAM is retained in LPM3 and LPM4 */
8457 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK25_EN] Bits */
8458 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN_OFS   (25)                            /*!< BLK25_EN Bit Offset */
8459 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK25_EN       ((uint32_t)0x02000000)          /*!< When 1, Block25 of the SRAM is retained in LPM3 and LPM4 */
8460 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK26_EN] Bits */
8461 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN_OFS   (26)                            /*!< BLK26_EN Bit Offset */
8462 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK26_EN       ((uint32_t)0x04000000)          /*!< When 1, Block26 of the SRAM is retained in LPM3 and LPM4 */
8463 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK27_EN] Bits */
8464 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN_OFS   (27)                            /*!< BLK27_EN Bit Offset */
8465 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK27_EN       ((uint32_t)0x08000000)          /*!< When 1, Block27 of the SRAM is retained in LPM3 and LPM4 */
8466 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK28_EN] Bits */
8467 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN_OFS   (28)                            /*!< BLK28_EN Bit Offset */
8468 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK28_EN       ((uint32_t)0x10000000)          /*!< When 1, Block28 of the SRAM is retained in LPM3 and LPM4 */
8469 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK29_EN] Bits */
8470 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN_OFS   (29)                            /*!< BLK29_EN Bit Offset */
8471 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK29_EN       ((uint32_t)0x20000000)          /*!< When 1, Block29 of the SRAM is retained in LPM3 and LPM4 */
8472 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK30_EN] Bits */
8473 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN_OFS   (30)                            /*!< BLK30_EN Bit Offset */
8474 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK30_EN       ((uint32_t)0x40000000)          /*!< When 1, Block30 of the SRAM is retained in LPM3 and LPM4 */
8475 /* SYSCTL_A_SRAM_BLKRET_CTL0[BLK31_EN] Bits */
8476 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN_OFS   (31)                            /*!< BLK31_EN Bit Offset */
8477 #define SYSCTL_A_SRAM_BLKRET_CTL0_BLK31_EN       ((uint32_t)0x80000000)          /*!< When 1, Block31 of the SRAM is retained in LPM3 and LPM4 */
8478 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK32_EN] Bits */
8479 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN_OFS   ( 0)                            /*!< BLK32_EN Bit Offset */
8480 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK32_EN       ((uint32_t)0x00000001)          /*!< When 1, Block32 of the SRAM is retained in LPM3 and LPM4 */
8481 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK33_EN] Bits */
8482 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN_OFS   ( 1)                            /*!< BLK33_EN Bit Offset */
8483 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK33_EN       ((uint32_t)0x00000002)          /*!< When 1, Block33 of the SRAM is retained in LPM3 and LPM4 */
8484 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK34_EN] Bits */
8485 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN_OFS   ( 2)                            /*!< BLK34_EN Bit Offset */
8486 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK34_EN       ((uint32_t)0x00000004)          /*!< When 1, Block34 of the SRAM is retained in LPM3 and LPM4 */
8487 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK35_EN] Bits */
8488 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN_OFS   ( 3)                            /*!< BLK35_EN Bit Offset */
8489 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK35_EN       ((uint32_t)0x00000008)          /*!< When 1, Block35 of the SRAM is retained in LPM3 and LPM4 */
8490 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK36_EN] Bits */
8491 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN_OFS   ( 4)                            /*!< BLK36_EN Bit Offset */
8492 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK36_EN       ((uint32_t)0x00000010)          /*!< When 1, Block36 of the SRAM is retained in LPM3 and LPM4 */
8493 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK37_EN] Bits */
8494 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN_OFS   ( 5)                            /*!< BLK37_EN Bit Offset */
8495 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK37_EN       ((uint32_t)0x00000020)          /*!< When 1, Block37 of the SRAM is retained in LPM3 and LPM4 */
8496 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK38_EN] Bits */
8497 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN_OFS   ( 6)                            /*!< BLK38_EN Bit Offset */
8498 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK38_EN       ((uint32_t)0x00000040)          /*!< When 1, Block38 of the SRAM is retained in LPM3 and LPM4 */
8499 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK39_EN] Bits */
8500 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN_OFS   ( 7)                            /*!< BLK39_EN Bit Offset */
8501 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK39_EN       ((uint32_t)0x00000080)          /*!< When 1, Block39 of the SRAM is retained in LPM3 and LPM4 */
8502 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK40_EN] Bits */
8503 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN_OFS   ( 8)                            /*!< BLK40_EN Bit Offset */
8504 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK40_EN       ((uint32_t)0x00000100)          /*!< When 1, Block40 of the SRAM is retained in LPM3 and LPM4 */
8505 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK41_EN] Bits */
8506 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN_OFS   ( 9)                            /*!< BLK41_EN Bit Offset */
8507 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK41_EN       ((uint32_t)0x00000200)          /*!< When 1, Block41 of the SRAM is retained in LPM3 and LPM4 */
8508 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK42_EN] Bits */
8509 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN_OFS   (10)                            /*!< BLK42_EN Bit Offset */
8510 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK42_EN       ((uint32_t)0x00000400)          /*!< When 1, Block42 of the SRAM is retained in LPM3 and LPM4 */
8511 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK43_EN] Bits */
8512 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN_OFS   (11)                            /*!< BLK43_EN Bit Offset */
8513 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK43_EN       ((uint32_t)0x00000800)          /*!< When 1, Block43 of the SRAM is retained in LPM3 and LPM4 */
8514 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK44_EN] Bits */
8515 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN_OFS   (12)                            /*!< BLK44_EN Bit Offset */
8516 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK44_EN       ((uint32_t)0x00001000)          /*!< When 1, Block44 of the SRAM is retained in LPM3 and LPM4 */
8517 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK45_EN] Bits */
8518 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN_OFS   (13)                            /*!< BLK45_EN Bit Offset */
8519 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK45_EN       ((uint32_t)0x00002000)          /*!< When 1, Block45 of the SRAM is retained in LPM3 and LPM4 */
8520 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK46_EN] Bits */
8521 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN_OFS   (14)                            /*!< BLK46_EN Bit Offset */
8522 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK46_EN       ((uint32_t)0x00004000)          /*!< When 1, Block46 of the SRAM is retained in LPM3 and LPM4 */
8523 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK47_EN] Bits */
8524 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN_OFS   (15)                            /*!< BLK47_EN Bit Offset */
8525 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK47_EN       ((uint32_t)0x00008000)          /*!< When 1, Block47 of the SRAM is retained in LPM3 and LPM4 */
8526 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK48_EN] Bits */
8527 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN_OFS   (16)                            /*!< BLK48_EN Bit Offset */
8528 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK48_EN       ((uint32_t)0x00010000)          /*!< When 1, Block48 of the SRAM is retained in LPM3 and LPM4 */
8529 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK49_EN] Bits */
8530 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN_OFS   (17)                            /*!< BLK49_EN Bit Offset */
8531 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK49_EN       ((uint32_t)0x00020000)          /*!< When 1, Block49 of the SRAM is retained in LPM3 and LPM4 */
8532 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK50_EN] Bits */
8533 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN_OFS   (18)                            /*!< BLK50_EN Bit Offset */
8534 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK50_EN       ((uint32_t)0x00040000)          /*!< When 1, Block50 of the SRAM is retained in LPM3 and LPM4 */
8535 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK51_EN] Bits */
8536 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN_OFS   (19)                            /*!< BLK51_EN Bit Offset */
8537 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK51_EN       ((uint32_t)0x00080000)          /*!< When 1, Block51 of the SRAM is retained in LPM3 and LPM4 */
8538 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK52_EN] Bits */
8539 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN_OFS   (20)                            /*!< BLK52_EN Bit Offset */
8540 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK52_EN       ((uint32_t)0x00100000)          /*!< When 1, Block52 of the SRAM is retained in LPM3 and LPM4 */
8541 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK53_EN] Bits */
8542 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN_OFS   (21)                            /*!< BLK53_EN Bit Offset */
8543 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK53_EN       ((uint32_t)0x00200000)          /*!< When 1, Block53 of the SRAM is retained in LPM3 and LPM4 */
8544 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK54_EN] Bits */
8545 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN_OFS   (22)                            /*!< BLK54_EN Bit Offset */
8546 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK54_EN       ((uint32_t)0x00400000)          /*!< When 1, Block54 of the SRAM is retained in LPM3 and LPM4 */
8547 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK55_EN] Bits */
8548 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN_OFS   (23)                            /*!< BLK55_EN Bit Offset */
8549 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK55_EN       ((uint32_t)0x00800000)          /*!< When 1, Block55 of the SRAM is retained in LPM3 and LPM4 */
8550 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK56_EN] Bits */
8551 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN_OFS   (24)                            /*!< BLK56_EN Bit Offset */
8552 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK56_EN       ((uint32_t)0x01000000)          /*!< When 1, Block56 of the SRAM is retained in LPM3 and LPM4 */
8553 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK57_EN] Bits */
8554 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN_OFS   (25)                            /*!< BLK57_EN Bit Offset */
8555 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK57_EN       ((uint32_t)0x02000000)          /*!< When 1, Block57 of the SRAM is retained in LPM3 and LPM4 */
8556 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK58_EN] Bits */
8557 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN_OFS   (26)                            /*!< BLK58_EN Bit Offset */
8558 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK58_EN       ((uint32_t)0x04000000)          /*!< When 1, Block58 of the SRAM is retained in LPM3 and LPM4 */
8559 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK59_EN] Bits */
8560 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN_OFS   (27)                            /*!< BLK59_EN Bit Offset */
8561 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK59_EN       ((uint32_t)0x08000000)          /*!< When 1, Block59 of the SRAM is retained in LPM3 and LPM4 */
8562 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK60_EN] Bits */
8563 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN_OFS   (28)                            /*!< BLK60_EN Bit Offset */
8564 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK60_EN       ((uint32_t)0x10000000)          /*!< When 1, Block60 of the SRAM is retained in LPM3 and LPM4 */
8565 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK61_EN] Bits */
8566 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN_OFS   (29)                            /*!< BLK61_EN Bit Offset */
8567 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK61_EN       ((uint32_t)0x20000000)          /*!< When 1, Block61 of the SRAM is retained in LPM3 and LPM4 */
8568 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK62_EN] Bits */
8569 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN_OFS   (30)                            /*!< BLK62_EN Bit Offset */
8570 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK62_EN       ((uint32_t)0x40000000)          /*!< When 1, Block62 of the SRAM is retained in LPM3 and LPM4 */
8571 /* SYSCTL_A_SRAM_BLKRET_CTL1[BLK63_EN] Bits */
8572 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN_OFS   (31)                            /*!< BLK63_EN Bit Offset */
8573 #define SYSCTL_A_SRAM_BLKRET_CTL1_BLK63_EN       ((uint32_t)0x80000000)          /*!< When 1, Block63 of the SRAM is retained in LPM3 and LPM4 */
8574 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK64_EN] Bits */
8575 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN_OFS   ( 0)                            /*!< BLK64_EN Bit Offset */
8576 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK64_EN       ((uint32_t)0x00000001)          /*!< When 1, Block64 of the SRAM is retained in LPM3 and LPM4 */
8577 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK65_EN] Bits */
8578 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN_OFS   ( 1)                            /*!< BLK65_EN Bit Offset */
8579 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK65_EN       ((uint32_t)0x00000002)          /*!< When 1, Block65 of the SRAM is retained in LPM3 and LPM4 */
8580 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK66_EN] Bits */
8581 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN_OFS   ( 2)                            /*!< BLK66_EN Bit Offset */
8582 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK66_EN       ((uint32_t)0x00000004)          /*!< When 1, Block66 of the SRAM is retained in LPM3 and LPM4 */
8583 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK67_EN] Bits */
8584 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN_OFS   ( 3)                            /*!< BLK67_EN Bit Offset */
8585 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK67_EN       ((uint32_t)0x00000008)          /*!< When 1, Block67 of the SRAM is retained in LPM3 and LPM4 */
8586 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK68_EN] Bits */
8587 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN_OFS   ( 4)                            /*!< BLK68_EN Bit Offset */
8588 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK68_EN       ((uint32_t)0x00000010)          /*!< When 1, Block68 of the SRAM is retained in LPM3 and LPM4 */
8589 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK69_EN] Bits */
8590 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN_OFS   ( 5)                            /*!< BLK69_EN Bit Offset */
8591 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK69_EN       ((uint32_t)0x00000020)          /*!< When 1, Block69 of the SRAM is retained in LPM3 and LPM4 */
8592 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK70_EN] Bits */
8593 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN_OFS   ( 6)                            /*!< BLK70_EN Bit Offset */
8594 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK70_EN       ((uint32_t)0x00000040)          /*!< When 1, Block70 of the SRAM is retained in LPM3 and LPM4 */
8595 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK71_EN] Bits */
8596 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN_OFS   ( 7)                            /*!< BLK71_EN Bit Offset */
8597 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK71_EN       ((uint32_t)0x00000080)          /*!< When 1, Block71 of the SRAM is retained in LPM3 and LPM4 */
8598 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK72_EN] Bits */
8599 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN_OFS   ( 8)                            /*!< BLK72_EN Bit Offset */
8600 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK72_EN       ((uint32_t)0x00000100)          /*!< When 1, Block72 of the SRAM is retained in LPM3 and LPM4 */
8601 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK73_EN] Bits */
8602 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN_OFS   ( 9)                            /*!< BLK73_EN Bit Offset */
8603 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK73_EN       ((uint32_t)0x00000200)          /*!< When 1, Block73 of the SRAM is retained in LPM3 and LPM4 */
8604 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK74_EN] Bits */
8605 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN_OFS   (10)                            /*!< BLK74_EN Bit Offset */
8606 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK74_EN       ((uint32_t)0x00000400)          /*!< When 1, Block74 of the SRAM is retained in LPM3 and LPM4 */
8607 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK75_EN] Bits */
8608 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN_OFS   (11)                            /*!< BLK75_EN Bit Offset */
8609 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK75_EN       ((uint32_t)0x00000800)          /*!< When 1, Block75 of the SRAM is retained in LPM3 and LPM4 */
8610 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK76_EN] Bits */
8611 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN_OFS   (12)                            /*!< BLK76_EN Bit Offset */
8612 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK76_EN       ((uint32_t)0x00001000)          /*!< When 1, Block76 of the SRAM is retained in LPM3 and LPM4 */
8613 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK77_EN] Bits */
8614 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN_OFS   (13)                            /*!< BLK77_EN Bit Offset */
8615 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK77_EN       ((uint32_t)0x00002000)          /*!< When 1, Block77 of the SRAM is retained in LPM3 and LPM4 */
8616 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK78_EN] Bits */
8617 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN_OFS   (14)                            /*!< BLK78_EN Bit Offset */
8618 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK78_EN       ((uint32_t)0x00004000)          /*!< When 1, Block78 of the SRAM is retained in LPM3 and LPM4 */
8619 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK79_EN] Bits */
8620 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN_OFS   (15)                            /*!< BLK79_EN Bit Offset */
8621 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK79_EN       ((uint32_t)0x00008000)          /*!< When 1, Block79 of the SRAM is retained in LPM3 and LPM4 */
8622 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK80_EN] Bits */
8623 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN_OFS   (16)                            /*!< BLK80_EN Bit Offset */
8624 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK80_EN       ((uint32_t)0x00010000)          /*!< When 1, Block80 of the SRAM is retained in LPM3 and LPM4 */
8625 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK81_EN] Bits */
8626 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN_OFS   (17)                            /*!< BLK81_EN Bit Offset */
8627 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK81_EN       ((uint32_t)0x00020000)          /*!< When 1, Block81 of the SRAM is retained in LPM3 and LPM4 */
8628 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK82_EN] Bits */
8629 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN_OFS   (18)                            /*!< BLK82_EN Bit Offset */
8630 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK82_EN       ((uint32_t)0x00040000)          /*!< When 1, Block82 of the SRAM is retained in LPM3 and LPM4 */
8631 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK83_EN] Bits */
8632 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN_OFS   (19)                            /*!< BLK83_EN Bit Offset */
8633 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK83_EN       ((uint32_t)0x00080000)          /*!< When 1, Block83 of the SRAM is retained in LPM3 and LPM4 */
8634 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK84_EN] Bits */
8635 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN_OFS   (20)                            /*!< BLK84_EN Bit Offset */
8636 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK84_EN       ((uint32_t)0x00100000)          /*!< When 1, Block84 of the SRAM is retained in LPM3 and LPM4 */
8637 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK85_EN] Bits */
8638 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN_OFS   (21)                            /*!< BLK85_EN Bit Offset */
8639 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK85_EN       ((uint32_t)0x00200000)          /*!< When 1, Block85 of the SRAM is retained in LPM3 and LPM4 */
8640 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK86_EN] Bits */
8641 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN_OFS   (22)                            /*!< BLK86_EN Bit Offset */
8642 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK86_EN       ((uint32_t)0x00400000)          /*!< When 1, Block86 of the SRAM is retained in LPM3 and LPM4 */
8643 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK87_EN] Bits */
8644 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN_OFS   (23)                            /*!< BLK87_EN Bit Offset */
8645 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK87_EN       ((uint32_t)0x00800000)          /*!< When 1, Block87 of the SRAM is retained in LPM3 and LPM4 */
8646 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK88_EN] Bits */
8647 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN_OFS   (24)                            /*!< BLK88_EN Bit Offset */
8648 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK88_EN       ((uint32_t)0x01000000)          /*!< When 1, Block88 of the SRAM is retained in LPM3 and LPM4 */
8649 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK89_EN] Bits */
8650 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN_OFS   (25)                            /*!< BLK89_EN Bit Offset */
8651 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK89_EN       ((uint32_t)0x02000000)          /*!< When 1, Block89 of the SRAM is retained in LPM3 and LPM4 */
8652 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK90_EN] Bits */
8653 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN_OFS   (26)                            /*!< BLK90_EN Bit Offset */
8654 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK90_EN       ((uint32_t)0x04000000)          /*!< When 1, Block90 of the SRAM is retained in LPM3 and LPM4 */
8655 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK91_EN] Bits */
8656 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN_OFS   (27)                            /*!< BLK91_EN Bit Offset */
8657 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK91_EN       ((uint32_t)0x08000000)          /*!< When 1, Block91 of the SRAM is retained in LPM3 and LPM4 */
8658 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK92_EN] Bits */
8659 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN_OFS   (28)                            /*!< BLK92_EN Bit Offset */
8660 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK92_EN       ((uint32_t)0x10000000)          /*!< When 1, Block92 of the SRAM is retained in LPM3 and LPM4 */
8661 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK93_EN] Bits */
8662 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN_OFS   (29)                            /*!< BLK93_EN Bit Offset */
8663 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK93_EN       ((uint32_t)0x20000000)          /*!< When 1, Block93 of the SRAM is retained in LPM3 and LPM4 */
8664 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK94_EN] Bits */
8665 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN_OFS   (30)                            /*!< BLK94_EN Bit Offset */
8666 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK94_EN       ((uint32_t)0x40000000)          /*!< When 1, Block94 of the SRAM is retained in LPM3 and LPM4 */
8667 /* SYSCTL_A_SRAM_BLKRET_CTL2[BLK95_EN] Bits */
8668 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN_OFS   (31)                            /*!< BLK95_EN Bit Offset */
8669 #define SYSCTL_A_SRAM_BLKRET_CTL2_BLK95_EN       ((uint32_t)0x80000000)          /*!< When 1, Block95 of the SRAM is retained in LPM3 and LPM4 */
8670 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK96_EN] Bits */
8671 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN_OFS   ( 0)                            /*!< BLK96_EN Bit Offset */
8672 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK96_EN       ((uint32_t)0x00000001)          /*!< When 1, Block96 of the SRAM is retained in LPM3 and LPM4 */
8673 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK97_EN] Bits */
8674 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN_OFS   ( 1)                            /*!< BLK97_EN Bit Offset */
8675 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK97_EN       ((uint32_t)0x00000002)          /*!< When 1, Block97 of the SRAM is retained in LPM3 and LPM4 */
8676 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK98_EN] Bits */
8677 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN_OFS   ( 2)                            /*!< BLK98_EN Bit Offset */
8678 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK98_EN       ((uint32_t)0x00000004)          /*!< When 1, Block98 of the SRAM is retained in LPM3 and LPM4 */
8679 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK99_EN] Bits */
8680 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN_OFS   ( 3)                            /*!< BLK99_EN Bit Offset */
8681 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK99_EN       ((uint32_t)0x00000008)          /*!< When 1, Block99 of the SRAM is retained in LPM3 and LPM4 */
8682 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK100_EN] Bits */
8683 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN_OFS  ( 4)                            /*!< BLK100_EN Bit Offset */
8684 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK100_EN      ((uint32_t)0x00000010)          /*!< When 1, Block100 of the SRAM is retained in LPM3 and LPM4 */
8685 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK101_EN] Bits */
8686 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN_OFS  ( 5)                            /*!< BLK101_EN Bit Offset */
8687 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK101_EN      ((uint32_t)0x00000020)          /*!< When 1, Block101 of the SRAM is retained in LPM3 and LPM4 */
8688 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK102_EN] Bits */
8689 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN_OFS  ( 6)                            /*!< BLK102_EN Bit Offset */
8690 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK102_EN      ((uint32_t)0x00000040)          /*!< When 1, Block102 of the SRAM is retained in LPM3 and LPM4 */
8691 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK103_EN] Bits */
8692 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN_OFS  ( 7)                            /*!< BLK103_EN Bit Offset */
8693 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK103_EN      ((uint32_t)0x00000080)          /*!< When 1, Block103 of the SRAM is retained in LPM3 and LPM4 */
8694 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK104_EN] Bits */
8695 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN_OFS  ( 8)                            /*!< BLK104_EN Bit Offset */
8696 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK104_EN      ((uint32_t)0x00000100)          /*!< When 1, Block104 of the SRAM is retained in LPM3 and LPM4 */
8697 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK105_EN] Bits */
8698 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN_OFS  ( 9)                            /*!< BLK105_EN Bit Offset */
8699 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK105_EN      ((uint32_t)0x00000200)          /*!< When 1, Block105 of the SRAM is retained in LPM3 and LPM4 */
8700 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK106_EN] Bits */
8701 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN_OFS  (10)                            /*!< BLK106_EN Bit Offset */
8702 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK106_EN      ((uint32_t)0x00000400)          /*!< When 1, Block106 of the SRAM is retained in LPM3 and LPM4 */
8703 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK107_EN] Bits */
8704 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN_OFS  (11)                            /*!< BLK107_EN Bit Offset */
8705 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK107_EN      ((uint32_t)0x00000800)          /*!< When 1, Block107 of the SRAM is retained in LPM3 and LPM4 */
8706 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK108_EN] Bits */
8707 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN_OFS  (12)                            /*!< BLK108_EN Bit Offset */
8708 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK108_EN      ((uint32_t)0x00001000)          /*!< When 1, Block108 of the SRAM is retained in LPM3 and LPM4 */
8709 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK109_EN] Bits */
8710 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN_OFS  (13)                            /*!< BLK109_EN Bit Offset */
8711 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK109_EN      ((uint32_t)0x00002000)          /*!< When 1, Block109 of the SRAM is retained in LPM3 and LPM4 */
8712 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK110_EN] Bits */
8713 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN_OFS  (14)                            /*!< BLK110_EN Bit Offset */
8714 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK110_EN      ((uint32_t)0x00004000)          /*!< When 1, Block110 of the SRAM is retained in LPM3 and LPM4 */
8715 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK111_EN] Bits */
8716 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN_OFS  (15)                            /*!< BLK111_EN Bit Offset */
8717 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK111_EN      ((uint32_t)0x00008000)          /*!< When 1, Block111 of the SRAM is retained in LPM3 and LPM4 */
8718 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK112_EN] Bits */
8719 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN_OFS  (16)                            /*!< BLK112_EN Bit Offset */
8720 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK112_EN      ((uint32_t)0x00010000)          /*!< When 1, Block112 of the SRAM is retained in LPM3 and LPM4 */
8721 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK113_EN] Bits */
8722 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN_OFS  (17)                            /*!< BLK113_EN Bit Offset */
8723 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK113_EN      ((uint32_t)0x00020000)          /*!< When 1, Block113 of the SRAM is retained in LPM3 and LPM4 */
8724 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK114_EN] Bits */
8725 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN_OFS  (18)                            /*!< BLK114_EN Bit Offset */
8726 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK114_EN      ((uint32_t)0x00040000)          /*!< When 1, Block114 of the SRAM is retained in LPM3 and LPM4 */
8727 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK115_EN] Bits */
8728 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN_OFS  (19)                            /*!< BLK115_EN Bit Offset */
8729 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK115_EN      ((uint32_t)0x00080000)          /*!< When 1, Block115 of the SRAM is retained in LPM3 and LPM4 */
8730 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK116_EN] Bits */
8731 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN_OFS  (20)                            /*!< BLK116_EN Bit Offset */
8732 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK116_EN      ((uint32_t)0x00100000)          /*!< When 1, Block116 of the SRAM is retained in LPM3 and LPM4 */
8733 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK117_EN] Bits */
8734 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN_OFS  (21)                            /*!< BLK117_EN Bit Offset */
8735 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK117_EN      ((uint32_t)0x00200000)          /*!< When 1, Block117 of the SRAM is retained in LPM3 and LPM4 */
8736 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK118_EN] Bits */
8737 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN_OFS  (22)                            /*!< BLK118_EN Bit Offset */
8738 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK118_EN      ((uint32_t)0x00400000)          /*!< When 1, Block118 of the SRAM is retained in LPM3 and LPM4 */
8739 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK119_EN] Bits */
8740 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN_OFS  (23)                            /*!< BLK119_EN Bit Offset */
8741 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK119_EN      ((uint32_t)0x00800000)          /*!< When 1, Block119 of the SRAM is retained in LPM3 and LPM4 */
8742 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK120_EN] Bits */
8743 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN_OFS  (24)                            /*!< BLK120_EN Bit Offset */
8744 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK120_EN      ((uint32_t)0x01000000)          /*!< When 1, Block120 of the SRAM is retained in LPM3 and LPM4 */
8745 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK121_EN] Bits */
8746 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN_OFS  (25)                            /*!< BLK121_EN Bit Offset */
8747 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK121_EN      ((uint32_t)0x02000000)          /*!< When 1, Block121 of the SRAM is retained in LPM3 and LPM4 */
8748 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK122_EN] Bits */
8749 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN_OFS  (26)                            /*!< BLK122_EN Bit Offset */
8750 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK122_EN      ((uint32_t)0x04000000)          /*!< When 1, Block122 of the SRAM is retained in LPM3 and LPM4 */
8751 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK123_EN] Bits */
8752 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN_OFS  (27)                            /*!< BLK123_EN Bit Offset */
8753 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK123_EN      ((uint32_t)0x08000000)          /*!< When 1, Block123 of the SRAM is retained in LPM3 and LPM4 */
8754 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK124_EN] Bits */
8755 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN_OFS  (28)                            /*!< BLK124_EN Bit Offset */
8756 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK124_EN      ((uint32_t)0x10000000)          /*!< When 1, Block124 of the SRAM is retained in LPM3 and LPM4 */
8757 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK125_EN] Bits */
8758 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN_OFS  (29)                            /*!< BLK125_EN Bit Offset */
8759 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK125_EN      ((uint32_t)0x20000000)          /*!< When 1, Block125 of the SRAM is retained in LPM3 and LPM4 */
8760 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK126_EN] Bits */
8761 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN_OFS  (30)                            /*!< BLK126_EN Bit Offset */
8762 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK126_EN      ((uint32_t)0x40000000)          /*!< When 1, Block126 of the SRAM is retained in LPM3 and LPM4 */
8763 /* SYSCTL_A_SRAM_BLKRET_CTL3[BLK127_EN] Bits */
8764 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN_OFS  (31)                            /*!< BLK127_EN Bit Offset */
8765 #define SYSCTL_A_SRAM_BLKRET_CTL3_BLK127_EN      ((uint32_t)0x80000000)          /*!< When 1, Block127 of the SRAM is retained in LPM3 and LPM4 */
8766 /* SYSCTL_A_SRAM_STAT[BNKEN_RDY] Bits */
8767 #define SYSCTL_A_SRAM_STAT_BNKEN_RDY_OFS         ( 0)                            /*!< BNKEN_RDY Bit Offset */
8768 #define SYSCTL_A_SRAM_STAT_BNKEN_RDY             ((uint32_t)0x00000001)          /*!< When 1, indicates SRAM is ready for access and banks can be  */
8769                                                                                  /* enabled/disabled. */
8770 /* SYSCTL_A_SRAM_STAT[BLKRET_RDY] Bits */
8771 #define SYSCTL_A_SRAM_STAT_BLKRET_RDY_OFS        ( 1)                            /*!< BLKRET_RDY Bit Offset */
8772 #define SYSCTL_A_SRAM_STAT_BLKRET_RDY            ((uint32_t)0x00000002)          /*!< When 1, indicates SRAM is ready for access and blocks can be  */
8773                                                                                  /* enabled/disabled for retention. */
8774 /* SYSCTL_A_MASTER_UNLOCK[UNLKEY] Bits */
8775 #define SYSCTL_A_MASTER_UNLOCK_UNLKEY_OFS        ( 0)                            /*!< UNLKEY Bit Offset */
8776 #define SYSCTL_A_MASTER_UNLOCK_UNLKEY_MASK       ((uint32_t)0x0000FFFF)          /*!< UNLKEY Bit Mask */
8777 /* SYSCTL_A_RESET_REQ[POR] Bits */
8778 #define SYSCTL_A_RESET_REQ_POR_OFS               ( 0)                            /*!< POR Bit Offset */
8779 #define SYSCTL_A_RESET_REQ_POR                   ((uint32_t)0x00000001)          /*!< Generate POR */
8780 /* SYSCTL_A_RESET_REQ[REBOOT] Bits */
8781 #define SYSCTL_A_RESET_REQ_REBOOT_OFS            ( 1)                            /*!< REBOOT Bit Offset */
8782 #define SYSCTL_A_RESET_REQ_REBOOT                ((uint32_t)0x00000002)          /*!< Generate Reboot_Reset */
8783 /* SYSCTL_A_RESET_REQ[WKEY] Bits */
8784 #define SYSCTL_A_RESET_REQ_WKEY_OFS              ( 8)                            /*!< WKEY Bit Offset */
8785 #define SYSCTL_A_RESET_REQ_WKEY_MASK             ((uint32_t)0x0000FF00)          /*!< WKEY Bit Mask */
8786 /* SYSCTL_A_RESET_STATOVER[SOFT] Bits */
8787 #define SYSCTL_A_RESET_STATOVER_SOFT_OFS         ( 0)                            /*!< SOFT Bit Offset */
8788 #define SYSCTL_A_RESET_STATOVER_SOFT             ((uint32_t)0x00000001)          /*!< Indicates if SOFT Reset is active */
8789 /* SYSCTL_A_RESET_STATOVER[HARD] Bits */
8790 #define SYSCTL_A_RESET_STATOVER_HARD_OFS         ( 1)                            /*!< HARD Bit Offset */
8791 #define SYSCTL_A_RESET_STATOVER_HARD             ((uint32_t)0x00000002)          /*!< Indicates if HARD Reset is active */
8792 /* SYSCTL_A_RESET_STATOVER[REBOOT] Bits */
8793 #define SYSCTL_A_RESET_STATOVER_REBOOT_OFS       ( 2)                            /*!< REBOOT Bit Offset */
8794 #define SYSCTL_A_RESET_STATOVER_REBOOT           ((uint32_t)0x00000004)          /*!< Indicates if Reboot Reset is active */
8795 /* SYSCTL_A_RESET_STATOVER[SOFT_OVER] Bits */
8796 #define SYSCTL_A_RESET_STATOVER_SOFT_OVER_OFS    ( 8)                            /*!< SOFT_OVER Bit Offset */
8797 #define SYSCTL_A_RESET_STATOVER_SOFT_OVER        ((uint32_t)0x00000100)          /*!< SOFT_Reset overwrite request */
8798 /* SYSCTL_A_RESET_STATOVER[HARD_OVER] Bits */
8799 #define SYSCTL_A_RESET_STATOVER_HARD_OVER_OFS    ( 9)                            /*!< HARD_OVER Bit Offset */
8800 #define SYSCTL_A_RESET_STATOVER_HARD_OVER        ((uint32_t)0x00000200)          /*!< HARD_Reset overwrite request */
8801 /* SYSCTL_A_RESET_STATOVER[RBT_OVER] Bits */
8802 #define SYSCTL_A_RESET_STATOVER_RBT_OVER_OFS     (10)                            /*!< RBT_OVER Bit Offset */
8803 #define SYSCTL_A_RESET_STATOVER_RBT_OVER         ((uint32_t)0x00000400)          /*!< Reboot Reset overwrite request */
8804 /* Pre-defined bitfield values */
8805 #define SYSCTL_A_CSYS_MASTER_UNLOCK_UNLKEY_VAL  ((uint32_t)0x0000695A)          /*!< Unlock key value which when written, determines if accesses to other CPU_SYS register */
8806 #define SYSCTL_A_REBOOT_CTL_WKEY_VAL            ((uint32_t)0x00006900)          /*!< Key value to validate write to bit 0 */
8807 #define SYSCTL_A_BOOT_CTL_WKEY_VAL              ((uint32_t)0x00006900)          /*!< Key value to validate write to bit 0 */
8808 #define SYSCTL_A_ETW_CTL_WKEY_VAL               ((uint32_t)0x00006900)          /*!< Key value to validate write to bit 0 */
8809 #define SYSCTL_A_SECDATA_UNLOCK_KEY_VAL         ((uint32_t)0x0000695A)          /*!< Unlock Key value, which requests for secure data region to be unlocked for data access */
8810 
8811 
8812 /******************************************************************************
8813 * SYSTICK Bits
8814 ******************************************************************************/
8815 
8816 /******************************************************************************
8817 * Timer32 Bits
8818 ******************************************************************************/
8819 /* TIMER32_CONTROL[ONESHOT] Bits */
8820 #define TIMER32_CONTROL_ONESHOT_OFS              ( 0)                            /*!< ONESHOT Bit Offset */
8821 #define TIMER32_CONTROL_ONESHOT                  ((uint32_t)0x00000001)          /*!< Selects one-shot or wrapping counter mode */
8822 /* TIMER32_CONTROL[SIZE] Bits */
8823 #define TIMER32_CONTROL_SIZE_OFS                 ( 1)                            /*!< SIZE Bit Offset */
8824 #define TIMER32_CONTROL_SIZE                     ((uint32_t)0x00000002)          /*!< Selects 16 or 32 bit counter operation */
8825 /* TIMER32_CONTROL[PRESCALE] Bits */
8826 #define TIMER32_CONTROL_PRESCALE_OFS             ( 2)                            /*!< PRESCALE Bit Offset */
8827 #define TIMER32_CONTROL_PRESCALE_MASK            ((uint32_t)0x0000000C)          /*!< PRESCALE Bit Mask */
8828 #define TIMER32_CONTROL_PRESCALE0                ((uint32_t)0x00000004)          /*!< PRESCALE Bit 0 */
8829 #define TIMER32_CONTROL_PRESCALE1                ((uint32_t)0x00000008)          /*!< PRESCALE Bit 1 */
8830 #define TIMER32_CONTROL_PRESCALE_0               ((uint32_t)0x00000000)          /*!< 0 stages of prescale, clock is divided by 1 */
8831 #define TIMER32_CONTROL_PRESCALE_1               ((uint32_t)0x00000004)          /*!< 4 stages of prescale, clock is divided by 16 */
8832 #define TIMER32_CONTROL_PRESCALE_2               ((uint32_t)0x00000008)          /*!< 8 stages of prescale, clock is divided by 256 */
8833 /* TIMER32_CONTROL[IE] Bits */
8834 #define TIMER32_CONTROL_IE_OFS                   ( 5)                            /*!< IE Bit Offset */
8835 #define TIMER32_CONTROL_IE                       ((uint32_t)0x00000020)          /*!< Interrupt enable bit */
8836 /* TIMER32_CONTROL[MODE] Bits */
8837 #define TIMER32_CONTROL_MODE_OFS                 ( 6)                            /*!< MODE Bit Offset */
8838 #define TIMER32_CONTROL_MODE                     ((uint32_t)0x00000040)          /*!< Mode bit */
8839 /* TIMER32_CONTROL[ENABLE] Bits */
8840 #define TIMER32_CONTROL_ENABLE_OFS               ( 7)                            /*!< ENABLE Bit Offset */
8841 #define TIMER32_CONTROL_ENABLE                   ((uint32_t)0x00000080)
8842 /* TIMER32_RIS[RAW_IFG] Bits */
8843 #define TIMER32_RIS_RAW_IFG_OFS                  ( 0)                            /*!< RAW_IFG Bit Offset */
8844 #define TIMER32_RIS_RAW_IFG                      ((uint32_t)0x00000001)          /*!< Raw interrupt status */
8845 /* TIMER32_MIS[IFG] Bits */
8846 #define TIMER32_MIS_IFG_OFS                      ( 0)                            /*!< IFG Bit Offset */
8847 #define TIMER32_MIS_IFG                          ((uint32_t)0x00000001)          /*!< Enabled interrupt status */
8848 
8849 
8850 
8851 /******************************************************************************
8852 * TIMER_A Bits
8853 ******************************************************************************/
8854 /* TIMER_A_CTL[IFG] Bits */
8855 #define TIMER_A_CTL_IFG_OFS                      ( 0)                            /*!< TAIFG Bit Offset */
8856 #define TIMER_A_CTL_IFG                          ((uint16_t)0x0001)              /*!< TimerA interrupt flag */
8857 /* TIMER_A_CTL[IE] Bits */
8858 #define TIMER_A_CTL_IE_OFS                       ( 1)                            /*!< TAIE Bit Offset */
8859 #define TIMER_A_CTL_IE                           ((uint16_t)0x0002)              /*!< TimerA interrupt enable */
8860 /* TIMER_A_CTL[CLR] Bits */
8861 #define TIMER_A_CTL_CLR_OFS                      ( 2)                            /*!< TACLR Bit Offset */
8862 #define TIMER_A_CTL_CLR                          ((uint16_t)0x0004)              /*!< TimerA clear */
8863 /* TIMER_A_CTL[MC] Bits */
8864 #define TIMER_A_CTL_MC_OFS                       ( 4)                            /*!< MC Bit Offset */
8865 #define TIMER_A_CTL_MC_MASK                      ((uint16_t)0x0030)              /*!< MC Bit Mask */
8866 #define TIMER_A_CTL_MC0                          ((uint16_t)0x0010)              /*!< MC Bit 0 */
8867 #define TIMER_A_CTL_MC1                          ((uint16_t)0x0020)              /*!< MC Bit 1 */
8868 #define TIMER_A_CTL_MC_0                         ((uint16_t)0x0000)              /*!< Stop mode: Timer is halted */
8869 #define TIMER_A_CTL_MC_1                         ((uint16_t)0x0010)              /*!< Up mode: Timer counts up to TAxCCR0 */
8870 #define TIMER_A_CTL_MC_2                         ((uint16_t)0x0020)              /*!< Continuous mode: Timer counts up to 0FFFFh */
8871 #define TIMER_A_CTL_MC_3                         ((uint16_t)0x0030)              /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
8872 #define TIMER_A_CTL_MC__STOP                     ((uint16_t)0x0000)              /*!< Stop mode: Timer is halted */
8873 #define TIMER_A_CTL_MC__UP                       ((uint16_t)0x0010)              /*!< Up mode: Timer counts up to TAxCCR0 */
8874 #define TIMER_A_CTL_MC__CONTINUOUS               ((uint16_t)0x0020)              /*!< Continuous mode: Timer counts up to 0FFFFh */
8875 #define TIMER_A_CTL_MC__UPDOWN                   ((uint16_t)0x0030)              /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */
8876 /* TIMER_A_CTL[ID] Bits */
8877 #define TIMER_A_CTL_ID_OFS                       ( 6)                            /*!< ID Bit Offset */
8878 #define TIMER_A_CTL_ID_MASK                      ((uint16_t)0x00C0)              /*!< ID Bit Mask */
8879 #define TIMER_A_CTL_ID0                          ((uint16_t)0x0040)              /*!< ID Bit 0 */
8880 #define TIMER_A_CTL_ID1                          ((uint16_t)0x0080)              /*!< ID Bit 1 */
8881 #define TIMER_A_CTL_ID_0                         ((uint16_t)0x0000)              /*!< /1 */
8882 #define TIMER_A_CTL_ID_1                         ((uint16_t)0x0040)              /*!< /2 */
8883 #define TIMER_A_CTL_ID_2                         ((uint16_t)0x0080)              /*!< /4 */
8884 #define TIMER_A_CTL_ID_3                         ((uint16_t)0x00C0)              /*!< /8 */
8885 #define TIMER_A_CTL_ID__1                        ((uint16_t)0x0000)              /*!< /1 */
8886 #define TIMER_A_CTL_ID__2                        ((uint16_t)0x0040)              /*!< /2 */
8887 #define TIMER_A_CTL_ID__4                        ((uint16_t)0x0080)              /*!< /4 */
8888 #define TIMER_A_CTL_ID__8                        ((uint16_t)0x00C0)              /*!< /8 */
8889 /* TIMER_A_CTL[SSEL] Bits */
8890 #define TIMER_A_CTL_SSEL_OFS                     ( 8)                            /*!< TASSEL Bit Offset */
8891 #define TIMER_A_CTL_SSEL_MASK                    ((uint16_t)0x0300)              /*!< TASSEL Bit Mask */
8892 #define TIMER_A_CTL_SSEL0                        ((uint16_t)0x0100)              /*!< SSEL Bit 0 */
8893 #define TIMER_A_CTL_SSEL1                        ((uint16_t)0x0200)              /*!< SSEL Bit 1 */
8894 #define TIMER_A_CTL_TASSEL_0                     ((uint16_t)0x0000)              /*!< TAxCLK */
8895 #define TIMER_A_CTL_TASSEL_1                     ((uint16_t)0x0100)              /*!< ACLK */
8896 #define TIMER_A_CTL_TASSEL_2                     ((uint16_t)0x0200)              /*!< SMCLK */
8897 #define TIMER_A_CTL_TASSEL_3                     ((uint16_t)0x0300)              /*!< INCLK */
8898 #define TIMER_A_CTL_SSEL__TACLK                  ((uint16_t)0x0000)              /*!< TAxCLK */
8899 #define TIMER_A_CTL_SSEL__ACLK                   ((uint16_t)0x0100)              /*!< ACLK */
8900 #define TIMER_A_CTL_SSEL__SMCLK                  ((uint16_t)0x0200)              /*!< SMCLK */
8901 #define TIMER_A_CTL_SSEL__INCLK                  ((uint16_t)0x0300)              /*!< INCLK */
8902 /* TIMER_A_CCTLN[CCIFG] Bits */
8903 #define TIMER_A_CCTLN_CCIFG_OFS                  ( 0)                            /*!< CCIFG Bit Offset */
8904 #define TIMER_A_CCTLN_CCIFG                      ((uint16_t)0x0001)              /*!< Capture/compare interrupt flag */
8905 /* TIMER_A_CCTLN[COV] Bits */
8906 #define TIMER_A_CCTLN_COV_OFS                    ( 1)                            /*!< COV Bit Offset */
8907 #define TIMER_A_CCTLN_COV                        ((uint16_t)0x0002)              /*!< Capture overflow */
8908 /* TIMER_A_CCTLN[OUT] Bits */
8909 #define TIMER_A_CCTLN_OUT_OFS                    ( 2)                            /*!< OUT Bit Offset */
8910 #define TIMER_A_CCTLN_OUT                        ((uint16_t)0x0004)              /*!< Output */
8911 /* TIMER_A_CCTLN[CCI] Bits */
8912 #define TIMER_A_CCTLN_CCI_OFS                    ( 3)                            /*!< CCI Bit Offset */
8913 #define TIMER_A_CCTLN_CCI                        ((uint16_t)0x0008)              /*!< Capture/compare input */
8914 /* TIMER_A_CCTLN[CCIE] Bits */
8915 #define TIMER_A_CCTLN_CCIE_OFS                   ( 4)                            /*!< CCIE Bit Offset */
8916 #define TIMER_A_CCTLN_CCIE                       ((uint16_t)0x0010)              /*!< Capture/compare interrupt enable */
8917 /* TIMER_A_CCTLN[OUTMOD] Bits */
8918 #define TIMER_A_CCTLN_OUTMOD_OFS                 ( 5)                            /*!< OUTMOD Bit Offset */
8919 #define TIMER_A_CCTLN_OUTMOD_MASK                ((uint16_t)0x00E0)              /*!< OUTMOD Bit Mask */
8920 #define TIMER_A_CCTLN_OUTMOD0                    ((uint16_t)0x0020)              /*!< OUTMOD Bit 0 */
8921 #define TIMER_A_CCTLN_OUTMOD1                    ((uint16_t)0x0040)              /*!< OUTMOD Bit 1 */
8922 #define TIMER_A_CCTLN_OUTMOD2                    ((uint16_t)0x0080)              /*!< OUTMOD Bit 2 */
8923 #define TIMER_A_CCTLN_OUTMOD_0                   ((uint16_t)0x0000)              /*!< OUT bit value */
8924 #define TIMER_A_CCTLN_OUTMOD_1                   ((uint16_t)0x0020)              /*!< Set */
8925 #define TIMER_A_CCTLN_OUTMOD_2                   ((uint16_t)0x0040)              /*!< Toggle/reset */
8926 #define TIMER_A_CCTLN_OUTMOD_3                   ((uint16_t)0x0060)              /*!< Set/reset */
8927 #define TIMER_A_CCTLN_OUTMOD_4                   ((uint16_t)0x0080)              /*!< Toggle */
8928 #define TIMER_A_CCTLN_OUTMOD_5                   ((uint16_t)0x00A0)              /*!< Reset */
8929 #define TIMER_A_CCTLN_OUTMOD_6                   ((uint16_t)0x00C0)              /*!< Toggle/set */
8930 #define TIMER_A_CCTLN_OUTMOD_7                   ((uint16_t)0x00E0)              /*!< Reset/set */
8931 /* TIMER_A_CCTLN[CAP] Bits */
8932 #define TIMER_A_CCTLN_CAP_OFS                    ( 8)                            /*!< CAP Bit Offset */
8933 #define TIMER_A_CCTLN_CAP                        ((uint16_t)0x0100)              /*!< Capture mode */
8934 /* TIMER_A_CCTLN[SCCI] Bits */
8935 #define TIMER_A_CCTLN_SCCI_OFS                   (10)                            /*!< SCCI Bit Offset */
8936 #define TIMER_A_CCTLN_SCCI                       ((uint16_t)0x0400)              /*!< Synchronized capture/compare input */
8937 /* TIMER_A_CCTLN[SCS] Bits */
8938 #define TIMER_A_CCTLN_SCS_OFS                    (11)                            /*!< SCS Bit Offset */
8939 #define TIMER_A_CCTLN_SCS                        ((uint16_t)0x0800)              /*!< Synchronize capture source */
8940 /* TIMER_A_CCTLN[CCIS] Bits */
8941 #define TIMER_A_CCTLN_CCIS_OFS                   (12)                            /*!< CCIS Bit Offset */
8942 #define TIMER_A_CCTLN_CCIS_MASK                  ((uint16_t)0x3000)              /*!< CCIS Bit Mask */
8943 #define TIMER_A_CCTLN_CCIS0                      ((uint16_t)0x1000)              /*!< CCIS Bit 0 */
8944 #define TIMER_A_CCTLN_CCIS1                      ((uint16_t)0x2000)              /*!< CCIS Bit 1 */
8945 #define TIMER_A_CCTLN_CCIS_0                     ((uint16_t)0x0000)              /*!< CCIxA */
8946 #define TIMER_A_CCTLN_CCIS_1                     ((uint16_t)0x1000)              /*!< CCIxB */
8947 #define TIMER_A_CCTLN_CCIS_2                     ((uint16_t)0x2000)              /*!< GND */
8948 #define TIMER_A_CCTLN_CCIS_3                     ((uint16_t)0x3000)              /*!< VCC */
8949 #define TIMER_A_CCTLN_CCIS__CCIA                 ((uint16_t)0x0000)              /*!< CCIxA */
8950 #define TIMER_A_CCTLN_CCIS__CCIB                 ((uint16_t)0x1000)              /*!< CCIxB */
8951 #define TIMER_A_CCTLN_CCIS__GND                  ((uint16_t)0x2000)              /*!< GND */
8952 #define TIMER_A_CCTLN_CCIS__VCC                  ((uint16_t)0x3000)              /*!< VCC */
8953 /* TIMER_A_CCTLN[CM] Bits */
8954 #define TIMER_A_CCTLN_CM_OFS                     (14)                            /*!< CM Bit Offset */
8955 #define TIMER_A_CCTLN_CM_MASK                    ((uint16_t)0xC000)              /*!< CM Bit Mask */
8956 #define TIMER_A_CCTLN_CM0                        ((uint16_t)0x4000)              /*!< CM Bit 0 */
8957 #define TIMER_A_CCTLN_CM1                        ((uint16_t)0x8000)              /*!< CM Bit 1 */
8958 #define TIMER_A_CCTLN_CM_0                       ((uint16_t)0x0000)              /*!< No capture */
8959 #define TIMER_A_CCTLN_CM_1                       ((uint16_t)0x4000)              /*!< Capture on rising edge */
8960 #define TIMER_A_CCTLN_CM_2                       ((uint16_t)0x8000)              /*!< Capture on falling edge */
8961 #define TIMER_A_CCTLN_CM_3                       ((uint16_t)0xC000)              /*!< Capture on both rising and falling edges */
8962 #define TIMER_A_CCTLN_CM__NONE                   ((uint16_t)0x0000)              /*!< No capture */
8963 #define TIMER_A_CCTLN_CM__RISING                 ((uint16_t)0x4000)              /*!< Capture on rising edge */
8964 #define TIMER_A_CCTLN_CM__FALLING                ((uint16_t)0x8000)              /*!< Capture on falling edge */
8965 #define TIMER_A_CCTLN_CM__BOTH                   ((uint16_t)0xC000)              /*!< Capture on both rising and falling edges */
8966 /* TIMER_A_EX0[IDEX] Bits */
8967 #define TIMER_A_EX0_IDEX_OFS                     ( 0)                            /*!< TAIDEX Bit Offset */
8968 #define TIMER_A_EX0_IDEX_MASK                    ((uint16_t)0x0007)              /*!< TAIDEX Bit Mask */
8969 #define TIMER_A_EX0_IDEX0                        ((uint16_t)0x0001)              /*!< IDEX Bit 0 */
8970 #define TIMER_A_EX0_IDEX1                        ((uint16_t)0x0002)              /*!< IDEX Bit 1 */
8971 #define TIMER_A_EX0_IDEX2                        ((uint16_t)0x0004)              /*!< IDEX Bit 2 */
8972 #define TIMER_A_EX0_TAIDEX_0                     ((uint16_t)0x0000)              /*!< Divide by 1 */
8973 #define TIMER_A_EX0_TAIDEX_1                     ((uint16_t)0x0001)              /*!< Divide by 2 */
8974 #define TIMER_A_EX0_TAIDEX_2                     ((uint16_t)0x0002)              /*!< Divide by 3 */
8975 #define TIMER_A_EX0_TAIDEX_3                     ((uint16_t)0x0003)              /*!< Divide by 4 */
8976 #define TIMER_A_EX0_TAIDEX_4                     ((uint16_t)0x0004)              /*!< Divide by 5 */
8977 #define TIMER_A_EX0_TAIDEX_5                     ((uint16_t)0x0005)              /*!< Divide by 6 */
8978 #define TIMER_A_EX0_TAIDEX_6                     ((uint16_t)0x0006)              /*!< Divide by 7 */
8979 #define TIMER_A_EX0_TAIDEX_7                     ((uint16_t)0x0007)              /*!< Divide by 8 */
8980 #define TIMER_A_EX0_IDEX__1                      ((uint16_t)0x0000)              /*!< Divide by 1 */
8981 #define TIMER_A_EX0_IDEX__2                      ((uint16_t)0x0001)              /*!< Divide by 2 */
8982 #define TIMER_A_EX0_IDEX__3                      ((uint16_t)0x0002)              /*!< Divide by 3 */
8983 #define TIMER_A_EX0_IDEX__4                      ((uint16_t)0x0003)              /*!< Divide by 4 */
8984 #define TIMER_A_EX0_IDEX__5                      ((uint16_t)0x0004)              /*!< Divide by 5 */
8985 #define TIMER_A_EX0_IDEX__6                      ((uint16_t)0x0005)              /*!< Divide by 6 */
8986 #define TIMER_A_EX0_IDEX__7                      ((uint16_t)0x0006)              /*!< Divide by 7 */
8987 #define TIMER_A_EX0_IDEX__8                      ((uint16_t)0x0007)              /*!< Divide by 8 */
8988 
8989 /******************************************************************************
8990 * TLV Bits
8991 ******************************************************************************/
8992 /******************************************************************************
8993 * TLV table start and TLV tags                                                *
8994 ******************************************************************************/
8995 #define TLV_START_ADDR                    (TLV_BASE + 0x0004)                    /*!< Start Address of the TLV structure */
8996 
8997 #define TLV_TAG_RESERVED1                                   1
8998 #define TLV_TAG_RESERVED2                                   2
8999 #define TLV_TAG_CS                                          3
9000 #define TLV_TAG_FLASHCTL                                    4
9001 #define TLV_TAG_ADC14                                       5
9002 #define TLV_TAG_RESERVED6                                   6
9003 #define TLV_TAG_RESERVED7                                   7
9004 #define TLV_TAG_REF                                         8
9005 #define TLV_TAG_RESERVED9                                   9
9006 #define TLV_TAG_RESERVED10                                 10
9007 #define TLV_TAG_DEVINFO                                    11
9008 #define TLV_TAG_DIEREC                                     12
9009 #define TLV_TAG_RANDNUM                                    13
9010 #define TLV_TAG_RESERVED14                                 14
9011 #define TLV_TAG_BSL                                        15
9012 #define TLV_TAG_END                                        (0x0BD0E11D)
9013 
9014 
9015 /******************************************************************************
9016 * TPIU Bits
9017 ******************************************************************************/
9018 
9019 
9020 /******************************************************************************
9021 * WDT_A Bits
9022 ******************************************************************************/
9023 /* WDT_A_CTL[IS] Bits */
9024 #define WDT_A_CTL_IS_OFS                         ( 0)                            /*!< WDTIS Bit Offset */
9025 #define WDT_A_CTL_IS_MASK                        ((uint16_t)0x0007)              /*!< WDTIS Bit Mask */
9026 #define WDT_A_CTL_IS0                            ((uint16_t)0x0001)              /*!< IS Bit 0 */
9027 #define WDT_A_CTL_IS1                            ((uint16_t)0x0002)              /*!< IS Bit 1 */
9028 #define WDT_A_CTL_IS2                            ((uint16_t)0x0004)              /*!< IS Bit 2 */
9029 #define WDT_A_CTL_IS_0                           ((uint16_t)0x0000)              /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */
9030 #define WDT_A_CTL_IS_1                           ((uint16_t)0x0001)              /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */
9031 #define WDT_A_CTL_IS_2                           ((uint16_t)0x0002)              /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */
9032 #define WDT_A_CTL_IS_3                           ((uint16_t)0x0003)              /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */
9033 #define WDT_A_CTL_IS_4                           ((uint16_t)0x0004)              /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */
9034 #define WDT_A_CTL_IS_5                           ((uint16_t)0x0005)              /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */
9035 #define WDT_A_CTL_IS_6                           ((uint16_t)0x0006)              /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */
9036 #define WDT_A_CTL_IS_7                           ((uint16_t)0x0007)              /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */
9037 /* WDT_A_CTL[CNTCL] Bits */
9038 #define WDT_A_CTL_CNTCL_OFS                      ( 3)                            /*!< WDTCNTCL Bit Offset */
9039 #define WDT_A_CTL_CNTCL                          ((uint16_t)0x0008)              /*!< Watchdog timer counter clear */
9040 /* WDT_A_CTL[TMSEL] Bits */
9041 #define WDT_A_CTL_TMSEL_OFS                      ( 4)                            /*!< WDTTMSEL Bit Offset */
9042 #define WDT_A_CTL_TMSEL                          ((uint16_t)0x0010)              /*!< Watchdog timer mode select */
9043 /* WDT_A_CTL[SSEL] Bits */
9044 #define WDT_A_CTL_SSEL_OFS                       ( 5)                            /*!< WDTSSEL Bit Offset */
9045 #define WDT_A_CTL_SSEL_MASK                      ((uint16_t)0x0060)              /*!< WDTSSEL Bit Mask */
9046 #define WDT_A_CTL_SSEL0                          ((uint16_t)0x0020)              /*!< SSEL Bit 0 */
9047 #define WDT_A_CTL_SSEL1                          ((uint16_t)0x0040)              /*!< SSEL Bit 1 */
9048 #define WDT_A_CTL_SSEL_0                         ((uint16_t)0x0000)              /*!< SMCLK */
9049 #define WDT_A_CTL_SSEL_1                         ((uint16_t)0x0020)              /*!< ACLK */
9050 #define WDT_A_CTL_SSEL_2                         ((uint16_t)0x0040)              /*!< VLOCLK */
9051 #define WDT_A_CTL_SSEL_3                         ((uint16_t)0x0060)              /*!< BCLK */
9052 #define WDT_A_CTL_SSEL__SMCLK                    ((uint16_t)0x0000)              /*!< SMCLK */
9053 #define WDT_A_CTL_SSEL__ACLK                     ((uint16_t)0x0020)              /*!< ACLK */
9054 #define WDT_A_CTL_SSEL__VLOCLK                   ((uint16_t)0x0040)              /*!< VLOCLK */
9055 #define WDT_A_CTL_SSEL__BCLK                     ((uint16_t)0x0060)              /*!< BCLK */
9056 /* WDT_A_CTL[HOLD] Bits */
9057 #define WDT_A_CTL_HOLD_OFS                       ( 7)                            /*!< WDTHOLD Bit Offset */
9058 #define WDT_A_CTL_HOLD                           ((uint16_t)0x0080)              /*!< Watchdog timer hold */
9059 /* WDT_A_CTL[PW] Bits */
9060 #define WDT_A_CTL_PW_OFS                         ( 8)                            /*!< WDTPW Bit Offset */
9061 #define WDT_A_CTL_PW_MASK                        ((uint16_t)0xFF00)              /*!< WDTPW Bit Mask */
9062 /* Pre-defined bitfield values */
9063 #define WDT_A_CTL_PW                              ((uint16_t)0x5A00)              /*!< WDT Key Value for WDT write access */
9064 
9065 
9066 /******************************************************************************
9067 * BSL                                                                         *
9068 ******************************************************************************/
9069 #define BSL_DEFAULT_PARAM                        ((uint32_t)0xFC48FFFF)          /*!< I2C slave address = 0x48, Interface selection = Auto */
9070 #define BSL_API_TABLE_ADDR                       ((uint32_t)0x00202000)          /*!< Address of BSL API table */
9071 #define BSL_ENTRY_FUNCTION                       (*((uint32_t *)BSL_API_TABLE_ADDR))
9072 
9073 #define BSL_AUTO_INTERFACE                       ((uint32_t)0x0000E0000)         /*!< Auto detect interface */
9074 #define BSL_UART_INTERFACE                       ((uint32_t)0x0000C0000)         /*!< UART interface */
9075 #define BSL_SPI_INTERFACE                        ((uint32_t)0x0000A0000)         /*!< SPI interface */
9076 #define BSL_I2C_INTERFACE                        ((uint32_t)0x000080000)         /*!< I2C interface */
9077 
9078 #define BSL_INVOKE(x)                            ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */
9079 
9080 
9081 /******************************************************************************
9082 * Mailbox struct legacy definition                                            *
9083 ******************************************************************************/
9084 #define FLASH_MAILBOX_Type                    FL_BOOTOVER_MAILBOX_Type
9085 
9086 /******************************************************************************
9087 * Device Unlock Support                                                       *
9088 ******************************************************************************/
9089 /* unlock the device by:
9090  *   Load SYSCTL_SECDATA_UNLOCK register address into R0
9091  *   Load SYSCTL_SECDATA_UNLOCK unlock key into R1
9092  *   Write the unlock key to the SYSCTL_SECDATA_UNLOCK register
9093  */
9094 #define UNLOCK_DEVICE\
9095     __asm("  MOVW.W          R0, #0x3040");\
9096     __asm("  MOVT.W          R0, #0xE004");\
9097     __asm("  MOVW.W          R1, #0x695A");\
9098     __asm("  MOVT.W          R1, #0x0000");\
9099     __asm("  STR             R1, [R0]");
9100 
9101 /******************************************************************************
9102 *
9103 * The following are values that can be used to choose the command that will be
9104 * run by the boot code. Perform a logical OR of these settings to create your
9105 * general parameter command.
9106 *
9107 ******************************************************************************/
9108 #define COMMAND_FACTORY_RESET                    ((uint32_t)0x00010000)
9109 #define COMMAND_BSL_CONFIG                       ((uint32_t)0x00020000)
9110 #define COMMAND_JTAG_SWD_LOCK_SECEN              ((uint32_t)0x00080000)
9111 #define COMMAND_SEC_ZONE0_EN                     ((uint32_t)0x00100000)
9112 #define COMMAND_SEC_ZONE1_EN                     ((uint32_t)0x00200000)
9113 #define COMMAND_SEC_ZONE2_EN                     ((uint32_t)0x00400000)
9114 #define COMMAND_SEC_ZONE3_EN                     ((uint32_t)0x00800000)
9115 #define COMMAND_SEC_ZONE0_UPDATE                 ((uint32_t)0x01000000)
9116 #define COMMAND_SEC_ZONE1_UPDATE                 ((uint32_t)0x02000000)
9117 #define COMMAND_SEC_ZONE2_UPDATE                 ((uint32_t)0x04000000)
9118 #define COMMAND_SEC_ZONE3_UPDATE                 ((uint32_t)0x08000000)
9119 #define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE         ((uint32_t)0x10000000)
9120 #define COMMAND_NONE                             ((uint32_t)0xFFFFFFFF)
9121 
9122 /******************************************************************************
9123 *
9124 * The following are values that can be used to configure the BSL. Perform a
9125 * logical OR of these settings to create your BSL parameter.
9126 *
9127 ******************************************************************************/
9128 #define BSL_CONFIG_HW_INVOKE                     ((uint32_t)0x70000000)
9129 
9130 #define BSL_CONFIG_HW_INVOKE_PORT1               ((uint32_t)0x00000000)
9131 #define BSL_CONFIG_HW_INVOKE_PORT2               ((uint32_t)0x00000001)
9132 #define BSL_CONFIG_HW_INVOKE_PORT3               ((uint32_t)0x00000002)
9133 
9134 #define BSL_CONFIG_HW_INVOKE_PIN0                ((uint32_t)0x00000000)
9135 #define BSL_CONFIG_HW_INVOKE_PIN1                ((uint32_t)0x00000010)
9136 #define BSL_CONFIG_HW_INVOKE_PIN2                ((uint32_t)0x00000020)
9137 #define BSL_CONFIG_HW_INVOKE_PIN3                ((uint32_t)0x00000030)
9138 #define BSL_CONFIG_HW_INVOKE_PIN4                ((uint32_t)0x00000040)
9139 #define BSL_CONFIG_HW_INVOKE_PIN5                ((uint32_t)0x00000050)
9140 #define BSL_CONFIG_HW_INVOKE_PIN6                ((uint32_t)0x00000060)
9141 #define BSL_CONFIG_HW_INVOKE_PIN7                ((uint32_t)0x00000070)
9142 
9143 #define BSL_CONFIG_HW_INVOKE_PIN_LOW             ((uint32_t)0x00000000)
9144 #define BSL_CONFIG_HW_INVOKE_PIN_HIGH            ((uint32_t)0x00001000)
9145 
9146 #define BSL_CONFIG_INTERFACE_I2C                 ((uint32_t)0x00008000)
9147 #define BSL_CONFIG_INTERFACE_SPI                 ((uint32_t)0x0000A000)
9148 #define BSL_CONFIG_INTERFACE_UART                ((uint32_t)0x0000C000)
9149 #define BSL_CONFIG_INTERFACE_AUTO                ((uint32_t)0x0000E000)
9150 
9151 #define BSL_CONFIG_I2C_ADD_OFFSET                (16)
9152 
9153 
9154 /******************************************************************************
9155 * ULP Advisor                                                                 *
9156 ******************************************************************************/
9157 #ifdef __TI_ARM__
9158 #pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8})
9159 #pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8})
9160 #pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8})
9161 #pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8})
9162 #pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8})
9163 #pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8})
9164 #pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8})
9165 #pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8})
9166 #pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8})
9167 #pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8})
9168 #endif
9169 
9170 
9171 #ifdef __cplusplus
9172 }
9173 #endif
9174 
9175 #endif /* __MSP432P401V_H__ */
9176 
9177