1 /****************************************************************************** 2 * 3 * Copyright (C) 2012 - 2018 Texas Instruments Incorporated - http://www.ti.com/ 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the 15 * distribution. 16 * 17 * Neither the name of Texas Instruments Incorporated nor the names of 18 * its contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * MSP432P401R Register Definitions 34 * 35 * This file includes CMSIS compliant component and register definitions 36 * 37 * For legacy components the definitions that are compatible with MSP430 code, 38 * are included with msp432p401r_classic.h 39 * 40 * With CMSIS definitions, the register defines have been reformatted: 41 * ModuleName[ModuleInstance]->RegisterName 42 * 43 * Writing to CMSIS bit fields can be done through register level 44 * or via bitband area access: 45 * - ADC14->CTL0 |= ADC14_CTL0_ENC; 46 * - BITBAND_PERI(ADC14->CTL0, ADC14_CTL0_ENC_OFS) = 1; 47 * 48 * File creation date: 2018-01-26 49 * 50 ******************************************************************************/ 51 52 #ifndef __MSP432P401R_H__ 53 #define __MSP432P401R_H__ 54 55 /* Use standard integer types with explicit width */ 56 #include <stdint.h> 57 58 #ifdef __cplusplus 59 extern "C" { 60 #endif 61 62 #define __MSP432_HEADER_VERSION__ 3231 63 64 /* Remap MSP432 intrinsics to ARM equivalents */ 65 #include "msp_compatibility.h" 66 67 /****************************************************************************** 68 * include MSP430 legacy definitions to make porting of code from MSP430 * 69 * code base easier * 70 * With fully CMSIS compliant code, NO_MSP_CLASSIC_DEFINES may be defined in * 71 * your project to omit including the classic defines * 72 ******************************************************************************/ 73 #ifndef NO_MSP_CLASSIC_DEFINES 74 #include "msp432p401r_classic.h" 75 #endif 76 77 78 #ifndef __CMSIS_CONFIG__ 79 #define __CMSIS_CONFIG__ 80 81 /** @addtogroup MSP432P401R_Definitions MSP432P401R Definitions 82 This file defines all structures and symbols for MSP432P401R: 83 - components and registers 84 - peripheral base address 85 - peripheral ID 86 - Peripheral definitions 87 @{ 88 */ 89 90 /****************************************************************************** 91 * Processor and Core Peripherals * 92 ******************************************************************************/ 93 /** @addtogroup MSP432P401R_CMSIS Device CMSIS Definitions 94 Configuration of the Cortex-M4 Processor and Core Peripherals 95 @{ 96 */ 97 98 /****************************************************************************** 99 * CMSIS-compatible Interrupt Number Definition * 100 ******************************************************************************/ 101 typedef enum IRQn 102 { 103 /* Cortex-M4 Processor Exceptions Numbers */ 104 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ 105 HardFault_IRQn = -13, /* 3 Hard Fault Interrupt */ 106 MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */ 107 BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */ 108 UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */ 109 SVCall_IRQn = -5, /* 11 SV Call Interrupt */ 110 DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */ 111 PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ 112 SysTick_IRQn = -1, /* 15 System Tick Interrupt */ 113 /* Peripheral Exceptions Numbers */ 114 PSS_IRQn = 0, /* 16 PSS Interrupt */ 115 CS_IRQn = 1, /* 17 CS Interrupt */ 116 PCM_IRQn = 2, /* 18 PCM Interrupt */ 117 WDT_A_IRQn = 3, /* 19 WDT_A Interrupt */ 118 FPU_IRQn = 4, /* 20 FPU Interrupt */ 119 FLCTL_IRQn = 5, /* 21 Flash Controller Interrupt*/ 120 COMP_E0_IRQn = 6, /* 22 COMP_E0 Interrupt */ 121 COMP_E1_IRQn = 7, /* 23 COMP_E1 Interrupt */ 122 TA0_0_IRQn = 8, /* 24 TA0_0 Interrupt */ 123 TA0_N_IRQn = 9, /* 25 TA0_N Interrupt */ 124 TA1_0_IRQn = 10, /* 26 TA1_0 Interrupt */ 125 TA1_N_IRQn = 11, /* 27 TA1_N Interrupt */ 126 TA2_0_IRQn = 12, /* 28 TA2_0 Interrupt */ 127 TA2_N_IRQn = 13, /* 29 TA2_N Interrupt */ 128 TA3_0_IRQn = 14, /* 30 TA3_0 Interrupt */ 129 TA3_N_IRQn = 15, /* 31 TA3_N Interrupt */ 130 EUSCIA0_IRQn = 16, /* 32 EUSCIA0 Interrupt */ 131 EUSCIA1_IRQn = 17, /* 33 EUSCIA1 Interrupt */ 132 EUSCIA2_IRQn = 18, /* 34 EUSCIA2 Interrupt */ 133 EUSCIA3_IRQn = 19, /* 35 EUSCIA3 Interrupt */ 134 EUSCIB0_IRQn = 20, /* 36 EUSCIB0 Interrupt */ 135 EUSCIB1_IRQn = 21, /* 37 EUSCIB1 Interrupt */ 136 EUSCIB2_IRQn = 22, /* 38 EUSCIB2 Interrupt */ 137 EUSCIB3_IRQn = 23, /* 39 EUSCIB3 Interrupt */ 138 ADC14_IRQn = 24, /* 40 ADC14 Interrupt */ 139 T32_INT1_IRQn = 25, /* 41 T32_INT1 Interrupt */ 140 T32_INT2_IRQn = 26, /* 42 T32_INT2 Interrupt */ 141 T32_INTC_IRQn = 27, /* 43 T32_INTC Interrupt */ 142 AES256_IRQn = 28, /* 44 AES256 Interrupt */ 143 RTC_C_IRQn = 29, /* 45 RTC_C Interrupt */ 144 DMA_ERR_IRQn = 30, /* 46 DMA_ERR Interrupt */ 145 DMA_INT3_IRQn = 31, /* 47 DMA_INT3 Interrupt */ 146 DMA_INT2_IRQn = 32, /* 48 DMA_INT2 Interrupt */ 147 DMA_INT1_IRQn = 33, /* 49 DMA_INT1 Interrupt */ 148 DMA_INT0_IRQn = 34, /* 50 DMA_INT0 Interrupt */ 149 PORT1_IRQn = 35, /* 51 Port1 Interrupt */ 150 PORT2_IRQn = 36, /* 52 Port2 Interrupt */ 151 PORT3_IRQn = 37, /* 53 Port3 Interrupt */ 152 PORT4_IRQn = 38, /* 54 Port4 Interrupt */ 153 PORT5_IRQn = 39, /* 55 Port5 Interrupt */ 154 PORT6_IRQn = 40 /* 56 Port6 Interrupt */ 155 } IRQn_Type; 156 157 /****************************************************************************** 158 * Processor and Core Peripheral Section * 159 ******************************************************************************/ 160 #define __CM4_REV 0x0001 /* Core revision r0p1 */ 161 #define __MPU_PRESENT 1 /* MPU present or not */ 162 #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Prio Levels */ 163 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ 164 #define __FPU_PRESENT 1 /* FPU present or not */ 165 166 /****************************************************************************** 167 * Available Peripherals * 168 ******************************************************************************/ 169 #define __MCU_HAS_ADC14__ /*!< Module ADC14 is available */ 170 #define __MCU_HAS_AES256__ /*!< Module AES256 is available */ 171 #define __MCU_HAS_CAPTIO0__ /*!< Module CAPTIO0 is available */ 172 #define __MCU_HAS_CAPTIO1__ /*!< Module CAPTIO1 is available */ 173 #define __MCU_HAS_COMP_E0__ /*!< Module COMP_E0 is available */ 174 #define __MCU_HAS_COMP_E1__ /*!< Module COMP_E1 is available */ 175 #define __MCU_HAS_CRC32__ /*!< Module CRC32 is available */ 176 #define __MCU_HAS_CS__ /*!< Module CS is available */ 177 #define __MCU_HAS_DIO__ /*!< Module DIO is available */ 178 #define __MCU_HAS_DMA__ /*!< Module DMA is available */ 179 #define __MCU_HAS_EUSCI_A0__ /*!< Module EUSCI_A0 is available */ 180 #define __MCU_HAS_EUSCI_A1__ /*!< Module EUSCI_A1 is available */ 181 #define __MCU_HAS_EUSCI_A2__ /*!< Module EUSCI_A2 is available */ 182 #define __MCU_HAS_EUSCI_A3__ /*!< Module EUSCI_A3 is available */ 183 #define __MCU_HAS_EUSCI_B0__ /*!< Module EUSCI_B0 is available */ 184 #define __MCU_HAS_EUSCI_B1__ /*!< Module EUSCI_B1 is available */ 185 #define __MCU_HAS_EUSCI_B2__ /*!< Module EUSCI_B2 is available */ 186 #define __MCU_HAS_EUSCI_B3__ /*!< Module EUSCI_B3 is available */ 187 #define __MCU_HAS_FLCTL__ /*!< Module FLCTL is available */ 188 #define __MCU_HAS_FL_BOOTOVER_MAILBOX__ /*!< Module FL_BOOTOVER_MAILBOX is available */ 189 #define __MCU_HAS_PCM__ /*!< Module PCM is available */ 190 #define __MCU_HAS_PMAP__ /*!< Module PMAP is available */ 191 #define __MCU_HAS_PSS__ /*!< Module PSS is available */ 192 #define __MCU_HAS_REF_A__ /*!< Module REF_A is available */ 193 #define __MCU_HAS_RSTCTL__ /*!< Module RSTCTL is available */ 194 #define __MCU_HAS_RTC_C__ /*!< Module RTC_C is available */ 195 #define __MCU_HAS_SYSCTL__ /*!< Module SYSCTL is available */ 196 #define __MCU_HAS_TIMER32__ /*!< Module TIMER32 is available */ 197 #define __MCU_HAS_TIMER_A0__ /*!< Module TIMER_A0 is available */ 198 #define __MCU_HAS_TIMER_A1__ /*!< Module TIMER_A1 is available */ 199 #define __MCU_HAS_TIMER_A2__ /*!< Module TIMER_A2 is available */ 200 #define __MCU_HAS_TIMER_A3__ /*!< Module TIMER_A3 is available */ 201 #define __MCU_HAS_TLV__ /*!< Module TLV is available */ 202 #define __MCU_HAS_WDT_A__ /*!< Module WDT_A is available */ 203 204 /* Definitions to show that specific ports are available */ 205 206 #define __MSP432_HAS_PORTA_R__ 207 #define __MSP432_HAS_PORTB_R__ 208 #define __MSP432_HAS_PORTC_R__ 209 #define __MSP432_HAS_PORTD_R__ 210 #define __MSP432_HAS_PORTE_R__ 211 #define __MSP432_HAS_PORTJ_R__ 212 213 #define __MSP432_HAS_PORT1_R__ 214 #define __MSP432_HAS_PORT2_R__ 215 #define __MSP432_HAS_PORT3_R__ 216 #define __MSP432_HAS_PORT4_R__ 217 #define __MSP432_HAS_PORT5_R__ 218 #define __MSP432_HAS_PORT6_R__ 219 #define __MSP432_HAS_PORT7_R__ 220 #define __MSP432_HAS_PORT8_R__ 221 #define __MSP432_HAS_PORT9_R__ 222 #define __MSP432_HAS_PORT10_R__ 223 224 225 /*@}*/ /* end of group MSP432P401R_CMSIS */ 226 227 /* Include CMSIS Cortex-M4 Core Peripheral Access Layer Header File */ 228 #ifdef __TI_ARM__ 229 /* disable the TI ULP advisor check for the core header file definitions */ 230 #pragma diag_push 231 #pragma CHECK_ULP("none") 232 #include "core_cm4.h" 233 #pragma diag_pop 234 #else 235 #include "core_cm4.h" 236 #endif 237 238 /* System Header */ 239 #include "system_msp432p401r.h" 240 241 /****************************************************************************** 242 * Definition of standard bits * 243 ******************************************************************************/ 244 #define BIT0 (uint16_t)(0x0001) 245 #define BIT1 (uint16_t)(0x0002) 246 #define BIT2 (uint16_t)(0x0004) 247 #define BIT3 (uint16_t)(0x0008) 248 #define BIT4 (uint16_t)(0x0010) 249 #define BIT5 (uint16_t)(0x0020) 250 #define BIT6 (uint16_t)(0x0040) 251 #define BIT7 (uint16_t)(0x0080) 252 #define BIT8 (uint16_t)(0x0100) 253 #define BIT9 (uint16_t)(0x0200) 254 #define BITA (uint16_t)(0x0400) 255 #define BITB (uint16_t)(0x0800) 256 #define BITC (uint16_t)(0x1000) 257 #define BITD (uint16_t)(0x2000) 258 #define BITE (uint16_t)(0x4000) 259 #define BITF (uint16_t)(0x8000) 260 #define BIT(x) ((uint16_t)1 << (x)) 261 262 /****************************************************************************** 263 * Device and peripheral memory map * 264 ******************************************************************************/ 265 /** @addtogroup MSP432P401R_MemoryMap MSP432P401R Memory Mapping 266 @{ 267 */ 268 269 #define FLASH_BASE ((uint32_t)0x00000000) /*!< Main Flash memory start address */ 270 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM memory start address */ 271 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripherals start address */ 272 #define PERIPH_BASE2 ((uint32_t)0xE0000000) /*!< Peripherals start address */ 273 274 #define ADC14_BASE (PERIPH_BASE +0x00012000) /*!< Base address of module ADC14 registers */ 275 #define AES256_BASE (PERIPH_BASE +0x00003C00) /*!< Base address of module AES256 registers */ 276 #define CAPTIO0_BASE (PERIPH_BASE +0x00005400) /*!< Base address of module CAPTIO0 registers */ 277 #define CAPTIO1_BASE (PERIPH_BASE +0x00005800) /*!< Base address of module CAPTIO1 registers */ 278 #define COMP_E0_BASE (PERIPH_BASE +0x00003400) /*!< Base address of module COMP_E0 registers */ 279 #define COMP_E1_BASE (PERIPH_BASE +0x00003800) /*!< Base address of module COMP_E1 registers */ 280 #define CRC32_BASE (PERIPH_BASE +0x00004000) /*!< Base address of module CRC32 registers */ 281 #define CS_BASE (PERIPH_BASE +0x00010400) /*!< Base address of module CS registers */ 282 #define DIO_BASE (PERIPH_BASE +0x00004C00) /*!< Base address of module DIO registers */ 283 #define DMA_BASE (PERIPH_BASE +0x0000E000) /*!< Base address of module DMA registers */ 284 #define EUSCI_A0_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ 285 #define EUSCI_A0_SPI_BASE (PERIPH_BASE +0x00001000) /*!< Base address of module EUSCI_A0 registers */ 286 #define EUSCI_A1_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ 287 #define EUSCI_A1_SPI_BASE (PERIPH_BASE +0x00001400) /*!< Base address of module EUSCI_A1 registers */ 288 #define EUSCI_A2_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ 289 #define EUSCI_A2_SPI_BASE (PERIPH_BASE +0x00001800) /*!< Base address of module EUSCI_A2 registers */ 290 #define EUSCI_A3_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ 291 #define EUSCI_A3_SPI_BASE (PERIPH_BASE +0x00001C00) /*!< Base address of module EUSCI_A3 registers */ 292 #define EUSCI_B0_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ 293 #define EUSCI_B0_SPI_BASE (PERIPH_BASE +0x00002000) /*!< Base address of module EUSCI_B0 registers */ 294 #define EUSCI_B1_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ 295 #define EUSCI_B1_SPI_BASE (PERIPH_BASE +0x00002400) /*!< Base address of module EUSCI_B1 registers */ 296 #define EUSCI_B2_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ 297 #define EUSCI_B2_SPI_BASE (PERIPH_BASE +0x00002800) /*!< Base address of module EUSCI_B2 registers */ 298 #define EUSCI_B3_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ 299 #define EUSCI_B3_SPI_BASE (PERIPH_BASE +0x00002C00) /*!< Base address of module EUSCI_B3 registers */ 300 #define FLCTL_BASE (PERIPH_BASE +0x00011000) /*!< Base address of module FLCTL registers */ 301 #define FL_BOOTOVER_MAILBOX_BASE ((uint32_t)0x00200000) /*!< Base address of module FL_BOOTOVER_MAILBOX registers */ 302 #define PCM_BASE (PERIPH_BASE +0x00010000) /*!< Base address of module PCM registers */ 303 #define PMAP_BASE (PERIPH_BASE +0x00005000) /*!< Base address of module PMAP registers */ 304 #define PSS_BASE (PERIPH_BASE +0x00010800) /*!< Base address of module PSS registers */ 305 #define REF_A_BASE (PERIPH_BASE +0x00003000) /*!< Base address of module REF_A registers */ 306 #define RSTCTL_BASE (PERIPH_BASE2+0x00042000) /*!< Base address of module RSTCTL registers */ 307 #define RTC_C_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ 308 #define RTC_C_BCD_BASE (PERIPH_BASE +0x00004400) /*!< Base address of module RTC_C registers */ 309 #define SYSCTL_BASE (PERIPH_BASE2+0x00043000) /*!< Base address of module SYSCTL registers */ 310 #define TIMER32_BASE (PERIPH_BASE +0x0000C000) /*!< Base address of module TIMER32 registers */ 311 #define TIMER_A0_BASE (PERIPH_BASE +0x00000000) /*!< Base address of module TIMER_A0 registers */ 312 #define TIMER_A1_BASE (PERIPH_BASE +0x00000400) /*!< Base address of module TIMER_A1 registers */ 313 #define TIMER_A2_BASE (PERIPH_BASE +0x00000800) /*!< Base address of module TIMER_A2 registers */ 314 #define TIMER_A3_BASE (PERIPH_BASE +0x00000C00) /*!< Base address of module TIMER_A3 registers */ 315 #define TLV_BASE ((uint32_t)0x00201000) /*!< Base address of module TLV registers */ 316 #define WDT_A_BASE (PERIPH_BASE +0x00004800) /*!< Base address of module WDT_A registers */ 317 318 319 /*@}*/ /* end of group MSP432P401R_MemoryMap */ 320 321 /****************************************************************************** 322 * Definitions for bit band access * 323 ******************************************************************************/ 324 #define BITBAND_SRAM_BASE ((uint32_t)(0x22000000)) 325 #define BITBAND_PERI_BASE ((uint32_t)(0x42000000)) 326 327 /* SRAM allows 32 bit bit band access */ 328 #define BITBAND_SRAM(x, b) (*((__IO uint32_t *) (BITBAND_SRAM_BASE + (((uint32_t)(volatile const uint32_t *)&(x)) - SRAM_BASE )*32 + (b)*4))) 329 /* peripherals with 8 bit or 16 bit register access allow only 8 bit or 16 bit bit band access, so cast to 8 bit always */ 330 #define BITBAND_PERI(x, b) (*((__IO uint8_t *) (BITBAND_PERI_BASE + (((uint32_t)(volatile const uint32_t *)&(x)) - PERIPH_BASE)*32 + (b)*4))) 331 332 /****************************************************************************** 333 * Peripheral register definitions * 334 ******************************************************************************/ 335 /** @addtogroup MSP432P401R_Peripherals MSP432P401R Peripherals 336 MSP432P401R Device Specific Peripheral registers structures 337 @{ 338 */ 339 340 /* ------- Start of section using anonymous unions and disabling warnings ------- */ 341 #if defined (__CC_ARM) 342 #pragma push 343 #pragma anon_unions 344 #elif defined (__ICCARM__) 345 #pragma language=extended 346 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 347 #pragma clang diagnostic push 348 #pragma clang diagnostic ignored "-Wc11-extensions" 349 #elif defined (__GNUC__) 350 /* anonymous unions are enabled by default */ 351 #elif defined (__TI_ARM__) 352 /* anonymous unions are enabled by default */ 353 #else 354 #warning Not supported compiler type 355 #endif 356 357 358 /****************************************************************************** 359 * ADC14 Registers 360 ******************************************************************************/ 361 /** @addtogroup ADC14 MSP432P401R (ADC14) 362 @{ 363 */ 364 typedef struct { 365 __IO uint32_t CTL0; /*!< Control 0 Register */ 366 __IO uint32_t CTL1; /*!< Control 1 Register */ 367 __IO uint32_t LO0; /*!< Window Comparator Low Threshold 0 Register */ 368 __IO uint32_t HI0; /*!< Window Comparator High Threshold 0 Register */ 369 __IO uint32_t LO1; /*!< Window Comparator Low Threshold 1 Register */ 370 __IO uint32_t HI1; /*!< Window Comparator High Threshold 1 Register */ 371 __IO uint32_t MCTL[32]; /*!< Conversion Memory Control Register */ 372 __IO uint32_t MEM[32]; /*!< Conversion Memory Register */ 373 uint32_t RESERVED0[9]; 374 __IO uint32_t IER0; /*!< Interrupt Enable 0 Register */ 375 __IO uint32_t IER1; /*!< Interrupt Enable 1 Register */ 376 __I uint32_t IFGR0; /*!< Interrupt Flag 0 Register */ 377 __I uint32_t IFGR1; /*!< Interrupt Flag 1 Register */ 378 __O uint32_t CLRIFGR0; /*!< Clear Interrupt Flag 0 Register */ 379 __IO uint32_t CLRIFGR1; /*!< Clear Interrupt Flag 1 Register */ 380 __IO uint32_t IV; /*!< Interrupt Vector Register */ 381 } ADC14_Type; 382 383 /*@}*/ /* end of group ADC14 */ 384 385 386 /****************************************************************************** 387 * AES256 Registers 388 ******************************************************************************/ 389 /** @addtogroup AES256 MSP432P401R (AES256) 390 @{ 391 */ 392 typedef struct { 393 __IO uint16_t CTL0; /*!< AES Accelerator Control Register 0 */ 394 __IO uint16_t CTL1; /*!< AES Accelerator Control Register 1 */ 395 __IO uint16_t STAT; /*!< AES Accelerator Status Register */ 396 __O uint16_t KEY; /*!< AES Accelerator Key Register */ 397 __O uint16_t DIN; /*!< AES Accelerator Data In Register */ 398 __O uint16_t DOUT; /*!< AES Accelerator Data Out Register */ 399 __O uint16_t XDIN; /*!< AES Accelerator XORed Data In Register */ 400 __O uint16_t XIN; /*!< AES Accelerator XORed Data In Register */ 401 } AES256_Type; 402 403 /*@}*/ /* end of group AES256 */ 404 405 406 /****************************************************************************** 407 * CAPTIO Registers 408 ******************************************************************************/ 409 /** @addtogroup CAPTIO MSP432P401R (CAPTIO) 410 @{ 411 */ 412 typedef struct { 413 uint16_t RESERVED0[7]; 414 __IO uint16_t CTL; /*!< Capacitive Touch IO x Control Register */ 415 } CAPTIO_Type; 416 417 /*@}*/ /* end of group CAPTIO */ 418 419 420 /****************************************************************************** 421 * COMP_E Registers 422 ******************************************************************************/ 423 /** @addtogroup COMP_E MSP432P401R (COMP_E) 424 @{ 425 */ 426 typedef struct { 427 __IO uint16_t CTL0; /*!< Comparator Control Register 0 */ 428 __IO uint16_t CTL1; /*!< Comparator Control Register 1 */ 429 __IO uint16_t CTL2; /*!< Comparator Control Register 2 */ 430 __IO uint16_t CTL3; /*!< Comparator Control Register 3 */ 431 uint16_t RESERVED0[2]; 432 __IO uint16_t INT; /*!< Comparator Interrupt Control Register */ 433 __I uint16_t IV; /*!< Comparator Interrupt Vector Word Register */ 434 } COMP_E_Type; 435 436 /*@}*/ /* end of group COMP_E */ 437 438 439 /****************************************************************************** 440 * CRC32 Registers 441 ******************************************************************************/ 442 /** @addtogroup CRC32 MSP432P401R (CRC32) 443 @{ 444 */ 445 typedef struct { 446 __IO uint16_t DI32; /*!< Data Input for CRC32 Signature Computation */ 447 uint16_t RESERVED0; 448 __IO uint16_t DIRB32; /*!< Data In Reverse for CRC32 Computation */ 449 uint16_t RESERVED1; 450 __IO uint16_t INIRES32_LO; /*!< CRC32 Initialization and Result, lower 16 bits */ 451 __IO uint16_t INIRES32_HI; /*!< CRC32 Initialization and Result, upper 16 bits */ 452 __IO uint16_t RESR32_LO; /*!< CRC32 Result Reverse, lower 16 bits */ 453 __IO uint16_t RESR32_HI; /*!< CRC32 Result Reverse, Upper 16 bits */ 454 __IO uint16_t DI16; /*!< Data Input for CRC16 computation */ 455 uint16_t RESERVED2; 456 __IO uint16_t DIRB16; /*!< CRC16 Data In Reverse */ 457 uint16_t RESERVED3; 458 __IO uint16_t INIRES16; /*!< CRC16 Initialization and Result register */ 459 uint16_t RESERVED4[2]; 460 __IO uint16_t RESR16; /*!< CRC16 Result Reverse */ 461 } CRC32_Type; 462 463 /*@}*/ /* end of group CRC32 */ 464 465 466 /****************************************************************************** 467 * CS Registers 468 ******************************************************************************/ 469 /** @addtogroup CS MSP432P401R (CS) 470 @{ 471 */ 472 typedef struct { 473 __IO uint32_t KEY; /*!< Key Register */ 474 __IO uint32_t CTL0; /*!< Control 0 Register */ 475 __IO uint32_t CTL1; /*!< Control 1 Register */ 476 __IO uint32_t CTL2; /*!< Control 2 Register */ 477 __IO uint32_t CTL3; /*!< Control 3 Register */ 478 uint32_t RESERVED0[7]; 479 __IO uint32_t CLKEN; /*!< Clock Enable Register */ 480 __I uint32_t STAT; /*!< Status Register */ 481 uint32_t RESERVED1[2]; 482 __IO uint32_t IE; /*!< Interrupt Enable Register */ 483 uint32_t RESERVED2; 484 __I uint32_t IFG; /*!< Interrupt Flag Register */ 485 uint32_t RESERVED3; 486 __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 487 uint32_t RESERVED4; 488 __O uint32_t SETIFG; /*!< Set Interrupt Flag Register */ 489 uint32_t RESERVED5; 490 __IO uint32_t DCOERCAL0; /*!< DCO External Resistor Cailbration 0 Register */ 491 __IO uint32_t DCOERCAL1; /*!< DCO External Resistor Calibration 1 Register */ 492 } CS_Type; 493 494 /*@}*/ /* end of group CS */ 495 496 497 /****************************************************************************** 498 * DIO Registers 499 ******************************************************************************/ 500 /** @addtogroup DIO MSP432P401R (DIO) 501 @{ 502 */ 503 typedef struct { 504 union { 505 __I uint16_t IN; /*!< Port Pair Input */ 506 struct { 507 __I uint8_t IN_L; /*!< Low Port Input */ 508 __I uint8_t IN_H; /*!< High Port Input */ 509 }; 510 }; 511 union { 512 __IO uint16_t OUT; /*!< Port Pair Output */ 513 struct { 514 __IO uint8_t OUT_L; /*!< Low Port Output */ 515 __IO uint8_t OUT_H; /*!< High Port Output */ 516 }; 517 }; 518 union { 519 __IO uint16_t DIR; /*!< Port Pair Direction */ 520 struct { 521 __IO uint8_t DIR_L; /*!< Low Port Direction */ 522 __IO uint8_t DIR_H; /*!< High Port Direction */ 523 }; 524 }; 525 union { 526 __IO uint16_t REN; /*!< Port Pair Resistor Enable */ 527 struct { 528 __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ 529 __IO uint8_t REN_H; /*!< High Port Resistor Enable */ 530 }; 531 }; 532 union { 533 __IO uint16_t DS; /*!< Port Pair Drive Strength */ 534 struct { 535 __IO uint8_t DS_L; /*!< Low Port Drive Strength */ 536 __IO uint8_t DS_H; /*!< High Port Drive Strength */ 537 }; 538 }; 539 union { 540 __IO uint16_t SEL0; /*!< Port Pair Select 0 */ 541 struct { 542 __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ 543 __IO uint8_t SEL0_H; /*!< High Port Select 0 */ 544 }; 545 }; 546 union { 547 __IO uint16_t SEL1; /*!< Port Pair Select 1 */ 548 struct { 549 __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ 550 __IO uint8_t SEL1_H; /*!< High Port Select 1 */ 551 }; 552 }; 553 __I uint16_t IV_L; /*!< Low Port Interrupt Vector Value */ 554 uint16_t RESERVED0[3]; 555 union { 556 __IO uint16_t SELC; /*!< Port Pair Complement Select */ 557 struct { 558 __IO uint8_t SELC_L; /*!< Low Port Complement Select */ 559 __IO uint8_t SELC_H; /*!< High Port Complement Select */ 560 }; 561 }; 562 union { 563 __IO uint16_t IES; /*!< Port Pair Interrupt Edge Select */ 564 struct { 565 __IO uint8_t IES_L; /*!< Low Port Interrupt Edge Select */ 566 __IO uint8_t IES_H; /*!< High Port Interrupt Edge Select */ 567 }; 568 }; 569 union { 570 __IO uint16_t IE; /*!< Port Pair Interrupt Enable */ 571 struct { 572 __IO uint8_t IE_L; /*!< Low Port Interrupt Enable */ 573 __IO uint8_t IE_H; /*!< High Port Interrupt Enable */ 574 }; 575 }; 576 union { 577 __IO uint16_t IFG; /*!< Port Pair Interrupt Flag */ 578 struct { 579 __IO uint8_t IFG_L; /*!< Low Port Interrupt Flag */ 580 __IO uint8_t IFG_H; /*!< High Port Interrupt Flag */ 581 }; 582 }; 583 __I uint16_t IV_H; /*!< High Port Interrupt Vector Value */ 584 } DIO_PORT_Interruptable_Type; 585 586 typedef struct { 587 union { 588 __I uint16_t IN; /*!< Port Pair Input */ 589 struct { 590 __I uint8_t IN_L; /*!< Low Port Input */ 591 __I uint8_t IN_H; /*!< High Port Input */ 592 }; 593 }; 594 union { 595 __IO uint16_t OUT; /*!< Port Pair Output */ 596 struct { 597 __IO uint8_t OUT_L; /*!< Low Port Output */ 598 __IO uint8_t OUT_H; /*!< High Port Output */ 599 }; 600 }; 601 union { 602 __IO uint16_t DIR; /*!< Port Pair Direction */ 603 struct { 604 __IO uint8_t DIR_L; /*!< Low Port Direction */ 605 __IO uint8_t DIR_H; /*!< High Port Direction */ 606 }; 607 }; 608 union { 609 __IO uint16_t REN; /*!< Port Pair Resistor Enable */ 610 struct { 611 __IO uint8_t REN_L; /*!< Low Port Resistor Enable */ 612 __IO uint8_t REN_H; /*!< High Port Resistor Enable */ 613 }; 614 }; 615 union { 616 __IO uint16_t DS; /*!< Port Pair Drive Strength */ 617 struct { 618 __IO uint8_t DS_L; /*!< Low Port Drive Strength */ 619 __IO uint8_t DS_H; /*!< High Port Drive Strength */ 620 }; 621 }; 622 union { 623 __IO uint16_t SEL0; /*!< Port Pair Select 0 */ 624 struct { 625 __IO uint8_t SEL0_L; /*!< Low Port Select 0 */ 626 __IO uint8_t SEL0_H; /*!< High Port Select 0 */ 627 }; 628 }; 629 union { 630 __IO uint16_t SEL1; /*!< Port Pair Select 1 */ 631 struct { 632 __IO uint8_t SEL1_L; /*!< Low Port Select 1 */ 633 __IO uint8_t SEL1_H; /*!< High Port Select 1 */ 634 }; 635 }; 636 uint16_t RESERVED0[4]; 637 union { 638 __IO uint16_t SELC; /*!< Port Pair Complement Select */ 639 struct { 640 __IO uint8_t SELC_L; /*!< Low Port Complement Select */ 641 __IO uint8_t SELC_H; /*!< High Port Complement Select */ 642 }; 643 }; 644 } DIO_PORT_Not_Interruptable_Type; 645 646 647 typedef struct { 648 __I uint8_t IN; /*!< Port Input */ 649 uint8_t RESERVED0; 650 __IO uint8_t OUT; /*!< Port Output */ 651 uint8_t RESERVED1; 652 __IO uint8_t DIR; /*!< Port Direction */ 653 uint8_t RESERVED2; 654 __IO uint8_t REN; /*!< Port Resistor Enable */ 655 uint8_t RESERVED3; 656 __IO uint8_t DS; /*!< Port Drive Strength */ 657 uint8_t RESERVED4; 658 __IO uint8_t SEL0; /*!< Port Select 0 */ 659 uint8_t RESERVED5; 660 __IO uint8_t SEL1; /*!< Port Select 1 */ 661 uint8_t RESERVED6; 662 __I uint16_t IV; /*!< Port Interrupt Vector Value */ 663 uint8_t RESERVED7[6]; 664 __IO uint8_t SELC; /*!< Port Complement Select */ 665 uint8_t RESERVED8; 666 __IO uint8_t IES; /*!< Port Interrupt Edge Select */ 667 uint8_t RESERVED9; 668 __IO uint8_t IE; /*!< Port Interrupt Enable */ 669 uint8_t RESERVED10; 670 __IO uint8_t IFG; /*!< Port Interrupt Flag */ 671 uint8_t RESERVED11; 672 } DIO_PORT_Odd_Interruptable_Type; 673 674 typedef struct { 675 uint8_t RESERVED0; 676 __I uint8_t IN; /*!< Port Input */ 677 uint8_t RESERVED1; 678 __IO uint8_t OUT; /*!< Port Output */ 679 uint8_t RESERVED2; 680 __IO uint8_t DIR; /*!< Port Direction */ 681 uint8_t RESERVED3; 682 __IO uint8_t REN; /*!< Port Resistor Enable */ 683 uint8_t RESERVED4; 684 __IO uint8_t DS; /*!< Port Drive Strength */ 685 uint8_t RESERVED5; 686 __IO uint8_t SEL0; /*!< Port Select 0 */ 687 uint8_t RESERVED6; 688 __IO uint8_t SEL1; /*!< Port Select 1 */ 689 uint8_t RESERVED7[9]; 690 __IO uint8_t SELC; /*!< Port Complement Select */ 691 uint8_t RESERVED8; 692 __IO uint8_t IES; /*!< Port Interrupt Edge Select */ 693 uint8_t RESERVED9; 694 __IO uint8_t IE; /*!< Port Interrupt Enable */ 695 uint8_t RESERVED10; 696 __IO uint8_t IFG; /*!< Port Interrupt Flag */ 697 __I uint16_t IV; /*!< Port Interrupt Vector Value */ 698 } DIO_PORT_Even_Interruptable_Type; 699 700 /*@}*/ /* end of group MSP432P401R_DIO */ 701 702 703 /****************************************************************************** 704 * DMA Registers 705 ******************************************************************************/ 706 /** @addtogroup DMA MSP432P401R (DMA) 707 @{ 708 */ 709 typedef struct { 710 __I uint32_t DEVICE_CFG; /*!< Device Configuration Status */ 711 __IO uint32_t SW_CHTRIG; /*!< Software Channel Trigger Register */ 712 uint32_t RESERVED0[2]; 713 __IO uint32_t CH_SRCCFG[32]; /*!< Channel n Source Configuration Register */ 714 uint32_t RESERVED1[28]; 715 __IO uint32_t INT1_SRCCFG; /*!< Interrupt 1 Source Channel Configuration */ 716 __IO uint32_t INT2_SRCCFG; /*!< Interrupt 2 Source Channel Configuration Register */ 717 __IO uint32_t INT3_SRCCFG; /*!< Interrupt 3 Source Channel Configuration Register */ 718 uint32_t RESERVED2; 719 __I uint32_t INT0_SRCFLG; /*!< Interrupt 0 Source Channel Flag Register */ 720 __O uint32_t INT0_CLRFLG; /*!< Interrupt 0 Source Channel Clear Flag Register */ 721 } DMA_Channel_Type; 722 723 typedef struct { 724 __I uint32_t STAT; /*!< Status Register */ 725 __O uint32_t CFG; /*!< Configuration Register */ 726 __IO uint32_t CTLBASE; /*!< Channel Control Data Base Pointer Register */ 727 __I uint32_t ALTBASE; /*!< Channel Alternate Control Data Base Pointer Register */ 728 __I uint32_t WAITSTAT; /*!< Channel Wait on Request Status Register */ 729 __O uint32_t SWREQ; /*!< Channel Software Request Register */ 730 __IO uint32_t USEBURSTSET; /*!< Channel Useburst Set Register */ 731 __O uint32_t USEBURSTCLR; /*!< Channel Useburst Clear Register */ 732 __IO uint32_t REQMASKSET; /*!< Channel Request Mask Set Register */ 733 __O uint32_t REQMASKCLR; /*!< Channel Request Mask Clear Register */ 734 __IO uint32_t ENASET; /*!< Channel Enable Set Register */ 735 __O uint32_t ENACLR; /*!< Channel Enable Clear Register */ 736 __IO uint32_t ALTSET; /*!< Channel Primary-Alternate Set Register */ 737 __O uint32_t ALTCLR; /*!< Channel Primary-Alternate Clear Register */ 738 __IO uint32_t PRIOSET; /*!< Channel Priority Set Register */ 739 __O uint32_t PRIOCLR; /*!< Channel Priority Clear Register */ 740 uint32_t RESERVED4[3]; 741 __IO uint32_t ERRCLR; /*!< Bus Error Clear Register */ 742 } DMA_Control_Type; 743 744 /*@}*/ /* end of group DMA */ 745 746 747 /****************************************************************************** 748 * EUSCI_A Registers 749 ******************************************************************************/ 750 /** @addtogroup EUSCI_A MSP432P401R (EUSCI_A) 751 @{ 752 */ 753 typedef struct { 754 __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ 755 __IO uint16_t CTLW1; /*!< eUSCI_Ax Control Word Register 1 */ 756 uint16_t RESERVED0; 757 __IO uint16_t BRW; /*!< eUSCI_Ax Baud Rate Control Word Register */ 758 __IO uint16_t MCTLW; /*!< eUSCI_Ax Modulation Control Word Register */ 759 __IO uint16_t STATW; /*!< eUSCI_Ax Status Register */ 760 __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ 761 __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ 762 __IO uint16_t ABCTL; /*!< eUSCI_Ax Auto Baud Rate Control Register */ 763 __IO uint16_t IRCTL; /*!< eUSCI_Ax IrDA Control Word Register */ 764 uint16_t RESERVED1[3]; 765 __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ 766 __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ 767 __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ 768 } EUSCI_A_Type; 769 770 /*@}*/ /* end of group EUSCI_A */ 771 772 /** @addtogroup EUSCI_A_SPI MSP432P401R (EUSCI_A_SPI) 773 @{ 774 */ 775 typedef struct { 776 __IO uint16_t CTLW0; /*!< eUSCI_Ax Control Word Register 0 */ 777 uint16_t RESERVED0[2]; 778 __IO uint16_t BRW; /*!< eUSCI_Ax Bit Rate Control Register 1 */ 779 uint16_t RESERVED1; 780 __IO uint16_t STATW; 781 __I uint16_t RXBUF; /*!< eUSCI_Ax Receive Buffer Register */ 782 __IO uint16_t TXBUF; /*!< eUSCI_Ax Transmit Buffer Register */ 783 uint16_t RESERVED2[5]; 784 __IO uint16_t IE; /*!< eUSCI_Ax Interrupt Enable Register */ 785 __IO uint16_t IFG; /*!< eUSCI_Ax Interrupt Flag Register */ 786 __I uint16_t IV; /*!< eUSCI_Ax Interrupt Vector Register */ 787 } EUSCI_A_SPI_Type; 788 789 /*@}*/ /* end of group EUSCI_A_SPI */ 790 791 792 /****************************************************************************** 793 * EUSCI_B Registers 794 ******************************************************************************/ 795 /** @addtogroup EUSCI_B MSP432P401R (EUSCI_B) 796 @{ 797 */ 798 typedef struct { 799 __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ 800 __IO uint16_t CTLW1; /*!< eUSCI_Bx Control Word Register 1 */ 801 uint16_t RESERVED0; 802 __IO uint16_t BRW; /*!< eUSCI_Bx Baud Rate Control Word Register */ 803 __IO uint16_t STATW; /*!< eUSCI_Bx Status Register */ 804 __IO uint16_t TBCNT; /*!< eUSCI_Bx Byte Counter Threshold Register */ 805 __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ 806 __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ 807 uint16_t RESERVED1[2]; 808 __IO uint16_t I2COA0; /*!< eUSCI_Bx I2C Own Address 0 Register */ 809 __IO uint16_t I2COA1; /*!< eUSCI_Bx I2C Own Address 1 Register */ 810 __IO uint16_t I2COA2; /*!< eUSCI_Bx I2C Own Address 2 Register */ 811 __IO uint16_t I2COA3; /*!< eUSCI_Bx I2C Own Address 3 Register */ 812 __I uint16_t ADDRX; /*!< eUSCI_Bx I2C Received Address Register */ 813 __IO uint16_t ADDMASK; /*!< eUSCI_Bx I2C Address Mask Register */ 814 __IO uint16_t I2CSA; /*!< eUSCI_Bx I2C Slave Address Register */ 815 uint16_t RESERVED2[4]; 816 __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ 817 __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ 818 __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ 819 } EUSCI_B_Type; 820 821 /*@}*/ /* end of group EUSCI_B */ 822 823 /** @addtogroup EUSCI_B_SPI MSP432P401R (EUSCI_B_SPI) 824 @{ 825 */ 826 typedef struct { 827 __IO uint16_t CTLW0; /*!< eUSCI_Bx Control Word Register 0 */ 828 uint16_t RESERVED0[2]; 829 __IO uint16_t BRW; /*!< eUSCI_Bx Bit Rate Control Register 1 */ 830 __IO uint16_t STATW; 831 uint16_t RESERVED1; 832 __I uint16_t RXBUF; /*!< eUSCI_Bx Receive Buffer Register */ 833 __IO uint16_t TXBUF; /*!< eUSCI_Bx Transmit Buffer Register */ 834 uint16_t RESERVED2[13]; 835 __IO uint16_t IE; /*!< eUSCI_Bx Interrupt Enable Register */ 836 __IO uint16_t IFG; /*!< eUSCI_Bx Interrupt Flag Register */ 837 __I uint16_t IV; /*!< eUSCI_Bx Interrupt Vector Register */ 838 } EUSCI_B_SPI_Type; 839 840 /*@}*/ /* end of group EUSCI_B_SPI */ 841 842 843 /****************************************************************************** 844 * FLCTL Registers 845 ******************************************************************************/ 846 /** @addtogroup FLCTL MSP432P401R (FLCTL) 847 @{ 848 */ 849 typedef struct { 850 __I uint32_t POWER_STAT; /*!< Power Status Register */ 851 uint32_t RESERVED0[3]; 852 __IO uint32_t BANK0_RDCTL; /*!< Bank0 Read Control Register */ 853 __IO uint32_t BANK1_RDCTL; /*!< Bank1 Read Control Register */ 854 uint32_t RESERVED1[2]; 855 __IO uint32_t RDBRST_CTLSTAT; /*!< Read Burst/Compare Control and Status Register */ 856 __IO uint32_t RDBRST_STARTADDR; /*!< Read Burst/Compare Start Address Register */ 857 __IO uint32_t RDBRST_LEN; /*!< Read Burst/Compare Length Register */ 858 uint32_t RESERVED2[4]; 859 __IO uint32_t RDBRST_FAILADDR; /*!< Read Burst/Compare Fail Address Register */ 860 __IO uint32_t RDBRST_FAILCNT; /*!< Read Burst/Compare Fail Count Register */ 861 uint32_t RESERVED3[3]; 862 __IO uint32_t PRG_CTLSTAT; /*!< Program Control and Status Register */ 863 __IO uint32_t PRGBRST_CTLSTAT; /*!< Program Burst Control and Status Register */ 864 __IO uint32_t PRGBRST_STARTADDR; /*!< Program Burst Start Address Register */ 865 uint32_t RESERVED4; 866 __IO uint32_t PRGBRST_DATA0_0; /*!< Program Burst Data0 Register0 */ 867 __IO uint32_t PRGBRST_DATA0_1; /*!< Program Burst Data0 Register1 */ 868 __IO uint32_t PRGBRST_DATA0_2; /*!< Program Burst Data0 Register2 */ 869 __IO uint32_t PRGBRST_DATA0_3; /*!< Program Burst Data0 Register3 */ 870 __IO uint32_t PRGBRST_DATA1_0; /*!< Program Burst Data1 Register0 */ 871 __IO uint32_t PRGBRST_DATA1_1; /*!< Program Burst Data1 Register1 */ 872 __IO uint32_t PRGBRST_DATA1_2; /*!< Program Burst Data1 Register2 */ 873 __IO uint32_t PRGBRST_DATA1_3; /*!< Program Burst Data1 Register3 */ 874 __IO uint32_t PRGBRST_DATA2_0; /*!< Program Burst Data2 Register0 */ 875 __IO uint32_t PRGBRST_DATA2_1; /*!< Program Burst Data2 Register1 */ 876 __IO uint32_t PRGBRST_DATA2_2; /*!< Program Burst Data2 Register2 */ 877 __IO uint32_t PRGBRST_DATA2_3; /*!< Program Burst Data2 Register3 */ 878 __IO uint32_t PRGBRST_DATA3_0; /*!< Program Burst Data3 Register0 */ 879 __IO uint32_t PRGBRST_DATA3_1; /*!< Program Burst Data3 Register1 */ 880 __IO uint32_t PRGBRST_DATA3_2; /*!< Program Burst Data3 Register2 */ 881 __IO uint32_t PRGBRST_DATA3_3; /*!< Program Burst Data3 Register3 */ 882 __IO uint32_t ERASE_CTLSTAT; /*!< Erase Control and Status Register */ 883 __IO uint32_t ERASE_SECTADDR; /*!< Erase Sector Address Register */ 884 uint32_t RESERVED5[2]; 885 __IO uint32_t BANK0_INFO_WEPROT; /*!< Information Memory Bank0 Write/Erase Protection Register */ 886 __IO uint32_t BANK0_MAIN_WEPROT; /*!< Main Memory Bank0 Write/Erase Protection Register */ 887 uint32_t RESERVED6[2]; 888 __IO uint32_t BANK1_INFO_WEPROT; /*!< Information Memory Bank1 Write/Erase Protection Register */ 889 __IO uint32_t BANK1_MAIN_WEPROT; /*!< Main Memory Bank1 Write/Erase Protection Register */ 890 uint32_t RESERVED7[2]; 891 __IO uint32_t BMRK_CTLSTAT; /*!< Benchmark Control and Status Register */ 892 __IO uint32_t BMRK_IFETCH; /*!< Benchmark Instruction Fetch Count Register */ 893 __IO uint32_t BMRK_DREAD; /*!< Benchmark Data Read Count Register */ 894 __IO uint32_t BMRK_CMP; /*!< Benchmark Count Compare Register */ 895 uint32_t RESERVED8[4]; 896 __IO uint32_t IFG; /*!< Interrupt Flag Register */ 897 __IO uint32_t IE; /*!< Interrupt Enable Register */ 898 __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 899 __IO uint32_t SETIFG; /*!< Set Interrupt Flag Register */ 900 __I uint32_t READ_TIMCTL; /*!< Read Timing Control Register */ 901 __I uint32_t READMARGIN_TIMCTL; /*!< Read Margin Timing Control Register */ 902 __I uint32_t PRGVER_TIMCTL; /*!< Program Verify Timing Control Register */ 903 __I uint32_t ERSVER_TIMCTL; /*!< Erase Verify Timing Control Register */ 904 __I uint32_t LKGVER_TIMCTL; /*!< Leakage Verify Timing Control Register */ 905 __I uint32_t PROGRAM_TIMCTL; /*!< Program Timing Control Register */ 906 __I uint32_t ERASE_TIMCTL; /*!< Erase Timing Control Register */ 907 __I uint32_t MASSERASE_TIMCTL; /*!< Mass Erase Timing Control Register */ 908 __I uint32_t BURSTPRG_TIMCTL; /*!< Burst Program Timing Control Register */ 909 } FLCTL_Type; 910 911 /*@}*/ /* end of group FLCTL */ 912 913 914 /****************************************************************************** 915 * FL_BOOTOVER_MAILBOX Registers 916 ******************************************************************************/ 917 /** @addtogroup SEC_ZONE_PARAMS MSP432P401R (FL_BOOTOVER_MAILBOX) 918 @{ 919 */ 920 typedef struct { 921 __IO uint32_t SEC_ZONE_SECEN; /*!< IP Protection Secure Zone Enable. */ 922 __IO uint32_t SEC_ZONE_START_ADDR; /*!< Start address of IP protected secure zone. */ 923 __IO uint32_t SEC_ZONE_LENGTH; /*!< Length of IP protected secure zone in number of bytes. */ 924 __IO uint32_t SEC_ZONE_AESINIT_VECT[4]; /*!< IP protected secure zone 0 AES initialization vector */ 925 __IO uint32_t SEC_ZONE_SECKEYS[8]; /*!< AES-CBC security keys. */ 926 __IO uint32_t SEC_ZONE_UNENC_PWD[4]; /*!< Unencrypted password for authentication. */ 927 __IO uint32_t SEC_ZONE_ENCUPDATE_EN; /*!< IP Protected Secure Zone Encrypted In-field Update Enable */ 928 __IO uint32_t SEC_ZONE_DATA_EN; /*!< IP Protected Secure Zone Data Access Enable */ 929 __IO uint32_t SEC_ZONE_ACK; /*!< Acknowledgment for IP Protection Secure Zone Enable Command. */ 930 uint32_t RESERVED0[2]; 931 } SEC_ZONE_PARAMS_Type; 932 933 /*@}*/ /* end of group SEC_ZONE_PARAMS */ 934 935 /** @addtogroup SEC_ZONE_UPDATE MSP432P401R (FL_BOOTOVER_MAILBOX) 936 @{ 937 */ 938 typedef struct { 939 __IO uint32_t SEC_ZONE_PAYLOADADDR; /*!< Start address where the payload is loaded in the device. */ 940 __IO uint32_t SEC_ZONE_PAYLOADLEN; /*!< Length of the payload in bytes. */ 941 __IO uint32_t SEC_ZONE_UPDATE_ACK; /*!< Acknowledgment for the IP Protected Secure Zone Update Command */ 942 uint32_t RESERVED0; 943 } SEC_ZONE_UPDATE_Type; 944 945 /*@}*/ /* end of group SEC_ZONE_UPDATE */ 946 947 /** @addtogroup FL_BOOTOVER_MAILBOX MSP432P401R (FL_BOOTOVER_MAILBOX) 948 @{ 949 */ 950 typedef struct { 951 __IO uint32_t MB_START; /*!< Flash MailBox start: 0x0115ACF6 */ 952 __IO uint32_t CMD; /*!< Command for Boot override operations. */ 953 uint32_t RESERVED0[2]; 954 __IO uint32_t JTAG_SWD_LOCK_SECEN; /*!< JTAG and SWD Lock Enable */ 955 __IO uint32_t JTAG_SWD_LOCK_AES_INIT_VECT[4]; /*!< JTAG and SWD lock AES initialization vector for AES-CBC */ 956 __IO uint32_t JTAG_SWD_LOCK_AES_SECKEYS[8]; /*!< JTAG and SWD lock AES CBC security Keys 0-7. */ 957 __IO uint32_t JTAG_SWD_LOCK_UNENC_PWD[4]; /*!< JTAG and SWD lock unencrypted password */ 958 __IO uint32_t JTAG_SWD_LOCK_ACK; /*!< Acknowledgment for JTAG and SWD Lock command */ 959 uint32_t RESERVED1[2]; 960 SEC_ZONE_PARAMS_Type SEC_ZONE_PARAMS[4]; 961 __IO uint32_t BSL_ENABLE; /*!< BSL Enable. */ 962 __IO uint32_t BSL_START_ADDRESS; /*!< Contains the pointer to the BSL function. */ 963 __IO uint32_t BSL_PARAMETERS; /*!< BSL hardware invoke conifguration field. */ 964 uint32_t RESERVED2[2]; 965 __IO uint32_t BSL_ACK; /*!< Acknowledgment for the BSL Configuration Command */ 966 __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADADD; /*!< Start address where the payload is loaded in the device. */ 967 __IO uint32_t JTAG_SWD_LOCK_ENCPAYLOADLEN; /*!< Length of the encrypted payload in bytes */ 968 __IO uint32_t JTAG_SWD_LOCK_DST_ADDR; /*!< Destination address where the final data needs to be stored into the device. */ 969 __IO uint32_t ENC_UPDATE_ACK; /*!< Acknowledgment for JTAG and SWD Lock Encrypted Update Command */ 970 uint32_t RESERVED3; 971 SEC_ZONE_UPDATE_Type SEC_ZONE_UPDATE[4]; 972 uint32_t RESERVED4; 973 __IO uint32_t FACTORY_RESET_ENABLE; /*!< Enable/Disable Factory Reset */ 974 __IO uint32_t FACTORY_RESET_PWDEN; /*!< Factory reset password enable */ 975 __IO uint32_t FACTORY_RESET_PWD[4]; /*!< 128-bit Password for factory reset to be saved into the device. */ 976 __IO uint32_t FACTORY_RESET_PARAMS_ACK; /*!< Acknowledgment for the Factory Reset Params Command */ 977 uint32_t RESERVED5; 978 __IO uint32_t FACTORY_RESET_PASSWORD[4]; /*!< 128-bit Password for factory reset. */ 979 __IO uint32_t FACTORY_RESET_ACK; /*!< Acknowledgment for the Factory Reset Command */ 980 uint32_t RESERVED6[2]; 981 __IO uint32_t MB_END; /*!< Mailbox end */ 982 } FL_BOOTOVER_MAILBOX_Type; 983 984 /*@}*/ /* end of group FL_BOOTOVER_MAILBOX */ 985 986 987 /****************************************************************************** 988 * PCM Registers 989 ******************************************************************************/ 990 /** @addtogroup PCM MSP432P401R (PCM) 991 @{ 992 */ 993 typedef struct { 994 __IO uint32_t CTL0; /*!< Control 0 Register */ 995 __IO uint32_t CTL1; /*!< Control 1 Register */ 996 __IO uint32_t IE; /*!< Interrupt Enable Register */ 997 __I uint32_t IFG; /*!< Interrupt Flag Register */ 998 __O uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 999 } PCM_Type; 1000 1001 /*@}*/ /* end of group PCM */ 1002 1003 1004 /****************************************************************************** 1005 * PMAP Registers 1006 ******************************************************************************/ 1007 /** @addtogroup PMAP MSP432P401R (PMAP) 1008 @{ 1009 */ 1010 typedef struct { 1011 __IO uint16_t KEYID; 1012 __IO uint16_t CTL; 1013 } PMAP_COMMON_Type; 1014 1015 typedef struct { 1016 union { 1017 __IO uint16_t PMAP_REGISTER[4]; 1018 struct { 1019 __IO uint8_t PMAP_REGISTER0; 1020 __IO uint8_t PMAP_REGISTER1; 1021 __IO uint8_t PMAP_REGISTER2; 1022 __IO uint8_t PMAP_REGISTER3; 1023 __IO uint8_t PMAP_REGISTER4; 1024 __IO uint8_t PMAP_REGISTER5; 1025 __IO uint8_t PMAP_REGISTER6; 1026 __IO uint8_t PMAP_REGISTER7; 1027 }; 1028 }; 1029 } PMAP_REGISTER_Type; 1030 1031 /*@}*/ /* end of group PMAP */ 1032 1033 1034 /****************************************************************************** 1035 * PSS Registers 1036 ******************************************************************************/ 1037 /** @addtogroup PSS MSP432P401R (PSS) 1038 @{ 1039 */ 1040 typedef struct { 1041 __IO uint32_t KEY; /*!< Key Register */ 1042 __IO uint32_t CTL0; /*!< Control 0 Register */ 1043 uint32_t RESERVED0[11]; 1044 __IO uint32_t IE; /*!< Interrupt Enable Register */ 1045 __I uint32_t IFG; /*!< Interrupt Flag Register */ 1046 __IO uint32_t CLRIFG; /*!< Clear Interrupt Flag Register */ 1047 } PSS_Type; 1048 1049 /*@}*/ /* end of group PSS */ 1050 1051 1052 /****************************************************************************** 1053 * REF_A Registers 1054 ******************************************************************************/ 1055 /** @addtogroup REF_A MSP432P401R (REF_A) 1056 @{ 1057 */ 1058 typedef struct { 1059 __IO uint16_t CTL0; /*!< REF Control Register 0 */ 1060 } REF_A_Type; 1061 1062 /*@}*/ /* end of group REF_A */ 1063 1064 1065 /****************************************************************************** 1066 * RSTCTL Registers 1067 ******************************************************************************/ 1068 /** @addtogroup RSTCTL MSP432P401R (RSTCTL) 1069 @{ 1070 */ 1071 typedef struct { 1072 __IO uint32_t RESET_REQ; /*!< Reset Request Register */ 1073 __I uint32_t HARDRESET_STAT; /*!< Hard Reset Status Register */ 1074 __IO uint32_t HARDRESET_CLR; /*!< Hard Reset Status Clear Register */ 1075 __IO uint32_t HARDRESET_SET; /*!< Hard Reset Status Set Register */ 1076 __I uint32_t SOFTRESET_STAT; /*!< Soft Reset Status Register */ 1077 __IO uint32_t SOFTRESET_CLR; /*!< Soft Reset Status Clear Register */ 1078 __IO uint32_t SOFTRESET_SET; /*!< Soft Reset Status Set Register */ 1079 uint32_t RESERVED0[57]; 1080 __I uint32_t PSSRESET_STAT; /*!< PSS Reset Status Register */ 1081 __IO uint32_t PSSRESET_CLR; /*!< PSS Reset Status Clear Register */ 1082 __I uint32_t PCMRESET_STAT; /*!< PCM Reset Status Register */ 1083 __IO uint32_t PCMRESET_CLR; /*!< PCM Reset Status Clear Register */ 1084 __I uint32_t PINRESET_STAT; /*!< Pin Reset Status Register */ 1085 __IO uint32_t PINRESET_CLR; /*!< Pin Reset Status Clear Register */ 1086 __I uint32_t REBOOTRESET_STAT; /*!< Reboot Reset Status Register */ 1087 __IO uint32_t REBOOTRESET_CLR; /*!< Reboot Reset Status Clear Register */ 1088 __I uint32_t CSRESET_STAT; /*!< CS Reset Status Register */ 1089 __IO uint32_t CSRESET_CLR; /*!< CS Reset Status Clear Register */ 1090 } RSTCTL_Type; 1091 1092 /*@}*/ /* end of group RSTCTL */ 1093 1094 1095 /****************************************************************************** 1096 * RTC_C Registers 1097 ******************************************************************************/ 1098 /** @addtogroup RTC_C MSP432P401R (RTC_C) 1099 @{ 1100 */ 1101 typedef struct { 1102 __IO uint16_t CTL0; /*!< RTCCTL0 Register */ 1103 __IO uint16_t CTL13; /*!< RTCCTL13 Register */ 1104 __IO uint16_t OCAL; /*!< RTCOCAL Register */ 1105 __IO uint16_t TCMP; /*!< RTCTCMP Register */ 1106 __IO uint16_t PS0CTL; /*!< Real-Time Clock Prescale Timer 0 Control Register */ 1107 __IO uint16_t PS1CTL; /*!< Real-Time Clock Prescale Timer 1 Control Register */ 1108 __IO uint16_t PS; /*!< Real-Time Clock Prescale Timer Counter Register */ 1109 __I uint16_t IV; /*!< Real-Time Clock Interrupt Vector Register */ 1110 __IO uint16_t TIM0; /*!< RTCTIM0 Register Hexadecimal Format */ 1111 __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week */ 1112 __IO uint16_t DATE; /*!< RTCDATE - Hexadecimal Format */ 1113 __IO uint16_t YEAR; /*!< RTCYEAR Register Hexadecimal Format */ 1114 __IO uint16_t AMINHR; /*!< RTCMINHR - Hexadecimal Format */ 1115 __IO uint16_t ADOWDAY; /*!< RTCADOWDAY - Hexadecimal Format */ 1116 __IO uint16_t BIN2BCD; /*!< Binary-to-BCD Conversion Register */ 1117 __IO uint16_t BCD2BIN; /*!< BCD-to-Binary Conversion Register */ 1118 } RTC_C_Type; 1119 1120 /*@}*/ /* end of group RTC_C */ 1121 1122 /** @addtogroup RTC_C_BCD MSP432P401R (RTC_C_BCD) 1123 @{ 1124 */ 1125 typedef struct { 1126 uint16_t RESERVED0[8]; 1127 __IO uint16_t TIM0; /*!< Real-Time Clock Seconds, Minutes Register - BCD Format */ 1128 __IO uint16_t TIM1; /*!< Real-Time Clock Hour, Day of Week - BCD Format */ 1129 __IO uint16_t DATE; /*!< Real-Time Clock Date - BCD Format */ 1130 __IO uint16_t YEAR; /*!< Real-Time Clock Year Register - BCD Format */ 1131 __IO uint16_t AMINHR; /*!< Real-Time Clock Minutes, Hour Alarm - BCD Format */ 1132 __IO uint16_t ADOWDAY; /*!< Real-Time Clock Day of Week, Day of Month Alarm - BCD Format */ 1133 } RTC_C_BCD_Type; 1134 1135 /*@}*/ /* end of group RTC_C_BCD */ 1136 1137 1138 /****************************************************************************** 1139 * SYSCTL Registers 1140 ******************************************************************************/ 1141 /** @addtogroup SYSCTL MSP432P401R (SYSCTL) 1142 @{ 1143 */ 1144 typedef struct { 1145 __IO uint32_t REBOOT_CTL; /*!< Reboot Control Register */ 1146 __IO uint32_t NMI_CTLSTAT; /*!< NMI Control and Status Register */ 1147 __IO uint32_t WDTRESET_CTL; /*!< Watchdog Reset Control Register */ 1148 __IO uint32_t PERIHALT_CTL; /*!< Peripheral Halt Control Register */ 1149 __I uint32_t SRAM_SIZE; /*!< SRAM Size Register */ 1150 __IO uint32_t SRAM_BANKEN; /*!< SRAM Bank Enable Register */ 1151 __IO uint32_t SRAM_BANKRET; /*!< SRAM Bank Retention Control Register */ 1152 uint32_t RESERVED0; 1153 __I uint32_t FLASH_SIZE; /*!< Flash Size Register */ 1154 uint32_t RESERVED1[3]; 1155 __IO uint32_t DIO_GLTFLT_CTL; /*!< Digital I/O Glitch Filter Control Register */ 1156 uint32_t RESERVED2[3]; 1157 __IO uint32_t SECDATA_UNLOCK; /*!< IP Protected Secure Zone Data Access Unlock Register */ 1158 } SYSCTL_Type; 1159 1160 typedef struct { 1161 __IO uint32_t MASTER_UNLOCK; /*!< Master Unlock Register */ 1162 __IO uint32_t BOOTOVER_REQ[2]; /*!< Boot Override Request Register */ 1163 __IO uint32_t BOOTOVER_ACK; /*!< Boot Override Acknowledge Register */ 1164 __IO uint32_t RESET_REQ; /*!< Reset Request Register */ 1165 __IO uint32_t RESET_STATOVER; /*!< Reset Status and Override Register */ 1166 uint32_t RESERVED7[2]; 1167 __I uint32_t SYSTEM_STAT; /*!< System Status Register */ 1168 } SYSCTL_Boot_Type; 1169 1170 /*@}*/ /* end of group SYSCTL */ 1171 1172 1173 /****************************************************************************** 1174 * Timer32 Registers 1175 ******************************************************************************/ 1176 /** @addtogroup Timer32 MSP432P401R (Timer32) 1177 @{ 1178 */ 1179 typedef struct { 1180 __IO uint32_t LOAD; /*!< Timer Load Register */ 1181 __I uint32_t VALUE; /*!< Timer Current Value Register */ 1182 __IO uint32_t CONTROL; /*!< Timer Control Register */ 1183 __O uint32_t INTCLR; /*!< Timer Interrupt Clear Register */ 1184 __I uint32_t RIS; /*!< Timer Raw Interrupt Status Register */ 1185 __I uint32_t MIS; /*!< Timer Interrupt Status Register */ 1186 __IO uint32_t BGLOAD; /*!< Timer Background Load Register */ 1187 } Timer32_Type; 1188 1189 /*@}*/ /* end of group Timer32 */ 1190 1191 1192 /****************************************************************************** 1193 * Timer_A Registers 1194 ******************************************************************************/ 1195 /** @addtogroup Timer_A MSP432P401R (Timer_A) 1196 @{ 1197 */ 1198 typedef struct { 1199 __IO uint16_t CTL; /*!< TimerAx Control Register */ 1200 __IO uint16_t CCTL[5]; /*!< Timer_A Capture/Compare Control Register */ 1201 uint16_t RESERVED0[2]; 1202 __IO uint16_t R; /*!< TimerA register */ 1203 __IO uint16_t CCR[5]; /*!< Timer_A Capture/Compare Register */ 1204 uint16_t RESERVED1[2]; 1205 __IO uint16_t EX0; /*!< TimerAx Expansion 0 Register */ 1206 uint16_t RESERVED2[6]; 1207 __I uint16_t IV; /*!< TimerAx Interrupt Vector Register */ 1208 } Timer_A_Type; 1209 1210 /*@}*/ /* end of group Timer_A */ 1211 1212 1213 /****************************************************************************** 1214 * TLV Registers 1215 ******************************************************************************/ 1216 /** @addtogroup TLV MSP432P401R (TLV) 1217 @{ 1218 */ 1219 typedef struct { 1220 __I uint32_t TLV_CHECKSUM; /*!< TLV Checksum */ 1221 __I uint32_t DEVICE_INFO_TAG; /*!< Device Info Tag */ 1222 __I uint32_t DEVICE_INFO_LEN; /*!< Device Info Length */ 1223 __I uint32_t DEVICE_ID; /*!< Device ID */ 1224 __I uint32_t HWREV; /*!< HW Revision */ 1225 __I uint32_t BCREV; /*!< Boot Code Revision */ 1226 __I uint32_t ROM_DRVLIB_REV; /*!< ROM Driver Library Revision */ 1227 __I uint32_t DIE_REC_TAG; /*!< Die Record Tag */ 1228 __I uint32_t DIE_REC_LEN; /*!< Die Record Length */ 1229 __I uint32_t DIE_XPOS; /*!< Die X-Position */ 1230 __I uint32_t DIE_YPOS; /*!< Die Y-Position */ 1231 __I uint32_t WAFER_ID; /*!< Wafer ID */ 1232 __I uint32_t LOT_ID; /*!< Lot ID */ 1233 __I uint32_t RESERVED0; /*!< Reserved */ 1234 __I uint32_t RESERVED1; /*!< Reserved */ 1235 __I uint32_t RESERVED2; /*!< Reserved */ 1236 __I uint32_t TEST_RESULTS; /*!< Test Results */ 1237 __I uint32_t CS_CAL_TAG; /*!< Clock System Calibration Tag */ 1238 __I uint32_t CS_CAL_LEN; /*!< Clock System Calibration Length */ 1239 __I uint32_t DCOIR_FCAL_RSEL04; /*!< DCO IR mode: Frequency calibration for DCORSEL 0 to 4 */ 1240 __I uint32_t DCOIR_FCAL_RSEL5; /*!< DCO IR mode: Frequency calibration for DCORSEL 5 */ 1241 __I uint32_t RESERVED3; /*!< Reserved */ 1242 __I uint32_t RESERVED4; /*!< Reserved */ 1243 __I uint32_t RESERVED5; /*!< Reserved */ 1244 __I uint32_t RESERVED6; /*!< Reserved */ 1245 __I uint32_t DCOIR_CONSTK_RSEL04; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 0 to 4 */ 1246 __I uint32_t DCOIR_CONSTK_RSEL5; /*!< DCO IR mode: DCO Constant (K) for DCORSEL 5 */ 1247 __I uint32_t DCOER_FCAL_RSEL04; /*!< DCO ER mode: Frequency calibration for DCORSEL 0 to 4 */ 1248 __I uint32_t DCOER_FCAL_RSEL5; /*!< DCO ER mode: Frequency calibration for DCORSEL 5 */ 1249 __I uint32_t RESERVED7; /*!< Reserved */ 1250 __I uint32_t RESERVED8; /*!< Reserved */ 1251 __I uint32_t RESERVED9; /*!< Reserved */ 1252 __I uint32_t RESERVED10; /*!< Reserved */ 1253 __I uint32_t DCOER_CONSTK_RSEL04; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 0 to 4 */ 1254 __I uint32_t DCOER_CONSTK_RSEL5; /*!< DCO ER mode: DCO Constant (K) for DCORSEL 5 */ 1255 __I uint32_t ADC14_CAL_TAG; /*!< ADC14 Calibration Tag */ 1256 __I uint32_t ADC14_CAL_LEN; /*!< ADC14 Calibration Length */ 1257 __I uint32_t ADC_GAIN_FACTOR; /*!< ADC Gain Factor */ 1258 __I uint32_t ADC_OFFSET; /*!< ADC Offset */ 1259 __I uint32_t RESERVED11; /*!< Reserved */ 1260 __I uint32_t RESERVED12; /*!< Reserved */ 1261 __I uint32_t RESERVED13; /*!< Reserved */ 1262 __I uint32_t RESERVED14; /*!< Reserved */ 1263 __I uint32_t RESERVED15; /*!< Reserved */ 1264 __I uint32_t RESERVED16; /*!< Reserved */ 1265 __I uint32_t RESERVED17; /*!< Reserved */ 1266 __I uint32_t RESERVED18; /*!< Reserved */ 1267 __I uint32_t RESERVED19; /*!< Reserved */ 1268 __I uint32_t RESERVED20; /*!< Reserved */ 1269 __I uint32_t RESERVED21; /*!< Reserved */ 1270 __I uint32_t RESERVED22; /*!< Reserved */ 1271 __I uint32_t RESERVED23; /*!< Reserved */ 1272 __I uint32_t RESERVED24; /*!< Reserved */ 1273 __I uint32_t RESERVED25; /*!< Reserved */ 1274 __I uint32_t RESERVED26; /*!< Reserved */ 1275 __I uint32_t ADC14_REF1P2V_TS30C; /*!< ADC14 1.2V Reference Temp. Sensor 30C */ 1276 __I uint32_t ADC14_REF1P2V_TS85C; /*!< ADC14 1.2V Reference Temp. Sensor 85C */ 1277 __I uint32_t ADC14_REF1P45V_TS30C; /*!< ADC14 1.45V Reference Temp. Sensor 30C */ 1278 __I uint32_t ADC14_REF1P45V_TS85C; /*!< ADC14 1.45V Reference Temp. Sensor 85C */ 1279 __I uint32_t ADC14_REF2P5V_TS30C; /*!< ADC14 2.5V Reference Temp. Sensor 30C */ 1280 __I uint32_t ADC14_REF2P5V_TS85C; /*!< ADC14 2.5V Reference Temp. Sensor 85C */ 1281 __I uint32_t REF_CAL_TAG; /*!< REF Calibration Tag */ 1282 __I uint32_t REF_CAL_LEN; /*!< REF Calibration Length */ 1283 __I uint32_t REF_1P2V; /*!< REF 1.2V Reference */ 1284 __I uint32_t REF_1P45V; /*!< REF 1.45V Reference */ 1285 __I uint32_t REF_2P5V; /*!< REF 2.5V Reference */ 1286 __I uint32_t FLASH_INFO_TAG; /*!< Flash Info Tag */ 1287 __I uint32_t FLASH_INFO_LEN; /*!< Flash Info Length */ 1288 __I uint32_t FLASH_MAX_PROG_PULSES; /*!< Flash Maximum Programming Pulses */ 1289 __I uint32_t FLASH_MAX_ERASE_PULSES; /*!< Flash Maximum Erase Pulses */ 1290 __I uint32_t RANDOM_NUM_TAG; /*!< 128-bit Random Number Tag */ 1291 __I uint32_t RANDOM_NUM_LEN; /*!< 128-bit Random Number Length */ 1292 __I uint32_t RANDOM_NUM_1; /*!< 32-bit Random Number 1 */ 1293 __I uint32_t RANDOM_NUM_2; /*!< 32-bit Random Number 2 */ 1294 __I uint32_t RANDOM_NUM_3; /*!< 32-bit Random Number 3 */ 1295 __I uint32_t RANDOM_NUM_4; /*!< 32-bit Random Number 4 */ 1296 __I uint32_t BSL_CFG_TAG; /*!< BSL Configuration Tag */ 1297 __I uint32_t BSL_CFG_LEN; /*!< BSL Configuration Length */ 1298 __I uint32_t BSL_PERIPHIF_SEL; /*!< BSL Peripheral Interface Selection */ 1299 __I uint32_t BSL_PORTIF_CFG_UART; /*!< BSL Port Interface Configuration for UART */ 1300 __I uint32_t BSL_PORTIF_CFG_SPI; /*!< BSL Port Interface Configuration for SPI */ 1301 __I uint32_t BSL_PORTIF_CFG_I2C; /*!< BSL Port Interface Configuration for I2C */ 1302 __I uint32_t TLV_END; /*!< TLV End Word */ 1303 } TLV_Type; 1304 1305 /*@}*/ /* end of group TLV */ 1306 1307 1308 /****************************************************************************** 1309 * WDT_A Registers 1310 ******************************************************************************/ 1311 /** @addtogroup WDT_A MSP432P401R (WDT_A) 1312 @{ 1313 */ 1314 typedef struct { 1315 uint16_t RESERVED0[6]; 1316 __IO uint16_t CTL; /*!< Watchdog Timer Control Register */ 1317 } WDT_A_Type; 1318 1319 /*@}*/ /* end of group WDT_A */ 1320 1321 1322 /* -------------------- End of section using anonymous unions ------------------- */ 1323 #if defined(__CC_ARM) 1324 #pragma pop 1325 #elif defined(__ICCARM__) 1326 /* leave anonymous unions enabled */ 1327 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 1328 #pragma clang diagnostic pop 1329 #elif defined(__GNUC__) 1330 /* anonymous unions are enabled by default */ 1331 #elif defined(__TI_ARM__) 1332 /* anonymous unions are enabled by default */ 1333 #else 1334 #warning Not supported compiler type 1335 #endif 1336 1337 /*@}*/ /* end of group MSP432P401R_Peripherals */ 1338 1339 /****************************************************************************** 1340 * Peripheral declaration * 1341 ******************************************************************************/ 1342 /** @addtogroup MSP432P401R_PeripheralDecl MSP432P401R Peripheral Declaration 1343 @{ 1344 */ 1345 1346 #define ADC14 ((ADC14_Type *) ADC14_BASE) 1347 #define AES256 ((AES256_Type *) AES256_BASE) 1348 #define CAPTIO0 ((CAPTIO_Type *) CAPTIO0_BASE) 1349 #define CAPTIO1 ((CAPTIO_Type *) CAPTIO1_BASE) 1350 #define COMP_E0 ((COMP_E_Type *) COMP_E0_BASE) 1351 #define COMP_E1 ((COMP_E_Type *) COMP_E1_BASE) 1352 #define CRC32 ((CRC32_Type *) CRC32_BASE) 1353 #define CS ((CS_Type *) CS_BASE) 1354 #define PA ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0000)) 1355 #define PB ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0020)) 1356 #define PC ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0040)) 1357 #define PD ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0060)) 1358 #define PE ((DIO_PORT_Interruptable_Type*) (DIO_BASE + 0x0080)) 1359 #define PJ ((DIO_PORT_Not_Interruptable_Type*) (DIO_BASE + 0x0120)) 1360 #define P1 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0000)) 1361 #define P2 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0000)) 1362 #define P3 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0020)) 1363 #define P4 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0020)) 1364 #define P5 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0040)) 1365 #define P6 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0040)) 1366 #define P7 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0060)) 1367 #define P8 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0060)) 1368 #define P9 ((DIO_PORT_Odd_Interruptable_Type*) (DIO_BASE + 0x0080)) 1369 #define P10 ((DIO_PORT_Even_Interruptable_Type*) (DIO_BASE + 0x0080)) 1370 #define DMA_Channel ((DMA_Channel_Type *) DMA_BASE) 1371 #define DMA_Control ((DMA_Control_Type *) (DMA_BASE + 0x1000)) 1372 #define EUSCI_A0 ((EUSCI_A_Type *) EUSCI_A0_BASE) 1373 #define EUSCI_A0_SPI ((EUSCI_A_SPI_Type *) EUSCI_A0_SPI_BASE) 1374 #define EUSCI_A1 ((EUSCI_A_Type *) EUSCI_A1_BASE) 1375 #define EUSCI_A1_SPI ((EUSCI_A_SPI_Type *) EUSCI_A1_SPI_BASE) 1376 #define EUSCI_A2 ((EUSCI_A_Type *) EUSCI_A2_BASE) 1377 #define EUSCI_A2_SPI ((EUSCI_A_SPI_Type *) EUSCI_A2_SPI_BASE) 1378 #define EUSCI_A3 ((EUSCI_A_Type *) EUSCI_A3_BASE) 1379 #define EUSCI_A3_SPI ((EUSCI_A_SPI_Type *) EUSCI_A3_SPI_BASE) 1380 #define EUSCI_B0 ((EUSCI_B_Type *) EUSCI_B0_BASE) 1381 #define EUSCI_B0_SPI ((EUSCI_B_SPI_Type *) EUSCI_B0_SPI_BASE) 1382 #define EUSCI_B1 ((EUSCI_B_Type *) EUSCI_B1_BASE) 1383 #define EUSCI_B1_SPI ((EUSCI_B_SPI_Type *) EUSCI_B1_SPI_BASE) 1384 #define EUSCI_B2 ((EUSCI_B_Type *) EUSCI_B2_BASE) 1385 #define EUSCI_B2_SPI ((EUSCI_B_SPI_Type *) EUSCI_B2_SPI_BASE) 1386 #define EUSCI_B3 ((EUSCI_B_Type *) EUSCI_B3_BASE) 1387 #define EUSCI_B3_SPI ((EUSCI_B_SPI_Type *) EUSCI_B3_SPI_BASE) 1388 #define FLCTL ((FLCTL_Type *) FLCTL_BASE) 1389 #define FL_BOOTOVER_MAILBOX ((FL_BOOTOVER_MAILBOX_Type *) FL_BOOTOVER_MAILBOX_BASE) 1390 #define PCM ((PCM_Type *) PCM_BASE) 1391 #define PMAP ((PMAP_COMMON_Type*) PMAP_BASE) 1392 #define P1MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0008)) 1393 #define P2MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0010)) 1394 #define P3MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0018)) 1395 #define P4MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0020)) 1396 #define P5MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0028)) 1397 #define P6MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0030)) 1398 #define P7MAP ((PMAP_REGISTER_Type*) (PMAP_BASE + 0x0038)) 1399 #define PSS ((PSS_Type *) PSS_BASE) 1400 #define REF_A ((REF_A_Type *) REF_A_BASE) 1401 #define RSTCTL ((RSTCTL_Type *) RSTCTL_BASE) 1402 #define RTC_C ((RTC_C_Type *) RTC_C_BASE) 1403 #define RTC_C_BCD ((RTC_C_BCD_Type *) RTC_C_BCD_BASE) 1404 #define SYSCTL ((SYSCTL_Type *) SYSCTL_BASE) 1405 #define SYSCTL_Boot ((SYSCTL_Boot_Type *) (SYSCTL_BASE + 0x1000)) 1406 #define TIMER32_1 ((Timer32_Type *) TIMER32_BASE) 1407 #define TIMER32_2 ((Timer32_Type *) (TIMER32_BASE + 0x00020)) 1408 #define TIMER_A0 ((Timer_A_Type *) TIMER_A0_BASE) 1409 #define TIMER_A1 ((Timer_A_Type *) TIMER_A1_BASE) 1410 #define TIMER_A2 ((Timer_A_Type *) TIMER_A2_BASE) 1411 #define TIMER_A3 ((Timer_A_Type *) TIMER_A3_BASE) 1412 #define TLV ((TLV_Type *) TLV_BASE) 1413 #define WDT_A ((WDT_A_Type *) WDT_A_BASE) 1414 1415 1416 /*@}*/ /* end of group MSP432P401R_PeripheralDecl */ 1417 1418 /*@}*/ /* end of group MSP432P401R_Definitions */ 1419 1420 #endif /* __CMSIS_CONFIG__ */ 1421 1422 /****************************************************************************** 1423 * Peripheral register control bits * 1424 ******************************************************************************/ 1425 1426 /****************************************************************************** 1427 * ADC14 Bits 1428 ******************************************************************************/ 1429 /* ADC14_CTL0[SC] Bits */ 1430 #define ADC14_CTL0_SC_OFS ( 0) /*!< ADC14SC Bit Offset */ 1431 #define ADC14_CTL0_SC ((uint32_t)0x00000001) /*!< ADC14 start conversion */ 1432 /* ADC14_CTL0[ENC] Bits */ 1433 #define ADC14_CTL0_ENC_OFS ( 1) /*!< ADC14ENC Bit Offset */ 1434 #define ADC14_CTL0_ENC ((uint32_t)0x00000002) /*!< ADC14 enable conversion */ 1435 /* ADC14_CTL0[ON] Bits */ 1436 #define ADC14_CTL0_ON_OFS ( 4) /*!< ADC14ON Bit Offset */ 1437 #define ADC14_CTL0_ON ((uint32_t)0x00000010) /*!< ADC14 on */ 1438 /* ADC14_CTL0[MSC] Bits */ 1439 #define ADC14_CTL0_MSC_OFS ( 7) /*!< ADC14MSC Bit Offset */ 1440 #define ADC14_CTL0_MSC ((uint32_t)0x00000080) /*!< ADC14 multiple sample and conversion */ 1441 /* ADC14_CTL0[SHT0] Bits */ 1442 #define ADC14_CTL0_SHT0_OFS ( 8) /*!< ADC14SHT0 Bit Offset */ 1443 #define ADC14_CTL0_SHT0_MASK ((uint32_t)0x00000F00) /*!< ADC14SHT0 Bit Mask */ 1444 #define ADC14_CTL0_SHT00 ((uint32_t)0x00000100) /*!< SHT0 Bit 0 */ 1445 #define ADC14_CTL0_SHT01 ((uint32_t)0x00000200) /*!< SHT0 Bit 1 */ 1446 #define ADC14_CTL0_SHT02 ((uint32_t)0x00000400) /*!< SHT0 Bit 2 */ 1447 #define ADC14_CTL0_SHT03 ((uint32_t)0x00000800) /*!< SHT0 Bit 3 */ 1448 #define ADC14_CTL0_SHT0_0 ((uint32_t)0x00000000) /*!< 4 */ 1449 #define ADC14_CTL0_SHT0_1 ((uint32_t)0x00000100) /*!< 8 */ 1450 #define ADC14_CTL0_SHT0_2 ((uint32_t)0x00000200) /*!< 16 */ 1451 #define ADC14_CTL0_SHT0_3 ((uint32_t)0x00000300) /*!< 32 */ 1452 #define ADC14_CTL0_SHT0_4 ((uint32_t)0x00000400) /*!< 64 */ 1453 #define ADC14_CTL0_SHT0_5 ((uint32_t)0x00000500) /*!< 96 */ 1454 #define ADC14_CTL0_SHT0_6 ((uint32_t)0x00000600) /*!< 128 */ 1455 #define ADC14_CTL0_SHT0_7 ((uint32_t)0x00000700) /*!< 192 */ 1456 #define ADC14_CTL0_SHT0__4 ((uint32_t)0x00000000) /*!< 4 */ 1457 #define ADC14_CTL0_SHT0__8 ((uint32_t)0x00000100) /*!< 8 */ 1458 #define ADC14_CTL0_SHT0__16 ((uint32_t)0x00000200) /*!< 16 */ 1459 #define ADC14_CTL0_SHT0__32 ((uint32_t)0x00000300) /*!< 32 */ 1460 #define ADC14_CTL0_SHT0__64 ((uint32_t)0x00000400) /*!< 64 */ 1461 #define ADC14_CTL0_SHT0__96 ((uint32_t)0x00000500) /*!< 96 */ 1462 #define ADC14_CTL0_SHT0__128 ((uint32_t)0x00000600) /*!< 128 */ 1463 #define ADC14_CTL0_SHT0__192 ((uint32_t)0x00000700) /*!< 192 */ 1464 /* ADC14_CTL0[SHT1] Bits */ 1465 #define ADC14_CTL0_SHT1_OFS (12) /*!< ADC14SHT1 Bit Offset */ 1466 #define ADC14_CTL0_SHT1_MASK ((uint32_t)0x0000F000) /*!< ADC14SHT1 Bit Mask */ 1467 #define ADC14_CTL0_SHT10 ((uint32_t)0x00001000) /*!< SHT1 Bit 0 */ 1468 #define ADC14_CTL0_SHT11 ((uint32_t)0x00002000) /*!< SHT1 Bit 1 */ 1469 #define ADC14_CTL0_SHT12 ((uint32_t)0x00004000) /*!< SHT1 Bit 2 */ 1470 #define ADC14_CTL0_SHT13 ((uint32_t)0x00008000) /*!< SHT1 Bit 3 */ 1471 #define ADC14_CTL0_SHT1_0 ((uint32_t)0x00000000) /*!< 4 */ 1472 #define ADC14_CTL0_SHT1_1 ((uint32_t)0x00001000) /*!< 8 */ 1473 #define ADC14_CTL0_SHT1_2 ((uint32_t)0x00002000) /*!< 16 */ 1474 #define ADC14_CTL0_SHT1_3 ((uint32_t)0x00003000) /*!< 32 */ 1475 #define ADC14_CTL0_SHT1_4 ((uint32_t)0x00004000) /*!< 64 */ 1476 #define ADC14_CTL0_SHT1_5 ((uint32_t)0x00005000) /*!< 96 */ 1477 #define ADC14_CTL0_SHT1_6 ((uint32_t)0x00006000) /*!< 128 */ 1478 #define ADC14_CTL0_SHT1_7 ((uint32_t)0x00007000) /*!< 192 */ 1479 #define ADC14_CTL0_SHT1__4 ((uint32_t)0x00000000) /*!< 4 */ 1480 #define ADC14_CTL0_SHT1__8 ((uint32_t)0x00001000) /*!< 8 */ 1481 #define ADC14_CTL0_SHT1__16 ((uint32_t)0x00002000) /*!< 16 */ 1482 #define ADC14_CTL0_SHT1__32 ((uint32_t)0x00003000) /*!< 32 */ 1483 #define ADC14_CTL0_SHT1__64 ((uint32_t)0x00004000) /*!< 64 */ 1484 #define ADC14_CTL0_SHT1__96 ((uint32_t)0x00005000) /*!< 96 */ 1485 #define ADC14_CTL0_SHT1__128 ((uint32_t)0x00006000) /*!< 128 */ 1486 #define ADC14_CTL0_SHT1__192 ((uint32_t)0x00007000) /*!< 192 */ 1487 /* ADC14_CTL0[BUSY] Bits */ 1488 #define ADC14_CTL0_BUSY_OFS (16) /*!< ADC14BUSY Bit Offset */ 1489 #define ADC14_CTL0_BUSY ((uint32_t)0x00010000) /*!< ADC14 busy */ 1490 /* ADC14_CTL0[CONSEQ] Bits */ 1491 #define ADC14_CTL0_CONSEQ_OFS (17) /*!< ADC14CONSEQ Bit Offset */ 1492 #define ADC14_CTL0_CONSEQ_MASK ((uint32_t)0x00060000) /*!< ADC14CONSEQ Bit Mask */ 1493 #define ADC14_CTL0_CONSEQ0 ((uint32_t)0x00020000) /*!< CONSEQ Bit 0 */ 1494 #define ADC14_CTL0_CONSEQ1 ((uint32_t)0x00040000) /*!< CONSEQ Bit 1 */ 1495 #define ADC14_CTL0_CONSEQ_0 ((uint32_t)0x00000000) /*!< Single-channel, single-conversion */ 1496 #define ADC14_CTL0_CONSEQ_1 ((uint32_t)0x00020000) /*!< Sequence-of-channels */ 1497 #define ADC14_CTL0_CONSEQ_2 ((uint32_t)0x00040000) /*!< Repeat-single-channel */ 1498 #define ADC14_CTL0_CONSEQ_3 ((uint32_t)0x00060000) /*!< Repeat-sequence-of-channels */ 1499 /* ADC14_CTL0[SSEL] Bits */ 1500 #define ADC14_CTL0_SSEL_OFS (19) /*!< ADC14SSEL Bit Offset */ 1501 #define ADC14_CTL0_SSEL_MASK ((uint32_t)0x00380000) /*!< ADC14SSEL Bit Mask */ 1502 #define ADC14_CTL0_SSEL0 ((uint32_t)0x00080000) /*!< SSEL Bit 0 */ 1503 #define ADC14_CTL0_SSEL1 ((uint32_t)0x00100000) /*!< SSEL Bit 1 */ 1504 #define ADC14_CTL0_SSEL2 ((uint32_t)0x00200000) /*!< SSEL Bit 2 */ 1505 #define ADC14_CTL0_SSEL_0 ((uint32_t)0x00000000) /*!< MODCLK */ 1506 #define ADC14_CTL0_SSEL_1 ((uint32_t)0x00080000) /*!< SYSCLK */ 1507 #define ADC14_CTL0_SSEL_2 ((uint32_t)0x00100000) /*!< ACLK */ 1508 #define ADC14_CTL0_SSEL_3 ((uint32_t)0x00180000) /*!< MCLK */ 1509 #define ADC14_CTL0_SSEL_4 ((uint32_t)0x00200000) /*!< SMCLK */ 1510 #define ADC14_CTL0_SSEL_5 ((uint32_t)0x00280000) /*!< HSMCLK */ 1511 #define ADC14_CTL0_SSEL__MODCLK ((uint32_t)0x00000000) /*!< MODCLK */ 1512 #define ADC14_CTL0_SSEL__SYSCLK ((uint32_t)0x00080000) /*!< SYSCLK */ 1513 #define ADC14_CTL0_SSEL__ACLK ((uint32_t)0x00100000) /*!< ACLK */ 1514 #define ADC14_CTL0_SSEL__MCLK ((uint32_t)0x00180000) /*!< MCLK */ 1515 #define ADC14_CTL0_SSEL__SMCLK ((uint32_t)0x00200000) /*!< SMCLK */ 1516 #define ADC14_CTL0_SSEL__HSMCLK ((uint32_t)0x00280000) /*!< HSMCLK */ 1517 /* ADC14_CTL0[DIV] Bits */ 1518 #define ADC14_CTL0_DIV_OFS (22) /*!< ADC14DIV Bit Offset */ 1519 #define ADC14_CTL0_DIV_MASK ((uint32_t)0x01C00000) /*!< ADC14DIV Bit Mask */ 1520 #define ADC14_CTL0_DIV0 ((uint32_t)0x00400000) /*!< DIV Bit 0 */ 1521 #define ADC14_CTL0_DIV1 ((uint32_t)0x00800000) /*!< DIV Bit 1 */ 1522 #define ADC14_CTL0_DIV2 ((uint32_t)0x01000000) /*!< DIV Bit 2 */ 1523 #define ADC14_CTL0_DIV_0 ((uint32_t)0x00000000) /*!< /1 */ 1524 #define ADC14_CTL0_DIV_1 ((uint32_t)0x00400000) /*!< /2 */ 1525 #define ADC14_CTL0_DIV_2 ((uint32_t)0x00800000) /*!< /3 */ 1526 #define ADC14_CTL0_DIV_3 ((uint32_t)0x00C00000) /*!< /4 */ 1527 #define ADC14_CTL0_DIV_4 ((uint32_t)0x01000000) /*!< /5 */ 1528 #define ADC14_CTL0_DIV_5 ((uint32_t)0x01400000) /*!< /6 */ 1529 #define ADC14_CTL0_DIV_6 ((uint32_t)0x01800000) /*!< /7 */ 1530 #define ADC14_CTL0_DIV_7 ((uint32_t)0x01C00000) /*!< /8 */ 1531 #define ADC14_CTL0_DIV__1 ((uint32_t)0x00000000) /*!< /1 */ 1532 #define ADC14_CTL0_DIV__2 ((uint32_t)0x00400000) /*!< /2 */ 1533 #define ADC14_CTL0_DIV__3 ((uint32_t)0x00800000) /*!< /3 */ 1534 #define ADC14_CTL0_DIV__4 ((uint32_t)0x00C00000) /*!< /4 */ 1535 #define ADC14_CTL0_DIV__5 ((uint32_t)0x01000000) /*!< /5 */ 1536 #define ADC14_CTL0_DIV__6 ((uint32_t)0x01400000) /*!< /6 */ 1537 #define ADC14_CTL0_DIV__7 ((uint32_t)0x01800000) /*!< /7 */ 1538 #define ADC14_CTL0_DIV__8 ((uint32_t)0x01C00000) /*!< /8 */ 1539 /* ADC14_CTL0[ISSH] Bits */ 1540 #define ADC14_CTL0_ISSH_OFS (25) /*!< ADC14ISSH Bit Offset */ 1541 #define ADC14_CTL0_ISSH ((uint32_t)0x02000000) /*!< ADC14 invert signal sample-and-hold */ 1542 /* ADC14_CTL0[SHP] Bits */ 1543 #define ADC14_CTL0_SHP_OFS (26) /*!< ADC14SHP Bit Offset */ 1544 #define ADC14_CTL0_SHP ((uint32_t)0x04000000) /*!< ADC14 sample-and-hold pulse-mode select */ 1545 /* ADC14_CTL0[SHS] Bits */ 1546 #define ADC14_CTL0_SHS_OFS (27) /*!< ADC14SHS Bit Offset */ 1547 #define ADC14_CTL0_SHS_MASK ((uint32_t)0x38000000) /*!< ADC14SHS Bit Mask */ 1548 #define ADC14_CTL0_SHS0 ((uint32_t)0x08000000) /*!< SHS Bit 0 */ 1549 #define ADC14_CTL0_SHS1 ((uint32_t)0x10000000) /*!< SHS Bit 1 */ 1550 #define ADC14_CTL0_SHS2 ((uint32_t)0x20000000) /*!< SHS Bit 2 */ 1551 #define ADC14_CTL0_SHS_0 ((uint32_t)0x00000000) /*!< ADC14SC bit */ 1552 #define ADC14_CTL0_SHS_1 ((uint32_t)0x08000000) /*!< See device-specific data sheet for source */ 1553 #define ADC14_CTL0_SHS_2 ((uint32_t)0x10000000) /*!< See device-specific data sheet for source */ 1554 #define ADC14_CTL0_SHS_3 ((uint32_t)0x18000000) /*!< See device-specific data sheet for source */ 1555 #define ADC14_CTL0_SHS_4 ((uint32_t)0x20000000) /*!< See device-specific data sheet for source */ 1556 #define ADC14_CTL0_SHS_5 ((uint32_t)0x28000000) /*!< See device-specific data sheet for source */ 1557 #define ADC14_CTL0_SHS_6 ((uint32_t)0x30000000) /*!< See device-specific data sheet for source */ 1558 #define ADC14_CTL0_SHS_7 ((uint32_t)0x38000000) /*!< See device-specific data sheet for source */ 1559 /* ADC14_CTL0[PDIV] Bits */ 1560 #define ADC14_CTL0_PDIV_OFS (30) /*!< ADC14PDIV Bit Offset */ 1561 #define ADC14_CTL0_PDIV_MASK ((uint32_t)0xC0000000) /*!< ADC14PDIV Bit Mask */ 1562 #define ADC14_CTL0_PDIV0 ((uint32_t)0x40000000) /*!< PDIV Bit 0 */ 1563 #define ADC14_CTL0_PDIV1 ((uint32_t)0x80000000) /*!< PDIV Bit 1 */ 1564 #define ADC14_CTL0_PDIV_0 ((uint32_t)0x00000000) /*!< Predivide by 1 */ 1565 #define ADC14_CTL0_PDIV_1 ((uint32_t)0x40000000) /*!< Predivide by 4 */ 1566 #define ADC14_CTL0_PDIV_2 ((uint32_t)0x80000000) /*!< Predivide by 32 */ 1567 #define ADC14_CTL0_PDIV_3 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ 1568 #define ADC14_CTL0_PDIV__1 ((uint32_t)0x00000000) /*!< Predivide by 1 */ 1569 #define ADC14_CTL0_PDIV__4 ((uint32_t)0x40000000) /*!< Predivide by 4 */ 1570 #define ADC14_CTL0_PDIV__32 ((uint32_t)0x80000000) /*!< Predivide by 32 */ 1571 #define ADC14_CTL0_PDIV__64 ((uint32_t)0xC0000000) /*!< Predivide by 64 */ 1572 /* ADC14_CTL1[PWRMD] Bits */ 1573 #define ADC14_CTL1_PWRMD_OFS ( 0) /*!< ADC14PWRMD Bit Offset */ 1574 #define ADC14_CTL1_PWRMD_MASK ((uint32_t)0x00000003) /*!< ADC14PWRMD Bit Mask */ 1575 #define ADC14_CTL1_PWRMD0 ((uint32_t)0x00000001) /*!< PWRMD Bit 0 */ 1576 #define ADC14_CTL1_PWRMD1 ((uint32_t)0x00000002) /*!< PWRMD Bit 1 */ 1577 #define ADC14_CTL1_PWRMD_0 ((uint32_t)0x00000000) /*!< Regular power mode for use with any resolution setting. Sample rate can be */ 1578 /* up to 1 Msps. */ 1579 #define ADC14_CTL1_PWRMD_2 ((uint32_t)0x00000002) /*!< Low-power mode for 12-bit, 10-bit, and 8-bit resolution settings. Sample */ 1580 /* rate must not exceed 200 ksps. */ 1581 /* ADC14_CTL1[REFBURST] Bits */ 1582 #define ADC14_CTL1_REFBURST_OFS ( 2) /*!< ADC14REFBURST Bit Offset */ 1583 #define ADC14_CTL1_REFBURST ((uint32_t)0x00000004) /*!< ADC14 reference buffer burst */ 1584 /* ADC14_CTL1[DF] Bits */ 1585 #define ADC14_CTL1_DF_OFS ( 3) /*!< ADC14DF Bit Offset */ 1586 #define ADC14_CTL1_DF ((uint32_t)0x00000008) /*!< ADC14 data read-back format */ 1587 /* ADC14_CTL1[RES] Bits */ 1588 #define ADC14_CTL1_RES_OFS ( 4) /*!< ADC14RES Bit Offset */ 1589 #define ADC14_CTL1_RES_MASK ((uint32_t)0x00000030) /*!< ADC14RES Bit Mask */ 1590 #define ADC14_CTL1_RES0 ((uint32_t)0x00000010) /*!< RES Bit 0 */ 1591 #define ADC14_CTL1_RES1 ((uint32_t)0x00000020) /*!< RES Bit 1 */ 1592 #define ADC14_CTL1_RES_0 ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ 1593 #define ADC14_CTL1_RES_1 ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ 1594 #define ADC14_CTL1_RES_2 ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ 1595 #define ADC14_CTL1_RES_3 ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ 1596 #define ADC14_CTL1_RES__8BIT ((uint32_t)0x00000000) /*!< 8 bit (9 clock cycle conversion time) */ 1597 #define ADC14_CTL1_RES__10BIT ((uint32_t)0x00000010) /*!< 10 bit (11 clock cycle conversion time) */ 1598 #define ADC14_CTL1_RES__12BIT ((uint32_t)0x00000020) /*!< 12 bit (14 clock cycle conversion time) */ 1599 #define ADC14_CTL1_RES__14BIT ((uint32_t)0x00000030) /*!< 14 bit (16 clock cycle conversion time) */ 1600 /* ADC14_CTL1[CSTARTADD] Bits */ 1601 #define ADC14_CTL1_CSTARTADD_OFS (16) /*!< ADC14CSTARTADD Bit Offset */ 1602 #define ADC14_CTL1_CSTARTADD_MASK ((uint32_t)0x001F0000) /*!< ADC14CSTARTADD Bit Mask */ 1603 /* ADC14_CTL1[BATMAP] Bits */ 1604 #define ADC14_CTL1_BATMAP_OFS (22) /*!< ADC14BATMAP Bit Offset */ 1605 #define ADC14_CTL1_BATMAP ((uint32_t)0x00400000) /*!< Controls 1/2 AVCC ADC input channel selection */ 1606 /* ADC14_CTL1[TCMAP] Bits */ 1607 #define ADC14_CTL1_TCMAP_OFS (23) /*!< ADC14TCMAP Bit Offset */ 1608 #define ADC14_CTL1_TCMAP ((uint32_t)0x00800000) /*!< Controls temperature sensor ADC input channel selection */ 1609 /* ADC14_CTL1[CH0MAP] Bits */ 1610 #define ADC14_CTL1_CH0MAP_OFS (24) /*!< ADC14CH0MAP Bit Offset */ 1611 #define ADC14_CTL1_CH0MAP ((uint32_t)0x01000000) /*!< Controls internal channel 0 selection to ADC input channel MAX-2 */ 1612 /* ADC14_CTL1[CH1MAP] Bits */ 1613 #define ADC14_CTL1_CH1MAP_OFS (25) /*!< ADC14CH1MAP Bit Offset */ 1614 #define ADC14_CTL1_CH1MAP ((uint32_t)0x02000000) /*!< Controls internal channel 1 selection to ADC input channel MAX-3 */ 1615 /* ADC14_CTL1[CH2MAP] Bits */ 1616 #define ADC14_CTL1_CH2MAP_OFS (26) /*!< ADC14CH2MAP Bit Offset */ 1617 #define ADC14_CTL1_CH2MAP ((uint32_t)0x04000000) /*!< Controls internal channel 2 selection to ADC input channel MAX-4 */ 1618 /* ADC14_CTL1[CH3MAP] Bits */ 1619 #define ADC14_CTL1_CH3MAP_OFS (27) /*!< ADC14CH3MAP Bit Offset */ 1620 #define ADC14_CTL1_CH3MAP ((uint32_t)0x08000000) /*!< Controls internal channel 3 selection to ADC input channel MAX-5 */ 1621 /* ADC14_LO0[LO0] Bits */ 1622 #define ADC14_LO0_LO0_OFS ( 0) /*!< ADC14LO0 Bit Offset */ 1623 #define ADC14_LO0_LO0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO0 Bit Mask */ 1624 /* ADC14_HI0[HI0] Bits */ 1625 #define ADC14_HI0_HI0_OFS ( 0) /*!< ADC14HI0 Bit Offset */ 1626 #define ADC14_HI0_HI0_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI0 Bit Mask */ 1627 /* ADC14_LO1[LO1] Bits */ 1628 #define ADC14_LO1_LO1_OFS ( 0) /*!< ADC14LO1 Bit Offset */ 1629 #define ADC14_LO1_LO1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14LO1 Bit Mask */ 1630 /* ADC14_HI1[HI1] Bits */ 1631 #define ADC14_HI1_HI1_OFS ( 0) /*!< ADC14HI1 Bit Offset */ 1632 #define ADC14_HI1_HI1_MASK ((uint32_t)0x0000FFFF) /*!< ADC14HI1 Bit Mask */ 1633 /* ADC14_MCTLN[INCH] Bits */ 1634 #define ADC14_MCTLN_INCH_OFS ( 0) /*!< ADC14INCH Bit Offset */ 1635 #define ADC14_MCTLN_INCH_MASK ((uint32_t)0x0000001F) /*!< ADC14INCH Bit Mask */ 1636 #define ADC14_MCTLN_INCH0 ((uint32_t)0x00000001) /*!< INCH Bit 0 */ 1637 #define ADC14_MCTLN_INCH1 ((uint32_t)0x00000002) /*!< INCH Bit 1 */ 1638 #define ADC14_MCTLN_INCH2 ((uint32_t)0x00000004) /*!< INCH Bit 2 */ 1639 #define ADC14_MCTLN_INCH3 ((uint32_t)0x00000008) /*!< INCH Bit 3 */ 1640 #define ADC14_MCTLN_INCH4 ((uint32_t)0x00000010) /*!< INCH Bit 4 */ 1641 #define ADC14_MCTLN_INCH_0 ((uint32_t)0x00000000) /*!< If ADC14DIF = 0: A0; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ 1642 #define ADC14_MCTLN_INCH_1 ((uint32_t)0x00000001) /*!< If ADC14DIF = 0: A1; If ADC14DIF = 1: Ain+ = A0, Ain- = A1 */ 1643 #define ADC14_MCTLN_INCH_2 ((uint32_t)0x00000002) /*!< If ADC14DIF = 0: A2; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ 1644 #define ADC14_MCTLN_INCH_3 ((uint32_t)0x00000003) /*!< If ADC14DIF = 0: A3; If ADC14DIF = 1: Ain+ = A2, Ain- = A3 */ 1645 #define ADC14_MCTLN_INCH_4 ((uint32_t)0x00000004) /*!< If ADC14DIF = 0: A4; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ 1646 #define ADC14_MCTLN_INCH_5 ((uint32_t)0x00000005) /*!< If ADC14DIF = 0: A5; If ADC14DIF = 1: Ain+ = A4, Ain- = A5 */ 1647 #define ADC14_MCTLN_INCH_6 ((uint32_t)0x00000006) /*!< If ADC14DIF = 0: A6; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ 1648 #define ADC14_MCTLN_INCH_7 ((uint32_t)0x00000007) /*!< If ADC14DIF = 0: A7; If ADC14DIF = 1: Ain+ = A6, Ain- = A7 */ 1649 #define ADC14_MCTLN_INCH_8 ((uint32_t)0x00000008) /*!< If ADC14DIF = 0: A8; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ 1650 #define ADC14_MCTLN_INCH_9 ((uint32_t)0x00000009) /*!< If ADC14DIF = 0: A9; If ADC14DIF = 1: Ain+ = A8, Ain- = A9 */ 1651 #define ADC14_MCTLN_INCH_10 ((uint32_t)0x0000000A) /*!< If ADC14DIF = 0: A10; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ 1652 #define ADC14_MCTLN_INCH_11 ((uint32_t)0x0000000B) /*!< If ADC14DIF = 0: A11; If ADC14DIF = 1: Ain+ = A10, Ain- = A11 */ 1653 #define ADC14_MCTLN_INCH_12 ((uint32_t)0x0000000C) /*!< If ADC14DIF = 0: A12; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ 1654 #define ADC14_MCTLN_INCH_13 ((uint32_t)0x0000000D) /*!< If ADC14DIF = 0: A13; If ADC14DIF = 1: Ain+ = A12, Ain- = A13 */ 1655 #define ADC14_MCTLN_INCH_14 ((uint32_t)0x0000000E) /*!< If ADC14DIF = 0: A14; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ 1656 #define ADC14_MCTLN_INCH_15 ((uint32_t)0x0000000F) /*!< If ADC14DIF = 0: A15; If ADC14DIF = 1: Ain+ = A14, Ain- = A15 */ 1657 #define ADC14_MCTLN_INCH_16 ((uint32_t)0x00000010) /*!< If ADC14DIF = 0: A16; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ 1658 #define ADC14_MCTLN_INCH_17 ((uint32_t)0x00000011) /*!< If ADC14DIF = 0: A17; If ADC14DIF = 1: Ain+ = A16, Ain- = A17 */ 1659 #define ADC14_MCTLN_INCH_18 ((uint32_t)0x00000012) /*!< If ADC14DIF = 0: A18; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ 1660 #define ADC14_MCTLN_INCH_19 ((uint32_t)0x00000013) /*!< If ADC14DIF = 0: A19; If ADC14DIF = 1: Ain+ = A18, Ain- = A19 */ 1661 #define ADC14_MCTLN_INCH_20 ((uint32_t)0x00000014) /*!< If ADC14DIF = 0: A20; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ 1662 #define ADC14_MCTLN_INCH_21 ((uint32_t)0x00000015) /*!< If ADC14DIF = 0: A21; If ADC14DIF = 1: Ain+ = A20, Ain- = A21 */ 1663 #define ADC14_MCTLN_INCH_22 ((uint32_t)0x00000016) /*!< If ADC14DIF = 0: A22; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ 1664 #define ADC14_MCTLN_INCH_23 ((uint32_t)0x00000017) /*!< If ADC14DIF = 0: A23; If ADC14DIF = 1: Ain+ = A22, Ain- = A23 */ 1665 #define ADC14_MCTLN_INCH_24 ((uint32_t)0x00000018) /*!< If ADC14DIF = 0: A24; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ 1666 #define ADC14_MCTLN_INCH_25 ((uint32_t)0x00000019) /*!< If ADC14DIF = 0: A25; If ADC14DIF = 1: Ain+ = A24, Ain- = A25 */ 1667 #define ADC14_MCTLN_INCH_26 ((uint32_t)0x0000001A) /*!< If ADC14DIF = 0: A26; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ 1668 #define ADC14_MCTLN_INCH_27 ((uint32_t)0x0000001B) /*!< If ADC14DIF = 0: A27; If ADC14DIF = 1: Ain+ = A26, Ain- = A27 */ 1669 #define ADC14_MCTLN_INCH_28 ((uint32_t)0x0000001C) /*!< If ADC14DIF = 0: A28; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ 1670 #define ADC14_MCTLN_INCH_29 ((uint32_t)0x0000001D) /*!< If ADC14DIF = 0: A29; If ADC14DIF = 1: Ain+ = A28, Ain- = A29 */ 1671 #define ADC14_MCTLN_INCH_30 ((uint32_t)0x0000001E) /*!< If ADC14DIF = 0: A30; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ 1672 #define ADC14_MCTLN_INCH_31 ((uint32_t)0x0000001F) /*!< If ADC14DIF = 0: A31; If ADC14DIF = 1: Ain+ = A30, Ain- = A31 */ 1673 /* ADC14_MCTLN[EOS] Bits */ 1674 #define ADC14_MCTLN_EOS_OFS ( 7) /*!< ADC14EOS Bit Offset */ 1675 #define ADC14_MCTLN_EOS ((uint32_t)0x00000080) /*!< End of sequence */ 1676 /* ADC14_MCTLN[VRSEL] Bits */ 1677 #define ADC14_MCTLN_VRSEL_OFS ( 8) /*!< ADC14VRSEL Bit Offset */ 1678 #define ADC14_MCTLN_VRSEL_MASK ((uint32_t)0x00000F00) /*!< ADC14VRSEL Bit Mask */ 1679 #define ADC14_MCTLN_VRSEL0 ((uint32_t)0x00000100) /*!< VRSEL Bit 0 */ 1680 #define ADC14_MCTLN_VRSEL1 ((uint32_t)0x00000200) /*!< VRSEL Bit 1 */ 1681 #define ADC14_MCTLN_VRSEL2 ((uint32_t)0x00000400) /*!< VRSEL Bit 2 */ 1682 #define ADC14_MCTLN_VRSEL3 ((uint32_t)0x00000800) /*!< VRSEL Bit 3 */ 1683 #define ADC14_MCTLN_VRSEL_0 ((uint32_t)0x00000000) /*!< V(R+) = AVCC, V(R-) = AVSS */ 1684 #define ADC14_MCTLN_VRSEL_1 ((uint32_t)0x00000100) /*!< V(R+) = VREF buffered, V(R-) = AVSS */ 1685 #define ADC14_MCTLN_VRSEL_14 ((uint32_t)0x00000E00) /*!< V(R+) = VeREF+, V(R-) = VeREF- */ 1686 #define ADC14_MCTLN_VRSEL_15 ((uint32_t)0x00000F00) /*!< V(R+) = VeREF+ buffered, V(R-) = VeREF */ 1687 /* ADC14_MCTLN[DIF] Bits */ 1688 #define ADC14_MCTLN_DIF_OFS (13) /*!< ADC14DIF Bit Offset */ 1689 #define ADC14_MCTLN_DIF ((uint32_t)0x00002000) /*!< Differential mode */ 1690 /* ADC14_MCTLN[WINC] Bits */ 1691 #define ADC14_MCTLN_WINC_OFS (14) /*!< ADC14WINC Bit Offset */ 1692 #define ADC14_MCTLN_WINC ((uint32_t)0x00004000) /*!< Comparator window enable */ 1693 /* ADC14_MCTLN[WINCTH] Bits */ 1694 #define ADC14_MCTLN_WINCTH_OFS (15) /*!< ADC14WINCTH Bit Offset */ 1695 #define ADC14_MCTLN_WINCTH ((uint32_t)0x00008000) /*!< Window comparator threshold register selection */ 1696 /* ADC14_MEMN[CONVRES] Bits */ 1697 #define ADC14_MEMN_CONVRES_OFS ( 0) /*!< Conversion_Results Bit Offset */ 1698 #define ADC14_MEMN_CONVRES_MASK ((uint32_t)0x0000FFFF) /*!< Conversion_Results Bit Mask */ 1699 /* ADC14_IER0[IE0] Bits */ 1700 #define ADC14_IER0_IE0_OFS ( 0) /*!< ADC14IE0 Bit Offset */ 1701 #define ADC14_IER0_IE0 ((uint32_t)0x00000001) /*!< Interrupt enable */ 1702 /* ADC14_IER0[IE1] Bits */ 1703 #define ADC14_IER0_IE1_OFS ( 1) /*!< ADC14IE1 Bit Offset */ 1704 #define ADC14_IER0_IE1 ((uint32_t)0x00000002) /*!< Interrupt enable */ 1705 /* ADC14_IER0[IE2] Bits */ 1706 #define ADC14_IER0_IE2_OFS ( 2) /*!< ADC14IE2 Bit Offset */ 1707 #define ADC14_IER0_IE2 ((uint32_t)0x00000004) /*!< Interrupt enable */ 1708 /* ADC14_IER0[IE3] Bits */ 1709 #define ADC14_IER0_IE3_OFS ( 3) /*!< ADC14IE3 Bit Offset */ 1710 #define ADC14_IER0_IE3 ((uint32_t)0x00000008) /*!< Interrupt enable */ 1711 /* ADC14_IER0[IE4] Bits */ 1712 #define ADC14_IER0_IE4_OFS ( 4) /*!< ADC14IE4 Bit Offset */ 1713 #define ADC14_IER0_IE4 ((uint32_t)0x00000010) /*!< Interrupt enable */ 1714 /* ADC14_IER0[IE5] Bits */ 1715 #define ADC14_IER0_IE5_OFS ( 5) /*!< ADC14IE5 Bit Offset */ 1716 #define ADC14_IER0_IE5 ((uint32_t)0x00000020) /*!< Interrupt enable */ 1717 /* ADC14_IER0[IE6] Bits */ 1718 #define ADC14_IER0_IE6_OFS ( 6) /*!< ADC14IE6 Bit Offset */ 1719 #define ADC14_IER0_IE6 ((uint32_t)0x00000040) /*!< Interrupt enable */ 1720 /* ADC14_IER0[IE7] Bits */ 1721 #define ADC14_IER0_IE7_OFS ( 7) /*!< ADC14IE7 Bit Offset */ 1722 #define ADC14_IER0_IE7 ((uint32_t)0x00000080) /*!< Interrupt enable */ 1723 /* ADC14_IER0[IE8] Bits */ 1724 #define ADC14_IER0_IE8_OFS ( 8) /*!< ADC14IE8 Bit Offset */ 1725 #define ADC14_IER0_IE8 ((uint32_t)0x00000100) /*!< Interrupt enable */ 1726 /* ADC14_IER0[IE9] Bits */ 1727 #define ADC14_IER0_IE9_OFS ( 9) /*!< ADC14IE9 Bit Offset */ 1728 #define ADC14_IER0_IE9 ((uint32_t)0x00000200) /*!< Interrupt enable */ 1729 /* ADC14_IER0[IE10] Bits */ 1730 #define ADC14_IER0_IE10_OFS (10) /*!< ADC14IE10 Bit Offset */ 1731 #define ADC14_IER0_IE10 ((uint32_t)0x00000400) /*!< Interrupt enable */ 1732 /* ADC14_IER0[IE11] Bits */ 1733 #define ADC14_IER0_IE11_OFS (11) /*!< ADC14IE11 Bit Offset */ 1734 #define ADC14_IER0_IE11 ((uint32_t)0x00000800) /*!< Interrupt enable */ 1735 /* ADC14_IER0[IE12] Bits */ 1736 #define ADC14_IER0_IE12_OFS (12) /*!< ADC14IE12 Bit Offset */ 1737 #define ADC14_IER0_IE12 ((uint32_t)0x00001000) /*!< Interrupt enable */ 1738 /* ADC14_IER0[IE13] Bits */ 1739 #define ADC14_IER0_IE13_OFS (13) /*!< ADC14IE13 Bit Offset */ 1740 #define ADC14_IER0_IE13 ((uint32_t)0x00002000) /*!< Interrupt enable */ 1741 /* ADC14_IER0[IE14] Bits */ 1742 #define ADC14_IER0_IE14_OFS (14) /*!< ADC14IE14 Bit Offset */ 1743 #define ADC14_IER0_IE14 ((uint32_t)0x00004000) /*!< Interrupt enable */ 1744 /* ADC14_IER0[IE15] Bits */ 1745 #define ADC14_IER0_IE15_OFS (15) /*!< ADC14IE15 Bit Offset */ 1746 #define ADC14_IER0_IE15 ((uint32_t)0x00008000) /*!< Interrupt enable */ 1747 /* ADC14_IER0[IE16] Bits */ 1748 #define ADC14_IER0_IE16_OFS (16) /*!< ADC14IE16 Bit Offset */ 1749 #define ADC14_IER0_IE16 ((uint32_t)0x00010000) /*!< Interrupt enable */ 1750 /* ADC14_IER0[IE17] Bits */ 1751 #define ADC14_IER0_IE17_OFS (17) /*!< ADC14IE17 Bit Offset */ 1752 #define ADC14_IER0_IE17 ((uint32_t)0x00020000) /*!< Interrupt enable */ 1753 /* ADC14_IER0[IE19] Bits */ 1754 #define ADC14_IER0_IE19_OFS (19) /*!< ADC14IE19 Bit Offset */ 1755 #define ADC14_IER0_IE19 ((uint32_t)0x00080000) /*!< Interrupt enable */ 1756 /* ADC14_IER0[IE18] Bits */ 1757 #define ADC14_IER0_IE18_OFS (18) /*!< ADC14IE18 Bit Offset */ 1758 #define ADC14_IER0_IE18 ((uint32_t)0x00040000) /*!< Interrupt enable */ 1759 /* ADC14_IER0[IE20] Bits */ 1760 #define ADC14_IER0_IE20_OFS (20) /*!< ADC14IE20 Bit Offset */ 1761 #define ADC14_IER0_IE20 ((uint32_t)0x00100000) /*!< Interrupt enable */ 1762 /* ADC14_IER0[IE21] Bits */ 1763 #define ADC14_IER0_IE21_OFS (21) /*!< ADC14IE21 Bit Offset */ 1764 #define ADC14_IER0_IE21 ((uint32_t)0x00200000) /*!< Interrupt enable */ 1765 /* ADC14_IER0[IE22] Bits */ 1766 #define ADC14_IER0_IE22_OFS (22) /*!< ADC14IE22 Bit Offset */ 1767 #define ADC14_IER0_IE22 ((uint32_t)0x00400000) /*!< Interrupt enable */ 1768 /* ADC14_IER0[IE23] Bits */ 1769 #define ADC14_IER0_IE23_OFS (23) /*!< ADC14IE23 Bit Offset */ 1770 #define ADC14_IER0_IE23 ((uint32_t)0x00800000) /*!< Interrupt enable */ 1771 /* ADC14_IER0[IE24] Bits */ 1772 #define ADC14_IER0_IE24_OFS (24) /*!< ADC14IE24 Bit Offset */ 1773 #define ADC14_IER0_IE24 ((uint32_t)0x01000000) /*!< Interrupt enable */ 1774 /* ADC14_IER0[IE25] Bits */ 1775 #define ADC14_IER0_IE25_OFS (25) /*!< ADC14IE25 Bit Offset */ 1776 #define ADC14_IER0_IE25 ((uint32_t)0x02000000) /*!< Interrupt enable */ 1777 /* ADC14_IER0[IE26] Bits */ 1778 #define ADC14_IER0_IE26_OFS (26) /*!< ADC14IE26 Bit Offset */ 1779 #define ADC14_IER0_IE26 ((uint32_t)0x04000000) /*!< Interrupt enable */ 1780 /* ADC14_IER0[IE27] Bits */ 1781 #define ADC14_IER0_IE27_OFS (27) /*!< ADC14IE27 Bit Offset */ 1782 #define ADC14_IER0_IE27 ((uint32_t)0x08000000) /*!< Interrupt enable */ 1783 /* ADC14_IER0[IE28] Bits */ 1784 #define ADC14_IER0_IE28_OFS (28) /*!< ADC14IE28 Bit Offset */ 1785 #define ADC14_IER0_IE28 ((uint32_t)0x10000000) /*!< Interrupt enable */ 1786 /* ADC14_IER0[IE29] Bits */ 1787 #define ADC14_IER0_IE29_OFS (29) /*!< ADC14IE29 Bit Offset */ 1788 #define ADC14_IER0_IE29 ((uint32_t)0x20000000) /*!< Interrupt enable */ 1789 /* ADC14_IER0[IE30] Bits */ 1790 #define ADC14_IER0_IE30_OFS (30) /*!< ADC14IE30 Bit Offset */ 1791 #define ADC14_IER0_IE30 ((uint32_t)0x40000000) /*!< Interrupt enable */ 1792 /* ADC14_IER0[IE31] Bits */ 1793 #define ADC14_IER0_IE31_OFS (31) /*!< ADC14IE31 Bit Offset */ 1794 #define ADC14_IER0_IE31 ((uint32_t)0x80000000) /*!< Interrupt enable */ 1795 /* ADC14_IER1[INIE] Bits */ 1796 #define ADC14_IER1_INIE_OFS ( 1) /*!< ADC14INIE Bit Offset */ 1797 #define ADC14_IER1_INIE ((uint32_t)0x00000002) /*!< Interrupt enable for ADC14MEMx within comparator window */ 1798 /* ADC14_IER1[LOIE] Bits */ 1799 #define ADC14_IER1_LOIE_OFS ( 2) /*!< ADC14LOIE Bit Offset */ 1800 #define ADC14_IER1_LOIE ((uint32_t)0x00000004) /*!< Interrupt enable for ADC14MEMx below comparator window */ 1801 /* ADC14_IER1[HIIE] Bits */ 1802 #define ADC14_IER1_HIIE_OFS ( 3) /*!< ADC14HIIE Bit Offset */ 1803 #define ADC14_IER1_HIIE ((uint32_t)0x00000008) /*!< Interrupt enable for ADC14MEMx above comparator window */ 1804 /* ADC14_IER1[OVIE] Bits */ 1805 #define ADC14_IER1_OVIE_OFS ( 4) /*!< ADC14OVIE Bit Offset */ 1806 #define ADC14_IER1_OVIE ((uint32_t)0x00000010) /*!< ADC14MEMx overflow-interrupt enable */ 1807 /* ADC14_IER1[TOVIE] Bits */ 1808 #define ADC14_IER1_TOVIE_OFS ( 5) /*!< ADC14TOVIE Bit Offset */ 1809 #define ADC14_IER1_TOVIE ((uint32_t)0x00000020) /*!< ADC14 conversion-time-overflow interrupt enable */ 1810 /* ADC14_IER1[RDYIE] Bits */ 1811 #define ADC14_IER1_RDYIE_OFS ( 6) /*!< ADC14RDYIE Bit Offset */ 1812 #define ADC14_IER1_RDYIE ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt enable */ 1813 /* ADC14_IFGR0[IFG0] Bits */ 1814 #define ADC14_IFGR0_IFG0_OFS ( 0) /*!< ADC14IFG0 Bit Offset */ 1815 #define ADC14_IFGR0_IFG0 ((uint32_t)0x00000001) /*!< ADC14MEM0 interrupt flag */ 1816 /* ADC14_IFGR0[IFG1] Bits */ 1817 #define ADC14_IFGR0_IFG1_OFS ( 1) /*!< ADC14IFG1 Bit Offset */ 1818 #define ADC14_IFGR0_IFG1 ((uint32_t)0x00000002) /*!< ADC14MEM1 interrupt flag */ 1819 /* ADC14_IFGR0[IFG2] Bits */ 1820 #define ADC14_IFGR0_IFG2_OFS ( 2) /*!< ADC14IFG2 Bit Offset */ 1821 #define ADC14_IFGR0_IFG2 ((uint32_t)0x00000004) /*!< ADC14MEM2 interrupt flag */ 1822 /* ADC14_IFGR0[IFG3] Bits */ 1823 #define ADC14_IFGR0_IFG3_OFS ( 3) /*!< ADC14IFG3 Bit Offset */ 1824 #define ADC14_IFGR0_IFG3 ((uint32_t)0x00000008) /*!< ADC14MEM3 interrupt flag */ 1825 /* ADC14_IFGR0[IFG4] Bits */ 1826 #define ADC14_IFGR0_IFG4_OFS ( 4) /*!< ADC14IFG4 Bit Offset */ 1827 #define ADC14_IFGR0_IFG4 ((uint32_t)0x00000010) /*!< ADC14MEM4 interrupt flag */ 1828 /* ADC14_IFGR0[IFG5] Bits */ 1829 #define ADC14_IFGR0_IFG5_OFS ( 5) /*!< ADC14IFG5 Bit Offset */ 1830 #define ADC14_IFGR0_IFG5 ((uint32_t)0x00000020) /*!< ADC14MEM5 interrupt flag */ 1831 /* ADC14_IFGR0[IFG6] Bits */ 1832 #define ADC14_IFGR0_IFG6_OFS ( 6) /*!< ADC14IFG6 Bit Offset */ 1833 #define ADC14_IFGR0_IFG6 ((uint32_t)0x00000040) /*!< ADC14MEM6 interrupt flag */ 1834 /* ADC14_IFGR0[IFG7] Bits */ 1835 #define ADC14_IFGR0_IFG7_OFS ( 7) /*!< ADC14IFG7 Bit Offset */ 1836 #define ADC14_IFGR0_IFG7 ((uint32_t)0x00000080) /*!< ADC14MEM7 interrupt flag */ 1837 /* ADC14_IFGR0[IFG8] Bits */ 1838 #define ADC14_IFGR0_IFG8_OFS ( 8) /*!< ADC14IFG8 Bit Offset */ 1839 #define ADC14_IFGR0_IFG8 ((uint32_t)0x00000100) /*!< ADC14MEM8 interrupt flag */ 1840 /* ADC14_IFGR0[IFG9] Bits */ 1841 #define ADC14_IFGR0_IFG9_OFS ( 9) /*!< ADC14IFG9 Bit Offset */ 1842 #define ADC14_IFGR0_IFG9 ((uint32_t)0x00000200) /*!< ADC14MEM9 interrupt flag */ 1843 /* ADC14_IFGR0[IFG10] Bits */ 1844 #define ADC14_IFGR0_IFG10_OFS (10) /*!< ADC14IFG10 Bit Offset */ 1845 #define ADC14_IFGR0_IFG10 ((uint32_t)0x00000400) /*!< ADC14MEM10 interrupt flag */ 1846 /* ADC14_IFGR0[IFG11] Bits */ 1847 #define ADC14_IFGR0_IFG11_OFS (11) /*!< ADC14IFG11 Bit Offset */ 1848 #define ADC14_IFGR0_IFG11 ((uint32_t)0x00000800) /*!< ADC14MEM11 interrupt flag */ 1849 /* ADC14_IFGR0[IFG12] Bits */ 1850 #define ADC14_IFGR0_IFG12_OFS (12) /*!< ADC14IFG12 Bit Offset */ 1851 #define ADC14_IFGR0_IFG12 ((uint32_t)0x00001000) /*!< ADC14MEM12 interrupt flag */ 1852 /* ADC14_IFGR0[IFG13] Bits */ 1853 #define ADC14_IFGR0_IFG13_OFS (13) /*!< ADC14IFG13 Bit Offset */ 1854 #define ADC14_IFGR0_IFG13 ((uint32_t)0x00002000) /*!< ADC14MEM13 interrupt flag */ 1855 /* ADC14_IFGR0[IFG14] Bits */ 1856 #define ADC14_IFGR0_IFG14_OFS (14) /*!< ADC14IFG14 Bit Offset */ 1857 #define ADC14_IFGR0_IFG14 ((uint32_t)0x00004000) /*!< ADC14MEM14 interrupt flag */ 1858 /* ADC14_IFGR0[IFG15] Bits */ 1859 #define ADC14_IFGR0_IFG15_OFS (15) /*!< ADC14IFG15 Bit Offset */ 1860 #define ADC14_IFGR0_IFG15 ((uint32_t)0x00008000) /*!< ADC14MEM15 interrupt flag */ 1861 /* ADC14_IFGR0[IFG16] Bits */ 1862 #define ADC14_IFGR0_IFG16_OFS (16) /*!< ADC14IFG16 Bit Offset */ 1863 #define ADC14_IFGR0_IFG16 ((uint32_t)0x00010000) /*!< ADC14MEM16 interrupt flag */ 1864 /* ADC14_IFGR0[IFG17] Bits */ 1865 #define ADC14_IFGR0_IFG17_OFS (17) /*!< ADC14IFG17 Bit Offset */ 1866 #define ADC14_IFGR0_IFG17 ((uint32_t)0x00020000) /*!< ADC14MEM17 interrupt flag */ 1867 /* ADC14_IFGR0[IFG18] Bits */ 1868 #define ADC14_IFGR0_IFG18_OFS (18) /*!< ADC14IFG18 Bit Offset */ 1869 #define ADC14_IFGR0_IFG18 ((uint32_t)0x00040000) /*!< ADC14MEM18 interrupt flag */ 1870 /* ADC14_IFGR0[IFG19] Bits */ 1871 #define ADC14_IFGR0_IFG19_OFS (19) /*!< ADC14IFG19 Bit Offset */ 1872 #define ADC14_IFGR0_IFG19 ((uint32_t)0x00080000) /*!< ADC14MEM19 interrupt flag */ 1873 /* ADC14_IFGR0[IFG20] Bits */ 1874 #define ADC14_IFGR0_IFG20_OFS (20) /*!< ADC14IFG20 Bit Offset */ 1875 #define ADC14_IFGR0_IFG20 ((uint32_t)0x00100000) /*!< ADC14MEM20 interrupt flag */ 1876 /* ADC14_IFGR0[IFG21] Bits */ 1877 #define ADC14_IFGR0_IFG21_OFS (21) /*!< ADC14IFG21 Bit Offset */ 1878 #define ADC14_IFGR0_IFG21 ((uint32_t)0x00200000) /*!< ADC14MEM21 interrupt flag */ 1879 /* ADC14_IFGR0[IFG22] Bits */ 1880 #define ADC14_IFGR0_IFG22_OFS (22) /*!< ADC14IFG22 Bit Offset */ 1881 #define ADC14_IFGR0_IFG22 ((uint32_t)0x00400000) /*!< ADC14MEM22 interrupt flag */ 1882 /* ADC14_IFGR0[IFG23] Bits */ 1883 #define ADC14_IFGR0_IFG23_OFS (23) /*!< ADC14IFG23 Bit Offset */ 1884 #define ADC14_IFGR0_IFG23 ((uint32_t)0x00800000) /*!< ADC14MEM23 interrupt flag */ 1885 /* ADC14_IFGR0[IFG24] Bits */ 1886 #define ADC14_IFGR0_IFG24_OFS (24) /*!< ADC14IFG24 Bit Offset */ 1887 #define ADC14_IFGR0_IFG24 ((uint32_t)0x01000000) /*!< ADC14MEM24 interrupt flag */ 1888 /* ADC14_IFGR0[IFG25] Bits */ 1889 #define ADC14_IFGR0_IFG25_OFS (25) /*!< ADC14IFG25 Bit Offset */ 1890 #define ADC14_IFGR0_IFG25 ((uint32_t)0x02000000) /*!< ADC14MEM25 interrupt flag */ 1891 /* ADC14_IFGR0[IFG26] Bits */ 1892 #define ADC14_IFGR0_IFG26_OFS (26) /*!< ADC14IFG26 Bit Offset */ 1893 #define ADC14_IFGR0_IFG26 ((uint32_t)0x04000000) /*!< ADC14MEM26 interrupt flag */ 1894 /* ADC14_IFGR0[IFG27] Bits */ 1895 #define ADC14_IFGR0_IFG27_OFS (27) /*!< ADC14IFG27 Bit Offset */ 1896 #define ADC14_IFGR0_IFG27 ((uint32_t)0x08000000) /*!< ADC14MEM27 interrupt flag */ 1897 /* ADC14_IFGR0[IFG28] Bits */ 1898 #define ADC14_IFGR0_IFG28_OFS (28) /*!< ADC14IFG28 Bit Offset */ 1899 #define ADC14_IFGR0_IFG28 ((uint32_t)0x10000000) /*!< ADC14MEM28 interrupt flag */ 1900 /* ADC14_IFGR0[IFG29] Bits */ 1901 #define ADC14_IFGR0_IFG29_OFS (29) /*!< ADC14IFG29 Bit Offset */ 1902 #define ADC14_IFGR0_IFG29 ((uint32_t)0x20000000) /*!< ADC14MEM29 interrupt flag */ 1903 /* ADC14_IFGR0[IFG30] Bits */ 1904 #define ADC14_IFGR0_IFG30_OFS (30) /*!< ADC14IFG30 Bit Offset */ 1905 #define ADC14_IFGR0_IFG30 ((uint32_t)0x40000000) /*!< ADC14MEM30 interrupt flag */ 1906 /* ADC14_IFGR0[IFG31] Bits */ 1907 #define ADC14_IFGR0_IFG31_OFS (31) /*!< ADC14IFG31 Bit Offset */ 1908 #define ADC14_IFGR0_IFG31 ((uint32_t)0x80000000) /*!< ADC14MEM31 interrupt flag */ 1909 /* ADC14_IFGR1[INIFG] Bits */ 1910 #define ADC14_IFGR1_INIFG_OFS ( 1) /*!< ADC14INIFG Bit Offset */ 1911 #define ADC14_IFGR1_INIFG ((uint32_t)0x00000002) /*!< Interrupt flag for ADC14MEMx within comparator window */ 1912 /* ADC14_IFGR1[LOIFG] Bits */ 1913 #define ADC14_IFGR1_LOIFG_OFS ( 2) /*!< ADC14LOIFG Bit Offset */ 1914 #define ADC14_IFGR1_LOIFG ((uint32_t)0x00000004) /*!< Interrupt flag for ADC14MEMx below comparator window */ 1915 /* ADC14_IFGR1[HIIFG] Bits */ 1916 #define ADC14_IFGR1_HIIFG_OFS ( 3) /*!< ADC14HIIFG Bit Offset */ 1917 #define ADC14_IFGR1_HIIFG ((uint32_t)0x00000008) /*!< Interrupt flag for ADC14MEMx above comparator window */ 1918 /* ADC14_IFGR1[OVIFG] Bits */ 1919 #define ADC14_IFGR1_OVIFG_OFS ( 4) /*!< ADC14OVIFG Bit Offset */ 1920 #define ADC14_IFGR1_OVIFG ((uint32_t)0x00000010) /*!< ADC14MEMx overflow interrupt flag */ 1921 /* ADC14_IFGR1[TOVIFG] Bits */ 1922 #define ADC14_IFGR1_TOVIFG_OFS ( 5) /*!< ADC14TOVIFG Bit Offset */ 1923 #define ADC14_IFGR1_TOVIFG ((uint32_t)0x00000020) /*!< ADC14 conversion time overflow interrupt flag */ 1924 /* ADC14_IFGR1[RDYIFG] Bits */ 1925 #define ADC14_IFGR1_RDYIFG_OFS ( 6) /*!< ADC14RDYIFG Bit Offset */ 1926 #define ADC14_IFGR1_RDYIFG ((uint32_t)0x00000040) /*!< ADC14 local buffered reference ready interrupt flag */ 1927 /* ADC14_CLRIFGR0[CLRIFG0] Bits */ 1928 #define ADC14_CLRIFGR0_CLRIFG0_OFS ( 0) /*!< CLRADC14IFG0 Bit Offset */ 1929 #define ADC14_CLRIFGR0_CLRIFG0 ((uint32_t)0x00000001) /*!< clear ADC14IFG0 */ 1930 /* ADC14_CLRIFGR0[CLRIFG1] Bits */ 1931 #define ADC14_CLRIFGR0_CLRIFG1_OFS ( 1) /*!< CLRADC14IFG1 Bit Offset */ 1932 #define ADC14_CLRIFGR0_CLRIFG1 ((uint32_t)0x00000002) /*!< clear ADC14IFG1 */ 1933 /* ADC14_CLRIFGR0[CLRIFG2] Bits */ 1934 #define ADC14_CLRIFGR0_CLRIFG2_OFS ( 2) /*!< CLRADC14IFG2 Bit Offset */ 1935 #define ADC14_CLRIFGR0_CLRIFG2 ((uint32_t)0x00000004) /*!< clear ADC14IFG2 */ 1936 /* ADC14_CLRIFGR0[CLRIFG3] Bits */ 1937 #define ADC14_CLRIFGR0_CLRIFG3_OFS ( 3) /*!< CLRADC14IFG3 Bit Offset */ 1938 #define ADC14_CLRIFGR0_CLRIFG3 ((uint32_t)0x00000008) /*!< clear ADC14IFG3 */ 1939 /* ADC14_CLRIFGR0[CLRIFG4] Bits */ 1940 #define ADC14_CLRIFGR0_CLRIFG4_OFS ( 4) /*!< CLRADC14IFG4 Bit Offset */ 1941 #define ADC14_CLRIFGR0_CLRIFG4 ((uint32_t)0x00000010) /*!< clear ADC14IFG4 */ 1942 /* ADC14_CLRIFGR0[CLRIFG5] Bits */ 1943 #define ADC14_CLRIFGR0_CLRIFG5_OFS ( 5) /*!< CLRADC14IFG5 Bit Offset */ 1944 #define ADC14_CLRIFGR0_CLRIFG5 ((uint32_t)0x00000020) /*!< clear ADC14IFG5 */ 1945 /* ADC14_CLRIFGR0[CLRIFG6] Bits */ 1946 #define ADC14_CLRIFGR0_CLRIFG6_OFS ( 6) /*!< CLRADC14IFG6 Bit Offset */ 1947 #define ADC14_CLRIFGR0_CLRIFG6 ((uint32_t)0x00000040) /*!< clear ADC14IFG6 */ 1948 /* ADC14_CLRIFGR0[CLRIFG7] Bits */ 1949 #define ADC14_CLRIFGR0_CLRIFG7_OFS ( 7) /*!< CLRADC14IFG7 Bit Offset */ 1950 #define ADC14_CLRIFGR0_CLRIFG7 ((uint32_t)0x00000080) /*!< clear ADC14IFG7 */ 1951 /* ADC14_CLRIFGR0[CLRIFG8] Bits */ 1952 #define ADC14_CLRIFGR0_CLRIFG8_OFS ( 8) /*!< CLRADC14IFG8 Bit Offset */ 1953 #define ADC14_CLRIFGR0_CLRIFG8 ((uint32_t)0x00000100) /*!< clear ADC14IFG8 */ 1954 /* ADC14_CLRIFGR0[CLRIFG9] Bits */ 1955 #define ADC14_CLRIFGR0_CLRIFG9_OFS ( 9) /*!< CLRADC14IFG9 Bit Offset */ 1956 #define ADC14_CLRIFGR0_CLRIFG9 ((uint32_t)0x00000200) /*!< clear ADC14IFG9 */ 1957 /* ADC14_CLRIFGR0[CLRIFG10] Bits */ 1958 #define ADC14_CLRIFGR0_CLRIFG10_OFS (10) /*!< CLRADC14IFG10 Bit Offset */ 1959 #define ADC14_CLRIFGR0_CLRIFG10 ((uint32_t)0x00000400) /*!< clear ADC14IFG10 */ 1960 /* ADC14_CLRIFGR0[CLRIFG11] Bits */ 1961 #define ADC14_CLRIFGR0_CLRIFG11_OFS (11) /*!< CLRADC14IFG11 Bit Offset */ 1962 #define ADC14_CLRIFGR0_CLRIFG11 ((uint32_t)0x00000800) /*!< clear ADC14IFG11 */ 1963 /* ADC14_CLRIFGR0[CLRIFG12] Bits */ 1964 #define ADC14_CLRIFGR0_CLRIFG12_OFS (12) /*!< CLRADC14IFG12 Bit Offset */ 1965 #define ADC14_CLRIFGR0_CLRIFG12 ((uint32_t)0x00001000) /*!< clear ADC14IFG12 */ 1966 /* ADC14_CLRIFGR0[CLRIFG13] Bits */ 1967 #define ADC14_CLRIFGR0_CLRIFG13_OFS (13) /*!< CLRADC14IFG13 Bit Offset */ 1968 #define ADC14_CLRIFGR0_CLRIFG13 ((uint32_t)0x00002000) /*!< clear ADC14IFG13 */ 1969 /* ADC14_CLRIFGR0[CLRIFG14] Bits */ 1970 #define ADC14_CLRIFGR0_CLRIFG14_OFS (14) /*!< CLRADC14IFG14 Bit Offset */ 1971 #define ADC14_CLRIFGR0_CLRIFG14 ((uint32_t)0x00004000) /*!< clear ADC14IFG14 */ 1972 /* ADC14_CLRIFGR0[CLRIFG15] Bits */ 1973 #define ADC14_CLRIFGR0_CLRIFG15_OFS (15) /*!< CLRADC14IFG15 Bit Offset */ 1974 #define ADC14_CLRIFGR0_CLRIFG15 ((uint32_t)0x00008000) /*!< clear ADC14IFG15 */ 1975 /* ADC14_CLRIFGR0[CLRIFG16] Bits */ 1976 #define ADC14_CLRIFGR0_CLRIFG16_OFS (16) /*!< CLRADC14IFG16 Bit Offset */ 1977 #define ADC14_CLRIFGR0_CLRIFG16 ((uint32_t)0x00010000) /*!< clear ADC14IFG16 */ 1978 /* ADC14_CLRIFGR0[CLRIFG17] Bits */ 1979 #define ADC14_CLRIFGR0_CLRIFG17_OFS (17) /*!< CLRADC14IFG17 Bit Offset */ 1980 #define ADC14_CLRIFGR0_CLRIFG17 ((uint32_t)0x00020000) /*!< clear ADC14IFG17 */ 1981 /* ADC14_CLRIFGR0[CLRIFG18] Bits */ 1982 #define ADC14_CLRIFGR0_CLRIFG18_OFS (18) /*!< CLRADC14IFG18 Bit Offset */ 1983 #define ADC14_CLRIFGR0_CLRIFG18 ((uint32_t)0x00040000) /*!< clear ADC14IFG18 */ 1984 /* ADC14_CLRIFGR0[CLRIFG19] Bits */ 1985 #define ADC14_CLRIFGR0_CLRIFG19_OFS (19) /*!< CLRADC14IFG19 Bit Offset */ 1986 #define ADC14_CLRIFGR0_CLRIFG19 ((uint32_t)0x00080000) /*!< clear ADC14IFG19 */ 1987 /* ADC14_CLRIFGR0[CLRIFG20] Bits */ 1988 #define ADC14_CLRIFGR0_CLRIFG20_OFS (20) /*!< CLRADC14IFG20 Bit Offset */ 1989 #define ADC14_CLRIFGR0_CLRIFG20 ((uint32_t)0x00100000) /*!< clear ADC14IFG20 */ 1990 /* ADC14_CLRIFGR0[CLRIFG21] Bits */ 1991 #define ADC14_CLRIFGR0_CLRIFG21_OFS (21) /*!< CLRADC14IFG21 Bit Offset */ 1992 #define ADC14_CLRIFGR0_CLRIFG21 ((uint32_t)0x00200000) /*!< clear ADC14IFG21 */ 1993 /* ADC14_CLRIFGR0[CLRIFG22] Bits */ 1994 #define ADC14_CLRIFGR0_CLRIFG22_OFS (22) /*!< CLRADC14IFG22 Bit Offset */ 1995 #define ADC14_CLRIFGR0_CLRIFG22 ((uint32_t)0x00400000) /*!< clear ADC14IFG22 */ 1996 /* ADC14_CLRIFGR0[CLRIFG23] Bits */ 1997 #define ADC14_CLRIFGR0_CLRIFG23_OFS (23) /*!< CLRADC14IFG23 Bit Offset */ 1998 #define ADC14_CLRIFGR0_CLRIFG23 ((uint32_t)0x00800000) /*!< clear ADC14IFG23 */ 1999 /* ADC14_CLRIFGR0[CLRIFG24] Bits */ 2000 #define ADC14_CLRIFGR0_CLRIFG24_OFS (24) /*!< CLRADC14IFG24 Bit Offset */ 2001 #define ADC14_CLRIFGR0_CLRIFG24 ((uint32_t)0x01000000) /*!< clear ADC14IFG24 */ 2002 /* ADC14_CLRIFGR0[CLRIFG25] Bits */ 2003 #define ADC14_CLRIFGR0_CLRIFG25_OFS (25) /*!< CLRADC14IFG25 Bit Offset */ 2004 #define ADC14_CLRIFGR0_CLRIFG25 ((uint32_t)0x02000000) /*!< clear ADC14IFG25 */ 2005 /* ADC14_CLRIFGR0[CLRIFG26] Bits */ 2006 #define ADC14_CLRIFGR0_CLRIFG26_OFS (26) /*!< CLRADC14IFG26 Bit Offset */ 2007 #define ADC14_CLRIFGR0_CLRIFG26 ((uint32_t)0x04000000) /*!< clear ADC14IFG26 */ 2008 /* ADC14_CLRIFGR0[CLRIFG27] Bits */ 2009 #define ADC14_CLRIFGR0_CLRIFG27_OFS (27) /*!< CLRADC14IFG27 Bit Offset */ 2010 #define ADC14_CLRIFGR0_CLRIFG27 ((uint32_t)0x08000000) /*!< clear ADC14IFG27 */ 2011 /* ADC14_CLRIFGR0[CLRIFG28] Bits */ 2012 #define ADC14_CLRIFGR0_CLRIFG28_OFS (28) /*!< CLRADC14IFG28 Bit Offset */ 2013 #define ADC14_CLRIFGR0_CLRIFG28 ((uint32_t)0x10000000) /*!< clear ADC14IFG28 */ 2014 /* ADC14_CLRIFGR0[CLRIFG29] Bits */ 2015 #define ADC14_CLRIFGR0_CLRIFG29_OFS (29) /*!< CLRADC14IFG29 Bit Offset */ 2016 #define ADC14_CLRIFGR0_CLRIFG29 ((uint32_t)0x20000000) /*!< clear ADC14IFG29 */ 2017 /* ADC14_CLRIFGR0[CLRIFG30] Bits */ 2018 #define ADC14_CLRIFGR0_CLRIFG30_OFS (30) /*!< CLRADC14IFG30 Bit Offset */ 2019 #define ADC14_CLRIFGR0_CLRIFG30 ((uint32_t)0x40000000) /*!< clear ADC14IFG30 */ 2020 /* ADC14_CLRIFGR0[CLRIFG31] Bits */ 2021 #define ADC14_CLRIFGR0_CLRIFG31_OFS (31) /*!< CLRADC14IFG31 Bit Offset */ 2022 #define ADC14_CLRIFGR0_CLRIFG31 ((uint32_t)0x80000000) /*!< clear ADC14IFG31 */ 2023 /* ADC14_CLRIFGR1[CLRINIFG] Bits */ 2024 #define ADC14_CLRIFGR1_CLRINIFG_OFS ( 1) /*!< CLRADC14INIFG Bit Offset */ 2025 #define ADC14_CLRIFGR1_CLRINIFG ((uint32_t)0x00000002) /*!< clear ADC14INIFG */ 2026 /* ADC14_CLRIFGR1[CLRLOIFG] Bits */ 2027 #define ADC14_CLRIFGR1_CLRLOIFG_OFS ( 2) /*!< CLRADC14LOIFG Bit Offset */ 2028 #define ADC14_CLRIFGR1_CLRLOIFG ((uint32_t)0x00000004) /*!< clear ADC14LOIFG */ 2029 /* ADC14_CLRIFGR1[CLRHIIFG] Bits */ 2030 #define ADC14_CLRIFGR1_CLRHIIFG_OFS ( 3) /*!< CLRADC14HIIFG Bit Offset */ 2031 #define ADC14_CLRIFGR1_CLRHIIFG ((uint32_t)0x00000008) /*!< clear ADC14HIIFG */ 2032 /* ADC14_CLRIFGR1[CLROVIFG] Bits */ 2033 #define ADC14_CLRIFGR1_CLROVIFG_OFS ( 4) /*!< CLRADC14OVIFG Bit Offset */ 2034 #define ADC14_CLRIFGR1_CLROVIFG ((uint32_t)0x00000010) /*!< clear ADC14OVIFG */ 2035 /* ADC14_CLRIFGR1[CLRTOVIFG] Bits */ 2036 #define ADC14_CLRIFGR1_CLRTOVIFG_OFS ( 5) /*!< CLRADC14TOVIFG Bit Offset */ 2037 #define ADC14_CLRIFGR1_CLRTOVIFG ((uint32_t)0x00000020) /*!< clear ADC14TOVIFG */ 2038 /* ADC14_CLRIFGR1[CLRRDYIFG] Bits */ 2039 #define ADC14_CLRIFGR1_CLRRDYIFG_OFS ( 6) /*!< CLRADC14RDYIFG Bit Offset */ 2040 #define ADC14_CLRIFGR1_CLRRDYIFG ((uint32_t)0x00000040) /*!< clear ADC14RDYIFG */ 2041 2042 /****************************************************************************** 2043 * AES256 Bits 2044 ******************************************************************************/ 2045 /* AES256_CTL0[OP] Bits */ 2046 #define AES256_CTL0_OP_OFS ( 0) /*!< AESOPx Bit Offset */ 2047 #define AES256_CTL0_OP_MASK ((uint16_t)0x0003) /*!< AESOPx Bit Mask */ 2048 #define AES256_CTL0_OP0 ((uint16_t)0x0001) /*!< OP Bit 0 */ 2049 #define AES256_CTL0_OP1 ((uint16_t)0x0002) /*!< OP Bit 1 */ 2050 #define AES256_CTL0_OP_0 ((uint16_t)0x0000) /*!< Encryption */ 2051 #define AES256_CTL0_OP_1 ((uint16_t)0x0001) /*!< Decryption. The provided key is the same key used for encryption */ 2052 #define AES256_CTL0_OP_2 ((uint16_t)0x0002) /*!< Generate first round key required for decryption */ 2053 #define AES256_CTL0_OP_3 ((uint16_t)0x0003) /*!< Decryption. The provided key is the first round key required for decryption */ 2054 /* AES256_CTL0[KL] Bits */ 2055 #define AES256_CTL0_KL_OFS ( 2) /*!< AESKLx Bit Offset */ 2056 #define AES256_CTL0_KL_MASK ((uint16_t)0x000C) /*!< AESKLx Bit Mask */ 2057 #define AES256_CTL0_KL0 ((uint16_t)0x0004) /*!< KL Bit 0 */ 2058 #define AES256_CTL0_KL1 ((uint16_t)0x0008) /*!< KL Bit 1 */ 2059 #define AES256_CTL0_KL_0 ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ 2060 #define AES256_CTL0_KL_1 ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ 2061 #define AES256_CTL0_KL_2 ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ 2062 #define AES256_CTL0_KL__128BIT ((uint16_t)0x0000) /*!< AES128. The key size is 128 bit */ 2063 #define AES256_CTL0_KL__192BIT ((uint16_t)0x0004) /*!< AES192. The key size is 192 bit. */ 2064 #define AES256_CTL0_KL__256BIT ((uint16_t)0x0008) /*!< AES256. The key size is 256 bit */ 2065 /* AES256_CTL0[CM] Bits */ 2066 #define AES256_CTL0_CM_OFS ( 5) /*!< AESCMx Bit Offset */ 2067 #define AES256_CTL0_CM_MASK ((uint16_t)0x0060) /*!< AESCMx Bit Mask */ 2068 #define AES256_CTL0_CM0 ((uint16_t)0x0020) /*!< CM Bit 0 */ 2069 #define AES256_CTL0_CM1 ((uint16_t)0x0040) /*!< CM Bit 1 */ 2070 #define AES256_CTL0_CM_0 ((uint16_t)0x0000) /*!< ECB */ 2071 #define AES256_CTL0_CM_1 ((uint16_t)0x0020) /*!< CBC */ 2072 #define AES256_CTL0_CM_2 ((uint16_t)0x0040) /*!< OFB */ 2073 #define AES256_CTL0_CM_3 ((uint16_t)0x0060) /*!< CFB */ 2074 #define AES256_CTL0_CM__ECB ((uint16_t)0x0000) /*!< ECB */ 2075 #define AES256_CTL0_CM__CBC ((uint16_t)0x0020) /*!< CBC */ 2076 #define AES256_CTL0_CM__OFB ((uint16_t)0x0040) /*!< OFB */ 2077 #define AES256_CTL0_CM__CFB ((uint16_t)0x0060) /*!< CFB */ 2078 /* AES256_CTL0[SWRST] Bits */ 2079 #define AES256_CTL0_SWRST_OFS ( 7) /*!< AESSWRST Bit Offset */ 2080 #define AES256_CTL0_SWRST ((uint16_t)0x0080) /*!< AES software reset */ 2081 /* AES256_CTL0[RDYIFG] Bits */ 2082 #define AES256_CTL0_RDYIFG_OFS ( 8) /*!< AESRDYIFG Bit Offset */ 2083 #define AES256_CTL0_RDYIFG ((uint16_t)0x0100) /*!< AES ready interrupt flag */ 2084 /* AES256_CTL0[ERRFG] Bits */ 2085 #define AES256_CTL0_ERRFG_OFS (11) /*!< AESERRFG Bit Offset */ 2086 #define AES256_CTL0_ERRFG ((uint16_t)0x0800) /*!< AES error flag */ 2087 /* AES256_CTL0[RDYIE] Bits */ 2088 #define AES256_CTL0_RDYIE_OFS (12) /*!< AESRDYIE Bit Offset */ 2089 #define AES256_CTL0_RDYIE ((uint16_t)0x1000) /*!< AES ready interrupt enable */ 2090 /* AES256_CTL0[CMEN] Bits */ 2091 #define AES256_CTL0_CMEN_OFS (15) /*!< AESCMEN Bit Offset */ 2092 #define AES256_CTL0_CMEN ((uint16_t)0x8000) /*!< AES cipher mode enable */ 2093 /* AES256_CTL1[BLKCNT] Bits */ 2094 #define AES256_CTL1_BLKCNT_OFS ( 0) /*!< AESBLKCNTx Bit Offset */ 2095 #define AES256_CTL1_BLKCNT_MASK ((uint16_t)0x00FF) /*!< AESBLKCNTx Bit Mask */ 2096 #define AES256_CTL1_BLKCNT0 ((uint16_t)0x0001) /*!< BLKCNT Bit 0 */ 2097 #define AES256_CTL1_BLKCNT1 ((uint16_t)0x0002) /*!< BLKCNT Bit 1 */ 2098 #define AES256_CTL1_BLKCNT2 ((uint16_t)0x0004) /*!< BLKCNT Bit 2 */ 2099 #define AES256_CTL1_BLKCNT3 ((uint16_t)0x0008) /*!< BLKCNT Bit 3 */ 2100 #define AES256_CTL1_BLKCNT4 ((uint16_t)0x0010) /*!< BLKCNT Bit 4 */ 2101 #define AES256_CTL1_BLKCNT5 ((uint16_t)0x0020) /*!< BLKCNT Bit 5 */ 2102 #define AES256_CTL1_BLKCNT6 ((uint16_t)0x0040) /*!< BLKCNT Bit 6 */ 2103 #define AES256_CTL1_BLKCNT7 ((uint16_t)0x0080) /*!< BLKCNT Bit 7 */ 2104 /* AES256_STAT[BUSY] Bits */ 2105 #define AES256_STAT_BUSY_OFS ( 0) /*!< AESBUSY Bit Offset */ 2106 #define AES256_STAT_BUSY ((uint16_t)0x0001) /*!< AES accelerator module busy */ 2107 /* AES256_STAT[KEYWR] Bits */ 2108 #define AES256_STAT_KEYWR_OFS ( 1) /*!< AESKEYWR Bit Offset */ 2109 #define AES256_STAT_KEYWR ((uint16_t)0x0002) /*!< All 16 bytes written to AESAKEY */ 2110 /* AES256_STAT[DINWR] Bits */ 2111 #define AES256_STAT_DINWR_OFS ( 2) /*!< AESDINWR Bit Offset */ 2112 #define AES256_STAT_DINWR ((uint16_t)0x0004) /*!< All 16 bytes written to AESADIN, AESAXDIN or AESAXIN */ 2113 /* AES256_STAT[DOUTRD] Bits */ 2114 #define AES256_STAT_DOUTRD_OFS ( 3) /*!< AESDOUTRD Bit Offset */ 2115 #define AES256_STAT_DOUTRD ((uint16_t)0x0008) /*!< All 16 bytes read from AESADOUT */ 2116 /* AES256_STAT[KEYCNT] Bits */ 2117 #define AES256_STAT_KEYCNT_OFS ( 4) /*!< AESKEYCNTx Bit Offset */ 2118 #define AES256_STAT_KEYCNT_MASK ((uint16_t)0x00F0) /*!< AESKEYCNTx Bit Mask */ 2119 #define AES256_STAT_KEYCNT0 ((uint16_t)0x0010) /*!< KEYCNT Bit 0 */ 2120 #define AES256_STAT_KEYCNT1 ((uint16_t)0x0020) /*!< KEYCNT Bit 1 */ 2121 #define AES256_STAT_KEYCNT2 ((uint16_t)0x0040) /*!< KEYCNT Bit 2 */ 2122 #define AES256_STAT_KEYCNT3 ((uint16_t)0x0080) /*!< KEYCNT Bit 3 */ 2123 /* AES256_STAT[DINCNT] Bits */ 2124 #define AES256_STAT_DINCNT_OFS ( 8) /*!< AESDINCNTx Bit Offset */ 2125 #define AES256_STAT_DINCNT_MASK ((uint16_t)0x0F00) /*!< AESDINCNTx Bit Mask */ 2126 #define AES256_STAT_DINCNT0 ((uint16_t)0x0100) /*!< DINCNT Bit 0 */ 2127 #define AES256_STAT_DINCNT1 ((uint16_t)0x0200) /*!< DINCNT Bit 1 */ 2128 #define AES256_STAT_DINCNT2 ((uint16_t)0x0400) /*!< DINCNT Bit 2 */ 2129 #define AES256_STAT_DINCNT3 ((uint16_t)0x0800) /*!< DINCNT Bit 3 */ 2130 /* AES256_STAT[DOUTCNT] Bits */ 2131 #define AES256_STAT_DOUTCNT_OFS (12) /*!< AESDOUTCNTx Bit Offset */ 2132 #define AES256_STAT_DOUTCNT_MASK ((uint16_t)0xF000) /*!< AESDOUTCNTx Bit Mask */ 2133 #define AES256_STAT_DOUTCNT0 ((uint16_t)0x1000) /*!< DOUTCNT Bit 0 */ 2134 #define AES256_STAT_DOUTCNT1 ((uint16_t)0x2000) /*!< DOUTCNT Bit 1 */ 2135 #define AES256_STAT_DOUTCNT2 ((uint16_t)0x4000) /*!< DOUTCNT Bit 2 */ 2136 #define AES256_STAT_DOUTCNT3 ((uint16_t)0x8000) /*!< DOUTCNT Bit 3 */ 2137 /* AES256_KEY[KEY0] Bits */ 2138 #define AES256_KEY_KEY0_OFS ( 0) /*!< AESKEY0x Bit Offset */ 2139 #define AES256_KEY_KEY0_MASK ((uint16_t)0x00FF) /*!< AESKEY0x Bit Mask */ 2140 #define AES256_KEY_KEY00 ((uint16_t)0x0001) /*!< KEY0 Bit 0 */ 2141 #define AES256_KEY_KEY01 ((uint16_t)0x0002) /*!< KEY0 Bit 1 */ 2142 #define AES256_KEY_KEY02 ((uint16_t)0x0004) /*!< KEY0 Bit 2 */ 2143 #define AES256_KEY_KEY03 ((uint16_t)0x0008) /*!< KEY0 Bit 3 */ 2144 #define AES256_KEY_KEY04 ((uint16_t)0x0010) /*!< KEY0 Bit 4 */ 2145 #define AES256_KEY_KEY05 ((uint16_t)0x0020) /*!< KEY0 Bit 5 */ 2146 #define AES256_KEY_KEY06 ((uint16_t)0x0040) /*!< KEY0 Bit 6 */ 2147 #define AES256_KEY_KEY07 ((uint16_t)0x0080) /*!< KEY0 Bit 7 */ 2148 /* AES256_KEY[KEY1] Bits */ 2149 #define AES256_KEY_KEY1_OFS ( 8) /*!< AESKEY1x Bit Offset */ 2150 #define AES256_KEY_KEY1_MASK ((uint16_t)0xFF00) /*!< AESKEY1x Bit Mask */ 2151 #define AES256_KEY_KEY10 ((uint16_t)0x0100) /*!< KEY1 Bit 0 */ 2152 #define AES256_KEY_KEY11 ((uint16_t)0x0200) /*!< KEY1 Bit 1 */ 2153 #define AES256_KEY_KEY12 ((uint16_t)0x0400) /*!< KEY1 Bit 2 */ 2154 #define AES256_KEY_KEY13 ((uint16_t)0x0800) /*!< KEY1 Bit 3 */ 2155 #define AES256_KEY_KEY14 ((uint16_t)0x1000) /*!< KEY1 Bit 4 */ 2156 #define AES256_KEY_KEY15 ((uint16_t)0x2000) /*!< KEY1 Bit 5 */ 2157 #define AES256_KEY_KEY16 ((uint16_t)0x4000) /*!< KEY1 Bit 6 */ 2158 #define AES256_KEY_KEY17 ((uint16_t)0x8000) /*!< KEY1 Bit 7 */ 2159 /* AES256_DIN[DIN0] Bits */ 2160 #define AES256_DIN_DIN0_OFS ( 0) /*!< AESDIN0x Bit Offset */ 2161 #define AES256_DIN_DIN0_MASK ((uint16_t)0x00FF) /*!< AESDIN0x Bit Mask */ 2162 #define AES256_DIN_DIN00 ((uint16_t)0x0001) /*!< DIN0 Bit 0 */ 2163 #define AES256_DIN_DIN01 ((uint16_t)0x0002) /*!< DIN0 Bit 1 */ 2164 #define AES256_DIN_DIN02 ((uint16_t)0x0004) /*!< DIN0 Bit 2 */ 2165 #define AES256_DIN_DIN03 ((uint16_t)0x0008) /*!< DIN0 Bit 3 */ 2166 #define AES256_DIN_DIN04 ((uint16_t)0x0010) /*!< DIN0 Bit 4 */ 2167 #define AES256_DIN_DIN05 ((uint16_t)0x0020) /*!< DIN0 Bit 5 */ 2168 #define AES256_DIN_DIN06 ((uint16_t)0x0040) /*!< DIN0 Bit 6 */ 2169 #define AES256_DIN_DIN07 ((uint16_t)0x0080) /*!< DIN0 Bit 7 */ 2170 /* AES256_DIN[DIN1] Bits */ 2171 #define AES256_DIN_DIN1_OFS ( 8) /*!< AESDIN1x Bit Offset */ 2172 #define AES256_DIN_DIN1_MASK ((uint16_t)0xFF00) /*!< AESDIN1x Bit Mask */ 2173 #define AES256_DIN_DIN10 ((uint16_t)0x0100) /*!< DIN1 Bit 0 */ 2174 #define AES256_DIN_DIN11 ((uint16_t)0x0200) /*!< DIN1 Bit 1 */ 2175 #define AES256_DIN_DIN12 ((uint16_t)0x0400) /*!< DIN1 Bit 2 */ 2176 #define AES256_DIN_DIN13 ((uint16_t)0x0800) /*!< DIN1 Bit 3 */ 2177 #define AES256_DIN_DIN14 ((uint16_t)0x1000) /*!< DIN1 Bit 4 */ 2178 #define AES256_DIN_DIN15 ((uint16_t)0x2000) /*!< DIN1 Bit 5 */ 2179 #define AES256_DIN_DIN16 ((uint16_t)0x4000) /*!< DIN1 Bit 6 */ 2180 #define AES256_DIN_DIN17 ((uint16_t)0x8000) /*!< DIN1 Bit 7 */ 2181 /* AES256_DOUT[DOUT0] Bits */ 2182 #define AES256_DOUT_DOUT0_OFS ( 0) /*!< AESDOUT0x Bit Offset */ 2183 #define AES256_DOUT_DOUT0_MASK ((uint16_t)0x00FF) /*!< AESDOUT0x Bit Mask */ 2184 #define AES256_DOUT_DOUT00 ((uint16_t)0x0001) /*!< DOUT0 Bit 0 */ 2185 #define AES256_DOUT_DOUT01 ((uint16_t)0x0002) /*!< DOUT0 Bit 1 */ 2186 #define AES256_DOUT_DOUT02 ((uint16_t)0x0004) /*!< DOUT0 Bit 2 */ 2187 #define AES256_DOUT_DOUT03 ((uint16_t)0x0008) /*!< DOUT0 Bit 3 */ 2188 #define AES256_DOUT_DOUT04 ((uint16_t)0x0010) /*!< DOUT0 Bit 4 */ 2189 #define AES256_DOUT_DOUT05 ((uint16_t)0x0020) /*!< DOUT0 Bit 5 */ 2190 #define AES256_DOUT_DOUT06 ((uint16_t)0x0040) /*!< DOUT0 Bit 6 */ 2191 #define AES256_DOUT_DOUT07 ((uint16_t)0x0080) /*!< DOUT0 Bit 7 */ 2192 /* AES256_DOUT[DOUT1] Bits */ 2193 #define AES256_DOUT_DOUT1_OFS ( 8) /*!< AESDOUT1x Bit Offset */ 2194 #define AES256_DOUT_DOUT1_MASK ((uint16_t)0xFF00) /*!< AESDOUT1x Bit Mask */ 2195 #define AES256_DOUT_DOUT10 ((uint16_t)0x0100) /*!< DOUT1 Bit 0 */ 2196 #define AES256_DOUT_DOUT11 ((uint16_t)0x0200) /*!< DOUT1 Bit 1 */ 2197 #define AES256_DOUT_DOUT12 ((uint16_t)0x0400) /*!< DOUT1 Bit 2 */ 2198 #define AES256_DOUT_DOUT13 ((uint16_t)0x0800) /*!< DOUT1 Bit 3 */ 2199 #define AES256_DOUT_DOUT14 ((uint16_t)0x1000) /*!< DOUT1 Bit 4 */ 2200 #define AES256_DOUT_DOUT15 ((uint16_t)0x2000) /*!< DOUT1 Bit 5 */ 2201 #define AES256_DOUT_DOUT16 ((uint16_t)0x4000) /*!< DOUT1 Bit 6 */ 2202 #define AES256_DOUT_DOUT17 ((uint16_t)0x8000) /*!< DOUT1 Bit 7 */ 2203 /* AES256_XDIN[XDIN0] Bits */ 2204 #define AES256_XDIN_XDIN0_OFS ( 0) /*!< AESXDIN0x Bit Offset */ 2205 #define AES256_XDIN_XDIN0_MASK ((uint16_t)0x00FF) /*!< AESXDIN0x Bit Mask */ 2206 #define AES256_XDIN_XDIN00 ((uint16_t)0x0001) /*!< XDIN0 Bit 0 */ 2207 #define AES256_XDIN_XDIN01 ((uint16_t)0x0002) /*!< XDIN0 Bit 1 */ 2208 #define AES256_XDIN_XDIN02 ((uint16_t)0x0004) /*!< XDIN0 Bit 2 */ 2209 #define AES256_XDIN_XDIN03 ((uint16_t)0x0008) /*!< XDIN0 Bit 3 */ 2210 #define AES256_XDIN_XDIN04 ((uint16_t)0x0010) /*!< XDIN0 Bit 4 */ 2211 #define AES256_XDIN_XDIN05 ((uint16_t)0x0020) /*!< XDIN0 Bit 5 */ 2212 #define AES256_XDIN_XDIN06 ((uint16_t)0x0040) /*!< XDIN0 Bit 6 */ 2213 #define AES256_XDIN_XDIN07 ((uint16_t)0x0080) /*!< XDIN0 Bit 7 */ 2214 /* AES256_XDIN[XDIN1] Bits */ 2215 #define AES256_XDIN_XDIN1_OFS ( 8) /*!< AESXDIN1x Bit Offset */ 2216 #define AES256_XDIN_XDIN1_MASK ((uint16_t)0xFF00) /*!< AESXDIN1x Bit Mask */ 2217 #define AES256_XDIN_XDIN10 ((uint16_t)0x0100) /*!< XDIN1 Bit 0 */ 2218 #define AES256_XDIN_XDIN11 ((uint16_t)0x0200) /*!< XDIN1 Bit 1 */ 2219 #define AES256_XDIN_XDIN12 ((uint16_t)0x0400) /*!< XDIN1 Bit 2 */ 2220 #define AES256_XDIN_XDIN13 ((uint16_t)0x0800) /*!< XDIN1 Bit 3 */ 2221 #define AES256_XDIN_XDIN14 ((uint16_t)0x1000) /*!< XDIN1 Bit 4 */ 2222 #define AES256_XDIN_XDIN15 ((uint16_t)0x2000) /*!< XDIN1 Bit 5 */ 2223 #define AES256_XDIN_XDIN16 ((uint16_t)0x4000) /*!< XDIN1 Bit 6 */ 2224 #define AES256_XDIN_XDIN17 ((uint16_t)0x8000) /*!< XDIN1 Bit 7 */ 2225 /* AES256_XIN[XIN0] Bits */ 2226 #define AES256_XIN_XIN0_OFS ( 0) /*!< AESXIN0x Bit Offset */ 2227 #define AES256_XIN_XIN0_MASK ((uint16_t)0x00FF) /*!< AESXIN0x Bit Mask */ 2228 #define AES256_XIN_XIN00 ((uint16_t)0x0001) /*!< XIN0 Bit 0 */ 2229 #define AES256_XIN_XIN01 ((uint16_t)0x0002) /*!< XIN0 Bit 1 */ 2230 #define AES256_XIN_XIN02 ((uint16_t)0x0004) /*!< XIN0 Bit 2 */ 2231 #define AES256_XIN_XIN03 ((uint16_t)0x0008) /*!< XIN0 Bit 3 */ 2232 #define AES256_XIN_XIN04 ((uint16_t)0x0010) /*!< XIN0 Bit 4 */ 2233 #define AES256_XIN_XIN05 ((uint16_t)0x0020) /*!< XIN0 Bit 5 */ 2234 #define AES256_XIN_XIN06 ((uint16_t)0x0040) /*!< XIN0 Bit 6 */ 2235 #define AES256_XIN_XIN07 ((uint16_t)0x0080) /*!< XIN0 Bit 7 */ 2236 /* AES256_XIN[XIN1] Bits */ 2237 #define AES256_XIN_XIN1_OFS ( 8) /*!< AESXIN1x Bit Offset */ 2238 #define AES256_XIN_XIN1_MASK ((uint16_t)0xFF00) /*!< AESXIN1x Bit Mask */ 2239 #define AES256_XIN_XIN10 ((uint16_t)0x0100) /*!< XIN1 Bit 0 */ 2240 #define AES256_XIN_XIN11 ((uint16_t)0x0200) /*!< XIN1 Bit 1 */ 2241 #define AES256_XIN_XIN12 ((uint16_t)0x0400) /*!< XIN1 Bit 2 */ 2242 #define AES256_XIN_XIN13 ((uint16_t)0x0800) /*!< XIN1 Bit 3 */ 2243 #define AES256_XIN_XIN14 ((uint16_t)0x1000) /*!< XIN1 Bit 4 */ 2244 #define AES256_XIN_XIN15 ((uint16_t)0x2000) /*!< XIN1 Bit 5 */ 2245 #define AES256_XIN_XIN16 ((uint16_t)0x4000) /*!< XIN1 Bit 6 */ 2246 #define AES256_XIN_XIN17 ((uint16_t)0x8000) /*!< XIN1 Bit 7 */ 2247 2248 /****************************************************************************** 2249 * CAPTIO Bits 2250 ******************************************************************************/ 2251 /* CAPTIO_CTL[PISEL] Bits */ 2252 #define CAPTIO_CTL_PISEL_OFS ( 1) /*!< CAPTIOPISELx Bit Offset */ 2253 #define CAPTIO_CTL_PISEL_MASK ((uint16_t)0x000E) /*!< CAPTIOPISELx Bit Mask */ 2254 #define CAPTIO_CTL_PISEL0 ((uint16_t)0x0002) /*!< PISEL Bit 0 */ 2255 #define CAPTIO_CTL_PISEL1 ((uint16_t)0x0004) /*!< PISEL Bit 1 */ 2256 #define CAPTIO_CTL_PISEL2 ((uint16_t)0x0008) /*!< PISEL Bit 2 */ 2257 #define CAPTIO_CTL_PISEL_0 ((uint16_t)0x0000) /*!< Px.0 */ 2258 #define CAPTIO_CTL_PISEL_1 ((uint16_t)0x0002) /*!< Px.1 */ 2259 #define CAPTIO_CTL_PISEL_2 ((uint16_t)0x0004) /*!< Px.2 */ 2260 #define CAPTIO_CTL_PISEL_3 ((uint16_t)0x0006) /*!< Px.3 */ 2261 #define CAPTIO_CTL_PISEL_4 ((uint16_t)0x0008) /*!< Px.4 */ 2262 #define CAPTIO_CTL_PISEL_5 ((uint16_t)0x000A) /*!< Px.5 */ 2263 #define CAPTIO_CTL_PISEL_6 ((uint16_t)0x000C) /*!< Px.6 */ 2264 #define CAPTIO_CTL_PISEL_7 ((uint16_t)0x000E) /*!< Px.7 */ 2265 /* CAPTIO_CTL[POSEL] Bits */ 2266 #define CAPTIO_CTL_POSEL_OFS ( 4) /*!< CAPTIOPOSELx Bit Offset */ 2267 #define CAPTIO_CTL_POSEL_MASK ((uint16_t)0x00F0) /*!< CAPTIOPOSELx Bit Mask */ 2268 #define CAPTIO_CTL_POSEL0 ((uint16_t)0x0010) /*!< POSEL Bit 0 */ 2269 #define CAPTIO_CTL_POSEL1 ((uint16_t)0x0020) /*!< POSEL Bit 1 */ 2270 #define CAPTIO_CTL_POSEL2 ((uint16_t)0x0040) /*!< POSEL Bit 2 */ 2271 #define CAPTIO_CTL_POSEL3 ((uint16_t)0x0080) /*!< POSEL Bit 3 */ 2272 #define CAPTIO_CTL_POSEL_0 ((uint16_t)0x0000) /*!< Px = PJ */ 2273 #define CAPTIO_CTL_POSEL_1 ((uint16_t)0x0010) /*!< Px = P1 */ 2274 #define CAPTIO_CTL_POSEL_2 ((uint16_t)0x0020) /*!< Px = P2 */ 2275 #define CAPTIO_CTL_POSEL_3 ((uint16_t)0x0030) /*!< Px = P3 */ 2276 #define CAPTIO_CTL_POSEL_4 ((uint16_t)0x0040) /*!< Px = P4 */ 2277 #define CAPTIO_CTL_POSEL_5 ((uint16_t)0x0050) /*!< Px = P5 */ 2278 #define CAPTIO_CTL_POSEL_6 ((uint16_t)0x0060) /*!< Px = P6 */ 2279 #define CAPTIO_CTL_POSEL_7 ((uint16_t)0x0070) /*!< Px = P7 */ 2280 #define CAPTIO_CTL_POSEL_8 ((uint16_t)0x0080) /*!< Px = P8 */ 2281 #define CAPTIO_CTL_POSEL_9 ((uint16_t)0x0090) /*!< Px = P9 */ 2282 #define CAPTIO_CTL_POSEL_10 ((uint16_t)0x00A0) /*!< Px = P10 */ 2283 #define CAPTIO_CTL_POSEL_11 ((uint16_t)0x00B0) /*!< Px = P11 */ 2284 #define CAPTIO_CTL_POSEL_12 ((uint16_t)0x00C0) /*!< Px = P12 */ 2285 #define CAPTIO_CTL_POSEL_13 ((uint16_t)0x00D0) /*!< Px = P13 */ 2286 #define CAPTIO_CTL_POSEL_14 ((uint16_t)0x00E0) /*!< Px = P14 */ 2287 #define CAPTIO_CTL_POSEL_15 ((uint16_t)0x00F0) /*!< Px = P15 */ 2288 #define CAPTIO_CTL_POSEL__PJ ((uint16_t)0x0000) /*!< Px = PJ */ 2289 #define CAPTIO_CTL_POSEL__P1 ((uint16_t)0x0010) /*!< Px = P1 */ 2290 #define CAPTIO_CTL_POSEL__P2 ((uint16_t)0x0020) /*!< Px = P2 */ 2291 #define CAPTIO_CTL_POSEL__P3 ((uint16_t)0x0030) /*!< Px = P3 */ 2292 #define CAPTIO_CTL_POSEL__P4 ((uint16_t)0x0040) /*!< Px = P4 */ 2293 #define CAPTIO_CTL_POSEL__P5 ((uint16_t)0x0050) /*!< Px = P5 */ 2294 #define CAPTIO_CTL_POSEL__P6 ((uint16_t)0x0060) /*!< Px = P6 */ 2295 #define CAPTIO_CTL_POSEL__P7 ((uint16_t)0x0070) /*!< Px = P7 */ 2296 #define CAPTIO_CTL_POSEL__P8 ((uint16_t)0x0080) /*!< Px = P8 */ 2297 #define CAPTIO_CTL_POSEL__P9 ((uint16_t)0x0090) /*!< Px = P9 */ 2298 #define CAPTIO_CTL_POSEL__P10 ((uint16_t)0x00A0) /*!< Px = P10 */ 2299 #define CAPTIO_CTL_POSEL__P11 ((uint16_t)0x00B0) /*!< Px = P11 */ 2300 #define CAPTIO_CTL_POSEL__P12 ((uint16_t)0x00C0) /*!< Px = P12 */ 2301 #define CAPTIO_CTL_POSEL__P13 ((uint16_t)0x00D0) /*!< Px = P13 */ 2302 #define CAPTIO_CTL_POSEL__P14 ((uint16_t)0x00E0) /*!< Px = P14 */ 2303 #define CAPTIO_CTL_POSEL__P15 ((uint16_t)0x00F0) /*!< Px = P15 */ 2304 /* CAPTIO_CTL[EN] Bits */ 2305 #define CAPTIO_CTL_EN_OFS ( 8) /*!< CAPTIOEN Bit Offset */ 2306 #define CAPTIO_CTL_EN ((uint16_t)0x0100) /*!< Capacitive Touch IO enable */ 2307 /* CAPTIO_CTL[STATE] Bits */ 2308 #define CAPTIO_CTL_STATE_OFS ( 9) /*!< CAPTIOSTATE Bit Offset */ 2309 #define CAPTIO_CTL_STATE ((uint16_t)0x0200) /*!< Capacitive Touch IO state */ 2310 2311 /****************************************************************************** 2312 * COMP_E Bits 2313 ******************************************************************************/ 2314 /* COMP_E_CTL0[IPSEL] Bits */ 2315 #define COMP_E_CTL0_IPSEL_OFS ( 0) /*!< CEIPSEL Bit Offset */ 2316 #define COMP_E_CTL0_IPSEL_MASK ((uint16_t)0x000F) /*!< CEIPSEL Bit Mask */ 2317 #define COMP_E_CTL0_IPSEL0 ((uint16_t)0x0001) /*!< IPSEL Bit 0 */ 2318 #define COMP_E_CTL0_IPSEL1 ((uint16_t)0x0002) /*!< IPSEL Bit 1 */ 2319 #define COMP_E_CTL0_IPSEL2 ((uint16_t)0x0004) /*!< IPSEL Bit 2 */ 2320 #define COMP_E_CTL0_IPSEL3 ((uint16_t)0x0008) /*!< IPSEL Bit 3 */ 2321 #define COMP_E_CTL0_IPSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ 2322 #define COMP_E_CTL0_IPSEL_1 ((uint16_t)0x0001) /*!< Channel 1 selected */ 2323 #define COMP_E_CTL0_IPSEL_2 ((uint16_t)0x0002) /*!< Channel 2 selected */ 2324 #define COMP_E_CTL0_IPSEL_3 ((uint16_t)0x0003) /*!< Channel 3 selected */ 2325 #define COMP_E_CTL0_IPSEL_4 ((uint16_t)0x0004) /*!< Channel 4 selected */ 2326 #define COMP_E_CTL0_IPSEL_5 ((uint16_t)0x0005) /*!< Channel 5 selected */ 2327 #define COMP_E_CTL0_IPSEL_6 ((uint16_t)0x0006) /*!< Channel 6 selected */ 2328 #define COMP_E_CTL0_IPSEL_7 ((uint16_t)0x0007) /*!< Channel 7 selected */ 2329 #define COMP_E_CTL0_IPSEL_8 ((uint16_t)0x0008) /*!< Channel 8 selected */ 2330 #define COMP_E_CTL0_IPSEL_9 ((uint16_t)0x0009) /*!< Channel 9 selected */ 2331 #define COMP_E_CTL0_IPSEL_10 ((uint16_t)0x000A) /*!< Channel 10 selected */ 2332 #define COMP_E_CTL0_IPSEL_11 ((uint16_t)0x000B) /*!< Channel 11 selected */ 2333 #define COMP_E_CTL0_IPSEL_12 ((uint16_t)0x000C) /*!< Channel 12 selected */ 2334 #define COMP_E_CTL0_IPSEL_13 ((uint16_t)0x000D) /*!< Channel 13 selected */ 2335 #define COMP_E_CTL0_IPSEL_14 ((uint16_t)0x000E) /*!< Channel 14 selected */ 2336 #define COMP_E_CTL0_IPSEL_15 ((uint16_t)0x000F) /*!< Channel 15 selected */ 2337 /* COMP_E_CTL0[IPEN] Bits */ 2338 #define COMP_E_CTL0_IPEN_OFS ( 7) /*!< CEIPEN Bit Offset */ 2339 #define COMP_E_CTL0_IPEN ((uint16_t)0x0080) /*!< Channel input enable for the V+ terminal */ 2340 /* COMP_E_CTL0[IMSEL] Bits */ 2341 #define COMP_E_CTL0_IMSEL_OFS ( 8) /*!< CEIMSEL Bit Offset */ 2342 #define COMP_E_CTL0_IMSEL_MASK ((uint16_t)0x0F00) /*!< CEIMSEL Bit Mask */ 2343 #define COMP_E_CTL0_IMSEL0 ((uint16_t)0x0100) /*!< IMSEL Bit 0 */ 2344 #define COMP_E_CTL0_IMSEL1 ((uint16_t)0x0200) /*!< IMSEL Bit 1 */ 2345 #define COMP_E_CTL0_IMSEL2 ((uint16_t)0x0400) /*!< IMSEL Bit 2 */ 2346 #define COMP_E_CTL0_IMSEL3 ((uint16_t)0x0800) /*!< IMSEL Bit 3 */ 2347 #define COMP_E_CTL0_IMSEL_0 ((uint16_t)0x0000) /*!< Channel 0 selected */ 2348 #define COMP_E_CTL0_IMSEL_1 ((uint16_t)0x0100) /*!< Channel 1 selected */ 2349 #define COMP_E_CTL0_IMSEL_2 ((uint16_t)0x0200) /*!< Channel 2 selected */ 2350 #define COMP_E_CTL0_IMSEL_3 ((uint16_t)0x0300) /*!< Channel 3 selected */ 2351 #define COMP_E_CTL0_IMSEL_4 ((uint16_t)0x0400) /*!< Channel 4 selected */ 2352 #define COMP_E_CTL0_IMSEL_5 ((uint16_t)0x0500) /*!< Channel 5 selected */ 2353 #define COMP_E_CTL0_IMSEL_6 ((uint16_t)0x0600) /*!< Channel 6 selected */ 2354 #define COMP_E_CTL0_IMSEL_7 ((uint16_t)0x0700) /*!< Channel 7 selected */ 2355 #define COMP_E_CTL0_IMSEL_8 ((uint16_t)0x0800) /*!< Channel 8 selected */ 2356 #define COMP_E_CTL0_IMSEL_9 ((uint16_t)0x0900) /*!< Channel 9 selected */ 2357 #define COMP_E_CTL0_IMSEL_10 ((uint16_t)0x0A00) /*!< Channel 10 selected */ 2358 #define COMP_E_CTL0_IMSEL_11 ((uint16_t)0x0B00) /*!< Channel 11 selected */ 2359 #define COMP_E_CTL0_IMSEL_12 ((uint16_t)0x0C00) /*!< Channel 12 selected */ 2360 #define COMP_E_CTL0_IMSEL_13 ((uint16_t)0x0D00) /*!< Channel 13 selected */ 2361 #define COMP_E_CTL0_IMSEL_14 ((uint16_t)0x0E00) /*!< Channel 14 selected */ 2362 #define COMP_E_CTL0_IMSEL_15 ((uint16_t)0x0F00) /*!< Channel 15 selected */ 2363 /* COMP_E_CTL0[IMEN] Bits */ 2364 #define COMP_E_CTL0_IMEN_OFS (15) /*!< CEIMEN Bit Offset */ 2365 #define COMP_E_CTL0_IMEN ((uint16_t)0x8000) /*!< Channel input enable for the - terminal */ 2366 /* COMP_E_CTL1[OUT] Bits */ 2367 #define COMP_E_CTL1_OUT_OFS ( 0) /*!< CEOUT Bit Offset */ 2368 #define COMP_E_CTL1_OUT ((uint16_t)0x0001) /*!< Comparator output value */ 2369 /* COMP_E_CTL1[OUTPOL] Bits */ 2370 #define COMP_E_CTL1_OUTPOL_OFS ( 1) /*!< CEOUTPOL Bit Offset */ 2371 #define COMP_E_CTL1_OUTPOL ((uint16_t)0x0002) /*!< Comparator output polarity */ 2372 /* COMP_E_CTL1[F] Bits */ 2373 #define COMP_E_CTL1_F_OFS ( 2) /*!< CEF Bit Offset */ 2374 #define COMP_E_CTL1_F ((uint16_t)0x0004) /*!< Comparator output filter */ 2375 /* COMP_E_CTL1[IES] Bits */ 2376 #define COMP_E_CTL1_IES_OFS ( 3) /*!< CEIES Bit Offset */ 2377 #define COMP_E_CTL1_IES ((uint16_t)0x0008) /*!< Interrupt edge select for CEIIFG and CEIFG */ 2378 /* COMP_E_CTL1[SHORT] Bits */ 2379 #define COMP_E_CTL1_SHORT_OFS ( 4) /*!< CESHORT Bit Offset */ 2380 #define COMP_E_CTL1_SHORT ((uint16_t)0x0010) /*!< Input short */ 2381 /* COMP_E_CTL1[EX] Bits */ 2382 #define COMP_E_CTL1_EX_OFS ( 5) /*!< CEEX Bit Offset */ 2383 #define COMP_E_CTL1_EX ((uint16_t)0x0020) /*!< Exchange */ 2384 /* COMP_E_CTL1[FDLY] Bits */ 2385 #define COMP_E_CTL1_FDLY_OFS ( 6) /*!< CEFDLY Bit Offset */ 2386 #define COMP_E_CTL1_FDLY_MASK ((uint16_t)0x00C0) /*!< CEFDLY Bit Mask */ 2387 #define COMP_E_CTL1_FDLY0 ((uint16_t)0x0040) /*!< FDLY Bit 0 */ 2388 #define COMP_E_CTL1_FDLY1 ((uint16_t)0x0080) /*!< FDLY Bit 1 */ 2389 #define COMP_E_CTL1_FDLY_0 ((uint16_t)0x0000) /*!< Typical filter delay of TBD (450) ns */ 2390 #define COMP_E_CTL1_FDLY_1 ((uint16_t)0x0040) /*!< Typical filter delay of TBD (900) ns */ 2391 #define COMP_E_CTL1_FDLY_2 ((uint16_t)0x0080) /*!< Typical filter delay of TBD (1800) ns */ 2392 #define COMP_E_CTL1_FDLY_3 ((uint16_t)0x00C0) /*!< Typical filter delay of TBD (3600) ns */ 2393 /* COMP_E_CTL1[PWRMD] Bits */ 2394 #define COMP_E_CTL1_PWRMD_OFS ( 8) /*!< CEPWRMD Bit Offset */ 2395 #define COMP_E_CTL1_PWRMD_MASK ((uint16_t)0x0300) /*!< CEPWRMD Bit Mask */ 2396 #define COMP_E_CTL1_PWRMD0 ((uint16_t)0x0100) /*!< PWRMD Bit 0 */ 2397 #define COMP_E_CTL1_PWRMD1 ((uint16_t)0x0200) /*!< PWRMD Bit 1 */ 2398 #define COMP_E_CTL1_PWRMD_0 ((uint16_t)0x0000) /*!< High-speed mode */ 2399 #define COMP_E_CTL1_PWRMD_1 ((uint16_t)0x0100) /*!< Normal mode */ 2400 #define COMP_E_CTL1_PWRMD_2 ((uint16_t)0x0200) /*!< Ultra-low power mode */ 2401 /* COMP_E_CTL1[ON] Bits */ 2402 #define COMP_E_CTL1_ON_OFS (10) /*!< CEON Bit Offset */ 2403 #define COMP_E_CTL1_ON ((uint16_t)0x0400) /*!< Comparator On */ 2404 /* COMP_E_CTL1[MRVL] Bits */ 2405 #define COMP_E_CTL1_MRVL_OFS (11) /*!< CEMRVL Bit Offset */ 2406 #define COMP_E_CTL1_MRVL ((uint16_t)0x0800) /*!< This bit is valid of CEMRVS is set to 1 */ 2407 /* COMP_E_CTL1[MRVS] Bits */ 2408 #define COMP_E_CTL1_MRVS_OFS (12) /*!< CEMRVS Bit Offset */ 2409 #define COMP_E_CTL1_MRVS ((uint16_t)0x1000) 2410 /* COMP_E_CTL2[REF0] Bits */ 2411 #define COMP_E_CTL2_REF0_OFS ( 0) /*!< CEREF0 Bit Offset */ 2412 #define COMP_E_CTL2_REF0_MASK ((uint16_t)0x001F) /*!< CEREF0 Bit Mask */ 2413 #define COMP_E_CTL2_REF00 ((uint16_t)0x0001) /*!< REF0 Bit 0 */ 2414 #define COMP_E_CTL2_REF01 ((uint16_t)0x0002) /*!< REF0 Bit 1 */ 2415 #define COMP_E_CTL2_REF02 ((uint16_t)0x0004) /*!< REF0 Bit 2 */ 2416 #define COMP_E_CTL2_REF03 ((uint16_t)0x0008) /*!< REF0 Bit 3 */ 2417 #define COMP_E_CTL2_REF04 ((uint16_t)0x0010) /*!< REF0 Bit 4 */ 2418 #define COMP_E_CTL2_REF0_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ 2419 #define COMP_E_CTL2_REF0_1 ((uint16_t)0x0001) /*!< Reference resistor tap for setting 1. */ 2420 #define COMP_E_CTL2_REF0_2 ((uint16_t)0x0002) /*!< Reference resistor tap for setting 2. */ 2421 #define COMP_E_CTL2_REF0_3 ((uint16_t)0x0003) /*!< Reference resistor tap for setting 3. */ 2422 #define COMP_E_CTL2_REF0_4 ((uint16_t)0x0004) /*!< Reference resistor tap for setting 4. */ 2423 #define COMP_E_CTL2_REF0_5 ((uint16_t)0x0005) /*!< Reference resistor tap for setting 5. */ 2424 #define COMP_E_CTL2_REF0_6 ((uint16_t)0x0006) /*!< Reference resistor tap for setting 6. */ 2425 #define COMP_E_CTL2_REF0_7 ((uint16_t)0x0007) /*!< Reference resistor tap for setting 7. */ 2426 #define COMP_E_CTL2_REF0_8 ((uint16_t)0x0008) /*!< Reference resistor tap for setting 8. */ 2427 #define COMP_E_CTL2_REF0_9 ((uint16_t)0x0009) /*!< Reference resistor tap for setting 9. */ 2428 #define COMP_E_CTL2_REF0_10 ((uint16_t)0x000A) /*!< Reference resistor tap for setting 10. */ 2429 #define COMP_E_CTL2_REF0_11 ((uint16_t)0x000B) /*!< Reference resistor tap for setting 11. */ 2430 #define COMP_E_CTL2_REF0_12 ((uint16_t)0x000C) /*!< Reference resistor tap for setting 12. */ 2431 #define COMP_E_CTL2_REF0_13 ((uint16_t)0x000D) /*!< Reference resistor tap for setting 13. */ 2432 #define COMP_E_CTL2_REF0_14 ((uint16_t)0x000E) /*!< Reference resistor tap for setting 14. */ 2433 #define COMP_E_CTL2_REF0_15 ((uint16_t)0x000F) /*!< Reference resistor tap for setting 15. */ 2434 #define COMP_E_CTL2_REF0_16 ((uint16_t)0x0010) /*!< Reference resistor tap for setting 16. */ 2435 #define COMP_E_CTL2_REF0_17 ((uint16_t)0x0011) /*!< Reference resistor tap for setting 17. */ 2436 #define COMP_E_CTL2_REF0_18 ((uint16_t)0x0012) /*!< Reference resistor tap for setting 18. */ 2437 #define COMP_E_CTL2_REF0_19 ((uint16_t)0x0013) /*!< Reference resistor tap for setting 19. */ 2438 #define COMP_E_CTL2_REF0_20 ((uint16_t)0x0014) /*!< Reference resistor tap for setting 20. */ 2439 #define COMP_E_CTL2_REF0_21 ((uint16_t)0x0015) /*!< Reference resistor tap for setting 21. */ 2440 #define COMP_E_CTL2_REF0_22 ((uint16_t)0x0016) /*!< Reference resistor tap for setting 22. */ 2441 #define COMP_E_CTL2_REF0_23 ((uint16_t)0x0017) /*!< Reference resistor tap for setting 23. */ 2442 #define COMP_E_CTL2_REF0_24 ((uint16_t)0x0018) /*!< Reference resistor tap for setting 24. */ 2443 #define COMP_E_CTL2_REF0_25 ((uint16_t)0x0019) /*!< Reference resistor tap for setting 25. */ 2444 #define COMP_E_CTL2_REF0_26 ((uint16_t)0x001A) /*!< Reference resistor tap for setting 26. */ 2445 #define COMP_E_CTL2_REF0_27 ((uint16_t)0x001B) /*!< Reference resistor tap for setting 27. */ 2446 #define COMP_E_CTL2_REF0_28 ((uint16_t)0x001C) /*!< Reference resistor tap for setting 28. */ 2447 #define COMP_E_CTL2_REF0_29 ((uint16_t)0x001D) /*!< Reference resistor tap for setting 29. */ 2448 #define COMP_E_CTL2_REF0_30 ((uint16_t)0x001E) /*!< Reference resistor tap for setting 30. */ 2449 #define COMP_E_CTL2_REF0_31 ((uint16_t)0x001F) /*!< Reference resistor tap for setting 31. */ 2450 /* COMP_E_CTL2[RSEL] Bits */ 2451 #define COMP_E_CTL2_RSEL_OFS ( 5) /*!< CERSEL Bit Offset */ 2452 #define COMP_E_CTL2_RSEL ((uint16_t)0x0020) /*!< Reference select */ 2453 /* COMP_E_CTL2[RS] Bits */ 2454 #define COMP_E_CTL2_RS_OFS ( 6) /*!< CERS Bit Offset */ 2455 #define COMP_E_CTL2_RS_MASK ((uint16_t)0x00C0) /*!< CERS Bit Mask */ 2456 #define COMP_E_CTL2_RS0 ((uint16_t)0x0040) /*!< RS Bit 0 */ 2457 #define COMP_E_CTL2_RS1 ((uint16_t)0x0080) /*!< RS Bit 1 */ 2458 #define COMP_E_CTL2_RS_0 ((uint16_t)0x0000) /*!< No current is drawn by the reference circuitry */ 2459 #define COMP_E_CTL2_RS_1 ((uint16_t)0x0040) /*!< VCC applied to the resistor ladder */ 2460 #define COMP_E_CTL2_RS_2 ((uint16_t)0x0080) /*!< Shared reference voltage applied to the resistor ladder */ 2461 #define COMP_E_CTL2_RS_3 ((uint16_t)0x00C0) /*!< Shared reference voltage supplied to V(CREF). Resistor ladder is off */ 2462 /* COMP_E_CTL2[REF1] Bits */ 2463 #define COMP_E_CTL2_REF1_OFS ( 8) /*!< CEREF1 Bit Offset */ 2464 #define COMP_E_CTL2_REF1_MASK ((uint16_t)0x1F00) /*!< CEREF1 Bit Mask */ 2465 #define COMP_E_CTL2_REF10 ((uint16_t)0x0100) /*!< REF1 Bit 0 */ 2466 #define COMP_E_CTL2_REF11 ((uint16_t)0x0200) /*!< REF1 Bit 1 */ 2467 #define COMP_E_CTL2_REF12 ((uint16_t)0x0400) /*!< REF1 Bit 2 */ 2468 #define COMP_E_CTL2_REF13 ((uint16_t)0x0800) /*!< REF1 Bit 3 */ 2469 #define COMP_E_CTL2_REF14 ((uint16_t)0x1000) /*!< REF1 Bit 4 */ 2470 #define COMP_E_CTL2_REF1_0 ((uint16_t)0x0000) /*!< Reference resistor tap for setting 0. */ 2471 #define COMP_E_CTL2_REF1_1 ((uint16_t)0x0100) /*!< Reference resistor tap for setting 1. */ 2472 #define COMP_E_CTL2_REF1_2 ((uint16_t)0x0200) /*!< Reference resistor tap for setting 2. */ 2473 #define COMP_E_CTL2_REF1_3 ((uint16_t)0x0300) /*!< Reference resistor tap for setting 3. */ 2474 #define COMP_E_CTL2_REF1_4 ((uint16_t)0x0400) /*!< Reference resistor tap for setting 4. */ 2475 #define COMP_E_CTL2_REF1_5 ((uint16_t)0x0500) /*!< Reference resistor tap for setting 5. */ 2476 #define COMP_E_CTL2_REF1_6 ((uint16_t)0x0600) /*!< Reference resistor tap for setting 6. */ 2477 #define COMP_E_CTL2_REF1_7 ((uint16_t)0x0700) /*!< Reference resistor tap for setting 7. */ 2478 #define COMP_E_CTL2_REF1_8 ((uint16_t)0x0800) /*!< Reference resistor tap for setting 8. */ 2479 #define COMP_E_CTL2_REF1_9 ((uint16_t)0x0900) /*!< Reference resistor tap for setting 9. */ 2480 #define COMP_E_CTL2_REF1_10 ((uint16_t)0x0A00) /*!< Reference resistor tap for setting 10. */ 2481 #define COMP_E_CTL2_REF1_11 ((uint16_t)0x0B00) /*!< Reference resistor tap for setting 11. */ 2482 #define COMP_E_CTL2_REF1_12 ((uint16_t)0x0C00) /*!< Reference resistor tap for setting 12. */ 2483 #define COMP_E_CTL2_REF1_13 ((uint16_t)0x0D00) /*!< Reference resistor tap for setting 13. */ 2484 #define COMP_E_CTL2_REF1_14 ((uint16_t)0x0E00) /*!< Reference resistor tap for setting 14. */ 2485 #define COMP_E_CTL2_REF1_15 ((uint16_t)0x0F00) /*!< Reference resistor tap for setting 15. */ 2486 #define COMP_E_CTL2_REF1_16 ((uint16_t)0x1000) /*!< Reference resistor tap for setting 16. */ 2487 #define COMP_E_CTL2_REF1_17 ((uint16_t)0x1100) /*!< Reference resistor tap for setting 17. */ 2488 #define COMP_E_CTL2_REF1_18 ((uint16_t)0x1200) /*!< Reference resistor tap for setting 18. */ 2489 #define COMP_E_CTL2_REF1_19 ((uint16_t)0x1300) /*!< Reference resistor tap for setting 19. */ 2490 #define COMP_E_CTL2_REF1_20 ((uint16_t)0x1400) /*!< Reference resistor tap for setting 20. */ 2491 #define COMP_E_CTL2_REF1_21 ((uint16_t)0x1500) /*!< Reference resistor tap for setting 21. */ 2492 #define COMP_E_CTL2_REF1_22 ((uint16_t)0x1600) /*!< Reference resistor tap for setting 22. */ 2493 #define COMP_E_CTL2_REF1_23 ((uint16_t)0x1700) /*!< Reference resistor tap for setting 23. */ 2494 #define COMP_E_CTL2_REF1_24 ((uint16_t)0x1800) /*!< Reference resistor tap for setting 24. */ 2495 #define COMP_E_CTL2_REF1_25 ((uint16_t)0x1900) /*!< Reference resistor tap for setting 25. */ 2496 #define COMP_E_CTL2_REF1_26 ((uint16_t)0x1A00) /*!< Reference resistor tap for setting 26. */ 2497 #define COMP_E_CTL2_REF1_27 ((uint16_t)0x1B00) /*!< Reference resistor tap for setting 27. */ 2498 #define COMP_E_CTL2_REF1_28 ((uint16_t)0x1C00) /*!< Reference resistor tap for setting 28. */ 2499 #define COMP_E_CTL2_REF1_29 ((uint16_t)0x1D00) /*!< Reference resistor tap for setting 29. */ 2500 #define COMP_E_CTL2_REF1_30 ((uint16_t)0x1E00) /*!< Reference resistor tap for setting 30. */ 2501 #define COMP_E_CTL2_REF1_31 ((uint16_t)0x1F00) /*!< Reference resistor tap for setting 31. */ 2502 /* COMP_E_CTL2[REFL] Bits */ 2503 #define COMP_E_CTL2_REFL_OFS (13) /*!< CEREFL Bit Offset */ 2504 #define COMP_E_CTL2_REFL_MASK ((uint16_t)0x6000) /*!< CEREFL Bit Mask */ 2505 #define COMP_E_CTL2_REFL0 ((uint16_t)0x2000) /*!< REFL Bit 0 */ 2506 #define COMP_E_CTL2_REFL1 ((uint16_t)0x4000) /*!< REFL Bit 1 */ 2507 #define COMP_E_CTL2_CEREFL_0 ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ 2508 #define COMP_E_CTL2_CEREFL_1 ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ 2509 #define COMP_E_CTL2_CEREFL_2 ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ 2510 #define COMP_E_CTL2_CEREFL_3 ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ 2511 #define COMP_E_CTL2_REFL__OFF ((uint16_t)0x0000) /*!< Reference amplifier is disabled. No reference voltage is requested */ 2512 #define COMP_E_CTL2_REFL__1P2V ((uint16_t)0x2000) /*!< 1.2 V is selected as shared reference voltage input */ 2513 #define COMP_E_CTL2_REFL__2P0V ((uint16_t)0x4000) /*!< 2.0 V is selected as shared reference voltage input */ 2514 #define COMP_E_CTL2_REFL__2P5V ((uint16_t)0x6000) /*!< 2.5 V is selected as shared reference voltage input */ 2515 /* COMP_E_CTL2[REFACC] Bits */ 2516 #define COMP_E_CTL2_REFACC_OFS (15) /*!< CEREFACC Bit Offset */ 2517 #define COMP_E_CTL2_REFACC ((uint16_t)0x8000) /*!< Reference accuracy */ 2518 /* COMP_E_CTL3[PD0] Bits */ 2519 #define COMP_E_CTL3_PD0_OFS ( 0) /*!< CEPD0 Bit Offset */ 2520 #define COMP_E_CTL3_PD0 ((uint16_t)0x0001) /*!< Port disable */ 2521 /* COMP_E_CTL3[PD1] Bits */ 2522 #define COMP_E_CTL3_PD1_OFS ( 1) /*!< CEPD1 Bit Offset */ 2523 #define COMP_E_CTL3_PD1 ((uint16_t)0x0002) /*!< Port disable */ 2524 /* COMP_E_CTL3[PD2] Bits */ 2525 #define COMP_E_CTL3_PD2_OFS ( 2) /*!< CEPD2 Bit Offset */ 2526 #define COMP_E_CTL3_PD2 ((uint16_t)0x0004) /*!< Port disable */ 2527 /* COMP_E_CTL3[PD3] Bits */ 2528 #define COMP_E_CTL3_PD3_OFS ( 3) /*!< CEPD3 Bit Offset */ 2529 #define COMP_E_CTL3_PD3 ((uint16_t)0x0008) /*!< Port disable */ 2530 /* COMP_E_CTL3[PD4] Bits */ 2531 #define COMP_E_CTL3_PD4_OFS ( 4) /*!< CEPD4 Bit Offset */ 2532 #define COMP_E_CTL3_PD4 ((uint16_t)0x0010) /*!< Port disable */ 2533 /* COMP_E_CTL3[PD5] Bits */ 2534 #define COMP_E_CTL3_PD5_OFS ( 5) /*!< CEPD5 Bit Offset */ 2535 #define COMP_E_CTL3_PD5 ((uint16_t)0x0020) /*!< Port disable */ 2536 /* COMP_E_CTL3[PD6] Bits */ 2537 #define COMP_E_CTL3_PD6_OFS ( 6) /*!< CEPD6 Bit Offset */ 2538 #define COMP_E_CTL3_PD6 ((uint16_t)0x0040) /*!< Port disable */ 2539 /* COMP_E_CTL3[PD7] Bits */ 2540 #define COMP_E_CTL3_PD7_OFS ( 7) /*!< CEPD7 Bit Offset */ 2541 #define COMP_E_CTL3_PD7 ((uint16_t)0x0080) /*!< Port disable */ 2542 /* COMP_E_CTL3[PD8] Bits */ 2543 #define COMP_E_CTL3_PD8_OFS ( 8) /*!< CEPD8 Bit Offset */ 2544 #define COMP_E_CTL3_PD8 ((uint16_t)0x0100) /*!< Port disable */ 2545 /* COMP_E_CTL3[PD9] Bits */ 2546 #define COMP_E_CTL3_PD9_OFS ( 9) /*!< CEPD9 Bit Offset */ 2547 #define COMP_E_CTL3_PD9 ((uint16_t)0x0200) /*!< Port disable */ 2548 /* COMP_E_CTL3[PD10] Bits */ 2549 #define COMP_E_CTL3_PD10_OFS (10) /*!< CEPD10 Bit Offset */ 2550 #define COMP_E_CTL3_PD10 ((uint16_t)0x0400) /*!< Port disable */ 2551 /* COMP_E_CTL3[PD11] Bits */ 2552 #define COMP_E_CTL3_PD11_OFS (11) /*!< CEPD11 Bit Offset */ 2553 #define COMP_E_CTL3_PD11 ((uint16_t)0x0800) /*!< Port disable */ 2554 /* COMP_E_CTL3[PD12] Bits */ 2555 #define COMP_E_CTL3_PD12_OFS (12) /*!< CEPD12 Bit Offset */ 2556 #define COMP_E_CTL3_PD12 ((uint16_t)0x1000) /*!< Port disable */ 2557 /* COMP_E_CTL3[PD13] Bits */ 2558 #define COMP_E_CTL3_PD13_OFS (13) /*!< CEPD13 Bit Offset */ 2559 #define COMP_E_CTL3_PD13 ((uint16_t)0x2000) /*!< Port disable */ 2560 /* COMP_E_CTL3[PD14] Bits */ 2561 #define COMP_E_CTL3_PD14_OFS (14) /*!< CEPD14 Bit Offset */ 2562 #define COMP_E_CTL3_PD14 ((uint16_t)0x4000) /*!< Port disable */ 2563 /* COMP_E_CTL3[PD15] Bits */ 2564 #define COMP_E_CTL3_PD15_OFS (15) /*!< CEPD15 Bit Offset */ 2565 #define COMP_E_CTL3_PD15 ((uint16_t)0x8000) /*!< Port disable */ 2566 /* COMP_E_INT[IFG] Bits */ 2567 #define COMP_E_INT_IFG_OFS ( 0) /*!< CEIFG Bit Offset */ 2568 #define COMP_E_INT_IFG ((uint16_t)0x0001) /*!< Comparator output interrupt flag */ 2569 /* COMP_E_INT[IIFG] Bits */ 2570 #define COMP_E_INT_IIFG_OFS ( 1) /*!< CEIIFG Bit Offset */ 2571 #define COMP_E_INT_IIFG ((uint16_t)0x0002) /*!< Comparator output inverted interrupt flag */ 2572 /* COMP_E_INT[RDYIFG] Bits */ 2573 #define COMP_E_INT_RDYIFG_OFS ( 4) /*!< CERDYIFG Bit Offset */ 2574 #define COMP_E_INT_RDYIFG ((uint16_t)0x0010) /*!< Comparator ready interrupt flag */ 2575 /* COMP_E_INT[IE] Bits */ 2576 #define COMP_E_INT_IE_OFS ( 8) /*!< CEIE Bit Offset */ 2577 #define COMP_E_INT_IE ((uint16_t)0x0100) /*!< Comparator output interrupt enable */ 2578 /* COMP_E_INT[IIE] Bits */ 2579 #define COMP_E_INT_IIE_OFS ( 9) /*!< CEIIE Bit Offset */ 2580 #define COMP_E_INT_IIE ((uint16_t)0x0200) /*!< Comparator output interrupt enable inverted polarity */ 2581 /* COMP_E_INT[RDYIE] Bits */ 2582 #define COMP_E_INT_RDYIE_OFS (12) /*!< CERDYIE Bit Offset */ 2583 #define COMP_E_INT_RDYIE ((uint16_t)0x1000) /*!< Comparator ready interrupt enable */ 2584 2585 /****************************************************************************** 2586 * COREDEBUG Bits 2587 ******************************************************************************/ 2588 2589 2590 /****************************************************************************** 2591 * CRC32 Bits 2592 ******************************************************************************/ 2593 2594 /****************************************************************************** 2595 * CS Bits 2596 ******************************************************************************/ 2597 /* CS_KEY[KEY] Bits */ 2598 #define CS_KEY_KEY_OFS ( 0) /*!< CSKEY Bit Offset */ 2599 #define CS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< CSKEY Bit Mask */ 2600 /* CS_CTL0[DCOTUNE] Bits */ 2601 #define CS_CTL0_DCOTUNE_OFS ( 0) /*!< DCOTUNE Bit Offset */ 2602 #define CS_CTL0_DCOTUNE_MASK ((uint32_t)0x000003FF) /*!< DCOTUNE Bit Mask */ 2603 /* CS_CTL0[DCORSEL] Bits */ 2604 #define CS_CTL0_DCORSEL_OFS (16) /*!< DCORSEL Bit Offset */ 2605 #define CS_CTL0_DCORSEL_MASK ((uint32_t)0x00070000) /*!< DCORSEL Bit Mask */ 2606 #define CS_CTL0_DCORSEL0 ((uint32_t)0x00010000) /*!< DCORSEL Bit 0 */ 2607 #define CS_CTL0_DCORSEL1 ((uint32_t)0x00020000) /*!< DCORSEL Bit 1 */ 2608 #define CS_CTL0_DCORSEL2 ((uint32_t)0x00040000) /*!< DCORSEL Bit 2 */ 2609 #define CS_CTL0_DCORSEL_0 ((uint32_t)0x00000000) /*!< Nominal DCO Frequency Range (MHz): 1 to 2 */ 2610 #define CS_CTL0_DCORSEL_1 ((uint32_t)0x00010000) /*!< Nominal DCO Frequency Range (MHz): 2 to 4 */ 2611 #define CS_CTL0_DCORSEL_2 ((uint32_t)0x00020000) /*!< Nominal DCO Frequency Range (MHz): 4 to 8 */ 2612 #define CS_CTL0_DCORSEL_3 ((uint32_t)0x00030000) /*!< Nominal DCO Frequency Range (MHz): 8 to 16 */ 2613 #define CS_CTL0_DCORSEL_4 ((uint32_t)0x00040000) /*!< Nominal DCO Frequency Range (MHz): 16 to 32 */ 2614 #define CS_CTL0_DCORSEL_5 ((uint32_t)0x00050000) /*!< Nominal DCO Frequency Range (MHz): 32 to 64 */ 2615 /* CS_CTL0[DCORES] Bits */ 2616 #define CS_CTL0_DCORES_OFS (22) /*!< DCORES Bit Offset */ 2617 #define CS_CTL0_DCORES ((uint32_t)0x00400000) /*!< Enables the DCO external resistor mode */ 2618 /* CS_CTL0[DCOEN] Bits */ 2619 #define CS_CTL0_DCOEN_OFS (23) /*!< DCOEN Bit Offset */ 2620 #define CS_CTL0_DCOEN ((uint32_t)0x00800000) /*!< Enables the DCO oscillator */ 2621 /* CS_CTL1[SELM] Bits */ 2622 #define CS_CTL1_SELM_OFS ( 0) /*!< SELM Bit Offset */ 2623 #define CS_CTL1_SELM_MASK ((uint32_t)0x00000007) /*!< SELM Bit Mask */ 2624 #define CS_CTL1_SELM0 ((uint32_t)0x00000001) /*!< SELM Bit 0 */ 2625 #define CS_CTL1_SELM1 ((uint32_t)0x00000002) /*!< SELM Bit 1 */ 2626 #define CS_CTL1_SELM2 ((uint32_t)0x00000004) /*!< SELM Bit 2 */ 2627 #define CS_CTL1_SELM_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2628 #define CS_CTL1_SELM_1 ((uint32_t)0x00000001) 2629 #define CS_CTL1_SELM_2 ((uint32_t)0x00000002) 2630 #define CS_CTL1_SELM_3 ((uint32_t)0x00000003) 2631 #define CS_CTL1_SELM_4 ((uint32_t)0x00000004) 2632 #define CS_CTL1_SELM_5 ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ 2633 #define CS_CTL1_SELM_6 ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ 2634 #define CS_CTL1_SELM__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2635 #define CS_CTL1_SELM__VLOCLK ((uint32_t)0x00000001) 2636 #define CS_CTL1_SELM__REFOCLK ((uint32_t)0x00000002) 2637 #define CS_CTL1_SELM__DCOCLK ((uint32_t)0x00000003) 2638 #define CS_CTL1_SELM__MODOSC ((uint32_t)0x00000004) 2639 #define CS_CTL1_SELM__HFXTCLK ((uint32_t)0x00000005) /*!< when HFXT available, otherwise DCOCLK */ 2640 #define CS_CTL1_SELM__HFXT2CLK ((uint32_t)0x00000006) /*!< when HFXT2 available, otherwise DCOCLK */ 2641 /* CS_CTL1[SELS] Bits */ 2642 #define CS_CTL1_SELS_OFS ( 4) /*!< SELS Bit Offset */ 2643 #define CS_CTL1_SELS_MASK ((uint32_t)0x00000070) /*!< SELS Bit Mask */ 2644 #define CS_CTL1_SELS0 ((uint32_t)0x00000010) /*!< SELS Bit 0 */ 2645 #define CS_CTL1_SELS1 ((uint32_t)0x00000020) /*!< SELS Bit 1 */ 2646 #define CS_CTL1_SELS2 ((uint32_t)0x00000040) /*!< SELS Bit 2 */ 2647 #define CS_CTL1_SELS_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2648 #define CS_CTL1_SELS_1 ((uint32_t)0x00000010) 2649 #define CS_CTL1_SELS_2 ((uint32_t)0x00000020) 2650 #define CS_CTL1_SELS_3 ((uint32_t)0x00000030) 2651 #define CS_CTL1_SELS_4 ((uint32_t)0x00000040) 2652 #define CS_CTL1_SELS_5 ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ 2653 #define CS_CTL1_SELS_6 ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ 2654 #define CS_CTL1_SELS__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2655 #define CS_CTL1_SELS__VLOCLK ((uint32_t)0x00000010) 2656 #define CS_CTL1_SELS__REFOCLK ((uint32_t)0x00000020) 2657 #define CS_CTL1_SELS__DCOCLK ((uint32_t)0x00000030) 2658 #define CS_CTL1_SELS__MODOSC ((uint32_t)0x00000040) 2659 #define CS_CTL1_SELS__HFXTCLK ((uint32_t)0x00000050) /*!< when HFXT available, otherwise DCOCLK */ 2660 #define CS_CTL1_SELS__HFXT2CLK ((uint32_t)0x00000060) /*!< when HFXT2 available, otherwise DCOCLK */ 2661 /* CS_CTL1[SELA] Bits */ 2662 #define CS_CTL1_SELA_OFS ( 8) /*!< SELA Bit Offset */ 2663 #define CS_CTL1_SELA_MASK ((uint32_t)0x00000700) /*!< SELA Bit Mask */ 2664 #define CS_CTL1_SELA0 ((uint32_t)0x00000100) /*!< SELA Bit 0 */ 2665 #define CS_CTL1_SELA1 ((uint32_t)0x00000200) /*!< SELA Bit 1 */ 2666 #define CS_CTL1_SELA2 ((uint32_t)0x00000400) /*!< SELA Bit 2 */ 2667 #define CS_CTL1_SELA_0 ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2668 #define CS_CTL1_SELA_1 ((uint32_t)0x00000100) 2669 #define CS_CTL1_SELA_2 ((uint32_t)0x00000200) 2670 #define CS_CTL1_SELA__LFXTCLK ((uint32_t)0x00000000) /*!< when LFXT available, otherwise REFOCLK */ 2671 #define CS_CTL1_SELA__VLOCLK ((uint32_t)0x00000100) 2672 #define CS_CTL1_SELA__REFOCLK ((uint32_t)0x00000200) 2673 /* CS_CTL1[SELB] Bits */ 2674 #define CS_CTL1_SELB_OFS (12) /*!< SELB Bit Offset */ 2675 #define CS_CTL1_SELB ((uint32_t)0x00001000) /*!< Selects the BCLK source */ 2676 /* CS_CTL1[DIVM] Bits */ 2677 #define CS_CTL1_DIVM_OFS (16) /*!< DIVM Bit Offset */ 2678 #define CS_CTL1_DIVM_MASK ((uint32_t)0x00070000) /*!< DIVM Bit Mask */ 2679 #define CS_CTL1_DIVM0 ((uint32_t)0x00010000) /*!< DIVM Bit 0 */ 2680 #define CS_CTL1_DIVM1 ((uint32_t)0x00020000) /*!< DIVM Bit 1 */ 2681 #define CS_CTL1_DIVM2 ((uint32_t)0x00040000) /*!< DIVM Bit 2 */ 2682 #define CS_CTL1_DIVM_0 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ 2683 #define CS_CTL1_DIVM_1 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ 2684 #define CS_CTL1_DIVM_2 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ 2685 #define CS_CTL1_DIVM_3 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ 2686 #define CS_CTL1_DIVM_4 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ 2687 #define CS_CTL1_DIVM_5 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ 2688 #define CS_CTL1_DIVM_6 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ 2689 #define CS_CTL1_DIVM_7 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ 2690 #define CS_CTL1_DIVM__1 ((uint32_t)0x00000000) /*!< f(MCLK)/1 */ 2691 #define CS_CTL1_DIVM__2 ((uint32_t)0x00010000) /*!< f(MCLK)/2 */ 2692 #define CS_CTL1_DIVM__4 ((uint32_t)0x00020000) /*!< f(MCLK)/4 */ 2693 #define CS_CTL1_DIVM__8 ((uint32_t)0x00030000) /*!< f(MCLK)/8 */ 2694 #define CS_CTL1_DIVM__16 ((uint32_t)0x00040000) /*!< f(MCLK)/16 */ 2695 #define CS_CTL1_DIVM__32 ((uint32_t)0x00050000) /*!< f(MCLK)/32 */ 2696 #define CS_CTL1_DIVM__64 ((uint32_t)0x00060000) /*!< f(MCLK)/64 */ 2697 #define CS_CTL1_DIVM__128 ((uint32_t)0x00070000) /*!< f(MCLK)/128 */ 2698 /* CS_CTL1[DIVHS] Bits */ 2699 #define CS_CTL1_DIVHS_OFS (20) /*!< DIVHS Bit Offset */ 2700 #define CS_CTL1_DIVHS_MASK ((uint32_t)0x00700000) /*!< DIVHS Bit Mask */ 2701 #define CS_CTL1_DIVHS0 ((uint32_t)0x00100000) /*!< DIVHS Bit 0 */ 2702 #define CS_CTL1_DIVHS1 ((uint32_t)0x00200000) /*!< DIVHS Bit 1 */ 2703 #define CS_CTL1_DIVHS2 ((uint32_t)0x00400000) /*!< DIVHS Bit 2 */ 2704 #define CS_CTL1_DIVHS_0 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ 2705 #define CS_CTL1_DIVHS_1 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ 2706 #define CS_CTL1_DIVHS_2 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ 2707 #define CS_CTL1_DIVHS_3 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ 2708 #define CS_CTL1_DIVHS_4 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ 2709 #define CS_CTL1_DIVHS_5 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ 2710 #define CS_CTL1_DIVHS_6 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ 2711 #define CS_CTL1_DIVHS_7 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ 2712 #define CS_CTL1_DIVHS__1 ((uint32_t)0x00000000) /*!< f(HSMCLK)/1 */ 2713 #define CS_CTL1_DIVHS__2 ((uint32_t)0x00100000) /*!< f(HSMCLK)/2 */ 2714 #define CS_CTL1_DIVHS__4 ((uint32_t)0x00200000) /*!< f(HSMCLK)/4 */ 2715 #define CS_CTL1_DIVHS__8 ((uint32_t)0x00300000) /*!< f(HSMCLK)/8 */ 2716 #define CS_CTL1_DIVHS__16 ((uint32_t)0x00400000) /*!< f(HSMCLK)/16 */ 2717 #define CS_CTL1_DIVHS__32 ((uint32_t)0x00500000) /*!< f(HSMCLK)/32 */ 2718 #define CS_CTL1_DIVHS__64 ((uint32_t)0x00600000) /*!< f(HSMCLK)/64 */ 2719 #define CS_CTL1_DIVHS__128 ((uint32_t)0x00700000) /*!< f(HSMCLK)/128 */ 2720 /* CS_CTL1[DIVA] Bits */ 2721 #define CS_CTL1_DIVA_OFS (24) /*!< DIVA Bit Offset */ 2722 #define CS_CTL1_DIVA_MASK ((uint32_t)0x07000000) /*!< DIVA Bit Mask */ 2723 #define CS_CTL1_DIVA0 ((uint32_t)0x01000000) /*!< DIVA Bit 0 */ 2724 #define CS_CTL1_DIVA1 ((uint32_t)0x02000000) /*!< DIVA Bit 1 */ 2725 #define CS_CTL1_DIVA2 ((uint32_t)0x04000000) /*!< DIVA Bit 2 */ 2726 #define CS_CTL1_DIVA_0 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ 2727 #define CS_CTL1_DIVA_1 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ 2728 #define CS_CTL1_DIVA_2 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ 2729 #define CS_CTL1_DIVA_3 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ 2730 #define CS_CTL1_DIVA_4 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ 2731 #define CS_CTL1_DIVA_5 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ 2732 #define CS_CTL1_DIVA_6 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ 2733 #define CS_CTL1_DIVA_7 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ 2734 #define CS_CTL1_DIVA__1 ((uint32_t)0x00000000) /*!< f(ACLK)/1 */ 2735 #define CS_CTL1_DIVA__2 ((uint32_t)0x01000000) /*!< f(ACLK)/2 */ 2736 #define CS_CTL1_DIVA__4 ((uint32_t)0x02000000) /*!< f(ACLK)/4 */ 2737 #define CS_CTL1_DIVA__8 ((uint32_t)0x03000000) /*!< f(ACLK)/8 */ 2738 #define CS_CTL1_DIVA__16 ((uint32_t)0x04000000) /*!< f(ACLK)/16 */ 2739 #define CS_CTL1_DIVA__32 ((uint32_t)0x05000000) /*!< f(ACLK)/32 */ 2740 #define CS_CTL1_DIVA__64 ((uint32_t)0x06000000) /*!< f(ACLK)/64 */ 2741 #define CS_CTL1_DIVA__128 ((uint32_t)0x07000000) /*!< f(ACLK)/128 */ 2742 /* CS_CTL1[DIVS] Bits */ 2743 #define CS_CTL1_DIVS_OFS (28) /*!< DIVS Bit Offset */ 2744 #define CS_CTL1_DIVS_MASK ((uint32_t)0x70000000) /*!< DIVS Bit Mask */ 2745 #define CS_CTL1_DIVS0 ((uint32_t)0x10000000) /*!< DIVS Bit 0 */ 2746 #define CS_CTL1_DIVS1 ((uint32_t)0x20000000) /*!< DIVS Bit 1 */ 2747 #define CS_CTL1_DIVS2 ((uint32_t)0x40000000) /*!< DIVS Bit 2 */ 2748 #define CS_CTL1_DIVS_0 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ 2749 #define CS_CTL1_DIVS_1 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ 2750 #define CS_CTL1_DIVS_2 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ 2751 #define CS_CTL1_DIVS_3 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ 2752 #define CS_CTL1_DIVS_4 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ 2753 #define CS_CTL1_DIVS_5 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ 2754 #define CS_CTL1_DIVS_6 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ 2755 #define CS_CTL1_DIVS_7 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ 2756 #define CS_CTL1_DIVS__1 ((uint32_t)0x00000000) /*!< f(SMCLK)/1 */ 2757 #define CS_CTL1_DIVS__2 ((uint32_t)0x10000000) /*!< f(SMCLK)/2 */ 2758 #define CS_CTL1_DIVS__4 ((uint32_t)0x20000000) /*!< f(SMCLK)/4 */ 2759 #define CS_CTL1_DIVS__8 ((uint32_t)0x30000000) /*!< f(SMCLK)/8 */ 2760 #define CS_CTL1_DIVS__16 ((uint32_t)0x40000000) /*!< f(SMCLK)/16 */ 2761 #define CS_CTL1_DIVS__32 ((uint32_t)0x50000000) /*!< f(SMCLK)/32 */ 2762 #define CS_CTL1_DIVS__64 ((uint32_t)0x60000000) /*!< f(SMCLK)/64 */ 2763 #define CS_CTL1_DIVS__128 ((uint32_t)0x70000000) /*!< f(SMCLK)/128 */ 2764 /* CS_CTL2[LFXTDRIVE] Bits */ 2765 #define CS_CTL2_LFXTDRIVE_OFS ( 0) /*!< LFXTDRIVE Bit Offset */ 2766 #define CS_CTL2_LFXTDRIVE_MASK ((uint32_t)0x00000003) /*!< LFXTDRIVE Bit Mask */ 2767 #define CS_CTL2_LFXTDRIVE0 ((uint32_t)0x00000001) /*!< LFXTDRIVE Bit 0 */ 2768 #define CS_CTL2_LFXTDRIVE1 ((uint32_t)0x00000002) /*!< LFXTDRIVE Bit 1 */ 2769 #define CS_CTL2_LFXTDRIVE_0 ((uint32_t)0x00000000) /*!< Lowest drive strength and current consumption LFXT oscillator. */ 2770 #define CS_CTL2_LFXTDRIVE_1 ((uint32_t)0x00000001) /*!< Increased drive strength LFXT oscillator. */ 2771 #define CS_CTL2_LFXTDRIVE_2 ((uint32_t)0x00000002) /*!< Increased drive strength LFXT oscillator. */ 2772 #define CS_CTL2_LFXTDRIVE_3 ((uint32_t)0x00000003) /*!< Maximum drive strength and maximum current consumption LFXT oscillator. */ 2773 /* CS_CTL2[LFXT_EN] Bits */ 2774 #define CS_CTL2_LFXT_EN_OFS ( 8) /*!< LFXT_EN Bit Offset */ 2775 #define CS_CTL2_LFXT_EN ((uint32_t)0x00000100) /*!< Turns on the LFXT oscillator regardless if used as a clock resource */ 2776 /* CS_CTL2[LFXTBYPASS] Bits */ 2777 #define CS_CTL2_LFXTBYPASS_OFS ( 9) /*!< LFXTBYPASS Bit Offset */ 2778 #define CS_CTL2_LFXTBYPASS ((uint32_t)0x00000200) /*!< LFXT bypass select */ 2779 /* CS_CTL2[HFXTDRIVE] Bits */ 2780 #define CS_CTL2_HFXTDRIVE_OFS (16) /*!< HFXTDRIVE Bit Offset */ 2781 #define CS_CTL2_HFXTDRIVE ((uint32_t)0x00010000) /*!< HFXT oscillator drive selection */ 2782 /* CS_CTL2[HFXTFREQ] Bits */ 2783 #define CS_CTL2_HFXTFREQ_OFS (20) /*!< HFXTFREQ Bit Offset */ 2784 #define CS_CTL2_HFXTFREQ_MASK ((uint32_t)0x00700000) /*!< HFXTFREQ Bit Mask */ 2785 #define CS_CTL2_HFXTFREQ0 ((uint32_t)0x00100000) /*!< HFXTFREQ Bit 0 */ 2786 #define CS_CTL2_HFXTFREQ1 ((uint32_t)0x00200000) /*!< HFXTFREQ Bit 1 */ 2787 #define CS_CTL2_HFXTFREQ2 ((uint32_t)0x00400000) /*!< HFXTFREQ Bit 2 */ 2788 #define CS_CTL2_HFXTFREQ_0 ((uint32_t)0x00000000) /*!< 1 MHz to 4 MHz */ 2789 #define CS_CTL2_HFXTFREQ_1 ((uint32_t)0x00100000) /*!< >4 MHz to 8 MHz */ 2790 #define CS_CTL2_HFXTFREQ_2 ((uint32_t)0x00200000) /*!< >8 MHz to 16 MHz */ 2791 #define CS_CTL2_HFXTFREQ_3 ((uint32_t)0x00300000) /*!< >16 MHz to 24 MHz */ 2792 #define CS_CTL2_HFXTFREQ_4 ((uint32_t)0x00400000) /*!< >24 MHz to 32 MHz */ 2793 #define CS_CTL2_HFXTFREQ_5 ((uint32_t)0x00500000) /*!< >32 MHz to 40 MHz */ 2794 #define CS_CTL2_HFXTFREQ_6 ((uint32_t)0x00600000) /*!< >40 MHz to 48 MHz */ 2795 #define CS_CTL2_HFXTFREQ_7 ((uint32_t)0x00700000) /*!< Reserved for future use. */ 2796 /* CS_CTL2[HFXT_EN] Bits */ 2797 #define CS_CTL2_HFXT_EN_OFS (24) /*!< HFXT_EN Bit Offset */ 2798 #define CS_CTL2_HFXT_EN ((uint32_t)0x01000000) /*!< Turns on the HFXT oscillator regardless if used as a clock resource */ 2799 /* CS_CTL2[HFXTBYPASS] Bits */ 2800 #define CS_CTL2_HFXTBYPASS_OFS (25) /*!< HFXTBYPASS Bit Offset */ 2801 #define CS_CTL2_HFXTBYPASS ((uint32_t)0x02000000) /*!< HFXT bypass select */ 2802 /* CS_CTL3[FCNTLF] Bits */ 2803 #define CS_CTL3_FCNTLF_OFS ( 0) /*!< FCNTLF Bit Offset */ 2804 #define CS_CTL3_FCNTLF_MASK ((uint32_t)0x00000003) /*!< FCNTLF Bit Mask */ 2805 #define CS_CTL3_FCNTLF0 ((uint32_t)0x00000001) /*!< FCNTLF Bit 0 */ 2806 #define CS_CTL3_FCNTLF1 ((uint32_t)0x00000002) /*!< FCNTLF Bit 1 */ 2807 #define CS_CTL3_FCNTLF_0 ((uint32_t)0x00000000) /*!< 4096 cycles */ 2808 #define CS_CTL3_FCNTLF_1 ((uint32_t)0x00000001) /*!< 8192 cycles */ 2809 #define CS_CTL3_FCNTLF_2 ((uint32_t)0x00000002) /*!< 16384 cycles */ 2810 #define CS_CTL3_FCNTLF_3 ((uint32_t)0x00000003) /*!< 32768 cycles */ 2811 #define CS_CTL3_FCNTLF__4096 ((uint32_t)0x00000000) /*!< 4096 cycles */ 2812 #define CS_CTL3_FCNTLF__8192 ((uint32_t)0x00000001) /*!< 8192 cycles */ 2813 #define CS_CTL3_FCNTLF__16384 ((uint32_t)0x00000002) /*!< 16384 cycles */ 2814 #define CS_CTL3_FCNTLF__32768 ((uint32_t)0x00000003) /*!< 32768 cycles */ 2815 /* CS_CTL3[RFCNTLF] Bits */ 2816 #define CS_CTL3_RFCNTLF_OFS ( 2) /*!< RFCNTLF Bit Offset */ 2817 #define CS_CTL3_RFCNTLF ((uint32_t)0x00000004) /*!< Reset start fault counter for LFXT */ 2818 /* CS_CTL3[FCNTLF_EN] Bits */ 2819 #define CS_CTL3_FCNTLF_EN_OFS ( 3) /*!< FCNTLF_EN Bit Offset */ 2820 #define CS_CTL3_FCNTLF_EN ((uint32_t)0x00000008) /*!< Enable start fault counter for LFXT */ 2821 /* CS_CTL3[FCNTHF] Bits */ 2822 #define CS_CTL3_FCNTHF_OFS ( 4) /*!< FCNTHF Bit Offset */ 2823 #define CS_CTL3_FCNTHF_MASK ((uint32_t)0x00000030) /*!< FCNTHF Bit Mask */ 2824 #define CS_CTL3_FCNTHF0 ((uint32_t)0x00000010) /*!< FCNTHF Bit 0 */ 2825 #define CS_CTL3_FCNTHF1 ((uint32_t)0x00000020) /*!< FCNTHF Bit 1 */ 2826 #define CS_CTL3_FCNTHF_0 ((uint32_t)0x00000000) /*!< 2048 cycles */ 2827 #define CS_CTL3_FCNTHF_1 ((uint32_t)0x00000010) /*!< 4096 cycles */ 2828 #define CS_CTL3_FCNTHF_2 ((uint32_t)0x00000020) /*!< 8192 cycles */ 2829 #define CS_CTL3_FCNTHF_3 ((uint32_t)0x00000030) /*!< 16384 cycles */ 2830 #define CS_CTL3_FCNTHF__2048 ((uint32_t)0x00000000) /*!< 2048 cycles */ 2831 #define CS_CTL3_FCNTHF__4096 ((uint32_t)0x00000010) /*!< 4096 cycles */ 2832 #define CS_CTL3_FCNTHF__8192 ((uint32_t)0x00000020) /*!< 8192 cycles */ 2833 #define CS_CTL3_FCNTHF__16384 ((uint32_t)0x00000030) /*!< 16384 cycles */ 2834 /* CS_CTL3[RFCNTHF] Bits */ 2835 #define CS_CTL3_RFCNTHF_OFS ( 6) /*!< RFCNTHF Bit Offset */ 2836 #define CS_CTL3_RFCNTHF ((uint32_t)0x00000040) /*!< Reset start fault counter for HFXT */ 2837 /* CS_CTL3[FCNTHF_EN] Bits */ 2838 #define CS_CTL3_FCNTHF_EN_OFS ( 7) /*!< FCNTHF_EN Bit Offset */ 2839 #define CS_CTL3_FCNTHF_EN ((uint32_t)0x00000080) /*!< Enable start fault counter for HFXT */ 2840 /* CS_CLKEN[ACLK_EN] Bits */ 2841 #define CS_CLKEN_ACLK_EN_OFS ( 0) /*!< ACLK_EN Bit Offset */ 2842 #define CS_CLKEN_ACLK_EN ((uint32_t)0x00000001) /*!< ACLK system clock conditional request enable */ 2843 /* CS_CLKEN[MCLK_EN] Bits */ 2844 #define CS_CLKEN_MCLK_EN_OFS ( 1) /*!< MCLK_EN Bit Offset */ 2845 #define CS_CLKEN_MCLK_EN ((uint32_t)0x00000002) /*!< MCLK system clock conditional request enable */ 2846 /* CS_CLKEN[HSMCLK_EN] Bits */ 2847 #define CS_CLKEN_HSMCLK_EN_OFS ( 2) /*!< HSMCLK_EN Bit Offset */ 2848 #define CS_CLKEN_HSMCLK_EN ((uint32_t)0x00000004) /*!< HSMCLK system clock conditional request enable */ 2849 /* CS_CLKEN[SMCLK_EN] Bits */ 2850 #define CS_CLKEN_SMCLK_EN_OFS ( 3) /*!< SMCLK_EN Bit Offset */ 2851 #define CS_CLKEN_SMCLK_EN ((uint32_t)0x00000008) /*!< SMCLK system clock conditional request enable */ 2852 /* CS_CLKEN[VLO_EN] Bits */ 2853 #define CS_CLKEN_VLO_EN_OFS ( 8) /*!< VLO_EN Bit Offset */ 2854 #define CS_CLKEN_VLO_EN ((uint32_t)0x00000100) /*!< Turns on the VLO oscillator */ 2855 /* CS_CLKEN[REFO_EN] Bits */ 2856 #define CS_CLKEN_REFO_EN_OFS ( 9) /*!< REFO_EN Bit Offset */ 2857 #define CS_CLKEN_REFO_EN ((uint32_t)0x00000200) /*!< Turns on the REFO oscillator */ 2858 /* CS_CLKEN[MODOSC_EN] Bits */ 2859 #define CS_CLKEN_MODOSC_EN_OFS (10) /*!< MODOSC_EN Bit Offset */ 2860 #define CS_CLKEN_MODOSC_EN ((uint32_t)0x00000400) /*!< Turns on the MODOSC oscillator */ 2861 /* CS_CLKEN[REFOFSEL] Bits */ 2862 #define CS_CLKEN_REFOFSEL_OFS (15) /*!< REFOFSEL Bit Offset */ 2863 #define CS_CLKEN_REFOFSEL ((uint32_t)0x00008000) /*!< Selects REFO nominal frequency */ 2864 /* CS_STAT[DCO_ON] Bits */ 2865 #define CS_STAT_DCO_ON_OFS ( 0) /*!< DCO_ON Bit Offset */ 2866 #define CS_STAT_DCO_ON ((uint32_t)0x00000001) /*!< DCO status */ 2867 /* CS_STAT[DCOBIAS_ON] Bits */ 2868 #define CS_STAT_DCOBIAS_ON_OFS ( 1) /*!< DCOBIAS_ON Bit Offset */ 2869 #define CS_STAT_DCOBIAS_ON ((uint32_t)0x00000002) /*!< DCO bias status */ 2870 /* CS_STAT[HFXT_ON] Bits */ 2871 #define CS_STAT_HFXT_ON_OFS ( 2) /*!< HFXT_ON Bit Offset */ 2872 #define CS_STAT_HFXT_ON ((uint32_t)0x00000004) /*!< HFXT status */ 2873 /* CS_STAT[MODOSC_ON] Bits */ 2874 #define CS_STAT_MODOSC_ON_OFS ( 4) /*!< MODOSC_ON Bit Offset */ 2875 #define CS_STAT_MODOSC_ON ((uint32_t)0x00000010) /*!< MODOSC status */ 2876 /* CS_STAT[VLO_ON] Bits */ 2877 #define CS_STAT_VLO_ON_OFS ( 5) /*!< VLO_ON Bit Offset */ 2878 #define CS_STAT_VLO_ON ((uint32_t)0x00000020) /*!< VLO status */ 2879 /* CS_STAT[LFXT_ON] Bits */ 2880 #define CS_STAT_LFXT_ON_OFS ( 6) /*!< LFXT_ON Bit Offset */ 2881 #define CS_STAT_LFXT_ON ((uint32_t)0x00000040) /*!< LFXT status */ 2882 /* CS_STAT[REFO_ON] Bits */ 2883 #define CS_STAT_REFO_ON_OFS ( 7) /*!< REFO_ON Bit Offset */ 2884 #define CS_STAT_REFO_ON ((uint32_t)0x00000080) /*!< REFO status */ 2885 /* CS_STAT[ACLK_ON] Bits */ 2886 #define CS_STAT_ACLK_ON_OFS (16) /*!< ACLK_ON Bit Offset */ 2887 #define CS_STAT_ACLK_ON ((uint32_t)0x00010000) /*!< ACLK system clock status */ 2888 /* CS_STAT[MCLK_ON] Bits */ 2889 #define CS_STAT_MCLK_ON_OFS (17) /*!< MCLK_ON Bit Offset */ 2890 #define CS_STAT_MCLK_ON ((uint32_t)0x00020000) /*!< MCLK system clock status */ 2891 /* CS_STAT[HSMCLK_ON] Bits */ 2892 #define CS_STAT_HSMCLK_ON_OFS (18) /*!< HSMCLK_ON Bit Offset */ 2893 #define CS_STAT_HSMCLK_ON ((uint32_t)0x00040000) /*!< HSMCLK system clock status */ 2894 /* CS_STAT[SMCLK_ON] Bits */ 2895 #define CS_STAT_SMCLK_ON_OFS (19) /*!< SMCLK_ON Bit Offset */ 2896 #define CS_STAT_SMCLK_ON ((uint32_t)0x00080000) /*!< SMCLK system clock status */ 2897 /* CS_STAT[MODCLK_ON] Bits */ 2898 #define CS_STAT_MODCLK_ON_OFS (20) /*!< MODCLK_ON Bit Offset */ 2899 #define CS_STAT_MODCLK_ON ((uint32_t)0x00100000) /*!< MODCLK system clock status */ 2900 /* CS_STAT[VLOCLK_ON] Bits */ 2901 #define CS_STAT_VLOCLK_ON_OFS (21) /*!< VLOCLK_ON Bit Offset */ 2902 #define CS_STAT_VLOCLK_ON ((uint32_t)0x00200000) /*!< VLOCLK system clock status */ 2903 /* CS_STAT[LFXTCLK_ON] Bits */ 2904 #define CS_STAT_LFXTCLK_ON_OFS (22) /*!< LFXTCLK_ON Bit Offset */ 2905 #define CS_STAT_LFXTCLK_ON ((uint32_t)0x00400000) /*!< LFXTCLK system clock status */ 2906 /* CS_STAT[REFOCLK_ON] Bits */ 2907 #define CS_STAT_REFOCLK_ON_OFS (23) /*!< REFOCLK_ON Bit Offset */ 2908 #define CS_STAT_REFOCLK_ON ((uint32_t)0x00800000) /*!< REFOCLK system clock status */ 2909 /* CS_STAT[ACLK_READY] Bits */ 2910 #define CS_STAT_ACLK_READY_OFS (24) /*!< ACLK_READY Bit Offset */ 2911 #define CS_STAT_ACLK_READY ((uint32_t)0x01000000) /*!< ACLK Ready status */ 2912 /* CS_STAT[MCLK_READY] Bits */ 2913 #define CS_STAT_MCLK_READY_OFS (25) /*!< MCLK_READY Bit Offset */ 2914 #define CS_STAT_MCLK_READY ((uint32_t)0x02000000) /*!< MCLK Ready status */ 2915 /* CS_STAT[HSMCLK_READY] Bits */ 2916 #define CS_STAT_HSMCLK_READY_OFS (26) /*!< HSMCLK_READY Bit Offset */ 2917 #define CS_STAT_HSMCLK_READY ((uint32_t)0x04000000) /*!< HSMCLK Ready status */ 2918 /* CS_STAT[SMCLK_READY] Bits */ 2919 #define CS_STAT_SMCLK_READY_OFS (27) /*!< SMCLK_READY Bit Offset */ 2920 #define CS_STAT_SMCLK_READY ((uint32_t)0x08000000) /*!< SMCLK Ready status */ 2921 /* CS_STAT[BCLK_READY] Bits */ 2922 #define CS_STAT_BCLK_READY_OFS (28) /*!< BCLK_READY Bit Offset */ 2923 #define CS_STAT_BCLK_READY ((uint32_t)0x10000000) /*!< BCLK Ready status */ 2924 /* CS_IE[LFXTIE] Bits */ 2925 #define CS_IE_LFXTIE_OFS ( 0) /*!< LFXTIE Bit Offset */ 2926 #define CS_IE_LFXTIE ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag interrupt enable */ 2927 /* CS_IE[HFXTIE] Bits */ 2928 #define CS_IE_HFXTIE_OFS ( 1) /*!< HFXTIE Bit Offset */ 2929 #define CS_IE_HFXTIE ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag interrupt enable */ 2930 /* CS_IE[DCOR_OPNIE] Bits */ 2931 #define CS_IE_DCOR_OPNIE_OFS ( 6) /*!< DCOR_OPNIE Bit Offset */ 2932 #define CS_IE_DCOR_OPNIE ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag interrupt enable. */ 2933 /* CS_IE[FCNTLFIE] Bits */ 2934 #define CS_IE_FCNTLFIE_OFS ( 8) /*!< FCNTLFIE Bit Offset */ 2935 #define CS_IE_FCNTLFIE ((uint32_t)0x00000100) /*!< Start fault counter interrupt enable LFXT */ 2936 /* CS_IE[FCNTHFIE] Bits */ 2937 #define CS_IE_FCNTHFIE_OFS ( 9) /*!< FCNTHFIE Bit Offset */ 2938 #define CS_IE_FCNTHFIE ((uint32_t)0x00000200) /*!< Start fault counter interrupt enable HFXT */ 2939 /* CS_IFG[LFXTIFG] Bits */ 2940 #define CS_IFG_LFXTIFG_OFS ( 0) /*!< LFXTIFG Bit Offset */ 2941 #define CS_IFG_LFXTIFG ((uint32_t)0x00000001) /*!< LFXT oscillator fault flag */ 2942 /* CS_IFG[HFXTIFG] Bits */ 2943 #define CS_IFG_HFXTIFG_OFS ( 1) /*!< HFXTIFG Bit Offset */ 2944 #define CS_IFG_HFXTIFG ((uint32_t)0x00000002) /*!< HFXT oscillator fault flag */ 2945 /* CS_IFG[DCOR_SHTIFG] Bits */ 2946 #define CS_IFG_DCOR_SHTIFG_OFS ( 5) /*!< DCOR_SHTIFG Bit Offset */ 2947 #define CS_IFG_DCOR_SHTIFG ((uint32_t)0x00000020) /*!< DCO external resistor short circuit fault flag. */ 2948 /* CS_IFG[DCOR_OPNIFG] Bits */ 2949 #define CS_IFG_DCOR_OPNIFG_OFS ( 6) /*!< DCOR_OPNIFG Bit Offset */ 2950 #define CS_IFG_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< DCO external resistor open circuit fault flag. */ 2951 /* CS_IFG[FCNTLFIFG] Bits */ 2952 #define CS_IFG_FCNTLFIFG_OFS ( 8) /*!< FCNTLFIFG Bit Offset */ 2953 #define CS_IFG_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter interrupt flag LFXT */ 2954 /* CS_IFG[FCNTHFIFG] Bits */ 2955 #define CS_IFG_FCNTHFIFG_OFS ( 9) /*!< FCNTHFIFG Bit Offset */ 2956 #define CS_IFG_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter interrupt flag HFXT */ 2957 /* CS_CLRIFG[CLR_LFXTIFG] Bits */ 2958 #define CS_CLRIFG_CLR_LFXTIFG_OFS ( 0) /*!< CLR_LFXTIFG Bit Offset */ 2959 #define CS_CLRIFG_CLR_LFXTIFG ((uint32_t)0x00000001) /*!< Clear LFXT oscillator fault interrupt flag */ 2960 /* CS_CLRIFG[CLR_HFXTIFG] Bits */ 2961 #define CS_CLRIFG_CLR_HFXTIFG_OFS ( 1) /*!< CLR_HFXTIFG Bit Offset */ 2962 #define CS_CLRIFG_CLR_HFXTIFG ((uint32_t)0x00000002) /*!< Clear HFXT oscillator fault interrupt flag */ 2963 /* CS_CLRIFG[CLR_DCOR_OPNIFG] Bits */ 2964 #define CS_CLRIFG_CLR_DCOR_OPNIFG_OFS ( 6) /*!< CLR_DCOR_OPNIFG Bit Offset */ 2965 #define CS_CLRIFG_CLR_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Clear DCO external resistor open circuit fault interrupt flag. */ 2966 /* CS_CLRIFG[CLR_FCNTLFIFG] Bits */ 2967 #define CS_CLRIFG_CLR_FCNTLFIFG_OFS ( 8) /*!< CLR_FCNTLFIFG Bit Offset */ 2968 #define CS_CLRIFG_CLR_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter clear interrupt flag LFXT */ 2969 /* CS_CLRIFG[CLR_FCNTHFIFG] Bits */ 2970 #define CS_CLRIFG_CLR_FCNTHFIFG_OFS ( 9) /*!< CLR_FCNTHFIFG Bit Offset */ 2971 #define CS_CLRIFG_CLR_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter clear interrupt flag HFXT */ 2972 /* CS_SETIFG[SET_LFXTIFG] Bits */ 2973 #define CS_SETIFG_SET_LFXTIFG_OFS ( 0) /*!< SET_LFXTIFG Bit Offset */ 2974 #define CS_SETIFG_SET_LFXTIFG ((uint32_t)0x00000001) /*!< Set LFXT oscillator fault interrupt flag */ 2975 /* CS_SETIFG[SET_HFXTIFG] Bits */ 2976 #define CS_SETIFG_SET_HFXTIFG_OFS ( 1) /*!< SET_HFXTIFG Bit Offset */ 2977 #define CS_SETIFG_SET_HFXTIFG ((uint32_t)0x00000002) /*!< Set HFXT oscillator fault interrupt flag */ 2978 /* CS_SETIFG[SET_DCOR_OPNIFG] Bits */ 2979 #define CS_SETIFG_SET_DCOR_OPNIFG_OFS ( 6) /*!< SET_DCOR_OPNIFG Bit Offset */ 2980 #define CS_SETIFG_SET_DCOR_OPNIFG ((uint32_t)0x00000040) /*!< Set DCO external resistor open circuit fault interrupt flag. */ 2981 /* CS_SETIFG[SET_FCNTHFIFG] Bits */ 2982 #define CS_SETIFG_SET_FCNTHFIFG_OFS ( 9) /*!< SET_FCNTHFIFG Bit Offset */ 2983 #define CS_SETIFG_SET_FCNTHFIFG ((uint32_t)0x00000200) /*!< Start fault counter set interrupt flag HFXT */ 2984 /* CS_SETIFG[SET_FCNTLFIFG] Bits */ 2985 #define CS_SETIFG_SET_FCNTLFIFG_OFS ( 8) /*!< SET_FCNTLFIFG Bit Offset */ 2986 #define CS_SETIFG_SET_FCNTLFIFG ((uint32_t)0x00000100) /*!< Start fault counter set interrupt flag LFXT */ 2987 /* CS_DCOERCAL0[DCO_TCCAL] Bits */ 2988 #define CS_DCOERCAL0_DCO_TCCAL_OFS ( 0) /*!< DCO_TCCAL Bit Offset */ 2989 #define CS_DCOERCAL0_DCO_TCCAL_MASK ((uint32_t)0x00000003) /*!< DCO_TCCAL Bit Mask */ 2990 /* CS_DCOERCAL0[DCO_FCAL_RSEL04] Bits */ 2991 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_OFS (16) /*!< DCO_FCAL_RSEL04 Bit Offset */ 2992 #define CS_DCOERCAL0_DCO_FCAL_RSEL04_MASK ((uint32_t)0x03FF0000) /*!< DCO_FCAL_RSEL04 Bit Mask */ 2993 /* CS_DCOERCAL1[DCO_FCAL_RSEL5] Bits */ 2994 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_OFS ( 0) /*!< DCO_FCAL_RSEL5 Bit Offset */ 2995 #define CS_DCOERCAL1_DCO_FCAL_RSEL5_MASK ((uint32_t)0x000003FF) /*!< DCO_FCAL_RSEL5 Bit Mask */ 2996 /* Pre-defined bitfield values */ 2997 #define CS_KEY_VAL ((uint32_t)0x0000695A) /*!< CS control key value */ 2998 2999 /****************************************************************************** 3000 * DIO Bits 3001 ******************************************************************************/ 3002 /* DIO_IV[IV] Bits */ 3003 #define DIO_PORT_IV_OFS ( 0) /*!< DIO Port IV Bit Offset */ 3004 #define DIO_PORT_IV_MASK ((uint16_t)0x001F) /*!< DIO Port IV Bit Mask */ 3005 #define DIO_PORT_IV0 ((uint16_t)0x0001) /*!< DIO Port IV Bit 0 */ 3006 #define DIO_PORT_IV1 ((uint16_t)0x0002) /*!< DIO Port IV Bit 1 */ 3007 #define DIO_PORT_IV2 ((uint16_t)0x0004) /*!< DIO Port IV Bit 2 */ 3008 #define DIO_PORT_IV3 ((uint16_t)0x0008) /*!< DIO Port IV Bit 3 */ 3009 #define DIO_PORT_IV4 ((uint16_t)0x0010) /*!< DIO Port IV Bit 4 */ 3010 #define DIO_PORT_IV_0 ((uint16_t)0x0000) /*!< No interrupt pending */ 3011 #define DIO_PORT_IV_2 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ 3012 /* Priority: Highest */ 3013 #define DIO_PORT_IV_4 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ 3014 #define DIO_PORT_IV_6 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ 3015 #define DIO_PORT_IV_8 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ 3016 #define DIO_PORT_IV_10 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ 3017 #define DIO_PORT_IV_12 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ 3018 #define DIO_PORT_IV_14 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ 3019 #define DIO_PORT_IV_16 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ 3020 /* Priority: Lowest */ 3021 #define DIO_PORT_IV__NONE ((uint16_t)0x0000) /*!< No interrupt pending */ 3022 #define DIO_PORT_IV__IFG0 ((uint16_t)0x0002) /*!< Interrupt Source: Port x.0 interrupt; Interrupt Flag: IFG0; Interrupt */ 3023 /* Priority: Highest */ 3024 #define DIO_PORT_IV__IFG1 ((uint16_t)0x0004) /*!< Interrupt Source: Port x.1 interrupt; Interrupt Flag: IFG1 */ 3025 #define DIO_PORT_IV__IFG2 ((uint16_t)0x0006) /*!< Interrupt Source: Port x.2 interrupt; Interrupt Flag: IFG2 */ 3026 #define DIO_PORT_IV__IFG3 ((uint16_t)0x0008) /*!< Interrupt Source: Port x.3 interrupt; Interrupt Flag: IFG3 */ 3027 #define DIO_PORT_IV__IFG4 ((uint16_t)0x000A) /*!< Interrupt Source: Port x.4 interrupt; Interrupt Flag: IFG4 */ 3028 #define DIO_PORT_IV__IFG5 ((uint16_t)0x000C) /*!< Interrupt Source: Port x.5 interrupt; Interrupt Flag: IFG5 */ 3029 #define DIO_PORT_IV__IFG6 ((uint16_t)0x000E) /*!< Interrupt Source: Port x.6 interrupt; Interrupt Flag: IFG6 */ 3030 #define DIO_PORT_IV__IFG7 ((uint16_t)0x0010) /*!< Interrupt Source: Port x.7 interrupt; Interrupt Flag: IFG7; Interrupt */ 3031 /* Priority: Lowest */ 3032 3033 3034 /****************************************************************************** 3035 * DMA Bits 3036 ******************************************************************************/ 3037 /* DMA_DEVICE_CFG[NUM_DMA_CHANNELS] Bits */ 3038 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_OFS ( 0) /*!< NUM_DMA_CHANNELS Bit Offset */ 3039 #define DMA_DEVICE_CFG_NUM_DMA_CHANNELS_MASK ((uint32_t)0x000000FF) /*!< NUM_DMA_CHANNELS Bit Mask */ 3040 /* DMA_DEVICE_CFG[NUM_SRC_PER_CHANNEL] Bits */ 3041 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_OFS ( 8) /*!< NUM_SRC_PER_CHANNEL Bit Offset */ 3042 #define DMA_DEVICE_CFG_NUM_SRC_PER_CHANNEL_MASK ((uint32_t)0x0000FF00) /*!< NUM_SRC_PER_CHANNEL Bit Mask */ 3043 /* DMA_SW_CHTRIG[CH0] Bits */ 3044 #define DMA_SW_CHTRIG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ 3045 #define DMA_SW_CHTRIG_CH0 ((uint32_t)0x00000001) /*!< Write 1, triggers DMA_CHANNEL0 */ 3046 /* DMA_SW_CHTRIG[CH1] Bits */ 3047 #define DMA_SW_CHTRIG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ 3048 #define DMA_SW_CHTRIG_CH1 ((uint32_t)0x00000002) /*!< Write 1, triggers DMA_CHANNEL1 */ 3049 /* DMA_SW_CHTRIG[CH2] Bits */ 3050 #define DMA_SW_CHTRIG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ 3051 #define DMA_SW_CHTRIG_CH2 ((uint32_t)0x00000004) /*!< Write 1, triggers DMA_CHANNEL2 */ 3052 /* DMA_SW_CHTRIG[CH3] Bits */ 3053 #define DMA_SW_CHTRIG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ 3054 #define DMA_SW_CHTRIG_CH3 ((uint32_t)0x00000008) /*!< Write 1, triggers DMA_CHANNEL3 */ 3055 /* DMA_SW_CHTRIG[CH4] Bits */ 3056 #define DMA_SW_CHTRIG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ 3057 #define DMA_SW_CHTRIG_CH4 ((uint32_t)0x00000010) /*!< Write 1, triggers DMA_CHANNEL4 */ 3058 /* DMA_SW_CHTRIG[CH5] Bits */ 3059 #define DMA_SW_CHTRIG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ 3060 #define DMA_SW_CHTRIG_CH5 ((uint32_t)0x00000020) /*!< Write 1, triggers DMA_CHANNEL5 */ 3061 /* DMA_SW_CHTRIG[CH6] Bits */ 3062 #define DMA_SW_CHTRIG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ 3063 #define DMA_SW_CHTRIG_CH6 ((uint32_t)0x00000040) /*!< Write 1, triggers DMA_CHANNEL6 */ 3064 /* DMA_SW_CHTRIG[CH7] Bits */ 3065 #define DMA_SW_CHTRIG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ 3066 #define DMA_SW_CHTRIG_CH7 ((uint32_t)0x00000080) /*!< Write 1, triggers DMA_CHANNEL7 */ 3067 /* DMA_SW_CHTRIG[CH8] Bits */ 3068 #define DMA_SW_CHTRIG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ 3069 #define DMA_SW_CHTRIG_CH8 ((uint32_t)0x00000100) /*!< Write 1, triggers DMA_CHANNEL8 */ 3070 /* DMA_SW_CHTRIG[CH9] Bits */ 3071 #define DMA_SW_CHTRIG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ 3072 #define DMA_SW_CHTRIG_CH9 ((uint32_t)0x00000200) /*!< Write 1, triggers DMA_CHANNEL9 */ 3073 /* DMA_SW_CHTRIG[CH10] Bits */ 3074 #define DMA_SW_CHTRIG_CH10_OFS (10) /*!< CH10 Bit Offset */ 3075 #define DMA_SW_CHTRIG_CH10 ((uint32_t)0x00000400) /*!< Write 1, triggers DMA_CHANNEL10 */ 3076 /* DMA_SW_CHTRIG[CH11] Bits */ 3077 #define DMA_SW_CHTRIG_CH11_OFS (11) /*!< CH11 Bit Offset */ 3078 #define DMA_SW_CHTRIG_CH11 ((uint32_t)0x00000800) /*!< Write 1, triggers DMA_CHANNEL11 */ 3079 /* DMA_SW_CHTRIG[CH12] Bits */ 3080 #define DMA_SW_CHTRIG_CH12_OFS (12) /*!< CH12 Bit Offset */ 3081 #define DMA_SW_CHTRIG_CH12 ((uint32_t)0x00001000) /*!< Write 1, triggers DMA_CHANNEL12 */ 3082 /* DMA_SW_CHTRIG[CH13] Bits */ 3083 #define DMA_SW_CHTRIG_CH13_OFS (13) /*!< CH13 Bit Offset */ 3084 #define DMA_SW_CHTRIG_CH13 ((uint32_t)0x00002000) /*!< Write 1, triggers DMA_CHANNEL13 */ 3085 /* DMA_SW_CHTRIG[CH14] Bits */ 3086 #define DMA_SW_CHTRIG_CH14_OFS (14) /*!< CH14 Bit Offset */ 3087 #define DMA_SW_CHTRIG_CH14 ((uint32_t)0x00004000) /*!< Write 1, triggers DMA_CHANNEL14 */ 3088 /* DMA_SW_CHTRIG[CH15] Bits */ 3089 #define DMA_SW_CHTRIG_CH15_OFS (15) /*!< CH15 Bit Offset */ 3090 #define DMA_SW_CHTRIG_CH15 ((uint32_t)0x00008000) /*!< Write 1, triggers DMA_CHANNEL15 */ 3091 /* DMA_SW_CHTRIG[CH16] Bits */ 3092 #define DMA_SW_CHTRIG_CH16_OFS (16) /*!< CH16 Bit Offset */ 3093 #define DMA_SW_CHTRIG_CH16 ((uint32_t)0x00010000) /*!< Write 1, triggers DMA_CHANNEL16 */ 3094 /* DMA_SW_CHTRIG[CH17] Bits */ 3095 #define DMA_SW_CHTRIG_CH17_OFS (17) /*!< CH17 Bit Offset */ 3096 #define DMA_SW_CHTRIG_CH17 ((uint32_t)0x00020000) /*!< Write 1, triggers DMA_CHANNEL17 */ 3097 /* DMA_SW_CHTRIG[CH18] Bits */ 3098 #define DMA_SW_CHTRIG_CH18_OFS (18) /*!< CH18 Bit Offset */ 3099 #define DMA_SW_CHTRIG_CH18 ((uint32_t)0x00040000) /*!< Write 1, triggers DMA_CHANNEL18 */ 3100 /* DMA_SW_CHTRIG[CH19] Bits */ 3101 #define DMA_SW_CHTRIG_CH19_OFS (19) /*!< CH19 Bit Offset */ 3102 #define DMA_SW_CHTRIG_CH19 ((uint32_t)0x00080000) /*!< Write 1, triggers DMA_CHANNEL19 */ 3103 /* DMA_SW_CHTRIG[CH20] Bits */ 3104 #define DMA_SW_CHTRIG_CH20_OFS (20) /*!< CH20 Bit Offset */ 3105 #define DMA_SW_CHTRIG_CH20 ((uint32_t)0x00100000) /*!< Write 1, triggers DMA_CHANNEL20 */ 3106 /* DMA_SW_CHTRIG[CH21] Bits */ 3107 #define DMA_SW_CHTRIG_CH21_OFS (21) /*!< CH21 Bit Offset */ 3108 #define DMA_SW_CHTRIG_CH21 ((uint32_t)0x00200000) /*!< Write 1, triggers DMA_CHANNEL21 */ 3109 /* DMA_SW_CHTRIG[CH22] Bits */ 3110 #define DMA_SW_CHTRIG_CH22_OFS (22) /*!< CH22 Bit Offset */ 3111 #define DMA_SW_CHTRIG_CH22 ((uint32_t)0x00400000) /*!< Write 1, triggers DMA_CHANNEL22 */ 3112 /* DMA_SW_CHTRIG[CH23] Bits */ 3113 #define DMA_SW_CHTRIG_CH23_OFS (23) /*!< CH23 Bit Offset */ 3114 #define DMA_SW_CHTRIG_CH23 ((uint32_t)0x00800000) /*!< Write 1, triggers DMA_CHANNEL23 */ 3115 /* DMA_SW_CHTRIG[CH24] Bits */ 3116 #define DMA_SW_CHTRIG_CH24_OFS (24) /*!< CH24 Bit Offset */ 3117 #define DMA_SW_CHTRIG_CH24 ((uint32_t)0x01000000) /*!< Write 1, triggers DMA_CHANNEL24 */ 3118 /* DMA_SW_CHTRIG[CH25] Bits */ 3119 #define DMA_SW_CHTRIG_CH25_OFS (25) /*!< CH25 Bit Offset */ 3120 #define DMA_SW_CHTRIG_CH25 ((uint32_t)0x02000000) /*!< Write 1, triggers DMA_CHANNEL25 */ 3121 /* DMA_SW_CHTRIG[CH26] Bits */ 3122 #define DMA_SW_CHTRIG_CH26_OFS (26) /*!< CH26 Bit Offset */ 3123 #define DMA_SW_CHTRIG_CH26 ((uint32_t)0x04000000) /*!< Write 1, triggers DMA_CHANNEL26 */ 3124 /* DMA_SW_CHTRIG[CH27] Bits */ 3125 #define DMA_SW_CHTRIG_CH27_OFS (27) /*!< CH27 Bit Offset */ 3126 #define DMA_SW_CHTRIG_CH27 ((uint32_t)0x08000000) /*!< Write 1, triggers DMA_CHANNEL27 */ 3127 /* DMA_SW_CHTRIG[CH28] Bits */ 3128 #define DMA_SW_CHTRIG_CH28_OFS (28) /*!< CH28 Bit Offset */ 3129 #define DMA_SW_CHTRIG_CH28 ((uint32_t)0x10000000) /*!< Write 1, triggers DMA_CHANNEL28 */ 3130 /* DMA_SW_CHTRIG[CH29] Bits */ 3131 #define DMA_SW_CHTRIG_CH29_OFS (29) /*!< CH29 Bit Offset */ 3132 #define DMA_SW_CHTRIG_CH29 ((uint32_t)0x20000000) /*!< Write 1, triggers DMA_CHANNEL29 */ 3133 /* DMA_SW_CHTRIG[CH30] Bits */ 3134 #define DMA_SW_CHTRIG_CH30_OFS (30) /*!< CH30 Bit Offset */ 3135 #define DMA_SW_CHTRIG_CH30 ((uint32_t)0x40000000) /*!< Write 1, triggers DMA_CHANNEL30 */ 3136 /* DMA_SW_CHTRIG[CH31] Bits */ 3137 #define DMA_SW_CHTRIG_CH31_OFS (31) /*!< CH31 Bit Offset */ 3138 #define DMA_SW_CHTRIG_CH31 ((uint32_t)0x80000000) /*!< Write 1, triggers DMA_CHANNEL31 */ 3139 /* DMA_CHN_SRCCFG[DMA_SRC] Bits */ 3140 #define DMA_CHN_SRCCFG_DMA_SRC_OFS ( 0) /*!< DMA_SRC Bit Offset */ 3141 #define DMA_CHN_SRCCFG_DMA_SRC_MASK ((uint32_t)0x000000FF) /*!< DMA_SRC Bit Mask */ 3142 /* DMA_INT1_SRCCFG[INT_SRC] Bits */ 3143 #define DMA_INT1_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ 3144 #define DMA_INT1_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ 3145 /* DMA_INT1_SRCCFG[EN] Bits */ 3146 #define DMA_INT1_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ 3147 #define DMA_INT1_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT1 mapping */ 3148 /* DMA_INT2_SRCCFG[INT_SRC] Bits */ 3149 #define DMA_INT2_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ 3150 #define DMA_INT2_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ 3151 /* DMA_INT2_SRCCFG[EN] Bits */ 3152 #define DMA_INT2_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ 3153 #define DMA_INT2_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT2 mapping */ 3154 /* DMA_INT3_SRCCFG[INT_SRC] Bits */ 3155 #define DMA_INT3_SRCCFG_INT_SRC_OFS ( 0) /*!< INT_SRC Bit Offset */ 3156 #define DMA_INT3_SRCCFG_INT_SRC_MASK ((uint32_t)0x0000001F) /*!< INT_SRC Bit Mask */ 3157 /* DMA_INT3_SRCCFG[EN] Bits */ 3158 #define DMA_INT3_SRCCFG_EN_OFS ( 5) /*!< EN Bit Offset */ 3159 #define DMA_INT3_SRCCFG_EN ((uint32_t)0x00000020) /*!< Enables DMA_INT3 mapping */ 3160 /* DMA_INT0_SRCFLG[CH0] Bits */ 3161 #define DMA_INT0_SRCFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ 3162 #define DMA_INT0_SRCFLG_CH0 ((uint32_t)0x00000001) /*!< Channel 0 was the source of DMA_INT0 */ 3163 /* DMA_INT0_SRCFLG[CH1] Bits */ 3164 #define DMA_INT0_SRCFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ 3165 #define DMA_INT0_SRCFLG_CH1 ((uint32_t)0x00000002) /*!< Channel 1 was the source of DMA_INT0 */ 3166 /* DMA_INT0_SRCFLG[CH2] Bits */ 3167 #define DMA_INT0_SRCFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ 3168 #define DMA_INT0_SRCFLG_CH2 ((uint32_t)0x00000004) /*!< Channel 2 was the source of DMA_INT0 */ 3169 /* DMA_INT0_SRCFLG[CH3] Bits */ 3170 #define DMA_INT0_SRCFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ 3171 #define DMA_INT0_SRCFLG_CH3 ((uint32_t)0x00000008) /*!< Channel 3 was the source of DMA_INT0 */ 3172 /* DMA_INT0_SRCFLG[CH4] Bits */ 3173 #define DMA_INT0_SRCFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ 3174 #define DMA_INT0_SRCFLG_CH4 ((uint32_t)0x00000010) /*!< Channel 4 was the source of DMA_INT0 */ 3175 /* DMA_INT0_SRCFLG[CH5] Bits */ 3176 #define DMA_INT0_SRCFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ 3177 #define DMA_INT0_SRCFLG_CH5 ((uint32_t)0x00000020) /*!< Channel 5 was the source of DMA_INT0 */ 3178 /* DMA_INT0_SRCFLG[CH6] Bits */ 3179 #define DMA_INT0_SRCFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ 3180 #define DMA_INT0_SRCFLG_CH6 ((uint32_t)0x00000040) /*!< Channel 6 was the source of DMA_INT0 */ 3181 /* DMA_INT0_SRCFLG[CH7] Bits */ 3182 #define DMA_INT0_SRCFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ 3183 #define DMA_INT0_SRCFLG_CH7 ((uint32_t)0x00000080) /*!< Channel 7 was the source of DMA_INT0 */ 3184 /* DMA_INT0_SRCFLG[CH8] Bits */ 3185 #define DMA_INT0_SRCFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ 3186 #define DMA_INT0_SRCFLG_CH8 ((uint32_t)0x00000100) /*!< Channel 8 was the source of DMA_INT0 */ 3187 /* DMA_INT0_SRCFLG[CH9] Bits */ 3188 #define DMA_INT0_SRCFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ 3189 #define DMA_INT0_SRCFLG_CH9 ((uint32_t)0x00000200) /*!< Channel 9 was the source of DMA_INT0 */ 3190 /* DMA_INT0_SRCFLG[CH10] Bits */ 3191 #define DMA_INT0_SRCFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ 3192 #define DMA_INT0_SRCFLG_CH10 ((uint32_t)0x00000400) /*!< Channel 10 was the source of DMA_INT0 */ 3193 /* DMA_INT0_SRCFLG[CH11] Bits */ 3194 #define DMA_INT0_SRCFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ 3195 #define DMA_INT0_SRCFLG_CH11 ((uint32_t)0x00000800) /*!< Channel 11 was the source of DMA_INT0 */ 3196 /* DMA_INT0_SRCFLG[CH12] Bits */ 3197 #define DMA_INT0_SRCFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ 3198 #define DMA_INT0_SRCFLG_CH12 ((uint32_t)0x00001000) /*!< Channel 12 was the source of DMA_INT0 */ 3199 /* DMA_INT0_SRCFLG[CH13] Bits */ 3200 #define DMA_INT0_SRCFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ 3201 #define DMA_INT0_SRCFLG_CH13 ((uint32_t)0x00002000) /*!< Channel 13 was the source of DMA_INT0 */ 3202 /* DMA_INT0_SRCFLG[CH14] Bits */ 3203 #define DMA_INT0_SRCFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ 3204 #define DMA_INT0_SRCFLG_CH14 ((uint32_t)0x00004000) /*!< Channel 14 was the source of DMA_INT0 */ 3205 /* DMA_INT0_SRCFLG[CH15] Bits */ 3206 #define DMA_INT0_SRCFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ 3207 #define DMA_INT0_SRCFLG_CH15 ((uint32_t)0x00008000) /*!< Channel 15 was the source of DMA_INT0 */ 3208 /* DMA_INT0_SRCFLG[CH16] Bits */ 3209 #define DMA_INT0_SRCFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ 3210 #define DMA_INT0_SRCFLG_CH16 ((uint32_t)0x00010000) /*!< Channel 16 was the source of DMA_INT0 */ 3211 /* DMA_INT0_SRCFLG[CH17] Bits */ 3212 #define DMA_INT0_SRCFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ 3213 #define DMA_INT0_SRCFLG_CH17 ((uint32_t)0x00020000) /*!< Channel 17 was the source of DMA_INT0 */ 3214 /* DMA_INT0_SRCFLG[CH18] Bits */ 3215 #define DMA_INT0_SRCFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ 3216 #define DMA_INT0_SRCFLG_CH18 ((uint32_t)0x00040000) /*!< Channel 18 was the source of DMA_INT0 */ 3217 /* DMA_INT0_SRCFLG[CH19] Bits */ 3218 #define DMA_INT0_SRCFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ 3219 #define DMA_INT0_SRCFLG_CH19 ((uint32_t)0x00080000) /*!< Channel 19 was the source of DMA_INT0 */ 3220 /* DMA_INT0_SRCFLG[CH20] Bits */ 3221 #define DMA_INT0_SRCFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ 3222 #define DMA_INT0_SRCFLG_CH20 ((uint32_t)0x00100000) /*!< Channel 20 was the source of DMA_INT0 */ 3223 /* DMA_INT0_SRCFLG[CH21] Bits */ 3224 #define DMA_INT0_SRCFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ 3225 #define DMA_INT0_SRCFLG_CH21 ((uint32_t)0x00200000) /*!< Channel 21 was the source of DMA_INT0 */ 3226 /* DMA_INT0_SRCFLG[CH22] Bits */ 3227 #define DMA_INT0_SRCFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ 3228 #define DMA_INT0_SRCFLG_CH22 ((uint32_t)0x00400000) /*!< Channel 22 was the source of DMA_INT0 */ 3229 /* DMA_INT0_SRCFLG[CH23] Bits */ 3230 #define DMA_INT0_SRCFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ 3231 #define DMA_INT0_SRCFLG_CH23 ((uint32_t)0x00800000) /*!< Channel 23 was the source of DMA_INT0 */ 3232 /* DMA_INT0_SRCFLG[CH24] Bits */ 3233 #define DMA_INT0_SRCFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ 3234 #define DMA_INT0_SRCFLG_CH24 ((uint32_t)0x01000000) /*!< Channel 24 was the source of DMA_INT0 */ 3235 /* DMA_INT0_SRCFLG[CH25] Bits */ 3236 #define DMA_INT0_SRCFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ 3237 #define DMA_INT0_SRCFLG_CH25 ((uint32_t)0x02000000) /*!< Channel 25 was the source of DMA_INT0 */ 3238 /* DMA_INT0_SRCFLG[CH26] Bits */ 3239 #define DMA_INT0_SRCFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ 3240 #define DMA_INT0_SRCFLG_CH26 ((uint32_t)0x04000000) /*!< Channel 26 was the source of DMA_INT0 */ 3241 /* DMA_INT0_SRCFLG[CH27] Bits */ 3242 #define DMA_INT0_SRCFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ 3243 #define DMA_INT0_SRCFLG_CH27 ((uint32_t)0x08000000) /*!< Channel 27 was the source of DMA_INT0 */ 3244 /* DMA_INT0_SRCFLG[CH28] Bits */ 3245 #define DMA_INT0_SRCFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ 3246 #define DMA_INT0_SRCFLG_CH28 ((uint32_t)0x10000000) /*!< Channel 28 was the source of DMA_INT0 */ 3247 /* DMA_INT0_SRCFLG[CH29] Bits */ 3248 #define DMA_INT0_SRCFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ 3249 #define DMA_INT0_SRCFLG_CH29 ((uint32_t)0x20000000) /*!< Channel 29 was the source of DMA_INT0 */ 3250 /* DMA_INT0_SRCFLG[CH30] Bits */ 3251 #define DMA_INT0_SRCFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ 3252 #define DMA_INT0_SRCFLG_CH30 ((uint32_t)0x40000000) /*!< Channel 30 was the source of DMA_INT0 */ 3253 /* DMA_INT0_SRCFLG[CH31] Bits */ 3254 #define DMA_INT0_SRCFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ 3255 #define DMA_INT0_SRCFLG_CH31 ((uint32_t)0x80000000) /*!< Channel 31 was the source of DMA_INT0 */ 3256 /* DMA_INT0_CLRFLG[CH0] Bits */ 3257 #define DMA_INT0_CLRFLG_CH0_OFS ( 0) /*!< CH0 Bit Offset */ 3258 #define DMA_INT0_CLRFLG_CH0 ((uint32_t)0x00000001) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3259 /* DMA_INT0_CLRFLG[CH1] Bits */ 3260 #define DMA_INT0_CLRFLG_CH1_OFS ( 1) /*!< CH1 Bit Offset */ 3261 #define DMA_INT0_CLRFLG_CH1 ((uint32_t)0x00000002) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3262 /* DMA_INT0_CLRFLG[CH2] Bits */ 3263 #define DMA_INT0_CLRFLG_CH2_OFS ( 2) /*!< CH2 Bit Offset */ 3264 #define DMA_INT0_CLRFLG_CH2 ((uint32_t)0x00000004) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3265 /* DMA_INT0_CLRFLG[CH3] Bits */ 3266 #define DMA_INT0_CLRFLG_CH3_OFS ( 3) /*!< CH3 Bit Offset */ 3267 #define DMA_INT0_CLRFLG_CH3 ((uint32_t)0x00000008) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3268 /* DMA_INT0_CLRFLG[CH4] Bits */ 3269 #define DMA_INT0_CLRFLG_CH4_OFS ( 4) /*!< CH4 Bit Offset */ 3270 #define DMA_INT0_CLRFLG_CH4 ((uint32_t)0x00000010) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3271 /* DMA_INT0_CLRFLG[CH5] Bits */ 3272 #define DMA_INT0_CLRFLG_CH5_OFS ( 5) /*!< CH5 Bit Offset */ 3273 #define DMA_INT0_CLRFLG_CH5 ((uint32_t)0x00000020) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3274 /* DMA_INT0_CLRFLG[CH6] Bits */ 3275 #define DMA_INT0_CLRFLG_CH6_OFS ( 6) /*!< CH6 Bit Offset */ 3276 #define DMA_INT0_CLRFLG_CH6 ((uint32_t)0x00000040) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3277 /* DMA_INT0_CLRFLG[CH7] Bits */ 3278 #define DMA_INT0_CLRFLG_CH7_OFS ( 7) /*!< CH7 Bit Offset */ 3279 #define DMA_INT0_CLRFLG_CH7 ((uint32_t)0x00000080) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3280 /* DMA_INT0_CLRFLG[CH8] Bits */ 3281 #define DMA_INT0_CLRFLG_CH8_OFS ( 8) /*!< CH8 Bit Offset */ 3282 #define DMA_INT0_CLRFLG_CH8 ((uint32_t)0x00000100) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3283 /* DMA_INT0_CLRFLG[CH9] Bits */ 3284 #define DMA_INT0_CLRFLG_CH9_OFS ( 9) /*!< CH9 Bit Offset */ 3285 #define DMA_INT0_CLRFLG_CH9 ((uint32_t)0x00000200) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3286 /* DMA_INT0_CLRFLG[CH10] Bits */ 3287 #define DMA_INT0_CLRFLG_CH10_OFS (10) /*!< CH10 Bit Offset */ 3288 #define DMA_INT0_CLRFLG_CH10 ((uint32_t)0x00000400) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3289 /* DMA_INT0_CLRFLG[CH11] Bits */ 3290 #define DMA_INT0_CLRFLG_CH11_OFS (11) /*!< CH11 Bit Offset */ 3291 #define DMA_INT0_CLRFLG_CH11 ((uint32_t)0x00000800) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3292 /* DMA_INT0_CLRFLG[CH12] Bits */ 3293 #define DMA_INT0_CLRFLG_CH12_OFS (12) /*!< CH12 Bit Offset */ 3294 #define DMA_INT0_CLRFLG_CH12 ((uint32_t)0x00001000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3295 /* DMA_INT0_CLRFLG[CH13] Bits */ 3296 #define DMA_INT0_CLRFLG_CH13_OFS (13) /*!< CH13 Bit Offset */ 3297 #define DMA_INT0_CLRFLG_CH13 ((uint32_t)0x00002000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3298 /* DMA_INT0_CLRFLG[CH14] Bits */ 3299 #define DMA_INT0_CLRFLG_CH14_OFS (14) /*!< CH14 Bit Offset */ 3300 #define DMA_INT0_CLRFLG_CH14 ((uint32_t)0x00004000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3301 /* DMA_INT0_CLRFLG[CH15] Bits */ 3302 #define DMA_INT0_CLRFLG_CH15_OFS (15) /*!< CH15 Bit Offset */ 3303 #define DMA_INT0_CLRFLG_CH15 ((uint32_t)0x00008000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3304 /* DMA_INT0_CLRFLG[CH16] Bits */ 3305 #define DMA_INT0_CLRFLG_CH16_OFS (16) /*!< CH16 Bit Offset */ 3306 #define DMA_INT0_CLRFLG_CH16 ((uint32_t)0x00010000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3307 /* DMA_INT0_CLRFLG[CH17] Bits */ 3308 #define DMA_INT0_CLRFLG_CH17_OFS (17) /*!< CH17 Bit Offset */ 3309 #define DMA_INT0_CLRFLG_CH17 ((uint32_t)0x00020000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3310 /* DMA_INT0_CLRFLG[CH18] Bits */ 3311 #define DMA_INT0_CLRFLG_CH18_OFS (18) /*!< CH18 Bit Offset */ 3312 #define DMA_INT0_CLRFLG_CH18 ((uint32_t)0x00040000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3313 /* DMA_INT0_CLRFLG[CH19] Bits */ 3314 #define DMA_INT0_CLRFLG_CH19_OFS (19) /*!< CH19 Bit Offset */ 3315 #define DMA_INT0_CLRFLG_CH19 ((uint32_t)0x00080000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3316 /* DMA_INT0_CLRFLG[CH20] Bits */ 3317 #define DMA_INT0_CLRFLG_CH20_OFS (20) /*!< CH20 Bit Offset */ 3318 #define DMA_INT0_CLRFLG_CH20 ((uint32_t)0x00100000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3319 /* DMA_INT0_CLRFLG[CH21] Bits */ 3320 #define DMA_INT0_CLRFLG_CH21_OFS (21) /*!< CH21 Bit Offset */ 3321 #define DMA_INT0_CLRFLG_CH21 ((uint32_t)0x00200000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3322 /* DMA_INT0_CLRFLG[CH22] Bits */ 3323 #define DMA_INT0_CLRFLG_CH22_OFS (22) /*!< CH22 Bit Offset */ 3324 #define DMA_INT0_CLRFLG_CH22 ((uint32_t)0x00400000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3325 /* DMA_INT0_CLRFLG[CH23] Bits */ 3326 #define DMA_INT0_CLRFLG_CH23_OFS (23) /*!< CH23 Bit Offset */ 3327 #define DMA_INT0_CLRFLG_CH23 ((uint32_t)0x00800000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3328 /* DMA_INT0_CLRFLG[CH24] Bits */ 3329 #define DMA_INT0_CLRFLG_CH24_OFS (24) /*!< CH24 Bit Offset */ 3330 #define DMA_INT0_CLRFLG_CH24 ((uint32_t)0x01000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3331 /* DMA_INT0_CLRFLG[CH25] Bits */ 3332 #define DMA_INT0_CLRFLG_CH25_OFS (25) /*!< CH25 Bit Offset */ 3333 #define DMA_INT0_CLRFLG_CH25 ((uint32_t)0x02000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3334 /* DMA_INT0_CLRFLG[CH26] Bits */ 3335 #define DMA_INT0_CLRFLG_CH26_OFS (26) /*!< CH26 Bit Offset */ 3336 #define DMA_INT0_CLRFLG_CH26 ((uint32_t)0x04000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3337 /* DMA_INT0_CLRFLG[CH27] Bits */ 3338 #define DMA_INT0_CLRFLG_CH27_OFS (27) /*!< CH27 Bit Offset */ 3339 #define DMA_INT0_CLRFLG_CH27 ((uint32_t)0x08000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3340 /* DMA_INT0_CLRFLG[CH28] Bits */ 3341 #define DMA_INT0_CLRFLG_CH28_OFS (28) /*!< CH28 Bit Offset */ 3342 #define DMA_INT0_CLRFLG_CH28 ((uint32_t)0x10000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3343 /* DMA_INT0_CLRFLG[CH29] Bits */ 3344 #define DMA_INT0_CLRFLG_CH29_OFS (29) /*!< CH29 Bit Offset */ 3345 #define DMA_INT0_CLRFLG_CH29 ((uint32_t)0x20000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3346 /* DMA_INT0_CLRFLG[CH30] Bits */ 3347 #define DMA_INT0_CLRFLG_CH30_OFS (30) /*!< CH30 Bit Offset */ 3348 #define DMA_INT0_CLRFLG_CH30 ((uint32_t)0x40000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3349 /* DMA_INT0_CLRFLG[CH31] Bits */ 3350 #define DMA_INT0_CLRFLG_CH31_OFS (31) /*!< CH31 Bit Offset */ 3351 #define DMA_INT0_CLRFLG_CH31 ((uint32_t)0x80000000) /*!< Clear corresponding DMA_INT0_SRCFLG_REG */ 3352 /* DMA_STAT[MASTEN] Bits */ 3353 #define DMA_STAT_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ 3354 #define DMA_STAT_MASTEN ((uint32_t)0x00000001) 3355 /* DMA_STAT[STATE] Bits */ 3356 #define DMA_STAT_STATE_OFS ( 4) /*!< STATE Bit Offset */ 3357 #define DMA_STAT_STATE_MASK ((uint32_t)0x000000F0) /*!< STATE Bit Mask */ 3358 #define DMA_STAT_STATE0 ((uint32_t)0x00000010) /*!< STATE Bit 0 */ 3359 #define DMA_STAT_STATE1 ((uint32_t)0x00000020) /*!< STATE Bit 1 */ 3360 #define DMA_STAT_STATE2 ((uint32_t)0x00000040) /*!< STATE Bit 2 */ 3361 #define DMA_STAT_STATE3 ((uint32_t)0x00000080) /*!< STATE Bit 3 */ 3362 #define DMA_STAT_STATE_0 ((uint32_t)0x00000000) /*!< idle */ 3363 #define DMA_STAT_STATE_1 ((uint32_t)0x00000010) /*!< reading channel controller data */ 3364 #define DMA_STAT_STATE_2 ((uint32_t)0x00000020) /*!< reading source data end pointer */ 3365 #define DMA_STAT_STATE_3 ((uint32_t)0x00000030) /*!< reading destination data end pointer */ 3366 #define DMA_STAT_STATE_4 ((uint32_t)0x00000040) /*!< reading source data */ 3367 #define DMA_STAT_STATE_5 ((uint32_t)0x00000050) /*!< writing destination data */ 3368 #define DMA_STAT_STATE_6 ((uint32_t)0x00000060) /*!< waiting for DMA request to clear */ 3369 #define DMA_STAT_STATE_7 ((uint32_t)0x00000070) /*!< writing channel controller data */ 3370 #define DMA_STAT_STATE_8 ((uint32_t)0x00000080) /*!< stalled */ 3371 #define DMA_STAT_STATE_9 ((uint32_t)0x00000090) /*!< done */ 3372 #define DMA_STAT_STATE_10 ((uint32_t)0x000000A0) /*!< peripheral scatter-gather transition */ 3373 #define DMA_STAT_STATE_11 ((uint32_t)0x000000B0) /*!< Reserved */ 3374 #define DMA_STAT_STATE_12 ((uint32_t)0x000000C0) /*!< Reserved */ 3375 #define DMA_STAT_STATE_13 ((uint32_t)0x000000D0) /*!< Reserved */ 3376 #define DMA_STAT_STATE_14 ((uint32_t)0x000000E0) /*!< Reserved */ 3377 #define DMA_STAT_STATE_15 ((uint32_t)0x000000F0) /*!< Reserved */ 3378 /* DMA_STAT[DMACHANS] Bits */ 3379 #define DMA_STAT_DMACHANS_OFS (16) /*!< DMACHANS Bit Offset */ 3380 #define DMA_STAT_DMACHANS_MASK ((uint32_t)0x001F0000) /*!< DMACHANS Bit Mask */ 3381 #define DMA_STAT_DMACHANS0 ((uint32_t)0x00010000) /*!< DMACHANS Bit 0 */ 3382 #define DMA_STAT_DMACHANS1 ((uint32_t)0x00020000) /*!< DMACHANS Bit 1 */ 3383 #define DMA_STAT_DMACHANS2 ((uint32_t)0x00040000) /*!< DMACHANS Bit 2 */ 3384 #define DMA_STAT_DMACHANS3 ((uint32_t)0x00080000) /*!< DMACHANS Bit 3 */ 3385 #define DMA_STAT_DMACHANS4 ((uint32_t)0x00100000) /*!< DMACHANS Bit 4 */ 3386 #define DMA_STAT_DMACHANS_0 ((uint32_t)0x00000000) /*!< Controller configured to use 1 DMA channel */ 3387 #define DMA_STAT_DMACHANS_1 ((uint32_t)0x00010000) /*!< Controller configured to use 2 DMA channels */ 3388 #define DMA_STAT_DMACHANS_30 ((uint32_t)0x001E0000) /*!< Controller configured to use 31 DMA channels */ 3389 #define DMA_STAT_DMACHANS_31 ((uint32_t)0x001F0000) /*!< Controller configured to use 32 DMA channels */ 3390 /* DMA_STAT[TESTSTAT] Bits */ 3391 #define DMA_STAT_TESTSTAT_OFS (28) /*!< TESTSTAT Bit Offset */ 3392 #define DMA_STAT_TESTSTAT_MASK ((uint32_t)0xF0000000) /*!< TESTSTAT Bit Mask */ 3393 #define DMA_STAT_TESTSTAT0 ((uint32_t)0x10000000) /*!< TESTSTAT Bit 0 */ 3394 #define DMA_STAT_TESTSTAT1 ((uint32_t)0x20000000) /*!< TESTSTAT Bit 1 */ 3395 #define DMA_STAT_TESTSTAT2 ((uint32_t)0x40000000) /*!< TESTSTAT Bit 2 */ 3396 #define DMA_STAT_TESTSTAT3 ((uint32_t)0x80000000) /*!< TESTSTAT Bit 3 */ 3397 #define DMA_STAT_TESTSTAT_0 ((uint32_t)0x00000000) /*!< Controller does not include the integration test logic */ 3398 #define DMA_STAT_TESTSTAT_1 ((uint32_t)0x10000000) /*!< Controller includes the integration test logic */ 3399 /* DMA_CFG[MASTEN] Bits */ 3400 #define DMA_CFG_MASTEN_OFS ( 0) /*!< MASTEN Bit Offset */ 3401 #define DMA_CFG_MASTEN ((uint32_t)0x00000001) 3402 /* DMA_CFG[CHPROTCTRL] Bits */ 3403 #define DMA_CFG_CHPROTCTRL_OFS ( 5) /*!< CHPROTCTRL Bit Offset */ 3404 #define DMA_CFG_CHPROTCTRL_MASK ((uint32_t)0x000000E0) /*!< CHPROTCTRL Bit Mask */ 3405 /* DMA_CTLBASE[ADDR] Bits */ 3406 #define DMA_CTLBASE_ADDR_OFS ( 5) /*!< ADDR Bit Offset */ 3407 #define DMA_CTLBASE_ADDR_MASK ((uint32_t)0xFFFFFFE0) /*!< ADDR Bit Mask */ 3408 /* DMA_ERRCLR[ERRCLR] Bits */ 3409 #define DMA_ERRCLR_ERRCLR_OFS ( 0) /*!< ERRCLR Bit Offset */ 3410 #define DMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) 3411 /* DMA channel definitions and memory structure alignment */ 3412 #define __MCU_NUM_DMA_CHANNELS__ 8 3413 #define DMA_CHANNEL_CONTROL_STRUCT_SIZE 0x10 3414 #define DMA_CONTROL_MEMORY_ALIGNMENT (__MCU_NUM_DMA_CHANNELS__ * DMA_CHANNEL_CONTROL_STRUCT_SIZE) 3415 3416 /* UDMA_STAT Control Bits */ 3417 #define UDMA_STAT_DMACHANS_M ((uint32_t)0x001F0000) /*!< Available uDMA Channels Minus 1 */ 3418 #define UDMA_STAT_STATE_M ((uint32_t)0x000000F0) /*!< Control State Machine Status */ 3419 #define UDMA_STAT_STATE_IDLE ((uint32_t)0x00000000) /*!< Idle */ 3420 #define UDMA_STAT_STATE_RD_CTRL ((uint32_t)0x00000010) /*!< Reading channel controller data */ 3421 #define UDMA_STAT_STATE_RD_SRCENDP ((uint32_t)0x00000020) /*!< Reading source end pointer */ 3422 #define UDMA_STAT_STATE_RD_DSTENDP ((uint32_t)0x00000030) /*!< Reading destination end pointer */ 3423 #define UDMA_STAT_STATE_RD_SRCDAT ((uint32_t)0x00000040) /*!< Reading source data */ 3424 #define UDMA_STAT_STATE_WR_DSTDAT ((uint32_t)0x00000050) /*!< Writing destination data */ 3425 #define UDMA_STAT_STATE_WAIT ((uint32_t)0x00000060) /*!< Waiting for uDMA request to clear */ 3426 #define UDMA_STAT_STATE_WR_CTRL ((uint32_t)0x00000070) /*!< Writing channel controller data */ 3427 #define UDMA_STAT_STATE_STALL ((uint32_t)0x00000080) /*!< Stalled */ 3428 #define UDMA_STAT_STATE_DONE ((uint32_t)0x00000090) /*!< Done */ 3429 #define UDMA_STAT_STATE_UNDEF ((uint32_t)0x000000A0) /*!< Undefined */ 3430 #define UDMA_STAT_MASTEN ((uint32_t)0x00000001) /*!< Master Enable Status */ 3431 #define UDMA_STAT_DMACHANS_S (16) 3432 3433 /* UDMA_CFG Control Bits */ 3434 #define UDMA_CFG_MASTEN ((uint32_t)0x00000001) /*!< Controller Master Enable */ 3435 3436 /* UDMA_CTLBASE Control Bits */ 3437 #define UDMA_CTLBASE_ADDR_M ((uint32_t)0xFFFFFC00) /*!< Channel Control Base Address */ 3438 #define UDMA_CTLBASE_ADDR_S (10) 3439 3440 /* UDMA_ALTBASE Control Bits */ 3441 #define UDMA_ALTBASE_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Alternate Channel Address Pointer */ 3442 #define UDMA_ALTBASE_ADDR_S ( 0) 3443 3444 /* UDMA_WAITSTAT Control Bits */ 3445 #define UDMA_WAITSTAT_WAITREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Wait Status */ 3446 3447 /* UDMA_SWREQ Control Bits */ 3448 #define UDMA_SWREQ_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Software Request */ 3449 3450 /* UDMA_USEBURSTSET Control Bits */ 3451 #define UDMA_USEBURSTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Set */ 3452 3453 /* UDMA_USEBURSTCLR Control Bits */ 3454 #define UDMA_USEBURSTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Useburst Clear */ 3455 3456 /* UDMA_REQMASKSET Control Bits */ 3457 #define UDMA_REQMASKSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Set */ 3458 3459 /* UDMA_REQMASKCLR Control Bits */ 3460 #define UDMA_REQMASKCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Request Mask Clear */ 3461 3462 /* UDMA_ENASET Control Bits */ 3463 #define UDMA_ENASET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Enable Set */ 3464 3465 /* UDMA_ENACLR Control Bits */ 3466 #define UDMA_ENACLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Clear Channel [n] Enable Clear */ 3467 3468 /* UDMA_ALTSET Control Bits */ 3469 #define UDMA_ALTSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Set */ 3470 3471 /* UDMA_ALTCLR Control Bits */ 3472 #define UDMA_ALTCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Alternate Clear */ 3473 3474 /* UDMA_PRIOSET Control Bits */ 3475 #define UDMA_PRIOSET_SET_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Set */ 3476 3477 /* UDMA_PRIOCLR Control Bits */ 3478 #define UDMA_PRIOCLR_CLR_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Priority Clear */ 3479 3480 /* UDMA_ERRCLR Control Bits */ 3481 #define UDMA_ERRCLR_ERRCLR ((uint32_t)0x00000001) /*!< uDMA Bus Error Status */ 3482 3483 /* UDMA_CHASGN Control Bits */ 3484 #define UDMA_CHASGN_M ((uint32_t)0xFFFFFFFF) /*!< Channel [n] Assignment Select */ 3485 #define UDMA_CHASGN_PRIMARY ((uint32_t)0x00000000) /*!< Use the primary channel assignment */ 3486 #define UDMA_CHASGN_SECONDARY ((uint32_t)0x00000001) /*!< Use the secondary channel assignment */ 3487 3488 /* Micro Direct Memory Access (uDMA) offsets */ 3489 #define UDMA_O_SRCENDP ((uint32_t)0x00000000) /*!< DMA Channel Source Address End Pointer */ 3490 #define UDMA_O_DSTENDP ((uint32_t)0x00000004) /*!< DMA Channel Destination Address End Pointer */ 3491 #define UDMA_O_CHCTL ((uint32_t)0x00000008) /*!< DMA Channel Control Word */ 3492 3493 /* UDMA_O_SRCENDP Control Bits */ 3494 #define UDMA_SRCENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Source Address End Pointer */ 3495 #define UDMA_SRCENDP_ADDR_S ( 0) 3496 3497 /* UDMA_O_DSTENDP Control Bits */ 3498 #define UDMA_DSTENDP_ADDR_M ((uint32_t)0xFFFFFFFF) /*!< Destination Address End Pointer */ 3499 #define UDMA_DSTENDP_ADDR_S ( 0) 3500 3501 /* UDMA_O_CHCTL Control Bits */ 3502 #define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /*!< Destination Address Increment */ 3503 #define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /*!< Byte */ 3504 #define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /*!< Half-word */ 3505 #define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /*!< Word */ 3506 #define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /*!< No increment */ 3507 #define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /*!< Destination Data Size */ 3508 #define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ 3509 #define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /*!< Half-word */ 3510 #define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /*!< Word */ 3511 #define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /*!< Source Address Increment */ 3512 #define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /*!< Byte */ 3513 #define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /*!< Half-word */ 3514 #define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /*!< Word */ 3515 #define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /*!< No increment */ 3516 #define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /*!< Source Data Size */ 3517 #define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /*!< Byte */ 3518 #define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /*!< Half-word */ 3519 #define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /*!< Word */ 3520 #define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /*!< Arbitration Size */ 3521 #define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /*!< 1 Transfer */ 3522 #define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /*!< 2 Transfers */ 3523 #define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /*!< 4 Transfers */ 3524 #define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /*!< 8 Transfers */ 3525 #define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /*!< 16 Transfers */ 3526 #define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /*!< 32 Transfers */ 3527 #define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /*!< 64 Transfers */ 3528 #define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /*!< 128 Transfers */ 3529 #define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /*!< 256 Transfers */ 3530 #define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /*!< 512 Transfers */ 3531 #define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /*!< 1024 Transfers */ 3532 #define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /*!< Transfer Size (minus 1) */ 3533 #define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /*!< Next Useburst */ 3534 #define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /*!< uDMA Transfer Mode */ 3535 #define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /*!< Stop */ 3536 #define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /*!< Basic */ 3537 #define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /*!< Auto-Request */ 3538 #define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /*!< Ping-Pong */ 3539 #define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /*!< Memory Scatter-Gather */ 3540 #define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /*!< Alternate Memory Scatter-Gather */ 3541 #define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /*!< Peripheral Scatter-Gather */ 3542 #define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /*!< Alternate Peripheral Scatter-Gather */ 3543 3544 #define UDMA_CHCTL_XFERSIZE_S ( 4) 3545 3546 3547 /****************************************************************************** 3548 * DWT Bits 3549 ******************************************************************************/ 3550 3551 3552 /****************************************************************************** 3553 * EUSCI_A Bits 3554 ******************************************************************************/ 3555 /* EUSCI_A_CTLW0[SWRST] Bits */ 3556 #define EUSCI_A_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ 3557 #define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ 3558 /* EUSCI_A_CTLW0[TXBRK] Bits */ 3559 #define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /*!< UCTXBRK Bit Offset */ 3560 #define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /*!< Transmit break */ 3561 /* EUSCI_A_CTLW0[TXADDR] Bits */ 3562 #define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /*!< UCTXADDR Bit Offset */ 3563 #define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /*!< Transmit address */ 3564 /* EUSCI_A_CTLW0[DORM] Bits */ 3565 #define EUSCI_A_CTLW0_DORM_OFS ( 3) /*!< UCDORM Bit Offset */ 3566 #define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /*!< Dormant */ 3567 /* EUSCI_A_CTLW0[BRKIE] Bits */ 3568 #define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /*!< UCBRKIE Bit Offset */ 3569 #define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /*!< Receive break character interrupt enable */ 3570 /* EUSCI_A_CTLW0[RXEIE] Bits */ 3571 #define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /*!< UCRXEIE Bit Offset */ 3572 #define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /*!< Receive erroneous-character interrupt enable */ 3573 /* EUSCI_A_CTLW0[SSEL] Bits */ 3574 #define EUSCI_A_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ 3575 #define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ 3576 #define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ 3577 #define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ 3578 #define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLK */ 3579 #define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ 3580 #define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ 3581 #define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /*!< UCLK */ 3582 #define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ 3583 #define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ 3584 /* EUSCI_A_CTLW0[SYNC] Bits */ 3585 #define EUSCI_A_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ 3586 #define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ 3587 /* EUSCI_A_CTLW0[MODE] Bits */ 3588 #define EUSCI_A_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ 3589 #define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ 3590 #define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ 3591 #define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ 3592 #define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< UART mode */ 3593 #define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< Idle-line multiprocessor mode */ 3594 #define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< Address-bit multiprocessor mode */ 3595 #define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< UART mode with automatic baud-rate detection */ 3596 /* EUSCI_A_CTLW0[SPB] Bits */ 3597 #define EUSCI_A_CTLW0_SPB_OFS (11) /*!< UCSPB Bit Offset */ 3598 #define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /*!< Stop bit select */ 3599 /* EUSCI_A_CTLW0[SEVENBIT] Bits */ 3600 #define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ 3601 #define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ 3602 /* EUSCI_A_CTLW0[MSB] Bits */ 3603 #define EUSCI_A_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ 3604 #define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ 3605 /* EUSCI_A_CTLW0[PAR] Bits */ 3606 #define EUSCI_A_CTLW0_PAR_OFS (14) /*!< UCPAR Bit Offset */ 3607 #define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /*!< Parity select */ 3608 /* EUSCI_A_CTLW0[PEN] Bits */ 3609 #define EUSCI_A_CTLW0_PEN_OFS (15) /*!< UCPEN Bit Offset */ 3610 #define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /*!< Parity enable */ 3611 /* EUSCI_A_CTLW0[STEM] Bits */ 3612 #define EUSCI_A_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ 3613 #define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ 3614 /* EUSCI_A_CTLW0[MST] Bits */ 3615 #define EUSCI_A_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ 3616 #define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ 3617 /* EUSCI_A_CTLW0[CKPL] Bits */ 3618 #define EUSCI_A_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ 3619 #define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ 3620 /* EUSCI_A_CTLW0[CKPH] Bits */ 3621 #define EUSCI_A_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ 3622 #define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ 3623 /* EUSCI_A_CTLW1[GLIT] Bits */ 3624 #define EUSCI_A_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ 3625 #define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ 3626 #define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ 3627 #define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ 3628 #define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< Approximately 2 ns (equivalent of 1 delay element) */ 3629 #define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< Approximately 50 ns */ 3630 #define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< Approximately 100 ns */ 3631 #define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< Approximately 200 ns */ 3632 /* EUSCI_A_MCTLW[OS16] Bits */ 3633 #define EUSCI_A_MCTLW_OS16_OFS ( 0) /*!< UCOS16 Bit Offset */ 3634 #define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /*!< Oversampling mode enabled */ 3635 /* EUSCI_A_MCTLW[BRF] Bits */ 3636 #define EUSCI_A_MCTLW_BRF_OFS ( 4) /*!< UCBRF Bit Offset */ 3637 #define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /*!< UCBRF Bit Mask */ 3638 /* EUSCI_A_MCTLW[BRS] Bits */ 3639 #define EUSCI_A_MCTLW_BRS_OFS ( 8) /*!< UCBRS Bit Offset */ 3640 #define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /*!< UCBRS Bit Mask */ 3641 /* EUSCI_A_STATW[BUSY] Bits */ 3642 #define EUSCI_A_STATW_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ 3643 #define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ 3644 /* EUSCI_A_STATW[ADDR_IDLE] Bits */ 3645 #define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /*!< UCADDR_UCIDLE Bit Offset */ 3646 #define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /*!< Address received / Idle line detected */ 3647 /* EUSCI_A_STATW[RXERR] Bits */ 3648 #define EUSCI_A_STATW_RXERR_OFS ( 2) /*!< UCRXERR Bit Offset */ 3649 #define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /*!< Receive error flag */ 3650 /* EUSCI_A_STATW[BRK] Bits */ 3651 #define EUSCI_A_STATW_BRK_OFS ( 3) /*!< UCBRK Bit Offset */ 3652 #define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /*!< Break detect flag */ 3653 /* EUSCI_A_STATW[PE] Bits */ 3654 #define EUSCI_A_STATW_PE_OFS ( 4) /*!< UCPE Bit Offset */ 3655 #define EUSCI_A_STATW_PE ((uint16_t)0x0010) 3656 /* EUSCI_A_STATW[OE] Bits */ 3657 #define EUSCI_A_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ 3658 #define EUSCI_A_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ 3659 /* EUSCI_A_STATW[FE] Bits */ 3660 #define EUSCI_A_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ 3661 #define EUSCI_A_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ 3662 /* EUSCI_A_STATW[LISTEN] Bits */ 3663 #define EUSCI_A_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ 3664 #define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ 3665 /* EUSCI_A_STATW[SPI_BUSY] Bits */ 3666 #define EUSCI_A_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ 3667 #define EUSCI_A_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_A busy */ 3668 /* EUSCI_A_RXBUF[RXBUF] Bits */ 3669 #define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ 3670 #define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ 3671 /* EUSCI_A_TXBUF[TXBUF] Bits */ 3672 #define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ 3673 #define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ 3674 /* EUSCI_A_ABCTL[ABDEN] Bits */ 3675 #define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /*!< UCABDEN Bit Offset */ 3676 #define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /*!< Automatic baud-rate detect enable */ 3677 /* EUSCI_A_ABCTL[BTOE] Bits */ 3678 #define EUSCI_A_ABCTL_BTOE_OFS ( 2) /*!< UCBTOE Bit Offset */ 3679 #define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /*!< Break time out error */ 3680 /* EUSCI_A_ABCTL[STOE] Bits */ 3681 #define EUSCI_A_ABCTL_STOE_OFS ( 3) /*!< UCSTOE Bit Offset */ 3682 #define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /*!< Synch field time out error */ 3683 /* EUSCI_A_ABCTL[DELIM] Bits */ 3684 #define EUSCI_A_ABCTL_DELIM_OFS ( 4) /*!< UCDELIM Bit Offset */ 3685 #define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /*!< UCDELIM Bit Mask */ 3686 #define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /*!< DELIM Bit 0 */ 3687 #define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /*!< DELIM Bit 1 */ 3688 #define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /*!< 1 bit time */ 3689 #define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /*!< 2 bit times */ 3690 #define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /*!< 3 bit times */ 3691 #define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /*!< 4 bit times */ 3692 /* EUSCI_A_IRCTL[IREN] Bits */ 3693 #define EUSCI_A_IRCTL_IREN_OFS ( 0) /*!< UCIREN Bit Offset */ 3694 #define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /*!< IrDA encoder/decoder enable */ 3695 /* EUSCI_A_IRCTL[IRTXCLK] Bits */ 3696 #define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /*!< UCIRTXCLK Bit Offset */ 3697 #define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /*!< IrDA transmit pulse clock select */ 3698 /* EUSCI_A_IRCTL[IRTXPL] Bits */ 3699 #define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /*!< UCIRTXPL Bit Offset */ 3700 #define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /*!< UCIRTXPL Bit Mask */ 3701 /* EUSCI_A_IRCTL[IRRXFE] Bits */ 3702 #define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /*!< UCIRRXFE Bit Offset */ 3703 #define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /*!< IrDA receive filter enabled */ 3704 /* EUSCI_A_IRCTL[IRRXPL] Bits */ 3705 #define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /*!< UCIRRXPL Bit Offset */ 3706 #define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /*!< IrDA receive input UCAxRXD polarity */ 3707 /* EUSCI_A_IRCTL[IRRXFL] Bits */ 3708 #define EUSCI_A_IRCTL_IRRXFL_OFS (10) /*!< UCIRRXFL Bit Offset */ 3709 #define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /*!< UCIRRXFL Bit Mask */ 3710 /* EUSCI_A_IE[RXIE] Bits */ 3711 #define EUSCI_A_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ 3712 #define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ 3713 /* EUSCI_A_IE[TXIE] Bits */ 3714 #define EUSCI_A_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ 3715 #define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ 3716 /* EUSCI_A_IE[STTIE] Bits */ 3717 #define EUSCI_A_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ 3718 #define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /*!< Start bit interrupt enable */ 3719 /* EUSCI_A_IE[TXCPTIE] Bits */ 3720 #define EUSCI_A_IE_TXCPTIE_OFS ( 3) /*!< UCTXCPTIE Bit Offset */ 3721 #define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /*!< Transmit complete interrupt enable */ 3722 /* EUSCI_A_IFG[RXIFG] Bits */ 3723 #define EUSCI_A_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ 3724 #define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ 3725 /* EUSCI_A_IFG[TXIFG] Bits */ 3726 #define EUSCI_A_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ 3727 #define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ 3728 /* EUSCI_A_IFG[STTIFG] Bits */ 3729 #define EUSCI_A_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ 3730 #define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /*!< Start bit interrupt flag */ 3731 /* EUSCI_A_IFG[TXCPTIFG] Bits */ 3732 #define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /*!< UCTXCPTIFG Bit Offset */ 3733 #define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /*!< Transmit ready interrupt enable */ 3734 /* legacy definitions for backward compatibility to version 2100 */ 3735 #define EUSCI_A__RXIE_OFS EUSCI_A_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ 3736 #define EUSCI_A__RXIE EUSCI_A_IE_RXIE /*!< Receive interrupt enable */ 3737 #define EUSCI_A__TXIE_OFS EUSCI_A_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ 3738 #define EUSCI_A__TXIE EUSCI_A_IE_TXIE /*!< Transmit interrupt enable */ 3739 3740 3741 /****************************************************************************** 3742 * EUSCI_B Bits 3743 ******************************************************************************/ 3744 /* EUSCI_B_CTLW0[SWRST] Bits */ 3745 #define EUSCI_B_CTLW0_SWRST_OFS ( 0) /*!< UCSWRST Bit Offset */ 3746 #define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /*!< Software reset enable */ 3747 /* EUSCI_B_CTLW0[TXSTT] Bits */ 3748 #define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /*!< UCTXSTT Bit Offset */ 3749 #define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /*!< Transmit START condition in master mode */ 3750 /* EUSCI_B_CTLW0[TXSTP] Bits */ 3751 #define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /*!< UCTXSTP Bit Offset */ 3752 #define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /*!< Transmit STOP condition in master mode */ 3753 /* EUSCI_B_CTLW0[TXNACK] Bits */ 3754 #define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /*!< UCTXNACK Bit Offset */ 3755 #define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /*!< Transmit a NACK */ 3756 /* EUSCI_B_CTLW0[TR] Bits */ 3757 #define EUSCI_B_CTLW0_TR_OFS ( 4) /*!< UCTR Bit Offset */ 3758 #define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /*!< Transmitter/receiver */ 3759 /* EUSCI_B_CTLW0[TXACK] Bits */ 3760 #define EUSCI_B_CTLW0_TXACK_OFS ( 5) /*!< UCTXACK Bit Offset */ 3761 #define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /*!< Transmit ACK condition in slave mode */ 3762 /* EUSCI_B_CTLW0[SSEL] Bits */ 3763 #define EUSCI_B_CTLW0_SSEL_OFS ( 6) /*!< UCSSEL Bit Offset */ 3764 #define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /*!< UCSSEL Bit Mask */ 3765 #define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /*!< SSEL Bit 0 */ 3766 #define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /*!< SSEL Bit 1 */ 3767 #define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /*!< UCLKI */ 3768 #define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /*!< ACLK */ 3769 #define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /*!< SMCLK */ 3770 #define EUSCI_B_CTLW0_UCSSEL_3 ((uint16_t)0x00C0) /*!< SMCLK */ 3771 #define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /*!< UCLKI */ 3772 #define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /*!< ACLK */ 3773 #define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /*!< SMCLK */ 3774 /* EUSCI_B_CTLW0[SYNC] Bits */ 3775 #define EUSCI_B_CTLW0_SYNC_OFS ( 8) /*!< UCSYNC Bit Offset */ 3776 #define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /*!< Synchronous mode enable */ 3777 /* EUSCI_B_CTLW0[MODE] Bits */ 3778 #define EUSCI_B_CTLW0_MODE_OFS ( 9) /*!< UCMODE Bit Offset */ 3779 #define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /*!< UCMODE Bit Mask */ 3780 #define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /*!< MODE Bit 0 */ 3781 #define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /*!< MODE Bit 1 */ 3782 #define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /*!< 3-pin SPI */ 3783 #define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /*!< 4-pin SPI (master or slave enabled if STE = 1) */ 3784 #define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /*!< 4-pin SPI (master or slave enabled if STE = 0) */ 3785 #define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /*!< I2C mode */ 3786 /* EUSCI_B_CTLW0[MST] Bits */ 3787 #define EUSCI_B_CTLW0_MST_OFS (11) /*!< UCMST Bit Offset */ 3788 #define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /*!< Master mode select */ 3789 /* EUSCI_B_CTLW0[MM] Bits */ 3790 #define EUSCI_B_CTLW0_MM_OFS (13) /*!< UCMM Bit Offset */ 3791 #define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /*!< Multi-master environment select */ 3792 /* EUSCI_B_CTLW0[SLA10] Bits */ 3793 #define EUSCI_B_CTLW0_SLA10_OFS (14) /*!< UCSLA10 Bit Offset */ 3794 #define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /*!< Slave addressing mode select */ 3795 /* EUSCI_B_CTLW0[A10] Bits */ 3796 #define EUSCI_B_CTLW0_A10_OFS (15) /*!< UCA10 Bit Offset */ 3797 #define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /*!< Own addressing mode select */ 3798 /* EUSCI_B_CTLW0[STEM] Bits */ 3799 #define EUSCI_B_CTLW0_STEM_OFS ( 1) /*!< UCSTEM Bit Offset */ 3800 #define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /*!< STE mode select in master mode. */ 3801 /* EUSCI_B_CTLW0[SEVENBIT] Bits */ 3802 #define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /*!< UC7BIT Bit Offset */ 3803 #define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /*!< Character length */ 3804 /* EUSCI_B_CTLW0[MSB] Bits */ 3805 #define EUSCI_B_CTLW0_MSB_OFS (13) /*!< UCMSB Bit Offset */ 3806 #define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /*!< MSB first select */ 3807 /* EUSCI_B_CTLW0[CKPL] Bits */ 3808 #define EUSCI_B_CTLW0_CKPL_OFS (14) /*!< UCCKPL Bit Offset */ 3809 #define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /*!< Clock polarity select */ 3810 /* EUSCI_B_CTLW0[CKPH] Bits */ 3811 #define EUSCI_B_CTLW0_CKPH_OFS (15) /*!< UCCKPH Bit Offset */ 3812 #define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /*!< Clock phase select */ 3813 /* EUSCI_B_CTLW1[GLIT] Bits */ 3814 #define EUSCI_B_CTLW1_GLIT_OFS ( 0) /*!< UCGLIT Bit Offset */ 3815 #define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /*!< UCGLIT Bit Mask */ 3816 #define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /*!< GLIT Bit 0 */ 3817 #define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /*!< GLIT Bit 1 */ 3818 #define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /*!< 50 ns */ 3819 #define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /*!< 25 ns */ 3820 #define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /*!< 12.5 ns */ 3821 #define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /*!< 6.25 ns */ 3822 /* EUSCI_B_CTLW1[ASTP] Bits */ 3823 #define EUSCI_B_CTLW1_ASTP_OFS ( 2) /*!< UCASTP Bit Offset */ 3824 #define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /*!< UCASTP Bit Mask */ 3825 #define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /*!< ASTP Bit 0 */ 3826 #define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /*!< ASTP Bit 1 */ 3827 #define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /*!< No automatic STOP generation. The STOP condition is generated after the user */ 3828 /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */ 3829 #define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /*!< UCBCNTIFG is set with the byte counter reaches the threshold defined in */ 3830 /* UCBxTBCNT */ 3831 #define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /*!< A STOP condition is generated automatically after the byte counter value */ 3832 /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */ 3833 /* threshold */ 3834 /* EUSCI_B_CTLW1[SWACK] Bits */ 3835 #define EUSCI_B_CTLW1_SWACK_OFS ( 4) /*!< UCSWACK Bit Offset */ 3836 #define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /*!< SW or HW ACK control */ 3837 /* EUSCI_B_CTLW1[STPNACK] Bits */ 3838 #define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /*!< UCSTPNACK Bit Offset */ 3839 #define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /*!< ACK all master bytes */ 3840 /* EUSCI_B_CTLW1[CLTO] Bits */ 3841 #define EUSCI_B_CTLW1_CLTO_OFS ( 6) /*!< UCCLTO Bit Offset */ 3842 #define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /*!< UCCLTO Bit Mask */ 3843 #define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /*!< CLTO Bit 0 */ 3844 #define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /*!< CLTO Bit 1 */ 3845 #define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /*!< Disable clock low timeout counter */ 3846 #define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /*!< 135 000 SYSCLK cycles (approximately 28 ms) */ 3847 #define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /*!< 150 000 SYSCLK cycles (approximately 31 ms) */ 3848 #define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /*!< 165 000 SYSCLK cycles (approximately 34 ms) */ 3849 /* EUSCI_B_CTLW1[ETXINT] Bits */ 3850 #define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /*!< UCETXINT Bit Offset */ 3851 #define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /*!< Early UCTXIFG0 */ 3852 /* EUSCI_B_STATW[BBUSY] Bits */ 3853 #define EUSCI_B_STATW_BBUSY_OFS ( 4) /*!< UCBBUSY Bit Offset */ 3854 #define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /*!< Bus busy */ 3855 /* EUSCI_B_STATW[GC] Bits */ 3856 #define EUSCI_B_STATW_GC_OFS ( 5) /*!< UCGC Bit Offset */ 3857 #define EUSCI_B_STATW_GC ((uint16_t)0x0020) /*!< General call address received */ 3858 /* EUSCI_B_STATW[SCLLOW] Bits */ 3859 #define EUSCI_B_STATW_SCLLOW_OFS ( 6) /*!< UCSCLLOW Bit Offset */ 3860 #define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /*!< SCL low */ 3861 /* EUSCI_B_STATW[BCNT] Bits */ 3862 #define EUSCI_B_STATW_BCNT_OFS ( 8) /*!< UCBCNT Bit Offset */ 3863 #define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /*!< UCBCNT Bit Mask */ 3864 /* EUSCI_B_STATW[SPI_BUSY] Bits */ 3865 #define EUSCI_B_STATW_SPI_BUSY_OFS ( 0) /*!< UCBUSY Bit Offset */ 3866 #define EUSCI_B_STATW_SPI_BUSY ((uint16_t)0x0001) /*!< eUSCI_B busy */ 3867 /* EUSCI_B_STATW[OE] Bits */ 3868 #define EUSCI_B_STATW_OE_OFS ( 5) /*!< UCOE Bit Offset */ 3869 #define EUSCI_B_STATW_OE ((uint16_t)0x0020) /*!< Overrun error flag */ 3870 /* EUSCI_B_STATW[FE] Bits */ 3871 #define EUSCI_B_STATW_FE_OFS ( 6) /*!< UCFE Bit Offset */ 3872 #define EUSCI_B_STATW_FE ((uint16_t)0x0040) /*!< Framing error flag */ 3873 /* EUSCI_B_STATW[LISTEN] Bits */ 3874 #define EUSCI_B_STATW_LISTEN_OFS ( 7) /*!< UCLISTEN Bit Offset */ 3875 #define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /*!< Listen enable */ 3876 /* EUSCI_B_TBCNT[TBCNT] Bits */ 3877 #define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /*!< UCTBCNT Bit Offset */ 3878 #define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /*!< UCTBCNT Bit Mask */ 3879 /* EUSCI_B_RXBUF[RXBUF] Bits */ 3880 #define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /*!< UCRXBUF Bit Offset */ 3881 #define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /*!< UCRXBUF Bit Mask */ 3882 /* EUSCI_B_TXBUF[TXBUF] Bits */ 3883 #define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /*!< UCTXBUF Bit Offset */ 3884 #define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /*!< UCTXBUF Bit Mask */ 3885 /* EUSCI_B_I2COA0[I2COA0] Bits */ 3886 #define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /*!< I2COA0 Bit Offset */ 3887 #define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /*!< I2COA0 Bit Mask */ 3888 /* EUSCI_B_I2COA0[OAEN] Bits */ 3889 #define EUSCI_B_I2COA0_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3890 #define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3891 /* EUSCI_B_I2COA0[GCEN] Bits */ 3892 #define EUSCI_B_I2COA0_GCEN_OFS (15) /*!< UCGCEN Bit Offset */ 3893 #define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /*!< General call response enable */ 3894 /* EUSCI_B_I2COA1[I2COA1] Bits */ 3895 #define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /*!< I2COA1 Bit Offset */ 3896 #define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /*!< I2COA1 Bit Mask */ 3897 /* EUSCI_B_I2COA1[OAEN] Bits */ 3898 #define EUSCI_B_I2COA1_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3899 #define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3900 /* EUSCI_B_I2COA2[I2COA2] Bits */ 3901 #define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /*!< I2COA2 Bit Offset */ 3902 #define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /*!< I2COA2 Bit Mask */ 3903 /* EUSCI_B_I2COA2[OAEN] Bits */ 3904 #define EUSCI_B_I2COA2_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3905 #define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3906 /* EUSCI_B_I2COA3[I2COA3] Bits */ 3907 #define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /*!< I2COA3 Bit Offset */ 3908 #define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /*!< I2COA3 Bit Mask */ 3909 /* EUSCI_B_I2COA3[OAEN] Bits */ 3910 #define EUSCI_B_I2COA3_OAEN_OFS (10) /*!< UCOAEN Bit Offset */ 3911 #define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /*!< Own Address enable register */ 3912 /* EUSCI_B_ADDRX[ADDRX] Bits */ 3913 #define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /*!< ADDRX Bit Offset */ 3914 #define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /*!< ADDRX Bit Mask */ 3915 #define EUSCI_B_ADDRX_ADDRX0 ((uint16_t)0x0001) /*!< ADDRX Bit 0 */ 3916 #define EUSCI_B_ADDRX_ADDRX1 ((uint16_t)0x0002) /*!< ADDRX Bit 1 */ 3917 #define EUSCI_B_ADDRX_ADDRX2 ((uint16_t)0x0004) /*!< ADDRX Bit 2 */ 3918 #define EUSCI_B_ADDRX_ADDRX3 ((uint16_t)0x0008) /*!< ADDRX Bit 3 */ 3919 #define EUSCI_B_ADDRX_ADDRX4 ((uint16_t)0x0010) /*!< ADDRX Bit 4 */ 3920 #define EUSCI_B_ADDRX_ADDRX5 ((uint16_t)0x0020) /*!< ADDRX Bit 5 */ 3921 #define EUSCI_B_ADDRX_ADDRX6 ((uint16_t)0x0040) /*!< ADDRX Bit 6 */ 3922 #define EUSCI_B_ADDRX_ADDRX7 ((uint16_t)0x0080) /*!< ADDRX Bit 7 */ 3923 #define EUSCI_B_ADDRX_ADDRX8 ((uint16_t)0x0100) /*!< ADDRX Bit 8 */ 3924 #define EUSCI_B_ADDRX_ADDRX9 ((uint16_t)0x0200) /*!< ADDRX Bit 9 */ 3925 /* EUSCI_B_ADDMASK[ADDMASK] Bits */ 3926 #define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /*!< ADDMASK Bit Offset */ 3927 #define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /*!< ADDMASK Bit Mask */ 3928 /* EUSCI_B_I2CSA[I2CSA] Bits */ 3929 #define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /*!< I2CSA Bit Offset */ 3930 #define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /*!< I2CSA Bit Mask */ 3931 /* EUSCI_B_IE[RXIE0] Bits */ 3932 #define EUSCI_B_IE_RXIE0_OFS ( 0) /*!< UCRXIE0 Bit Offset */ 3933 #define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /*!< Receive interrupt enable 0 */ 3934 /* EUSCI_B_IE[TXIE0] Bits */ 3935 #define EUSCI_B_IE_TXIE0_OFS ( 1) /*!< UCTXIE0 Bit Offset */ 3936 #define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /*!< Transmit interrupt enable 0 */ 3937 /* EUSCI_B_IE[STTIE] Bits */ 3938 #define EUSCI_B_IE_STTIE_OFS ( 2) /*!< UCSTTIE Bit Offset */ 3939 #define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /*!< START condition interrupt enable */ 3940 /* EUSCI_B_IE[STPIE] Bits */ 3941 #define EUSCI_B_IE_STPIE_OFS ( 3) /*!< UCSTPIE Bit Offset */ 3942 #define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /*!< STOP condition interrupt enable */ 3943 /* EUSCI_B_IE[ALIE] Bits */ 3944 #define EUSCI_B_IE_ALIE_OFS ( 4) /*!< UCALIE Bit Offset */ 3945 #define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /*!< Arbitration lost interrupt enable */ 3946 /* EUSCI_B_IE[NACKIE] Bits */ 3947 #define EUSCI_B_IE_NACKIE_OFS ( 5) /*!< UCNACKIE Bit Offset */ 3948 #define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /*!< Not-acknowledge interrupt enable */ 3949 /* EUSCI_B_IE[BCNTIE] Bits */ 3950 #define EUSCI_B_IE_BCNTIE_OFS ( 6) /*!< UCBCNTIE Bit Offset */ 3951 #define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /*!< Byte counter interrupt enable */ 3952 /* EUSCI_B_IE[CLTOIE] Bits */ 3953 #define EUSCI_B_IE_CLTOIE_OFS ( 7) /*!< UCCLTOIE Bit Offset */ 3954 #define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /*!< Clock low timeout interrupt enable */ 3955 /* EUSCI_B_IE[RXIE1] Bits */ 3956 #define EUSCI_B_IE_RXIE1_OFS ( 8) /*!< UCRXIE1 Bit Offset */ 3957 #define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /*!< Receive interrupt enable 1 */ 3958 /* EUSCI_B_IE[TXIE1] Bits */ 3959 #define EUSCI_B_IE_TXIE1_OFS ( 9) /*!< UCTXIE1 Bit Offset */ 3960 #define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /*!< Transmit interrupt enable 1 */ 3961 /* EUSCI_B_IE[RXIE2] Bits */ 3962 #define EUSCI_B_IE_RXIE2_OFS (10) /*!< UCRXIE2 Bit Offset */ 3963 #define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /*!< Receive interrupt enable 2 */ 3964 /* EUSCI_B_IE[TXIE2] Bits */ 3965 #define EUSCI_B_IE_TXIE2_OFS (11) /*!< UCTXIE2 Bit Offset */ 3966 #define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /*!< Transmit interrupt enable 2 */ 3967 /* EUSCI_B_IE[RXIE3] Bits */ 3968 #define EUSCI_B_IE_RXIE3_OFS (12) /*!< UCRXIE3 Bit Offset */ 3969 #define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /*!< Receive interrupt enable 3 */ 3970 /* EUSCI_B_IE[TXIE3] Bits */ 3971 #define EUSCI_B_IE_TXIE3_OFS (13) /*!< UCTXIE3 Bit Offset */ 3972 #define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /*!< Transmit interrupt enable 3 */ 3973 /* EUSCI_B_IE[BIT9IE] Bits */ 3974 #define EUSCI_B_IE_BIT9IE_OFS (14) /*!< UCBIT9IE Bit Offset */ 3975 #define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /*!< Bit position 9 interrupt enable */ 3976 /* EUSCI_B_IE[RXIE] Bits */ 3977 #define EUSCI_B_IE_RXIE_OFS ( 0) /*!< UCRXIE Bit Offset */ 3978 #define EUSCI_B_IE_RXIE ((uint16_t)0x0001) /*!< Receive interrupt enable */ 3979 /* EUSCI_B_IE[TXIE] Bits */ 3980 #define EUSCI_B_IE_TXIE_OFS ( 1) /*!< UCTXIE Bit Offset */ 3981 #define EUSCI_B_IE_TXIE ((uint16_t)0x0002) /*!< Transmit interrupt enable */ 3982 /* EUSCI_B_IFG[RXIFG0] Bits */ 3983 #define EUSCI_B_IFG_RXIFG0_OFS ( 0) /*!< UCRXIFG0 Bit Offset */ 3984 #define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /*!< eUSCI_B receive interrupt flag 0 */ 3985 /* EUSCI_B_IFG[TXIFG0] Bits */ 3986 #define EUSCI_B_IFG_TXIFG0_OFS ( 1) /*!< UCTXIFG0 Bit Offset */ 3987 #define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /*!< eUSCI_B transmit interrupt flag 0 */ 3988 /* EUSCI_B_IFG[STTIFG] Bits */ 3989 #define EUSCI_B_IFG_STTIFG_OFS ( 2) /*!< UCSTTIFG Bit Offset */ 3990 #define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /*!< START condition interrupt flag */ 3991 /* EUSCI_B_IFG[STPIFG] Bits */ 3992 #define EUSCI_B_IFG_STPIFG_OFS ( 3) /*!< UCSTPIFG Bit Offset */ 3993 #define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /*!< STOP condition interrupt flag */ 3994 /* EUSCI_B_IFG[ALIFG] Bits */ 3995 #define EUSCI_B_IFG_ALIFG_OFS ( 4) /*!< UCALIFG Bit Offset */ 3996 #define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /*!< Arbitration lost interrupt flag */ 3997 /* EUSCI_B_IFG[NACKIFG] Bits */ 3998 #define EUSCI_B_IFG_NACKIFG_OFS ( 5) /*!< UCNACKIFG Bit Offset */ 3999 #define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /*!< Not-acknowledge received interrupt flag */ 4000 /* EUSCI_B_IFG[BCNTIFG] Bits */ 4001 #define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /*!< UCBCNTIFG Bit Offset */ 4002 #define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /*!< Byte counter interrupt flag */ 4003 /* EUSCI_B_IFG[CLTOIFG] Bits */ 4004 #define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /*!< UCCLTOIFG Bit Offset */ 4005 #define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /*!< Clock low timeout interrupt flag */ 4006 /* EUSCI_B_IFG[RXIFG1] Bits */ 4007 #define EUSCI_B_IFG_RXIFG1_OFS ( 8) /*!< UCRXIFG1 Bit Offset */ 4008 #define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /*!< eUSCI_B receive interrupt flag 1 */ 4009 /* EUSCI_B_IFG[TXIFG1] Bits */ 4010 #define EUSCI_B_IFG_TXIFG1_OFS ( 9) /*!< UCTXIFG1 Bit Offset */ 4011 #define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /*!< eUSCI_B transmit interrupt flag 1 */ 4012 /* EUSCI_B_IFG[RXIFG2] Bits */ 4013 #define EUSCI_B_IFG_RXIFG2_OFS (10) /*!< UCRXIFG2 Bit Offset */ 4014 #define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /*!< eUSCI_B receive interrupt flag 2 */ 4015 /* EUSCI_B_IFG[TXIFG2] Bits */ 4016 #define EUSCI_B_IFG_TXIFG2_OFS (11) /*!< UCTXIFG2 Bit Offset */ 4017 #define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /*!< eUSCI_B transmit interrupt flag 2 */ 4018 /* EUSCI_B_IFG[RXIFG3] Bits */ 4019 #define EUSCI_B_IFG_RXIFG3_OFS (12) /*!< UCRXIFG3 Bit Offset */ 4020 #define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /*!< eUSCI_B receive interrupt flag 3 */ 4021 /* EUSCI_B_IFG[TXIFG3] Bits */ 4022 #define EUSCI_B_IFG_TXIFG3_OFS (13) /*!< UCTXIFG3 Bit Offset */ 4023 #define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /*!< eUSCI_B transmit interrupt flag 3 */ 4024 /* EUSCI_B_IFG[BIT9IFG] Bits */ 4025 #define EUSCI_B_IFG_BIT9IFG_OFS (14) /*!< UCBIT9IFG Bit Offset */ 4026 #define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /*!< Bit position 9 interrupt flag */ 4027 /* EUSCI_B_IFG[RXIFG] Bits */ 4028 #define EUSCI_B_IFG_RXIFG_OFS ( 0) /*!< UCRXIFG Bit Offset */ 4029 #define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /*!< Receive interrupt flag */ 4030 /* EUSCI_B_IFG[TXIFG] Bits */ 4031 #define EUSCI_B_IFG_TXIFG_OFS ( 1) /*!< UCTXIFG Bit Offset */ 4032 #define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /*!< Transmit interrupt flag */ 4033 /* legacy definitions for backward compatibility to version 2100 */ 4034 #define EUSCI_B__RXIE_OFS EUSCI_B_IE_RXIE_OFS /*!< UCRXIE Bit Offset */ 4035 #define EUSCI_B__RXIE EUSCI_B_IE_RXIE /*!< Receive interrupt enable */ 4036 #define EUSCI_B__TXIE_OFS EUSCI_B_IE_TXIE_OFS /*!< UCTXIE Bit Offset */ 4037 #define EUSCI_B__TXIE EUSCI_B_IE_TXIE /*!< Transmit interrupt enable */ 4038 4039 4040 /****************************************************************************** 4041 * FLCTL Bits 4042 ******************************************************************************/ 4043 /* FLCTL_POWER_STAT[PSTAT] Bits */ 4044 #define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /*!< PSTAT Bit Offset */ 4045 #define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /*!< PSTAT Bit Mask */ 4046 #define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /*!< PSTAT Bit 0 */ 4047 #define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /*!< PSTAT Bit 1 */ 4048 #define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /*!< PSTAT Bit 2 */ 4049 #define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /*!< Flash IP in power-down mode */ 4050 #define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /*!< Flash IP Vdd domain power-up in progress */ 4051 #define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /*!< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */ 4052 #define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /*!< Flash IP SAFE_LV check in progress */ 4053 #define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /*!< Flash IP Active */ 4054 #define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /*!< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */ 4055 #define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /*!< Flash IP in Standby mode */ 4056 #define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /*!< Flash IP in Current mirror boost state */ 4057 /* FLCTL_POWER_STAT[LDOSTAT] Bits */ 4058 #define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /*!< LDOSTAT Bit Offset */ 4059 #define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /*!< PSS FLDO GOOD status */ 4060 /* FLCTL_POWER_STAT[VREFSTAT] Bits */ 4061 #define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /*!< VREFSTAT Bit Offset */ 4062 #define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /*!< PSS VREF stable status */ 4063 /* FLCTL_POWER_STAT[IREFSTAT] Bits */ 4064 #define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /*!< IREFSTAT Bit Offset */ 4065 #define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /*!< PSS IREF stable status */ 4066 /* FLCTL_POWER_STAT[TRIMSTAT] Bits */ 4067 #define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /*!< TRIMSTAT Bit Offset */ 4068 #define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /*!< PSS trim done status */ 4069 /* FLCTL_POWER_STAT[RD_2T] Bits */ 4070 #define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /*!< RD_2T Bit Offset */ 4071 #define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /*!< Indicates if Flash is being accessed in 2T mode */ 4072 /* FLCTL_BANK0_RDCTL[RD_MODE] Bits */ 4073 #define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ 4074 #define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ 4075 #define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ 4076 #define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ 4077 #define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ 4078 #define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ 4079 #define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4080 #define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ 4081 #define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ 4082 #define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ 4083 #define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ 4084 #define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ 4085 #define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ 4086 #define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ 4087 /* FLCTL_BANK0_RDCTL[BUFI] Bits */ 4088 #define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ 4089 #define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ 4090 /* FLCTL_BANK0_RDCTL[BUFD] Bits */ 4091 #define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ 4092 #define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ 4093 /* FLCTL_BANK0_RDCTL[WAIT] Bits */ 4094 #define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ 4095 #define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ 4096 #define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ 4097 #define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ 4098 #define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ 4099 #define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ 4100 #define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ 4101 #define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ 4102 #define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ 4103 #define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ 4104 #define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ 4105 #define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ 4106 #define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ 4107 #define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ 4108 #define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ 4109 #define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ 4110 #define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ 4111 #define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ 4112 #define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ 4113 #define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ 4114 #define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ 4115 #define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ 4116 /* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */ 4117 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ 4118 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ 4119 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ 4120 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ 4121 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ 4122 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ 4123 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4124 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ 4125 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ 4126 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ 4127 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ 4128 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ 4129 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ 4130 #define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ 4131 /* FLCTL_BANK1_RDCTL[RD_MODE] Bits */ 4132 #define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /*!< RD_MODE Bit Offset */ 4133 #define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /*!< RD_MODE Bit Mask */ 4134 #define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /*!< RD_MODE Bit 0 */ 4135 #define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /*!< RD_MODE Bit 1 */ 4136 #define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /*!< RD_MODE Bit 2 */ 4137 #define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /*!< RD_MODE Bit 3 */ 4138 #define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4139 #define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /*!< Read Margin 0 */ 4140 #define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /*!< Read Margin 1 */ 4141 #define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /*!< Program Verify */ 4142 #define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /*!< Erase Verify */ 4143 #define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /*!< Leakage Verify */ 4144 #define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /*!< Read Margin 0B */ 4145 #define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /*!< Read Margin 1B */ 4146 /* FLCTL_BANK1_RDCTL[BUFI] Bits */ 4147 #define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /*!< BUFI Bit Offset */ 4148 #define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /*!< Enables read buffering feature for instruction fetches to this Bank */ 4149 /* FLCTL_BANK1_RDCTL[BUFD] Bits */ 4150 #define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /*!< BUFD Bit Offset */ 4151 #define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /*!< Enables read buffering feature for data reads to this Bank */ 4152 /* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */ 4153 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /*!< RD_MODE_STATUS Bit Offset */ 4154 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /*!< RD_MODE_STATUS Bit Mask */ 4155 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /*!< RD_MODE_STATUS Bit 0 */ 4156 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /*!< RD_MODE_STATUS Bit 1 */ 4157 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /*!< RD_MODE_STATUS Bit 2 */ 4158 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /*!< RD_MODE_STATUS Bit 3 */ 4159 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /*!< Normal read mode */ 4160 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /*!< Read Margin 0 */ 4161 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /*!< Read Margin 1 */ 4162 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /*!< Program Verify */ 4163 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /*!< Erase Verify */ 4164 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /*!< Leakage Verify */ 4165 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /*!< Read Margin 0B */ 4166 #define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /*!< Read Margin 1B */ 4167 /* FLCTL_BANK1_RDCTL[WAIT] Bits */ 4168 #define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /*!< WAIT Bit Offset */ 4169 #define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /*!< WAIT Bit Mask */ 4170 #define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /*!< WAIT Bit 0 */ 4171 #define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /*!< WAIT Bit 1 */ 4172 #define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /*!< WAIT Bit 2 */ 4173 #define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /*!< WAIT Bit 3 */ 4174 #define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /*!< 0 wait states */ 4175 #define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /*!< 1 wait states */ 4176 #define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /*!< 2 wait states */ 4177 #define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /*!< 3 wait states */ 4178 #define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /*!< 4 wait states */ 4179 #define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /*!< 5 wait states */ 4180 #define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /*!< 6 wait states */ 4181 #define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /*!< 7 wait states */ 4182 #define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /*!< 8 wait states */ 4183 #define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /*!< 9 wait states */ 4184 #define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /*!< 10 wait states */ 4185 #define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /*!< 11 wait states */ 4186 #define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /*!< 12 wait states */ 4187 #define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /*!< 13 wait states */ 4188 #define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /*!< 14 wait states */ 4189 #define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /*!< 15 wait states */ 4190 /* FLCTL_RDBRST_CTLSTAT[START] Bits */ 4191 #define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ 4192 #define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of burst/compare operation */ 4193 /* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */ 4194 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /*!< MEM_TYPE Bit Offset */ 4195 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /*!< MEM_TYPE Bit Mask */ 4196 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /*!< MEM_TYPE Bit 0 */ 4197 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /*!< MEM_TYPE Bit 1 */ 4198 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ 4199 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ 4200 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ 4201 #define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ 4202 /* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */ 4203 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /*!< STOP_FAIL Bit Offset */ 4204 #define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /*!< Terminate burst/compare operation */ 4205 /* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */ 4206 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /*!< DATA_CMP Bit Offset */ 4207 #define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /*!< Data pattern used for comparison against memory read data */ 4208 /* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */ 4209 #define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /*!< TEST_EN Bit Offset */ 4210 #define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /*!< Enable comparison against test data compare registers */ 4211 /* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */ 4212 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /*!< BRST_STAT Bit Offset */ 4213 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /*!< BRST_STAT Bit Mask */ 4214 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /*!< BRST_STAT Bit 0 */ 4215 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /*!< BRST_STAT Bit 1 */ 4216 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /*!< Idle */ 4217 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /*!< Burst/Compare START bit written, but operation pending */ 4218 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /*!< Burst/Compare in progress */ 4219 #define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /*!< Burst complete (status of completed burst remains in this state unless */ 4220 /* explicitly cleared by SW) */ 4221 /* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */ 4222 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /*!< CMP_ERR Bit Offset */ 4223 #define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /*!< Burst/Compare Operation encountered atleast one data */ 4224 /* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */ 4225 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /*!< ADDR_ERR Bit Offset */ 4226 #define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /*!< Burst/Compare Operation was terminated due to access to */ 4227 /* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */ 4228 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ 4229 #define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 19-16 of this register */ 4230 /* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */ 4231 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ 4232 #define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< START_ADDRESS Bit Mask */ 4233 /* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */ 4234 #define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /*!< BURST_LENGTH Bit Offset */ 4235 #define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /*!< BURST_LENGTH Bit Mask */ 4236 /* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */ 4237 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /*!< FAIL_ADDRESS Bit Offset */ 4238 #define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /*!< FAIL_ADDRESS Bit Mask */ 4239 /* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */ 4240 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /*!< FAIL_COUNT Bit Offset */ 4241 #define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /*!< FAIL_COUNT Bit Mask */ 4242 /* FLCTL_PRG_CTLSTAT[ENABLE] Bits */ 4243 #define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /*!< ENABLE Bit Offset */ 4244 #define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /*!< Master control for all word program operations */ 4245 /* FLCTL_PRG_CTLSTAT[MODE] Bits */ 4246 #define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ 4247 #define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Write mode */ 4248 /* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */ 4249 #define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /*!< VER_PRE Bit Offset */ 4250 #define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /*!< Controls automatic pre program verify operations */ 4251 /* FLCTL_PRG_CTLSTAT[VER_PST] Bits */ 4252 #define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /*!< VER_PST Bit Offset */ 4253 #define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /*!< Controls automatic post program verify operations */ 4254 /* FLCTL_PRG_CTLSTAT[STATUS] Bits */ 4255 #define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ 4256 #define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ 4257 #define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ 4258 #define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ 4259 #define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ 4260 #define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Single word program operation triggered, but pending */ 4261 #define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Single word program in progress */ 4262 #define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Reserved (Idle) */ 4263 /* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */ 4264 #define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /*!< BNK_ACT Bit Offset */ 4265 #define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /*!< Bank active */ 4266 /* FLCTL_PRGBRST_CTLSTAT[START] Bits */ 4267 #define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ 4268 #define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /*!< Trigger start of burst program operation */ 4269 /* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */ 4270 #define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /*!< TYPE Bit Offset */ 4271 #define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /*!< TYPE Bit Mask */ 4272 #define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /*!< TYPE Bit 0 */ 4273 #define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /*!< TYPE Bit 1 */ 4274 #define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ 4275 #define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /*!< Information Memory */ 4276 #define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /*!< Reserved */ 4277 #define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /*!< Engineering Memory */ 4278 /* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */ 4279 #define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /*!< LEN Bit Offset */ 4280 #define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /*!< LEN Bit Mask */ 4281 #define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /*!< LEN Bit 0 */ 4282 #define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /*!< LEN Bit 1 */ 4283 #define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /*!< LEN Bit 2 */ 4284 #define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /*!< No burst operation */ 4285 #define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /*!< 1 word burst of 128 bits, starting with address in the */ 4286 /* FLCTL_PRGBRST_STARTADDR Register */ 4287 #define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /*!< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ 4288 /* Register */ 4289 #define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /*!< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ 4290 /* Register */ 4291 #define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /*!< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */ 4292 /* Register */ 4293 /* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */ 4294 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /*!< AUTO_PRE Bit Offset */ 4295 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /*!< Auto-Verify operation before the Burst Program */ 4296 /* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */ 4297 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /*!< AUTO_PST Bit Offset */ 4298 #define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /*!< Auto-Verify operation after the Burst Program */ 4299 /* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */ 4300 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /*!< BURST_STATUS Bit Offset */ 4301 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /*!< BURST_STATUS Bit Mask */ 4302 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /*!< BURST_STATUS Bit 0 */ 4303 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /*!< BURST_STATUS Bit 1 */ 4304 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /*!< BURST_STATUS Bit 2 */ 4305 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (Burst not active) */ 4306 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /*!< Burst program started but pending */ 4307 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /*!< Burst active, with 1st 128 bit word being written into Flash */ 4308 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /*!< Burst active, with 2nd 128 bit word being written into Flash */ 4309 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /*!< Burst active, with 3rd 128 bit word being written into Flash */ 4310 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /*!< Burst active, with 4th 128 bit word being written into Flash */ 4311 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /*!< Reserved (Idle) */ 4312 #define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /*!< Burst Complete (status of completed burst remains in this state unless */ 4313 /* explicitly cleared by SW) */ 4314 /* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */ 4315 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /*!< PRE_ERR Bit Offset */ 4316 #define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /*!< Burst Operation encountered preprogram auto-verify errors */ 4317 /* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */ 4318 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /*!< PST_ERR Bit Offset */ 4319 #define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /*!< Burst Operation encountered postprogram auto-verify errors */ 4320 /* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */ 4321 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /*!< ADDR_ERR Bit Offset */ 4322 #define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /*!< Burst Operation was terminated due to attempted program of reserved memory */ 4323 /* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */ 4324 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /*!< CLR_STAT Bit Offset */ 4325 #define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /*!< Clear status bits 21-16 of this register */ 4326 /* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */ 4327 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /*!< START_ADDRESS Bit Offset */ 4328 #define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< START_ADDRESS Bit Mask */ 4329 /* FLCTL_ERASE_CTLSTAT[START] Bits */ 4330 #define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /*!< START Bit Offset */ 4331 #define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /*!< Start of Erase operation */ 4332 /* FLCTL_ERASE_CTLSTAT[MODE] Bits */ 4333 #define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /*!< MODE Bit Offset */ 4334 #define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /*!< Erase mode selected by application */ 4335 /* FLCTL_ERASE_CTLSTAT[TYPE] Bits */ 4336 #define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /*!< TYPE Bit Offset */ 4337 #define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /*!< TYPE Bit Mask */ 4338 #define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /*!< TYPE Bit 0 */ 4339 #define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /*!< TYPE Bit 1 */ 4340 #define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /*!< Main Memory */ 4341 #define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /*!< Information Memory */ 4342 #define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /*!< Reserved */ 4343 #define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /*!< Engineering Memory */ 4344 /* FLCTL_ERASE_CTLSTAT[STATUS] Bits */ 4345 #define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /*!< STATUS Bit Offset */ 4346 #define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /*!< STATUS Bit Mask */ 4347 #define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /*!< STATUS Bit 0 */ 4348 #define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /*!< STATUS Bit 1 */ 4349 #define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /*!< Idle (no program operation currently active) */ 4350 #define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /*!< Erase operation triggered to START but pending */ 4351 #define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /*!< Erase operation in progress */ 4352 #define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /*!< Erase operation completed (status of completed erase remains in this state */ 4353 /* unless explicitly cleared by SW) */ 4354 /* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */ 4355 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /*!< ADDR_ERR Bit Offset */ 4356 #define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /*!< Erase Operation was terminated due to attempted erase of reserved memory */ 4357 /* address */ 4358 /* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */ 4359 #define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /*!< CLR_STAT Bit Offset */ 4360 #define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /*!< Clear status bits 18-16 of this register */ 4361 /* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */ 4362 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /*!< SECT_ADDRESS Bit Offset */ 4363 #define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /*!< SECT_ADDRESS Bit Mask */ 4364 /* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */ 4365 #define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4366 #define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ 4367 /* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */ 4368 #define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4369 #define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ 4370 /* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */ 4371 #define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4372 #define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase */ 4373 /* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */ 4374 #define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4375 #define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase */ 4376 /* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */ 4377 #define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 4378 #define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase */ 4379 /* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */ 4380 #define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 4381 #define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase */ 4382 /* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */ 4383 #define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ 4384 #define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase */ 4385 /* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */ 4386 #define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ 4387 #define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase */ 4388 /* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */ 4389 #define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ 4390 #define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase */ 4391 /* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */ 4392 #define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ 4393 #define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase */ 4394 /* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */ 4395 #define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ 4396 #define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase */ 4397 /* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */ 4398 #define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ 4399 #define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase */ 4400 /* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */ 4401 #define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ 4402 #define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase */ 4403 /* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */ 4404 #define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ 4405 #define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase */ 4406 /* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */ 4407 #define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ 4408 #define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase */ 4409 /* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */ 4410 #define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ 4411 #define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase */ 4412 /* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */ 4413 #define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ 4414 #define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase */ 4415 /* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */ 4416 #define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ 4417 #define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase */ 4418 /* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */ 4419 #define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ 4420 #define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase */ 4421 /* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */ 4422 #define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ 4423 #define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase */ 4424 /* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */ 4425 #define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ 4426 #define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase */ 4427 /* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */ 4428 #define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ 4429 #define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase */ 4430 /* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */ 4431 #define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ 4432 #define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase */ 4433 /* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */ 4434 #define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ 4435 #define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase */ 4436 /* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */ 4437 #define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ 4438 #define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase */ 4439 /* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */ 4440 #define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ 4441 #define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase */ 4442 /* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */ 4443 #define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ 4444 #define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase */ 4445 /* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */ 4446 #define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ 4447 #define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase */ 4448 /* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */ 4449 #define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ 4450 #define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase */ 4451 /* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */ 4452 #define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ 4453 #define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase */ 4454 /* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */ 4455 #define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ 4456 #define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase */ 4457 /* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */ 4458 #define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ 4459 #define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase */ 4460 /* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */ 4461 #define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ 4462 #define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase */ 4463 /* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */ 4464 #define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ 4465 #define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase */ 4466 /* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */ 4467 #define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4468 #define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ 4469 /* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */ 4470 #define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4471 #define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ 4472 /* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */ 4473 #define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /*!< PROT0 Bit Offset */ 4474 #define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /*!< Protects Sector 0 from program or erase operations */ 4475 /* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */ 4476 #define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /*!< PROT1 Bit Offset */ 4477 #define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /*!< Protects Sector 1 from program or erase operations */ 4478 /* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */ 4479 #define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /*!< PROT2 Bit Offset */ 4480 #define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /*!< Protects Sector 2 from program or erase operations */ 4481 /* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */ 4482 #define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /*!< PROT3 Bit Offset */ 4483 #define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /*!< Protects Sector 3 from program or erase operations */ 4484 /* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */ 4485 #define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /*!< PROT4 Bit Offset */ 4486 #define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /*!< Protects Sector 4 from program or erase operations */ 4487 /* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */ 4488 #define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /*!< PROT5 Bit Offset */ 4489 #define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /*!< Protects Sector 5 from program or erase operations */ 4490 /* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */ 4491 #define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /*!< PROT6 Bit Offset */ 4492 #define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /*!< Protects Sector 6 from program or erase operations */ 4493 /* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */ 4494 #define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /*!< PROT7 Bit Offset */ 4495 #define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /*!< Protects Sector 7 from program or erase operations */ 4496 /* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */ 4497 #define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /*!< PROT8 Bit Offset */ 4498 #define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /*!< Protects Sector 8 from program or erase operations */ 4499 /* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */ 4500 #define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /*!< PROT9 Bit Offset */ 4501 #define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /*!< Protects Sector 9 from program or erase operations */ 4502 /* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */ 4503 #define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /*!< PROT10 Bit Offset */ 4504 #define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /*!< Protects Sector 10 from program or erase operations */ 4505 /* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */ 4506 #define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /*!< PROT11 Bit Offset */ 4507 #define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /*!< Protects Sector 11 from program or erase operations */ 4508 /* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */ 4509 #define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /*!< PROT12 Bit Offset */ 4510 #define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /*!< Protects Sector 12 from program or erase operations */ 4511 /* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */ 4512 #define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /*!< PROT13 Bit Offset */ 4513 #define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /*!< Protects Sector 13 from program or erase operations */ 4514 /* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */ 4515 #define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /*!< PROT14 Bit Offset */ 4516 #define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /*!< Protects Sector 14 from program or erase operations */ 4517 /* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */ 4518 #define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /*!< PROT15 Bit Offset */ 4519 #define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /*!< Protects Sector 15 from program or erase operations */ 4520 /* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */ 4521 #define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /*!< PROT16 Bit Offset */ 4522 #define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /*!< Protects Sector 16 from program or erase operations */ 4523 /* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */ 4524 #define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /*!< PROT17 Bit Offset */ 4525 #define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /*!< Protects Sector 17 from program or erase operations */ 4526 /* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */ 4527 #define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /*!< PROT18 Bit Offset */ 4528 #define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /*!< Protects Sector 18 from program or erase operations */ 4529 /* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */ 4530 #define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /*!< PROT19 Bit Offset */ 4531 #define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /*!< Protects Sector 19 from program or erase operations */ 4532 /* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */ 4533 #define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /*!< PROT20 Bit Offset */ 4534 #define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /*!< Protects Sector 20 from program or erase operations */ 4535 /* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */ 4536 #define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /*!< PROT21 Bit Offset */ 4537 #define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /*!< Protects Sector 21 from program or erase operations */ 4538 /* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */ 4539 #define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /*!< PROT22 Bit Offset */ 4540 #define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /*!< Protects Sector 22 from program or erase operations */ 4541 /* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */ 4542 #define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /*!< PROT23 Bit Offset */ 4543 #define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /*!< Protects Sector 23 from program or erase operations */ 4544 /* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */ 4545 #define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /*!< PROT24 Bit Offset */ 4546 #define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /*!< Protects Sector 24 from program or erase operations */ 4547 /* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */ 4548 #define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /*!< PROT25 Bit Offset */ 4549 #define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /*!< Protects Sector 25 from program or erase operations */ 4550 /* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */ 4551 #define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /*!< PROT26 Bit Offset */ 4552 #define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /*!< Protects Sector 26 from program or erase operations */ 4553 /* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */ 4554 #define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /*!< PROT27 Bit Offset */ 4555 #define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /*!< Protects Sector 27 from program or erase operations */ 4556 /* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */ 4557 #define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /*!< PROT28 Bit Offset */ 4558 #define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /*!< Protects Sector 28 from program or erase operations */ 4559 /* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */ 4560 #define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /*!< PROT29 Bit Offset */ 4561 #define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /*!< Protects Sector 29 from program or erase operations */ 4562 /* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */ 4563 #define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /*!< PROT30 Bit Offset */ 4564 #define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /*!< Protects Sector 30 from program or erase operations */ 4565 /* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */ 4566 #define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /*!< PROT31 Bit Offset */ 4567 #define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /*!< Protects Sector 31 from program or erase operations */ 4568 /* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */ 4569 #define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /*!< I_BMRK Bit Offset */ 4570 #define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001) 4571 /* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */ 4572 #define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /*!< D_BMRK Bit Offset */ 4573 #define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002) 4574 /* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */ 4575 #define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /*!< CMP_EN Bit Offset */ 4576 #define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004) 4577 /* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */ 4578 #define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /*!< CMP_SEL Bit Offset */ 4579 #define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008) 4580 /* FLCTL_IFG[RDBRST] Bits */ 4581 #define FLCTL_IFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4582 #define FLCTL_IFG_RDBRST ((uint32_t)0x00000001) 4583 /* FLCTL_IFG[AVPRE] Bits */ 4584 #define FLCTL_IFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4585 #define FLCTL_IFG_AVPRE ((uint32_t)0x00000002) 4586 /* FLCTL_IFG[AVPST] Bits */ 4587 #define FLCTL_IFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4588 #define FLCTL_IFG_AVPST ((uint32_t)0x00000004) 4589 /* FLCTL_IFG[PRG] Bits */ 4590 #define FLCTL_IFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4591 #define FLCTL_IFG_PRG ((uint32_t)0x00000008) 4592 /* FLCTL_IFG[PRGB] Bits */ 4593 #define FLCTL_IFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4594 #define FLCTL_IFG_PRGB ((uint32_t)0x00000010) 4595 /* FLCTL_IFG[ERASE] Bits */ 4596 #define FLCTL_IFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4597 #define FLCTL_IFG_ERASE ((uint32_t)0x00000020) 4598 /* FLCTL_IFG[BMRK] Bits */ 4599 #define FLCTL_IFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4600 #define FLCTL_IFG_BMRK ((uint32_t)0x00000100) 4601 /* FLCTL_IFG[PRG_ERR] Bits */ 4602 #define FLCTL_IFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4603 #define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200) 4604 /* FLCTL_IE[RDBRST] Bits */ 4605 #define FLCTL_IE_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4606 #define FLCTL_IE_RDBRST ((uint32_t)0x00000001) 4607 /* FLCTL_IE[AVPRE] Bits */ 4608 #define FLCTL_IE_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4609 #define FLCTL_IE_AVPRE ((uint32_t)0x00000002) 4610 /* FLCTL_IE[AVPST] Bits */ 4611 #define FLCTL_IE_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4612 #define FLCTL_IE_AVPST ((uint32_t)0x00000004) 4613 /* FLCTL_IE[PRG] Bits */ 4614 #define FLCTL_IE_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4615 #define FLCTL_IE_PRG ((uint32_t)0x00000008) 4616 /* FLCTL_IE[PRGB] Bits */ 4617 #define FLCTL_IE_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4618 #define FLCTL_IE_PRGB ((uint32_t)0x00000010) 4619 /* FLCTL_IE[ERASE] Bits */ 4620 #define FLCTL_IE_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4621 #define FLCTL_IE_ERASE ((uint32_t)0x00000020) 4622 /* FLCTL_IE[BMRK] Bits */ 4623 #define FLCTL_IE_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4624 #define FLCTL_IE_BMRK ((uint32_t)0x00000100) 4625 /* FLCTL_IE[PRG_ERR] Bits */ 4626 #define FLCTL_IE_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4627 #define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200) 4628 /* FLCTL_CLRIFG[RDBRST] Bits */ 4629 #define FLCTL_CLRIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4630 #define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001) 4631 /* FLCTL_CLRIFG[AVPRE] Bits */ 4632 #define FLCTL_CLRIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4633 #define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002) 4634 /* FLCTL_CLRIFG[AVPST] Bits */ 4635 #define FLCTL_CLRIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4636 #define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004) 4637 /* FLCTL_CLRIFG[PRG] Bits */ 4638 #define FLCTL_CLRIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4639 #define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008) 4640 /* FLCTL_CLRIFG[PRGB] Bits */ 4641 #define FLCTL_CLRIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4642 #define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010) 4643 /* FLCTL_CLRIFG[ERASE] Bits */ 4644 #define FLCTL_CLRIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4645 #define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020) 4646 /* FLCTL_CLRIFG[BMRK] Bits */ 4647 #define FLCTL_CLRIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4648 #define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100) 4649 /* FLCTL_CLRIFG[PRG_ERR] Bits */ 4650 #define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4651 #define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200) 4652 /* FLCTL_SETIFG[RDBRST] Bits */ 4653 #define FLCTL_SETIFG_RDBRST_OFS ( 0) /*!< RDBRST Bit Offset */ 4654 #define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001) 4655 /* FLCTL_SETIFG[AVPRE] Bits */ 4656 #define FLCTL_SETIFG_AVPRE_OFS ( 1) /*!< AVPRE Bit Offset */ 4657 #define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002) 4658 /* FLCTL_SETIFG[AVPST] Bits */ 4659 #define FLCTL_SETIFG_AVPST_OFS ( 2) /*!< AVPST Bit Offset */ 4660 #define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004) 4661 /* FLCTL_SETIFG[PRG] Bits */ 4662 #define FLCTL_SETIFG_PRG_OFS ( 3) /*!< PRG Bit Offset */ 4663 #define FLCTL_SETIFG_PRG ((uint32_t)0x00000008) 4664 /* FLCTL_SETIFG[PRGB] Bits */ 4665 #define FLCTL_SETIFG_PRGB_OFS ( 4) /*!< PRGB Bit Offset */ 4666 #define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010) 4667 /* FLCTL_SETIFG[ERASE] Bits */ 4668 #define FLCTL_SETIFG_ERASE_OFS ( 5) /*!< ERASE Bit Offset */ 4669 #define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020) 4670 /* FLCTL_SETIFG[BMRK] Bits */ 4671 #define FLCTL_SETIFG_BMRK_OFS ( 8) /*!< BMRK Bit Offset */ 4672 #define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100) 4673 /* FLCTL_SETIFG[PRG_ERR] Bits */ 4674 #define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /*!< PRG_ERR Bit Offset */ 4675 #define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200) 4676 /* FLCTL_READ_TIMCTL[SETUP] Bits */ 4677 #define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4678 #define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4679 /* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */ 4680 #define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /*!< IREF_BOOST1 Bit Offset */ 4681 #define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /*!< IREF_BOOST1 Bit Mask */ 4682 /* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */ 4683 #define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /*!< SETUP_LONG Bit Offset */ 4684 #define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /*!< SETUP_LONG Bit Mask */ 4685 /* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */ 4686 #define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4687 #define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4688 /* FLCTL_PRGVER_TIMCTL[SETUP] Bits */ 4689 #define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4690 #define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4691 /* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */ 4692 #define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4693 #define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /*!< ACTIVE Bit Mask */ 4694 /* FLCTL_PRGVER_TIMCTL[HOLD] Bits */ 4695 #define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /*!< HOLD Bit Offset */ 4696 #define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /*!< HOLD Bit Mask */ 4697 /* FLCTL_ERSVER_TIMCTL[SETUP] Bits */ 4698 #define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4699 #define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4700 /* FLCTL_LKGVER_TIMCTL[SETUP] Bits */ 4701 #define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4702 #define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4703 /* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */ 4704 #define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4705 #define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4706 /* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */ 4707 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4708 #define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ 4709 /* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */ 4710 #define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ 4711 #define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ 4712 /* FLCTL_ERASE_TIMCTL[SETUP] Bits */ 4713 #define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /*!< SETUP Bit Offset */ 4714 #define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /*!< SETUP Bit Mask */ 4715 /* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */ 4716 #define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4717 #define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ 4718 /* FLCTL_ERASE_TIMCTL[HOLD] Bits */ 4719 #define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /*!< HOLD Bit Offset */ 4720 #define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /*!< HOLD Bit Mask */ 4721 /* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */ 4722 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /*!< BOOST_ACTIVE Bit Offset */ 4723 #define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /*!< BOOST_ACTIVE Bit Mask */ 4724 /* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */ 4725 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /*!< BOOST_HOLD Bit Offset */ 4726 #define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /*!< BOOST_HOLD Bit Mask */ 4727 /* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */ 4728 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /*!< ACTIVE Bit Offset */ 4729 #define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /*!< ACTIVE Bit Mask */ 4730 4731 /****************************************************************************** 4732 * FL_BOOTOVER_MAILBOX Bits 4733 ******************************************************************************/ 4734 4735 /****************************************************************************** 4736 * FPB Bits 4737 ******************************************************************************/ 4738 4739 4740 /****************************************************************************** 4741 * FPU Bits 4742 ******************************************************************************/ 4743 4744 4745 /****************************************************************************** 4746 * ITM Bits 4747 ******************************************************************************/ 4748 4749 4750 /****************************************************************************** 4751 * MPU Bits 4752 ******************************************************************************/ 4753 4754 /* Pre-defined bitfield values */ 4755 4756 /* MPU_RASR_SIZE Bitfield Bits */ 4757 #define MPU_RASR_SIZE__32B ((uint32_t)0x00000008) /*!< 32B */ 4758 #define MPU_RASR_SIZE__64B ((uint32_t)0x0000000A) /*!< 64B */ 4759 #define MPU_RASR_SIZE__128B ((uint32_t)0x0000000C) /*!< 128B */ 4760 #define MPU_RASR_SIZE__256B ((uint32_t)0x0000000E) /*!< 256B */ 4761 #define MPU_RASR_SIZE__512B ((uint32_t)0x00000010) /*!< 512B */ 4762 #define MPU_RASR_SIZE__1K ((uint32_t)0x00000012) /*!< 1KB */ 4763 #define MPU_RASR_SIZE__2K ((uint32_t)0x00000014) /*!< 2KB */ 4764 #define MPU_RASR_SIZE__4K ((uint32_t)0x00000016) /*!< 4KB */ 4765 #define MPU_RASR_SIZE__8K ((uint32_t)0x00000018) /*!< 8KB */ 4766 #define MPU_RASR_SIZE__16K ((uint32_t)0x0000001A) /*!< 16KB */ 4767 #define MPU_RASR_SIZE__32K ((uint32_t)0x0000001C) /*!< 32KB */ 4768 #define MPU_RASR_SIZE__64K ((uint32_t)0x0000001E) /*!< 64KB */ 4769 #define MPU_RASR_SIZE__128K ((uint32_t)0x00000020) /*!< 128KB */ 4770 #define MPU_RASR_SIZE__256K ((uint32_t)0x00000022) /*!< 256KB */ 4771 #define MPU_RASR_SIZE__512K ((uint32_t)0x00000024) /*!< 512KB */ 4772 #define MPU_RASR_SIZE__1M ((uint32_t)0x00000026) /*!< 1MB */ 4773 #define MPU_RASR_SIZE__2M ((uint32_t)0x00000028) /*!< 2MB */ 4774 #define MPU_RASR_SIZE__4M ((uint32_t)0x0000002A) /*!< 4MB */ 4775 #define MPU_RASR_SIZE__8M ((uint32_t)0x0000002C) /*!< 8MB */ 4776 #define MPU_RASR_SIZE__16M ((uint32_t)0x0000002E) /*!< 16MB */ 4777 #define MPU_RASR_SIZE__32M ((uint32_t)0x00000030) /*!< 32MB */ 4778 #define MPU_RASR_SIZE__64M ((uint32_t)0x00000032) /*!< 64MB */ 4779 #define MPU_RASR_SIZE__128M ((uint32_t)0x00000034) /*!< 128MB */ 4780 #define MPU_RASR_SIZE__256M ((uint32_t)0x00000036) /*!< 256MB */ 4781 #define MPU_RASR_SIZE__512M ((uint32_t)0x00000038) /*!< 512MB */ 4782 #define MPU_RASR_SIZE__1G ((uint32_t)0x0000003A) /*!< 1GB */ 4783 #define MPU_RASR_SIZE__2G ((uint32_t)0x0000003C) /*!< 2GB */ 4784 #define MPU_RASR_SIZE__4G ((uint32_t)0x0000003E) /*!< 4GB */ 4785 4786 /* MPU_RASR_AP Bitfield Bits */ 4787 #define MPU_RASR_AP_PRV_NO_USR_NO ((uint32_t)0x00000000) /*!< Privileged permissions: No access. User permissions: No access. */ 4788 #define MPU_RASR_AP_PRV_RW_USR_NO ((uint32_t)0x01000000) /*!< Privileged permissions: Read-write. User permissions: No access. */ 4789 #define MPU_RASR_AP_PRV_RW_USR_RO ((uint32_t)0x02000000) /*!< Privileged permissions: Read-write. User permissions: Read-only. */ 4790 #define MPU_RASR_AP_PRV_RW_USR_RW ((uint32_t)0x03000000) /*!< Privileged permissions: Read-write. User permissions: Read-write. */ 4791 #define MPU_RASR_AP_PRV_RO_USR_NO ((uint32_t)0x05000000) /*!< Privileged permissions: Read-only. User permissions: No access. */ 4792 #define MPU_RASR_AP_PRV_RO_USR_RO ((uint32_t)0x06000000) /*!< Privileged permissions: Read-only. User permissions: Read-only. */ 4793 4794 /* MPU_RASR_XN Bitfield Bits */ 4795 #define MPU_RASR_AP_EXEC ((uint32_t)0x00000000) /*!< Instruction access enabled */ 4796 #define MPU_RASR_AP_NOEXEC ((uint32_t)0x10000000) /*!< Instruction access disabled */ 4797 4798 4799 /****************************************************************************** 4800 * NVIC Bits 4801 ******************************************************************************/ 4802 4803 /* NVIC_IPR0[NVIC_IPR0_PRI_0] Bits */ 4804 #define NVIC_IPR0_PRI_0_OFS ( 0) /*!< PRI_0 Offset */ 4805 #define NVIC_IPR0_PRI_0_M ((uint32_t)0x000000ff) /* */ 4806 /* NVIC_IPR0[NVIC_IPR0_PRI_1] Bits */ 4807 #define NVIC_IPR0_PRI_1_OFS ( 8) /*!< PRI_1 Offset */ 4808 #define NVIC_IPR0_PRI_1_M ((uint32_t)0x0000ff00) /* */ 4809 /* NVIC_IPR0[NVIC_IPR0_PRI_2] Bits */ 4810 #define NVIC_IPR0_PRI_2_OFS (16) /*!< PRI_2 Offset */ 4811 #define NVIC_IPR0_PRI_2_M ((uint32_t)0x00ff0000) /* */ 4812 /* NVIC_IPR0[NVIC_IPR0_PRI_3] Bits */ 4813 #define NVIC_IPR0_PRI_3_OFS (24) /*!< PRI_3 Offset */ 4814 #define NVIC_IPR0_PRI_3_M ((uint32_t)0xff000000) /* */ 4815 /* NVIC_IPR1[NVIC_IPR1_PRI_4] Bits */ 4816 #define NVIC_IPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ 4817 #define NVIC_IPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ 4818 /* NVIC_IPR1[NVIC_IPR1_PRI_5] Bits */ 4819 #define NVIC_IPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ 4820 #define NVIC_IPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ 4821 /* NVIC_IPR1[NVIC_IPR1_PRI_6] Bits */ 4822 #define NVIC_IPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ 4823 #define NVIC_IPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ 4824 /* NVIC_IPR1[NVIC_IPR1_PRI_7] Bits */ 4825 #define NVIC_IPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ 4826 #define NVIC_IPR1_PRI_7_M ((uint32_t)0xff000000) /* */ 4827 /* NVIC_IPR2[NVIC_IPR2_PRI_8] Bits */ 4828 #define NVIC_IPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ 4829 #define NVIC_IPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ 4830 /* NVIC_IPR2[NVIC_IPR2_PRI_9] Bits */ 4831 #define NVIC_IPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ 4832 #define NVIC_IPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ 4833 /* NVIC_IPR2[NVIC_IPR2_PRI_10] Bits */ 4834 #define NVIC_IPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ 4835 #define NVIC_IPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ 4836 /* NVIC_IPR2[NVIC_IPR2_PRI_11] Bits */ 4837 #define NVIC_IPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ 4838 #define NVIC_IPR2_PRI_11_M ((uint32_t)0xff000000) /* */ 4839 /* NVIC_IPR3[NVIC_IPR3_PRI_12] Bits */ 4840 #define NVIC_IPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ 4841 #define NVIC_IPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ 4842 /* NVIC_IPR3[NVIC_IPR3_PRI_13] Bits */ 4843 #define NVIC_IPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ 4844 #define NVIC_IPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ 4845 /* NVIC_IPR3[NVIC_IPR3_PRI_14] Bits */ 4846 #define NVIC_IPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ 4847 #define NVIC_IPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ 4848 /* NVIC_IPR3[NVIC_IPR3_PRI_15] Bits */ 4849 #define NVIC_IPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ 4850 #define NVIC_IPR3_PRI_15_M ((uint32_t)0xff000000) /* */ 4851 /* NVIC_IPR4[NVIC_IPR4_PRI_16] Bits */ 4852 #define NVIC_IPR4_PRI_16_OFS ( 0) /*!< PRI_16 Offset */ 4853 #define NVIC_IPR4_PRI_16_M ((uint32_t)0x000000ff) /* */ 4854 /* NVIC_IPR4[NVIC_IPR4_PRI_17] Bits */ 4855 #define NVIC_IPR4_PRI_17_OFS ( 8) /*!< PRI_17 Offset */ 4856 #define NVIC_IPR4_PRI_17_M ((uint32_t)0x0000ff00) /* */ 4857 /* NVIC_IPR4[NVIC_IPR4_PRI_18] Bits */ 4858 #define NVIC_IPR4_PRI_18_OFS (16) /*!< PRI_18 Offset */ 4859 #define NVIC_IPR4_PRI_18_M ((uint32_t)0x00ff0000) /* */ 4860 /* NVIC_IPR4[NVIC_IPR4_PRI_19] Bits */ 4861 #define NVIC_IPR4_PRI_19_OFS (24) /*!< PRI_19 Offset */ 4862 #define NVIC_IPR4_PRI_19_M ((uint32_t)0xff000000) /* */ 4863 /* NVIC_IPR5[NVIC_IPR5_PRI_20] Bits */ 4864 #define NVIC_IPR5_PRI_20_OFS ( 0) /*!< PRI_20 Offset */ 4865 #define NVIC_IPR5_PRI_20_M ((uint32_t)0x000000ff) /* */ 4866 /* NVIC_IPR5[NVIC_IPR5_PRI_21] Bits */ 4867 #define NVIC_IPR5_PRI_21_OFS ( 8) /*!< PRI_21 Offset */ 4868 #define NVIC_IPR5_PRI_21_M ((uint32_t)0x0000ff00) /* */ 4869 /* NVIC_IPR5[NVIC_IPR5_PRI_22] Bits */ 4870 #define NVIC_IPR5_PRI_22_OFS (16) /*!< PRI_22 Offset */ 4871 #define NVIC_IPR5_PRI_22_M ((uint32_t)0x00ff0000) /* */ 4872 /* NVIC_IPR5[NVIC_IPR5_PRI_23] Bits */ 4873 #define NVIC_IPR5_PRI_23_OFS (24) /*!< PRI_23 Offset */ 4874 #define NVIC_IPR5_PRI_23_M ((uint32_t)0xff000000) /* */ 4875 /* NVIC_IPR6[NVIC_IPR6_PRI_24] Bits */ 4876 #define NVIC_IPR6_PRI_24_OFS ( 0) /*!< PRI_24 Offset */ 4877 #define NVIC_IPR6_PRI_24_M ((uint32_t)0x000000ff) /* */ 4878 /* NVIC_IPR6[NVIC_IPR6_PRI_25] Bits */ 4879 #define NVIC_IPR6_PRI_25_OFS ( 8) /*!< PRI_25 Offset */ 4880 #define NVIC_IPR6_PRI_25_M ((uint32_t)0x0000ff00) /* */ 4881 /* NVIC_IPR6[NVIC_IPR6_PRI_26] Bits */ 4882 #define NVIC_IPR6_PRI_26_OFS (16) /*!< PRI_26 Offset */ 4883 #define NVIC_IPR6_PRI_26_M ((uint32_t)0x00ff0000) /* */ 4884 /* NVIC_IPR6[NVIC_IPR6_PRI_27] Bits */ 4885 #define NVIC_IPR6_PRI_27_OFS (24) /*!< PRI_27 Offset */ 4886 #define NVIC_IPR6_PRI_27_M ((uint32_t)0xff000000) /* */ 4887 /* NVIC_IPR7[NVIC_IPR7_PRI_28] Bits */ 4888 #define NVIC_IPR7_PRI_28_OFS ( 0) /*!< PRI_28 Offset */ 4889 #define NVIC_IPR7_PRI_28_M ((uint32_t)0x000000ff) /* */ 4890 /* NVIC_IPR7[NVIC_IPR7_PRI_29] Bits */ 4891 #define NVIC_IPR7_PRI_29_OFS ( 8) /*!< PRI_29 Offset */ 4892 #define NVIC_IPR7_PRI_29_M ((uint32_t)0x0000ff00) /* */ 4893 /* NVIC_IPR7[NVIC_IPR7_PRI_30] Bits */ 4894 #define NVIC_IPR7_PRI_30_OFS (16) /*!< PRI_30 Offset */ 4895 #define NVIC_IPR7_PRI_30_M ((uint32_t)0x00ff0000) /* */ 4896 /* NVIC_IPR7[NVIC_IPR7_PRI_31] Bits */ 4897 #define NVIC_IPR7_PRI_31_OFS (24) /*!< PRI_31 Offset */ 4898 #define NVIC_IPR7_PRI_31_M ((uint32_t)0xff000000) /* */ 4899 /* NVIC_IPR8[NVIC_IPR8_PRI_32] Bits */ 4900 #define NVIC_IPR8_PRI_32_OFS ( 0) /*!< PRI_32 Offset */ 4901 #define NVIC_IPR8_PRI_32_M ((uint32_t)0x000000ff) /* */ 4902 /* NVIC_IPR8[NVIC_IPR8_PRI_33] Bits */ 4903 #define NVIC_IPR8_PRI_33_OFS ( 8) /*!< PRI_33 Offset */ 4904 #define NVIC_IPR8_PRI_33_M ((uint32_t)0x0000ff00) /* */ 4905 /* NVIC_IPR8[NVIC_IPR8_PRI_34] Bits */ 4906 #define NVIC_IPR8_PRI_34_OFS (16) /*!< PRI_34 Offset */ 4907 #define NVIC_IPR8_PRI_34_M ((uint32_t)0x00ff0000) /* */ 4908 /* NVIC_IPR8[NVIC_IPR8_PRI_35] Bits */ 4909 #define NVIC_IPR8_PRI_35_OFS (24) /*!< PRI_35 Offset */ 4910 #define NVIC_IPR8_PRI_35_M ((uint32_t)0xff000000) /* */ 4911 /* NVIC_IPR9[NVIC_IPR9_PRI_36] Bits */ 4912 #define NVIC_IPR9_PRI_36_OFS ( 0) /*!< PRI_36 Offset */ 4913 #define NVIC_IPR9_PRI_36_M ((uint32_t)0x000000ff) /* */ 4914 /* NVIC_IPR9[NVIC_IPR9_PRI_37] Bits */ 4915 #define NVIC_IPR9_PRI_37_OFS ( 8) /*!< PRI_37 Offset */ 4916 #define NVIC_IPR9_PRI_37_M ((uint32_t)0x0000ff00) /* */ 4917 /* NVIC_IPR9[NVIC_IPR9_PRI_38] Bits */ 4918 #define NVIC_IPR9_PRI_38_OFS (16) /*!< PRI_38 Offset */ 4919 #define NVIC_IPR9_PRI_38_M ((uint32_t)0x00ff0000) /* */ 4920 /* NVIC_IPR9[NVIC_IPR9_PRI_39] Bits */ 4921 #define NVIC_IPR9_PRI_39_OFS (24) /*!< PRI_39 Offset */ 4922 #define NVIC_IPR9_PRI_39_M ((uint32_t)0xff000000) /* */ 4923 /* NVIC_IPR10[NVIC_IPR10_PRI_40] Bits */ 4924 #define NVIC_IPR10_PRI_40_OFS ( 0) /*!< PRI_40 Offset */ 4925 #define NVIC_IPR10_PRI_40_M ((uint32_t)0x000000ff) /* */ 4926 /* NVIC_IPR10[NVIC_IPR10_PRI_41] Bits */ 4927 #define NVIC_IPR10_PRI_41_OFS ( 8) /*!< PRI_41 Offset */ 4928 #define NVIC_IPR10_PRI_41_M ((uint32_t)0x0000ff00) /* */ 4929 /* NVIC_IPR10[NVIC_IPR10_PRI_42] Bits */ 4930 #define NVIC_IPR10_PRI_42_OFS (16) /*!< PRI_42 Offset */ 4931 #define NVIC_IPR10_PRI_42_M ((uint32_t)0x00ff0000) /* */ 4932 /* NVIC_IPR10[NVIC_IPR10_PRI_43] Bits */ 4933 #define NVIC_IPR10_PRI_43_OFS (24) /*!< PRI_43 Offset */ 4934 #define NVIC_IPR10_PRI_43_M ((uint32_t)0xff000000) /* */ 4935 /* NVIC_IPR11[NVIC_IPR11_PRI_44] Bits */ 4936 #define NVIC_IPR11_PRI_44_OFS ( 0) /*!< PRI_44 Offset */ 4937 #define NVIC_IPR11_PRI_44_M ((uint32_t)0x000000ff) /* */ 4938 /* NVIC_IPR11[NVIC_IPR11_PRI_45] Bits */ 4939 #define NVIC_IPR11_PRI_45_OFS ( 8) /*!< PRI_45 Offset */ 4940 #define NVIC_IPR11_PRI_45_M ((uint32_t)0x0000ff00) /* */ 4941 /* NVIC_IPR11[NVIC_IPR11_PRI_46] Bits */ 4942 #define NVIC_IPR11_PRI_46_OFS (16) /*!< PRI_46 Offset */ 4943 #define NVIC_IPR11_PRI_46_M ((uint32_t)0x00ff0000) /* */ 4944 /* NVIC_IPR11[NVIC_IPR11_PRI_47] Bits */ 4945 #define NVIC_IPR11_PRI_47_OFS (24) /*!< PRI_47 Offset */ 4946 #define NVIC_IPR11_PRI_47_M ((uint32_t)0xff000000) /* */ 4947 /* NVIC_IPR12[NVIC_IPR12_PRI_48] Bits */ 4948 #define NVIC_IPR12_PRI_48_OFS ( 0) /*!< PRI_48 Offset */ 4949 #define NVIC_IPR12_PRI_48_M ((uint32_t)0x000000ff) /* */ 4950 /* NVIC_IPR12[NVIC_IPR12_PRI_49] Bits */ 4951 #define NVIC_IPR12_PRI_49_OFS ( 8) /*!< PRI_49 Offset */ 4952 #define NVIC_IPR12_PRI_49_M ((uint32_t)0x0000ff00) /* */ 4953 /* NVIC_IPR12[NVIC_IPR12_PRI_50] Bits */ 4954 #define NVIC_IPR12_PRI_50_OFS (16) /*!< PRI_50 Offset */ 4955 #define NVIC_IPR12_PRI_50_M ((uint32_t)0x00ff0000) /* */ 4956 /* NVIC_IPR12[NVIC_IPR12_PRI_51] Bits */ 4957 #define NVIC_IPR12_PRI_51_OFS (24) /*!< PRI_51 Offset */ 4958 #define NVIC_IPR12_PRI_51_M ((uint32_t)0xff000000) /* */ 4959 /* NVIC_IPR13[NVIC_IPR13_PRI_52] Bits */ 4960 #define NVIC_IPR13_PRI_52_OFS ( 0) /*!< PRI_52 Offset */ 4961 #define NVIC_IPR13_PRI_52_M ((uint32_t)0x000000ff) /* */ 4962 /* NVIC_IPR13[NVIC_IPR13_PRI_53] Bits */ 4963 #define NVIC_IPR13_PRI_53_OFS ( 8) /*!< PRI_53 Offset */ 4964 #define NVIC_IPR13_PRI_53_M ((uint32_t)0x0000ff00) /* */ 4965 /* NVIC_IPR13[NVIC_IPR13_PRI_54] Bits */ 4966 #define NVIC_IPR13_PRI_54_OFS (16) /*!< PRI_54 Offset */ 4967 #define NVIC_IPR13_PRI_54_M ((uint32_t)0x00ff0000) /* */ 4968 /* NVIC_IPR13[NVIC_IPR13_PRI_55] Bits */ 4969 #define NVIC_IPR13_PRI_55_OFS (24) /*!< PRI_55 Offset */ 4970 #define NVIC_IPR13_PRI_55_M ((uint32_t)0xff000000) /* */ 4971 /* NVIC_IPR14[NVIC_IPR14_PRI_56] Bits */ 4972 #define NVIC_IPR14_PRI_56_OFS ( 0) /*!< PRI_56 Offset */ 4973 #define NVIC_IPR14_PRI_56_M ((uint32_t)0x000000ff) /* */ 4974 /* NVIC_IPR14[NVIC_IPR14_PRI_57] Bits */ 4975 #define NVIC_IPR14_PRI_57_OFS ( 8) /*!< PRI_57 Offset */ 4976 #define NVIC_IPR14_PRI_57_M ((uint32_t)0x0000ff00) /* */ 4977 /* NVIC_IPR14[NVIC_IPR14_PRI_58] Bits */ 4978 #define NVIC_IPR14_PRI_58_OFS (16) /*!< PRI_58 Offset */ 4979 #define NVIC_IPR14_PRI_58_M ((uint32_t)0x00ff0000) /* */ 4980 /* NVIC_IPR14[NVIC_IPR14_PRI_59] Bits */ 4981 #define NVIC_IPR14_PRI_59_OFS (24) /*!< PRI_59 Offset */ 4982 #define NVIC_IPR14_PRI_59_M ((uint32_t)0xff000000) /* */ 4983 /* NVIC_IPR15[NVIC_IPR15_PRI_60] Bits */ 4984 #define NVIC_IPR15_PRI_60_OFS ( 0) /*!< PRI_60 Offset */ 4985 #define NVIC_IPR15_PRI_60_M ((uint32_t)0x000000ff) /* */ 4986 /* NVIC_IPR15[NVIC_IPR15_PRI_61] Bits */ 4987 #define NVIC_IPR15_PRI_61_OFS ( 8) /*!< PRI_61 Offset */ 4988 #define NVIC_IPR15_PRI_61_M ((uint32_t)0x0000ff00) /* */ 4989 /* NVIC_IPR15[NVIC_IPR15_PRI_62] Bits */ 4990 #define NVIC_IPR15_PRI_62_OFS (16) /*!< PRI_62 Offset */ 4991 #define NVIC_IPR15_PRI_62_M ((uint32_t)0x00ff0000) /* */ 4992 /* NVIC_IPR15[NVIC_IPR15_PRI_63] Bits */ 4993 #define NVIC_IPR15_PRI_63_OFS (24) /*!< PRI_63 Offset */ 4994 #define NVIC_IPR15_PRI_63_M ((uint32_t)0xff000000) /* */ 4995 4996 4997 /****************************************************************************** 4998 * PCM Bits 4999 ******************************************************************************/ 5000 /* PCM_CTL0[AMR] Bits */ 5001 #define PCM_CTL0_AMR_OFS ( 0) /*!< AMR Bit Offset */ 5002 #define PCM_CTL0_AMR_MASK ((uint32_t)0x0000000F) /*!< AMR Bit Mask */ 5003 #define PCM_CTL0_AMR0 ((uint32_t)0x00000001) /*!< AMR Bit 0 */ 5004 #define PCM_CTL0_AMR1 ((uint32_t)0x00000002) /*!< AMR Bit 1 */ 5005 #define PCM_CTL0_AMR2 ((uint32_t)0x00000004) /*!< AMR Bit 2 */ 5006 #define PCM_CTL0_AMR3 ((uint32_t)0x00000008) /*!< AMR Bit 3 */ 5007 #define PCM_CTL0_AMR_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 5008 #define PCM_CTL0_AMR_1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ 5009 #define PCM_CTL0_AMR_4 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 5010 #define PCM_CTL0_AMR_5 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 5011 #define PCM_CTL0_AMR_8 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 5012 #define PCM_CTL0_AMR_9 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 5013 #define PCM_CTL0_AMR__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 5014 #define PCM_CTL0_AMR__AM_LDO_VCORE1 ((uint32_t)0x00000001) /*!< LDO based Active Mode at Core voltage setting 1. */ 5015 #define PCM_CTL0_AMR__AM_DCDC_VCORE0 ((uint32_t)0x00000004) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 5016 #define PCM_CTL0_AMR__AM_DCDC_VCORE1 ((uint32_t)0x00000005) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 5017 #define PCM_CTL0_AMR__AM_LF_VCORE0 ((uint32_t)0x00000008) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 5018 #define PCM_CTL0_AMR__AM_LF_VCORE1 ((uint32_t)0x00000009) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 5019 /* PCM_CTL0[LPMR] Bits */ 5020 #define PCM_CTL0_LPMR_OFS ( 4) /*!< LPMR Bit Offset */ 5021 #define PCM_CTL0_LPMR_MASK ((uint32_t)0x000000F0) /*!< LPMR Bit Mask */ 5022 #define PCM_CTL0_LPMR0 ((uint32_t)0x00000010) /*!< LPMR Bit 0 */ 5023 #define PCM_CTL0_LPMR1 ((uint32_t)0x00000020) /*!< LPMR Bit 1 */ 5024 #define PCM_CTL0_LPMR2 ((uint32_t)0x00000040) /*!< LPMR Bit 2 */ 5025 #define PCM_CTL0_LPMR3 ((uint32_t)0x00000080) /*!< LPMR Bit 3 */ 5026 #define PCM_CTL0_LPMR_0 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ 5027 /* entered. */ 5028 #define PCM_CTL0_LPMR_10 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ 5029 #define PCM_CTL0_LPMR_12 ((uint32_t)0x000000C0) /*!< LPM4.5 */ 5030 #define PCM_CTL0_LPMR__LPM3 ((uint32_t)0x00000000) /*!< LPM3. Core voltage setting is similar to the mode from which LPM3 is */ 5031 /* entered. */ 5032 #define PCM_CTL0_LPMR__LPM35 ((uint32_t)0x000000A0) /*!< LPM3.5. Core voltage setting 0. */ 5033 #define PCM_CTL0_LPMR__LPM45 ((uint32_t)0x000000C0) /*!< LPM4.5 */ 5034 /* PCM_CTL0[CPM] Bits */ 5035 #define PCM_CTL0_CPM_OFS ( 8) /*!< CPM Bit Offset */ 5036 #define PCM_CTL0_CPM_MASK ((uint32_t)0x00003F00) /*!< CPM Bit Mask */ 5037 #define PCM_CTL0_CPM0 ((uint32_t)0x00000100) /*!< CPM Bit 0 */ 5038 #define PCM_CTL0_CPM1 ((uint32_t)0x00000200) /*!< CPM Bit 1 */ 5039 #define PCM_CTL0_CPM2 ((uint32_t)0x00000400) /*!< CPM Bit 2 */ 5040 #define PCM_CTL0_CPM3 ((uint32_t)0x00000800) /*!< CPM Bit 3 */ 5041 #define PCM_CTL0_CPM4 ((uint32_t)0x00001000) /*!< CPM Bit 4 */ 5042 #define PCM_CTL0_CPM5 ((uint32_t)0x00002000) /*!< CPM Bit 5 */ 5043 #define PCM_CTL0_CPM_0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 5044 #define PCM_CTL0_CPM_1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ 5045 #define PCM_CTL0_CPM_4 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 5046 #define PCM_CTL0_CPM_5 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 5047 #define PCM_CTL0_CPM_8 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 5048 #define PCM_CTL0_CPM_9 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 5049 #define PCM_CTL0_CPM_16 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ 5050 #define PCM_CTL0_CPM_17 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ 5051 #define PCM_CTL0_CPM_20 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ 5052 #define PCM_CTL0_CPM_21 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ 5053 #define PCM_CTL0_CPM_24 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ 5054 #define PCM_CTL0_CPM_25 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ 5055 #define PCM_CTL0_CPM_32 ((uint32_t)0x00002000) /*!< LPM3 */ 5056 #define PCM_CTL0_CPM__AM_LDO_VCORE0 ((uint32_t)0x00000000) /*!< LDO based Active Mode at Core voltage setting 0. */ 5057 #define PCM_CTL0_CPM__AM_LDO_VCORE1 ((uint32_t)0x00000100) /*!< LDO based Active Mode at Core voltage setting 1. */ 5058 #define PCM_CTL0_CPM__AM_DCDC_VCORE0 ((uint32_t)0x00000400) /*!< DC-DC based Active Mode at Core voltage setting 0. */ 5059 #define PCM_CTL0_CPM__AM_DCDC_VCORE1 ((uint32_t)0x00000500) /*!< DC-DC based Active Mode at Core voltage setting 1. */ 5060 #define PCM_CTL0_CPM__AM_LF_VCORE0 ((uint32_t)0x00000800) /*!< Low-Frequency Active Mode at Core voltage setting 0. */ 5061 #define PCM_CTL0_CPM__AM_LF_VCORE1 ((uint32_t)0x00000900) /*!< Low-Frequency Active Mode at Core voltage setting 1. */ 5062 #define PCM_CTL0_CPM__LPM0_LDO_VCORE0 ((uint32_t)0x00001000) /*!< LDO based LPM0 at Core voltage setting 0. */ 5063 #define PCM_CTL0_CPM__LPM0_LDO_VCORE1 ((uint32_t)0x00001100) /*!< LDO based LPM0 at Core voltage setting 1. */ 5064 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE0 ((uint32_t)0x00001400) /*!< DC-DC based LPM0 at Core voltage setting 0. */ 5065 #define PCM_CTL0_CPM__LPM0_DCDC_VCORE1 ((uint32_t)0x00001500) /*!< DC-DC based LPM0 at Core voltage setting 1. */ 5066 #define PCM_CTL0_CPM__LPM0_LF_VCORE0 ((uint32_t)0x00001800) /*!< Low-Frequency LPM0 at Core voltage setting 0. */ 5067 #define PCM_CTL0_CPM__LPM0_LF_VCORE1 ((uint32_t)0x00001900) /*!< Low-Frequency LPM0 at Core voltage setting 1. */ 5068 #define PCM_CTL0_CPM__LPM3 ((uint32_t)0x00002000) /*!< LPM3 */ 5069 /* PCM_CTL0[KEY] Bits */ 5070 #define PCM_CTL0_KEY_OFS (16) /*!< PCMKEY Bit Offset */ 5071 #define PCM_CTL0_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ 5072 /* PCM_CTL1[LOCKLPM5] Bits */ 5073 #define PCM_CTL1_LOCKLPM5_OFS ( 0) /*!< LOCKLPM5 Bit Offset */ 5074 #define PCM_CTL1_LOCKLPM5 ((uint32_t)0x00000001) /*!< Lock LPM5 */ 5075 /* PCM_CTL1[LOCKBKUP] Bits */ 5076 #define PCM_CTL1_LOCKBKUP_OFS ( 1) /*!< LOCKBKUP Bit Offset */ 5077 #define PCM_CTL1_LOCKBKUP ((uint32_t)0x00000002) /*!< Lock Backup */ 5078 /* PCM_CTL1[FORCE_LPM_ENTRY] Bits */ 5079 #define PCM_CTL1_FORCE_LPM_ENTRY_OFS ( 2) /*!< FORCE_LPM_ENTRY Bit Offset */ 5080 #define PCM_CTL1_FORCE_LPM_ENTRY ((uint32_t)0x00000004) /*!< Force LPM entry */ 5081 /* PCM_CTL1[PMR_BUSY] Bits */ 5082 #define PCM_CTL1_PMR_BUSY_OFS ( 8) /*!< PMR_BUSY Bit Offset */ 5083 #define PCM_CTL1_PMR_BUSY ((uint32_t)0x00000100) /*!< Power mode request busy flag */ 5084 /* PCM_CTL1[KEY] Bits */ 5085 #define PCM_CTL1_KEY_OFS (16) /*!< PCMKEY Bit Offset */ 5086 #define PCM_CTL1_KEY_MASK ((uint32_t)0xFFFF0000) /*!< PCMKEY Bit Mask */ 5087 /* PCM_IE[LPM_INVALID_TR_IE] Bits */ 5088 #define PCM_IE_LPM_INVALID_TR_IE_OFS ( 0) /*!< LPM_INVALID_TR_IE Bit Offset */ 5089 #define PCM_IE_LPM_INVALID_TR_IE ((uint32_t)0x00000001) /*!< LPM invalid transition interrupt enable */ 5090 /* PCM_IE[LPM_INVALID_CLK_IE] Bits */ 5091 #define PCM_IE_LPM_INVALID_CLK_IE_OFS ( 1) /*!< LPM_INVALID_CLK_IE Bit Offset */ 5092 #define PCM_IE_LPM_INVALID_CLK_IE ((uint32_t)0x00000002) /*!< LPM invalid clock interrupt enable */ 5093 /* PCM_IE[AM_INVALID_TR_IE] Bits */ 5094 #define PCM_IE_AM_INVALID_TR_IE_OFS ( 2) /*!< AM_INVALID_TR_IE Bit Offset */ 5095 #define PCM_IE_AM_INVALID_TR_IE ((uint32_t)0x00000004) /*!< Active mode invalid transition interrupt enable */ 5096 /* PCM_IE[DCDC_ERROR_IE] Bits */ 5097 #define PCM_IE_DCDC_ERROR_IE_OFS ( 6) /*!< DCDC_ERROR_IE Bit Offset */ 5098 #define PCM_IE_DCDC_ERROR_IE ((uint32_t)0x00000040) /*!< DC-DC error interrupt enable */ 5099 /* PCM_IFG[LPM_INVALID_TR_IFG] Bits */ 5100 #define PCM_IFG_LPM_INVALID_TR_IFG_OFS ( 0) /*!< LPM_INVALID_TR_IFG Bit Offset */ 5101 #define PCM_IFG_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< LPM invalid transition flag */ 5102 /* PCM_IFG[LPM_INVALID_CLK_IFG] Bits */ 5103 #define PCM_IFG_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< LPM_INVALID_CLK_IFG Bit Offset */ 5104 #define PCM_IFG_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< LPM invalid clock flag */ 5105 /* PCM_IFG[AM_INVALID_TR_IFG] Bits */ 5106 #define PCM_IFG_AM_INVALID_TR_IFG_OFS ( 2) /*!< AM_INVALID_TR_IFG Bit Offset */ 5107 #define PCM_IFG_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Active mode invalid transition flag */ 5108 /* PCM_IFG[DCDC_ERROR_IFG] Bits */ 5109 #define PCM_IFG_DCDC_ERROR_IFG_OFS ( 6) /*!< DCDC_ERROR_IFG Bit Offset */ 5110 #define PCM_IFG_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< DC-DC error flag */ 5111 /* PCM_CLRIFG[CLR_LPM_INVALID_TR_IFG] Bits */ 5112 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG_OFS ( 0) /*!< CLR_LPM_INVALID_TR_IFG Bit Offset */ 5113 #define PCM_CLRIFG_CLR_LPM_INVALID_TR_IFG ((uint32_t)0x00000001) /*!< Clear LPM invalid transition flag */ 5114 /* PCM_CLRIFG[CLR_LPM_INVALID_CLK_IFG] Bits */ 5115 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG_OFS ( 1) /*!< CLR_LPM_INVALID_CLK_IFG Bit Offset */ 5116 #define PCM_CLRIFG_CLR_LPM_INVALID_CLK_IFG ((uint32_t)0x00000002) /*!< Clear LPM invalid clock flag */ 5117 /* PCM_CLRIFG[CLR_AM_INVALID_TR_IFG] Bits */ 5118 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG_OFS ( 2) /*!< CLR_AM_INVALID_TR_IFG Bit Offset */ 5119 #define PCM_CLRIFG_CLR_AM_INVALID_TR_IFG ((uint32_t)0x00000004) /*!< Clear active mode invalid transition flag */ 5120 /* PCM_CLRIFG[CLR_DCDC_ERROR_IFG] Bits */ 5121 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG_OFS ( 6) /*!< CLR_DCDC_ERROR_IFG Bit Offset */ 5122 #define PCM_CLRIFG_CLR_DCDC_ERROR_IFG ((uint32_t)0x00000040) /*!< Clear DC-DC error flag */ 5123 /* Pre-defined bitfield values */ 5124 #define PCM_CTL0_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ 5125 #define PCM_CTL1_KEY_VAL ((uint32_t)0x695A0000) /*!< PCM key value */ 5126 5127 5128 /****************************************************************************** 5129 * PMAP Bits 5130 ******************************************************************************/ 5131 /* PMAP_CTL[LOCKED] Bits */ 5132 #define PMAP_CTL_LOCKED_OFS ( 0) /*!< PMAPLOCKED Bit Offset */ 5133 #define PMAP_CTL_LOCKED ((uint16_t)0x0001) /*!< Port mapping lock bit */ 5134 /* PMAP_CTL[PRECFG] Bits */ 5135 #define PMAP_CTL_PRECFG_OFS ( 1) /*!< PMAPRECFG Bit Offset */ 5136 #define PMAP_CTL_PRECFG ((uint16_t)0x0002) /*!< Port mapping reconfiguration control bit */ 5137 /* Pre-defined bitfield values */ 5138 #define PMAP_NONE 0 5139 #define PMAP_UCA0CLK 1 5140 #define PMAP_UCA0RXD 2 5141 #define PMAP_UCA0SOMI 2 5142 #define PMAP_UCA0TXD 3 5143 #define PMAP_UCA0SIMO 3 5144 #define PMAP_UCB0CLK 4 5145 #define PMAP_UCB0SDA 5 5146 #define PMAP_UCB0SIMO 5 5147 #define PMAP_UCB0SCL 6 5148 #define PMAP_UCB0SOMI 6 5149 #define PMAP_UCA1STE 7 5150 #define PMAP_UCA1CLK 8 5151 #define PMAP_UCA1RXD 9 5152 #define PMAP_UCA1SOMI 9 5153 #define PMAP_UCA1TXD 10 5154 #define PMAP_UCA1SIMO 10 5155 #define PMAP_UCA2STE 11 5156 #define PMAP_UCA2CLK 12 5157 #define PMAP_UCA2RXD 13 5158 #define PMAP_UCA2SOMI 13 5159 #define PMAP_UCA2TXD 14 5160 #define PMAP_UCA2SIMO 14 5161 #define PMAP_UCB2STE 15 5162 #define PMAP_UCB2CLK 16 5163 #define PMAP_UCB2SDA 17 5164 #define PMAP_UCB2SIMO 17 5165 #define PMAP_UCB2SCL 18 5166 #define PMAP_UCB2SOMI 18 5167 #define PMAP_TA0CCR0A 19 5168 #define PMAP_TA0CCR1A 20 5169 #define PMAP_TA0CCR2A 21 5170 #define PMAP_TA0CCR3A 22 5171 #define PMAP_TA0CCR4A 23 5172 #define PMAP_TA1CCR1A 24 5173 #define PMAP_TA1CCR2A 25 5174 #define PMAP_TA1CCR3A 26 5175 #define PMAP_TA1CCR4A 27 5176 #define PMAP_TA0CLK 28 5177 #define PMAP_CE0OUT 28 5178 #define PMAP_TA1CLK 29 5179 #define PMAP_CE1OUT 29 5180 #define PMAP_DMAE0 30 5181 #define PMAP_SMCLK 30 5182 #define PMAP_ANALOG 31 5183 5184 #define PMAP_KEYID_VAL ((uint16_t)0x2D52) /*!< Port Mapping Key */ 5185 5186 5187 /****************************************************************************** 5188 * PSS Bits 5189 ******************************************************************************/ 5190 /* PSS_KEY[KEY] Bits */ 5191 #define PSS_KEY_KEY_OFS ( 0) /*!< PSSKEY Bit Offset */ 5192 #define PSS_KEY_KEY_MASK ((uint32_t)0x0000FFFF) /*!< PSSKEY Bit Mask */ 5193 /* PSS_CTL0[SVSMHOFF] Bits */ 5194 #define PSS_CTL0_SVSMHOFF_OFS ( 0) /*!< SVSMHOFF Bit Offset */ 5195 #define PSS_CTL0_SVSMHOFF ((uint32_t)0x00000001) /*!< SVSM high-side off */ 5196 /* PSS_CTL0[SVSMHLP] Bits */ 5197 #define PSS_CTL0_SVSMHLP_OFS ( 1) /*!< SVSMHLP Bit Offset */ 5198 #define PSS_CTL0_SVSMHLP ((uint32_t)0x00000002) /*!< SVSM high-side low power normal performance mode */ 5199 /* PSS_CTL0[SVSMHS] Bits */ 5200 #define PSS_CTL0_SVSMHS_OFS ( 2) /*!< SVSMHS Bit Offset */ 5201 #define PSS_CTL0_SVSMHS ((uint32_t)0x00000004) /*!< Supply supervisor or monitor selection for the high-side */ 5202 /* PSS_CTL0[SVSMHTH] Bits */ 5203 #define PSS_CTL0_SVSMHTH_OFS ( 3) /*!< SVSMHTH Bit Offset */ 5204 #define PSS_CTL0_SVSMHTH_MASK ((uint32_t)0x00000038) /*!< SVSMHTH Bit Mask */ 5205 /* PSS_CTL0[SVMHOE] Bits */ 5206 #define PSS_CTL0_SVMHOE_OFS ( 6) /*!< SVMHOE Bit Offset */ 5207 #define PSS_CTL0_SVMHOE ((uint32_t)0x00000040) /*!< SVSM high-side output enable */ 5208 /* PSS_CTL0[SVMHOUTPOLAL] Bits */ 5209 #define PSS_CTL0_SVMHOUTPOLAL_OFS ( 7) /*!< SVMHOUTPOLAL Bit Offset */ 5210 #define PSS_CTL0_SVMHOUTPOLAL ((uint32_t)0x00000080) /*!< SVMHOUT pin polarity active low */ 5211 /* PSS_CTL0[DCDC_FORCE] Bits */ 5212 #define PSS_CTL0_DCDC_FORCE_OFS (10) /*!< DCDC_FORCE Bit Offset */ 5213 #define PSS_CTL0_DCDC_FORCE ((uint32_t)0x00000400) /*!< Force DC-DC regulator operation */ 5214 /* PSS_CTL0[VCORETRAN] Bits */ 5215 #define PSS_CTL0_VCORETRAN_OFS (12) /*!< VCORETRAN Bit Offset */ 5216 #define PSS_CTL0_VCORETRAN_MASK ((uint32_t)0x00003000) /*!< VCORETRAN Bit Mask */ 5217 #define PSS_CTL0_VCORETRAN0 ((uint32_t)0x00001000) /*!< VCORETRAN Bit 0 */ 5218 #define PSS_CTL0_VCORETRAN1 ((uint32_t)0x00002000) /*!< VCORETRAN Bit 1 */ 5219 #define PSS_CTL0_VCORETRAN_0 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ 5220 #define PSS_CTL0_VCORETRAN_1 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ 5221 #define PSS_CTL0_VCORETRAN_2 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ 5222 #define PSS_CTL0_VCORETRAN_3 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ 5223 #define PSS_CTL0_VCORETRAN__32 ((uint32_t)0x00000000) /*!< 32 s / 100 mV */ 5224 #define PSS_CTL0_VCORETRAN__64 ((uint32_t)0x00001000) /*!< 64 s / 100 mV */ 5225 #define PSS_CTL0_VCORETRAN__128 ((uint32_t)0x00002000) /*!< 128 s / 100 mV (default) */ 5226 #define PSS_CTL0_VCORETRAN__256 ((uint32_t)0x00003000) /*!< 256 s / 100 mV */ 5227 /* PSS_IE[SVSMHIE] Bits */ 5228 #define PSS_IE_SVSMHIE_OFS ( 1) /*!< SVSMHIE Bit Offset */ 5229 #define PSS_IE_SVSMHIE ((uint32_t)0x00000002) /*!< High-side SVSM interrupt enable */ 5230 /* PSS_IFG[SVSMHIFG] Bits */ 5231 #define PSS_IFG_SVSMHIFG_OFS ( 1) /*!< SVSMHIFG Bit Offset */ 5232 #define PSS_IFG_SVSMHIFG ((uint32_t)0x00000002) /*!< High-side SVSM interrupt flag */ 5233 /* PSS_CLRIFG[CLRSVSMHIFG] Bits */ 5234 #define PSS_CLRIFG_CLRSVSMHIFG_OFS ( 1) /*!< CLRSVSMHIFG Bit Offset */ 5235 #define PSS_CLRIFG_CLRSVSMHIFG ((uint32_t)0x00000002) /*!< SVSMH clear interrupt flag */ 5236 /* Pre-defined bitfield values */ 5237 #define PSS_KEY_KEY_VAL ((uint32_t)0x0000695A) /*!< PSS control key value */ 5238 5239 5240 /****************************************************************************** 5241 * REF_A Bits 5242 ******************************************************************************/ 5243 /* REF_A_CTL0[ON] Bits */ 5244 #define REF_A_CTL0_ON_OFS ( 0) /*!< REFON Bit Offset */ 5245 #define REF_A_CTL0_ON ((uint16_t)0x0001) /*!< Reference enable */ 5246 /* REF_A_CTL0[OUT] Bits */ 5247 #define REF_A_CTL0_OUT_OFS ( 1) /*!< REFOUT Bit Offset */ 5248 #define REF_A_CTL0_OUT ((uint16_t)0x0002) /*!< Reference output buffer */ 5249 /* REF_A_CTL0[TCOFF] Bits */ 5250 #define REF_A_CTL0_TCOFF_OFS ( 3) /*!< REFTCOFF Bit Offset */ 5251 #define REF_A_CTL0_TCOFF ((uint16_t)0x0008) /*!< Temperature sensor disabled */ 5252 /* REF_A_CTL0[VSEL] Bits */ 5253 #define REF_A_CTL0_VSEL_OFS ( 4) /*!< REFVSEL Bit Offset */ 5254 #define REF_A_CTL0_VSEL_MASK ((uint16_t)0x0030) /*!< REFVSEL Bit Mask */ 5255 #define REF_A_CTL0_VSEL0 ((uint16_t)0x0010) /*!< VSEL Bit 0 */ 5256 #define REF_A_CTL0_VSEL1 ((uint16_t)0x0020) /*!< VSEL Bit 1 */ 5257 #define REF_A_CTL0_VSEL_0 ((uint16_t)0x0000) /*!< 1.2 V available when reference requested or REFON = 1 */ 5258 #define REF_A_CTL0_VSEL_1 ((uint16_t)0x0010) /*!< 1.45 V available when reference requested or REFON = 1 */ 5259 #define REF_A_CTL0_VSEL_3 ((uint16_t)0x0030) /*!< 2.5 V available when reference requested or REFON = 1 */ 5260 /* REF_A_CTL0[GENOT] Bits */ 5261 #define REF_A_CTL0_GENOT_OFS ( 6) /*!< REFGENOT Bit Offset */ 5262 #define REF_A_CTL0_GENOT ((uint16_t)0x0040) /*!< Reference generator one-time trigger */ 5263 /* REF_A_CTL0[BGOT] Bits */ 5264 #define REF_A_CTL0_BGOT_OFS ( 7) /*!< REFBGOT Bit Offset */ 5265 #define REF_A_CTL0_BGOT ((uint16_t)0x0080) /*!< Bandgap and bandgap buffer one-time trigger */ 5266 /* REF_A_CTL0[GENACT] Bits */ 5267 #define REF_A_CTL0_GENACT_OFS ( 8) /*!< REFGENACT Bit Offset */ 5268 #define REF_A_CTL0_GENACT ((uint16_t)0x0100) /*!< Reference generator active */ 5269 /* REF_A_CTL0[BGACT] Bits */ 5270 #define REF_A_CTL0_BGACT_OFS ( 9) /*!< REFBGACT Bit Offset */ 5271 #define REF_A_CTL0_BGACT ((uint16_t)0x0200) /*!< Reference bandgap active */ 5272 /* REF_A_CTL0[GENBUSY] Bits */ 5273 #define REF_A_CTL0_GENBUSY_OFS (10) /*!< REFGENBUSY Bit Offset */ 5274 #define REF_A_CTL0_GENBUSY ((uint16_t)0x0400) /*!< Reference generator busy */ 5275 /* REF_A_CTL0[BGMODE] Bits */ 5276 #define REF_A_CTL0_BGMODE_OFS (11) /*!< BGMODE Bit Offset */ 5277 #define REF_A_CTL0_BGMODE ((uint16_t)0x0800) /*!< Bandgap mode */ 5278 /* REF_A_CTL0[GENRDY] Bits */ 5279 #define REF_A_CTL0_GENRDY_OFS (12) /*!< REFGENRDY Bit Offset */ 5280 #define REF_A_CTL0_GENRDY ((uint16_t)0x1000) /*!< Variable reference voltage ready status */ 5281 /* REF_A_CTL0[BGRDY] Bits */ 5282 #define REF_A_CTL0_BGRDY_OFS (13) /*!< REFBGRDY Bit Offset */ 5283 #define REF_A_CTL0_BGRDY ((uint16_t)0x2000) /*!< Buffered bandgap voltage ready status */ 5284 5285 /****************************************************************************** 5286 * RSTCTL Bits 5287 ******************************************************************************/ 5288 /* RSTCTL_RESET_REQ[SOFT_REQ] Bits */ 5289 #define RSTCTL_RESET_REQ_SOFT_REQ_OFS ( 0) /*!< SOFT_REQ Bit Offset */ 5290 #define RSTCTL_RESET_REQ_SOFT_REQ ((uint32_t)0x00000001) /*!< Soft Reset request */ 5291 /* RSTCTL_RESET_REQ[HARD_REQ] Bits */ 5292 #define RSTCTL_RESET_REQ_HARD_REQ_OFS ( 1) /*!< HARD_REQ Bit Offset */ 5293 #define RSTCTL_RESET_REQ_HARD_REQ ((uint32_t)0x00000002) /*!< Hard Reset request */ 5294 /* RSTCTL_RESET_REQ[RSTKEY] Bits */ 5295 #define RSTCTL_RESET_REQ_RSTKEY_OFS ( 8) /*!< RSTKEY Bit Offset */ 5296 #define RSTCTL_RESET_REQ_RSTKEY_MASK ((uint32_t)0x0000FF00) /*!< RSTKEY Bit Mask */ 5297 /* RSTCTL_HARDRESET_STAT[SRC0] Bits */ 5298 #define RSTCTL_HARDRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5299 #define RSTCTL_HARDRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< Indicates that SRC0 was the source of the Hard Reset */ 5300 /* RSTCTL_HARDRESET_STAT[SRC1] Bits */ 5301 #define RSTCTL_HARDRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5302 #define RSTCTL_HARDRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< Indicates that SRC1 was the source of the Hard Reset */ 5303 /* RSTCTL_HARDRESET_STAT[SRC2] Bits */ 5304 #define RSTCTL_HARDRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5305 #define RSTCTL_HARDRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< Indicates that SRC2 was the source of the Hard Reset */ 5306 /* RSTCTL_HARDRESET_STAT[SRC3] Bits */ 5307 #define RSTCTL_HARDRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5308 #define RSTCTL_HARDRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< Indicates that SRC3 was the source of the Hard Reset */ 5309 /* RSTCTL_HARDRESET_STAT[SRC4] Bits */ 5310 #define RSTCTL_HARDRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5311 #define RSTCTL_HARDRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< Indicates that SRC4 was the source of the Hard Reset */ 5312 /* RSTCTL_HARDRESET_STAT[SRC5] Bits */ 5313 #define RSTCTL_HARDRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5314 #define RSTCTL_HARDRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< Indicates that SRC5 was the source of the Hard Reset */ 5315 /* RSTCTL_HARDRESET_STAT[SRC6] Bits */ 5316 #define RSTCTL_HARDRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5317 #define RSTCTL_HARDRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< Indicates that SRC6 was the source of the Hard Reset */ 5318 /* RSTCTL_HARDRESET_STAT[SRC7] Bits */ 5319 #define RSTCTL_HARDRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5320 #define RSTCTL_HARDRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< Indicates that SRC7 was the source of the Hard Reset */ 5321 /* RSTCTL_HARDRESET_STAT[SRC8] Bits */ 5322 #define RSTCTL_HARDRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5323 #define RSTCTL_HARDRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< Indicates that SRC8 was the source of the Hard Reset */ 5324 /* RSTCTL_HARDRESET_STAT[SRC9] Bits */ 5325 #define RSTCTL_HARDRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5326 #define RSTCTL_HARDRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< Indicates that SRC9 was the source of the Hard Reset */ 5327 /* RSTCTL_HARDRESET_STAT[SRC10] Bits */ 5328 #define RSTCTL_HARDRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5329 #define RSTCTL_HARDRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< Indicates that SRC10 was the source of the Hard Reset */ 5330 /* RSTCTL_HARDRESET_STAT[SRC11] Bits */ 5331 #define RSTCTL_HARDRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5332 #define RSTCTL_HARDRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< Indicates that SRC11 was the source of the Hard Reset */ 5333 /* RSTCTL_HARDRESET_STAT[SRC12] Bits */ 5334 #define RSTCTL_HARDRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5335 #define RSTCTL_HARDRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< Indicates that SRC12 was the source of the Hard Reset */ 5336 /* RSTCTL_HARDRESET_STAT[SRC13] Bits */ 5337 #define RSTCTL_HARDRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5338 #define RSTCTL_HARDRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< Indicates that SRC13 was the source of the Hard Reset */ 5339 /* RSTCTL_HARDRESET_STAT[SRC14] Bits */ 5340 #define RSTCTL_HARDRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5341 #define RSTCTL_HARDRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< Indicates that SRC14 was the source of the Hard Reset */ 5342 /* RSTCTL_HARDRESET_STAT[SRC15] Bits */ 5343 #define RSTCTL_HARDRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5344 #define RSTCTL_HARDRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< Indicates that SRC15 was the source of the Hard Reset */ 5345 /* RSTCTL_HARDRESET_CLR[SRC0] Bits */ 5346 #define RSTCTL_HARDRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5347 #define RSTCTL_HARDRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5348 /* RSTCTL_HARDRESET_CLR[SRC1] Bits */ 5349 #define RSTCTL_HARDRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5350 #define RSTCTL_HARDRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5351 /* RSTCTL_HARDRESET_CLR[SRC2] Bits */ 5352 #define RSTCTL_HARDRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5353 #define RSTCTL_HARDRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5354 /* RSTCTL_HARDRESET_CLR[SRC3] Bits */ 5355 #define RSTCTL_HARDRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5356 #define RSTCTL_HARDRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5357 /* RSTCTL_HARDRESET_CLR[SRC4] Bits */ 5358 #define RSTCTL_HARDRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5359 #define RSTCTL_HARDRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5360 /* RSTCTL_HARDRESET_CLR[SRC5] Bits */ 5361 #define RSTCTL_HARDRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5362 #define RSTCTL_HARDRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5363 /* RSTCTL_HARDRESET_CLR[SRC6] Bits */ 5364 #define RSTCTL_HARDRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5365 #define RSTCTL_HARDRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5366 /* RSTCTL_HARDRESET_CLR[SRC7] Bits */ 5367 #define RSTCTL_HARDRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5368 #define RSTCTL_HARDRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5369 /* RSTCTL_HARDRESET_CLR[SRC8] Bits */ 5370 #define RSTCTL_HARDRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5371 #define RSTCTL_HARDRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5372 /* RSTCTL_HARDRESET_CLR[SRC9] Bits */ 5373 #define RSTCTL_HARDRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5374 #define RSTCTL_HARDRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5375 /* RSTCTL_HARDRESET_CLR[SRC10] Bits */ 5376 #define RSTCTL_HARDRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5377 #define RSTCTL_HARDRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5378 /* RSTCTL_HARDRESET_CLR[SRC11] Bits */ 5379 #define RSTCTL_HARDRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5380 #define RSTCTL_HARDRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5381 /* RSTCTL_HARDRESET_CLR[SRC12] Bits */ 5382 #define RSTCTL_HARDRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5383 #define RSTCTL_HARDRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5384 /* RSTCTL_HARDRESET_CLR[SRC13] Bits */ 5385 #define RSTCTL_HARDRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5386 #define RSTCTL_HARDRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5387 /* RSTCTL_HARDRESET_CLR[SRC14] Bits */ 5388 #define RSTCTL_HARDRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5389 #define RSTCTL_HARDRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HARDRESET_STAT */ 5390 /* RSTCTL_HARDRESET_CLR[SRC15] Bits */ 5391 #define RSTCTL_HARDRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5392 #define RSTCTL_HARDRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_HRDRESETSTAT_REG */ 5393 /* RSTCTL_HARDRESET_SET[SRC0] Bits */ 5394 #define RSTCTL_HARDRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5395 #define RSTCTL_HARDRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5396 /* initiates a Hard Reset) */ 5397 /* RSTCTL_HARDRESET_SET[SRC1] Bits */ 5398 #define RSTCTL_HARDRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5399 #define RSTCTL_HARDRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5400 /* initiates a Hard Reset) */ 5401 /* RSTCTL_HARDRESET_SET[SRC2] Bits */ 5402 #define RSTCTL_HARDRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5403 #define RSTCTL_HARDRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5404 /* initiates a Hard Reset) */ 5405 /* RSTCTL_HARDRESET_SET[SRC3] Bits */ 5406 #define RSTCTL_HARDRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5407 #define RSTCTL_HARDRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5408 /* initiates a Hard Reset) */ 5409 /* RSTCTL_HARDRESET_SET[SRC4] Bits */ 5410 #define RSTCTL_HARDRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5411 #define RSTCTL_HARDRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5412 /* initiates a Hard Reset) */ 5413 /* RSTCTL_HARDRESET_SET[SRC5] Bits */ 5414 #define RSTCTL_HARDRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5415 #define RSTCTL_HARDRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5416 /* initiates a Hard Reset) */ 5417 /* RSTCTL_HARDRESET_SET[SRC6] Bits */ 5418 #define RSTCTL_HARDRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5419 #define RSTCTL_HARDRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5420 /* initiates a Hard Reset) */ 5421 /* RSTCTL_HARDRESET_SET[SRC7] Bits */ 5422 #define RSTCTL_HARDRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5423 #define RSTCTL_HARDRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5424 /* initiates a Hard Reset) */ 5425 /* RSTCTL_HARDRESET_SET[SRC8] Bits */ 5426 #define RSTCTL_HARDRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5427 #define RSTCTL_HARDRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5428 /* initiates a Hard Reset) */ 5429 /* RSTCTL_HARDRESET_SET[SRC9] Bits */ 5430 #define RSTCTL_HARDRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5431 #define RSTCTL_HARDRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5432 /* initiates a Hard Reset) */ 5433 /* RSTCTL_HARDRESET_SET[SRC10] Bits */ 5434 #define RSTCTL_HARDRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5435 #define RSTCTL_HARDRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5436 /* initiates a Hard Reset) */ 5437 /* RSTCTL_HARDRESET_SET[SRC11] Bits */ 5438 #define RSTCTL_HARDRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5439 #define RSTCTL_HARDRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5440 /* initiates a Hard Reset) */ 5441 /* RSTCTL_HARDRESET_SET[SRC12] Bits */ 5442 #define RSTCTL_HARDRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5443 #define RSTCTL_HARDRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5444 /* initiates a Hard Reset) */ 5445 /* RSTCTL_HARDRESET_SET[SRC13] Bits */ 5446 #define RSTCTL_HARDRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5447 #define RSTCTL_HARDRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5448 /* initiates a Hard Reset) */ 5449 /* RSTCTL_HARDRESET_SET[SRC14] Bits */ 5450 #define RSTCTL_HARDRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5451 #define RSTCTL_HARDRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5452 /* initiates a Hard Reset) */ 5453 /* RSTCTL_HARDRESET_SET[SRC15] Bits */ 5454 #define RSTCTL_HARDRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5455 #define RSTCTL_HARDRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_HARDRESET_STAT (and */ 5456 /* initiates a Hard Reset) */ 5457 /* RSTCTL_SOFTRESET_STAT[SRC0] Bits */ 5458 #define RSTCTL_SOFTRESET_STAT_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5459 #define RSTCTL_SOFTRESET_STAT_SRC0 ((uint32_t)0x00000001) /*!< If 1, indicates that SRC0 was the source of the Soft Reset */ 5460 /* RSTCTL_SOFTRESET_STAT[SRC1] Bits */ 5461 #define RSTCTL_SOFTRESET_STAT_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5462 #define RSTCTL_SOFTRESET_STAT_SRC1 ((uint32_t)0x00000002) /*!< If 1, indicates that SRC1 was the source of the Soft Reset */ 5463 /* RSTCTL_SOFTRESET_STAT[SRC2] Bits */ 5464 #define RSTCTL_SOFTRESET_STAT_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5465 #define RSTCTL_SOFTRESET_STAT_SRC2 ((uint32_t)0x00000004) /*!< If 1, indicates that SRC2 was the source of the Soft Reset */ 5466 /* RSTCTL_SOFTRESET_STAT[SRC3] Bits */ 5467 #define RSTCTL_SOFTRESET_STAT_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5468 #define RSTCTL_SOFTRESET_STAT_SRC3 ((uint32_t)0x00000008) /*!< If 1, indicates that SRC3 was the source of the Soft Reset */ 5469 /* RSTCTL_SOFTRESET_STAT[SRC4] Bits */ 5470 #define RSTCTL_SOFTRESET_STAT_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5471 #define RSTCTL_SOFTRESET_STAT_SRC4 ((uint32_t)0x00000010) /*!< If 1, indicates that SRC4 was the source of the Soft Reset */ 5472 /* RSTCTL_SOFTRESET_STAT[SRC5] Bits */ 5473 #define RSTCTL_SOFTRESET_STAT_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5474 #define RSTCTL_SOFTRESET_STAT_SRC5 ((uint32_t)0x00000020) /*!< If 1, indicates that SRC5 was the source of the Soft Reset */ 5475 /* RSTCTL_SOFTRESET_STAT[SRC6] Bits */ 5476 #define RSTCTL_SOFTRESET_STAT_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5477 #define RSTCTL_SOFTRESET_STAT_SRC6 ((uint32_t)0x00000040) /*!< If 1, indicates that SRC6 was the source of the Soft Reset */ 5478 /* RSTCTL_SOFTRESET_STAT[SRC7] Bits */ 5479 #define RSTCTL_SOFTRESET_STAT_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5480 #define RSTCTL_SOFTRESET_STAT_SRC7 ((uint32_t)0x00000080) /*!< If 1, indicates that SRC7 was the source of the Soft Reset */ 5481 /* RSTCTL_SOFTRESET_STAT[SRC8] Bits */ 5482 #define RSTCTL_SOFTRESET_STAT_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5483 #define RSTCTL_SOFTRESET_STAT_SRC8 ((uint32_t)0x00000100) /*!< If 1, indicates that SRC8 was the source of the Soft Reset */ 5484 /* RSTCTL_SOFTRESET_STAT[SRC9] Bits */ 5485 #define RSTCTL_SOFTRESET_STAT_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5486 #define RSTCTL_SOFTRESET_STAT_SRC9 ((uint32_t)0x00000200) /*!< If 1, indicates that SRC9 was the source of the Soft Reset */ 5487 /* RSTCTL_SOFTRESET_STAT[SRC10] Bits */ 5488 #define RSTCTL_SOFTRESET_STAT_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5489 #define RSTCTL_SOFTRESET_STAT_SRC10 ((uint32_t)0x00000400) /*!< If 1, indicates that SRC10 was the source of the Soft Reset */ 5490 /* RSTCTL_SOFTRESET_STAT[SRC11] Bits */ 5491 #define RSTCTL_SOFTRESET_STAT_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5492 #define RSTCTL_SOFTRESET_STAT_SRC11 ((uint32_t)0x00000800) /*!< If 1, indicates that SRC11 was the source of the Soft Reset */ 5493 /* RSTCTL_SOFTRESET_STAT[SRC12] Bits */ 5494 #define RSTCTL_SOFTRESET_STAT_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5495 #define RSTCTL_SOFTRESET_STAT_SRC12 ((uint32_t)0x00001000) /*!< If 1, indicates that SRC12 was the source of the Soft Reset */ 5496 /* RSTCTL_SOFTRESET_STAT[SRC13] Bits */ 5497 #define RSTCTL_SOFTRESET_STAT_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5498 #define RSTCTL_SOFTRESET_STAT_SRC13 ((uint32_t)0x00002000) /*!< If 1, indicates that SRC13 was the source of the Soft Reset */ 5499 /* RSTCTL_SOFTRESET_STAT[SRC14] Bits */ 5500 #define RSTCTL_SOFTRESET_STAT_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5501 #define RSTCTL_SOFTRESET_STAT_SRC14 ((uint32_t)0x00004000) /*!< If 1, indicates that SRC14 was the source of the Soft Reset */ 5502 /* RSTCTL_SOFTRESET_STAT[SRC15] Bits */ 5503 #define RSTCTL_SOFTRESET_STAT_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5504 #define RSTCTL_SOFTRESET_STAT_SRC15 ((uint32_t)0x00008000) /*!< If 1, indicates that SRC15 was the source of the Soft Reset */ 5505 /* RSTCTL_SOFTRESET_CLR[SRC0] Bits */ 5506 #define RSTCTL_SOFTRESET_CLR_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5507 #define RSTCTL_SOFTRESET_CLR_SRC0 ((uint32_t)0x00000001) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5508 /* RSTCTL_SOFTRESET_CLR[SRC1] Bits */ 5509 #define RSTCTL_SOFTRESET_CLR_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5510 #define RSTCTL_SOFTRESET_CLR_SRC1 ((uint32_t)0x00000002) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5511 /* RSTCTL_SOFTRESET_CLR[SRC2] Bits */ 5512 #define RSTCTL_SOFTRESET_CLR_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5513 #define RSTCTL_SOFTRESET_CLR_SRC2 ((uint32_t)0x00000004) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5514 /* RSTCTL_SOFTRESET_CLR[SRC3] Bits */ 5515 #define RSTCTL_SOFTRESET_CLR_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5516 #define RSTCTL_SOFTRESET_CLR_SRC3 ((uint32_t)0x00000008) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5517 /* RSTCTL_SOFTRESET_CLR[SRC4] Bits */ 5518 #define RSTCTL_SOFTRESET_CLR_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5519 #define RSTCTL_SOFTRESET_CLR_SRC4 ((uint32_t)0x00000010) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5520 /* RSTCTL_SOFTRESET_CLR[SRC5] Bits */ 5521 #define RSTCTL_SOFTRESET_CLR_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5522 #define RSTCTL_SOFTRESET_CLR_SRC5 ((uint32_t)0x00000020) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5523 /* RSTCTL_SOFTRESET_CLR[SRC6] Bits */ 5524 #define RSTCTL_SOFTRESET_CLR_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5525 #define RSTCTL_SOFTRESET_CLR_SRC6 ((uint32_t)0x00000040) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5526 /* RSTCTL_SOFTRESET_CLR[SRC7] Bits */ 5527 #define RSTCTL_SOFTRESET_CLR_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5528 #define RSTCTL_SOFTRESET_CLR_SRC7 ((uint32_t)0x00000080) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5529 /* RSTCTL_SOFTRESET_CLR[SRC8] Bits */ 5530 #define RSTCTL_SOFTRESET_CLR_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5531 #define RSTCTL_SOFTRESET_CLR_SRC8 ((uint32_t)0x00000100) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5532 /* RSTCTL_SOFTRESET_CLR[SRC9] Bits */ 5533 #define RSTCTL_SOFTRESET_CLR_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5534 #define RSTCTL_SOFTRESET_CLR_SRC9 ((uint32_t)0x00000200) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5535 /* RSTCTL_SOFTRESET_CLR[SRC10] Bits */ 5536 #define RSTCTL_SOFTRESET_CLR_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5537 #define RSTCTL_SOFTRESET_CLR_SRC10 ((uint32_t)0x00000400) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5538 /* RSTCTL_SOFTRESET_CLR[SRC11] Bits */ 5539 #define RSTCTL_SOFTRESET_CLR_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5540 #define RSTCTL_SOFTRESET_CLR_SRC11 ((uint32_t)0x00000800) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5541 /* RSTCTL_SOFTRESET_CLR[SRC12] Bits */ 5542 #define RSTCTL_SOFTRESET_CLR_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5543 #define RSTCTL_SOFTRESET_CLR_SRC12 ((uint32_t)0x00001000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5544 /* RSTCTL_SOFTRESET_CLR[SRC13] Bits */ 5545 #define RSTCTL_SOFTRESET_CLR_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5546 #define RSTCTL_SOFTRESET_CLR_SRC13 ((uint32_t)0x00002000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5547 /* RSTCTL_SOFTRESET_CLR[SRC14] Bits */ 5548 #define RSTCTL_SOFTRESET_CLR_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5549 #define RSTCTL_SOFTRESET_CLR_SRC14 ((uint32_t)0x00004000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5550 /* RSTCTL_SOFTRESET_CLR[SRC15] Bits */ 5551 #define RSTCTL_SOFTRESET_CLR_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5552 #define RSTCTL_SOFTRESET_CLR_SRC15 ((uint32_t)0x00008000) /*!< Write 1 clears the corresponding bit in the RSTCTL_SOFTRESET_STAT */ 5553 /* RSTCTL_SOFTRESET_SET[SRC0] Bits */ 5554 #define RSTCTL_SOFTRESET_SET_SRC0_OFS ( 0) /*!< SRC0 Bit Offset */ 5555 #define RSTCTL_SOFTRESET_SET_SRC0 ((uint32_t)0x00000001) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5556 /* initiates a Soft Reset) */ 5557 /* RSTCTL_SOFTRESET_SET[SRC1] Bits */ 5558 #define RSTCTL_SOFTRESET_SET_SRC1_OFS ( 1) /*!< SRC1 Bit Offset */ 5559 #define RSTCTL_SOFTRESET_SET_SRC1 ((uint32_t)0x00000002) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5560 /* initiates a Soft Reset) */ 5561 /* RSTCTL_SOFTRESET_SET[SRC2] Bits */ 5562 #define RSTCTL_SOFTRESET_SET_SRC2_OFS ( 2) /*!< SRC2 Bit Offset */ 5563 #define RSTCTL_SOFTRESET_SET_SRC2 ((uint32_t)0x00000004) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5564 /* initiates a Soft Reset) */ 5565 /* RSTCTL_SOFTRESET_SET[SRC3] Bits */ 5566 #define RSTCTL_SOFTRESET_SET_SRC3_OFS ( 3) /*!< SRC3 Bit Offset */ 5567 #define RSTCTL_SOFTRESET_SET_SRC3 ((uint32_t)0x00000008) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5568 /* initiates a Soft Reset) */ 5569 /* RSTCTL_SOFTRESET_SET[SRC4] Bits */ 5570 #define RSTCTL_SOFTRESET_SET_SRC4_OFS ( 4) /*!< SRC4 Bit Offset */ 5571 #define RSTCTL_SOFTRESET_SET_SRC4 ((uint32_t)0x00000010) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5572 /* initiates a Soft Reset) */ 5573 /* RSTCTL_SOFTRESET_SET[SRC5] Bits */ 5574 #define RSTCTL_SOFTRESET_SET_SRC5_OFS ( 5) /*!< SRC5 Bit Offset */ 5575 #define RSTCTL_SOFTRESET_SET_SRC5 ((uint32_t)0x00000020) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5576 /* initiates a Soft Reset) */ 5577 /* RSTCTL_SOFTRESET_SET[SRC6] Bits */ 5578 #define RSTCTL_SOFTRESET_SET_SRC6_OFS ( 6) /*!< SRC6 Bit Offset */ 5579 #define RSTCTL_SOFTRESET_SET_SRC6 ((uint32_t)0x00000040) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5580 /* initiates a Soft Reset) */ 5581 /* RSTCTL_SOFTRESET_SET[SRC7] Bits */ 5582 #define RSTCTL_SOFTRESET_SET_SRC7_OFS ( 7) /*!< SRC7 Bit Offset */ 5583 #define RSTCTL_SOFTRESET_SET_SRC7 ((uint32_t)0x00000080) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5584 /* initiates a Soft Reset) */ 5585 /* RSTCTL_SOFTRESET_SET[SRC8] Bits */ 5586 #define RSTCTL_SOFTRESET_SET_SRC8_OFS ( 8) /*!< SRC8 Bit Offset */ 5587 #define RSTCTL_SOFTRESET_SET_SRC8 ((uint32_t)0x00000100) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5588 /* initiates a Soft Reset) */ 5589 /* RSTCTL_SOFTRESET_SET[SRC9] Bits */ 5590 #define RSTCTL_SOFTRESET_SET_SRC9_OFS ( 9) /*!< SRC9 Bit Offset */ 5591 #define RSTCTL_SOFTRESET_SET_SRC9 ((uint32_t)0x00000200) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5592 /* initiates a Soft Reset) */ 5593 /* RSTCTL_SOFTRESET_SET[SRC10] Bits */ 5594 #define RSTCTL_SOFTRESET_SET_SRC10_OFS (10) /*!< SRC10 Bit Offset */ 5595 #define RSTCTL_SOFTRESET_SET_SRC10 ((uint32_t)0x00000400) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5596 /* initiates a Soft Reset) */ 5597 /* RSTCTL_SOFTRESET_SET[SRC11] Bits */ 5598 #define RSTCTL_SOFTRESET_SET_SRC11_OFS (11) /*!< SRC11 Bit Offset */ 5599 #define RSTCTL_SOFTRESET_SET_SRC11 ((uint32_t)0x00000800) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5600 /* initiates a Soft Reset) */ 5601 /* RSTCTL_SOFTRESET_SET[SRC12] Bits */ 5602 #define RSTCTL_SOFTRESET_SET_SRC12_OFS (12) /*!< SRC12 Bit Offset */ 5603 #define RSTCTL_SOFTRESET_SET_SRC12 ((uint32_t)0x00001000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5604 /* initiates a Soft Reset) */ 5605 /* RSTCTL_SOFTRESET_SET[SRC13] Bits */ 5606 #define RSTCTL_SOFTRESET_SET_SRC13_OFS (13) /*!< SRC13 Bit Offset */ 5607 #define RSTCTL_SOFTRESET_SET_SRC13 ((uint32_t)0x00002000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5608 /* initiates a Soft Reset) */ 5609 /* RSTCTL_SOFTRESET_SET[SRC14] Bits */ 5610 #define RSTCTL_SOFTRESET_SET_SRC14_OFS (14) /*!< SRC14 Bit Offset */ 5611 #define RSTCTL_SOFTRESET_SET_SRC14 ((uint32_t)0x00004000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5612 /* initiates a Soft Reset) */ 5613 /* RSTCTL_SOFTRESET_SET[SRC15] Bits */ 5614 #define RSTCTL_SOFTRESET_SET_SRC15_OFS (15) /*!< SRC15 Bit Offset */ 5615 #define RSTCTL_SOFTRESET_SET_SRC15 ((uint32_t)0x00008000) /*!< Write 1 sets the corresponding bit in the RSTCTL_SOFTRESET_STAT (and */ 5616 /* initiates a Soft Reset) */ 5617 /* RSTCTL_PSSRESET_STAT[SVSMH] Bits */ 5618 #define RSTCTL_PSSRESET_STAT_SVSMH_OFS ( 1) /*!< SVSMH Bit Offset */ 5619 #define RSTCTL_PSSRESET_STAT_SVSMH ((uint32_t)0x00000002) /*!< Indicates if POR was caused by an SVSMH trip condition int the PSS */ 5620 /* RSTCTL_PSSRESET_STAT[BGREF] Bits */ 5621 #define RSTCTL_PSSRESET_STAT_BGREF_OFS ( 2) /*!< BGREF Bit Offset */ 5622 #define RSTCTL_PSSRESET_STAT_BGREF ((uint32_t)0x00000004) /*!< Indicates if POR was caused by a BGREF not okay condition in the PSS */ 5623 /* RSTCTL_PSSRESET_STAT[VCCDET] Bits */ 5624 #define RSTCTL_PSSRESET_STAT_VCCDET_OFS ( 3) /*!< VCCDET Bit Offset */ 5625 #define RSTCTL_PSSRESET_STAT_VCCDET ((uint32_t)0x00000008) /*!< Indicates if POR was caused by a VCCDET trip condition in the PSS */ 5626 /* RSTCTL_PSSRESET_CLR[CLR] Bits */ 5627 #define RSTCTL_PSSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5628 #define RSTCTL_PSSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PSS Reset Flags in the RSTCTL_PSSRESET_STAT */ 5629 /* RSTCTL_PCMRESET_STAT[LPM35] Bits */ 5630 #define RSTCTL_PCMRESET_STAT_LPM35_OFS ( 0) /*!< LPM35 Bit Offset */ 5631 #define RSTCTL_PCMRESET_STAT_LPM35 ((uint32_t)0x00000001) /*!< Indicates if POR was caused by PCM due to an exit from LPM3.5 */ 5632 /* RSTCTL_PCMRESET_STAT[LPM45] Bits */ 5633 #define RSTCTL_PCMRESET_STAT_LPM45_OFS ( 1) /*!< LPM45 Bit Offset */ 5634 #define RSTCTL_PCMRESET_STAT_LPM45 ((uint32_t)0x00000002) /*!< Indicates if POR was caused by PCM due to an exit from LPM4.5 */ 5635 /* RSTCTL_PCMRESET_CLR[CLR] Bits */ 5636 #define RSTCTL_PCMRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5637 #define RSTCTL_PCMRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears all PCM Reset Flags in the RSTCTL_PCMRESET_STAT */ 5638 /* RSTCTL_PINRESET_STAT[RSTNMI] Bits */ 5639 #define RSTCTL_PINRESET_STAT_RSTNMI_OFS ( 0) /*!< RSTNMI Bit Offset */ 5640 #define RSTCTL_PINRESET_STAT_RSTNMI ((uint32_t)0x00000001) /*!< POR was caused by RSTn/NMI pin based reset event */ 5641 /* RSTCTL_PINRESET_CLR[CLR] Bits */ 5642 #define RSTCTL_PINRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5643 #define RSTCTL_PINRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the RSTn/NMI Pin Reset Flag in RSTCTL_PINRESET_STAT */ 5644 /* RSTCTL_REBOOTRESET_STAT[REBOOT] Bits */ 5645 #define RSTCTL_REBOOTRESET_STAT_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ 5646 #define RSTCTL_REBOOTRESET_STAT_REBOOT ((uint32_t)0x00000001) /*!< Indicates if Reboot reset was caused by the SYSCTL module. */ 5647 /* RSTCTL_REBOOTRESET_CLR[CLR] Bits */ 5648 #define RSTCTL_REBOOTRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5649 #define RSTCTL_REBOOTRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the Reboot Reset Flag in RSTCTL_REBOOTRESET_STAT */ 5650 /* RSTCTL_CSRESET_STAT[DCOR_SHT] Bits */ 5651 #define RSTCTL_CSRESET_STAT_DCOR_SHT_OFS ( 0) /*!< DCOR_SHT Bit Offset */ 5652 #define RSTCTL_CSRESET_STAT_DCOR_SHT ((uint32_t)0x00000001) /*!< Indicates if POR was caused by DCO short circuit fault in the external */ 5653 /* resistor mode */ 5654 /* RSTCTL_CSRESET_CLR[CLR] Bits */ 5655 #define RSTCTL_CSRESET_CLR_CLR_OFS ( 0) /*!< CLR Bit Offset */ 5656 #define RSTCTL_CSRESET_CLR_CLR ((uint32_t)0x00000001) /*!< Write 1 clears the DCOR_SHT Flag in RSTCTL_CSRESET_STAT as well as */ 5657 /* DCOR_SHTIFG flag in CSIFG register of clock system */ 5658 /* Pre-defined bitfield values */ 5659 #define RSTCTL_RESETREQ_RSTKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bits 1-0 */ 5660 5661 5662 /****************************************************************************** 5663 * RTC_C Bits 5664 ******************************************************************************/ 5665 /* RTC_C_CTL0[RDYIFG] Bits */ 5666 #define RTC_C_CTL0_RDYIFG_OFS ( 0) /*!< RTCRDYIFG Bit Offset */ 5667 #define RTC_C_CTL0_RDYIFG ((uint16_t)0x0001) /*!< Real-time clock ready interrupt flag */ 5668 /* RTC_C_CTL0[AIFG] Bits */ 5669 #define RTC_C_CTL0_AIFG_OFS ( 1) /*!< RTCAIFG Bit Offset */ 5670 #define RTC_C_CTL0_AIFG ((uint16_t)0x0002) /*!< Real-time clock alarm interrupt flag */ 5671 /* RTC_C_CTL0[TEVIFG] Bits */ 5672 #define RTC_C_CTL0_TEVIFG_OFS ( 2) /*!< RTCTEVIFG Bit Offset */ 5673 #define RTC_C_CTL0_TEVIFG ((uint16_t)0x0004) /*!< Real-time clock time event interrupt flag */ 5674 /* RTC_C_CTL0[OFIFG] Bits */ 5675 #define RTC_C_CTL0_OFIFG_OFS ( 3) /*!< RTCOFIFG Bit Offset */ 5676 #define RTC_C_CTL0_OFIFG ((uint16_t)0x0008) /*!< 32-kHz crystal oscillator fault interrupt flag */ 5677 /* RTC_C_CTL0[RDYIE] Bits */ 5678 #define RTC_C_CTL0_RDYIE_OFS ( 4) /*!< RTCRDYIE Bit Offset */ 5679 #define RTC_C_CTL0_RDYIE ((uint16_t)0x0010) /*!< Real-time clock ready interrupt enable */ 5680 /* RTC_C_CTL0[AIE] Bits */ 5681 #define RTC_C_CTL0_AIE_OFS ( 5) /*!< RTCAIE Bit Offset */ 5682 #define RTC_C_CTL0_AIE ((uint16_t)0x0020) /*!< Real-time clock alarm interrupt enable */ 5683 /* RTC_C_CTL0[TEVIE] Bits */ 5684 #define RTC_C_CTL0_TEVIE_OFS ( 6) /*!< RTCTEVIE Bit Offset */ 5685 #define RTC_C_CTL0_TEVIE ((uint16_t)0x0040) /*!< Real-time clock time event interrupt enable */ 5686 /* RTC_C_CTL0[OFIE] Bits */ 5687 #define RTC_C_CTL0_OFIE_OFS ( 7) /*!< RTCOFIE Bit Offset */ 5688 #define RTC_C_CTL0_OFIE ((uint16_t)0x0080) /*!< 32-kHz crystal oscillator fault interrupt enable */ 5689 /* RTC_C_CTL0[KEY] Bits */ 5690 #define RTC_C_CTL0_KEY_OFS ( 8) /*!< RTCKEY Bit Offset */ 5691 #define RTC_C_CTL0_KEY_MASK ((uint16_t)0xFF00) /*!< RTCKEY Bit Mask */ 5692 /* RTC_C_CTL13[TEV] Bits */ 5693 #define RTC_C_CTL13_TEV_OFS ( 0) /*!< RTCTEV Bit Offset */ 5694 #define RTC_C_CTL13_TEV_MASK ((uint16_t)0x0003) /*!< RTCTEV Bit Mask */ 5695 #define RTC_C_CTL13_TEV0 ((uint16_t)0x0001) /*!< TEV Bit 0 */ 5696 #define RTC_C_CTL13_TEV1 ((uint16_t)0x0002) /*!< TEV Bit 1 */ 5697 #define RTC_C_CTL13_TEV_0 ((uint16_t)0x0000) /*!< Minute changed */ 5698 #define RTC_C_CTL13_TEV_1 ((uint16_t)0x0001) /*!< Hour changed */ 5699 #define RTC_C_CTL13_TEV_2 ((uint16_t)0x0002) /*!< Every day at midnight (00:00) */ 5700 #define RTC_C_CTL13_TEV_3 ((uint16_t)0x0003) /*!< Every day at noon (12:00) */ 5701 /* RTC_C_CTL13[SSEL] Bits */ 5702 #define RTC_C_CTL13_SSEL_OFS ( 2) /*!< RTCSSEL Bit Offset */ 5703 #define RTC_C_CTL13_SSEL_MASK ((uint16_t)0x000C) /*!< RTCSSEL Bit Mask */ 5704 #define RTC_C_CTL13_SSEL0 ((uint16_t)0x0004) /*!< SSEL Bit 0 */ 5705 #define RTC_C_CTL13_SSEL1 ((uint16_t)0x0008) /*!< SSEL Bit 1 */ 5706 #define RTC_C_CTL13_SSEL_0 ((uint16_t)0x0000) /*!< BCLK */ 5707 #define RTC_C_CTL13_SSEL__BCLK ((uint16_t)0x0000) /*!< BCLK */ 5708 /* RTC_C_CTL13[RDY] Bits */ 5709 #define RTC_C_CTL13_RDY_OFS ( 4) /*!< RTCRDY Bit Offset */ 5710 #define RTC_C_CTL13_RDY ((uint16_t)0x0010) /*!< Real-time clock ready */ 5711 /* RTC_C_CTL13[MODE] Bits */ 5712 #define RTC_C_CTL13_MODE_OFS ( 5) /*!< RTCMODE Bit Offset */ 5713 #define RTC_C_CTL13_MODE ((uint16_t)0x0020) 5714 /* RTC_C_CTL13[HOLD] Bits */ 5715 #define RTC_C_CTL13_HOLD_OFS ( 6) /*!< RTCHOLD Bit Offset */ 5716 #define RTC_C_CTL13_HOLD ((uint16_t)0x0040) /*!< Real-time clock hold */ 5717 /* RTC_C_CTL13[BCD] Bits */ 5718 #define RTC_C_CTL13_BCD_OFS ( 7) /*!< RTCBCD Bit Offset */ 5719 #define RTC_C_CTL13_BCD ((uint16_t)0x0080) /*!< Real-time clock BCD select */ 5720 /* RTC_C_CTL13[CALF] Bits */ 5721 #define RTC_C_CTL13_CALF_OFS ( 8) /*!< RTCCALF Bit Offset */ 5722 #define RTC_C_CTL13_CALF_MASK ((uint16_t)0x0300) /*!< RTCCALF Bit Mask */ 5723 #define RTC_C_CTL13_CALF0 ((uint16_t)0x0100) /*!< CALF Bit 0 */ 5724 #define RTC_C_CTL13_CALF1 ((uint16_t)0x0200) /*!< CALF Bit 1 */ 5725 #define RTC_C_CTL13_CALF_0 ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ 5726 #define RTC_C_CTL13_CALF_1 ((uint16_t)0x0100) /*!< 512 Hz */ 5727 #define RTC_C_CTL13_CALF_2 ((uint16_t)0x0200) /*!< 256 Hz */ 5728 #define RTC_C_CTL13_CALF_3 ((uint16_t)0x0300) /*!< 1 Hz */ 5729 #define RTC_C_CTL13_CALF__NONE ((uint16_t)0x0000) /*!< No frequency output to RTCCLK pin */ 5730 #define RTC_C_CTL13_CALF__512 ((uint16_t)0x0100) /*!< 512 Hz */ 5731 #define RTC_C_CTL13_CALF__256 ((uint16_t)0x0200) /*!< 256 Hz */ 5732 #define RTC_C_CTL13_CALF__1 ((uint16_t)0x0300) /*!< 1 Hz */ 5733 /* RTC_C_OCAL[OCAL] Bits */ 5734 #define RTC_C_OCAL_OCAL_OFS ( 0) /*!< RTCOCAL Bit Offset */ 5735 #define RTC_C_OCAL_OCAL_MASK ((uint16_t)0x00FF) /*!< RTCOCAL Bit Mask */ 5736 /* RTC_C_OCAL[OCALS] Bits */ 5737 #define RTC_C_OCAL_OCALS_OFS (15) /*!< RTCOCALS Bit Offset */ 5738 #define RTC_C_OCAL_OCALS ((uint16_t)0x8000) /*!< Real-time clock offset error calibration sign */ 5739 /* RTC_C_TCMP[TCMPx] Bits */ 5740 #define RTC_C_TCMP_TCMPX_OFS ( 0) /*!< RTCTCMP Bit Offset */ 5741 #define RTC_C_TCMP_TCMPX_MASK ((uint16_t)0x00FF) /*!< RTCTCMP Bit Mask */ 5742 /* RTC_C_TCMP[TCOK] Bits */ 5743 #define RTC_C_TCMP_TCOK_OFS (13) /*!< RTCTCOK Bit Offset */ 5744 #define RTC_C_TCMP_TCOK ((uint16_t)0x2000) /*!< Real-time clock temperature compensation write OK */ 5745 /* RTC_C_TCMP[TCRDY] Bits */ 5746 #define RTC_C_TCMP_TCRDY_OFS (14) /*!< RTCTCRDY Bit Offset */ 5747 #define RTC_C_TCMP_TCRDY ((uint16_t)0x4000) /*!< Real-time clock temperature compensation ready */ 5748 /* RTC_C_TCMP[TCMPS] Bits */ 5749 #define RTC_C_TCMP_TCMPS_OFS (15) /*!< RTCTCMPS Bit Offset */ 5750 #define RTC_C_TCMP_TCMPS ((uint16_t)0x8000) /*!< Real-time clock temperature compensation sign */ 5751 /* RTC_C_PS0CTL[RT0PSIFG] Bits */ 5752 #define RTC_C_PS0CTL_RT0PSIFG_OFS ( 0) /*!< RT0PSIFG Bit Offset */ 5753 #define RTC_C_PS0CTL_RT0PSIFG ((uint16_t)0x0001) /*!< Prescale timer 0 interrupt flag */ 5754 /* RTC_C_PS0CTL[RT0PSIE] Bits */ 5755 #define RTC_C_PS0CTL_RT0PSIE_OFS ( 1) /*!< RT0PSIE Bit Offset */ 5756 #define RTC_C_PS0CTL_RT0PSIE ((uint16_t)0x0002) /*!< Prescale timer 0 interrupt enable */ 5757 /* RTC_C_PS0CTL[RT0IP] Bits */ 5758 #define RTC_C_PS0CTL_RT0IP_OFS ( 2) /*!< RT0IP Bit Offset */ 5759 #define RTC_C_PS0CTL_RT0IP_MASK ((uint16_t)0x001C) /*!< RT0IP Bit Mask */ 5760 #define RTC_C_PS0CTL_RT0IP0 ((uint16_t)0x0004) /*!< RT0IP Bit 0 */ 5761 #define RTC_C_PS0CTL_RT0IP1 ((uint16_t)0x0008) /*!< RT0IP Bit 1 */ 5762 #define RTC_C_PS0CTL_RT0IP2 ((uint16_t)0x0010) /*!< RT0IP Bit 2 */ 5763 #define RTC_C_PS0CTL_RT0IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ 5764 #define RTC_C_PS0CTL_RT0IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ 5765 #define RTC_C_PS0CTL_RT0IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ 5766 #define RTC_C_PS0CTL_RT0IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ 5767 #define RTC_C_PS0CTL_RT0IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ 5768 #define RTC_C_PS0CTL_RT0IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ 5769 #define RTC_C_PS0CTL_RT0IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ 5770 #define RTC_C_PS0CTL_RT0IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ 5771 #define RTC_C_PS0CTL_RT0IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ 5772 #define RTC_C_PS0CTL_RT0IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ 5773 #define RTC_C_PS0CTL_RT0IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ 5774 #define RTC_C_PS0CTL_RT0IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ 5775 #define RTC_C_PS0CTL_RT0IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ 5776 #define RTC_C_PS0CTL_RT0IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ 5777 #define RTC_C_PS0CTL_RT0IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ 5778 #define RTC_C_PS0CTL_RT0IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ 5779 /* RTC_C_PS1CTL[RT1PSIFG] Bits */ 5780 #define RTC_C_PS1CTL_RT1PSIFG_OFS ( 0) /*!< RT1PSIFG Bit Offset */ 5781 #define RTC_C_PS1CTL_RT1PSIFG ((uint16_t)0x0001) /*!< Prescale timer 1 interrupt flag */ 5782 /* RTC_C_PS1CTL[RT1PSIE] Bits */ 5783 #define RTC_C_PS1CTL_RT1PSIE_OFS ( 1) /*!< RT1PSIE Bit Offset */ 5784 #define RTC_C_PS1CTL_RT1PSIE ((uint16_t)0x0002) /*!< Prescale timer 1 interrupt enable */ 5785 /* RTC_C_PS1CTL[RT1IP] Bits */ 5786 #define RTC_C_PS1CTL_RT1IP_OFS ( 2) /*!< RT1IP Bit Offset */ 5787 #define RTC_C_PS1CTL_RT1IP_MASK ((uint16_t)0x001C) /*!< RT1IP Bit Mask */ 5788 #define RTC_C_PS1CTL_RT1IP0 ((uint16_t)0x0004) /*!< RT1IP Bit 0 */ 5789 #define RTC_C_PS1CTL_RT1IP1 ((uint16_t)0x0008) /*!< RT1IP Bit 1 */ 5790 #define RTC_C_PS1CTL_RT1IP2 ((uint16_t)0x0010) /*!< RT1IP Bit 2 */ 5791 #define RTC_C_PS1CTL_RT1IP_0 ((uint16_t)0x0000) /*!< Divide by 2 */ 5792 #define RTC_C_PS1CTL_RT1IP_1 ((uint16_t)0x0004) /*!< Divide by 4 */ 5793 #define RTC_C_PS1CTL_RT1IP_2 ((uint16_t)0x0008) /*!< Divide by 8 */ 5794 #define RTC_C_PS1CTL_RT1IP_3 ((uint16_t)0x000C) /*!< Divide by 16 */ 5795 #define RTC_C_PS1CTL_RT1IP_4 ((uint16_t)0x0010) /*!< Divide by 32 */ 5796 #define RTC_C_PS1CTL_RT1IP_5 ((uint16_t)0x0014) /*!< Divide by 64 */ 5797 #define RTC_C_PS1CTL_RT1IP_6 ((uint16_t)0x0018) /*!< Divide by 128 */ 5798 #define RTC_C_PS1CTL_RT1IP_7 ((uint16_t)0x001C) /*!< Divide by 256 */ 5799 #define RTC_C_PS1CTL_RT1IP__2 ((uint16_t)0x0000) /*!< Divide by 2 */ 5800 #define RTC_C_PS1CTL_RT1IP__4 ((uint16_t)0x0004) /*!< Divide by 4 */ 5801 #define RTC_C_PS1CTL_RT1IP__8 ((uint16_t)0x0008) /*!< Divide by 8 */ 5802 #define RTC_C_PS1CTL_RT1IP__16 ((uint16_t)0x000C) /*!< Divide by 16 */ 5803 #define RTC_C_PS1CTL_RT1IP__32 ((uint16_t)0x0010) /*!< Divide by 32 */ 5804 #define RTC_C_PS1CTL_RT1IP__64 ((uint16_t)0x0014) /*!< Divide by 64 */ 5805 #define RTC_C_PS1CTL_RT1IP__128 ((uint16_t)0x0018) /*!< Divide by 128 */ 5806 #define RTC_C_PS1CTL_RT1IP__256 ((uint16_t)0x001C) /*!< Divide by 256 */ 5807 /* RTC_C_PS[RT0PS] Bits */ 5808 #define RTC_C_PS_RT0PS_OFS ( 0) /*!< RT0PS Bit Offset */ 5809 #define RTC_C_PS_RT0PS_MASK ((uint16_t)0x00FF) /*!< RT0PS Bit Mask */ 5810 /* RTC_C_PS[RT1PS] Bits */ 5811 #define RTC_C_PS_RT1PS_OFS ( 8) /*!< RT1PS Bit Offset */ 5812 #define RTC_C_PS_RT1PS_MASK ((uint16_t)0xFF00) /*!< RT1PS Bit Mask */ 5813 /* RTC_C_TIM0[SEC] Bits */ 5814 #define RTC_C_TIM0_SEC_OFS ( 0) /*!< Seconds Bit Offset */ 5815 #define RTC_C_TIM0_SEC_MASK ((uint16_t)0x003F) /*!< Seconds Bit Mask */ 5816 /* RTC_C_TIM0[MIN] Bits */ 5817 #define RTC_C_TIM0_MIN_OFS ( 8) /*!< Minutes Bit Offset */ 5818 #define RTC_C_TIM0_MIN_MASK ((uint16_t)0x3F00) /*!< Minutes Bit Mask */ 5819 /* RTC_C_TIM0[SEC_LD] Bits */ 5820 #define RTC_C_TIM0_SEC_LD_OFS ( 0) /*!< SecondsLowDigit Bit Offset */ 5821 #define RTC_C_TIM0_SEC_LD_MASK ((uint16_t)0x000F) /*!< SecondsLowDigit Bit Mask */ 5822 /* RTC_C_TIM0[SEC_HD] Bits */ 5823 #define RTC_C_TIM0_SEC_HD_OFS ( 4) /*!< SecondsHighDigit Bit Offset */ 5824 #define RTC_C_TIM0_SEC_HD_MASK ((uint16_t)0x0070) /*!< SecondsHighDigit Bit Mask */ 5825 /* RTC_C_TIM0[MIN_LD] Bits */ 5826 #define RTC_C_TIM0_MIN_LD_OFS ( 8) /*!< MinutesLowDigit Bit Offset */ 5827 #define RTC_C_TIM0_MIN_LD_MASK ((uint16_t)0x0F00) /*!< MinutesLowDigit Bit Mask */ 5828 /* RTC_C_TIM0[MIN_HD] Bits */ 5829 #define RTC_C_TIM0_MIN_HD_OFS (12) /*!< MinutesHighDigit Bit Offset */ 5830 #define RTC_C_TIM0_MIN_HD_MASK ((uint16_t)0x7000) /*!< MinutesHighDigit Bit Mask */ 5831 /* RTC_C_TIM1[HOUR] Bits */ 5832 #define RTC_C_TIM1_HOUR_OFS ( 0) /*!< Hours Bit Offset */ 5833 #define RTC_C_TIM1_HOUR_MASK ((uint16_t)0x001F) /*!< Hours Bit Mask */ 5834 /* RTC_C_TIM1[DOW] Bits */ 5835 #define RTC_C_TIM1_DOW_OFS ( 8) /*!< DayofWeek Bit Offset */ 5836 #define RTC_C_TIM1_DOW_MASK ((uint16_t)0x0700) /*!< DayofWeek Bit Mask */ 5837 /* RTC_C_TIM1[HOUR_LD] Bits */ 5838 #define RTC_C_TIM1_HOUR_LD_OFS ( 0) /*!< HoursLowDigit Bit Offset */ 5839 #define RTC_C_TIM1_HOUR_LD_MASK ((uint16_t)0x000F) /*!< HoursLowDigit Bit Mask */ 5840 /* RTC_C_TIM1[HOUR_HD] Bits */ 5841 #define RTC_C_TIM1_HOUR_HD_OFS ( 4) /*!< HoursHighDigit Bit Offset */ 5842 #define RTC_C_TIM1_HOUR_HD_MASK ((uint16_t)0x0030) /*!< HoursHighDigit Bit Mask */ 5843 /* RTC_C_DATE[DAY] Bits */ 5844 #define RTC_C_DATE_DAY_OFS ( 0) /*!< Day Bit Offset */ 5845 #define RTC_C_DATE_DAY_MASK ((uint16_t)0x001F) /*!< Day Bit Mask */ 5846 /* RTC_C_DATE[MON] Bits */ 5847 #define RTC_C_DATE_MON_OFS ( 8) /*!< Month Bit Offset */ 5848 #define RTC_C_DATE_MON_MASK ((uint16_t)0x0F00) /*!< Month Bit Mask */ 5849 /* RTC_C_DATE[DAY_LD] Bits */ 5850 #define RTC_C_DATE_DAY_LD_OFS ( 0) /*!< DayLowDigit Bit Offset */ 5851 #define RTC_C_DATE_DAY_LD_MASK ((uint16_t)0x000F) /*!< DayLowDigit Bit Mask */ 5852 /* RTC_C_DATE[DAY_HD] Bits */ 5853 #define RTC_C_DATE_DAY_HD_OFS ( 4) /*!< DayHighDigit Bit Offset */ 5854 #define RTC_C_DATE_DAY_HD_MASK ((uint16_t)0x0030) /*!< DayHighDigit Bit Mask */ 5855 /* RTC_C_DATE[MON_LD] Bits */ 5856 #define RTC_C_DATE_MON_LD_OFS ( 8) /*!< MonthLowDigit Bit Offset */ 5857 #define RTC_C_DATE_MON_LD_MASK ((uint16_t)0x0F00) /*!< MonthLowDigit Bit Mask */ 5858 /* RTC_C_DATE[MON_HD] Bits */ 5859 #define RTC_C_DATE_MON_HD_OFS (12) /*!< MonthHighDigit Bit Offset */ 5860 #define RTC_C_DATE_MON_HD ((uint16_t)0x1000) /*!< Month high digit (0 or 1) */ 5861 /* RTC_C_YEAR[YEAR_LB] Bits */ 5862 #define RTC_C_YEAR_YEAR_LB_OFS ( 0) /*!< YearLowByte Bit Offset */ 5863 #define RTC_C_YEAR_YEAR_LB_MASK ((uint16_t)0x00FF) /*!< YearLowByte Bit Mask */ 5864 /* RTC_C_YEAR[YEAR_HB] Bits */ 5865 #define RTC_C_YEAR_YEAR_HB_OFS ( 8) /*!< YearHighByte Bit Offset */ 5866 #define RTC_C_YEAR_YEAR_HB_MASK ((uint16_t)0x0F00) /*!< YearHighByte Bit Mask */ 5867 /* RTC_C_YEAR[YEAR] Bits */ 5868 #define RTC_C_YEAR_YEAR_OFS ( 0) /*!< Year Bit Offset */ 5869 #define RTC_C_YEAR_YEAR_MASK ((uint16_t)0x000F) /*!< Year Bit Mask */ 5870 /* RTC_C_YEAR[DEC] Bits */ 5871 #define RTC_C_YEAR_DEC_OFS ( 4) /*!< Decade Bit Offset */ 5872 #define RTC_C_YEAR_DEC_MASK ((uint16_t)0x00F0) /*!< Decade Bit Mask */ 5873 /* RTC_C_YEAR[CENT_LD] Bits */ 5874 #define RTC_C_YEAR_CENT_LD_OFS ( 8) /*!< CenturyLowDigit Bit Offset */ 5875 #define RTC_C_YEAR_CENT_LD_MASK ((uint16_t)0x0F00) /*!< CenturyLowDigit Bit Mask */ 5876 /* RTC_C_YEAR[CENT_HD] Bits */ 5877 #define RTC_C_YEAR_CENT_HD_OFS (12) /*!< CenturyHighDigit Bit Offset */ 5878 #define RTC_C_YEAR_CENT_HD_MASK ((uint16_t)0x7000) /*!< CenturyHighDigit Bit Mask */ 5879 /* RTC_C_AMINHR[MIN] Bits */ 5880 #define RTC_C_AMINHR_MIN_OFS ( 0) /*!< Minutes Bit Offset */ 5881 #define RTC_C_AMINHR_MIN_MASK ((uint16_t)0x003F) /*!< Minutes Bit Mask */ 5882 /* RTC_C_AMINHR[MINAE] Bits */ 5883 #define RTC_C_AMINHR_MINAE_OFS ( 7) /*!< MINAE Bit Offset */ 5884 #define RTC_C_AMINHR_MINAE ((uint16_t)0x0080) /*!< Alarm enable */ 5885 /* RTC_C_AMINHR[HOUR] Bits */ 5886 #define RTC_C_AMINHR_HOUR_OFS ( 8) /*!< Hours Bit Offset */ 5887 #define RTC_C_AMINHR_HOUR_MASK ((uint16_t)0x1F00) /*!< Hours Bit Mask */ 5888 /* RTC_C_AMINHR[HOURAE] Bits */ 5889 #define RTC_C_AMINHR_HOURAE_OFS (15) /*!< HOURAE Bit Offset */ 5890 #define RTC_C_AMINHR_HOURAE ((uint16_t)0x8000) /*!< Alarm enable */ 5891 /* RTC_C_AMINHR[MIN_LD] Bits */ 5892 #define RTC_C_AMINHR_MIN_LD_OFS ( 0) /*!< MinutesLowDigit Bit Offset */ 5893 #define RTC_C_AMINHR_MIN_LD_MASK ((uint16_t)0x000F) /*!< MinutesLowDigit Bit Mask */ 5894 /* RTC_C_AMINHR[MIN_HD] Bits */ 5895 #define RTC_C_AMINHR_MIN_HD_OFS ( 4) /*!< MinutesHighDigit Bit Offset */ 5896 #define RTC_C_AMINHR_MIN_HD_MASK ((uint16_t)0x0070) /*!< MinutesHighDigit Bit Mask */ 5897 /* RTC_C_AMINHR[HOUR_LD] Bits */ 5898 #define RTC_C_AMINHR_HOUR_LD_OFS ( 8) /*!< HoursLowDigit Bit Offset */ 5899 #define RTC_C_AMINHR_HOUR_LD_MASK ((uint16_t)0x0F00) /*!< HoursLowDigit Bit Mask */ 5900 /* RTC_C_AMINHR[HOUR_HD] Bits */ 5901 #define RTC_C_AMINHR_HOUR_HD_OFS (12) /*!< HoursHighDigit Bit Offset */ 5902 #define RTC_C_AMINHR_HOUR_HD_MASK ((uint16_t)0x3000) /*!< HoursHighDigit Bit Mask */ 5903 /* RTC_C_ADOWDAY[DOW] Bits */ 5904 #define RTC_C_ADOWDAY_DOW_OFS ( 0) /*!< DayofWeek Bit Offset */ 5905 #define RTC_C_ADOWDAY_DOW_MASK ((uint16_t)0x0007) /*!< DayofWeek Bit Mask */ 5906 /* RTC_C_ADOWDAY[DOWAE] Bits */ 5907 #define RTC_C_ADOWDAY_DOWAE_OFS ( 7) /*!< DOWAE Bit Offset */ 5908 #define RTC_C_ADOWDAY_DOWAE ((uint16_t)0x0080) /*!< Alarm enable */ 5909 /* RTC_C_ADOWDAY[DAY] Bits */ 5910 #define RTC_C_ADOWDAY_DAY_OFS ( 8) /*!< DayofMonth Bit Offset */ 5911 #define RTC_C_ADOWDAY_DAY_MASK ((uint16_t)0x1F00) /*!< DayofMonth Bit Mask */ 5912 /* RTC_C_ADOWDAY[DAYAE] Bits */ 5913 #define RTC_C_ADOWDAY_DAYAE_OFS (15) /*!< DAYAE Bit Offset */ 5914 #define RTC_C_ADOWDAY_DAYAE ((uint16_t)0x8000) /*!< Alarm enable */ 5915 /* RTC_C_ADOWDAY[DAY_LD] Bits */ 5916 #define RTC_C_ADOWDAY_DAY_LD_OFS ( 8) /*!< DayLowDigit Bit Offset */ 5917 #define RTC_C_ADOWDAY_DAY_LD_MASK ((uint16_t)0x0F00) /*!< DayLowDigit Bit Mask */ 5918 /* RTC_C_ADOWDAY[DAY_HD] Bits */ 5919 #define RTC_C_ADOWDAY_DAY_HD_OFS (12) /*!< DayHighDigit Bit Offset */ 5920 #define RTC_C_ADOWDAY_DAY_HD_MASK ((uint16_t)0x3000) /*!< DayHighDigit Bit Mask */ 5921 /* Pre-defined bitfield values */ 5922 #define RTC_C_KEY ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ 5923 #define RTC_C_KEY_H ((uint16_t)0x00A5) /*!< RTC_C Key Value for RTC_C write access */ 5924 #define RTC_C_KEY_VAL ((uint16_t)0xA500) /*!< RTC_C Key Value for RTC_C write access */ 5925 5926 5927 /****************************************************************************** 5928 * SCB Bits 5929 ******************************************************************************/ 5930 /* SCB_PFR0[STATE0] Bits */ 5931 #define SCB_PFR0_STATE0_OFS ( 0) /*!< STATE0 Bit Offset */ 5932 #define SCB_PFR0_STATE0_MASK ((uint32_t)0x0000000F) /*!< STATE0 Bit Mask */ 5933 #define SCB_PFR0_STATE00 ((uint32_t)0x00000001) /*!< STATE0 Bit 0 */ 5934 #define SCB_PFR0_STATE01 ((uint32_t)0x00000002) /*!< STATE0 Bit 1 */ 5935 #define SCB_PFR0_STATE02 ((uint32_t)0x00000004) /*!< STATE0 Bit 2 */ 5936 #define SCB_PFR0_STATE03 ((uint32_t)0x00000008) /*!< STATE0 Bit 3 */ 5937 #define SCB_PFR0_STATE0_0 ((uint32_t)0x00000000) /*!< no ARM encoding */ 5938 #define SCB_PFR0_STATE0_1 ((uint32_t)0x00000001) /*!< N/A */ 5939 /* SCB_PFR0[STATE1] Bits */ 5940 #define SCB_PFR0_STATE1_OFS ( 4) /*!< STATE1 Bit Offset */ 5941 #define SCB_PFR0_STATE1_MASK ((uint32_t)0x000000F0) /*!< STATE1 Bit Mask */ 5942 #define SCB_PFR0_STATE10 ((uint32_t)0x00000010) /*!< STATE1 Bit 0 */ 5943 #define SCB_PFR0_STATE11 ((uint32_t)0x00000020) /*!< STATE1 Bit 1 */ 5944 #define SCB_PFR0_STATE12 ((uint32_t)0x00000040) /*!< STATE1 Bit 2 */ 5945 #define SCB_PFR0_STATE13 ((uint32_t)0x00000080) /*!< STATE1 Bit 3 */ 5946 #define SCB_PFR0_STATE1_0 ((uint32_t)0x00000000) /*!< N/A */ 5947 #define SCB_PFR0_STATE1_1 ((uint32_t)0x00000010) /*!< N/A */ 5948 #define SCB_PFR0_STATE1_2 ((uint32_t)0x00000020) /*!< Thumb-2 encoding with the 16-bit basic instructions plus 32-bit Buncond/BL */ 5949 /* but no other 32-bit basic instructions (Note non-basic 32-bit instructions */ 5950 /* can be added using the appropriate instruction attribute, but other 32-bit */ 5951 /* basic instructions cannot.) */ 5952 #define SCB_PFR0_STATE1_3 ((uint32_t)0x00000030) /*!< Thumb-2 encoding with all Thumb-2 basic instructions */ 5953 /* SCB_PFR1[MICROCONTROLLER_PROGRAMMERS_MODEL] Bits */ 5954 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_OFS ( 8) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Offset */ 5955 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_MASK ((uint32_t)0x00000F00) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit Mask */ 5956 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL0 ((uint32_t)0x00000100) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 0 */ 5957 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL1 ((uint32_t)0x00000200) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 1 */ 5958 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL2 ((uint32_t)0x00000400) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 2 */ 5959 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL3 ((uint32_t)0x00000800) /*!< MICROCONTROLLER_PROGRAMMERS_MODEL Bit 3 */ 5960 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ 5961 #define SCB_PFR1_MICROCONTROLLER_PROGRAMMERS_MODEL_2 ((uint32_t)0x00000200) /*!< two-stack support */ 5962 /* SCB_DFR0[MICROCONTROLLER_DEBUG_MODEL] Bits */ 5963 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_OFS (20) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Offset */ 5964 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_MASK ((uint32_t)0x00F00000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit Mask */ 5965 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL0 ((uint32_t)0x00100000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 0 */ 5966 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL1 ((uint32_t)0x00200000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 1 */ 5967 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL2 ((uint32_t)0x00400000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 2 */ 5968 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL3 ((uint32_t)0x00800000) /*!< MICROCONTROLLER_DEBUG_MODEL Bit 3 */ 5969 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_0 ((uint32_t)0x00000000) /*!< not supported */ 5970 #define SCB_DFR0_MICROCONTROLLER_DEBUG_MODEL_1 ((uint32_t)0x00100000) /*!< Microcontroller debug v1 (ITMv1, DWTv1, optional ETM) */ 5971 /* SCB_MMFR0[PMSA_SUPPORT] Bits */ 5972 #define SCB_MMFR0_PMSA_SUPPORT_OFS ( 4) /*!< PMSA_SUPPORT Bit Offset */ 5973 #define SCB_MMFR0_PMSA_SUPPORT_MASK ((uint32_t)0x000000F0) /*!< PMSA_SUPPORT Bit Mask */ 5974 #define SCB_MMFR0_PMSA_SUPPORT0 ((uint32_t)0x00000010) /*!< PMSA_SUPPORT Bit 0 */ 5975 #define SCB_MMFR0_PMSA_SUPPORT1 ((uint32_t)0x00000020) /*!< PMSA_SUPPORT Bit 1 */ 5976 #define SCB_MMFR0_PMSA_SUPPORT2 ((uint32_t)0x00000040) /*!< PMSA_SUPPORT Bit 2 */ 5977 #define SCB_MMFR0_PMSA_SUPPORT3 ((uint32_t)0x00000080) /*!< PMSA_SUPPORT Bit 3 */ 5978 #define SCB_MMFR0_PMSA_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ 5979 #define SCB_MMFR0_PMSA_SUPPORT_1 ((uint32_t)0x00000010) /*!< IMPLEMENTATION DEFINED (N/A) */ 5980 #define SCB_MMFR0_PMSA_SUPPORT_2 ((uint32_t)0x00000020) /*!< PMSA base (features as defined for ARMv6) (N/A) */ 5981 #define SCB_MMFR0_PMSA_SUPPORT_3 ((uint32_t)0x00000030) /*!< PMSAv7 (base plus subregion support) */ 5982 /* SCB_MMFR0[CACHE_COHERENCE_SUPPORT] Bits */ 5983 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_OFS ( 8) /*!< CACHE_COHERENCE_SUPPORT Bit Offset */ 5984 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_MASK ((uint32_t)0x00000F00) /*!< CACHE_COHERENCE_SUPPORT Bit Mask */ 5985 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT0 ((uint32_t)0x00000100) /*!< CACHE_COHERENCE_SUPPORT Bit 0 */ 5986 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT1 ((uint32_t)0x00000200) /*!< CACHE_COHERENCE_SUPPORT Bit 1 */ 5987 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT2 ((uint32_t)0x00000400) /*!< CACHE_COHERENCE_SUPPORT Bit 2 */ 5988 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT3 ((uint32_t)0x00000800) /*!< CACHE_COHERENCE_SUPPORT Bit 3 */ 5989 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_0 ((uint32_t)0x00000000) /*!< no shared support */ 5990 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_1 ((uint32_t)0x00000100) /*!< partial-inner-shared coherency (coherency amongst some - but not all - of */ 5991 /* the entities within an inner-coherent domain) */ 5992 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_2 ((uint32_t)0x00000200) /*!< full-inner-shared coherency (coherency amongst all of the entities within an */ 5993 /* inner-coherent domain) */ 5994 #define SCB_MMFR0_CACHE_COHERENCE_SUPPORT_3 ((uint32_t)0x00000300) /*!< full coherency (coherency amongst all of the entities) */ 5995 /* SCB_MMFR0[OUTER_NON_SHARABLE_SUPPORT] Bits */ 5996 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_OFS (12) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Offset */ 5997 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_MASK ((uint32_t)0x0000F000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit Mask */ 5998 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT0 ((uint32_t)0x00001000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 0 */ 5999 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT1 ((uint32_t)0x00002000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 1 */ 6000 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT2 ((uint32_t)0x00004000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 2 */ 6001 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT3 ((uint32_t)0x00008000) /*!< OUTER_NON_SHARABLE_SUPPORT Bit 3 */ 6002 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_0 ((uint32_t)0x00000000) /*!< Outer non-sharable not supported */ 6003 #define SCB_MMFR0_OUTER_NON_SHARABLE_SUPPORT_1 ((uint32_t)0x00001000) /*!< Outer sharable supported */ 6004 /* SCB_MMFR0[AUILIARY_REGISTER_SUPPORT] Bits */ 6005 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_OFS (20) /*!< AUXILIARY_REGISTER_SUPPORT Bit Offset */ 6006 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_MASK ((uint32_t)0x00F00000) /*!< AUXILIARY_REGISTER_SUPPORT Bit Mask */ 6007 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT0 ((uint32_t)0x00100000) /*!< AUILIARY_REGISTER_SUPPORT Bit 0 */ 6008 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT1 ((uint32_t)0x00200000) /*!< AUILIARY_REGISTER_SUPPORT Bit 1 */ 6009 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT2 ((uint32_t)0x00400000) /*!< AUILIARY_REGISTER_SUPPORT Bit 2 */ 6010 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT3 ((uint32_t)0x00800000) /*!< AUILIARY_REGISTER_SUPPORT Bit 3 */ 6011 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_0 ((uint32_t)0x00000000) /*!< not supported */ 6012 #define SCB_MMFR0_AUILIARY_REGISTER_SUPPORT_1 ((uint32_t)0x00100000) /*!< Auxiliary control register */ 6013 /* SCB_MMFR2[WAIT_FOR_INTERRUPT_STALLING] Bits */ 6014 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_OFS (24) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Offset */ 6015 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_MASK ((uint32_t)0x0F000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit Mask */ 6016 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING0 ((uint32_t)0x01000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 0 */ 6017 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING1 ((uint32_t)0x02000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 1 */ 6018 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING2 ((uint32_t)0x04000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 2 */ 6019 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING3 ((uint32_t)0x08000000) /*!< WAIT_FOR_INTERRUPT_STALLING Bit 3 */ 6020 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_0 ((uint32_t)0x00000000) /*!< not supported */ 6021 #define SCB_MMFR2_WAIT_FOR_INTERRUPT_STALLING_1 ((uint32_t)0x01000000) /*!< wait for interrupt supported */ 6022 /* SCB_ISAR0[BITCOUNT_INSTRS] Bits */ 6023 #define SCB_ISAR0_BITCOUNT_INSTRS_OFS ( 4) /*!< BITCOUNT_INSTRS Bit Offset */ 6024 #define SCB_ISAR0_BITCOUNT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< BITCOUNT_INSTRS Bit Mask */ 6025 #define SCB_ISAR0_BITCOUNT_INSTRS0 ((uint32_t)0x00000010) /*!< BITCOUNT_INSTRS Bit 0 */ 6026 #define SCB_ISAR0_BITCOUNT_INSTRS1 ((uint32_t)0x00000020) /*!< BITCOUNT_INSTRS Bit 1 */ 6027 #define SCB_ISAR0_BITCOUNT_INSTRS2 ((uint32_t)0x00000040) /*!< BITCOUNT_INSTRS Bit 2 */ 6028 #define SCB_ISAR0_BITCOUNT_INSTRS3 ((uint32_t)0x00000080) /*!< BITCOUNT_INSTRS Bit 3 */ 6029 #define SCB_ISAR0_BITCOUNT_INSTRS_0 ((uint32_t)0x00000000) /*!< no bit-counting instructions present */ 6030 #define SCB_ISAR0_BITCOUNT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds CLZ */ 6031 /* SCB_ISAR0[BITFIELD_INSTRS] Bits */ 6032 #define SCB_ISAR0_BITFIELD_INSTRS_OFS ( 8) /*!< BITFIELD_INSTRS Bit Offset */ 6033 #define SCB_ISAR0_BITFIELD_INSTRS_MASK ((uint32_t)0x00000F00) /*!< BITFIELD_INSTRS Bit Mask */ 6034 #define SCB_ISAR0_BITFIELD_INSTRS0 ((uint32_t)0x00000100) /*!< BITFIELD_INSTRS Bit 0 */ 6035 #define SCB_ISAR0_BITFIELD_INSTRS1 ((uint32_t)0x00000200) /*!< BITFIELD_INSTRS Bit 1 */ 6036 #define SCB_ISAR0_BITFIELD_INSTRS2 ((uint32_t)0x00000400) /*!< BITFIELD_INSTRS Bit 2 */ 6037 #define SCB_ISAR0_BITFIELD_INSTRS3 ((uint32_t)0x00000800) /*!< BITFIELD_INSTRS Bit 3 */ 6038 #define SCB_ISAR0_BITFIELD_INSTRS_0 ((uint32_t)0x00000000) /*!< no bitfield instructions present */ 6039 #define SCB_ISAR0_BITFIELD_INSTRS_1 ((uint32_t)0x00000100) /*!< adds BFC, BFI, SBFX, UBFX */ 6040 /* SCB_ISAR0[CMPBRANCH_INSTRS] Bits */ 6041 #define SCB_ISAR0_CMPBRANCH_INSTRS_OFS (12) /*!< CMPBRANCH_INSTRS Bit Offset */ 6042 #define SCB_ISAR0_CMPBRANCH_INSTRS_MASK ((uint32_t)0x0000F000) /*!< CMPBRANCH_INSTRS Bit Mask */ 6043 #define SCB_ISAR0_CMPBRANCH_INSTRS0 ((uint32_t)0x00001000) /*!< CMPBRANCH_INSTRS Bit 0 */ 6044 #define SCB_ISAR0_CMPBRANCH_INSTRS1 ((uint32_t)0x00002000) /*!< CMPBRANCH_INSTRS Bit 1 */ 6045 #define SCB_ISAR0_CMPBRANCH_INSTRS2 ((uint32_t)0x00004000) /*!< CMPBRANCH_INSTRS Bit 2 */ 6046 #define SCB_ISAR0_CMPBRANCH_INSTRS3 ((uint32_t)0x00008000) /*!< CMPBRANCH_INSTRS Bit 3 */ 6047 #define SCB_ISAR0_CMPBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no combined compare-and-branch instructions present */ 6048 #define SCB_ISAR0_CMPBRANCH_INSTRS_1 ((uint32_t)0x00001000) /*!< adds CB{N}Z */ 6049 /* SCB_ISAR0[COPROC_INSTRS] Bits */ 6050 #define SCB_ISAR0_COPROC_INSTRS_OFS (16) /*!< COPROC_INSTRS Bit Offset */ 6051 #define SCB_ISAR0_COPROC_INSTRS_MASK ((uint32_t)0x000F0000) /*!< COPROC_INSTRS Bit Mask */ 6052 #define SCB_ISAR0_COPROC_INSTRS0 ((uint32_t)0x00010000) /*!< COPROC_INSTRS Bit 0 */ 6053 #define SCB_ISAR0_COPROC_INSTRS1 ((uint32_t)0x00020000) /*!< COPROC_INSTRS Bit 1 */ 6054 #define SCB_ISAR0_COPROC_INSTRS2 ((uint32_t)0x00040000) /*!< COPROC_INSTRS Bit 2 */ 6055 #define SCB_ISAR0_COPROC_INSTRS3 ((uint32_t)0x00080000) /*!< COPROC_INSTRS Bit 3 */ 6056 #define SCB_ISAR0_COPROC_INSTRS_0 ((uint32_t)0x00000000) /*!< no coprocessor support, other than for separately attributed architectures */ 6057 /* such as CP15 or VFP */ 6058 #define SCB_ISAR0_COPROC_INSTRS_1 ((uint32_t)0x00010000) /*!< adds generic CDP, LDC, MCR, MRC, STC */ 6059 #define SCB_ISAR0_COPROC_INSTRS_2 ((uint32_t)0x00020000) /*!< adds generic CDP2, LDC2, MCR2, MRC2, STC2 */ 6060 #define SCB_ISAR0_COPROC_INSTRS_3 ((uint32_t)0x00030000) /*!< adds generic MCRR, MRRC */ 6061 #define SCB_ISAR0_COPROC_INSTRS_4 ((uint32_t)0x00040000) /*!< adds generic MCRR2, MRRC2 */ 6062 /* SCB_ISAR0[DEBUG_INSTRS] Bits */ 6063 #define SCB_ISAR0_DEBUG_INSTRS_OFS (20) /*!< DEBUG_INSTRS Bit Offset */ 6064 #define SCB_ISAR0_DEBUG_INSTRS_MASK ((uint32_t)0x00F00000) /*!< DEBUG_INSTRS Bit Mask */ 6065 #define SCB_ISAR0_DEBUG_INSTRS0 ((uint32_t)0x00100000) /*!< DEBUG_INSTRS Bit 0 */ 6066 #define SCB_ISAR0_DEBUG_INSTRS1 ((uint32_t)0x00200000) /*!< DEBUG_INSTRS Bit 1 */ 6067 #define SCB_ISAR0_DEBUG_INSTRS2 ((uint32_t)0x00400000) /*!< DEBUG_INSTRS Bit 2 */ 6068 #define SCB_ISAR0_DEBUG_INSTRS3 ((uint32_t)0x00800000) /*!< DEBUG_INSTRS Bit 3 */ 6069 #define SCB_ISAR0_DEBUG_INSTRS_0 ((uint32_t)0x00000000) /*!< no debug instructions present */ 6070 #define SCB_ISAR0_DEBUG_INSTRS_1 ((uint32_t)0x00100000) /*!< adds BKPT */ 6071 /* SCB_ISAR0[DIVIDE_INSTRS] Bits */ 6072 #define SCB_ISAR0_DIVIDE_INSTRS_OFS (24) /*!< DIVIDE_INSTRS Bit Offset */ 6073 #define SCB_ISAR0_DIVIDE_INSTRS_MASK ((uint32_t)0x0F000000) /*!< DIVIDE_INSTRS Bit Mask */ 6074 #define SCB_ISAR0_DIVIDE_INSTRS0 ((uint32_t)0x01000000) /*!< DIVIDE_INSTRS Bit 0 */ 6075 #define SCB_ISAR0_DIVIDE_INSTRS1 ((uint32_t)0x02000000) /*!< DIVIDE_INSTRS Bit 1 */ 6076 #define SCB_ISAR0_DIVIDE_INSTRS2 ((uint32_t)0x04000000) /*!< DIVIDE_INSTRS Bit 2 */ 6077 #define SCB_ISAR0_DIVIDE_INSTRS3 ((uint32_t)0x08000000) /*!< DIVIDE_INSTRS Bit 3 */ 6078 #define SCB_ISAR0_DIVIDE_INSTRS_0 ((uint32_t)0x00000000) /*!< no divide instructions present */ 6079 #define SCB_ISAR0_DIVIDE_INSTRS_1 ((uint32_t)0x01000000) /*!< adds SDIV, UDIV (v1 quotient only result) */ 6080 /* SCB_ISAR1[ETEND_INSRS] Bits */ 6081 #define SCB_ISAR1_ETEND_INSRS_OFS (12) /*!< EXTEND_INSRS Bit Offset */ 6082 #define SCB_ISAR1_ETEND_INSRS_MASK ((uint32_t)0x0000F000) /*!< EXTEND_INSRS Bit Mask */ 6083 #define SCB_ISAR1_ETEND_INSRS0 ((uint32_t)0x00001000) /*!< ETEND_INSRS Bit 0 */ 6084 #define SCB_ISAR1_ETEND_INSRS1 ((uint32_t)0x00002000) /*!< ETEND_INSRS Bit 1 */ 6085 #define SCB_ISAR1_ETEND_INSRS2 ((uint32_t)0x00004000) /*!< ETEND_INSRS Bit 2 */ 6086 #define SCB_ISAR1_ETEND_INSRS3 ((uint32_t)0x00008000) /*!< ETEND_INSRS Bit 3 */ 6087 #define SCB_ISAR1_ETEND_INSRS_0 ((uint32_t)0x00000000) /*!< no scalar (i.e. non-SIMD) sign/zero-extend instructions present */ 6088 #define SCB_ISAR1_ETEND_INSRS_1 ((uint32_t)0x00001000) /*!< adds SXTB, SXTH, UXTB, UXTH */ 6089 #define SCB_ISAR1_ETEND_INSRS_2 ((uint32_t)0x00002000) /*!< N/A */ 6090 /* SCB_ISAR1[IFTHEN_INSTRS] Bits */ 6091 #define SCB_ISAR1_IFTHEN_INSTRS_OFS (16) /*!< IFTHEN_INSTRS Bit Offset */ 6092 #define SCB_ISAR1_IFTHEN_INSTRS_MASK ((uint32_t)0x000F0000) /*!< IFTHEN_INSTRS Bit Mask */ 6093 #define SCB_ISAR1_IFTHEN_INSTRS0 ((uint32_t)0x00010000) /*!< IFTHEN_INSTRS Bit 0 */ 6094 #define SCB_ISAR1_IFTHEN_INSTRS1 ((uint32_t)0x00020000) /*!< IFTHEN_INSTRS Bit 1 */ 6095 #define SCB_ISAR1_IFTHEN_INSTRS2 ((uint32_t)0x00040000) /*!< IFTHEN_INSTRS Bit 2 */ 6096 #define SCB_ISAR1_IFTHEN_INSTRS3 ((uint32_t)0x00080000) /*!< IFTHEN_INSTRS Bit 3 */ 6097 #define SCB_ISAR1_IFTHEN_INSTRS_0 ((uint32_t)0x00000000) /*!< IT instructions not present */ 6098 #define SCB_ISAR1_IFTHEN_INSTRS_1 ((uint32_t)0x00010000) /*!< adds IT instructions (and IT bits in PSRs) */ 6099 /* SCB_ISAR1[IMMEDIATE_INSTRS] Bits */ 6100 #define SCB_ISAR1_IMMEDIATE_INSTRS_OFS (20) /*!< IMMEDIATE_INSTRS Bit Offset */ 6101 #define SCB_ISAR1_IMMEDIATE_INSTRS_MASK ((uint32_t)0x00F00000) /*!< IMMEDIATE_INSTRS Bit Mask */ 6102 #define SCB_ISAR1_IMMEDIATE_INSTRS0 ((uint32_t)0x00100000) /*!< IMMEDIATE_INSTRS Bit 0 */ 6103 #define SCB_ISAR1_IMMEDIATE_INSTRS1 ((uint32_t)0x00200000) /*!< IMMEDIATE_INSTRS Bit 1 */ 6104 #define SCB_ISAR1_IMMEDIATE_INSTRS2 ((uint32_t)0x00400000) /*!< IMMEDIATE_INSTRS Bit 2 */ 6105 #define SCB_ISAR1_IMMEDIATE_INSTRS3 ((uint32_t)0x00800000) /*!< IMMEDIATE_INSTRS Bit 3 */ 6106 #define SCB_ISAR1_IMMEDIATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no special immediate-generating instructions present */ 6107 #define SCB_ISAR1_IMMEDIATE_INSTRS_1 ((uint32_t)0x00100000) /*!< adds ADDW, MOVW, MOVT, SUBW */ 6108 /* SCB_ISAR1[INTERWORK_INSTRS] Bits */ 6109 #define SCB_ISAR1_INTERWORK_INSTRS_OFS (24) /*!< INTERWORK_INSTRS Bit Offset */ 6110 #define SCB_ISAR1_INTERWORK_INSTRS_MASK ((uint32_t)0x0F000000) /*!< INTERWORK_INSTRS Bit Mask */ 6111 #define SCB_ISAR1_INTERWORK_INSTRS0 ((uint32_t)0x01000000) /*!< INTERWORK_INSTRS Bit 0 */ 6112 #define SCB_ISAR1_INTERWORK_INSTRS1 ((uint32_t)0x02000000) /*!< INTERWORK_INSTRS Bit 1 */ 6113 #define SCB_ISAR1_INTERWORK_INSTRS2 ((uint32_t)0x04000000) /*!< INTERWORK_INSTRS Bit 2 */ 6114 #define SCB_ISAR1_INTERWORK_INSTRS3 ((uint32_t)0x08000000) /*!< INTERWORK_INSTRS Bit 3 */ 6115 #define SCB_ISAR1_INTERWORK_INSTRS_0 ((uint32_t)0x00000000) /*!< no interworking instructions supported */ 6116 #define SCB_ISAR1_INTERWORK_INSTRS_1 ((uint32_t)0x01000000) /*!< adds BX (and T bit in PSRs) */ 6117 #define SCB_ISAR1_INTERWORK_INSTRS_2 ((uint32_t)0x02000000) /*!< adds BLX, and PC loads have BX-like behavior */ 6118 #define SCB_ISAR1_INTERWORK_INSTRS_3 ((uint32_t)0x03000000) /*!< N/A */ 6119 /* SCB_ISAR2[LOADSTORE_INSTRS] Bits */ 6120 #define SCB_ISAR2_LOADSTORE_INSTRS_OFS ( 0) /*!< LOADSTORE_INSTRS Bit Offset */ 6121 #define SCB_ISAR2_LOADSTORE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< LOADSTORE_INSTRS Bit Mask */ 6122 #define SCB_ISAR2_LOADSTORE_INSTRS0 ((uint32_t)0x00000001) /*!< LOADSTORE_INSTRS Bit 0 */ 6123 #define SCB_ISAR2_LOADSTORE_INSTRS1 ((uint32_t)0x00000002) /*!< LOADSTORE_INSTRS Bit 1 */ 6124 #define SCB_ISAR2_LOADSTORE_INSTRS2 ((uint32_t)0x00000004) /*!< LOADSTORE_INSTRS Bit 2 */ 6125 #define SCB_ISAR2_LOADSTORE_INSTRS3 ((uint32_t)0x00000008) /*!< LOADSTORE_INSTRS Bit 3 */ 6126 #define SCB_ISAR2_LOADSTORE_INSTRS_0 ((uint32_t)0x00000000) /*!< no additional normal load/store instructions present */ 6127 #define SCB_ISAR2_LOADSTORE_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRD/STRD */ 6128 /* SCB_ISAR2[MEMHINT_INSTRS] Bits */ 6129 #define SCB_ISAR2_MEMHINT_INSTRS_OFS ( 4) /*!< MEMHINT_INSTRS Bit Offset */ 6130 #define SCB_ISAR2_MEMHINT_INSTRS_MASK ((uint32_t)0x000000F0) /*!< MEMHINT_INSTRS Bit Mask */ 6131 #define SCB_ISAR2_MEMHINT_INSTRS0 ((uint32_t)0x00000010) /*!< MEMHINT_INSTRS Bit 0 */ 6132 #define SCB_ISAR2_MEMHINT_INSTRS1 ((uint32_t)0x00000020) /*!< MEMHINT_INSTRS Bit 1 */ 6133 #define SCB_ISAR2_MEMHINT_INSTRS2 ((uint32_t)0x00000040) /*!< MEMHINT_INSTRS Bit 2 */ 6134 #define SCB_ISAR2_MEMHINT_INSTRS3 ((uint32_t)0x00000080) /*!< MEMHINT_INSTRS Bit 3 */ 6135 #define SCB_ISAR2_MEMHINT_INSTRS_0 ((uint32_t)0x00000000) /*!< no memory hint instructions presen */ 6136 #define SCB_ISAR2_MEMHINT_INSTRS_1 ((uint32_t)0x00000010) /*!< adds PLD */ 6137 #define SCB_ISAR2_MEMHINT_INSTRS_2 ((uint32_t)0x00000020) /*!< adds PLD (ie a repeat on value 1) */ 6138 #define SCB_ISAR2_MEMHINT_INSTRS_3 ((uint32_t)0x00000030) /*!< adds PLI */ 6139 /* SCB_ISAR2[MULTIACCESSINT_INSTRS] Bits */ 6140 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_OFS ( 8) /*!< MULTIACCESSINT_INSTRS Bit Offset */ 6141 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_MASK ((uint32_t)0x00000F00) /*!< MULTIACCESSINT_INSTRS Bit Mask */ 6142 #define SCB_ISAR2_MULTIACCESSINT_INSTRS0 ((uint32_t)0x00000100) /*!< MULTIACCESSINT_INSTRS Bit 0 */ 6143 #define SCB_ISAR2_MULTIACCESSINT_INSTRS1 ((uint32_t)0x00000200) /*!< MULTIACCESSINT_INSTRS Bit 1 */ 6144 #define SCB_ISAR2_MULTIACCESSINT_INSTRS2 ((uint32_t)0x00000400) /*!< MULTIACCESSINT_INSTRS Bit 2 */ 6145 #define SCB_ISAR2_MULTIACCESSINT_INSTRS3 ((uint32_t)0x00000800) /*!< MULTIACCESSINT_INSTRS Bit 3 */ 6146 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_0 ((uint32_t)0x00000000) /*!< the (LDM/STM) instructions are non-interruptible */ 6147 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_1 ((uint32_t)0x00000100) /*!< the (LDM/STM) instructions are restartable */ 6148 #define SCB_ISAR2_MULTIACCESSINT_INSTRS_2 ((uint32_t)0x00000200) /*!< the (LDM/STM) instructions are continuable */ 6149 /* SCB_ISAR2[MULT_INSTRS] Bits */ 6150 #define SCB_ISAR2_MULT_INSTRS_OFS (12) /*!< MULT_INSTRS Bit Offset */ 6151 #define SCB_ISAR2_MULT_INSTRS_MASK ((uint32_t)0x0000F000) /*!< MULT_INSTRS Bit Mask */ 6152 #define SCB_ISAR2_MULT_INSTRS0 ((uint32_t)0x00001000) /*!< MULT_INSTRS Bit 0 */ 6153 #define SCB_ISAR2_MULT_INSTRS1 ((uint32_t)0x00002000) /*!< MULT_INSTRS Bit 1 */ 6154 #define SCB_ISAR2_MULT_INSTRS2 ((uint32_t)0x00004000) /*!< MULT_INSTRS Bit 2 */ 6155 #define SCB_ISAR2_MULT_INSTRS3 ((uint32_t)0x00008000) /*!< MULT_INSTRS Bit 3 */ 6156 #define SCB_ISAR2_MULT_INSTRS_0 ((uint32_t)0x00000000) /*!< only MUL present */ 6157 #define SCB_ISAR2_MULT_INSTRS_1 ((uint32_t)0x00001000) /*!< adds MLA */ 6158 #define SCB_ISAR2_MULT_INSTRS_2 ((uint32_t)0x00002000) /*!< adds MLS */ 6159 /* SCB_ISAR2[MULTS_INSTRS] Bits */ 6160 #define SCB_ISAR2_MULTS_INSTRS_OFS (16) /*!< MULTS_INSTRS Bit Offset */ 6161 #define SCB_ISAR2_MULTS_INSTRS_MASK ((uint32_t)0x000F0000) /*!< MULTS_INSTRS Bit Mask */ 6162 #define SCB_ISAR2_MULTS_INSTRS0 ((uint32_t)0x00010000) /*!< MULTS_INSTRS Bit 0 */ 6163 #define SCB_ISAR2_MULTS_INSTRS1 ((uint32_t)0x00020000) /*!< MULTS_INSTRS Bit 1 */ 6164 #define SCB_ISAR2_MULTS_INSTRS2 ((uint32_t)0x00040000) /*!< MULTS_INSTRS Bit 2 */ 6165 #define SCB_ISAR2_MULTS_INSTRS3 ((uint32_t)0x00080000) /*!< MULTS_INSTRS Bit 3 */ 6166 #define SCB_ISAR2_MULTS_INSTRS_0 ((uint32_t)0x00000000) /*!< no signed multiply instructions present */ 6167 #define SCB_ISAR2_MULTS_INSTRS_1 ((uint32_t)0x00010000) /*!< adds SMULL, SMLAL */ 6168 #define SCB_ISAR2_MULTS_INSTRS_2 ((uint32_t)0x00020000) /*!< N/A */ 6169 #define SCB_ISAR2_MULTS_INSTRS_3 ((uint32_t)0x00030000) /*!< N/A */ 6170 /* SCB_ISAR2[MULTU_INSTRS] Bits */ 6171 #define SCB_ISAR2_MULTU_INSTRS_OFS (20) /*!< MULTU_INSTRS Bit Offset */ 6172 #define SCB_ISAR2_MULTU_INSTRS_MASK ((uint32_t)0x00F00000) /*!< MULTU_INSTRS Bit Mask */ 6173 #define SCB_ISAR2_MULTU_INSTRS0 ((uint32_t)0x00100000) /*!< MULTU_INSTRS Bit 0 */ 6174 #define SCB_ISAR2_MULTU_INSTRS1 ((uint32_t)0x00200000) /*!< MULTU_INSTRS Bit 1 */ 6175 #define SCB_ISAR2_MULTU_INSTRS2 ((uint32_t)0x00400000) /*!< MULTU_INSTRS Bit 2 */ 6176 #define SCB_ISAR2_MULTU_INSTRS3 ((uint32_t)0x00800000) /*!< MULTU_INSTRS Bit 3 */ 6177 #define SCB_ISAR2_MULTU_INSTRS_0 ((uint32_t)0x00000000) /*!< no unsigned multiply instructions present */ 6178 #define SCB_ISAR2_MULTU_INSTRS_1 ((uint32_t)0x00100000) /*!< adds UMULL, UMLAL */ 6179 #define SCB_ISAR2_MULTU_INSTRS_2 ((uint32_t)0x00200000) /*!< N/A */ 6180 /* SCB_ISAR2[REVERSAL_INSTRS] Bits */ 6181 #define SCB_ISAR2_REVERSAL_INSTRS_OFS (28) /*!< REVERSAL_INSTRS Bit Offset */ 6182 #define SCB_ISAR2_REVERSAL_INSTRS_MASK ((uint32_t)0xF0000000) /*!< REVERSAL_INSTRS Bit Mask */ 6183 #define SCB_ISAR2_REVERSAL_INSTRS0 ((uint32_t)0x10000000) /*!< REVERSAL_INSTRS Bit 0 */ 6184 #define SCB_ISAR2_REVERSAL_INSTRS1 ((uint32_t)0x20000000) /*!< REVERSAL_INSTRS Bit 1 */ 6185 #define SCB_ISAR2_REVERSAL_INSTRS2 ((uint32_t)0x40000000) /*!< REVERSAL_INSTRS Bit 2 */ 6186 #define SCB_ISAR2_REVERSAL_INSTRS3 ((uint32_t)0x80000000) /*!< REVERSAL_INSTRS Bit 3 */ 6187 #define SCB_ISAR2_REVERSAL_INSTRS_0 ((uint32_t)0x00000000) /*!< no reversal instructions present */ 6188 #define SCB_ISAR2_REVERSAL_INSTRS_1 ((uint32_t)0x10000000) /*!< adds REV, REV16, REVSH */ 6189 #define SCB_ISAR2_REVERSAL_INSTRS_2 ((uint32_t)0x20000000) /*!< adds RBIT */ 6190 /* SCB_ISAR3[SATRUATE_INSTRS] Bits */ 6191 #define SCB_ISAR3_SATRUATE_INSTRS_OFS ( 0) /*!< SATRUATE_INSTRS Bit Offset */ 6192 #define SCB_ISAR3_SATRUATE_INSTRS_MASK ((uint32_t)0x0000000F) /*!< SATRUATE_INSTRS Bit Mask */ 6193 #define SCB_ISAR3_SATRUATE_INSTRS0 ((uint32_t)0x00000001) /*!< SATRUATE_INSTRS Bit 0 */ 6194 #define SCB_ISAR3_SATRUATE_INSTRS1 ((uint32_t)0x00000002) /*!< SATRUATE_INSTRS Bit 1 */ 6195 #define SCB_ISAR3_SATRUATE_INSTRS2 ((uint32_t)0x00000004) /*!< SATRUATE_INSTRS Bit 2 */ 6196 #define SCB_ISAR3_SATRUATE_INSTRS3 ((uint32_t)0x00000008) /*!< SATRUATE_INSTRS Bit 3 */ 6197 #define SCB_ISAR3_SATRUATE_INSTRS_0 ((uint32_t)0x00000000) /*!< no non-SIMD saturate instructions present */ 6198 #define SCB_ISAR3_SATRUATE_INSTRS_1 ((uint32_t)0x00000001) /*!< N/A */ 6199 /* SCB_ISAR3[SIMD_INSTRS] Bits */ 6200 #define SCB_ISAR3_SIMD_INSTRS_OFS ( 4) /*!< SIMD_INSTRS Bit Offset */ 6201 #define SCB_ISAR3_SIMD_INSTRS_MASK ((uint32_t)0x000000F0) /*!< SIMD_INSTRS Bit Mask */ 6202 #define SCB_ISAR3_SIMD_INSTRS0 ((uint32_t)0x00000010) /*!< SIMD_INSTRS Bit 0 */ 6203 #define SCB_ISAR3_SIMD_INSTRS1 ((uint32_t)0x00000020) /*!< SIMD_INSTRS Bit 1 */ 6204 #define SCB_ISAR3_SIMD_INSTRS2 ((uint32_t)0x00000040) /*!< SIMD_INSTRS Bit 2 */ 6205 #define SCB_ISAR3_SIMD_INSTRS3 ((uint32_t)0x00000080) /*!< SIMD_INSTRS Bit 3 */ 6206 #define SCB_ISAR3_SIMD_INSTRS_0 ((uint32_t)0x00000000) /*!< no SIMD instructions present */ 6207 #define SCB_ISAR3_SIMD_INSTRS_1 ((uint32_t)0x00000010) /*!< adds SSAT, USAT (and the Q flag in the PSRs) */ 6208 #define SCB_ISAR3_SIMD_INSTRS_3 ((uint32_t)0x00000030) /*!< N/A */ 6209 /* SCB_ISAR3[SVC_INSTRS] Bits */ 6210 #define SCB_ISAR3_SVC_INSTRS_OFS ( 8) /*!< SVC_INSTRS Bit Offset */ 6211 #define SCB_ISAR3_SVC_INSTRS_MASK ((uint32_t)0x00000F00) /*!< SVC_INSTRS Bit Mask */ 6212 #define SCB_ISAR3_SVC_INSTRS0 ((uint32_t)0x00000100) /*!< SVC_INSTRS Bit 0 */ 6213 #define SCB_ISAR3_SVC_INSTRS1 ((uint32_t)0x00000200) /*!< SVC_INSTRS Bit 1 */ 6214 #define SCB_ISAR3_SVC_INSTRS2 ((uint32_t)0x00000400) /*!< SVC_INSTRS Bit 2 */ 6215 #define SCB_ISAR3_SVC_INSTRS3 ((uint32_t)0x00000800) /*!< SVC_INSTRS Bit 3 */ 6216 #define SCB_ISAR3_SVC_INSTRS_0 ((uint32_t)0x00000000) /*!< no SVC (SWI) instructions present */ 6217 #define SCB_ISAR3_SVC_INSTRS_1 ((uint32_t)0x00000100) /*!< adds SVC (SWI) */ 6218 /* SCB_ISAR3[SYNCPRIM_INSTRS] Bits */ 6219 #define SCB_ISAR3_SYNCPRIM_INSTRS_OFS (12) /*!< SYNCPRIM_INSTRS Bit Offset */ 6220 #define SCB_ISAR3_SYNCPRIM_INSTRS_MASK ((uint32_t)0x0000F000) /*!< SYNCPRIM_INSTRS Bit Mask */ 6221 #define SCB_ISAR3_SYNCPRIM_INSTRS0 ((uint32_t)0x00001000) /*!< SYNCPRIM_INSTRS Bit 0 */ 6222 #define SCB_ISAR3_SYNCPRIM_INSTRS1 ((uint32_t)0x00002000) /*!< SYNCPRIM_INSTRS Bit 1 */ 6223 #define SCB_ISAR3_SYNCPRIM_INSTRS2 ((uint32_t)0x00004000) /*!< SYNCPRIM_INSTRS Bit 2 */ 6224 #define SCB_ISAR3_SYNCPRIM_INSTRS3 ((uint32_t)0x00008000) /*!< SYNCPRIM_INSTRS Bit 3 */ 6225 #define SCB_ISAR3_SYNCPRIM_INSTRS_0 ((uint32_t)0x00000000) /*!< no synchronization primitives present */ 6226 #define SCB_ISAR3_SYNCPRIM_INSTRS_1 ((uint32_t)0x00001000) /*!< adds LDREX, STREX */ 6227 #define SCB_ISAR3_SYNCPRIM_INSTRS_2 ((uint32_t)0x00002000) /*!< adds LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, CLREX(N/A) */ 6228 /* SCB_ISAR3[TABBRANCH_INSTRS] Bits */ 6229 #define SCB_ISAR3_TABBRANCH_INSTRS_OFS (16) /*!< TABBRANCH_INSTRS Bit Offset */ 6230 #define SCB_ISAR3_TABBRANCH_INSTRS_MASK ((uint32_t)0x000F0000) /*!< TABBRANCH_INSTRS Bit Mask */ 6231 #define SCB_ISAR3_TABBRANCH_INSTRS0 ((uint32_t)0x00010000) /*!< TABBRANCH_INSTRS Bit 0 */ 6232 #define SCB_ISAR3_TABBRANCH_INSTRS1 ((uint32_t)0x00020000) /*!< TABBRANCH_INSTRS Bit 1 */ 6233 #define SCB_ISAR3_TABBRANCH_INSTRS2 ((uint32_t)0x00040000) /*!< TABBRANCH_INSTRS Bit 2 */ 6234 #define SCB_ISAR3_TABBRANCH_INSTRS3 ((uint32_t)0x00080000) /*!< TABBRANCH_INSTRS Bit 3 */ 6235 #define SCB_ISAR3_TABBRANCH_INSTRS_0 ((uint32_t)0x00000000) /*!< no table-branch instructions present */ 6236 #define SCB_ISAR3_TABBRANCH_INSTRS_1 ((uint32_t)0x00010000) /*!< adds TBB, TBH */ 6237 /* SCB_ISAR3[THUMBCOPY_INSTRS] Bits */ 6238 #define SCB_ISAR3_THUMBCOPY_INSTRS_OFS (20) /*!< THUMBCOPY_INSTRS Bit Offset */ 6239 #define SCB_ISAR3_THUMBCOPY_INSTRS_MASK ((uint32_t)0x00F00000) /*!< THUMBCOPY_INSTRS Bit Mask */ 6240 #define SCB_ISAR3_THUMBCOPY_INSTRS0 ((uint32_t)0x00100000) /*!< THUMBCOPY_INSTRS Bit 0 */ 6241 #define SCB_ISAR3_THUMBCOPY_INSTRS1 ((uint32_t)0x00200000) /*!< THUMBCOPY_INSTRS Bit 1 */ 6242 #define SCB_ISAR3_THUMBCOPY_INSTRS2 ((uint32_t)0x00400000) /*!< THUMBCOPY_INSTRS Bit 2 */ 6243 #define SCB_ISAR3_THUMBCOPY_INSTRS3 ((uint32_t)0x00800000) /*!< THUMBCOPY_INSTRS Bit 3 */ 6244 #define SCB_ISAR3_THUMBCOPY_INSTRS_0 ((uint32_t)0x00000000) /*!< Thumb MOV(register) instruction does not allow low reg -> low reg */ 6245 #define SCB_ISAR3_THUMBCOPY_INSTRS_1 ((uint32_t)0x00100000) /*!< adds Thumb MOV(register) low reg -> low reg and the CPY alias */ 6246 /* SCB_ISAR3[TRUENOP_INSTRS] Bits */ 6247 #define SCB_ISAR3_TRUENOP_INSTRS_OFS (24) /*!< TRUENOP_INSTRS Bit Offset */ 6248 #define SCB_ISAR3_TRUENOP_INSTRS_MASK ((uint32_t)0x0F000000) /*!< TRUENOP_INSTRS Bit Mask */ 6249 #define SCB_ISAR3_TRUENOP_INSTRS0 ((uint32_t)0x01000000) /*!< TRUENOP_INSTRS Bit 0 */ 6250 #define SCB_ISAR3_TRUENOP_INSTRS1 ((uint32_t)0x02000000) /*!< TRUENOP_INSTRS Bit 1 */ 6251 #define SCB_ISAR3_TRUENOP_INSTRS2 ((uint32_t)0x04000000) /*!< TRUENOP_INSTRS Bit 2 */ 6252 #define SCB_ISAR3_TRUENOP_INSTRS3 ((uint32_t)0x08000000) /*!< TRUENOP_INSTRS Bit 3 */ 6253 #define SCB_ISAR3_TRUENOP_INSTRS_0 ((uint32_t)0x00000000) /*!< true NOP instructions not present - that is, NOP instructions with no */ 6254 /* register dependencies */ 6255 #define SCB_ISAR3_TRUENOP_INSTRS_1 ((uint32_t)0x01000000) /*!< adds "true NOP", and the capability of additional "NOP compatible hints" */ 6256 /* SCB_ISAR4[UNPRIV_INSTRS] Bits */ 6257 #define SCB_ISAR4_UNPRIV_INSTRS_OFS ( 0) /*!< UNPRIV_INSTRS Bit Offset */ 6258 #define SCB_ISAR4_UNPRIV_INSTRS_MASK ((uint32_t)0x0000000F) /*!< UNPRIV_INSTRS Bit Mask */ 6259 #define SCB_ISAR4_UNPRIV_INSTRS0 ((uint32_t)0x00000001) /*!< UNPRIV_INSTRS Bit 0 */ 6260 #define SCB_ISAR4_UNPRIV_INSTRS1 ((uint32_t)0x00000002) /*!< UNPRIV_INSTRS Bit 1 */ 6261 #define SCB_ISAR4_UNPRIV_INSTRS2 ((uint32_t)0x00000004) /*!< UNPRIV_INSTRS Bit 2 */ 6262 #define SCB_ISAR4_UNPRIV_INSTRS3 ((uint32_t)0x00000008) /*!< UNPRIV_INSTRS Bit 3 */ 6263 #define SCB_ISAR4_UNPRIV_INSTRS_0 ((uint32_t)0x00000000) /*!< no "T variant" instructions exist */ 6264 #define SCB_ISAR4_UNPRIV_INSTRS_1 ((uint32_t)0x00000001) /*!< adds LDRBT, LDRT, STRBT, STRT */ 6265 #define SCB_ISAR4_UNPRIV_INSTRS_2 ((uint32_t)0x00000002) /*!< adds LDRHT, LDRSBT, LDRSHT, STRHT */ 6266 /* SCB_ISAR4[WITHSHIFTS_INSTRS] Bits */ 6267 #define SCB_ISAR4_WITHSHIFTS_INSTRS_OFS ( 4) /*!< WITHSHIFTS_INSTRS Bit Offset */ 6268 #define SCB_ISAR4_WITHSHIFTS_INSTRS_MASK ((uint32_t)0x000000F0) /*!< WITHSHIFTS_INSTRS Bit Mask */ 6269 #define SCB_ISAR4_WITHSHIFTS_INSTRS0 ((uint32_t)0x00000010) /*!< WITHSHIFTS_INSTRS Bit 0 */ 6270 #define SCB_ISAR4_WITHSHIFTS_INSTRS1 ((uint32_t)0x00000020) /*!< WITHSHIFTS_INSTRS Bit 1 */ 6271 #define SCB_ISAR4_WITHSHIFTS_INSTRS2 ((uint32_t)0x00000040) /*!< WITHSHIFTS_INSTRS Bit 2 */ 6272 #define SCB_ISAR4_WITHSHIFTS_INSTRS3 ((uint32_t)0x00000080) /*!< WITHSHIFTS_INSTRS Bit 3 */ 6273 #define SCB_ISAR4_WITHSHIFTS_INSTRS_0 ((uint32_t)0x00000000) /*!< non-zero shifts only support MOV and shift instructions (see notes) */ 6274 #define SCB_ISAR4_WITHSHIFTS_INSTRS_1 ((uint32_t)0x00000010) /*!< shifts of loads/stores over the range LSL 0-3 */ 6275 #define SCB_ISAR4_WITHSHIFTS_INSTRS_3 ((uint32_t)0x00000030) /*!< adds other constant shift options. */ 6276 #define SCB_ISAR4_WITHSHIFTS_INSTRS_4 ((uint32_t)0x00000040) /*!< adds register-controlled shift options. */ 6277 /* SCB_ISAR4[WRITEBACK_INSTRS] Bits */ 6278 #define SCB_ISAR4_WRITEBACK_INSTRS_OFS ( 8) /*!< WRITEBACK_INSTRS Bit Offset */ 6279 #define SCB_ISAR4_WRITEBACK_INSTRS_MASK ((uint32_t)0x00000F00) /*!< WRITEBACK_INSTRS Bit Mask */ 6280 #define SCB_ISAR4_WRITEBACK_INSTRS0 ((uint32_t)0x00000100) /*!< WRITEBACK_INSTRS Bit 0 */ 6281 #define SCB_ISAR4_WRITEBACK_INSTRS1 ((uint32_t)0x00000200) /*!< WRITEBACK_INSTRS Bit 1 */ 6282 #define SCB_ISAR4_WRITEBACK_INSTRS2 ((uint32_t)0x00000400) /*!< WRITEBACK_INSTRS Bit 2 */ 6283 #define SCB_ISAR4_WRITEBACK_INSTRS3 ((uint32_t)0x00000800) /*!< WRITEBACK_INSTRS Bit 3 */ 6284 #define SCB_ISAR4_WRITEBACK_INSTRS_0 ((uint32_t)0x00000000) /*!< only non-writeback addressing modes present, except that */ 6285 /* LDMIA/STMDB/PUSH/POP instructions support writeback addressing. */ 6286 #define SCB_ISAR4_WRITEBACK_INSTRS_1 ((uint32_t)0x00000100) /*!< adds all currently-defined writeback addressing modes (ARMv7, Thumb-2) */ 6287 /* SCB_ISAR4[BARRIER_INSTRS] Bits */ 6288 #define SCB_ISAR4_BARRIER_INSTRS_OFS (16) /*!< BARRIER_INSTRS Bit Offset */ 6289 #define SCB_ISAR4_BARRIER_INSTRS_MASK ((uint32_t)0x000F0000) /*!< BARRIER_INSTRS Bit Mask */ 6290 #define SCB_ISAR4_BARRIER_INSTRS0 ((uint32_t)0x00010000) /*!< BARRIER_INSTRS Bit 0 */ 6291 #define SCB_ISAR4_BARRIER_INSTRS1 ((uint32_t)0x00020000) /*!< BARRIER_INSTRS Bit 1 */ 6292 #define SCB_ISAR4_BARRIER_INSTRS2 ((uint32_t)0x00040000) /*!< BARRIER_INSTRS Bit 2 */ 6293 #define SCB_ISAR4_BARRIER_INSTRS3 ((uint32_t)0x00080000) /*!< BARRIER_INSTRS Bit 3 */ 6294 #define SCB_ISAR4_BARRIER_INSTRS_0 ((uint32_t)0x00000000) /*!< no barrier instructions supported */ 6295 #define SCB_ISAR4_BARRIER_INSTRS_1 ((uint32_t)0x00010000) /*!< adds DMB, DSB, ISB barrier instructions */ 6296 /* SCB_ISAR4[SYNCPRIM_INSTRS_FRAC] Bits */ 6297 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_OFS (20) /*!< SYNCPRIM_INSTRS_FRAC Bit Offset */ 6298 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_MASK ((uint32_t)0x00F00000) /*!< SYNCPRIM_INSTRS_FRAC Bit Mask */ 6299 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC0 ((uint32_t)0x00100000) /*!< SYNCPRIM_INSTRS_FRAC Bit 0 */ 6300 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC1 ((uint32_t)0x00200000) /*!< SYNCPRIM_INSTRS_FRAC Bit 1 */ 6301 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC2 ((uint32_t)0x00400000) /*!< SYNCPRIM_INSTRS_FRAC Bit 2 */ 6302 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC3 ((uint32_t)0x00800000) /*!< SYNCPRIM_INSTRS_FRAC Bit 3 */ 6303 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_0 ((uint32_t)0x00000000) /*!< no additional support */ 6304 #define SCB_ISAR4_SYNCPRIM_INSTRS_FRAC_3 ((uint32_t)0x00300000) /*!< adds CLREX, LDREXB, STREXB, LDREXH, STREXH */ 6305 /* SCB_ISAR4[PSR_M_INSTRS] Bits */ 6306 #define SCB_ISAR4_PSR_M_INSTRS_OFS (24) /*!< PSR_M_INSTRS Bit Offset */ 6307 #define SCB_ISAR4_PSR_M_INSTRS_MASK ((uint32_t)0x0F000000) /*!< PSR_M_INSTRS Bit Mask */ 6308 #define SCB_ISAR4_PSR_M_INSTRS0 ((uint32_t)0x01000000) /*!< PSR_M_INSTRS Bit 0 */ 6309 #define SCB_ISAR4_PSR_M_INSTRS1 ((uint32_t)0x02000000) /*!< PSR_M_INSTRS Bit 1 */ 6310 #define SCB_ISAR4_PSR_M_INSTRS2 ((uint32_t)0x04000000) /*!< PSR_M_INSTRS Bit 2 */ 6311 #define SCB_ISAR4_PSR_M_INSTRS3 ((uint32_t)0x08000000) /*!< PSR_M_INSTRS Bit 3 */ 6312 #define SCB_ISAR4_PSR_M_INSTRS_0 ((uint32_t)0x00000000) /*!< instructions not present */ 6313 #define SCB_ISAR4_PSR_M_INSTRS_1 ((uint32_t)0x01000000) /*!< adds CPS, MRS, and MSR instructions (M-profile forms) */ 6314 /* SCB_CPACR[CP11] Bits */ 6315 #define SCB_CPACR_CP11_OFS (22) /*!< CP11 Bit Offset */ 6316 #define SCB_CPACR_CP11_MASK ((uint32_t)0x00C00000) /*!< CP11 Bit Mask */ 6317 /* SCB_CPACR[CP10] Bits */ 6318 #define SCB_CPACR_CP10_OFS (20) /*!< CP10 Bit Offset */ 6319 #define SCB_CPACR_CP10_MASK ((uint32_t)0x00300000) /*!< CP10 Bit Mask */ 6320 /* SCB_SHPR1[SCB_SHPR1_PRI_4] Bits */ 6321 #define SCB_SHPR1_PRI_4_OFS ( 0) /*!< PRI_4 Offset */ 6322 #define SCB_SHPR1_PRI_4_M ((uint32_t)0x000000ff) /* */ 6323 /* SCB_SHPR1[SCB_SHPR1_PRI_5] Bits */ 6324 #define SCB_SHPR1_PRI_5_OFS ( 8) /*!< PRI_5 Offset */ 6325 #define SCB_SHPR1_PRI_5_M ((uint32_t)0x0000ff00) /* */ 6326 /* SCB_SHPR1[SCB_SHPR1_PRI_6] Bits */ 6327 #define SCB_SHPR1_PRI_6_OFS (16) /*!< PRI_6 Offset */ 6328 #define SCB_SHPR1_PRI_6_M ((uint32_t)0x00ff0000) /* */ 6329 /* SCB_SHPR1[SCB_SHPR1_PRI_7] Bits */ 6330 #define SCB_SHPR1_PRI_7_OFS (24) /*!< PRI_7 Offset */ 6331 #define SCB_SHPR1_PRI_7_M ((uint32_t)0xff000000) /* */ 6332 /* SCB_SHPR2[SCB_SHPR2_PRI_8] Bits */ 6333 #define SCB_SHPR2_PRI_8_OFS ( 0) /*!< PRI_8 Offset */ 6334 #define SCB_SHPR2_PRI_8_M ((uint32_t)0x000000ff) /* */ 6335 /* SCB_SHPR2[SCB_SHPR2_PRI_9] Bits */ 6336 #define SCB_SHPR2_PRI_9_OFS ( 8) /*!< PRI_9 Offset */ 6337 #define SCB_SHPR2_PRI_9_M ((uint32_t)0x0000ff00) /* */ 6338 /* SCB_SHPR2[SCB_SHPR2_PRI_10] Bits */ 6339 #define SCB_SHPR2_PRI_10_OFS (16) /*!< PRI_10 Offset */ 6340 #define SCB_SHPR2_PRI_10_M ((uint32_t)0x00ff0000) /* */ 6341 /* SCB_SHPR2[SCB_SHPR2_PRI_11] Bits */ 6342 #define SCB_SHPR2_PRI_11_OFS (24) /*!< PRI_11 Offset */ 6343 #define SCB_SHPR2_PRI_11_M ((uint32_t)0xff000000) /* */ 6344 /* SCB_SHPR3[SCB_SHPR3_PRI_12] Bits */ 6345 #define SCB_SHPR3_PRI_12_OFS ( 0) /*!< PRI_12 Offset */ 6346 #define SCB_SHPR3_PRI_12_M ((uint32_t)0x000000ff) /* */ 6347 /* SCB_SHPR3[SCB_SHPR3_PRI_13] Bits */ 6348 #define SCB_SHPR3_PRI_13_OFS ( 8) /*!< PRI_13 Offset */ 6349 #define SCB_SHPR3_PRI_13_M ((uint32_t)0x0000ff00) /* */ 6350 /* SCB_SHPR3[SCB_SHPR3_PRI_14] Bits */ 6351 #define SCB_SHPR3_PRI_14_OFS (16) /*!< PRI_14 Offset */ 6352 #define SCB_SHPR3_PRI_14_M ((uint32_t)0x00ff0000) /* */ 6353 /* SCB_SHPR3[SCB_SHPR3_PRI_15] Bits */ 6354 #define SCB_SHPR3_PRI_15_OFS (24) /*!< PRI_15 Offset */ 6355 #define SCB_SHPR3_PRI_15_M ((uint32_t)0xff000000) /* */ 6356 6357 /* SCB_CFSR[SCB_CFSR_IACCVIOL] Bits */ 6358 #define SCB_CFSR_IACCVIOL_OFS ( 0) /*!< IACCVIOL Offset */ 6359 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /* */ 6360 /* SCB_CFSR[SCB_CFSR_DACCVIOL] Bits */ 6361 #define SCB_CFSR_DACCVIOL_OFS ( 1) /*!< DACCVIOL Offset */ 6362 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /* */ 6363 /* SCB_CFSR[SCB_CFSR_MUNSTKERR] Bits */ 6364 #define SCB_CFSR_MUNSTKERR_OFS ( 3) /*!< MUNSTKERR Offset */ 6365 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /* */ 6366 /* SCB_CFSR[SCB_CFSR_MSTKERR] Bits */ 6367 #define SCB_CFSR_MSTKERR_OFS ( 4) /*!< MSTKERR Offset */ 6368 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /* */ 6369 /* SCB_CFSR[SCB_CFSR_MMARVALID] Bits */ 6370 #define SCB_CFSR_MMARVALID_OFS ( 7) /*!< MMARVALID Offset */ 6371 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /* */ 6372 /* SCB_CFSR[SCB_CFSR_IBUSERR] Bits */ 6373 #define SCB_CFSR_IBUSERR_OFS ( 8) /*!< IBUSERR Offset */ 6374 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /* */ 6375 /* SCB_CFSR[SCB_CFSR_PRECISERR] Bits */ 6376 #define SCB_CFSR_PRECISERR_OFS ( 9) /*!< PRECISERR Offset */ 6377 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /* */ 6378 /* SCB_CFSR[SCB_CFSR_IMPRECISERR] Bits */ 6379 #define SCB_CFSR_IMPRECISERR_OFS (10) /*!< IMPRECISERR Offset */ 6380 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /* */ 6381 /* SCB_CFSR[SCB_CFSR_UNSTKERR] Bits */ 6382 #define SCB_CFSR_UNSTKERR_OFS (11) /*!< UNSTKERR Offset */ 6383 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /* */ 6384 /* SCB_CFSR[SCB_CFSR_STKERR] Bits */ 6385 #define SCB_CFSR_STKERR_OFS (12) /*!< STKERR Offset */ 6386 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /* */ 6387 /* SCB_CFSR[SCB_CFSR_BFARVALID] Bits */ 6388 #define SCB_CFSR_BFARVALID_OFS (15) /*!< BFARVALID Offset */ 6389 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /* */ 6390 /* SCB_CFSR[SCB_CFSR_UNDEFINSTR] Bits */ 6391 #define SCB_CFSR_UNDEFINSTR_OFS (16) /*!< UNDEFINSTR Offset */ 6392 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /* */ 6393 /* SCB_CFSR[SCB_CFSR_INVSTATE] Bits */ 6394 #define SCB_CFSR_INVSTATE_OFS (17) /*!< INVSTATE Offset */ 6395 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /* */ 6396 /* SCB_CFSR[SCB_CFSR_INVPC] Bits */ 6397 #define SCB_CFSR_INVPC_OFS (18) /*!< INVPC Offset */ 6398 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /* */ 6399 /* SCB_CFSR[SCB_CFSR_NOCP] Bits */ 6400 #define SCB_CFSR_NOCP_OFS (19) /*!< NOCP Offset */ 6401 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /* */ 6402 /* SCB_CFSR[SCB_CFSR_UNALIGNED] Bits */ 6403 #define SCB_CFSR_UNALIGNED_OFS (24) /*!< UNALIGNED Offset */ 6404 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /* */ 6405 /* SCB_CFSR[SCB_CFSR_DIVBYZERO] Bits */ 6406 #define SCB_CFSR_DIVBYZERO_OFS (25) /*!< DIVBYZERO Offset */ 6407 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /* */ 6408 /* SCB_CFSR[SCB_CFSR_MLSPERR] Bits */ 6409 #define SCB_CFSR_MLSPERR_OFS ( 5) /*!< MLSPERR Offset */ 6410 #define SCB_CFSR_MLSPERR ((uint32_t)0x00000020) /* */ 6411 /* SCB_CFSR[SCB_CFSR_LSPERR] Bits */ 6412 #define SCB_CFSR_LSPERR_OFS (13) /*!< LSPERR Offset */ 6413 #define SCB_CFSR_LSPERR ((uint32_t)0x00002000) /* */ 6414 6415 6416 /****************************************************************************** 6417 * SCNSCB Bits 6418 ******************************************************************************/ 6419 6420 6421 /****************************************************************************** 6422 * SYSCTL Bits 6423 ******************************************************************************/ 6424 /* SYSCTL_REBOOT_CTL[REBOOT] Bits */ 6425 #define SYSCTL_REBOOT_CTL_REBOOT_OFS ( 0) /*!< REBOOT Bit Offset */ 6426 #define SYSCTL_REBOOT_CTL_REBOOT ((uint32_t)0x00000001) /*!< Write 1 initiates a Reboot of the device */ 6427 /* SYSCTL_REBOOT_CTL[WKEY] Bits */ 6428 #define SYSCTL_REBOOT_CTL_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ 6429 #define SYSCTL_REBOOT_CTL_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ 6430 /* SYSCTL_NMI_CTLSTAT[CS_SRC] Bits */ 6431 #define SYSCTL_NMI_CTLSTAT_CS_SRC_OFS ( 0) /*!< CS_SRC Bit Offset */ 6432 #define SYSCTL_NMI_CTLSTAT_CS_SRC ((uint32_t)0x00000001) /*!< CS interrupt as a source of NMI */ 6433 /* SYSCTL_NMI_CTLSTAT[PSS_SRC] Bits */ 6434 #define SYSCTL_NMI_CTLSTAT_PSS_SRC_OFS ( 1) /*!< PSS_SRC Bit Offset */ 6435 #define SYSCTL_NMI_CTLSTAT_PSS_SRC ((uint32_t)0x00000002) /*!< PSS interrupt as a source of NMI */ 6436 /* SYSCTL_NMI_CTLSTAT[PCM_SRC] Bits */ 6437 #define SYSCTL_NMI_CTLSTAT_PCM_SRC_OFS ( 2) /*!< PCM_SRC Bit Offset */ 6438 #define SYSCTL_NMI_CTLSTAT_PCM_SRC ((uint32_t)0x00000004) /*!< PCM interrupt as a source of NMI */ 6439 /* SYSCTL_NMI_CTLSTAT[PIN_SRC] Bits */ 6440 #define SYSCTL_NMI_CTLSTAT_PIN_SRC_OFS ( 3) /*!< PIN_SRC Bit Offset */ 6441 #define SYSCTL_NMI_CTLSTAT_PIN_SRC ((uint32_t)0x00000008) 6442 /* SYSCTL_NMI_CTLSTAT[CS_FLG] Bits */ 6443 #define SYSCTL_NMI_CTLSTAT_CS_FLG_OFS (16) /*!< CS_FLG Bit Offset */ 6444 #define SYSCTL_NMI_CTLSTAT_CS_FLG ((uint32_t)0x00010000) /*!< CS interrupt was the source of NMI */ 6445 /* SYSCTL_NMI_CTLSTAT[PSS_FLG] Bits */ 6446 #define SYSCTL_NMI_CTLSTAT_PSS_FLG_OFS (17) /*!< PSS_FLG Bit Offset */ 6447 #define SYSCTL_NMI_CTLSTAT_PSS_FLG ((uint32_t)0x00020000) /*!< PSS interrupt was the source of NMI */ 6448 /* SYSCTL_NMI_CTLSTAT[PCM_FLG] Bits */ 6449 #define SYSCTL_NMI_CTLSTAT_PCM_FLG_OFS (18) /*!< PCM_FLG Bit Offset */ 6450 #define SYSCTL_NMI_CTLSTAT_PCM_FLG ((uint32_t)0x00040000) /*!< PCM interrupt was the source of NMI */ 6451 /* SYSCTL_NMI_CTLSTAT[PIN_FLG] Bits */ 6452 #define SYSCTL_NMI_CTLSTAT_PIN_FLG_OFS (19) /*!< PIN_FLG Bit Offset */ 6453 #define SYSCTL_NMI_CTLSTAT_PIN_FLG ((uint32_t)0x00080000) /*!< RSTn/NMI pin was the source of NMI */ 6454 /* SYSCTL_WDTRESET_CTL[TIMEOUT] Bits */ 6455 #define SYSCTL_WDTRESET_CTL_TIMEOUT_OFS ( 0) /*!< TIMEOUT Bit Offset */ 6456 #define SYSCTL_WDTRESET_CTL_TIMEOUT ((uint32_t)0x00000001) /*!< WDT timeout reset type */ 6457 /* SYSCTL_WDTRESET_CTL[VIOLATION] Bits */ 6458 #define SYSCTL_WDTRESET_CTL_VIOLATION_OFS ( 1) /*!< VIOLATION Bit Offset */ 6459 #define SYSCTL_WDTRESET_CTL_VIOLATION ((uint32_t)0x00000002) /*!< WDT password violation reset type */ 6460 /* SYSCTL_PERIHALT_CTL[HALT_T16_0] Bits */ 6461 #define SYSCTL_PERIHALT_CTL_HALT_T16_0_OFS ( 0) /*!< HALT_T16_0 Bit Offset */ 6462 #define SYSCTL_PERIHALT_CTL_HALT_T16_0 ((uint32_t)0x00000001) /*!< Freezes IP operation when CPU is halted */ 6463 /* SYSCTL_PERIHALT_CTL[HALT_T16_1] Bits */ 6464 #define SYSCTL_PERIHALT_CTL_HALT_T16_1_OFS ( 1) /*!< HALT_T16_1 Bit Offset */ 6465 #define SYSCTL_PERIHALT_CTL_HALT_T16_1 ((uint32_t)0x00000002) /*!< Freezes IP operation when CPU is halted */ 6466 /* SYSCTL_PERIHALT_CTL[HALT_T16_2] Bits */ 6467 #define SYSCTL_PERIHALT_CTL_HALT_T16_2_OFS ( 2) /*!< HALT_T16_2 Bit Offset */ 6468 #define SYSCTL_PERIHALT_CTL_HALT_T16_2 ((uint32_t)0x00000004) /*!< Freezes IP operation when CPU is halted */ 6469 /* SYSCTL_PERIHALT_CTL[HALT_T16_3] Bits */ 6470 #define SYSCTL_PERIHALT_CTL_HALT_T16_3_OFS ( 3) /*!< HALT_T16_3 Bit Offset */ 6471 #define SYSCTL_PERIHALT_CTL_HALT_T16_3 ((uint32_t)0x00000008) /*!< Freezes IP operation when CPU is halted */ 6472 /* SYSCTL_PERIHALT_CTL[HALT_T32_0] Bits */ 6473 #define SYSCTL_PERIHALT_CTL_HALT_T32_0_OFS ( 4) /*!< HALT_T32_0 Bit Offset */ 6474 #define SYSCTL_PERIHALT_CTL_HALT_T32_0 ((uint32_t)0x00000010) /*!< Freezes IP operation when CPU is halted */ 6475 /* SYSCTL_PERIHALT_CTL[HALT_eUA0] Bits */ 6476 #define SYSCTL_PERIHALT_CTL_HALT_EUA0_OFS ( 5) /*!< HALT_eUA0 Bit Offset */ 6477 #define SYSCTL_PERIHALT_CTL_HALT_EUA0 ((uint32_t)0x00000020) /*!< Freezes IP operation when CPU is halted */ 6478 /* SYSCTL_PERIHALT_CTL[HALT_eUA1] Bits */ 6479 #define SYSCTL_PERIHALT_CTL_HALT_EUA1_OFS ( 6) /*!< HALT_eUA1 Bit Offset */ 6480 #define SYSCTL_PERIHALT_CTL_HALT_EUA1 ((uint32_t)0x00000040) /*!< Freezes IP operation when CPU is halted */ 6481 /* SYSCTL_PERIHALT_CTL[HALT_eUA2] Bits */ 6482 #define SYSCTL_PERIHALT_CTL_HALT_EUA2_OFS ( 7) /*!< HALT_eUA2 Bit Offset */ 6483 #define SYSCTL_PERIHALT_CTL_HALT_EUA2 ((uint32_t)0x00000080) /*!< Freezes IP operation when CPU is halted */ 6484 /* SYSCTL_PERIHALT_CTL[HALT_eUA3] Bits */ 6485 #define SYSCTL_PERIHALT_CTL_HALT_EUA3_OFS ( 8) /*!< HALT_eUA3 Bit Offset */ 6486 #define SYSCTL_PERIHALT_CTL_HALT_EUA3 ((uint32_t)0x00000100) /*!< Freezes IP operation when CPU is halted */ 6487 /* SYSCTL_PERIHALT_CTL[HALT_eUB0] Bits */ 6488 #define SYSCTL_PERIHALT_CTL_HALT_EUB0_OFS ( 9) /*!< HALT_eUB0 Bit Offset */ 6489 #define SYSCTL_PERIHALT_CTL_HALT_EUB0 ((uint32_t)0x00000200) /*!< Freezes IP operation when CPU is halted */ 6490 /* SYSCTL_PERIHALT_CTL[HALT_eUB1] Bits */ 6491 #define SYSCTL_PERIHALT_CTL_HALT_EUB1_OFS (10) /*!< HALT_eUB1 Bit Offset */ 6492 #define SYSCTL_PERIHALT_CTL_HALT_EUB1 ((uint32_t)0x00000400) /*!< Freezes IP operation when CPU is halted */ 6493 /* SYSCTL_PERIHALT_CTL[HALT_eUB2] Bits */ 6494 #define SYSCTL_PERIHALT_CTL_HALT_EUB2_OFS (11) /*!< HALT_eUB2 Bit Offset */ 6495 #define SYSCTL_PERIHALT_CTL_HALT_EUB2 ((uint32_t)0x00000800) /*!< Freezes IP operation when CPU is halted */ 6496 /* SYSCTL_PERIHALT_CTL[HALT_eUB3] Bits */ 6497 #define SYSCTL_PERIHALT_CTL_HALT_EUB3_OFS (12) /*!< HALT_eUB3 Bit Offset */ 6498 #define SYSCTL_PERIHALT_CTL_HALT_EUB3 ((uint32_t)0x00001000) /*!< Freezes IP operation when CPU is halted */ 6499 /* SYSCTL_PERIHALT_CTL[HALT_ADC] Bits */ 6500 #define SYSCTL_PERIHALT_CTL_HALT_ADC_OFS (13) /*!< HALT_ADC Bit Offset */ 6501 #define SYSCTL_PERIHALT_CTL_HALT_ADC ((uint32_t)0x00002000) /*!< Freezes IP operation when CPU is halted */ 6502 /* SYSCTL_PERIHALT_CTL[HALT_WDT] Bits */ 6503 #define SYSCTL_PERIHALT_CTL_HALT_WDT_OFS (14) /*!< HALT_WDT Bit Offset */ 6504 #define SYSCTL_PERIHALT_CTL_HALT_WDT ((uint32_t)0x00004000) /*!< Freezes IP operation when CPU is halted */ 6505 /* SYSCTL_PERIHALT_CTL[HALT_DMA] Bits */ 6506 #define SYSCTL_PERIHALT_CTL_HALT_DMA_OFS (15) /*!< HALT_DMA Bit Offset */ 6507 #define SYSCTL_PERIHALT_CTL_HALT_DMA ((uint32_t)0x00008000) /*!< Freezes IP operation when CPU is halted */ 6508 /* SYSCTL_SRAM_BANKEN[BNK0_EN] Bits */ 6509 #define SYSCTL_SRAM_BANKEN_BNK0_EN_OFS ( 0) /*!< BNK0_EN Bit Offset */ 6510 #define SYSCTL_SRAM_BANKEN_BNK0_EN ((uint32_t)0x00000001) /*!< SRAM Bank0 enable */ 6511 /* SYSCTL_SRAM_BANKEN[BNK1_EN] Bits */ 6512 #define SYSCTL_SRAM_BANKEN_BNK1_EN_OFS ( 1) /*!< BNK1_EN Bit Offset */ 6513 #define SYSCTL_SRAM_BANKEN_BNK1_EN ((uint32_t)0x00000002) /*!< SRAM Bank1 enable */ 6514 /* SYSCTL_SRAM_BANKEN[BNK2_EN] Bits */ 6515 #define SYSCTL_SRAM_BANKEN_BNK2_EN_OFS ( 2) /*!< BNK2_EN Bit Offset */ 6516 #define SYSCTL_SRAM_BANKEN_BNK2_EN ((uint32_t)0x00000004) /*!< SRAM Bank1 enable */ 6517 /* SYSCTL_SRAM_BANKEN[BNK3_EN] Bits */ 6518 #define SYSCTL_SRAM_BANKEN_BNK3_EN_OFS ( 3) /*!< BNK3_EN Bit Offset */ 6519 #define SYSCTL_SRAM_BANKEN_BNK3_EN ((uint32_t)0x00000008) /*!< SRAM Bank1 enable */ 6520 /* SYSCTL_SRAM_BANKEN[BNK4_EN] Bits */ 6521 #define SYSCTL_SRAM_BANKEN_BNK4_EN_OFS ( 4) /*!< BNK4_EN Bit Offset */ 6522 #define SYSCTL_SRAM_BANKEN_BNK4_EN ((uint32_t)0x00000010) /*!< SRAM Bank1 enable */ 6523 /* SYSCTL_SRAM_BANKEN[BNK5_EN] Bits */ 6524 #define SYSCTL_SRAM_BANKEN_BNK5_EN_OFS ( 5) /*!< BNK5_EN Bit Offset */ 6525 #define SYSCTL_SRAM_BANKEN_BNK5_EN ((uint32_t)0x00000020) /*!< SRAM Bank1 enable */ 6526 /* SYSCTL_SRAM_BANKEN[BNK6_EN] Bits */ 6527 #define SYSCTL_SRAM_BANKEN_BNK6_EN_OFS ( 6) /*!< BNK6_EN Bit Offset */ 6528 #define SYSCTL_SRAM_BANKEN_BNK6_EN ((uint32_t)0x00000040) /*!< SRAM Bank1 enable */ 6529 /* SYSCTL_SRAM_BANKEN[BNK7_EN] Bits */ 6530 #define SYSCTL_SRAM_BANKEN_BNK7_EN_OFS ( 7) /*!< BNK7_EN Bit Offset */ 6531 #define SYSCTL_SRAM_BANKEN_BNK7_EN ((uint32_t)0x00000080) /*!< SRAM Bank1 enable */ 6532 /* SYSCTL_SRAM_BANKEN[SRAM_RDY] Bits */ 6533 #define SYSCTL_SRAM_BANKEN_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ 6534 #define SYSCTL_SRAM_BANKEN_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ 6535 /* SYSCTL_SRAM_BANKRET[BNK0_RET] Bits */ 6536 #define SYSCTL_SRAM_BANKRET_BNK0_RET_OFS ( 0) /*!< BNK0_RET Bit Offset */ 6537 #define SYSCTL_SRAM_BANKRET_BNK0_RET ((uint32_t)0x00000001) /*!< Bank0 retention */ 6538 /* SYSCTL_SRAM_BANKRET[BNK1_RET] Bits */ 6539 #define SYSCTL_SRAM_BANKRET_BNK1_RET_OFS ( 1) /*!< BNK1_RET Bit Offset */ 6540 #define SYSCTL_SRAM_BANKRET_BNK1_RET ((uint32_t)0x00000002) /*!< Bank1 retention */ 6541 /* SYSCTL_SRAM_BANKRET[BNK2_RET] Bits */ 6542 #define SYSCTL_SRAM_BANKRET_BNK2_RET_OFS ( 2) /*!< BNK2_RET Bit Offset */ 6543 #define SYSCTL_SRAM_BANKRET_BNK2_RET ((uint32_t)0x00000004) /*!< Bank2 retention */ 6544 /* SYSCTL_SRAM_BANKRET[BNK3_RET] Bits */ 6545 #define SYSCTL_SRAM_BANKRET_BNK3_RET_OFS ( 3) /*!< BNK3_RET Bit Offset */ 6546 #define SYSCTL_SRAM_BANKRET_BNK3_RET ((uint32_t)0x00000008) /*!< Bank3 retention */ 6547 /* SYSCTL_SRAM_BANKRET[BNK4_RET] Bits */ 6548 #define SYSCTL_SRAM_BANKRET_BNK4_RET_OFS ( 4) /*!< BNK4_RET Bit Offset */ 6549 #define SYSCTL_SRAM_BANKRET_BNK4_RET ((uint32_t)0x00000010) /*!< Bank4 retention */ 6550 /* SYSCTL_SRAM_BANKRET[BNK5_RET] Bits */ 6551 #define SYSCTL_SRAM_BANKRET_BNK5_RET_OFS ( 5) /*!< BNK5_RET Bit Offset */ 6552 #define SYSCTL_SRAM_BANKRET_BNK5_RET ((uint32_t)0x00000020) /*!< Bank5 retention */ 6553 /* SYSCTL_SRAM_BANKRET[BNK6_RET] Bits */ 6554 #define SYSCTL_SRAM_BANKRET_BNK6_RET_OFS ( 6) /*!< BNK6_RET Bit Offset */ 6555 #define SYSCTL_SRAM_BANKRET_BNK6_RET ((uint32_t)0x00000040) /*!< Bank6 retention */ 6556 /* SYSCTL_SRAM_BANKRET[BNK7_RET] Bits */ 6557 #define SYSCTL_SRAM_BANKRET_BNK7_RET_OFS ( 7) /*!< BNK7_RET Bit Offset */ 6558 #define SYSCTL_SRAM_BANKRET_BNK7_RET ((uint32_t)0x00000080) /*!< Bank7 retention */ 6559 /* SYSCTL_SRAM_BANKRET[SRAM_RDY] Bits */ 6560 #define SYSCTL_SRAM_BANKRET_SRAM_RDY_OFS (16) /*!< SRAM_RDY Bit Offset */ 6561 #define SYSCTL_SRAM_BANKRET_SRAM_RDY ((uint32_t)0x00010000) /*!< SRAM ready */ 6562 /* SYSCTL_DIO_GLTFLT_CTL[GLTCH_EN] Bits */ 6563 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN_OFS ( 0) /*!< GLTCH_EN Bit Offset */ 6564 #define SYSCTL_DIO_GLTFLT_CTL_GLTCH_EN ((uint32_t)0x00000001) /*!< Glitch filter enable */ 6565 /* SYSCTL_SECDATA_UNLOCK[UNLKEY] Bits */ 6566 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ 6567 #define SYSCTL_SECDATA_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ 6568 /* SYSCTL_MASTER_UNLOCK[UNLKEY] Bits */ 6569 #define SYSCTL_MASTER_UNLOCK_UNLKEY_OFS ( 0) /*!< UNLKEY Bit Offset */ 6570 #define SYSCTL_MASTER_UNLOCK_UNLKEY_MASK ((uint32_t)0x0000FFFF) /*!< UNLKEY Bit Mask */ 6571 /* SYSCTL_RESET_REQ[POR] Bits */ 6572 #define SYSCTL_RESET_REQ_POR_OFS ( 0) /*!< POR Bit Offset */ 6573 #define SYSCTL_RESET_REQ_POR ((uint32_t)0x00000001) /*!< Generate POR */ 6574 /* SYSCTL_RESET_REQ[REBOOT] Bits */ 6575 #define SYSCTL_RESET_REQ_REBOOT_OFS ( 1) /*!< REBOOT Bit Offset */ 6576 #define SYSCTL_RESET_REQ_REBOOT ((uint32_t)0x00000002) /*!< Generate Reboot_Reset */ 6577 /* SYSCTL_RESET_REQ[WKEY] Bits */ 6578 #define SYSCTL_RESET_REQ_WKEY_OFS ( 8) /*!< WKEY Bit Offset */ 6579 #define SYSCTL_RESET_REQ_WKEY_MASK ((uint32_t)0x0000FF00) /*!< WKEY Bit Mask */ 6580 /* SYSCTL_RESET_STATOVER[SOFT] Bits */ 6581 #define SYSCTL_RESET_STATOVER_SOFT_OFS ( 0) /*!< SOFT Bit Offset */ 6582 #define SYSCTL_RESET_STATOVER_SOFT ((uint32_t)0x00000001) /*!< Indicates if SOFT Reset is active */ 6583 /* SYSCTL_RESET_STATOVER[HARD] Bits */ 6584 #define SYSCTL_RESET_STATOVER_HARD_OFS ( 1) /*!< HARD Bit Offset */ 6585 #define SYSCTL_RESET_STATOVER_HARD ((uint32_t)0x00000002) /*!< Indicates if HARD Reset is active */ 6586 /* SYSCTL_RESET_STATOVER[REBOOT] Bits */ 6587 #define SYSCTL_RESET_STATOVER_REBOOT_OFS ( 2) /*!< REBOOT Bit Offset */ 6588 #define SYSCTL_RESET_STATOVER_REBOOT ((uint32_t)0x00000004) /*!< Indicates if Reboot Reset is active */ 6589 /* SYSCTL_RESET_STATOVER[SOFT_OVER] Bits */ 6590 #define SYSCTL_RESET_STATOVER_SOFT_OVER_OFS ( 8) /*!< SOFT_OVER Bit Offset */ 6591 #define SYSCTL_RESET_STATOVER_SOFT_OVER ((uint32_t)0x00000100) /*!< SOFT_Reset overwrite request */ 6592 /* SYSCTL_RESET_STATOVER[HARD_OVER] Bits */ 6593 #define SYSCTL_RESET_STATOVER_HARD_OVER_OFS ( 9) /*!< HARD_OVER Bit Offset */ 6594 #define SYSCTL_RESET_STATOVER_HARD_OVER ((uint32_t)0x00000200) /*!< HARD_Reset overwrite request */ 6595 /* SYSCTL_RESET_STATOVER[RBT_OVER] Bits */ 6596 #define SYSCTL_RESET_STATOVER_RBT_OVER_OFS (10) /*!< RBT_OVER Bit Offset */ 6597 #define SYSCTL_RESET_STATOVER_RBT_OVER ((uint32_t)0x00000400) /*!< Reboot Reset overwrite request */ 6598 /* Pre-defined bitfield values */ 6599 #define SYSCTL_REBOOT_CTL_WKEY_VAL ((uint32_t)0x00006900) /*!< Key value to enable writes to bit 0 */ 6600 /* cleared */ 6601 6602 6603 /****************************************************************************** 6604 * SYSTICK Bits 6605 ******************************************************************************/ 6606 6607 /****************************************************************************** 6608 * Timer32 Bits 6609 ******************************************************************************/ 6610 /* TIMER32_CONTROL[ONESHOT] Bits */ 6611 #define TIMER32_CONTROL_ONESHOT_OFS ( 0) /*!< ONESHOT Bit Offset */ 6612 #define TIMER32_CONTROL_ONESHOT ((uint32_t)0x00000001) /*!< Selects one-shot or wrapping counter mode */ 6613 /* TIMER32_CONTROL[SIZE] Bits */ 6614 #define TIMER32_CONTROL_SIZE_OFS ( 1) /*!< SIZE Bit Offset */ 6615 #define TIMER32_CONTROL_SIZE ((uint32_t)0x00000002) /*!< Selects 16 or 32 bit counter operation */ 6616 /* TIMER32_CONTROL[PRESCALE] Bits */ 6617 #define TIMER32_CONTROL_PRESCALE_OFS ( 2) /*!< PRESCALE Bit Offset */ 6618 #define TIMER32_CONTROL_PRESCALE_MASK ((uint32_t)0x0000000C) /*!< PRESCALE Bit Mask */ 6619 #define TIMER32_CONTROL_PRESCALE0 ((uint32_t)0x00000004) /*!< PRESCALE Bit 0 */ 6620 #define TIMER32_CONTROL_PRESCALE1 ((uint32_t)0x00000008) /*!< PRESCALE Bit 1 */ 6621 #define TIMER32_CONTROL_PRESCALE_0 ((uint32_t)0x00000000) /*!< 0 stages of prescale, clock is divided by 1 */ 6622 #define TIMER32_CONTROL_PRESCALE_1 ((uint32_t)0x00000004) /*!< 4 stages of prescale, clock is divided by 16 */ 6623 #define TIMER32_CONTROL_PRESCALE_2 ((uint32_t)0x00000008) /*!< 8 stages of prescale, clock is divided by 256 */ 6624 /* TIMER32_CONTROL[IE] Bits */ 6625 #define TIMER32_CONTROL_IE_OFS ( 5) /*!< IE Bit Offset */ 6626 #define TIMER32_CONTROL_IE ((uint32_t)0x00000020) /*!< Interrupt enable bit */ 6627 /* TIMER32_CONTROL[MODE] Bits */ 6628 #define TIMER32_CONTROL_MODE_OFS ( 6) /*!< MODE Bit Offset */ 6629 #define TIMER32_CONTROL_MODE ((uint32_t)0x00000040) /*!< Mode bit */ 6630 /* TIMER32_CONTROL[ENABLE] Bits */ 6631 #define TIMER32_CONTROL_ENABLE_OFS ( 7) /*!< ENABLE Bit Offset */ 6632 #define TIMER32_CONTROL_ENABLE ((uint32_t)0x00000080) 6633 /* TIMER32_RIS[RAW_IFG] Bits */ 6634 #define TIMER32_RIS_RAW_IFG_OFS ( 0) /*!< RAW_IFG Bit Offset */ 6635 #define TIMER32_RIS_RAW_IFG ((uint32_t)0x00000001) /*!< Raw interrupt status */ 6636 /* TIMER32_MIS[IFG] Bits */ 6637 #define TIMER32_MIS_IFG_OFS ( 0) /*!< IFG Bit Offset */ 6638 #define TIMER32_MIS_IFG ((uint32_t)0x00000001) /*!< Enabled interrupt status */ 6639 6640 6641 6642 /****************************************************************************** 6643 * TIMER_A Bits 6644 ******************************************************************************/ 6645 /* TIMER_A_CTL[IFG] Bits */ 6646 #define TIMER_A_CTL_IFG_OFS ( 0) /*!< TAIFG Bit Offset */ 6647 #define TIMER_A_CTL_IFG ((uint16_t)0x0001) /*!< TimerA interrupt flag */ 6648 /* TIMER_A_CTL[IE] Bits */ 6649 #define TIMER_A_CTL_IE_OFS ( 1) /*!< TAIE Bit Offset */ 6650 #define TIMER_A_CTL_IE ((uint16_t)0x0002) /*!< TimerA interrupt enable */ 6651 /* TIMER_A_CTL[CLR] Bits */ 6652 #define TIMER_A_CTL_CLR_OFS ( 2) /*!< TACLR Bit Offset */ 6653 #define TIMER_A_CTL_CLR ((uint16_t)0x0004) /*!< TimerA clear */ 6654 /* TIMER_A_CTL[MC] Bits */ 6655 #define TIMER_A_CTL_MC_OFS ( 4) /*!< MC Bit Offset */ 6656 #define TIMER_A_CTL_MC_MASK ((uint16_t)0x0030) /*!< MC Bit Mask */ 6657 #define TIMER_A_CTL_MC0 ((uint16_t)0x0010) /*!< MC Bit 0 */ 6658 #define TIMER_A_CTL_MC1 ((uint16_t)0x0020) /*!< MC Bit 1 */ 6659 #define TIMER_A_CTL_MC_0 ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ 6660 #define TIMER_A_CTL_MC_1 ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ 6661 #define TIMER_A_CTL_MC_2 ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ 6662 #define TIMER_A_CTL_MC_3 ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ 6663 #define TIMER_A_CTL_MC__STOP ((uint16_t)0x0000) /*!< Stop mode: Timer is halted */ 6664 #define TIMER_A_CTL_MC__UP ((uint16_t)0x0010) /*!< Up mode: Timer counts up to TAxCCR0 */ 6665 #define TIMER_A_CTL_MC__CONTINUOUS ((uint16_t)0x0020) /*!< Continuous mode: Timer counts up to 0FFFFh */ 6666 #define TIMER_A_CTL_MC__UPDOWN ((uint16_t)0x0030) /*!< Up/down mode: Timer counts up to TAxCCR0 then down to 0000h */ 6667 /* TIMER_A_CTL[ID] Bits */ 6668 #define TIMER_A_CTL_ID_OFS ( 6) /*!< ID Bit Offset */ 6669 #define TIMER_A_CTL_ID_MASK ((uint16_t)0x00C0) /*!< ID Bit Mask */ 6670 #define TIMER_A_CTL_ID0 ((uint16_t)0x0040) /*!< ID Bit 0 */ 6671 #define TIMER_A_CTL_ID1 ((uint16_t)0x0080) /*!< ID Bit 1 */ 6672 #define TIMER_A_CTL_ID_0 ((uint16_t)0x0000) /*!< /1 */ 6673 #define TIMER_A_CTL_ID_1 ((uint16_t)0x0040) /*!< /2 */ 6674 #define TIMER_A_CTL_ID_2 ((uint16_t)0x0080) /*!< /4 */ 6675 #define TIMER_A_CTL_ID_3 ((uint16_t)0x00C0) /*!< /8 */ 6676 #define TIMER_A_CTL_ID__1 ((uint16_t)0x0000) /*!< /1 */ 6677 #define TIMER_A_CTL_ID__2 ((uint16_t)0x0040) /*!< /2 */ 6678 #define TIMER_A_CTL_ID__4 ((uint16_t)0x0080) /*!< /4 */ 6679 #define TIMER_A_CTL_ID__8 ((uint16_t)0x00C0) /*!< /8 */ 6680 /* TIMER_A_CTL[SSEL] Bits */ 6681 #define TIMER_A_CTL_SSEL_OFS ( 8) /*!< TASSEL Bit Offset */ 6682 #define TIMER_A_CTL_SSEL_MASK ((uint16_t)0x0300) /*!< TASSEL Bit Mask */ 6683 #define TIMER_A_CTL_SSEL0 ((uint16_t)0x0100) /*!< SSEL Bit 0 */ 6684 #define TIMER_A_CTL_SSEL1 ((uint16_t)0x0200) /*!< SSEL Bit 1 */ 6685 #define TIMER_A_CTL_TASSEL_0 ((uint16_t)0x0000) /*!< TAxCLK */ 6686 #define TIMER_A_CTL_TASSEL_1 ((uint16_t)0x0100) /*!< ACLK */ 6687 #define TIMER_A_CTL_TASSEL_2 ((uint16_t)0x0200) /*!< SMCLK */ 6688 #define TIMER_A_CTL_TASSEL_3 ((uint16_t)0x0300) /*!< INCLK */ 6689 #define TIMER_A_CTL_SSEL__TACLK ((uint16_t)0x0000) /*!< TAxCLK */ 6690 #define TIMER_A_CTL_SSEL__ACLK ((uint16_t)0x0100) /*!< ACLK */ 6691 #define TIMER_A_CTL_SSEL__SMCLK ((uint16_t)0x0200) /*!< SMCLK */ 6692 #define TIMER_A_CTL_SSEL__INCLK ((uint16_t)0x0300) /*!< INCLK */ 6693 /* TIMER_A_CCTLN[CCIFG] Bits */ 6694 #define TIMER_A_CCTLN_CCIFG_OFS ( 0) /*!< CCIFG Bit Offset */ 6695 #define TIMER_A_CCTLN_CCIFG ((uint16_t)0x0001) /*!< Capture/compare interrupt flag */ 6696 /* TIMER_A_CCTLN[COV] Bits */ 6697 #define TIMER_A_CCTLN_COV_OFS ( 1) /*!< COV Bit Offset */ 6698 #define TIMER_A_CCTLN_COV ((uint16_t)0x0002) /*!< Capture overflow */ 6699 /* TIMER_A_CCTLN[OUT] Bits */ 6700 #define TIMER_A_CCTLN_OUT_OFS ( 2) /*!< OUT Bit Offset */ 6701 #define TIMER_A_CCTLN_OUT ((uint16_t)0x0004) /*!< Output */ 6702 /* TIMER_A_CCTLN[CCI] Bits */ 6703 #define TIMER_A_CCTLN_CCI_OFS ( 3) /*!< CCI Bit Offset */ 6704 #define TIMER_A_CCTLN_CCI ((uint16_t)0x0008) /*!< Capture/compare input */ 6705 /* TIMER_A_CCTLN[CCIE] Bits */ 6706 #define TIMER_A_CCTLN_CCIE_OFS ( 4) /*!< CCIE Bit Offset */ 6707 #define TIMER_A_CCTLN_CCIE ((uint16_t)0x0010) /*!< Capture/compare interrupt enable */ 6708 /* TIMER_A_CCTLN[OUTMOD] Bits */ 6709 #define TIMER_A_CCTLN_OUTMOD_OFS ( 5) /*!< OUTMOD Bit Offset */ 6710 #define TIMER_A_CCTLN_OUTMOD_MASK ((uint16_t)0x00E0) /*!< OUTMOD Bit Mask */ 6711 #define TIMER_A_CCTLN_OUTMOD0 ((uint16_t)0x0020) /*!< OUTMOD Bit 0 */ 6712 #define TIMER_A_CCTLN_OUTMOD1 ((uint16_t)0x0040) /*!< OUTMOD Bit 1 */ 6713 #define TIMER_A_CCTLN_OUTMOD2 ((uint16_t)0x0080) /*!< OUTMOD Bit 2 */ 6714 #define TIMER_A_CCTLN_OUTMOD_0 ((uint16_t)0x0000) /*!< OUT bit value */ 6715 #define TIMER_A_CCTLN_OUTMOD_1 ((uint16_t)0x0020) /*!< Set */ 6716 #define TIMER_A_CCTLN_OUTMOD_2 ((uint16_t)0x0040) /*!< Toggle/reset */ 6717 #define TIMER_A_CCTLN_OUTMOD_3 ((uint16_t)0x0060) /*!< Set/reset */ 6718 #define TIMER_A_CCTLN_OUTMOD_4 ((uint16_t)0x0080) /*!< Toggle */ 6719 #define TIMER_A_CCTLN_OUTMOD_5 ((uint16_t)0x00A0) /*!< Reset */ 6720 #define TIMER_A_CCTLN_OUTMOD_6 ((uint16_t)0x00C0) /*!< Toggle/set */ 6721 #define TIMER_A_CCTLN_OUTMOD_7 ((uint16_t)0x00E0) /*!< Reset/set */ 6722 /* TIMER_A_CCTLN[CAP] Bits */ 6723 #define TIMER_A_CCTLN_CAP_OFS ( 8) /*!< CAP Bit Offset */ 6724 #define TIMER_A_CCTLN_CAP ((uint16_t)0x0100) /*!< Capture mode */ 6725 /* TIMER_A_CCTLN[SCCI] Bits */ 6726 #define TIMER_A_CCTLN_SCCI_OFS (10) /*!< SCCI Bit Offset */ 6727 #define TIMER_A_CCTLN_SCCI ((uint16_t)0x0400) /*!< Synchronized capture/compare input */ 6728 /* TIMER_A_CCTLN[SCS] Bits */ 6729 #define TIMER_A_CCTLN_SCS_OFS (11) /*!< SCS Bit Offset */ 6730 #define TIMER_A_CCTLN_SCS ((uint16_t)0x0800) /*!< Synchronize capture source */ 6731 /* TIMER_A_CCTLN[CCIS] Bits */ 6732 #define TIMER_A_CCTLN_CCIS_OFS (12) /*!< CCIS Bit Offset */ 6733 #define TIMER_A_CCTLN_CCIS_MASK ((uint16_t)0x3000) /*!< CCIS Bit Mask */ 6734 #define TIMER_A_CCTLN_CCIS0 ((uint16_t)0x1000) /*!< CCIS Bit 0 */ 6735 #define TIMER_A_CCTLN_CCIS1 ((uint16_t)0x2000) /*!< CCIS Bit 1 */ 6736 #define TIMER_A_CCTLN_CCIS_0 ((uint16_t)0x0000) /*!< CCIxA */ 6737 #define TIMER_A_CCTLN_CCIS_1 ((uint16_t)0x1000) /*!< CCIxB */ 6738 #define TIMER_A_CCTLN_CCIS_2 ((uint16_t)0x2000) /*!< GND */ 6739 #define TIMER_A_CCTLN_CCIS_3 ((uint16_t)0x3000) /*!< VCC */ 6740 #define TIMER_A_CCTLN_CCIS__CCIA ((uint16_t)0x0000) /*!< CCIxA */ 6741 #define TIMER_A_CCTLN_CCIS__CCIB ((uint16_t)0x1000) /*!< CCIxB */ 6742 #define TIMER_A_CCTLN_CCIS__GND ((uint16_t)0x2000) /*!< GND */ 6743 #define TIMER_A_CCTLN_CCIS__VCC ((uint16_t)0x3000) /*!< VCC */ 6744 /* TIMER_A_CCTLN[CM] Bits */ 6745 #define TIMER_A_CCTLN_CM_OFS (14) /*!< CM Bit Offset */ 6746 #define TIMER_A_CCTLN_CM_MASK ((uint16_t)0xC000) /*!< CM Bit Mask */ 6747 #define TIMER_A_CCTLN_CM0 ((uint16_t)0x4000) /*!< CM Bit 0 */ 6748 #define TIMER_A_CCTLN_CM1 ((uint16_t)0x8000) /*!< CM Bit 1 */ 6749 #define TIMER_A_CCTLN_CM_0 ((uint16_t)0x0000) /*!< No capture */ 6750 #define TIMER_A_CCTLN_CM_1 ((uint16_t)0x4000) /*!< Capture on rising edge */ 6751 #define TIMER_A_CCTLN_CM_2 ((uint16_t)0x8000) /*!< Capture on falling edge */ 6752 #define TIMER_A_CCTLN_CM_3 ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ 6753 #define TIMER_A_CCTLN_CM__NONE ((uint16_t)0x0000) /*!< No capture */ 6754 #define TIMER_A_CCTLN_CM__RISING ((uint16_t)0x4000) /*!< Capture on rising edge */ 6755 #define TIMER_A_CCTLN_CM__FALLING ((uint16_t)0x8000) /*!< Capture on falling edge */ 6756 #define TIMER_A_CCTLN_CM__BOTH ((uint16_t)0xC000) /*!< Capture on both rising and falling edges */ 6757 /* TIMER_A_EX0[IDEX] Bits */ 6758 #define TIMER_A_EX0_IDEX_OFS ( 0) /*!< TAIDEX Bit Offset */ 6759 #define TIMER_A_EX0_IDEX_MASK ((uint16_t)0x0007) /*!< TAIDEX Bit Mask */ 6760 #define TIMER_A_EX0_IDEX0 ((uint16_t)0x0001) /*!< IDEX Bit 0 */ 6761 #define TIMER_A_EX0_IDEX1 ((uint16_t)0x0002) /*!< IDEX Bit 1 */ 6762 #define TIMER_A_EX0_IDEX2 ((uint16_t)0x0004) /*!< IDEX Bit 2 */ 6763 #define TIMER_A_EX0_TAIDEX_0 ((uint16_t)0x0000) /*!< Divide by 1 */ 6764 #define TIMER_A_EX0_TAIDEX_1 ((uint16_t)0x0001) /*!< Divide by 2 */ 6765 #define TIMER_A_EX0_TAIDEX_2 ((uint16_t)0x0002) /*!< Divide by 3 */ 6766 #define TIMER_A_EX0_TAIDEX_3 ((uint16_t)0x0003) /*!< Divide by 4 */ 6767 #define TIMER_A_EX0_TAIDEX_4 ((uint16_t)0x0004) /*!< Divide by 5 */ 6768 #define TIMER_A_EX0_TAIDEX_5 ((uint16_t)0x0005) /*!< Divide by 6 */ 6769 #define TIMER_A_EX0_TAIDEX_6 ((uint16_t)0x0006) /*!< Divide by 7 */ 6770 #define TIMER_A_EX0_TAIDEX_7 ((uint16_t)0x0007) /*!< Divide by 8 */ 6771 #define TIMER_A_EX0_IDEX__1 ((uint16_t)0x0000) /*!< Divide by 1 */ 6772 #define TIMER_A_EX0_IDEX__2 ((uint16_t)0x0001) /*!< Divide by 2 */ 6773 #define TIMER_A_EX0_IDEX__3 ((uint16_t)0x0002) /*!< Divide by 3 */ 6774 #define TIMER_A_EX0_IDEX__4 ((uint16_t)0x0003) /*!< Divide by 4 */ 6775 #define TIMER_A_EX0_IDEX__5 ((uint16_t)0x0004) /*!< Divide by 5 */ 6776 #define TIMER_A_EX0_IDEX__6 ((uint16_t)0x0005) /*!< Divide by 6 */ 6777 #define TIMER_A_EX0_IDEX__7 ((uint16_t)0x0006) /*!< Divide by 7 */ 6778 #define TIMER_A_EX0_IDEX__8 ((uint16_t)0x0007) /*!< Divide by 8 */ 6779 6780 /****************************************************************************** 6781 * TLV Bits 6782 ******************************************************************************/ 6783 /****************************************************************************** 6784 * TLV table start and TLV tags * 6785 ******************************************************************************/ 6786 #define TLV_START_ADDR (TLV_BASE + 0x0004) /*!< Start Address of the TLV structure */ 6787 6788 #define TLV_TAG_RESERVED1 1 6789 #define TLV_TAG_RESERVED2 2 6790 #define TLV_TAG_CS 3 6791 #define TLV_TAG_FLASHCTL 4 6792 #define TLV_TAG_ADC14 5 6793 #define TLV_TAG_RESERVED6 6 6794 #define TLV_TAG_RESERVED7 7 6795 #define TLV_TAG_REF 8 6796 #define TLV_TAG_RESERVED9 9 6797 #define TLV_TAG_RESERVED10 10 6798 #define TLV_TAG_DEVINFO 11 6799 #define TLV_TAG_DIEREC 12 6800 #define TLV_TAG_RANDNUM 13 6801 #define TLV_TAG_RESERVED14 14 6802 #define TLV_TAG_BSL 15 6803 #define TLV_TAG_END (0x0BD0E11D) 6804 6805 6806 /****************************************************************************** 6807 * TPIU Bits 6808 ******************************************************************************/ 6809 6810 6811 /****************************************************************************** 6812 * WDT_A Bits 6813 ******************************************************************************/ 6814 /* WDT_A_CTL[IS] Bits */ 6815 #define WDT_A_CTL_IS_OFS ( 0) /*!< WDTIS Bit Offset */ 6816 #define WDT_A_CTL_IS_MASK ((uint16_t)0x0007) /*!< WDTIS Bit Mask */ 6817 #define WDT_A_CTL_IS0 ((uint16_t)0x0001) /*!< IS Bit 0 */ 6818 #define WDT_A_CTL_IS1 ((uint16_t)0x0002) /*!< IS Bit 1 */ 6819 #define WDT_A_CTL_IS2 ((uint16_t)0x0004) /*!< IS Bit 2 */ 6820 #define WDT_A_CTL_IS_0 ((uint16_t)0x0000) /*!< Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz) */ 6821 #define WDT_A_CTL_IS_1 ((uint16_t)0x0001) /*!< Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz) */ 6822 #define WDT_A_CTL_IS_2 ((uint16_t)0x0002) /*!< Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz) */ 6823 #define WDT_A_CTL_IS_3 ((uint16_t)0x0003) /*!< Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz) */ 6824 #define WDT_A_CTL_IS_4 ((uint16_t)0x0004) /*!< Watchdog clock source /(2^(15)) (1 s at 32.768 kHz) */ 6825 #define WDT_A_CTL_IS_5 ((uint16_t)0x0005) /*!< Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz) */ 6826 #define WDT_A_CTL_IS_6 ((uint16_t)0x0006) /*!< Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz) */ 6827 #define WDT_A_CTL_IS_7 ((uint16_t)0x0007) /*!< Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz) */ 6828 /* WDT_A_CTL[CNTCL] Bits */ 6829 #define WDT_A_CTL_CNTCL_OFS ( 3) /*!< WDTCNTCL Bit Offset */ 6830 #define WDT_A_CTL_CNTCL ((uint16_t)0x0008) /*!< Watchdog timer counter clear */ 6831 /* WDT_A_CTL[TMSEL] Bits */ 6832 #define WDT_A_CTL_TMSEL_OFS ( 4) /*!< WDTTMSEL Bit Offset */ 6833 #define WDT_A_CTL_TMSEL ((uint16_t)0x0010) /*!< Watchdog timer mode select */ 6834 /* WDT_A_CTL[SSEL] Bits */ 6835 #define WDT_A_CTL_SSEL_OFS ( 5) /*!< WDTSSEL Bit Offset */ 6836 #define WDT_A_CTL_SSEL_MASK ((uint16_t)0x0060) /*!< WDTSSEL Bit Mask */ 6837 #define WDT_A_CTL_SSEL0 ((uint16_t)0x0020) /*!< SSEL Bit 0 */ 6838 #define WDT_A_CTL_SSEL1 ((uint16_t)0x0040) /*!< SSEL Bit 1 */ 6839 #define WDT_A_CTL_SSEL_0 ((uint16_t)0x0000) /*!< SMCLK */ 6840 #define WDT_A_CTL_SSEL_1 ((uint16_t)0x0020) /*!< ACLK */ 6841 #define WDT_A_CTL_SSEL_2 ((uint16_t)0x0040) /*!< VLOCLK */ 6842 #define WDT_A_CTL_SSEL_3 ((uint16_t)0x0060) /*!< BCLK */ 6843 #define WDT_A_CTL_SSEL__SMCLK ((uint16_t)0x0000) /*!< SMCLK */ 6844 #define WDT_A_CTL_SSEL__ACLK ((uint16_t)0x0020) /*!< ACLK */ 6845 #define WDT_A_CTL_SSEL__VLOCLK ((uint16_t)0x0040) /*!< VLOCLK */ 6846 #define WDT_A_CTL_SSEL__BCLK ((uint16_t)0x0060) /*!< BCLK */ 6847 /* WDT_A_CTL[HOLD] Bits */ 6848 #define WDT_A_CTL_HOLD_OFS ( 7) /*!< WDTHOLD Bit Offset */ 6849 #define WDT_A_CTL_HOLD ((uint16_t)0x0080) /*!< Watchdog timer hold */ 6850 /* WDT_A_CTL[PW] Bits */ 6851 #define WDT_A_CTL_PW_OFS ( 8) /*!< WDTPW Bit Offset */ 6852 #define WDT_A_CTL_PW_MASK ((uint16_t)0xFF00) /*!< WDTPW Bit Mask */ 6853 /* Pre-defined bitfield values */ 6854 #define WDT_A_CTL_PW ((uint16_t)0x5A00) /*!< WDT Key Value for WDT write access */ 6855 6856 6857 /****************************************************************************** 6858 * BSL * 6859 ******************************************************************************/ 6860 #define BSL_DEFAULT_PARAM ((uint32_t)0xFC48FFFF) /*!< I2C slave address = 0x48, Interface selection = Auto */ 6861 #define BSL_API_TABLE_ADDR ((uint32_t)0x00202000) /*!< Address of BSL API table */ 6862 #define BSL_ENTRY_FUNCTION (*((uint32_t *)BSL_API_TABLE_ADDR)) 6863 6864 #define BSL_AUTO_INTERFACE ((uint32_t)0x0000E0000) /*!< Auto detect interface */ 6865 #define BSL_UART_INTERFACE ((uint32_t)0x0000C0000) /*!< UART interface */ 6866 #define BSL_SPI_INTERFACE ((uint32_t)0x0000A0000) /*!< SPI interface */ 6867 #define BSL_I2C_INTERFACE ((uint32_t)0x000080000) /*!< I2C interface */ 6868 6869 #define BSL_INVOKE(x) ((void (*)())BSL_ENTRY_FUNCTION)((uint32_t) x) /*!< Invoke the BSL with parameters */ 6870 6871 6872 /****************************************************************************** 6873 * Mailbox struct legacy definition * 6874 ******************************************************************************/ 6875 #define FLASH_MAILBOX_Type FL_BOOTOVER_MAILBOX_Type 6876 6877 /****************************************************************************** 6878 * Device Unlock Support * 6879 ******************************************************************************/ 6880 /* unlock the device by: 6881 * Load SYSCTL_SECDATA_UNLOCK register address into R0 6882 * Load SYSCTL_SECDATA_UNLOCK unlock key into R1 6883 * Write the unlock key to the SYSCTL_SECDATA_UNLOCK register 6884 */ 6885 #define UNLOCK_DEVICE\ 6886 __asm(" MOVW.W R0, #0x3040");\ 6887 __asm(" MOVT.W R0, #0xE004");\ 6888 __asm(" MOVW.W R1, #0x695A");\ 6889 __asm(" MOVT.W R1, #0x0000");\ 6890 __asm(" STR R1, [R0]"); 6891 6892 /****************************************************************************** 6893 * 6894 * The following are values that can be used to choose the command that will be 6895 * run by the boot code. Perform a logical OR of these settings to create your 6896 * general parameter command. 6897 * 6898 ******************************************************************************/ 6899 #define COMMAND_FACTORY_RESET ((uint32_t)0x00010000) 6900 #define COMMAND_BSL_CONFIG ((uint32_t)0x00020000) 6901 #define COMMAND_JTAG_SWD_LOCK_SECEN ((uint32_t)0x00080000) 6902 #define COMMAND_SEC_ZONE0_EN ((uint32_t)0x00100000) 6903 #define COMMAND_SEC_ZONE1_EN ((uint32_t)0x00200000) 6904 #define COMMAND_SEC_ZONE2_EN ((uint32_t)0x00400000) 6905 #define COMMAND_SEC_ZONE3_EN ((uint32_t)0x00800000) 6906 #define COMMAND_SEC_ZONE0_UPDATE ((uint32_t)0x01000000) 6907 #define COMMAND_SEC_ZONE1_UPDATE ((uint32_t)0x02000000) 6908 #define COMMAND_SEC_ZONE2_UPDATE ((uint32_t)0x04000000) 6909 #define COMMAND_SEC_ZONE3_UPDATE ((uint32_t)0x08000000) 6910 #define COMMAND_JTAG_SWD_LOCK_ENC_UPDATE ((uint32_t)0x10000000) 6911 #define COMMAND_NONE ((uint32_t)0xFFFFFFFF) 6912 6913 /****************************************************************************** 6914 * 6915 * The following are values that can be used to configure the BSL. Perform a 6916 * logical OR of these settings to create your BSL parameter. 6917 * 6918 ******************************************************************************/ 6919 #define BSL_CONFIG_HW_INVOKE ((uint32_t)0x70000000) 6920 6921 #define BSL_CONFIG_HW_INVOKE_PORT1 ((uint32_t)0x00000000) 6922 #define BSL_CONFIG_HW_INVOKE_PORT2 ((uint32_t)0x00000001) 6923 #define BSL_CONFIG_HW_INVOKE_PORT3 ((uint32_t)0x00000002) 6924 6925 #define BSL_CONFIG_HW_INVOKE_PIN0 ((uint32_t)0x00000000) 6926 #define BSL_CONFIG_HW_INVOKE_PIN1 ((uint32_t)0x00000010) 6927 #define BSL_CONFIG_HW_INVOKE_PIN2 ((uint32_t)0x00000020) 6928 #define BSL_CONFIG_HW_INVOKE_PIN3 ((uint32_t)0x00000030) 6929 #define BSL_CONFIG_HW_INVOKE_PIN4 ((uint32_t)0x00000040) 6930 #define BSL_CONFIG_HW_INVOKE_PIN5 ((uint32_t)0x00000050) 6931 #define BSL_CONFIG_HW_INVOKE_PIN6 ((uint32_t)0x00000060) 6932 #define BSL_CONFIG_HW_INVOKE_PIN7 ((uint32_t)0x00000070) 6933 6934 #define BSL_CONFIG_HW_INVOKE_PIN_LOW ((uint32_t)0x00000000) 6935 #define BSL_CONFIG_HW_INVOKE_PIN_HIGH ((uint32_t)0x00001000) 6936 6937 #define BSL_CONFIG_INTERFACE_I2C ((uint32_t)0x00008000) 6938 #define BSL_CONFIG_INTERFACE_SPI ((uint32_t)0x0000A000) 6939 #define BSL_CONFIG_INTERFACE_UART ((uint32_t)0x0000C000) 6940 #define BSL_CONFIG_INTERFACE_AUTO ((uint32_t)0x0000E000) 6941 6942 #define BSL_CONFIG_I2C_ADD_OFFSET (16) 6943 6944 6945 /****************************************************************************** 6946 * ULP Advisor * 6947 ******************************************************************************/ 6948 #ifdef __TI_ARM__ 6949 #pragma ULP_PORT_CONFIG(1,DIR={0x40004C04,8},OUT={0x40004C02,8},SEL1={0x40004C0A,8},SEL2={0x40004C0C,8}) 6950 #pragma ULP_PORT_CONFIG(2,DIR={0x40004C05,8},OUT={0x40004C03,8},SEL1={0x40004C0B,8},SEL2={0x40004C0D,8}) 6951 #pragma ULP_PORT_CONFIG(3,DIR={0x40004C24,8},OUT={0x40004C22,8},SEL1={0x40004C2A,8},SEL2={0x40004C2C,8}) 6952 #pragma ULP_PORT_CONFIG(4,DIR={0x40004C25,8},OUT={0x40004C23,8},SEL1={0x40004C2B,8},SEL2={0x40004C2D,8}) 6953 #pragma ULP_PORT_CONFIG(5,DIR={0x40004C44,8},OUT={0x40004C42,8},SEL1={0x40004C4A,8},SEL2={0x40004C4C,8}) 6954 #pragma ULP_PORT_CONFIG(6,DIR={0x40004C45,8},OUT={0x40004C43,8},SEL1={0x40004C4B,8},SEL2={0x40004C4D,8}) 6955 #pragma ULP_PORT_CONFIG(7,DIR={0x40004C64,8},OUT={0x40004C62,8},SEL1={0x40004C6A,8},SEL2={0x40004C6C,8}) 6956 #pragma ULP_PORT_CONFIG(8,DIR={0x40004C65,8},OUT={0x40004C63,8},SEL1={0x40004C6B,8},SEL2={0x40004C6D,8}) 6957 #pragma ULP_PORT_CONFIG(9,DIR={0x40004C84,8},OUT={0x40004C82,8},SEL1={0x40004C8A,8},SEL2={0x40004C8C,8}) 6958 #pragma ULP_PORT_CONFIG(10,DIR={0x40004C85,8},OUT={0x40004C83,8},SEL1={0x40004C8B,8},SEL2={0x40004C8D,8}) 6959 #endif 6960 6961 6962 #ifdef __cplusplus 6963 } 6964 #endif 6965 6966 #endif /* __MSP432P401R_H__ */ 6967 6968