1# Multiple Processor (MP) Initialization 2 3This section is intended to document the purpose of performing multiprocessor 4initialization and its possible ways in coreboot space. 5 6Entire CPU multiprocessor initialization can be divided into two parts 71. BSP (Boot Strap Processor) Initialization 82. AP (Application Processor) Initialization 9 10* [Multiple Processor Init](https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-vol-3a-part-1-manual.pdf) - section 8.4 11 12## Problem Statement 13 141. coreboot is capable enough to handle multiprocessor initialization on 15IA platforms. 16 172. With restricted CPU programming logic, there might be some cases where 18certain feature programming can't be open sourced at early development of SOC. 19 20Platform code might need to compromise on those closed source nature of CPU 21programming if we don't plan to provide an alternate interface which can be 22used by coreboot to get rid of such close sourced CPU programming. 23 24## Possible Solution Space 25 26Considering these facts, there are 3 possible solutions to perform MP 27initialization from coreboot + FSP space. 28 291. coreboot to perform complete MP initialization by its own. This includes 30BSP and AP programming of CPU features mostly non-restricted one. This is 31the default configuration. Most SoCs like SKL, KBL, APL are okay to make use 32of this MP initialization method. 33 342. Alternatively, SoC users also can skip coreboot doing MP initialization 35and make use of FSP binary to perform same task. This can be achieved by using 36Kconfig name USE_INTEL_FSP_MP_INIT. As of 2019 all Google Chrome products are 37using coreboot native MP initialization mechanism and some IOTG platforms 38are using FSP MP Init solution as well. 39 403. Final option is to let coreboot publish PPI (PEIM to PEIM Interface) to 41perform some restricted (closed source) CPU programming. In that case, 42coreboot will use its native MP init and additionally publish MP service PPI 43for FSP to consume. FSP will execute some CPU programming using same PPI 44service from its own context. One can use 45USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI Kconfig to perform this 46operation. 47 48For latest SoCs like CNL, WHL, ICL, etc, its recommended to make use of this 49option in order to perform SGX and C6DRAM enabling. 50 51Typically all platforms supported by FSP 2.1 specification will have 52external PPI service feature implemented. 53 54## References 55```{toctree} 56:maxdepth: 1 57 58PPI <../fsp/ppi/ppi.md> 59MP Service PPI <../fsp/ppi/mp_service_ppi.md> 60``` 61