1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <console/console.h>
4 #include <device/device.h>
5 #include <cpu/cpu.h>
6 #include <cpu/x86/mtrr.h>
7 #include <cpu/x86/msr.h>
8 #include <cpu/x86/mp.h>
9 #include <cpu/intel/microcode.h>
10 #include <cpu/intel/speedstep.h>
11 #include <cpu/intel/turbo.h>
12 #include <cpu/x86/cache.h>
13 #include <cpu/x86/name.h>
14 #include "commonlib/bsd/helpers.h"
15 #include "model_206ax.h"
16 #include "chip.h"
17 #include <cpu/intel/smm_reloc.h>
18 #include <cpu/intel/common/common.h>
19 #include <smbios.h>
20 #include <smp/node.h>
21 #include <types.h>
22
23 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
24 static const u8 power_limit_time_sec_to_msr[] = {
25 [0] = 0x00,
26 [1] = 0x0a,
27 [2] = 0x0b,
28 [3] = 0x4b,
29 [4] = 0x0c,
30 [5] = 0x2c,
31 [6] = 0x4c,
32 [7] = 0x6c,
33 [8] = 0x0d,
34 [10] = 0x2d,
35 [12] = 0x4d,
36 [14] = 0x6d,
37 [16] = 0x0e,
38 [20] = 0x2e,
39 [24] = 0x4e,
40 [28] = 0x6e,
41 [32] = 0x0f,
42 [40] = 0x2f,
43 [48] = 0x4f,
44 [56] = 0x6f,
45 [64] = 0x10,
46 [80] = 0x30,
47 [96] = 0x50,
48 [112] = 0x70,
49 [128] = 0x11,
50 };
51
52 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
53 static const u8 power_limit_time_msr_to_sec[] = {
54 [0x00] = 0,
55 [0x0a] = 1,
56 [0x0b] = 2,
57 [0x4b] = 3,
58 [0x0c] = 4,
59 [0x2c] = 5,
60 [0x4c] = 6,
61 [0x6c] = 7,
62 [0x0d] = 8,
63 [0x2d] = 10,
64 [0x4d] = 12,
65 [0x6d] = 14,
66 [0x0e] = 16,
67 [0x2e] = 20,
68 [0x4e] = 24,
69 [0x6e] = 28,
70 [0x0f] = 32,
71 [0x2f] = 40,
72 [0x4f] = 48,
73 [0x6f] = 56,
74 [0x10] = 64,
75 [0x30] = 80,
76 [0x50] = 96,
77 [0x70] = 112,
78 [0x11] = 128,
79 };
80
cpu_config_tdp_levels(void)81 int cpu_config_tdp_levels(void)
82 {
83 msr_t platform_info;
84
85 /* Minimum CPU revision */
86 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
87 return 0;
88
89 /* Bits 34:33 indicate how many levels supported */
90 platform_info = rdmsr(MSR_PLATFORM_INFO);
91 return (platform_info.hi >> 1) & 3;
92 }
93
94 /*
95 * Configure processor power limits if possible
96 * This must be done AFTER set of BIOS_RESET_CPL
97 */
set_power_limits(u8 power_limit_1_time)98 void set_power_limits(u8 power_limit_1_time)
99 {
100 struct cpu_intel_model_206ax_config *conf = DEV_PTR(cpu_bus)->chip_info;
101 msr_t msr = rdmsr(MSR_PLATFORM_INFO);
102 msr_t limit;
103 unsigned int power_unit;
104 unsigned int tdp, min_power, max_power, max_time;
105 u8 power_limit_1_val;
106
107 if (power_limit_1_time >= ARRAY_SIZE(power_limit_time_sec_to_msr))
108 return;
109
110 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
111 return;
112
113 /* Get units */
114 msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
115 power_unit = 2 << ((msr.lo & 0xf) - 1);
116
117 /* Get power defaults for this SKU */
118 msr = rdmsr(MSR_PKG_POWER_SKU);
119 tdp = msr.lo & 0x7fff;
120 min_power = (msr.lo >> 16) & 0x7fff;
121 max_power = msr.hi & 0x7fff;
122 max_time = (msr.hi >> 16) & 0x7f;
123
124 printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
125
126 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
127 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
128
129 if (min_power > 0 && tdp < min_power)
130 tdp = min_power;
131
132 if (max_power > 0 && tdp > max_power)
133 tdp = max_power;
134
135 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
136
137 limit.lo = 0;
138 if (conf->pl1_mw) {
139 printk(BIOS_DEBUG, "Setting PL1 to %u milliwatts\n", conf->pl1_mw);
140 limit.lo |= ((conf->pl1_mw * power_unit) / 1000) & PKG_POWER_LIMIT_MASK;
141 } else {
142 /* Set long term power limit to TDP */
143 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
144 }
145 if (conf->pl2_clamp) {
146 printk(BIOS_DEBUG, "Enabling PL1 clamping limitation\n");
147 limit.lo |= PKG_POWER_LIMIT_CLAMP;
148 }
149 limit.lo |= PKG_POWER_LIMIT_EN;
150 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
151 PKG_POWER_LIMIT_TIME_SHIFT;
152
153 limit.hi = 0;
154 if (conf->pl2_mw) {
155 printk(BIOS_DEBUG, "Setting PL2 to %u milliwatts\n", conf->pl2_mw);
156 limit.hi |= ((conf->pl2_mw * power_unit) / 1000) & PKG_POWER_LIMIT_MASK;
157 } else {
158 /* Set short term power limit to 1.25 * TDP */
159 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
160 }
161 if (conf->pl2_clamp) {
162 printk(BIOS_DEBUG, "Enabling PL2 clamping limitation\n");
163 limit.hi |= PKG_POWER_LIMIT_CLAMP;
164 }
165 limit.hi |= PKG_POWER_LIMIT_EN;
166 /* Power limit 2 time is only programmable on SNB EP/EX */
167
168 wrmsr(MSR_PKG_POWER_LIMIT, limit);
169
170 /* Use nominal TDP values for CPUs with configurable TDP */
171 if (cpu_config_tdp_levels()) {
172 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
173 limit.hi = 0;
174 limit.lo = msr.lo & 0xff;
175 wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
176 }
177 }
178
configure_turbo_ratio_limits(struct cpu_intel_model_206ax_config * conf)179 static void configure_turbo_ratio_limits(struct cpu_intel_model_206ax_config *conf)
180 {
181 msr_t msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
182
183 for (int i = 0; i < ARRAY_SIZE(conf->turbo_limits.raw); i++) {
184 const int shift = i * 8;
185 const int limit = conf->turbo_limits.raw[i];
186
187 if (limit) {
188 msr.lo &= ~(0xff << shift);
189 msr.lo |= (limit << shift);
190 }
191 }
192
193 wrmsr(MSR_TURBO_RATIO_LIMIT, msr);
194 }
195
configure_c_states(struct device * dev)196 static void configure_c_states(struct device *dev)
197 {
198 struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->chip_info;
199 msr_t msr;
200
201 msr = rdmsr(MSR_PKG_CST_CONFIG_CONTROL);
202 msr.lo |= (1 << 28); // C1 Auto Undemotion Enable
203 msr.lo |= (1 << 27); // C3 Auto Undemotion Enable
204 msr.lo |= (1 << 26); // C1 Auto Demotion Enable
205 msr.lo |= (1 << 25); // C3 Auto Demotion Enable
206 msr.lo &= ~(1 << 10); // Disable IO MWAIT redirection
207 msr.lo |= 7; // No package C-state limit
208
209 msr.lo |= (1 << 15); // Lock C-State MSR
210 wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);
211
212 if (boot_cpu()) {
213 /*
214 * The following MSRs are in scope 'Package', thus it's sufficient
215 * to write them once on one core.
216 */
217
218 msr = rdmsr(MSR_MISC_PWR_MGMT);
219 msr.lo &= ~(1 << 0); // Enable P-state HW_ALL coordination
220 wrmsr(MSR_MISC_PWR_MGMT, msr);
221
222 msr = rdmsr(MSR_POWER_CTL);
223 msr.lo |= (1 << 18); // Enable Energy Perf Bias MSR 0x1b0
224 msr.lo |= (1 << 1); // C1E Enable
225 msr.lo |= (1 << 0); // Bi-directional PROCHOT#
226 wrmsr(MSR_POWER_CTL, msr);
227
228 /* C3 Interrupt Response Time Limit */
229 msr.hi = 0;
230 if (IS_IVY_CPU(cpu_get_cpuid()))
231 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x3b;
232 else
233 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
234 wrmsr(MSR_PKGC3_IRTL, msr);
235
236 /* C6 Interrupt Response Time Limit */
237 msr.hi = 0;
238 if (IS_IVY_CPU(cpu_get_cpuid()))
239 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
240 else
241 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
242 wrmsr(MSR_PKGC6_IRTL, msr);
243
244 /* C7 Interrupt Response Time Limit */
245 msr.hi = 0;
246 if (IS_IVY_CPU(cpu_get_cpuid()))
247 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x57;
248 else
249 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
250 wrmsr(MSR_PKGC7_IRTL, msr);
251
252 /* Primary Plane Current Limit (Icc) */
253 msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
254 msr.lo &= ~0x1fff;
255 if (conf->pp0_current_limit) {
256 /* Fill in board specific maximum current supported by VR */
257 msr.lo |= conf->pp0_current_limit * 8;
258 } else {
259 printk(BIOS_INFO, "%s: PP0 current limit not set in devicetree\n", dev_path(dev));
260 /*
261 * The default value might over-stress the voltage regulator or
262 * prevent OC on boards with regulators that can handle currents
263 * above the Intel recommendation.
264 */
265 msr.lo |= PP0_CURRENT_LIMIT;
266 }
267 for (int i = 0; i < VR12_PSI_MAX; i++) {
268 /*
269 * Light load optimization. Depending on the VR output filter the
270 * number of phases can be reduced at light load. This is a board
271 * specific setting.
272 */
273 if (conf->pp0_psi[i].phases != VR12_KEEP_DEFAULT) {
274 msr.hi &= ~(0x3ff << (i * 10));
275 msr.hi |= (conf->pp0_psi[i].phases - 1) << (i * 10 + 7);
276 msr.hi |= conf->pp0_psi[i].current << (i * 10);
277 } else {
278 printk(BIOS_INFO, "%s: PP0 PSI%d not set in devicetree\n", dev_path(dev), i);
279 }
280 }
281 msr.lo |= PP0_CURRENT_LIMIT_LOCK;
282 wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
283
284 /* Secondary Plane Current Limit (IAXG) */
285 msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
286 msr.lo &= ~0x1fff;
287 if (conf->pp1_current_limit) {
288 /* Fill in board specific maximum current supported by VR */
289 msr.lo |= conf->pp1_current_limit * 8;
290 } else {
291 printk(BIOS_INFO, "%s: PP1 current limit not set in devicetree\n", dev_path(dev));
292 /*
293 * The default value might over-stress the voltage regulator or
294 * prevent OC on boards with regulators that can handle currents
295 * above the Intel recommendation.
296 */
297 if (IS_IVY_CPU(cpu_get_cpuid()))
298 msr.lo |= PP1_CURRENT_LIMIT_IVB;
299 else
300 msr.lo |= PP1_CURRENT_LIMIT_SNB;
301 }
302 for (int i = 0; i < VR12_PSI_MAX; i++) {
303 /*
304 * Light load optimization. Depending on the VR output filter the
305 * number of phases can be reduced at light load. This is a board
306 * specific setting.
307 */
308 if (conf->pp1_psi[i].phases != VR12_KEEP_DEFAULT) {
309 msr.hi &= ~(0x3ff << (i * 10));
310 msr.hi |= (conf->pp1_psi[i].phases - 1) << (i * 10 + 7);
311 msr.hi |= conf->pp1_psi[i].current << (i * 10);
312 } else {
313 printk(BIOS_INFO, "%s: PP1 PSI%d not set in devicetree\n", dev_path(dev), i);
314 }
315 }
316 msr.lo |= PP1_CURRENT_LIMIT_LOCK;
317 wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
318 }
319
320 msr = rdmsr(MSR_PLATFORM_INFO);
321 if (msr.lo & PLATFORM_INFO_SET_TURBO_LIMIT) {
322 configure_turbo_ratio_limits(conf);
323 } else {
324 printk(BIOS_INFO, "%s: Programmable ratio limit for turbo mode is disabled\n",
325 dev_path(dev));
326 }
327 }
328
configure_thermal_target(struct device * dev)329 static void configure_thermal_target(struct device *dev)
330 {
331 struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->chip_info;
332 msr_t msr;
333
334 if (boot_cpu()) {
335 /*
336 * The following MSR is in scope 'Package', thus it's sufficient
337 * to write it once on one core.
338 */
339
340 /* Set TCC activation offset if supported */
341 msr = rdmsr(MSR_PLATFORM_INFO);
342 if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
343 msr = rdmsr(MSR_TEMPERATURE_TARGET);
344 msr.lo &= ~(0xf << 24); /* Bits 27:24 */
345 msr.lo |= (conf->tcc_offset & 0xf) << 24;
346 wrmsr(MSR_TEMPERATURE_TARGET, msr);
347 }
348 }
349 }
350
configure_misc(void)351 static void configure_misc(void)
352 {
353 msr_t msr;
354
355 msr = rdmsr(IA32_MISC_ENABLE);
356 msr.lo |= (1 << 0); /* Fast String enable */
357 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
358 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
359 wrmsr(IA32_MISC_ENABLE, msr);
360
361 /* Disable Thermal interrupts */
362 msr.lo = 0;
363 msr.hi = 0;
364 wrmsr(IA32_THERM_INTERRUPT, msr);
365
366 if (boot_cpu()) {
367 /*
368 * The following MSR is in scope 'Package', thus it's sufficient
369 * to write it once on one core.
370 */
371
372 /* Enable package critical interrupt only */
373 msr.lo = 1 << 4;
374 msr.hi = 0;
375 wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
376 }
377 }
378
set_max_ratio(void)379 static void set_max_ratio(void)
380 {
381 msr_t msr, perf_ctl;
382
383 perf_ctl.hi = 0;
384
385 /* Check for configurable TDP option */
386 if (cpu_config_tdp_levels()) {
387 /* Set to nominal TDP ratio */
388 msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
389 perf_ctl.lo = (msr.lo & 0xff) << 8;
390 } else {
391 /* Platform Info bits 15:8 give max ratio */
392 msr = rdmsr(MSR_PLATFORM_INFO);
393 perf_ctl.lo = msr.lo & 0xff00;
394 }
395 wrmsr(IA32_PERF_CTL, perf_ctl);
396
397 printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
398 ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
399 }
400
smbios_cpu_get_max_speed_mhz(void)401 unsigned int smbios_cpu_get_max_speed_mhz(void)
402 {
403 msr_t msr;
404 msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
405 return (msr.lo & 0xff) * SANDYBRIDGE_BCLK;
406 }
407
smbios_cpu_get_current_speed_mhz(void)408 unsigned int smbios_cpu_get_current_speed_mhz(void)
409 {
410 msr_t msr;
411 msr = rdmsr(MSR_PLATFORM_INFO);
412 return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK;
413 }
414
smbios_processor_external_clock(void)415 unsigned int smbios_processor_external_clock(void)
416 {
417 return SANDYBRIDGE_BCLK;
418 }
419
model_206ax_report(void)420 static void model_206ax_report(void)
421 {
422 static const char *const mode[] = {"NOT ", ""};
423 char processor_name[49];
424 int vt, txt, aes;
425 uint32_t cpu_id, cpu_feature_flag;
426
427 /* Print processor name */
428 fill_processor_name(processor_name);
429 printk(BIOS_INFO, "CPU: %s.\n", processor_name);
430
431 /* CPUID and features */
432 cpu_id = cpu_get_cpuid();
433 printk(BIOS_INFO, "CPU: cpuid(1) 0x%x\n", cpu_id);
434
435 cpu_feature_flag = cpu_get_feature_flags_ecx();
436 aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
437 txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
438 vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
439 printk(BIOS_INFO, "CPU: AES %ssupported\n", mode[aes]);
440 printk(BIOS_INFO, "CPU: TXT %ssupported\n", mode[txt]);
441 printk(BIOS_INFO, "CPU: VT %ssupported\n", mode[vt]);
442 }
443
model_206ax_init(struct device * cpu)444 static void model_206ax_init(struct device *cpu)
445 {
446 /* Clear out pending MCEs */
447 /* This should only be done on a cold boot */
448 mca_clear_status();
449
450 /* Print infos */
451 model_206ax_report();
452
453 /* Setup Page Attribute Tables (PAT) */
454 // TODO set up PAT
455
456 enable_lapic_tpr();
457
458 /* Set virtualization based on Kconfig option */
459 set_vmx_and_lock();
460
461 /* Configure C States */
462 configure_c_states(cpu);
463
464 /* Configure Enhanced SpeedStep and Thermal Sensors */
465 configure_misc();
466
467 /* Thermal throttle activation offset */
468 configure_thermal_target(cpu);
469
470 set_aesni_lock();
471
472 /* Enable Direct Cache Access */
473 configure_dca_cap();
474
475 /* Set energy policy */
476 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
477
478 /* Set Max Ratio */
479 set_max_ratio();
480
481 /* Enable Turbo */
482 enable_turbo();
483 }
484
485 /* MP initialization support. */
pre_mp_init(void)486 static void pre_mp_init(void)
487 {
488 /* Setup MTRRs based on physical address size. */
489 x86_setup_mtrrs_with_detect();
490 x86_mtrr_check();
491 }
492
get_cpu_count(void)493 static int get_cpu_count(void)
494 {
495 msr_t msr;
496 unsigned int num_threads;
497 unsigned int num_cores;
498
499 msr = rdmsr(MSR_CORE_THREAD_COUNT);
500 num_threads = (msr.lo >> 0) & 0xffff;
501 num_cores = (msr.lo >> 16) & 0xffff;
502 printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",
503 num_cores, num_threads);
504
505 return num_threads;
506 }
507
get_microcode_info(const void ** microcode,int * parallel)508 static void get_microcode_info(const void **microcode, int *parallel)
509 {
510 *microcode = intel_microcode_find();
511 *parallel = !intel_ht_supported();
512 }
513
per_cpu_smm_trigger(void)514 static void per_cpu_smm_trigger(void)
515 {
516 /* Relocate the SMM handler. */
517 smm_relocate();
518
519 /* After SMM relocation a 2nd microcode load is required. */
520 const void *microcode_patch = intel_microcode_find();
521 intel_microcode_load_unlocked(microcode_patch);
522 }
523
post_mp_init(void)524 static void post_mp_init(void)
525 {
526 /* Now that all APs have been relocated as well as the BSP let SMIs
527 * start flowing. */
528 global_smi_enable();
529
530 /* Lock down the SMRAM space. */
531 smm_lock();
532 }
533
534 static const struct mp_ops mp_ops = {
535 .pre_mp_init = pre_mp_init,
536 .get_cpu_count = get_cpu_count,
537 .get_smm_info = smm_info,
538 .get_microcode_info = get_microcode_info,
539 .pre_mp_smm_init = smm_initialize,
540 .per_cpu_smm_trigger = per_cpu_smm_trigger,
541 .relocation_handler = smm_relocation_handler,
542 .post_mp_init = post_mp_init,
543 };
544
mp_init_cpus(struct bus * cpu_bus)545 void mp_init_cpus(struct bus *cpu_bus)
546 {
547 /* TODO: Handle mp_init_with_smm failure? */
548 mp_init_with_smm(cpu_bus, &mp_ops);
549 }
550
551 static struct device_operations cpu_dev_ops = {
552 .init = model_206ax_init,
553 };
554
555 static const struct cpu_device_id cpu_table[] = {
556 { X86_VENDOR_INTEL, 0x206a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel Sandybridge */
557 { X86_VENDOR_INTEL, 0x306a0, CPUID_ALL_STEPPINGS_MASK }, /* Intel IvyBridge */
558 CPU_TABLE_END
559 };
560
561 static const struct cpu_driver driver __cpu_driver = {
562 .ops = &cpu_dev_ops,
563 .id_table = cpu_table,
564 };
565