1 /* 2 * Copyright 2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _mmhub_3_3_0_OFFSET_HEADER 24 #define _mmhub_3_3_0_OFFSET_HEADER 25 26 27 28 // addressBlock: mmhub_dagbdec 29 // base address: 0x68000 30 #define regDAGB0_RDCLI0 0x0000 31 #define regDAGB0_RDCLI0_BASE_IDX 1 32 #define regDAGB0_RDCLI1 0x0001 33 #define regDAGB0_RDCLI1_BASE_IDX 1 34 #define regDAGB0_RDCLI2 0x0002 35 #define regDAGB0_RDCLI2_BASE_IDX 1 36 #define regDAGB0_RDCLI3 0x0003 37 #define regDAGB0_RDCLI3_BASE_IDX 1 38 #define regDAGB0_RDCLI4 0x0004 39 #define regDAGB0_RDCLI4_BASE_IDX 1 40 #define regDAGB0_RDCLI5 0x0005 41 #define regDAGB0_RDCLI5_BASE_IDX 1 42 #define regDAGB0_RDCLI6 0x0006 43 #define regDAGB0_RDCLI6_BASE_IDX 1 44 #define regDAGB0_RDCLI7 0x0007 45 #define regDAGB0_RDCLI7_BASE_IDX 1 46 #define regDAGB0_RDCLI8 0x0008 47 #define regDAGB0_RDCLI8_BASE_IDX 1 48 #define regDAGB0_RDCLI9 0x0009 49 #define regDAGB0_RDCLI9_BASE_IDX 1 50 #define regDAGB0_RDCLI10 0x000a 51 #define regDAGB0_RDCLI10_BASE_IDX 1 52 #define regDAGB0_RDCLI11 0x000b 53 #define regDAGB0_RDCLI11_BASE_IDX 1 54 #define regDAGB0_RDCLI12 0x000c 55 #define regDAGB0_RDCLI12_BASE_IDX 1 56 #define regDAGB0_RDCLI13 0x000d 57 #define regDAGB0_RDCLI13_BASE_IDX 1 58 #define regDAGB0_RDCLI14 0x000e 59 #define regDAGB0_RDCLI14_BASE_IDX 1 60 #define regDAGB0_RDCLI15 0x000f 61 #define regDAGB0_RDCLI15_BASE_IDX 1 62 #define regDAGB0_RDCLI16 0x0010 63 #define regDAGB0_RDCLI16_BASE_IDX 1 64 #define regDAGB0_RDCLI17 0x0011 65 #define regDAGB0_RDCLI17_BASE_IDX 1 66 #define regDAGB0_RDCLI18 0x0012 67 #define regDAGB0_RDCLI18_BASE_IDX 1 68 #define regDAGB0_RDCLI19 0x0013 69 #define regDAGB0_RDCLI19_BASE_IDX 1 70 #define regDAGB0_RDCLI20 0x0014 71 #define regDAGB0_RDCLI20_BASE_IDX 1 72 #define regDAGB0_RDCLI21 0x0015 73 #define regDAGB0_RDCLI21_BASE_IDX 1 74 #define regDAGB0_RDCLI22 0x0016 75 #define regDAGB0_RDCLI22_BASE_IDX 1 76 #define regDAGB0_RDCLI23 0x0017 77 #define regDAGB0_RDCLI23_BASE_IDX 1 78 #define regDAGB0_RDCLI24 0x0018 79 #define regDAGB0_RDCLI24_BASE_IDX 1 80 #define regDAGB0_RDCLI25 0x0019 81 #define regDAGB0_RDCLI25_BASE_IDX 1 82 #define regDAGB0_RDCLI26 0x001a 83 #define regDAGB0_RDCLI26_BASE_IDX 1 84 #define regDAGB0_RDCLI27 0x001b 85 #define regDAGB0_RDCLI27_BASE_IDX 1 86 #define regDAGB0_RDCLI28 0x001c 87 #define regDAGB0_RDCLI28_BASE_IDX 1 88 #define regDAGB0_RDCLI29 0x001d 89 #define regDAGB0_RDCLI29_BASE_IDX 1 90 #define regDAGB0_RDCLI30 0x001e 91 #define regDAGB0_RDCLI30_BASE_IDX 1 92 #define regDAGB0_RD_CNTL 0x001f 93 #define regDAGB0_RD_CNTL_BASE_IDX 1 94 #define regDAGB0_RD_IO_CNTL 0x0020 95 #define regDAGB0_RD_IO_CNTL_BASE_IDX 1 96 #define regDAGB0_RD_GMI_CNTL 0x0021 97 #define regDAGB0_RD_GMI_CNTL_BASE_IDX 1 98 #define regDAGB0_RD_ADDR_DAGB 0x0022 99 #define regDAGB0_RD_ADDR_DAGB_BASE_IDX 1 100 #define regDAGB0_RD_CGTT_CLK_CTRL 0x0023 101 #define regDAGB0_RD_CGTT_CLK_CTRL_BASE_IDX 1 102 #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL 0x0024 103 #define regDAGB0_L1TLB_RD_CGTT_CLK_CTRL_BASE_IDX 1 104 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0 0x0025 105 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 106 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0 0x0026 107 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 108 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1 0x0027 109 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 110 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1 0x0028 111 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 112 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST2 0x0029 113 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 114 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2 0x002a 115 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 116 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST3 0x002b 117 #define regDAGB0_RD_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 118 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3 0x002c 119 #define regDAGB0_RD_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 120 #define regDAGB0_RD_VC0_CNTL 0x002d 121 #define regDAGB0_RD_VC0_CNTL_BASE_IDX 1 122 #define regDAGB0_RD_VC1_CNTL 0x002e 123 #define regDAGB0_RD_VC1_CNTL_BASE_IDX 1 124 #define regDAGB0_RD_VC2_CNTL 0x002f 125 #define regDAGB0_RD_VC2_CNTL_BASE_IDX 1 126 #define regDAGB0_RD_VC3_CNTL 0x0030 127 #define regDAGB0_RD_VC3_CNTL_BASE_IDX 1 128 #define regDAGB0_RD_VC4_CNTL 0x0031 129 #define regDAGB0_RD_VC4_CNTL_BASE_IDX 1 130 #define regDAGB0_RD_VC5_CNTL 0x0032 131 #define regDAGB0_RD_VC5_CNTL_BASE_IDX 1 132 #define regDAGB0_RD_IO_VC_CNTL 0x0033 133 #define regDAGB0_RD_IO_VC_CNTL_BASE_IDX 1 134 #define regDAGB0_RD_GMI_VC_CNTL 0x0034 135 #define regDAGB0_RD_GMI_VC_CNTL_BASE_IDX 1 136 #define regDAGB0_RD_CNTL_MISC 0x0035 137 #define regDAGB0_RD_CNTL_MISC_BASE_IDX 1 138 #define regDAGB0_RD_TLB_CREDIT 0x0036 139 #define regDAGB0_RD_TLB_CREDIT_BASE_IDX 1 140 #define regDAGB0_RDCLI_ASK_PENDING 0x0037 141 #define regDAGB0_RDCLI_ASK_PENDING_BASE_IDX 1 142 #define regDAGB0_RDCLI_GO_PENDING 0x0038 143 #define regDAGB0_RDCLI_GO_PENDING_BASE_IDX 1 144 #define regDAGB0_RDCLI_GBLSEND_PENDING 0x0039 145 #define regDAGB0_RDCLI_GBLSEND_PENDING_BASE_IDX 1 146 #define regDAGB0_RDCLI_TLB_PENDING 0x003a 147 #define regDAGB0_RDCLI_TLB_PENDING_BASE_IDX 1 148 #define regDAGB0_RDCLI_OARB_PENDING 0x003b 149 #define regDAGB0_RDCLI_OARB_PENDING_BASE_IDX 1 150 #define regDAGB0_RDCLI_ASK2ARB_PENDING 0x003c 151 #define regDAGB0_RDCLI_ASK2ARB_PENDING_BASE_IDX 1 152 #define regDAGB0_RDCLI_ASK2DF_PENDING 0x003d 153 #define regDAGB0_RDCLI_ASK2DF_PENDING_BASE_IDX 1 154 #define regDAGB0_RDCLI_OSD_PENDING 0x003e 155 #define regDAGB0_RDCLI_OSD_PENDING_BASE_IDX 1 156 #define regDAGB0_RDCLI_ASK_OSD_PENDING 0x003f 157 #define regDAGB0_RDCLI_ASK_OSD_PENDING_BASE_IDX 1 158 #define regDAGB0_RDCLI_NOALLOC_OVERRIDE 0x0040 159 #define regDAGB0_RDCLI_NOALLOC_OVERRIDE_BASE_IDX 1 160 #define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE 0x0041 161 #define regDAGB0_RDCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 1 162 #define regDAGB0_WRCLI0 0x0042 163 #define regDAGB0_WRCLI0_BASE_IDX 1 164 #define regDAGB0_WRCLI1 0x0043 165 #define regDAGB0_WRCLI1_BASE_IDX 1 166 #define regDAGB0_WRCLI2 0x0044 167 #define regDAGB0_WRCLI2_BASE_IDX 1 168 #define regDAGB0_WRCLI3 0x0045 169 #define regDAGB0_WRCLI3_BASE_IDX 1 170 #define regDAGB0_WRCLI4 0x0046 171 #define regDAGB0_WRCLI4_BASE_IDX 1 172 #define regDAGB0_WRCLI5 0x0047 173 #define regDAGB0_WRCLI5_BASE_IDX 1 174 #define regDAGB0_WRCLI6 0x0048 175 #define regDAGB0_WRCLI6_BASE_IDX 1 176 #define regDAGB0_WRCLI7 0x0049 177 #define regDAGB0_WRCLI7_BASE_IDX 1 178 #define regDAGB0_WRCLI8 0x004a 179 #define regDAGB0_WRCLI8_BASE_IDX 1 180 #define regDAGB0_WRCLI9 0x004b 181 #define regDAGB0_WRCLI9_BASE_IDX 1 182 #define regDAGB0_WRCLI10 0x004c 183 #define regDAGB0_WRCLI10_BASE_IDX 1 184 #define regDAGB0_WRCLI11 0x004d 185 #define regDAGB0_WRCLI11_BASE_IDX 1 186 #define regDAGB0_WRCLI12 0x004e 187 #define regDAGB0_WRCLI12_BASE_IDX 1 188 #define regDAGB0_WRCLI13 0x004f 189 #define regDAGB0_WRCLI13_BASE_IDX 1 190 #define regDAGB0_WRCLI14 0x0050 191 #define regDAGB0_WRCLI14_BASE_IDX 1 192 #define regDAGB0_WRCLI15 0x0051 193 #define regDAGB0_WRCLI15_BASE_IDX 1 194 #define regDAGB0_WRCLI16 0x0052 195 #define regDAGB0_WRCLI16_BASE_IDX 1 196 #define regDAGB0_WRCLI17 0x0053 197 #define regDAGB0_WRCLI17_BASE_IDX 1 198 #define regDAGB0_WRCLI18 0x0054 199 #define regDAGB0_WRCLI18_BASE_IDX 1 200 #define regDAGB0_WRCLI19 0x0055 201 #define regDAGB0_WRCLI19_BASE_IDX 1 202 #define regDAGB0_WRCLI20 0x0056 203 #define regDAGB0_WRCLI20_BASE_IDX 1 204 #define regDAGB0_WRCLI21 0x0057 205 #define regDAGB0_WRCLI21_BASE_IDX 1 206 #define regDAGB0_WRCLI22 0x0058 207 #define regDAGB0_WRCLI22_BASE_IDX 1 208 #define regDAGB0_WRCLI23 0x0059 209 #define regDAGB0_WRCLI23_BASE_IDX 1 210 #define regDAGB0_WRCLI24 0x005a 211 #define regDAGB0_WRCLI24_BASE_IDX 1 212 #define regDAGB0_WRCLI25 0x005b 213 #define regDAGB0_WRCLI25_BASE_IDX 1 214 #define regDAGB0_WRCLI26 0x005c 215 #define regDAGB0_WRCLI26_BASE_IDX 1 216 #define regDAGB0_WRCLI27 0x005d 217 #define regDAGB0_WRCLI27_BASE_IDX 1 218 #define regDAGB0_WRCLI28 0x005e 219 #define regDAGB0_WRCLI28_BASE_IDX 1 220 #define regDAGB0_WRCLI29 0x005f 221 #define regDAGB0_WRCLI29_BASE_IDX 1 222 #define regDAGB0_WRCLI30 0x0060 223 #define regDAGB0_WRCLI30_BASE_IDX 1 224 #define regDAGB0_WR_CNTL 0x0061 225 #define regDAGB0_WR_CNTL_BASE_IDX 1 226 #define regDAGB0_WR_IO_CNTL 0x0062 227 #define regDAGB0_WR_IO_CNTL_BASE_IDX 1 228 #define regDAGB0_WR_GMI_CNTL 0x0063 229 #define regDAGB0_WR_GMI_CNTL_BASE_IDX 1 230 #define regDAGB0_WR_ADDR_DAGB 0x0064 231 #define regDAGB0_WR_ADDR_DAGB_BASE_IDX 1 232 #define regDAGB0_WR_CGTT_CLK_CTRL 0x0065 233 #define regDAGB0_WR_CGTT_CLK_CTRL_BASE_IDX 1 234 #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL 0x0066 235 #define regDAGB0_L1TLB_WR_CGTT_CLK_CTRL_BASE_IDX 1 236 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0 0x0067 237 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST0_BASE_IDX 1 238 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0 0x0068 239 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_BASE_IDX 1 240 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1 0x0069 241 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST1_BASE_IDX 1 242 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1 0x006a 243 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_BASE_IDX 1 244 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST2 0x006b 245 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST2_BASE_IDX 1 246 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2 0x006c 247 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER2_BASE_IDX 1 248 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST3 0x006d 249 #define regDAGB0_WR_ADDR_DAGB_MAX_BURST3_BASE_IDX 1 250 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3 0x006e 251 #define regDAGB0_WR_ADDR_DAGB_LAZY_TIMER3_BASE_IDX 1 252 #define regDAGB0_WR_DATA_DAGB 0x006f 253 #define regDAGB0_WR_DATA_DAGB_BASE_IDX 1 254 #define regDAGB0_WR_DATA_DAGB_MAX_BURST0 0x0070 255 #define regDAGB0_WR_DATA_DAGB_MAX_BURST0_BASE_IDX 1 256 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0 0x0071 257 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER0_BASE_IDX 1 258 #define regDAGB0_WR_DATA_DAGB_MAX_BURST1 0x0072 259 #define regDAGB0_WR_DATA_DAGB_MAX_BURST1_BASE_IDX 1 260 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1 0x0073 261 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER1_BASE_IDX 1 262 #define regDAGB0_WR_DATA_DAGB_MAX_BURST2 0x0074 263 #define regDAGB0_WR_DATA_DAGB_MAX_BURST2_BASE_IDX 1 264 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2 0x0075 265 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER2_BASE_IDX 1 266 #define regDAGB0_WR_DATA_DAGB_MAX_BURST3 0x0076 267 #define regDAGB0_WR_DATA_DAGB_MAX_BURST3_BASE_IDX 1 268 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3 0x0077 269 #define regDAGB0_WR_DATA_DAGB_LAZY_TIMER3_BASE_IDX 1 270 #define regDAGB0_WR_VC0_CNTL 0x0078 271 #define regDAGB0_WR_VC0_CNTL_BASE_IDX 1 272 #define regDAGB0_WR_VC1_CNTL 0x0079 273 #define regDAGB0_WR_VC1_CNTL_BASE_IDX 1 274 #define regDAGB0_WR_VC2_CNTL 0x007a 275 #define regDAGB0_WR_VC2_CNTL_BASE_IDX 1 276 #define regDAGB0_WR_VC3_CNTL 0x007b 277 #define regDAGB0_WR_VC3_CNTL_BASE_IDX 1 278 #define regDAGB0_WR_VC4_CNTL 0x007c 279 #define regDAGB0_WR_VC4_CNTL_BASE_IDX 1 280 #define regDAGB0_WR_VC5_CNTL 0x007d 281 #define regDAGB0_WR_VC5_CNTL_BASE_IDX 1 282 #define regDAGB0_WR_IO_VC_CNTL 0x007e 283 #define regDAGB0_WR_IO_VC_CNTL_BASE_IDX 1 284 #define regDAGB0_WR_GMI_VC_CNTL 0x007f 285 #define regDAGB0_WR_GMI_VC_CNTL_BASE_IDX 1 286 #define regDAGB0_WR_CNTL_MISC 0x0080 287 #define regDAGB0_WR_CNTL_MISC_BASE_IDX 1 288 #define regDAGB0_WR_TLB_CREDIT 0x0081 289 #define regDAGB0_WR_TLB_CREDIT_BASE_IDX 1 290 #define regDAGB0_WR_DATA_CREDIT 0x0082 291 #define regDAGB0_WR_DATA_CREDIT_BASE_IDX 1 292 #define regDAGB0_WR_MISC_CREDIT 0x0083 293 #define regDAGB0_WR_MISC_CREDIT_BASE_IDX 1 294 #define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1 0x0084 295 #define regDAGB0_WR_DATA_FIFO_CREDIT_CNTL1_BASE_IDX 1 296 #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 0x0085 297 #define regDAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1_BASE_IDX 1 298 #define regDAGB0_WRCLI_ASK_PENDING 0x0086 299 #define regDAGB0_WRCLI_ASK_PENDING_BASE_IDX 1 300 #define regDAGB0_WRCLI_GO_PENDING 0x0087 301 #define regDAGB0_WRCLI_GO_PENDING_BASE_IDX 1 302 #define regDAGB0_WRCLI_GBLSEND_PENDING 0x0088 303 #define regDAGB0_WRCLI_GBLSEND_PENDING_BASE_IDX 1 304 #define regDAGB0_WRCLI_TLB_PENDING 0x0089 305 #define regDAGB0_WRCLI_TLB_PENDING_BASE_IDX 1 306 #define regDAGB0_WRCLI_OARB_PENDING 0x008a 307 #define regDAGB0_WRCLI_OARB_PENDING_BASE_IDX 1 308 #define regDAGB0_WRCLI_ASK2ARB_PENDING 0x008b 309 #define regDAGB0_WRCLI_ASK2ARB_PENDING_BASE_IDX 1 310 #define regDAGB0_WRCLI_ASK2DF_PENDING 0x008c 311 #define regDAGB0_WRCLI_ASK2DF_PENDING_BASE_IDX 1 312 #define regDAGB0_WRCLI_OSD_PENDING 0x008d 313 #define regDAGB0_WRCLI_OSD_PENDING_BASE_IDX 1 314 #define regDAGB0_WRCLI_ASK_OSD_PENDING 0x008e 315 #define regDAGB0_WRCLI_ASK_OSD_PENDING_BASE_IDX 1 316 #define regDAGB0_WRCLI_DBUS_ASK_PENDING 0x008f 317 #define regDAGB0_WRCLI_DBUS_ASK_PENDING_BASE_IDX 1 318 #define regDAGB0_WRCLI_DBUS_GO_PENDING 0x0090 319 #define regDAGB0_WRCLI_DBUS_GO_PENDING_BASE_IDX 1 320 #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE 0x0091 321 #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_BASE_IDX 1 322 #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 0x0092 323 #define regDAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE_BASE_IDX 1 324 #define regDAGB0_WRCLI_NOALLOC_OVERRIDE 0x0093 325 #define regDAGB0_WRCLI_NOALLOC_OVERRIDE_BASE_IDX 1 326 #define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE 0x0094 327 #define regDAGB0_WRCLI_NOALLOC_OVERRIDE_VALUE_BASE_IDX 1 328 #define regDAGB0_DAGB_DLY 0x0095 329 #define regDAGB0_DAGB_DLY_BASE_IDX 1 330 #define regDAGB0_CNTL_MISC 0x0096 331 #define regDAGB0_CNTL_MISC_BASE_IDX 1 332 #define regDAGB0_CNTL_MISC2 0x0097 333 #define regDAGB0_CNTL_MISC2_BASE_IDX 1 334 #define regDAGB0_FIFO_EMPTY 0x0098 335 #define regDAGB0_FIFO_EMPTY_BASE_IDX 1 336 #define regDAGB0_FIFO_FULL 0x0099 337 #define regDAGB0_FIFO_FULL_BASE_IDX 1 338 #define regDAGB0_RD_CREDITS_FULL 0x009a 339 #define regDAGB0_RD_CREDITS_FULL_BASE_IDX 1 340 #define regDAGB0_WR_CREDITS_FULL 0x009b 341 #define regDAGB0_WR_CREDITS_FULL_BASE_IDX 1 342 #define regDAGB0_PERFCOUNTER_LO 0x009c 343 #define regDAGB0_PERFCOUNTER_LO_BASE_IDX 1 344 #define regDAGB0_PERFCOUNTER_HI 0x009d 345 #define regDAGB0_PERFCOUNTER_HI_BASE_IDX 1 346 #define regDAGB0_PERFCOUNTER0_CFG 0x009e 347 #define regDAGB0_PERFCOUNTER0_CFG_BASE_IDX 1 348 #define regDAGB0_PERFCOUNTER1_CFG 0x009f 349 #define regDAGB0_PERFCOUNTER1_CFG_BASE_IDX 1 350 #define regDAGB0_PERFCOUNTER2_CFG 0x00a0 351 #define regDAGB0_PERFCOUNTER2_CFG_BASE_IDX 1 352 #define regDAGB0_PERFCOUNTER_RSLT_CNTL 0x00a1 353 #define regDAGB0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 354 #define regDAGB0_L1TLB_REG_RW 0x00a2 355 #define regDAGB0_L1TLB_REG_RW_BASE_IDX 1 356 #define regDAGB0_RESERVE1 0x00a3 357 #define regDAGB0_RESERVE1_BASE_IDX 1 358 #define regDAGB0_RESERVE2 0x00a4 359 #define regDAGB0_RESERVE2_BASE_IDX 1 360 #define regDAGB0_RESERVE3 0x00a5 361 #define regDAGB0_RESERVE3_BASE_IDX 1 362 #define regDAGB0_RESERVE4 0x00a6 363 #define regDAGB0_RESERVE4_BASE_IDX 1 364 #define regDAGB0_SDP_RD_BW_CNTL 0x00a7 365 #define regDAGB0_SDP_RD_BW_CNTL_BASE_IDX 1 366 #define regDAGB0_SDP_PRIORITY_OVERRIDE 0x00a8 367 #define regDAGB0_SDP_PRIORITY_OVERRIDE_BASE_IDX 1 368 #define regDAGB0_SDP_RD_PRIORITY 0x00a9 369 #define regDAGB0_SDP_RD_PRIORITY_BASE_IDX 1 370 #define regDAGB0_SDP_WR_PRIORITY 0x00aa 371 #define regDAGB0_SDP_WR_PRIORITY_BASE_IDX 1 372 #define regDAGB0_SDP_RD_CLI2SDP_VC_MAP 0x00ab 373 #define regDAGB0_SDP_RD_CLI2SDP_VC_MAP_BASE_IDX 1 374 #define regDAGB0_SDP_WR_CLI2SDP_VC_MAP 0x00ac 375 #define regDAGB0_SDP_WR_CLI2SDP_VC_MAP_BASE_IDX 1 376 #define regDAGB0_SDP_ENABLE 0x00ad 377 #define regDAGB0_SDP_ENABLE_BASE_IDX 1 378 #define regDAGB0_SDP_CREDITS 0x00ae 379 #define regDAGB0_SDP_CREDITS_BASE_IDX 1 380 #define regDAGB0_SDP_TAG_RESERVE0 0x00af 381 #define regDAGB0_SDP_TAG_RESERVE0_BASE_IDX 1 382 #define regDAGB0_SDP_TAG_RESERVE1 0x00b0 383 #define regDAGB0_SDP_TAG_RESERVE1_BASE_IDX 1 384 #define regDAGB0_SDP_VCC_RESERVE0 0x00b1 385 #define regDAGB0_SDP_VCC_RESERVE0_BASE_IDX 1 386 #define regDAGB0_SDP_VCC_RESERVE1 0x00b2 387 #define regDAGB0_SDP_VCC_RESERVE1_BASE_IDX 1 388 #define regDAGB0_SDP_ERR_STATUS 0x00b3 389 #define regDAGB0_SDP_ERR_STATUS_BASE_IDX 1 390 #define regDAGB0_SDP_REQ_CNTL 0x00b4 391 #define regDAGB0_SDP_REQ_CNTL_BASE_IDX 1 392 #define regDAGB0_SDP_MISC_AON 0x00b5 393 #define regDAGB0_SDP_MISC_AON_BASE_IDX 1 394 #define regDAGB0_SDP_MISC 0x00b6 395 #define regDAGB0_SDP_MISC_BASE_IDX 1 396 #define regDAGB0_SDP_MISC2 0x00b7 397 #define regDAGB0_SDP_MISC2_BASE_IDX 1 398 #define regDAGB0_SDP_VCD_RESERVE0 0x00b9 399 #define regDAGB0_SDP_VCD_RESERVE0_BASE_IDX 1 400 #define regDAGB0_SDP_VCD_RESERVE1 0x00ba 401 #define regDAGB0_SDP_VCD_RESERVE1_BASE_IDX 1 402 #define regDAGB0_SDP_ARB_CNTL0 0x00bb 403 #define regDAGB0_SDP_ARB_CNTL0_BASE_IDX 1 404 #define regDAGB0_SDP_ARB_CNTL1 0x00bc 405 #define regDAGB0_SDP_ARB_CNTL1_BASE_IDX 1 406 #define regDAGB0_SDP_CGTT_CLK_CTRL 0x00bd 407 #define regDAGB0_SDP_CGTT_CLK_CTRL_BASE_IDX 1 408 #define regDAGB0_SDP_LATENCY_SAMPLING 0x00be 409 #define regDAGB0_SDP_LATENCY_SAMPLING_BASE_IDX 1 410 411 412 // addressBlock: mmhub_pctldec 413 // base address: 0x68e00 414 #define regPCTL_CTRL 0x0380 415 #define regPCTL_CTRL_BASE_IDX 1 416 #define regPCTL_MMHUB_DEEPSLEEP_IB 0x0381 417 #define regPCTL_MMHUB_DEEPSLEEP_IB_BASE_IDX 1 418 #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE 0x0382 419 #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_BASE_IDX 1 420 #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB 0x0383 421 #define regPCTL_MMHUB_DEEPSLEEP_OVERRIDE_IB_BASE_IDX 1 422 #define regPCTL_PG_IGNORE_DEEPSLEEP 0x0384 423 #define regPCTL_PG_IGNORE_DEEPSLEEP_BASE_IDX 1 424 #define regPCTL_PG_IGNORE_DEEPSLEEP_IB 0x0385 425 #define regPCTL_PG_IGNORE_DEEPSLEEP_IB_BASE_IDX 1 426 #define regPCTL_SLICE0_CFG_DAGB_WRBUSY 0x0386 427 #define regPCTL_SLICE0_CFG_DAGB_WRBUSY_BASE_IDX 1 428 #define regPCTL_SLICE0_CFG_DAGB_RDBUSY 0x0387 429 #define regPCTL_SLICE0_CFG_DAGB_RDBUSY_BASE_IDX 1 430 #define regPCTL_SLICE0_CFG_DS_ALLOW 0x0388 431 #define regPCTL_SLICE0_CFG_DS_ALLOW_BASE_IDX 1 432 #define regPCTL_SLICE0_CFG_DS_ALLOW_IB 0x0389 433 #define regPCTL_SLICE0_CFG_DS_ALLOW_IB_BASE_IDX 1 434 #define regPCTL_SLICE1_CFG_DAGB_WRBUSY 0x038a 435 #define regPCTL_SLICE1_CFG_DAGB_WRBUSY_BASE_IDX 1 436 #define regPCTL_SLICE1_CFG_DAGB_RDBUSY 0x038b 437 #define regPCTL_SLICE1_CFG_DAGB_RDBUSY_BASE_IDX 1 438 #define regPCTL_SLICE1_CFG_DS_ALLOW 0x038c 439 #define regPCTL_SLICE1_CFG_DS_ALLOW_BASE_IDX 1 440 #define regPCTL_SLICE1_CFG_DS_ALLOW_IB 0x038d 441 #define regPCTL_SLICE1_CFG_DS_ALLOW_IB_BASE_IDX 1 442 #define regPCTL_UTCL2_MISC 0x038e 443 #define regPCTL_UTCL2_MISC_BASE_IDX 1 444 #define regPCTL_SLICE0_MISC 0x038f 445 #define regPCTL_SLICE0_MISC_BASE_IDX 1 446 #define regPCTL_SLICE1_MISC 0x0390 447 #define regPCTL_SLICE1_MISC_BASE_IDX 1 448 #define regPCTL_RENG_CTRL 0x0391 449 #define regPCTL_RENG_CTRL_BASE_IDX 1 450 #define regPCTL_UTCL2_RENG_EXECUTE 0x0392 451 #define regPCTL_UTCL2_RENG_EXECUTE_BASE_IDX 1 452 #define regPCTL_SLICE0_RENG_EXECUTE 0x0393 453 #define regPCTL_SLICE0_RENG_EXECUTE_BASE_IDX 1 454 #define regPCTL_SLICE1_RENG_EXECUTE 0x0394 455 #define regPCTL_SLICE1_RENG_EXECUTE_BASE_IDX 1 456 #define regPCTL_UTCL2_RENG_RAM_INDEX 0x0395 457 #define regPCTL_UTCL2_RENG_RAM_INDEX_BASE_IDX 1 458 #define regPCTL_UTCL2_RENG_RAM_DATA 0x0396 459 #define regPCTL_UTCL2_RENG_RAM_DATA_BASE_IDX 1 460 #define regPCTL_SLICE0_RENG_RAM_INDEX 0x0397 461 #define regPCTL_SLICE0_RENG_RAM_INDEX_BASE_IDX 1 462 #define regPCTL_SLICE0_RENG_RAM_DATA 0x0398 463 #define regPCTL_SLICE0_RENG_RAM_DATA_BASE_IDX 1 464 #define regPCTL_SLICE1_RENG_RAM_INDEX 0x0399 465 #define regPCTL_SLICE1_RENG_RAM_INDEX_BASE_IDX 1 466 #define regPCTL_SLICE1_RENG_RAM_DATA 0x039a 467 #define regPCTL_SLICE1_RENG_RAM_DATA_BASE_IDX 1 468 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0 0x039b 469 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 470 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1 0x039c 471 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 472 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2 0x039d 473 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 474 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3 0x039e 475 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 476 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4 0x039f 477 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 478 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a0 479 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 480 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a1 481 #define regPCTL_UTCL2_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 482 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0 0x03a2 483 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 484 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1 0x03a3 485 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 486 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2 0x03a4 487 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 488 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3 0x03a5 489 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 490 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4 0x03a6 491 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 492 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03a7 493 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 494 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03a8 495 #define regPCTL_SLICE0_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 496 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0 0x03a9 497 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE0_BASE_IDX 1 498 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1 0x03aa 499 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE1_BASE_IDX 1 500 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2 0x03ab 501 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE2_BASE_IDX 1 502 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3 0x03ac 503 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE3_BASE_IDX 1 504 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4 0x03ad 505 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_RANGE4_BASE_IDX 1 506 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0 0x03ae 507 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET0_BASE_IDX 1 508 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1 0x03af 509 #define regPCTL_SLICE1_STCTRL_REGISTER_SAVE_EXCL_SET1_BASE_IDX 1 510 #define regPCTL_STATUS 0x03b0 511 #define regPCTL_STATUS_BASE_IDX 1 512 #define regPCTL_PERFCOUNTER_LO 0x03b1 513 #define regPCTL_PERFCOUNTER_LO_BASE_IDX 1 514 #define regPCTL_PERFCOUNTER_HI 0x03b2 515 #define regPCTL_PERFCOUNTER_HI_BASE_IDX 1 516 #define regPCTL_PERFCOUNTER0_CFG 0x03b3 517 #define regPCTL_PERFCOUNTER0_CFG_BASE_IDX 1 518 #define regPCTL_PERFCOUNTER1_CFG 0x03b4 519 #define regPCTL_PERFCOUNTER1_CFG_BASE_IDX 1 520 #define regPCTL_PERFCOUNTER_RSLT_CNTL 0x03b5 521 #define regPCTL_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 522 #define regPCTL_RESERVED_0 0x03b6 523 #define regPCTL_RESERVED_0_BASE_IDX 1 524 #define regPCTL_RESERVED_1 0x03b7 525 #define regPCTL_RESERVED_1_BASE_IDX 1 526 #define regPCTL_RESERVED_2 0x03b8 527 #define regPCTL_RESERVED_2_BASE_IDX 1 528 #define regPCTL_RESERVED_3 0x03b9 529 #define regPCTL_RESERVED_3_BASE_IDX 1 530 531 532 // addressBlock: mmhub_l1tlb_mmutcl1pfdec 533 // base address: 0x69600 534 #define regMMMC_VM_MX_L1_TLB0_STATUS 0x0588 535 #define regMMMC_VM_MX_L1_TLB0_STATUS_BASE_IDX 1 536 #define regMMMC_VM_MX_L1_TLB1_STATUS 0x0589 537 #define regMMMC_VM_MX_L1_TLB1_STATUS_BASE_IDX 1 538 #define regMMMC_VM_MX_L1_TLB2_STATUS 0x058a 539 #define regMMMC_VM_MX_L1_TLB2_STATUS_BASE_IDX 1 540 #define regMMMC_VM_MX_L1_TLB3_STATUS 0x058b 541 #define regMMMC_VM_MX_L1_TLB3_STATUS_BASE_IDX 1 542 #define regMMMC_VM_MX_L1_TLB4_STATUS 0x058c 543 #define regMMMC_VM_MX_L1_TLB4_STATUS_BASE_IDX 1 544 #define regMMMC_VM_MX_L1_TLB5_STATUS 0x058d 545 #define regMMMC_VM_MX_L1_TLB5_STATUS_BASE_IDX 1 546 #define regMMMC_VM_MX_L1_TLB6_STATUS 0x058e 547 #define regMMMC_VM_MX_L1_TLB6_STATUS_BASE_IDX 1 548 #define regMMMC_VM_MX_L1_TLB7_STATUS 0x058f 549 #define regMMMC_VM_MX_L1_TLB7_STATUS_BASE_IDX 1 550 551 552 // addressBlock: mmhub_l1tlb_mmutcl1pldec 553 // base address: 0x69670 554 #define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG 0x059c 555 #define regMMMC_VM_MX_L1_PERFCOUNTER0_CFG_BASE_IDX 1 556 #define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG 0x059d 557 #define regMMMC_VM_MX_L1_PERFCOUNTER1_CFG_BASE_IDX 1 558 #define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG 0x059e 559 #define regMMMC_VM_MX_L1_PERFCOUNTER2_CFG_BASE_IDX 1 560 #define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG 0x059f 561 #define regMMMC_VM_MX_L1_PERFCOUNTER3_CFG_BASE_IDX 1 562 #define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 0x05a0 563 #define regMMMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 564 565 566 // addressBlock: mmhub_l1tlb_mmutcl1prdec 567 // base address: 0x69690 568 #define regMMMC_VM_MX_L1_PERFCOUNTER_LO 0x05a4 569 #define regMMMC_VM_MX_L1_PERFCOUNTER_LO_BASE_IDX 1 570 #define regMMMC_VM_MX_L1_PERFCOUNTER_HI 0x05a5 571 #define regMMMC_VM_MX_L1_PERFCOUNTER_HI_BASE_IDX 1 572 573 574 // addressBlock: mmhub_l1tlb_mmvmtlspfdec 575 // base address: 0x696c0 576 #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS 0x0701 577 #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_STATUS_BASE_IDX 1 578 #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32 0x0702 579 #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 580 #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32 0x0703 581 #define regMMMC_VM_MX_L1_TLS0_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 582 #define regMMVM_L2_SAW_CNTL 0x0704 583 #define regMMVM_L2_SAW_CNTL_BASE_IDX 1 584 #define regMMVM_L2_SAW_CNTL2 0x0705 585 #define regMMVM_L2_SAW_CNTL2_BASE_IDX 1 586 #define regMMVM_L2_SAW_CNTL3 0x0706 587 #define regMMVM_L2_SAW_CNTL3_BASE_IDX 1 588 #define regMMVM_L2_SAW_CNTL4 0x0707 589 #define regMMVM_L2_SAW_CNTL4_BASE_IDX 1 590 #define regMMVM_L2_SAW_CONTEXT0_CNTL 0x0708 591 #define regMMVM_L2_SAW_CONTEXT0_CNTL_BASE_IDX 1 592 #define regMMVM_L2_SAW_CONTEXT0_CNTL2 0x0709 593 #define regMMVM_L2_SAW_CONTEXT0_CNTL2_BASE_IDX 1 594 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x070a 595 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 596 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x070b 597 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 598 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x070c 599 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 600 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x070d 601 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 602 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x070e 603 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 604 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x070f 605 #define regMMVM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 606 #define regMMVM_L2_SAW_CONTEXTS_DISABLE 0x0710 607 #define regMMVM_L2_SAW_CONTEXTS_DISABLE_BASE_IDX 1 608 #define regMMVM_L2_SAW_PIPES_BUSY_LO32 0x0711 609 #define regMMVM_L2_SAW_PIPES_BUSY_LO32_BASE_IDX 1 610 #define regMMVM_L2_SAW_PIPES_BUSY_HI32 0x0712 611 #define regMMVM_L2_SAW_PIPES_BUSY_HI32_BASE_IDX 1 612 #define regMMVM_L2_SAW_PIPES_BUSY_1_LO32 0x0713 613 #define regMMVM_L2_SAW_PIPES_BUSY_1_LO32_BASE_IDX 1 614 #define regMMVM_L2_SAW_PIPES_BUSY_1_HI32 0x0714 615 #define regMMVM_L2_SAW_PIPES_BUSY_1_HI32_BASE_IDX 1 616 617 618 // addressBlock: mmhub_mmutcl2_mmatcl2dec 619 // base address: 0x69f00 620 #define regMM_ATC_L2_CNTL 0x07c0 621 #define regMM_ATC_L2_CNTL_BASE_IDX 1 622 #define regMM_ATC_L2_CNTL2 0x07c1 623 #define regMM_ATC_L2_CNTL2_BASE_IDX 1 624 #define regMM_ATC_L2_CACHE_DATA0 0x07c4 625 #define regMM_ATC_L2_CACHE_DATA0_BASE_IDX 1 626 #define regMM_ATC_L2_CACHE_DATA1 0x07c5 627 #define regMM_ATC_L2_CACHE_DATA1_BASE_IDX 1 628 #define regMM_ATC_L2_CACHE_DATA2 0x07c6 629 #define regMM_ATC_L2_CACHE_DATA2_BASE_IDX 1 630 #define regMM_ATC_L2_CNTL3 0x07c7 631 #define regMM_ATC_L2_CNTL3_BASE_IDX 1 632 #define regMM_ATC_L2_CNTL4 0x07c8 633 #define regMM_ATC_L2_CNTL4_BASE_IDX 1 634 #define regMM_ATC_L2_CNTL5 0x07c9 635 #define regMM_ATC_L2_CNTL5_BASE_IDX 1 636 #define regMM_ATC_L2_MM_GROUP_RT_CLASSES 0x07ca 637 #define regMM_ATC_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 638 #define regMM_ATC_L2_STATUS 0x07cb 639 #define regMM_ATC_L2_STATUS_BASE_IDX 1 640 #define regMM_ATC_L2_STATUS2 0x07cc 641 #define regMM_ATC_L2_STATUS2_BASE_IDX 1 642 #define regMM_ATC_L2_MISC_CG 0x07cd 643 #define regMM_ATC_L2_MISC_CG_BASE_IDX 1 644 #define regMM_ATC_L2_MEM_POWER_LS 0x07ce 645 #define regMM_ATC_L2_MEM_POWER_LS_BASE_IDX 1 646 #define regMM_ATC_L2_CGTT_CLK_CTRL 0x07cf 647 #define regMM_ATC_L2_CGTT_CLK_CTRL_BASE_IDX 1 648 #define regMM_ATC_L2_SDPPORT_CTRL 0x07d2 649 #define regMM_ATC_L2_SDPPORT_CTRL_BASE_IDX 1 650 651 652 // addressBlock: mmhub_mmutcl2_mmvml2pfdec 653 // base address: 0x6a000 654 #define regMMVM_L2_CNTL 0x0800 655 #define regMMVM_L2_CNTL_BASE_IDX 1 656 #define regMMVM_L2_CNTL2 0x0801 657 #define regMMVM_L2_CNTL2_BASE_IDX 1 658 #define regMMVM_L2_CNTL3 0x0802 659 #define regMMVM_L2_CNTL3_BASE_IDX 1 660 #define regMMVM_L2_STATUS 0x0803 661 #define regMMVM_L2_STATUS_BASE_IDX 1 662 #define regMMVM_DUMMY_PAGE_FAULT_CNTL 0x0804 663 #define regMMVM_DUMMY_PAGE_FAULT_CNTL_BASE_IDX 1 664 #define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32 0x0805 665 #define regMMVM_DUMMY_PAGE_FAULT_ADDR_LO32_BASE_IDX 1 666 #define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32 0x0806 667 #define regMMVM_DUMMY_PAGE_FAULT_ADDR_HI32_BASE_IDX 1 668 #define regMMVM_INVALIDATE_CNTL 0x0807 669 #define regMMVM_INVALIDATE_CNTL_BASE_IDX 1 670 #define regMMVM_L2_PROTECTION_FAULT_CNTL 0x0808 671 #define regMMVM_L2_PROTECTION_FAULT_CNTL_BASE_IDX 1 672 #define regMMVM_L2_PROTECTION_FAULT_CNTL2 0x0809 673 #define regMMVM_L2_PROTECTION_FAULT_CNTL2_BASE_IDX 1 674 #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3 0x080a 675 #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL3_BASE_IDX 1 676 #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4 0x080b 677 #define regMMVM_L2_PROTECTION_FAULT_MM_CNTL4_BASE_IDX 1 678 #define regMMVM_L2_PROTECTION_FAULT_STATUS 0x080c 679 #define regMMVM_L2_PROTECTION_FAULT_STATUS_BASE_IDX 1 680 #define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32 0x080d 681 #define regMMVM_L2_PROTECTION_FAULT_ADDR_LO32_BASE_IDX 1 682 #define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32 0x080e 683 #define regMMVM_L2_PROTECTION_FAULT_ADDR_HI32_BASE_IDX 1 684 #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 0x080f 685 #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 1 686 #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x0810 687 #define regMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 1 688 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x0812 689 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 1 690 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x0813 691 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_BASE_IDX 1 692 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 0x0814 693 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_BASE_IDX 1 694 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 0x0815 695 #define regMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_BASE_IDX 1 696 #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 0x0816 697 #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_BASE_IDX 1 698 #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 0x0817 699 #define regMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_BASE_IDX 1 700 #define regMMVM_L2_CNTL4 0x0818 701 #define regMMVM_L2_CNTL4_BASE_IDX 1 702 #define regMMVM_L2_MM_GROUP_RT_CLASSES 0x0819 703 #define regMMVM_L2_MM_GROUP_RT_CLASSES_BASE_IDX 1 704 #define regMMVM_L2_BANK_SELECT_RESERVED_CID 0x081a 705 #define regMMVM_L2_BANK_SELECT_RESERVED_CID_BASE_IDX 1 706 #define regMMVM_L2_BANK_SELECT_RESERVED_CID2 0x081b 707 #define regMMVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 1 708 #define regMMVM_L2_CACHE_PARITY_CNTL 0x081c 709 #define regMMVM_L2_CACHE_PARITY_CNTL_BASE_IDX 1 710 #define regMMVM_L2_CGTT_CLK_CTRL 0x081d 711 #define regMMVM_L2_CGTT_CLK_CTRL_BASE_IDX 1 712 #define regMMVM_L2_CNTL5 0x081e 713 #define regMMVM_L2_CNTL5_BASE_IDX 1 714 #define regMMVM_L2_GCR_CNTL 0x081f 715 #define regMMVM_L2_GCR_CNTL_BASE_IDX 1 716 #define regMMVM_L2_CGTT_BUSY_CTRL 0x0820 717 #define regMMVM_L2_CGTT_BUSY_CTRL_BASE_IDX 1 718 #define regMMVM_L2_PTE_CACHE_DUMP_CNTL 0x0821 719 #define regMMVM_L2_PTE_CACHE_DUMP_CNTL_BASE_IDX 1 720 #define regMMVM_L2_PTE_CACHE_DUMP_READ 0x0822 721 #define regMMVM_L2_PTE_CACHE_DUMP_READ_BASE_IDX 1 722 #define regMMVM_L2_BANK_SELECT_MASKS 0x0825 723 #define regMMVM_L2_BANK_SELECT_MASKS_BASE_IDX 1 724 #define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC 0x0826 725 #define regMMUTCL2_CREDIT_SAFETY_GROUP_RET_CDC_BASE_IDX 1 726 #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC 0x0827 727 #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_CDC_BASE_IDX 1 728 #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC 0x0828 729 #define regMMUTCL2_CREDIT_SAFETY_GROUP_CLIENTS_INVREQ_NOCDC_BASE_IDX 1 730 #define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT 0x0829 731 #define regMMVML2_CREDIT_SAFETY_IH_FAULT_INTERRUPT_BASE_IDX 1 732 #define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ 0x082a 733 #define regMMVML2_WALKER_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 734 735 736 // addressBlock: mmhub_mmutcl2_mmvml2vcdec 737 // base address: 0x6a100 738 #define regMMVM_CONTEXT0_CNTL 0x0840 739 #define regMMVM_CONTEXT0_CNTL_BASE_IDX 1 740 #define regMMVM_CONTEXT1_CNTL 0x0841 741 #define regMMVM_CONTEXT1_CNTL_BASE_IDX 1 742 #define regMMVM_CONTEXT2_CNTL 0x0842 743 #define regMMVM_CONTEXT2_CNTL_BASE_IDX 1 744 #define regMMVM_CONTEXT3_CNTL 0x0843 745 #define regMMVM_CONTEXT3_CNTL_BASE_IDX 1 746 #define regMMVM_CONTEXT4_CNTL 0x0844 747 #define regMMVM_CONTEXT4_CNTL_BASE_IDX 1 748 #define regMMVM_CONTEXT5_CNTL 0x0845 749 #define regMMVM_CONTEXT5_CNTL_BASE_IDX 1 750 #define regMMVM_CONTEXT6_CNTL 0x0846 751 #define regMMVM_CONTEXT6_CNTL_BASE_IDX 1 752 #define regMMVM_CONTEXT7_CNTL 0x0847 753 #define regMMVM_CONTEXT7_CNTL_BASE_IDX 1 754 #define regMMVM_CONTEXT8_CNTL 0x0848 755 #define regMMVM_CONTEXT8_CNTL_BASE_IDX 1 756 #define regMMVM_CONTEXT9_CNTL 0x0849 757 #define regMMVM_CONTEXT9_CNTL_BASE_IDX 1 758 #define regMMVM_CONTEXT10_CNTL 0x084a 759 #define regMMVM_CONTEXT10_CNTL_BASE_IDX 1 760 #define regMMVM_CONTEXT11_CNTL 0x084b 761 #define regMMVM_CONTEXT11_CNTL_BASE_IDX 1 762 #define regMMVM_CONTEXT12_CNTL 0x084c 763 #define regMMVM_CONTEXT12_CNTL_BASE_IDX 1 764 #define regMMVM_CONTEXT13_CNTL 0x084d 765 #define regMMVM_CONTEXT13_CNTL_BASE_IDX 1 766 #define regMMVM_CONTEXT14_CNTL 0x084e 767 #define regMMVM_CONTEXT14_CNTL_BASE_IDX 1 768 #define regMMVM_CONTEXT15_CNTL 0x084f 769 #define regMMVM_CONTEXT15_CNTL_BASE_IDX 1 770 #define regMMVM_CONTEXTS_DISABLE 0x0850 771 #define regMMVM_CONTEXTS_DISABLE_BASE_IDX 1 772 #define regMMVM_INVALIDATE_ENG0_SEM 0x0851 773 #define regMMVM_INVALIDATE_ENG0_SEM_BASE_IDX 1 774 #define regMMVM_INVALIDATE_ENG1_SEM 0x0852 775 #define regMMVM_INVALIDATE_ENG1_SEM_BASE_IDX 1 776 #define regMMVM_INVALIDATE_ENG2_SEM 0x0853 777 #define regMMVM_INVALIDATE_ENG2_SEM_BASE_IDX 1 778 #define regMMVM_INVALIDATE_ENG3_SEM 0x0854 779 #define regMMVM_INVALIDATE_ENG3_SEM_BASE_IDX 1 780 #define regMMVM_INVALIDATE_ENG4_SEM 0x0855 781 #define regMMVM_INVALIDATE_ENG4_SEM_BASE_IDX 1 782 #define regMMVM_INVALIDATE_ENG5_SEM 0x0856 783 #define regMMVM_INVALIDATE_ENG5_SEM_BASE_IDX 1 784 #define regMMVM_INVALIDATE_ENG6_SEM 0x0857 785 #define regMMVM_INVALIDATE_ENG6_SEM_BASE_IDX 1 786 #define regMMVM_INVALIDATE_ENG7_SEM 0x0858 787 #define regMMVM_INVALIDATE_ENG7_SEM_BASE_IDX 1 788 #define regMMVM_INVALIDATE_ENG8_SEM 0x0859 789 #define regMMVM_INVALIDATE_ENG8_SEM_BASE_IDX 1 790 #define regMMVM_INVALIDATE_ENG9_SEM 0x085a 791 #define regMMVM_INVALIDATE_ENG9_SEM_BASE_IDX 1 792 #define regMMVM_INVALIDATE_ENG10_SEM 0x085b 793 #define regMMVM_INVALIDATE_ENG10_SEM_BASE_IDX 1 794 #define regMMVM_INVALIDATE_ENG11_SEM 0x085c 795 #define regMMVM_INVALIDATE_ENG11_SEM_BASE_IDX 1 796 #define regMMVM_INVALIDATE_ENG12_SEM 0x085d 797 #define regMMVM_INVALIDATE_ENG12_SEM_BASE_IDX 1 798 #define regMMVM_INVALIDATE_ENG13_SEM 0x085e 799 #define regMMVM_INVALIDATE_ENG13_SEM_BASE_IDX 1 800 #define regMMVM_INVALIDATE_ENG14_SEM 0x085f 801 #define regMMVM_INVALIDATE_ENG14_SEM_BASE_IDX 1 802 #define regMMVM_INVALIDATE_ENG15_SEM 0x0860 803 #define regMMVM_INVALIDATE_ENG15_SEM_BASE_IDX 1 804 #define regMMVM_INVALIDATE_ENG16_SEM 0x0861 805 #define regMMVM_INVALIDATE_ENG16_SEM_BASE_IDX 1 806 #define regMMVM_INVALIDATE_ENG17_SEM 0x0862 807 #define regMMVM_INVALIDATE_ENG17_SEM_BASE_IDX 1 808 #define regMMVM_INVALIDATE_ENG0_REQ 0x0863 809 #define regMMVM_INVALIDATE_ENG0_REQ_BASE_IDX 1 810 #define regMMVM_INVALIDATE_ENG1_REQ 0x0864 811 #define regMMVM_INVALIDATE_ENG1_REQ_BASE_IDX 1 812 #define regMMVM_INVALIDATE_ENG2_REQ 0x0865 813 #define regMMVM_INVALIDATE_ENG2_REQ_BASE_IDX 1 814 #define regMMVM_INVALIDATE_ENG3_REQ 0x0866 815 #define regMMVM_INVALIDATE_ENG3_REQ_BASE_IDX 1 816 #define regMMVM_INVALIDATE_ENG4_REQ 0x0867 817 #define regMMVM_INVALIDATE_ENG4_REQ_BASE_IDX 1 818 #define regMMVM_INVALIDATE_ENG5_REQ 0x0868 819 #define regMMVM_INVALIDATE_ENG5_REQ_BASE_IDX 1 820 #define regMMVM_INVALIDATE_ENG6_REQ 0x0869 821 #define regMMVM_INVALIDATE_ENG6_REQ_BASE_IDX 1 822 #define regMMVM_INVALIDATE_ENG7_REQ 0x086a 823 #define regMMVM_INVALIDATE_ENG7_REQ_BASE_IDX 1 824 #define regMMVM_INVALIDATE_ENG8_REQ 0x086b 825 #define regMMVM_INVALIDATE_ENG8_REQ_BASE_IDX 1 826 #define regMMVM_INVALIDATE_ENG9_REQ 0x086c 827 #define regMMVM_INVALIDATE_ENG9_REQ_BASE_IDX 1 828 #define regMMVM_INVALIDATE_ENG10_REQ 0x086d 829 #define regMMVM_INVALIDATE_ENG10_REQ_BASE_IDX 1 830 #define regMMVM_INVALIDATE_ENG11_REQ 0x086e 831 #define regMMVM_INVALIDATE_ENG11_REQ_BASE_IDX 1 832 #define regMMVM_INVALIDATE_ENG12_REQ 0x086f 833 #define regMMVM_INVALIDATE_ENG12_REQ_BASE_IDX 1 834 #define regMMVM_INVALIDATE_ENG13_REQ 0x0870 835 #define regMMVM_INVALIDATE_ENG13_REQ_BASE_IDX 1 836 #define regMMVM_INVALIDATE_ENG14_REQ 0x0871 837 #define regMMVM_INVALIDATE_ENG14_REQ_BASE_IDX 1 838 #define regMMVM_INVALIDATE_ENG15_REQ 0x0872 839 #define regMMVM_INVALIDATE_ENG15_REQ_BASE_IDX 1 840 #define regMMVM_INVALIDATE_ENG16_REQ 0x0873 841 #define regMMVM_INVALIDATE_ENG16_REQ_BASE_IDX 1 842 #define regMMVM_INVALIDATE_ENG17_REQ 0x0874 843 #define regMMVM_INVALIDATE_ENG17_REQ_BASE_IDX 1 844 #define regMMVM_INVALIDATE_ENG0_ACK 0x0875 845 #define regMMVM_INVALIDATE_ENG0_ACK_BASE_IDX 1 846 #define regMMVM_INVALIDATE_ENG1_ACK 0x0876 847 #define regMMVM_INVALIDATE_ENG1_ACK_BASE_IDX 1 848 #define regMMVM_INVALIDATE_ENG2_ACK 0x0877 849 #define regMMVM_INVALIDATE_ENG2_ACK_BASE_IDX 1 850 #define regMMVM_INVALIDATE_ENG3_ACK 0x0878 851 #define regMMVM_INVALIDATE_ENG3_ACK_BASE_IDX 1 852 #define regMMVM_INVALIDATE_ENG4_ACK 0x0879 853 #define regMMVM_INVALIDATE_ENG4_ACK_BASE_IDX 1 854 #define regMMVM_INVALIDATE_ENG5_ACK 0x087a 855 #define regMMVM_INVALIDATE_ENG5_ACK_BASE_IDX 1 856 #define regMMVM_INVALIDATE_ENG6_ACK 0x087b 857 #define regMMVM_INVALIDATE_ENG6_ACK_BASE_IDX 1 858 #define regMMVM_INVALIDATE_ENG7_ACK 0x087c 859 #define regMMVM_INVALIDATE_ENG7_ACK_BASE_IDX 1 860 #define regMMVM_INVALIDATE_ENG8_ACK 0x087d 861 #define regMMVM_INVALIDATE_ENG8_ACK_BASE_IDX 1 862 #define regMMVM_INVALIDATE_ENG9_ACK 0x087e 863 #define regMMVM_INVALIDATE_ENG9_ACK_BASE_IDX 1 864 #define regMMVM_INVALIDATE_ENG10_ACK 0x087f 865 #define regMMVM_INVALIDATE_ENG10_ACK_BASE_IDX 1 866 #define regMMVM_INVALIDATE_ENG11_ACK 0x0880 867 #define regMMVM_INVALIDATE_ENG11_ACK_BASE_IDX 1 868 #define regMMVM_INVALIDATE_ENG12_ACK 0x0881 869 #define regMMVM_INVALIDATE_ENG12_ACK_BASE_IDX 1 870 #define regMMVM_INVALIDATE_ENG13_ACK 0x0882 871 #define regMMVM_INVALIDATE_ENG13_ACK_BASE_IDX 1 872 #define regMMVM_INVALIDATE_ENG14_ACK 0x0883 873 #define regMMVM_INVALIDATE_ENG14_ACK_BASE_IDX 1 874 #define regMMVM_INVALIDATE_ENG15_ACK 0x0884 875 #define regMMVM_INVALIDATE_ENG15_ACK_BASE_IDX 1 876 #define regMMVM_INVALIDATE_ENG16_ACK 0x0885 877 #define regMMVM_INVALIDATE_ENG16_ACK_BASE_IDX 1 878 #define regMMVM_INVALIDATE_ENG17_ACK 0x0886 879 #define regMMVM_INVALIDATE_ENG17_ACK_BASE_IDX 1 880 #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32 0x0887 881 #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_BASE_IDX 1 882 #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32 0x0888 883 #define regMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_BASE_IDX 1 884 #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 0x0889 885 #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_BASE_IDX 1 886 #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32 0x088a 887 #define regMMVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_BASE_IDX 1 888 #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32 0x088b 889 #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_BASE_IDX 1 890 #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32 0x088c 891 #define regMMVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_BASE_IDX 1 892 #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32 0x088d 893 #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_BASE_IDX 1 894 #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32 0x088e 895 #define regMMVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_BASE_IDX 1 896 #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32 0x088f 897 #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_BASE_IDX 1 898 #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32 0x0890 899 #define regMMVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_BASE_IDX 1 900 #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32 0x0891 901 #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_BASE_IDX 1 902 #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32 0x0892 903 #define regMMVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_BASE_IDX 1 904 #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32 0x0893 905 #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_BASE_IDX 1 906 #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32 0x0894 907 #define regMMVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_BASE_IDX 1 908 #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32 0x0895 909 #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_BASE_IDX 1 910 #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32 0x0896 911 #define regMMVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_BASE_IDX 1 912 #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32 0x0897 913 #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_BASE_IDX 1 914 #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32 0x0898 915 #define regMMVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_BASE_IDX 1 916 #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32 0x0899 917 #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_BASE_IDX 1 918 #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32 0x089a 919 #define regMMVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_BASE_IDX 1 920 #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32 0x089b 921 #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_BASE_IDX 1 922 #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32 0x089c 923 #define regMMVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_BASE_IDX 1 924 #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32 0x089d 925 #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_BASE_IDX 1 926 #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32 0x089e 927 #define regMMVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_BASE_IDX 1 928 #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32 0x089f 929 #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_BASE_IDX 1 930 #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32 0x08a0 931 #define regMMVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_BASE_IDX 1 932 #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32 0x08a1 933 #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_BASE_IDX 1 934 #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32 0x08a2 935 #define regMMVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_BASE_IDX 1 936 #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32 0x08a3 937 #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_BASE_IDX 1 938 #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32 0x08a4 939 #define regMMVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_BASE_IDX 1 940 #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32 0x08a5 941 #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_BASE_IDX 1 942 #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32 0x08a6 943 #define regMMVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_BASE_IDX 1 944 #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32 0x08a7 945 #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_BASE_IDX 1 946 #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32 0x08a8 947 #define regMMVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_BASE_IDX 1 948 #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32 0x08a9 949 #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_BASE_IDX 1 950 #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32 0x08aa 951 #define regMMVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_BASE_IDX 1 952 #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 0x08ab 953 #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 954 #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 0x08ac 955 #define regMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 956 #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 0x08ad 957 #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 958 #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 0x08ae 959 #define regMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 960 #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 0x08af 961 #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 962 #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 0x08b0 963 #define regMMVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 964 #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 0x08b1 965 #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 966 #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 0x08b2 967 #define regMMVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 968 #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 0x08b3 969 #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 970 #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 0x08b4 971 #define regMMVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 972 #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 0x08b5 973 #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 974 #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 0x08b6 975 #define regMMVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 976 #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 0x08b7 977 #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 978 #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 0x08b8 979 #define regMMVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 980 #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 0x08b9 981 #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 982 #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 0x08ba 983 #define regMMVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 984 #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 0x08bb 985 #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 986 #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 0x08bc 987 #define regMMVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 988 #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 0x08bd 989 #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 990 #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 0x08be 991 #define regMMVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 992 #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 0x08bf 993 #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 994 #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 0x08c0 995 #define regMMVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 996 #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 0x08c1 997 #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 998 #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 0x08c2 999 #define regMMVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1000 #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 0x08c3 1001 #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1002 #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 0x08c4 1003 #define regMMVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1004 #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 0x08c5 1005 #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1006 #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 0x08c6 1007 #define regMMVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1008 #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 0x08c7 1009 #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1010 #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 0x08c8 1011 #define regMMVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1012 #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 0x08c9 1013 #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_BASE_IDX 1 1014 #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 0x08ca 1015 #define regMMVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_BASE_IDX 1 1016 #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 0x08cb 1017 #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1018 #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 0x08cc 1019 #define regMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1020 #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 0x08cd 1021 #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1022 #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 0x08ce 1023 #define regMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1024 #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 0x08cf 1025 #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1026 #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 0x08d0 1027 #define regMMVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1028 #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 0x08d1 1029 #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1030 #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 0x08d2 1031 #define regMMVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1032 #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 0x08d3 1033 #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1034 #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 0x08d4 1035 #define regMMVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1036 #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 0x08d5 1037 #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1038 #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 0x08d6 1039 #define regMMVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1040 #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 0x08d7 1041 #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1042 #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 0x08d8 1043 #define regMMVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1044 #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 0x08d9 1045 #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1046 #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 0x08da 1047 #define regMMVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1048 #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 0x08db 1049 #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1050 #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 0x08dc 1051 #define regMMVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1052 #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 0x08dd 1053 #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1054 #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 0x08de 1055 #define regMMVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1056 #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 0x08df 1057 #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1058 #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 0x08e0 1059 #define regMMVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1060 #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 0x08e1 1061 #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1062 #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 0x08e2 1063 #define regMMVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1064 #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 0x08e3 1065 #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1066 #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 0x08e4 1067 #define regMMVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1068 #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 0x08e5 1069 #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1070 #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 0x08e6 1071 #define regMMVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1072 #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 0x08e7 1073 #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1074 #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 0x08e8 1075 #define regMMVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1076 #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 0x08e9 1077 #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_BASE_IDX 1 1078 #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 0x08ea 1079 #define regMMVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_BASE_IDX 1 1080 #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 0x08eb 1081 #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1082 #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 0x08ec 1083 #define regMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1084 #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 0x08ed 1085 #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1086 #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 0x08ee 1087 #define regMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1088 #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 0x08ef 1089 #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1090 #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 0x08f0 1091 #define regMMVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1092 #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 0x08f1 1093 #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1094 #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 0x08f2 1095 #define regMMVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1096 #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 0x08f3 1097 #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1098 #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 0x08f4 1099 #define regMMVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1100 #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 0x08f5 1101 #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1102 #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 0x08f6 1103 #define regMMVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1104 #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 0x08f7 1105 #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1106 #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 0x08f8 1107 #define regMMVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1108 #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 0x08f9 1109 #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1110 #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 0x08fa 1111 #define regMMVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1112 #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 0x08fb 1113 #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1114 #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 0x08fc 1115 #define regMMVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1116 #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 0x08fd 1117 #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1118 #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 0x08fe 1119 #define regMMVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1120 #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 0x08ff 1121 #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1122 #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 0x0900 1123 #define regMMVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1124 #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 0x0901 1125 #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1126 #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 0x0902 1127 #define regMMVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1128 #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 0x0903 1129 #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1130 #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 0x0904 1131 #define regMMVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1132 #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 0x0905 1133 #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1134 #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 0x0906 1135 #define regMMVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1136 #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 0x0907 1137 #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1138 #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 0x0908 1139 #define regMMVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1140 #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 0x0909 1141 #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_BASE_IDX 1 1142 #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 0x090a 1143 #define regMMVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_BASE_IDX 1 1144 #define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x090b 1145 #define regMMVM_L2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1146 #define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x090c 1147 #define regMMVM_L2_CONTEXT0_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1148 #define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x090d 1149 #define regMMVM_L2_CONTEXT1_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1150 #define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x090e 1151 #define regMMVM_L2_CONTEXT2_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1152 #define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x090f 1153 #define regMMVM_L2_CONTEXT3_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1154 #define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0910 1155 #define regMMVM_L2_CONTEXT4_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1156 #define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0911 1157 #define regMMVM_L2_CONTEXT5_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1158 #define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0912 1159 #define regMMVM_L2_CONTEXT6_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1160 #define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0913 1161 #define regMMVM_L2_CONTEXT7_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1162 #define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0914 1163 #define regMMVM_L2_CONTEXT8_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1164 #define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0915 1165 #define regMMVM_L2_CONTEXT9_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1166 #define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0916 1167 #define regMMVM_L2_CONTEXT10_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1168 #define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0917 1169 #define regMMVM_L2_CONTEXT11_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1170 #define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0918 1171 #define regMMVM_L2_CONTEXT12_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1172 #define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x0919 1173 #define regMMVM_L2_CONTEXT13_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1174 #define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x091a 1175 #define regMMVM_L2_CONTEXT14_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1176 #define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES 0x091b 1177 #define regMMVM_L2_CONTEXT15_PER_PFVF_PTE_CACHE_FRAGMENT_SIZES_BASE_IDX 1 1178 1179 1180 // addressBlock: mmhub_mmutcl2_mmvml2pldec 1181 // base address: 0x6a490 1182 #define regMMMC_VM_L2_PERFCOUNTER0_CFG 0x0924 1183 #define regMMMC_VM_L2_PERFCOUNTER0_CFG_BASE_IDX 1 1184 #define regMMMC_VM_L2_PERFCOUNTER1_CFG 0x0925 1185 #define regMMMC_VM_L2_PERFCOUNTER1_CFG_BASE_IDX 1 1186 #define regMMMC_VM_L2_PERFCOUNTER2_CFG 0x0926 1187 #define regMMMC_VM_L2_PERFCOUNTER2_CFG_BASE_IDX 1 1188 #define regMMMC_VM_L2_PERFCOUNTER3_CFG 0x0927 1189 #define regMMMC_VM_L2_PERFCOUNTER3_CFG_BASE_IDX 1 1190 #define regMMMC_VM_L2_PERFCOUNTER4_CFG 0x0928 1191 #define regMMMC_VM_L2_PERFCOUNTER4_CFG_BASE_IDX 1 1192 #define regMMMC_VM_L2_PERFCOUNTER5_CFG 0x0929 1193 #define regMMMC_VM_L2_PERFCOUNTER5_CFG_BASE_IDX 1 1194 #define regMMMC_VM_L2_PERFCOUNTER6_CFG 0x092a 1195 #define regMMMC_VM_L2_PERFCOUNTER6_CFG_BASE_IDX 1 1196 #define regMMMC_VM_L2_PERFCOUNTER7_CFG 0x092b 1197 #define regMMMC_VM_L2_PERFCOUNTER7_CFG_BASE_IDX 1 1198 #define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL 0x092c 1199 #define regMMMC_VM_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1200 #define regMMUTCL2_PERFCOUNTER0_CFG 0x092d 1201 #define regMMUTCL2_PERFCOUNTER0_CFG_BASE_IDX 1 1202 #define regMMUTCL2_PERFCOUNTER1_CFG 0x092e 1203 #define regMMUTCL2_PERFCOUNTER1_CFG_BASE_IDX 1 1204 #define regMMUTCL2_PERFCOUNTER2_CFG 0x092f 1205 #define regMMUTCL2_PERFCOUNTER2_CFG_BASE_IDX 1 1206 #define regMMUTCL2_PERFCOUNTER3_CFG 0x0930 1207 #define regMMUTCL2_PERFCOUNTER3_CFG_BASE_IDX 1 1208 #define regMMUTCL2_PERFCOUNTER_RSLT_CNTL 0x0931 1209 #define regMMUTCL2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1210 1211 1212 // addressBlock: mmhub_mmutcl2_mmvml2prdec 1213 // base address: 0x6a4e0 1214 #define regMMMC_VM_L2_PERFCOUNTER_LO 0x0938 1215 #define regMMMC_VM_L2_PERFCOUNTER_LO_BASE_IDX 1 1216 #define regMMMC_VM_L2_PERFCOUNTER_HI 0x0939 1217 #define regMMMC_VM_L2_PERFCOUNTER_HI_BASE_IDX 1 1218 #define regMMUTCL2_PERFCOUNTER_LO 0x093a 1219 #define regMMUTCL2_PERFCOUNTER_LO_BASE_IDX 1 1220 #define regMMUTCL2_PERFCOUNTER_HI 0x093b 1221 #define regMMUTCL2_PERFCOUNTER_HI_BASE_IDX 1 1222 1223 1224 // addressBlock: mmhub_mmutcl2_mmvmsharedhvdec 1225 // base address: 0x6a530 1226 #define regMMVM_PCIE_ATS_CNTL 0x094c 1227 #define regMMVM_PCIE_ATS_CNTL_BASE_IDX 1 1228 1229 1230 // addressBlock: mmhub_mmutcl2_mmvmsharedpfdec 1231 // base address: 0x6a740 1232 #define regMMMC_VM_NB_MMIOBASE 0x09d0 1233 #define regMMMC_VM_NB_MMIOBASE_BASE_IDX 1 1234 #define regMMMC_VM_NB_MMIOLIMIT 0x09d1 1235 #define regMMMC_VM_NB_MMIOLIMIT_BASE_IDX 1 1236 #define regMMMC_VM_NB_PCI_CTRL 0x09d2 1237 #define regMMMC_VM_NB_PCI_CTRL_BASE_IDX 1 1238 #define regMMMC_VM_NB_PCI_ARB 0x09d3 1239 #define regMMMC_VM_NB_PCI_ARB_BASE_IDX 1 1240 #define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1 0x09d4 1241 #define regMMMC_VM_NB_TOP_OF_DRAM_SLOT1_BASE_IDX 1 1242 #define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2 0x09d5 1243 #define regMMMC_VM_NB_LOWER_TOP_OF_DRAM2_BASE_IDX 1 1244 #define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2 0x09d6 1245 #define regMMMC_VM_NB_UPPER_TOP_OF_DRAM2_BASE_IDX 1 1246 #define regMMMC_VM_FB_OFFSET 0x09d7 1247 #define regMMMC_VM_FB_OFFSET_BASE_IDX 1 1248 #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x09d8 1249 #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 1 1250 #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x09d9 1251 #define regMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 1 1252 #define regMMMC_VM_STEERING 0x09da 1253 #define regMMMC_VM_STEERING_BASE_IDX 1 1254 #define regMMMC_SHARED_VIRT_RESET_REQ 0x09db 1255 #define regMMMC_SHARED_VIRT_RESET_REQ_BASE_IDX 1 1256 #define regMMMC_MEM_POWER_LS 0x09dc 1257 #define regMMMC_MEM_POWER_LS_BASE_IDX 1 1258 #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START 0x09dd 1259 #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 1 1260 #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END 0x09de 1261 #define regMMMC_VM_CACHEABLE_DRAM_ADDRESS_END_BASE_IDX 1 1262 #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START 0x09df 1263 #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_START_BASE_IDX 1 1264 #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END 0x09e0 1265 #define regMMMC_VM_LOCAL_SYSMEM_ADDRESS_END_BASE_IDX 1 1266 #define regMMMC_VM_APT_CNTL 0x09e1 1267 #define regMMMC_VM_APT_CNTL_BASE_IDX 1 1268 #define regMMMC_VM_LOCAL_FB_ADDRESS_START 0x09e2 1269 #define regMMMC_VM_LOCAL_FB_ADDRESS_START_BASE_IDX 1 1270 #define regMMMC_VM_LOCAL_FB_ADDRESS_END 0x09e3 1271 #define regMMMC_VM_LOCAL_FB_ADDRESS_END_BASE_IDX 1 1272 #define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL 0x09e4 1273 #define regMMMC_VM_LOCAL_FB_ADDRESS_LOCK_CNTL_BASE_IDX 1 1274 #define regMMUTCL2_CGTT_CLK_CTRL 0x09e5 1275 #define regMMUTCL2_CGTT_CLK_CTRL_BASE_IDX 1 1276 #define regMMMC_SHARED_ACTIVE_FCN_ID 0x09e6 1277 #define regMMMC_SHARED_ACTIVE_FCN_ID_BASE_IDX 1 1278 #define regMMUTCL2_CGTT_BUSY_CTRL 0x09e7 1279 #define regMMUTCL2_CGTT_BUSY_CTRL_BASE_IDX 1 1280 #define regMMMC_VM_FB_NOALLOC_CNTL 0x09e8 1281 #define regMMMC_VM_FB_NOALLOC_CNTL_BASE_IDX 1 1282 #define regMMUTCL2_HARVEST_BYPASS_GROUPS 0x09e9 1283 #define regMMUTCL2_HARVEST_BYPASS_GROUPS_BASE_IDX 1 1284 #define regMMUTCL2_GROUP_RET_FAULT_STATUS 0x09eb 1285 #define regMMUTCL2_GROUP_RET_FAULT_STATUS_BASE_IDX 1 1286 1287 1288 // addressBlock: mmhub_mmutcl2_mmvmsharedvcdec 1289 // base address: 0x6a7b0 1290 #define regMMMC_VM_FB_LOCATION_BASE 0x09ec 1291 #define regMMMC_VM_FB_LOCATION_BASE_BASE_IDX 1 1292 #define regMMMC_VM_FB_LOCATION_TOP 0x09ed 1293 #define regMMMC_VM_FB_LOCATION_TOP_BASE_IDX 1 1294 #define regMMMC_VM_AGP_TOP 0x09ee 1295 #define regMMMC_VM_AGP_TOP_BASE_IDX 1 1296 #define regMMMC_VM_AGP_BOT 0x09ef 1297 #define regMMMC_VM_AGP_BOT_BASE_IDX 1 1298 #define regMMMC_VM_AGP_BASE 0x09f0 1299 #define regMMMC_VM_AGP_BASE_BASE_IDX 1 1300 #define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR 0x09f1 1301 #define regMMMC_VM_SYSTEM_APERTURE_LOW_ADDR_BASE_IDX 1 1302 #define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x09f2 1303 #define regMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR_BASE_IDX 1 1304 #define regMMMC_VM_MX_L1_TLB_CNTL 0x09f3 1305 #define regMMMC_VM_MX_L1_TLB_CNTL_BASE_IDX 1 1306 1307 1308 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntrdec 1309 // base address: 0x6a800 1310 #define regMM_ATC_L2_PERFCOUNTER_LO 0x0a00 1311 #define regMM_ATC_L2_PERFCOUNTER_LO_BASE_IDX 1 1312 #define regMM_ATC_L2_PERFCOUNTER_HI 0x0a01 1313 #define regMM_ATC_L2_PERFCOUNTER_HI_BASE_IDX 1 1314 1315 1316 // addressBlock: mmhub_mmutcl2_mmatcl2pfcntldec 1317 // base address: 0x6a820 1318 #define regMM_ATC_L2_PERFCOUNTER0_CFG 0x0a08 1319 #define regMM_ATC_L2_PERFCOUNTER0_CFG_BASE_IDX 1 1320 #define regMM_ATC_L2_PERFCOUNTER1_CFG 0x0a09 1321 #define regMM_ATC_L2_PERFCOUNTER1_CFG_BASE_IDX 1 1322 #define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL 0x0a0a 1323 #define regMM_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1324 1325 1326 // addressBlock: mmhub_mmutcl2_mmvml2pspdec 1327 // base address: 0x6ae50 1328 #define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID 0x0b94 1329 #define regMMUTCL2_TRANSLATION_BYPASS_BY_VMID_BASE_IDX 1 1330 #define regMMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE 0x0b96 1331 #define regMMVM_IOMMU_GPU_HOST_TRANSLATION_ENABLE_BASE_IDX 1 1332 #define regMMVM_IOMMU_CONTROL_REGISTER 0x0b97 1333 #define regMMVM_IOMMU_CONTROL_REGISTER_BASE_IDX 1 1334 #define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 0x0b98 1335 #define regMMVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_BASE_IDX 1 1336 #define regMMUTC_TRANSLATION_FAULT_CNTL0 0x0b99 1337 #define regMMUTC_TRANSLATION_FAULT_CNTL0_BASE_IDX 1 1338 #define regMMUTC_TRANSLATION_FAULT_CNTL1 0x0b9a 1339 #define regMMUTC_TRANSLATION_FAULT_CNTL1_BASE_IDX 1 1340 #define regMMUTCL2_VSCH_POWER_STATUS 0x0b9b 1341 #define regMMUTCL2_VSCH_POWER_STATUS_BASE_IDX 1 1342 1343 1344 // addressBlock: mmhub_mmutcl2_mml2tlbpspdec 1345 // base address: 0x6ae80 1346 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL 0x0ba0 1347 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_CNTL_BASE_IDX 1 1348 1349 1350 // addressBlock: mmhub_mmutcl2_mmatcl2pspdec 1351 // base address: 0x6ae90 1352 #define regMM_ATC_L2_IOV_MODE_CNTL 0x0ba4 1353 #define regMM_ATC_L2_IOV_MODE_CNTL_BASE_IDX 1 1354 1355 1356 // addressBlock: mmhub_mmutcl2_mml2tlbpfdec 1357 // base address: 0x6aec0 1358 #define regMML2TLB_TLB0_STATUS 0x0bb1 1359 #define regMML2TLB_TLB0_STATUS_BASE_IDX 1 1360 #define regMML2TLB_TMZ_CNTL 0x0bb2 1361 #define regMML2TLB_TMZ_CNTL_BASE_IDX 1 1362 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 0x0bb3 1363 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO_BASE_IDX 1 1364 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 0x0bb4 1365 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI_BASE_IDX 1 1366 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 0x0bb5 1367 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO_BASE_IDX 1 1368 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 0x0bb6 1369 #define regMMUTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI_BASE_IDX 1 1370 #define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ 0x0bb7 1371 #define regMMUTCL2_L2TLB_CREDIT_SAFETY_FETCH_RDREQ_BASE_IDX 1 1372 1373 1374 // addressBlock: mmhub_mmutcl2_mml2tlbpldec 1375 // base address: 0x6af00 1376 #define regMML2TLB_PERFCOUNTER0_CFG 0x0bc0 1377 #define regMML2TLB_PERFCOUNTER0_CFG_BASE_IDX 1 1378 #define regMML2TLB_PERFCOUNTER1_CFG 0x0bc1 1379 #define regMML2TLB_PERFCOUNTER1_CFG_BASE_IDX 1 1380 #define regMML2TLB_PERFCOUNTER2_CFG 0x0bc2 1381 #define regMML2TLB_PERFCOUNTER2_CFG_BASE_IDX 1 1382 #define regMML2TLB_PERFCOUNTER3_CFG 0x0bc3 1383 #define regMML2TLB_PERFCOUNTER3_CFG_BASE_IDX 1 1384 #define regMML2TLB_PERFCOUNTER_RSLT_CNTL 0x0bc4 1385 #define regMML2TLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX 1 1386 1387 1388 // addressBlock: mmhub_mmutcl2_mml2tlbprdec 1389 // base address: 0x6af20 1390 #define regMML2TLB_PERFCOUNTER_LO 0x0bc8 1391 #define regMML2TLB_PERFCOUNTER_LO_BASE_IDX 1 1392 #define regMML2TLB_PERFCOUNTER_HI 0x0bc9 1393 #define regMML2TLB_PERFCOUNTER_HI_BASE_IDX 1 1394 1395 #endif 1396