1/* 2 * File : mips_cache_gcc.S 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Change Logs: 21 * Date Author Notes 22 * 2016��9��19�� Urey the first version 23 */ 24 25#ifndef __ASSEMBLY__ 26# define __ASSEMBLY__ 27#endif 28 29#include "../common/mips.h" 30 31 .text 32 .set noreorder 33 34 .globl cache_init 35 .ent cache_init 36cache_init: 37 .set noreorder 38 mtc0 zero, CP0_TAGLO 39 move t0, a0 // cache total size 40 move t1, a1 // cache line size 41 li t2, 0x80000000 42 addu t3, t0, t2 43 44_cache_init_loop: 45 cache 8, 0(t2) // icache_index_store_tag 46 cache 9, 0(t2) // dcache_index_store_tag 47 addu t2, t1 48 bne t2, t3, _cache_init_loop 49 nop 50 51 mfc0 t0, CP0_CONFIG 52 li t1, 0x7 53 not t1 54 and t0, t0, t1 55 or t0, 0x3 // cacheable, noncoherent, write-back, write allocate 56 mtc0 t0, CP0_CONFIG 57 58 jr ra 59 nop 60 61 .set reorder 62 .end cache_init 63