1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _mipi_backend_defs_h 8 #define _mipi_backend_defs_h 9 10 #include "mipi_backend_common_defs.h" 11 12 #define MIPI_BACKEND_REG_ALIGN 4 // assuming 32 bit control bus width 13 14 #define _HRT_MIPI_BACKEND_NOF_IRQS 3 // sid_lut 15 16 // SH Backend Register IDs 17 #define _HRT_MIPI_BACKEND_ENABLE_REG_IDX 0 18 #define _HRT_MIPI_BACKEND_STATUS_REG_IDX 1 19 //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX 2 20 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX 2 21 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX 3 22 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG2_IDX 4 23 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG3_IDX 5 24 #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX 6 25 #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX 7 26 #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX 8 27 #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX 9 28 #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX 10 29 //// 30 #define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX 11 31 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX 12 32 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX 13 33 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX 14 34 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P2_REG_IDX 15 35 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P3_REG_IDX 16 36 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P0_REG_IDX 17 37 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P1_REG_IDX 18 38 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P2_REG_IDX 19 39 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P3_REG_IDX 20 40 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P0_REG_IDX 21 41 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P1_REG_IDX 22 42 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P2_REG_IDX 23 43 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P3_REG_IDX 24 44 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX 25 45 //// 46 #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX 26 47 #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX 27 48 //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX 28 49 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX 28 50 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX 29 51 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX 30 52 #define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX 31 53 54 #define _HRT_MIPI_BACKEND_NOF_REGISTERS 32 // excluding the LP LUT entries 55 56 #define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX 32 57 58 ///////////////////////////////////////////////////////////////////////////////////////////////////// 59 #define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH 1 60 #define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH 1 61 //#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH 1 62 #define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH 32 63 #define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH 7 64 #define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH 9 65 #define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH 8 66 #define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH _HRT_MIPI_BACKEND_NOF_IRQS 67 #define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH 0 68 #define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH 1 69 #define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH 1 + 2 + 6 70 //#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH 1 71 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7 72 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7 73 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7 74 //#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7 75 76 ///////////////////////////////////////////////////////////////////////////////////////////////////// 77 78 #define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES 4 79 80 //#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES 16 // to satisfy hss model static array declaration 81 82 #define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH 2 83 #define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 6 84 #define _HRT_MIPI_BACKEND_PACKET_ID_WIDTH _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 85 86 #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB 0 87 #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB + (pix_width) - 1) 88 #define _HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) + 1) 89 #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) + 1) 90 #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) + (pix_width) - 1) 91 #define _HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) + 1) 92 #define _HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) + 1) 93 #define _HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) + 1) 94 #define _HRT_MIPI_BACKEND_STREAMING_WIDTH(pix_width) (_HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) + 1) 95 96 /*************************************************************************************************/ 97 /* Custom Decoding */ 98 /* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ 99 /*************************************************************************************************/ 100 #define _HRT_MIPI_BACKEND_CUST_EN_IDX 0 /* 2bits */ 101 #define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ 102 #define _HRT_MIPI_BACKEND_CUST_EN_HIGH_PREC_IDX 8 // 1 bit 103 #define _HRT_MIPI_BACKEND_CUST_EN_WIDTH 9 104 #define _HRT_MIPI_BACKEND_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ 105 #define _HRT_MIPI_BACKEND_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ 106 107 #define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX 1 108 109 /* Data State config = {get_bits(6bits), valid(1bit)} */ 110 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ 111 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX 8 /* 7bits */ 112 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S2_IDX 16 /* was 14 7bits */ 113 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_WIDTH 24 /* was 21*/ 114 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ 115 #define _HRT_MIPI_BACKEND_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ 116 117 /* Pixel Extractor config */ 118 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 6bits */ 119 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_ALIGN_IDX 6 /* 5bits */ 120 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_MASK_IDX 11 /* was 10 18bits */ 121 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_EN_IDX 29 /* was 28 1bits */ 122 123 #define _HRT_MIPI_BACKEND_CUST_PIX_EXT_WIDTH 30 /* was 29 */ 124 125 /* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ 126 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ 127 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ 128 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ 129 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ 130 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH 16 131 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ 132 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ 133 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ 134 #define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ 135 136 /*************************************************************************************************/ 137 /* MIPI backend output streaming interface definition */ 138 /* These parameters define the fields within the streaming bus. These should also be used by the */ 139 /* subsequent block, ie stream2mmio. */ 140 /*************************************************************************************************/ 141 /* The pipe backend - stream2mmio should be design time configurable in */ 142 /* PixWidth - Number of bits per pixel */ 143 /* PPC - Pixel per Clocks */ 144 /* NumSids - Max number of source Ids (ifc's) and derived from that: */ 145 /* SidWidth - Number of bits required for the sid parameter */ 146 /* In order to keep this configurability, below Macro's have these as a parameter */ 147 /*************************************************************************************************/ 148 149 #define HRT_MIPI_BACKEND_STREAM_EOP_BIT 0 150 #define HRT_MIPI_BACKEND_STREAM_SOP_BIT 1 151 #define HRT_MIPI_BACKEND_STREAM_EOF_BIT 2 152 #define HRT_MIPI_BACKEND_STREAM_SOF_BIT 3 153 #define HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT 4 154 #define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT + (sid_width) - 1) 155 #define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, p) (HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) + 1 + p) 156 157 #define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width, ppc) + ((pix_width) * p)) 158 #define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, p) + (pix_width) - 1) 159 160 #if 0 161 //#define HRT_MIPI_BACKEND_STREAM_PIX_BITS 14 162 //#define HRT_MIPI_BACKEND_STREAM_CHID_BITS 4 163 //#define HRT_MIPI_BACKEND_STREAM_PPC 4 164 #endif 165 166 #define HRT_MIPI_BACKEND_STREAM_BITS(sid_width, ppc, pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width, ppc, pix_width, (ppc - 1)) + 1) 167 168 /* SP and LP LUT BIT POSITIONS */ 169 #define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT 0 // 0 170 #define HRT_MIPI_BACKEND_LUT_SID_LS_BIT HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT + 1 // 1 171 #define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_LUT_SID_LS_BIT + (sid_width) - 1) // 1 + (4) - 1 = 4 172 #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 // 5 173 #define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH - 1 // 6 174 #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 175 #define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH - 1 // 12 176 177 /* #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 */ 178 179 #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 180 #define HRT_MIPI_BACKEND_LP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) + 1 // 13 181 182 // temp solution 183 //#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8 184 //#define HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT + 1 // 9 185 //#define HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT + 1 // 10 186 //#define HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT + 1 // 11 187 //#define HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT + 1 // 12 188 //#define HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 25 189 //#define HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT + 1 // 26 190 //#define HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 39 191 //#define HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT + 1 // 40 192 //#define HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 53 193 //#define HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT + 1 // 54 194 //#define HRT_MIPI_BACKEND_STREAM_PIXD_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 67 195 196 // vc hidden in pixb data (passed as raw12 the pipe) 197 #define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width, ppc, pix_width, 1) + 10 //HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + 10 // 36 198 #define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width, ppc, pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width, ppc, pix_width) + 1 // 37 199 200 #endif /* _mipi_backend_defs_h */ 201