1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <soc/addressmap.h>
4 #include <soc/clock.h>
5 #include <device/device.h>
6 #include <soc/nvidia/tegra/types.h>
7 #include <soc/display.h>
8 #include <soc/mipi_dsi.h>
9 #include <soc/mipi_display.h>
10 #include <soc/tegra_dsi.h>
11 #include <soc/mipi-phy.h>
12 #include <types.h>
13
mipi_dphy_set_timing(struct tegra_dsi * dsi)14 int mipi_dphy_set_timing(struct tegra_dsi *dsi)
15 {
16 u32 freq = (dsi->clk_rate * 2) / 1000000;
17
18 u32 thsdexit = (DSI_PHY_TIMING_DIV(120, (freq)));
19 u32 thstrial = (((3) + (DSI_PHY_TIMING_DIV((DSI_THSTRAIL_VAL(freq)),
20 freq))));
21 u32 tdatzero = DSI_PHY_TIMING_DIV(((145) + (5 * (DSI_TBIT(freq)))),
22 (freq));
23 u32 thsprepare = DSI_PHY_TIMING_DIV((65 + (5*(DSI_TBIT(freq)))), freq);
24 u32 tclktrial = (DSI_PHY_TIMING_DIV(80, freq));
25 u32 tclkpost = ((DSI_PHY_TIMING_DIV(((70) + ((52) * (DSI_TBIT(freq)))),
26 freq)));
27 u32 tclkzero = (DSI_PHY_TIMING_DIV(260, freq));
28 u32 ttlpx = (DSI_PHY_TIMING_DIV(60, freq));
29 u32 tclkprepare = (DSI_PHY_TIMING_DIV(60, freq));
30 u32 tclkpre = 1; //min = 8*UI per mipi spec, tclk_pre=0 should be ok, but using 1 value
31 u32 twakeup = 0x7F; //min = 1ms
32
33 u32 ttaget;
34 u32 ttassure;
35 u32 ttago;
36 u32 value;
37
38 if (!ttlpx) {
39 ttaget = 5;
40 ttassure = 2;
41 ttago = 4;
42 } else {
43 ttaget = 5 * ttlpx;
44 ttassure = 2 * ttlpx;
45 ttago = 4 * ttlpx;
46 }
47
48 value = (thsdexit << 24) |
49 (thstrial << 16) |
50 (tdatzero << 8) |
51 (thsprepare << 0);
52 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
53
54 value = (tclktrial << 24) |
55 (tclkpost << 16) |
56 (tclkzero << 8) |
57 (ttlpx << 0);
58 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
59
60 value = (tclkprepare << 16) |
61 (tclkpre << 8) |
62 (twakeup << 0);
63 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
64
65 value = (ttaget << 16) |
66 (ttassure << 8) |
67 (ttago << 0),
68 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
69 return 0;
70 }
71