1 /* 2 * Copyright (c) 2018, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vebox_hwcmd_g9_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g9_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_VEBOX_HWCMD_G9_X_H__ 29 #define __MHW_VEBOX_HWCMD_G9_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_vebox_g9_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief VEBOX_ACE_LACE_STATE 50 //! \details 51 //! This state structure contains the IECP State Table Contents for ACE 52 //! state. 53 //! 54 struct VEBOX_ACE_LACE_STATE_CMD 55 { 56 union 57 { 58 //!< DWORD 0 59 struct 60 { 61 uint32_t AceEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< ACE Enable 62 uint32_t Reserved1 : __CODEGEN_BITFIELD( 1, 1) ; //!< Reserved 63 uint32_t SkinThreshold : __CODEGEN_BITFIELD( 2, 6) ; //!< SKIN_THRESHOLD 64 uint32_t Reserved7 : __CODEGEN_BITFIELD( 7, 11) ; //!< Reserved 65 uint32_t LaceHistogramEnable : __CODEGEN_BITFIELD(12, 12) ; //!< LACE_HISTOGRAM_ENABLE 66 uint32_t LaceHistogramSize : __CODEGEN_BITFIELD(13, 13) ; //!< LACE_HISTOGRAM_SIZE 67 uint32_t LaceSingleHistogramSet : __CODEGEN_BITFIELD(14, 15) ; //!< LACE_SINGLE_HISTOGRAM_SET 68 uint32_t MinAceLuma : __CODEGEN_BITFIELD(16, 31) ; //!< Min_ACE_luma 69 }; 70 uint32_t Value; 71 } DW0; 72 union 73 { 74 //!< DWORD 1 75 struct 76 { 77 uint32_t Ymin : __CODEGEN_BITFIELD( 0, 7) ; //!< YMIN 78 uint32_t Y1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y1 79 uint32_t Y2 : __CODEGEN_BITFIELD(16, 23) ; //!< Y2 80 uint32_t Y3 : __CODEGEN_BITFIELD(24, 31) ; //!< Y3 81 }; 82 uint32_t Value; 83 } DW1; 84 union 85 { 86 //!< DWORD 2 87 struct 88 { 89 uint32_t Y4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y4 90 uint32_t Y5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y5 91 uint32_t Y6 : __CODEGEN_BITFIELD(16, 23) ; //!< Y6 92 uint32_t Y7 : __CODEGEN_BITFIELD(24, 31) ; //!< Y7 93 }; 94 uint32_t Value; 95 } DW2; 96 union 97 { 98 //!< DWORD 3 99 struct 100 { 101 uint32_t Y8 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y8 102 uint32_t Y9 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y9 103 uint32_t Y10 : __CODEGEN_BITFIELD(16, 23) ; //!< Y10 104 uint32_t Ymax : __CODEGEN_BITFIELD(24, 31) ; //!< YMAX 105 }; 106 uint32_t Value; 107 } DW3; 108 union 109 { 110 //!< DWORD 4 111 struct 112 { 113 uint32_t B1 : __CODEGEN_BITFIELD( 0, 7) ; //!< B1 114 uint32_t B2 : __CODEGEN_BITFIELD( 8, 15) ; //!< B2 115 uint32_t B3 : __CODEGEN_BITFIELD(16, 23) ; //!< B3 116 uint32_t B4 : __CODEGEN_BITFIELD(24, 31) ; //!< B4 117 }; 118 uint32_t Value; 119 } DW4; 120 union 121 { 122 //!< DWORD 5 123 struct 124 { 125 uint32_t B5 : __CODEGEN_BITFIELD( 0, 7) ; //!< B5 126 uint32_t B6 : __CODEGEN_BITFIELD( 8, 15) ; //!< B6 127 uint32_t B7 : __CODEGEN_BITFIELD(16, 23) ; //!< B7 128 uint32_t B8 : __CODEGEN_BITFIELD(24, 31) ; //!< B8 129 }; 130 uint32_t Value; 131 } DW5; 132 union 133 { 134 //!< DWORD 6 135 struct 136 { 137 uint32_t B9 : __CODEGEN_BITFIELD( 0, 7) ; //!< B9 138 uint32_t B10 : __CODEGEN_BITFIELD( 8, 15) ; //!< B10 139 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 140 }; 141 uint32_t Value; 142 } DW6; 143 union 144 { 145 //!< DWORD 7 146 struct 147 { 148 uint32_t S0 : __CODEGEN_BITFIELD( 0, 10) ; //!< S0 149 uint32_t Reserved235 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 150 uint32_t S1 : __CODEGEN_BITFIELD(16, 26) ; //!< S1 151 uint32_t Reserved251 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 152 }; 153 uint32_t Value; 154 } DW7; 155 union 156 { 157 //!< DWORD 8 158 struct 159 { 160 uint32_t S2 : __CODEGEN_BITFIELD( 0, 10) ; //!< S2 161 uint32_t Reserved267 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 162 uint32_t S3 : __CODEGEN_BITFIELD(16, 26) ; //!< S3 163 uint32_t Reserved283 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 164 }; 165 uint32_t Value; 166 } DW8; 167 union 168 { 169 //!< DWORD 9 170 struct 171 { 172 uint32_t S4 : __CODEGEN_BITFIELD( 0, 10) ; //!< S4 173 uint32_t Reserved299 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 174 uint32_t S5 : __CODEGEN_BITFIELD(16, 26) ; //!< S5 175 uint32_t Reserved315 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 176 }; 177 uint32_t Value; 178 } DW9; 179 union 180 { 181 //!< DWORD 10 182 struct 183 { 184 uint32_t S6 : __CODEGEN_BITFIELD( 0, 10) ; //!< S6 185 uint32_t Reserved331 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 186 uint32_t S7 : __CODEGEN_BITFIELD(16, 26) ; //!< S7 187 uint32_t Reserved347 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 188 }; 189 uint32_t Value; 190 } DW10; 191 union 192 { 193 //!< DWORD 11 194 struct 195 { 196 uint32_t S8 : __CODEGEN_BITFIELD( 0, 10) ; //!< S8 197 uint32_t Reserved363 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 198 uint32_t S9 : __CODEGEN_BITFIELD(16, 26) ; //!< S9 199 uint32_t Reserved379 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 200 }; 201 uint32_t Value; 202 } DW11; 203 union 204 { 205 //!< DWORD 12 206 struct 207 { 208 uint32_t S10 : __CODEGEN_BITFIELD( 0, 10) ; //!< S10 209 uint32_t Reserved395 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 210 uint32_t MaxAceLuma : __CODEGEN_BITFIELD(16, 31) ; //!< Max_ACE_luma 211 }; 212 uint32_t Value; 213 } DW12; 214 215 //! \name Local enumerations 216 217 //! \brief SKIN_THRESHOLD 218 //! \details 219 //! Used for Y analysis (min/max) for pixels which are higher than skin 220 //! threshold. 221 enum SKIN_THRESHOLD 222 { 223 SKIN_THRESHOLD_UNNAMED26 = 26, //!< No additional details 224 }; 225 226 //! \brief LACE_HISTOGRAM_ENABLE 227 //! \details 228 //! This bit enables the collection of LACE histogram data. If this bit is 0 229 //! then only the ACE histogram will be collected. 230 enum LACE_HISTOGRAM_ENABLE 231 { 232 LACE_HISTOGRAM_ENABLE_UNNAMED0 = 0, //!< No additional details 233 }; 234 235 enum LACE_HISTOGRAM_SIZE 236 { 237 LACE_HISTOGRAM_SIZE_128_BINHISTOGRAM = 0, //!< No additional details 238 LACE_HISTOGRAM_SIZE_256_BINHISTOGRAM = 1, //!< No additional details 239 }; 240 241 //! \brief LACE_SINGLE_HISTOGRAM_SET 242 //! \details 243 //! This bit tells LACE which frames will be included in the histogram when 244 //! the Deinterlacer is enabled. 245 enum LACE_SINGLE_HISTOGRAM_SET 246 { 247 LACE_SINGLE_HISTOGRAM_SET_CURRENT = 0, //!< The histogram includes only the current frame. 248 LACE_SINGLE_HISTOGRAM_SET_PREVIOUS = 1, //!< The histogram includes only the previous frame. 249 LACE_SINGLE_HISTOGRAM_SET_CURRENTPREVIOUS = 2, //!< The histogram includes pixels from both the current and previous frame. 250 LACE_SINGLE_HISTOGRAM_SET_PREVIOUSCURRENT = 3, //!< The histogram includes the previous frame followed by the current frame. 251 }; 252 253 //! \brief YMIN 254 //! \details 255 //! The value of the y_pixel for point 0 in PWL. 256 enum YMIN 257 { 258 YMIN_UNNAMED16 = 16, //!< No additional details 259 }; 260 261 //! \brief Y1 262 //! \details 263 //! The value of the y_pixel for point 1 in PWL. 264 enum Y1 265 { 266 Y1_UNNAMED36 = 36, //!< No additional details 267 }; 268 269 //! \brief Y2 270 //! \details 271 //! The value of the y_pixel for point 2 in PWL. 272 enum Y2 273 { 274 Y2_UNNAMED56 = 56, //!< No additional details 275 }; 276 277 //! \brief Y3 278 //! \details 279 //! The value of the y_pixel for point 3 in PWL. 280 enum Y3 281 { 282 Y3_UNNAMED76 = 76, //!< No additional details 283 }; 284 285 //! \brief Y4 286 //! \details 287 //! The value of the y_pixel for point 4 in PWL. 288 enum Y4 289 { 290 Y4_UNNAMED96 = 96, //!< No additional details 291 }; 292 293 //! \brief Y5 294 //! \details 295 //! The value of the y_pixel for point 5 in PWL. 296 enum Y5 297 { 298 Y5_UNNAMED116 = 116, //!< No additional details 299 }; 300 301 //! \brief Y6 302 //! \details 303 //! The value of the y_pixel for point 6 in PWL. 304 enum Y6 305 { 306 Y6_UNNAMED136 = 136, //!< No additional details 307 }; 308 309 //! \brief Y7 310 //! \details 311 //! The value of the y_pixel for point 7 in PWL. 312 enum Y7 313 { 314 Y7_UNNAMED156 = 156, //!< No additional details 315 }; 316 317 //! \brief Y8 318 //! \details 319 //! The value of the y_pixel for point 8 in PWL. 320 enum Y8 321 { 322 Y8_UNNAMED176 = 176, //!< No additional details 323 }; 324 325 //! \brief Y9 326 //! \details 327 //! The value of the y_pixel for point 9 in PWL. 328 enum Y9 329 { 330 Y9_UNNAMED196 = 196, //!< No additional details 331 }; 332 333 //! \brief Y10 334 //! \details 335 //! The value of the y_pixel for point 10 in PWL. 336 enum Y10 337 { 338 Y10_UNNAMED216 = 216, //!< No additional details 339 }; 340 341 //! \brief YMAX 342 //! \details 343 //! The value of the y_pixel for point 11 in PWL. 344 enum YMAX 345 { 346 YMAX_UNNAMED235 = 235, //!< No additional details 347 }; 348 349 //! \brief B1 350 //! \details 351 //! The value of the bias for point 1 in PWL. 352 enum B1 353 { 354 B1_UNNAMED36 = 36, //!< No additional details 355 }; 356 357 //! \brief B2 358 //! \details 359 //! The value of the bias for point 2 in PWL. 360 enum B2 361 { 362 B2_UNNAMED56 = 56, //!< No additional details 363 }; 364 365 //! \brief B3 366 //! \details 367 //! The value of the bias for point 3 in PWL. 368 enum B3 369 { 370 B3_UNNAMED76 = 76, //!< No additional details 371 }; 372 373 //! \brief B4 374 //! \details 375 //! The value of the bias for point 4 in PWL. 376 enum B4 377 { 378 B4_UNNAMED96 = 96, //!< No additional details 379 }; 380 381 //! \brief B5 382 //! \details 383 //! The value of the bias for point 5 in PWL. 384 enum B5 385 { 386 B5_UNNAMED116 = 116, //!< No additional details 387 }; 388 389 //! \brief B6 390 //! \details 391 //! The value of the bias for point 6 in PWL. 392 enum B6 393 { 394 B6_UNNAMED136 = 136, //!< No additional details 395 }; 396 397 //! \brief B7 398 //! \details 399 //! The value of the bias for point 7 in PWL. 400 enum B7 401 { 402 B7_UNNAMED156 = 156, //!< No additional details 403 }; 404 405 //! \brief B8 406 //! \details 407 //! The value of the bias for point 8 in PWL. 408 enum B8 409 { 410 B8_UNNAMED176 = 176, //!< No additional details 411 }; 412 413 //! \brief B9 414 //! \details 415 //! The value of the bias for point 9 in PWL. 416 enum B9 417 { 418 B9_UNNAMED196 = 196, //!< No additional details 419 }; 420 421 //! \brief B10 422 //! \details 423 //! The value of the bias for point 10 in PWL. 424 enum B10 425 { 426 B10_UNNAMED216 = 216, //!< No additional details 427 }; 428 429 //! \brief S0 430 //! \details 431 //! The value of the slope for point 0 in PWL 432 enum S0 433 { 434 S0_UNNAMED1024 = 1024, //!< No additional details 435 }; 436 437 //! \brief S1 438 //! \details 439 //! The value of the slope for point 1 in PWL 440 enum S1 441 { 442 S1_UNNAMED1024 = 1024, //!< No additional details 443 }; 444 445 //! \brief S2 446 //! \details 447 //! The value of the slope for point 2 in PWL 448 enum S2 449 { 450 S2_UNNAMED1024 = 1024, //!< No additional details 451 }; 452 453 //! \brief S3 454 //! \details 455 //! The value of the slope for point 3 in PWL 456 enum S3 457 { 458 S3_UNNAMED1024 = 1024, //!< No additional details 459 }; 460 461 //! \brief S4 462 //! \details 463 //! The value of the slope for point 4 in PWL 464 enum S4 465 { 466 S4_UNNAMED1024 = 1024, //!< No additional details 467 }; 468 469 //! \brief S5 470 //! \details 471 //! The value of the slope for point 5 in PWL 472 enum S5 473 { 474 S5_UNNAMED1024 = 1024, //!< No additional details 475 }; 476 477 //! \brief S6 478 //! \details 479 //! The default is 1024/1024 480 enum S6 481 { 482 S6_UNNAMED1024 = 1024, //!< No additional details 483 }; 484 485 //! \brief S7 486 //! \details 487 //! The value of the slope for point 7 in PWL 488 enum S7 489 { 490 S7_UNNAMED1024 = 1024, //!< No additional details 491 }; 492 493 //! \brief S8 494 //! \details 495 //! The value of the slope for point 8 in PWL 496 enum S8 497 { 498 S8_UNNAMED1024 = 1024, //!< No additional details 499 }; 500 501 //! \brief S9 502 //! \details 503 //! The value of the slope for point 9 in PWL 504 enum S9 505 { 506 S9_UNNAMED1024 = 1024, //!< No additional details 507 }; 508 509 //! \brief S10 510 //! \details 511 //! The value of the slope for point 10 in PWL. 512 enum S10 513 { 514 S10_UNNAMED1024 = 1024, //!< No additional details 515 }; 516 517 //! \name Initializations 518 519 //! \brief Explicit member initialization function 520 VEBOX_ACE_LACE_STATE_CMD(); 521 522 static const size_t dwSize = 13; 523 static const size_t byteSize = 52; 524 }; 525 526 //! 527 //! \brief VEBOX_ALPHA_AOI_STATE 528 //! \details 529 //! This state structure contains the IECP State Table Contents for Fixed 530 //! Alpha State and Area of Interest State. 531 //! 532 struct VEBOX_ALPHA_AOI_STATE_CMD 533 { 534 union 535 { 536 //!< DWORD 0 537 struct 538 { 539 uint32_t ColorPipeAlpha : __CODEGEN_BITFIELD( 0, 15) ; //!< Color Pipe Alpha 540 uint32_t AlphaFromStateSelect : __CODEGEN_BITFIELD(16, 16) ; //!< ALPHA_FROM_STATE_SELECT 541 uint32_t FullImageHistogram : __CODEGEN_BITFIELD(17, 17) ; //!< FULL_IMAGE_HISTOGRAM 542 uint32_t Reserved18 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 543 }; 544 uint32_t Value; 545 } DW0; 546 union 547 { 548 //!< DWORD 1 549 struct 550 { 551 uint32_t AoiMinX : __CODEGEN_BITFIELD( 0, 13) ; //!< AOI_MIN_X 552 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 553 uint32_t AoiMaxX : __CODEGEN_BITFIELD(16, 29) ; //!< AOI_MAX_X 554 uint32_t Reserved62 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 555 }; 556 uint32_t Value; 557 } DW1; 558 union 559 { 560 //!< DWORD 2 561 struct 562 { 563 uint32_t AoiMinY : __CODEGEN_BITFIELD( 0, 13) ; //!< AOI_MIN_Y 564 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 565 uint32_t AoiMaxY : __CODEGEN_BITFIELD(16, 29) ; //!< AOI_MAX_Y 566 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 567 }; 568 uint32_t Value; 569 } DW2; 570 571 //! \name Local enumerations 572 573 //! \brief ALPHA_FROM_STATE_SELECT 574 //! \details 575 //! If the input format does not have alpha available and the output format 576 //! provides alpha, this bit should be set to 1. 577 //! This should be 0 when Alpha Plane Enable is 1. 578 enum ALPHA_FROM_STATE_SELECT 579 { 580 ALPHA_FROM_STATE_SELECT_ALPHAISTAKENFROMMESSAGE = 0, //!< No additional details 581 ALPHA_FROM_STATE_SELECT_ALPHAISTAKENFROMSTATE = 1, //!< No additional details 582 }; 583 584 //! \brief FULL_IMAGE_HISTOGRAM 585 //! \details 586 //! Used to ignore the area of interest for a histogram across the full 587 //! image. This applies to all statistics that are affected by AOI (Area of 588 //! Interest). 589 enum FULL_IMAGE_HISTOGRAM 590 { 591 FULL_IMAGE_HISTOGRAM_UNNAMED0 = 0, //!< No additional details 592 }; 593 594 //! \brief AOI_MIN_X 595 //! \details 596 //! <b>This value must be a multiple of 4.</b> 597 enum AOI_MIN_X 598 { 599 AOI_MIN_X_UNNAMED0 = 0, //!< No additional details 600 }; 601 602 //! \brief AOI_MAX_X 603 //! \details 604 //! Area of Interest Minimum X - The ACE histogram and Skin Tone Detection 605 //! statistic gathering will occur within the MinX/MinY to MaxX/MaxY area 606 //! (inclusive). 607 //! AOI must intersect the frame such that at least 1 608 //! pixel is in the AOI. 609 enum AOI_MAX_X 610 { 611 AOI_MAX_X_UNNAMED3 = 3, //!< No additional details 612 }; 613 614 //! \brief AOI_MIN_Y 615 //! \details 616 //! <b>This value must be a multiple of 4.</b> 617 enum AOI_MIN_Y 618 { 619 AOI_MIN_Y_UNNAMED0 = 0, //!< No additional details 620 }; 621 622 //! \brief AOI_MAX_Y 623 //! \details 624 //! <b>This value must be a multiple of 4 minus 1.</b> 625 enum AOI_MAX_Y 626 { 627 AOI_MAX_Y_UNNAMED3 = 3, //!< No additional details 628 }; 629 630 //! \name Initializations 631 632 //! \brief Explicit member initialization function 633 VEBOX_ALPHA_AOI_STATE_CMD(); 634 635 static const size_t dwSize = 3; 636 static const size_t byteSize = 12; 637 }; 638 639 //! 640 //! \brief VEBOX_CAPTURE_PIPE_STATE 641 //! \details 642 //! This command contains variables for controlling Demosaic and the White 643 //! Balance Statistics. 644 //! 645 struct VEBOX_CAPTURE_PIPE_STATE_CMD 646 { 647 union 648 { 649 //!< DWORD 0 650 struct 651 { 652 uint32_t GoodPixelNeighborThreshold : __CODEGEN_BITFIELD( 0, 5) ; //!< GOOD_PIXEL_NEIGHBOR_THRESHOLD 653 uint32_t Reserved6 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 654 uint32_t AverageColorThreshold : __CODEGEN_BITFIELD( 8, 15) ; //!< AVERAGE_COLOR_THRESHOLD 655 uint32_t GreenImbalanceThreshold : __CODEGEN_BITFIELD(16, 19) ; //!< GREEN_IMBALANCE_THRESHOLD 656 uint32_t ShiftMinCost : __CODEGEN_BITFIELD(20, 22) ; //!< SHIFT_MIN_COST 657 uint32_t Reserved23 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 658 uint32_t GoodPixelThreshold : __CODEGEN_BITFIELD(24, 29) ; //!< GOOD_PIXEL_THRESHOLD 659 uint32_t Reserved30 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 660 }; 661 uint32_t Value; 662 } DW0; 663 union 664 { 665 //!< DWORD 1 666 struct 667 { 668 uint32_t BadColorThreshold3 : __CODEGEN_BITFIELD( 0, 3) ; //!< BAD_COLOR_THRESHOLD_3 669 uint32_t NumberBigPixelThreshold : __CODEGEN_BITFIELD( 4, 7) ; //!< NUMBER_BIG_PIXEL_THRESHOLD 670 uint32_t BadColorThreshold2 : __CODEGEN_BITFIELD( 8, 15) ; //!< BAD_COLOR_THRESHOLD_2 671 uint32_t BadColorThreshold1 : __CODEGEN_BITFIELD(16, 23) ; //!< BAD_COLOR_THRESHOLD_1 672 uint32_t GoodIntesityThreshold : __CODEGEN_BITFIELD(24, 27) ; //!< GOOD_INTESITY_THRESHOLD 673 uint32_t ScaleForMinCost : __CODEGEN_BITFIELD(28, 31) ; //!< SCALE_FOR_MIN_COST 674 }; 675 uint32_t Value; 676 } DW1; 677 union 678 { 679 //!< DWORD 2 680 struct 681 { 682 uint32_t WhiteBalanceCorrectionEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< White Balance Correction Enable 683 uint32_t BlackPointCorrectionEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Black Point Correction Enable 684 uint32_t VignetteCorrectionFormat : __CODEGEN_BITFIELD( 2, 2) ; //!< VIGNETTE_CORRECTION_FORMAT 685 uint32_t RgbHistogramEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< RGB Histogram Enable 686 uint32_t BlackPointOffsetGreenBottomMsb : __CODEGEN_BITFIELD( 4, 4) ; //!< Black Point Offset Green Bottom MSB 687 uint32_t BlackPointOffsetBlueMsb : __CODEGEN_BITFIELD( 5, 5) ; //!< Black Point Offset Blue MSB 688 uint32_t BlackPointOffsetGreenTopMsb : __CODEGEN_BITFIELD( 6, 6) ; //!< Black Point Offset Green Top MSB 689 uint32_t BlackPointOffsetRedMsb : __CODEGEN_BITFIELD( 7, 7) ; //!< Black Point Offset Red MSB 690 uint32_t UvThresholdValue : __CODEGEN_BITFIELD( 8, 15) ; //!< UV_THRESHOLD_VALUE 691 uint32_t YOutlierValue : __CODEGEN_BITFIELD(16, 23) ; //!< Y_OUTLIER_VALUE 692 uint32_t YBrightValue : __CODEGEN_BITFIELD(24, 31) ; //!< Y_BRIGHT_VALUE 693 }; 694 uint32_t Value; 695 } DW2; 696 union 697 { 698 //!< DWORD 3 699 struct 700 { 701 uint32_t BlackPointOffsetGreenTop : __CODEGEN_BITFIELD( 0, 15) ; //!< BLACK_POINT_OFFSET_GREEN_TOP 702 uint32_t BlackPointOffsetRed : __CODEGEN_BITFIELD(16, 31) ; //!< BLACK_POINT_OFFSET_RED 703 }; 704 uint32_t Value; 705 } DW3; 706 union 707 { 708 //!< DWORD 4 709 struct 710 { 711 uint32_t BlackPointOffsetGreenBottom : __CODEGEN_BITFIELD( 0, 15) ; //!< BLACK_POINT_OFFSET_GREEN_BOTTOM 712 uint32_t BlackPointOffsetBlue : __CODEGEN_BITFIELD(16, 31) ; //!< BLACK_POINT_OFFSET_BLUE 713 }; 714 uint32_t Value; 715 } DW4; 716 union 717 { 718 //!< DWORD 5 719 struct 720 { 721 uint32_t WhiteBalanceGreenTopCorrection : __CODEGEN_BITFIELD( 0, 15) ; //!< White Balance Green Top Correction 722 uint32_t WhiteBalanceRedCorrection : __CODEGEN_BITFIELD(16, 31) ; //!< White Balance Red Correction 723 }; 724 uint32_t Value; 725 } DW5; 726 union 727 { 728 //!< DWORD 6 729 struct 730 { 731 uint32_t WhiteBalanceGreenBottomCorrection : __CODEGEN_BITFIELD( 0, 15) ; //!< White Balance Green Bottom Correction 732 uint32_t WhiteBalanceBlueCorrection : __CODEGEN_BITFIELD(16, 31) ; //!< White Balance Blue Correction 733 }; 734 uint32_t Value; 735 } DW6; 736 737 //! \name Local enumerations 738 739 //! \brief GOOD_PIXEL_NEIGHBOR_THRESHOLD 740 //! \details 741 //! Number of comparisons with neighbor pixels which pass before a pixel is 742 //! considered good. 743 enum GOOD_PIXEL_NEIGHBOR_THRESHOLD 744 { 745 GOOD_PIXEL_NEIGHBOR_THRESHOLD_UNNAMED35 = 35, //!< No additional details 746 }; 747 748 //! \brief AVERAGE_COLOR_THRESHOLD 749 //! \details 750 //! The threshold between two colors in a pixel for the Avg interpolation to 751 //! be considered. 752 enum AVERAGE_COLOR_THRESHOLD 753 { 754 AVERAGE_COLOR_THRESHOLD_UNNAMED255 = 255, //!< No additional details 755 }; 756 757 enum GREEN_IMBALANCE_THRESHOLD 758 { 759 GREEN_IMBALANCE_THRESHOLD_UNNAMED1 = 1, //!< No additional details 760 }; 761 762 //! \brief SHIFT_MIN_COST 763 //! \details 764 //! The amount to shift the H2/V2 versions of min_cost. 765 enum SHIFT_MIN_COST 766 { 767 SHIFT_MIN_COST_UNNAMED1 = 1, //!< No additional details 768 }; 769 770 //! \brief GOOD_PIXEL_THRESHOLD 771 //! \details 772 //! The difference threshold between adjacent pixels for a pixel to be 773 //! considered "good". 774 enum GOOD_PIXEL_THRESHOLD 775 { 776 GOOD_PIXEL_THRESHOLD_UNNAMED5 = 5, //!< No additional details 777 }; 778 779 //! \brief BAD_COLOR_THRESHOLD_3 780 //! \details 781 //! Color value threshold used during the bad pixel check. 782 enum BAD_COLOR_THRESHOLD_3 783 { 784 BAD_COLOR_THRESHOLD_3_UNNAMED10 = 10, //!< No additional details 785 }; 786 787 //! \brief NUMBER_BIG_PIXEL_THRESHOLD 788 //! \details 789 //! Number of comparisons with neighbor pixels which pass before a pixel is 790 //! considered good. 791 enum NUMBER_BIG_PIXEL_THRESHOLD 792 { 793 NUMBER_BIG_PIXEL_THRESHOLD_UNNAMED10 = 10, //!< No additional details 794 }; 795 796 //! \brief BAD_COLOR_THRESHOLD_2 797 //! \details 798 //! Color value threshold used during the bad pixel check. 799 enum BAD_COLOR_THRESHOLD_2 800 { 801 BAD_COLOR_THRESHOLD_2_UNNAMED175 = 175, //!< No additional details 802 }; 803 804 //! \brief BAD_COLOR_THRESHOLD_1 805 //! \details 806 //! Color value threshold used during the bad pixel check. 807 enum BAD_COLOR_THRESHOLD_1 808 { 809 BAD_COLOR_THRESHOLD_1_UNNAMED100 = 100, //!< No additional details 810 }; 811 812 enum GOOD_INTESITY_THRESHOLD 813 { 814 GOOD_INTESITY_THRESHOLD_UNNAMED10 = 10, //!< No additional details 815 }; 816 817 //! \brief SCALE_FOR_MIN_COST 818 //! \details 819 //! The amount to scale the min_cost difference during the confidence check. 820 enum SCALE_FOR_MIN_COST 821 { 822 SCALE_FOR_MIN_COST_UNNAMED10 = 10, //!< No additional details 823 }; 824 825 //! \brief VIGNETTE_CORRECTION_FORMAT 826 //! \details 827 //! Defines what shift should be assumed for the <b>Vignette</b> Correction 828 //! input values: 829 enum VIGNETTE_CORRECTION_FORMAT 830 { 831 VIGNETTE_CORRECTION_FORMAT_U88 = 0, //!< No additional details 832 VIGNETTE_CORRECTION_FORMAT_U412 = 1, //!< No additional details 833 }; 834 835 //! \brief UV_THRESHOLD_VALUE 836 //! \details 837 //! The value denotes the maximum threshold of the ratio between U+V to Y 838 //! can have to be considered a gray point. 839 enum UV_THRESHOLD_VALUE 840 { 841 UV_THRESHOLD_VALUE_UNNAMED64 = 64, //!< 0.25 * 255 = 64 842 }; 843 844 //! \brief Y_OUTLIER_VALUE 845 //! \details 846 //! The outlier threshold percentile in the Y histogram. Any pixel with Y 847 //! value above this either clipped or an outlier in the image. These points 848 //! will not be included in the white patch calculation. 849 enum Y_OUTLIER_VALUE 850 { 851 Y_OUTLIER_VALUE_UNNAMED253 = 253, //!< No additional details 852 }; 853 854 //! \brief Y_BRIGHT_VALUE 855 //! \details 856 //! The whitepoint threshold percentile in the Y histogram. Any pixel with Y 857 //! value above this could be a whitepoint. 858 //! This is the larger of the calculated Ybright value 859 //! and the Ythreshold value, which is the minimum Y required to be 860 //! considered a white point. 861 enum Y_BRIGHT_VALUE 862 { 863 Y_BRIGHT_VALUE_UNNAMED230 = 230, //!< No additional details 864 }; 865 866 //! \brief BLACK_POINT_OFFSET_GREEN_TOP 867 //! \details 868 //! Value subtracted from the top Green pixels of Bayer pattern (X=1, Y=0 869 //! for Bayer Pattern #1) - combined with MSB to form a 2's complement 870 //! signed number. 871 enum BLACK_POINT_OFFSET_GREEN_TOP 872 { 873 BLACK_POINT_OFFSET_GREEN_TOP_UNNAMED0 = 0, //!< No additional details 874 }; 875 876 //! \brief BLACK_POINT_OFFSET_RED 877 //! \details 878 //! Value subtracted from Red pixels of Bayer pattern - combined with MSB to 879 //! form a 2's complement signed number. 880 enum BLACK_POINT_OFFSET_RED 881 { 882 BLACK_POINT_OFFSET_RED_UNNAMED0 = 0, //!< No additional details 883 }; 884 885 //! \brief BLACK_POINT_OFFSET_GREEN_BOTTOM 886 //! \details 887 //! Value subtracted from the bottom Green pixels of Bayer pattern (X=0, Y=1 888 //! for Bayer Pattern #1) - combined with MSB to form a 2's complement 889 //! signed number. 890 enum BLACK_POINT_OFFSET_GREEN_BOTTOM 891 { 892 BLACK_POINT_OFFSET_GREEN_BOTTOM_UNNAMED0 = 0, //!< No additional details 893 }; 894 895 //! \brief BLACK_POINT_OFFSET_BLUE 896 //! \details 897 //! Value subtracted from Blue pixels of Bayer pattern - Combine with MSB to 898 //! form a 2's complement signed number. 899 enum BLACK_POINT_OFFSET_BLUE 900 { 901 BLACK_POINT_OFFSET_BLUE_UNNAMED0 = 0, //!< No additional details 902 }; 903 904 //! \name Initializations 905 906 //! \brief Explicit member initialization function 907 VEBOX_CAPTURE_PIPE_STATE_CMD(); 908 909 static const size_t dwSize = 7; 910 static const size_t byteSize = 28; 911 }; 912 913 //! 914 //! \brief VEBOX_CCM_STATE 915 //! \details 916 //! This state structure contains the IECP State Table Contents for the 917 //! Color Correction Matrix State. 918 //! 919 struct VEBOX_CCM_STATE_CMD 920 { 921 union 922 { 923 //!< DWORD 0 924 struct 925 { 926 uint32_t C1 : __CODEGEN_BITFIELD( 0, 16) ; //!< C1 927 uint32_t Reserved17 : __CODEGEN_BITFIELD(17, 30) ; //!< Reserved 928 uint32_t ColorCorrectionMatrixEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Color Correction Matrix Enable 929 }; 930 uint32_t Value; 931 } DW0; 932 union 933 { 934 //!< DWORD 1 935 struct 936 { 937 uint32_t C0 : __CODEGEN_BITFIELD( 0, 16) ; //!< C0 938 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 939 }; 940 uint32_t Value; 941 } DW1; 942 union 943 { 944 //!< DWORD 2 945 struct 946 { 947 uint32_t C3 : __CODEGEN_BITFIELD( 0, 16) ; //!< C3 948 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 949 }; 950 uint32_t Value; 951 } DW2; 952 union 953 { 954 //!< DWORD 3 955 struct 956 { 957 uint32_t C2 : __CODEGEN_BITFIELD( 0, 16) ; //!< C2 958 uint32_t Reserved113 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 959 }; 960 uint32_t Value; 961 } DW3; 962 union 963 { 964 //!< DWORD 4 965 struct 966 { 967 uint32_t C5 : __CODEGEN_BITFIELD( 0, 16) ; //!< C5 968 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 969 }; 970 uint32_t Value; 971 } DW4; 972 union 973 { 974 //!< DWORD 5 975 struct 976 { 977 uint32_t C4 : __CODEGEN_BITFIELD( 0, 16) ; //!< C4 978 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 979 }; 980 uint32_t Value; 981 } DW5; 982 union 983 { 984 //!< DWORD 6 985 struct 986 { 987 uint32_t C7 : __CODEGEN_BITFIELD( 0, 16) ; //!< C7 988 uint32_t Reserved209 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 989 }; 990 uint32_t Value; 991 } DW6; 992 union 993 { 994 //!< DWORD 7 995 struct 996 { 997 uint32_t C6 : __CODEGEN_BITFIELD( 0, 16) ; //!< C6 998 uint32_t Reserved241 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 999 }; 1000 uint32_t Value; 1001 } DW7; 1002 union 1003 { 1004 //!< DWORD 8 1005 struct 1006 { 1007 uint32_t C8 : __CODEGEN_BITFIELD( 0, 16) ; //!< C8 1008 uint32_t Reserved273 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1009 }; 1010 uint32_t Value; 1011 } DW8; 1012 1013 //! \name Local enumerations 1014 1015 //! \brief C1 1016 //! \details 1017 //! Coefficient of 3x3 Transform matrix 1018 enum C1 1019 { 1020 C1_11414096 = 1141, //!< No additional details 1021 }; 1022 1023 //! \brief C0 1024 //! \details 1025 //! Coefficient of 3x3 Transform matrix 1026 enum C0 1027 { 1028 C0_27924096 = 2792, //!< No additional details 1029 }; 1030 1031 //! \brief C3 1032 //! \details 1033 //! Coefficient of 3x3 Transform matrix 1034 enum C3 1035 { 1036 C3_714096 = 71, //!< No additional details 1037 }; 1038 1039 //! \brief C2 1040 //! \details 1041 //! Coefficient of 3x3 Transform matrix 1042 enum C2 1043 { 1044 C2_344096 = 34, //!< No additional details 1045 }; 1046 1047 //! \brief C5 1048 //! \details 1049 //! Coefficient of 3x3 Transform matrix 1050 enum C5 1051 { 1052 C5_524096 = 131020, //!< No additional details 1053 }; 1054 1055 //! \brief C4 1056 //! \details 1057 //! Coefficient of 3x3 Transform matrix 1058 enum C4 1059 { 1060 C4_33634096 = 3363, //!< No additional details 1061 }; 1062 1063 //! \brief C7 1064 //! \details 1065 //! Coefficient of 3x3 Transform matrix 1066 enum C7 1067 { 1068 C7_1684096 = 168, //!< No additional details 1069 }; 1070 1071 //! \brief C6 1072 //! \details 1073 //! Coefficient of 3x3 Transform matrix 1074 enum C6 1075 { 1076 C6_124096 = 131060, //!< No additional details 1077 }; 1078 1079 //! \brief C8 1080 //! \details 1081 //! Coefficient of 3x3 Transform matrix 1082 enum C8 1083 { 1084 C8_34344096 = 3434, //!< No additional details 1085 }; 1086 1087 //! \name Initializations 1088 1089 //! \brief Explicit member initialization function 1090 VEBOX_CCM_STATE_CMD(); 1091 1092 static const size_t dwSize = 9; 1093 static const size_t byteSize = 36; 1094 }; 1095 1096 //! 1097 //! \brief VEBOX_CSC_STATE 1098 //! \details 1099 //! This state structure contains the IECP State Table Contents for CSC 1100 //! state. 1101 //! 1102 struct VEBOX_CSC_STATE_CMD 1103 { 1104 union 1105 { 1106 //!< DWORD 0 1107 struct 1108 { 1109 uint32_t C0 : __CODEGEN_BITFIELD( 0, 18) ; //!< C0 1110 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 29) ; //!< Reserved 1111 uint32_t YuvChannelSwap : __CODEGEN_BITFIELD(30, 30) ; //!< YUV_CHANNEL_SWAP 1112 uint32_t TransformEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Transform Enable 1113 }; 1114 uint32_t Value; 1115 } DW0; 1116 union 1117 { 1118 //!< DWORD 1 1119 struct 1120 { 1121 uint32_t C1 : __CODEGEN_BITFIELD( 0, 18) ; //!< C1 1122 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1123 }; 1124 uint32_t Value; 1125 } DW1; 1126 union 1127 { 1128 //!< DWORD 2 1129 struct 1130 { 1131 uint32_t C2 : __CODEGEN_BITFIELD( 0, 18) ; //!< C2 1132 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1133 }; 1134 uint32_t Value; 1135 } DW2; 1136 union 1137 { 1138 //!< DWORD 3 1139 struct 1140 { 1141 uint32_t C3 : __CODEGEN_BITFIELD( 0, 18) ; //!< C3 1142 uint32_t Reserved115 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1143 }; 1144 uint32_t Value; 1145 } DW3; 1146 union 1147 { 1148 //!< DWORD 4 1149 struct 1150 { 1151 uint32_t C4 : __CODEGEN_BITFIELD( 0, 18) ; //!< C4 1152 uint32_t Reserved147 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1153 }; 1154 uint32_t Value; 1155 } DW4; 1156 union 1157 { 1158 //!< DWORD 5 1159 struct 1160 { 1161 uint32_t C5 : __CODEGEN_BITFIELD( 0, 18) ; //!< C5 1162 uint32_t Reserved179 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1163 }; 1164 uint32_t Value; 1165 } DW5; 1166 union 1167 { 1168 //!< DWORD 6 1169 struct 1170 { 1171 uint32_t C6 : __CODEGEN_BITFIELD( 0, 18) ; //!< C6 1172 uint32_t Reserved211 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1173 }; 1174 uint32_t Value; 1175 } DW6; 1176 union 1177 { 1178 //!< DWORD 7 1179 struct 1180 { 1181 uint32_t C7 : __CODEGEN_BITFIELD( 0, 18) ; //!< C7 1182 uint32_t Reserved243 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1183 }; 1184 uint32_t Value; 1185 } DW7; 1186 union 1187 { 1188 //!< DWORD 8 1189 struct 1190 { 1191 uint32_t C8 : __CODEGEN_BITFIELD( 0, 18) ; //!< C8 1192 uint32_t Reserved275 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1193 }; 1194 uint32_t Value; 1195 } DW8; 1196 union 1197 { 1198 //!< DWORD 9 1199 struct 1200 { 1201 uint32_t OffsetIn1 : __CODEGEN_BITFIELD( 0, 15) ; //!< OFFSET_IN_1 1202 uint32_t OffsetOut1 : __CODEGEN_BITFIELD(16, 31) ; //!< OFFSET_OUT_1 1203 }; 1204 uint32_t Value; 1205 } DW9; 1206 union 1207 { 1208 //!< DWORD 10 1209 struct 1210 { 1211 uint32_t OffsetIn2 : __CODEGEN_BITFIELD( 0, 15) ; //!< OFFSET_IN_2 1212 uint32_t OffsetOut2 : __CODEGEN_BITFIELD(16, 31) ; //!< OFFSET_OUT_2 1213 }; 1214 uint32_t Value; 1215 } DW10; 1216 union 1217 { 1218 //!< DWORD 11 1219 struct 1220 { 1221 uint32_t OffsetIn3 : __CODEGEN_BITFIELD( 0, 15) ; //!< OFFSET_IN_3 1222 uint32_t OffsetOut3 : __CODEGEN_BITFIELD(16, 31) ; //!< OFFSET_OUT_3 1223 }; 1224 uint32_t Value; 1225 } DW11; 1226 1227 //! \name Local enumerations 1228 1229 //! \brief C0 1230 //! \details 1231 //! Transform coefficient. 1232 enum C0 1233 { 1234 C0_OR10 = 65536, //!< No additional details 1235 }; 1236 1237 //! \brief YUV_CHANNEL_SWAP 1238 //! \details 1239 //! This bit should only be used with R8G8B8A8 output formats. When this bit 1240 //! is set, the YUV channels are swapped into the output RGB channels as 1241 //! shown in the following table to support B8G8R8A8 output on surface 1242 //! format R8G8B8A8: 1243 //! <table> 1244 //! <tr> 1245 //! <td></td> 1246 //! <td>YUV_Channel_Swap</td> 1247 //! </tr> 1248 //! <tr> 1249 //! <td> </td> 1250 //! <td> 0 --> 1</td> 1251 //! </tr> 1252 //! <tr> 1253 //! <td>Y</td> 1254 //! <td> R --> B</td> 1255 //! </tr> 1256 //! <tr> 1257 //! <td>U</td> 1258 //! <td> G --> G</td> 1259 //! </tr> 1260 //! <tr> 1261 //! <td>V</td> 1262 //! <td> B --> R</td> 1263 //! </tr> 1264 //! </table> 1265 enum YUV_CHANNEL_SWAP 1266 { 1267 YUV_CHANNEL_SWAP_UNNAMED0 = 0, //!< No additional details 1268 }; 1269 1270 //! \brief C1 1271 //! \details 1272 //! Transform coefficient. 1273 enum C1 1274 { 1275 C1_UNNAMED0 = 0, //!< No additional details 1276 }; 1277 1278 //! \brief C2 1279 //! \details 1280 //! Transform coefficient. 1281 enum C2 1282 { 1283 C2_UNNAMED0 = 0, //!< No additional details 1284 }; 1285 1286 //! \brief C3 1287 //! \details 1288 //! Transform coefficient. 1289 enum C3 1290 { 1291 C3_UNNAMED0 = 0, //!< No additional details 1292 }; 1293 1294 //! \brief C4 1295 //! \details 1296 //! Transform coefficient. 1297 enum C4 1298 { 1299 C4_OR10 = 65536, //!< No additional details 1300 }; 1301 1302 //! \brief C5 1303 //! \details 1304 //! Transform coefficient. 1305 enum C5 1306 { 1307 C5_UNNAMED0 = 0, //!< No additional details 1308 }; 1309 1310 //! \brief C6 1311 //! \details 1312 //! Transform coefficient. 1313 enum C6 1314 { 1315 C6_UNNAMED0 = 0, //!< No additional details 1316 }; 1317 1318 //! \brief C7 1319 //! \details 1320 //! Transform coefficient. 1321 enum C7 1322 { 1323 C7_UNNAMED0 = 0, //!< No additional details 1324 }; 1325 1326 //! \brief C8 1327 //! \details 1328 //! Transform coefficient. The offset value is multiplied by 2 before being 1329 //! added to the output. 1330 enum C8 1331 { 1332 C8_OR10 = 65536, //!< No additional details 1333 }; 1334 1335 //! \brief OFFSET_IN_1 1336 //! \details 1337 //! Offset in for Y/R. The offset value is multiplied by 2 before being 1338 //! added to the output. 1339 enum OFFSET_IN_1 1340 { 1341 OFFSET_IN_1_UNNAMED0 = 0, //!< No additional details 1342 }; 1343 1344 //! \brief OFFSET_OUT_1 1345 //! \details 1346 //! Offset in for Y/R. The offset value is multiplied by 2 before being 1347 //! added to the output. 1348 enum OFFSET_OUT_1 1349 { 1350 OFFSET_OUT_1_UNNAMED0 = 0, //!< No additional details 1351 }; 1352 1353 //! \brief OFFSET_IN_2 1354 //! \details 1355 //! Offset out for U/G. The offset value is multiplied by 2 before being 1356 //! added to the output. 1357 enum OFFSET_IN_2 1358 { 1359 OFFSET_IN_2_UNNAMED0 = 0, //!< No additional details 1360 }; 1361 1362 //! \brief OFFSET_OUT_2 1363 //! \details 1364 //! Offset out for U/G. The offset value is multiplied by 2 before being 1365 //! added to the output. 1366 enum OFFSET_OUT_2 1367 { 1368 OFFSET_OUT_2_UNNAMED0 = 0, //!< No additional details 1369 }; 1370 1371 //! \brief OFFSET_IN_3 1372 //! \details 1373 //! Offset out for V/B. The offset value is multiplied by 2 before being 1374 //! added to the output. 1375 enum OFFSET_IN_3 1376 { 1377 OFFSET_IN_3_UNNAMED0 = 0, //!< No additional details 1378 }; 1379 1380 //! \brief OFFSET_OUT_3 1381 //! \details 1382 //! Offset out for V/B. The offset value is multiplied by 2 before being 1383 //! added to the output. 1384 enum OFFSET_OUT_3 1385 { 1386 OFFSET_OUT_3_UNNAMED0 = 0, //!< No additional details 1387 }; 1388 1389 //! \name Initializations 1390 1391 //! \brief Explicit member initialization function 1392 VEBOX_CSC_STATE_CMD(); 1393 1394 static const size_t dwSize = 12; 1395 static const size_t byteSize = 48; 1396 }; 1397 1398 //! 1399 //! \brief VEBOX_DNDI_STATE 1400 //! \details 1401 //! This state table is used by the Denoise and Deinterlacer functions. 1402 //! DW0 to 2 are for Temporal Denoise 1403 //! DW3 is for global noise estimate and hot pixel detection 1404 //! DW4 is for Chroma Denoise 1405 //! DW5 to 11 are for 5x5 spatial denoise 1406 //! DW12 to 17 are for Deinterlacer 1407 //! DW18 to 24 [CNL+] Added controls for Deinterlace. Added Deflicker 1408 //! filter at output of DI. 1409 //! 1410 //! 1411 struct VEBOX_DNDI_STATE_CMD 1412 { 1413 union 1414 { 1415 //!< DWORD 0 1416 struct 1417 { 1418 uint32_t DenoiseMovingPixelThreshold : __CODEGEN_BITFIELD( 0, 4) ; //!< Denoise Moving Pixel Threshold 1419 uint32_t Reserved5 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved 1420 uint32_t DenoiseHistoryIncrease : __CODEGEN_BITFIELD( 8, 11) ; //!< DENOISE_HISTORY_INCREASE 1421 uint32_t DenoiseMaximumHistory : __CODEGEN_BITFIELD(12, 19) ; //!< Denoise Maximum History 1422 uint32_t DenoiseStadThreshold : __CODEGEN_BITFIELD(20, 31) ; //!< Denoise STAD Threshold 1423 }; 1424 uint32_t Value; 1425 } DW0; 1426 union 1427 { 1428 //!< DWORD 1 1429 struct 1430 { 1431 uint32_t LowTemporalDifferenceThreshold : __CODEGEN_BITFIELD( 0, 9) ; //!< Low Temporal Difference Threshold 1432 uint32_t TemporalDifferenceThreshold : __CODEGEN_BITFIELD(10, 19) ; //!< Temporal Difference Threshold 1433 uint32_t DenoiseAsdThreshold : __CODEGEN_BITFIELD(20, 31) ; //!< Denoise ASD Threshold 1434 }; 1435 uint32_t Value; 1436 } DW1; 1437 union 1438 { 1439 //!< DWORD 2 1440 struct 1441 { 1442 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 9) ; //!< Reserved 1443 uint32_t InitialDenoiseHistory : __CODEGEN_BITFIELD(10, 15) ; //!< INITIAL_DENOISE_HISTORY 1444 uint32_t DenoiseThresholdForSumOfComplexityMeasure : __CODEGEN_BITFIELD(16, 27) ; //!< Denoise Threshold for Sum of Complexity Measure 1445 uint32_t ProgressiveDn : __CODEGEN_BITFIELD(28, 28) ; //!< PROGRESSIVE_DN 1446 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1447 }; 1448 uint32_t Value; 1449 } DW2; 1450 union 1451 { 1452 //!< DWORD 3 1453 struct 1454 { 1455 uint32_t BlockNoiseEstimateNoiseThreshold : __CODEGEN_BITFIELD( 0, 11) ; //!< Block Noise Estimate Noise Threshold 1456 uint32_t BlockNoiseEstimateEdgeThreshold : __CODEGEN_BITFIELD(12, 19) ; //!< BLOCK_NOISE_ESTIMATE_EDGE_THRESHOLD 1457 uint32_t HotPixelThreshold : __CODEGEN_BITFIELD(20, 27) ; //!< Hot Pixel Threshold 1458 uint32_t HotPixelCount : __CODEGEN_BITFIELD(28, 31) ; //!< Hot Pixel Count 1459 }; 1460 uint32_t Value; 1461 } DW3; 1462 union 1463 { 1464 //!< DWORD 4 1465 struct 1466 { 1467 uint32_t ChromaLowTemporalDifferenceThreshold : __CODEGEN_BITFIELD( 0, 5) ; //!< Chroma Low Temporal Difference Threshold 1468 uint32_t ChromaTemporalDifferenceThreshold : __CODEGEN_BITFIELD( 6, 11) ; //!< Chroma Temporal Difference Threshold 1469 uint32_t ChromaDenoiseEnable : __CODEGEN_BITFIELD(12, 12) ; //!< CHROMA_DENOISE_ENABLE 1470 uint32_t Reserved141 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 1471 uint32_t ChromaDenoiseStadThreshold : __CODEGEN_BITFIELD(16, 23) ; //!< Chroma Denoise STAD Threshold 1472 uint32_t Reserved152 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1473 }; 1474 uint32_t Value; 1475 } DW4; 1476 union 1477 { 1478 //!< DWORD 5 1479 struct 1480 { 1481 uint32_t DnWr0 : __CODEGEN_BITFIELD( 0, 4) ; //!< Dn_Wr0 1482 uint32_t DnWr1 : __CODEGEN_BITFIELD( 5, 9) ; //!< Dn_Wr1 1483 uint32_t DnWr2 : __CODEGEN_BITFIELD(10, 14) ; //!< Dn_Wr2 1484 uint32_t DnWr3 : __CODEGEN_BITFIELD(15, 19) ; //!< Dn_Wr3 1485 uint32_t DnWr4 : __CODEGEN_BITFIELD(20, 24) ; //!< Dn_Wr4 1486 uint32_t DnWr5 : __CODEGEN_BITFIELD(25, 29) ; //!< Dn_Wr5 1487 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1488 }; 1489 uint32_t Value; 1490 } DW5; 1491 union 1492 { 1493 //!< DWORD 6 1494 struct 1495 { 1496 uint32_t DnThmin : __CODEGEN_BITFIELD( 0, 12) ; //!< Dn_thmin 1497 uint32_t Reserved205 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 1498 uint32_t DnThmax : __CODEGEN_BITFIELD(16, 28) ; //!< Dn_thmax 1499 uint32_t Reserved221 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1500 }; 1501 uint32_t Value; 1502 } DW6; 1503 union 1504 { 1505 //!< DWORD 7 1506 struct 1507 { 1508 uint32_t DnDynThmin : __CODEGEN_BITFIELD( 0, 12) ; //!< Dn_dyn_thmin 1509 uint32_t Reserved237 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 1510 uint32_t DnPrt5 : __CODEGEN_BITFIELD(16, 28) ; //!< Dn_prt5 1511 uint32_t Reserved253 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1512 }; 1513 uint32_t Value; 1514 } DW7; 1515 union 1516 { 1517 //!< DWORD 8 1518 struct 1519 { 1520 uint32_t DnPrt3 : __CODEGEN_BITFIELD( 0, 12) ; //!< Dn_prt3 1521 uint32_t Reserved269 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 1522 uint32_t DnPrt4 : __CODEGEN_BITFIELD(16, 28) ; //!< Dn_prt4 1523 uint32_t Reserved285 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1524 }; 1525 uint32_t Value; 1526 } DW8; 1527 union 1528 { 1529 //!< DWORD 9 1530 struct 1531 { 1532 uint32_t DnPrt1 : __CODEGEN_BITFIELD( 0, 12) ; //!< Dn_prt1 1533 uint32_t Reserved301 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 1534 uint32_t DnPrt2 : __CODEGEN_BITFIELD(16, 28) ; //!< Dn_prt2 1535 uint32_t Reserved317 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1536 }; 1537 uint32_t Value; 1538 } DW9; 1539 union 1540 { 1541 //!< DWORD 10 1542 struct 1543 { 1544 uint32_t DnWd20 : __CODEGEN_BITFIELD( 0, 4) ; //!< Dn_wd20 1545 uint32_t DnWd21 : __CODEGEN_BITFIELD( 5, 9) ; //!< Dn_wd21 1546 uint32_t DnWd22 : __CODEGEN_BITFIELD(10, 14) ; //!< Dn_wd22 1547 uint32_t Reserved335 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1548 uint32_t DnPrt0 : __CODEGEN_BITFIELD(16, 28) ; //!< Dn_prt0 1549 uint32_t Reserved349 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1550 }; 1551 uint32_t Value; 1552 } DW10; 1553 union 1554 { 1555 //!< DWORD 11 1556 struct 1557 { 1558 uint32_t DnWd00 : __CODEGEN_BITFIELD( 0, 4) ; //!< Dn_wd00 1559 uint32_t DnWd01 : __CODEGEN_BITFIELD( 5, 9) ; //!< Dn_wd01 1560 uint32_t DnWd02 : __CODEGEN_BITFIELD(10, 14) ; //!< Dn_wd02 1561 uint32_t DnWd10 : __CODEGEN_BITFIELD(15, 19) ; //!< Dn_wd10 1562 uint32_t DnWd11 : __CODEGEN_BITFIELD(20, 24) ; //!< Dn_wd11 1563 uint32_t DnWd12 : __CODEGEN_BITFIELD(25, 29) ; //!< Dn_wd12 1564 uint32_t Reserved382 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1565 }; 1566 uint32_t Value; 1567 } DW11; 1568 union 1569 { 1570 //!< DWORD 12 1571 struct 1572 { 1573 uint32_t SmoothMvThreshold : __CODEGEN_BITFIELD( 0, 1) ; //!< Smooth MV Threshold 1574 uint32_t SadTightThreshold : __CODEGEN_BITFIELD( 2, 5) ; //!< SAD_TIGHT_THRESHOLD 1575 uint32_t ContentAdaptiveThresholdSlope : __CODEGEN_BITFIELD( 6, 9) ; //!< CONTENT_ADAPTIVE_THRESHOLD_SLOPE 1576 uint32_t StmmC2 : __CODEGEN_BITFIELD(10, 12) ; //!< STMM C2 1577 uint32_t Reserved397 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1578 }; 1579 uint32_t Value; 1580 } DW12; 1581 union 1582 { 1583 //!< DWORD 13 1584 struct 1585 { 1586 uint32_t MaximumStmm : __CODEGEN_BITFIELD( 0, 7) ; //!< Maximum STMM 1587 uint32_t MultiplierForVecm : __CODEGEN_BITFIELD( 8, 13) ; //!< Multiplier for VECM 1588 uint32_t Reserved430 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1589 uint32_t BlendingConstantAcrossTimeForSmallValuesOfStmm : __CODEGEN_BITFIELD(16, 23) ; //!< Blending constant across time for small values of STMM 1590 uint32_t BlendingConstantAcrossTimeForLargeValuesOfStmm : __CODEGEN_BITFIELD(24, 30) ; //!< Blending constant across time for large values of STMM 1591 uint32_t StmmBlendingConstantSelect : __CODEGEN_BITFIELD(31, 31) ; //!< STMM_BLENDING_CONSTANT_SELECT 1592 }; 1593 uint32_t Value; 1594 } DW13; 1595 union 1596 { 1597 //!< DWORD 14 1598 struct 1599 { 1600 uint32_t SdiDelta : __CODEGEN_BITFIELD( 0, 7) ; //!< SDI Delta 1601 uint32_t SdiThreshold : __CODEGEN_BITFIELD( 8, 15) ; //!< SDI Threshold 1602 uint32_t StmmOutputShift : __CODEGEN_BITFIELD(16, 19) ; //!< STMM Output Shift 1603 uint32_t StmmShiftUp : __CODEGEN_BITFIELD(20, 21) ; //!< STMM_SHIFT_UP 1604 uint32_t StmmShiftDown : __CODEGEN_BITFIELD(22, 23) ; //!< STMM_SHIFT_DOWN 1605 uint32_t MinimumStmm : __CODEGEN_BITFIELD(24, 31) ; //!< Minimum STMM 1606 }; 1607 uint32_t Value; 1608 } DW14; 1609 union 1610 { 1611 //!< DWORD 15 1612 struct 1613 { 1614 uint32_t FmdTemporalDifferenceThreshold : __CODEGEN_BITFIELD( 0, 7) ; //!< FMD Temporal Difference Threshold 1615 uint32_t SdiFallbackMode2ConstantAngle2X1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SDI Fallback Mode 2 Constant (Angle2x1) 1616 uint32_t SdiFallbackMode1T2Constant : __CODEGEN_BITFIELD(16, 23) ; //!< SDI Fallback Mode 1 T2 Constant 1617 uint32_t SdiFallbackMode1T1Constant : __CODEGEN_BITFIELD(24, 31) ; //!< SDI Fallback Mode 1 T1 Constant 1618 }; 1619 uint32_t Value; 1620 } DW15; 1621 union 1622 { 1623 //!< DWORD 16 1624 struct 1625 { 1626 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1627 uint32_t DnDiTopFirst : __CODEGEN_BITFIELD( 3, 3) ; //!< DNDI_TOP_FIRST 1628 uint32_t Reserved516 : __CODEGEN_BITFIELD( 4, 6) ; //!< Reserved 1629 uint32_t McdiEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< MCDI Enable 1630 uint32_t FmdTearThreshold : __CODEGEN_BITFIELD( 8, 13) ; //!< FMD Tear Threshold 1631 uint32_t CatThreshold : __CODEGEN_BITFIELD(14, 15) ; //!< CAT_THRESHOLD 1632 uint32_t Fmd2VerticalDifferenceThreshold : __CODEGEN_BITFIELD(16, 23) ; //!< FMD #2 Vertical Difference Threshold 1633 uint32_t Fmd1VerticalDifferenceThreshold : __CODEGEN_BITFIELD(24, 31) ; //!< FMD #1 Vertical Difference Threshold 1634 }; 1635 uint32_t Value; 1636 } DW16; 1637 union 1638 { 1639 //!< DWORD 17 1640 struct 1641 { 1642 uint32_t SadTha : __CODEGEN_BITFIELD( 0, 3) ; //!< SAD_THA 1643 uint32_t SadThb : __CODEGEN_BITFIELD( 4, 7) ; //!< SAD_THB 1644 uint32_t ProgressiveCadenceReconstructionFor1StFieldOfCurrentFrame : __CODEGEN_BITFIELD( 8, 9) ; //!< PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_1ST_FIELD_OF_CURRENT_FRAME 1645 uint32_t McPixelConsistencyThreshold : __CODEGEN_BITFIELD(10, 15) ; //!< MC_PIXEL_CONSISTENCY_THRESHOLD 1646 uint32_t ProgressiveCadenceReconstructionFor2NdFieldOfPreviousFrame : __CODEGEN_BITFIELD(16, 17) ; //!< PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_2ND_FIELD_OF_PREVIOUS_FRAME 1647 uint32_t Reserved562 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 1648 uint32_t NeighborPixelThreshold : __CODEGEN_BITFIELD(19, 22) ; //!< NEIGHBOR_PIXEL_THRESHOLD 1649 uint32_t Reserved567 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 1650 }; 1651 uint32_t Value; 1652 } DW17; 1653 1654 //! \name Local enumerations 1655 1656 //! \brief DENOISE_HISTORY_INCREASE 1657 //! \details 1658 //! Amount that denoise_history is increased by. 1659 //! MAX:15 1660 enum DENOISE_HISTORY_INCREASE 1661 { 1662 DENOISE_HISTORY_INCREASE_UNNAMED8 = 8, //!< No additional details 1663 DENOISE_HISTORY_INCREASE_UNNAMED15 = 15, //!< Maximum Allowed 1664 }; 1665 1666 //! \brief INITIAL_DENOISE_HISTORY 1667 //! \details 1668 //! Initial value for Denoise history for both Luma and Chroma 1669 enum INITIAL_DENOISE_HISTORY 1670 { 1671 INITIAL_DENOISE_HISTORY_UNNAMED32 = 32, //!< No additional details 1672 }; 1673 1674 //! \brief PROGRESSIVE_DN 1675 //! \details 1676 //! Indicates that the denoise algorithm should assume progressive input 1677 //! when filtering neighboring pixels. 1678 //! <b>This bit must be set if the input to Denoise is 1679 //! RGB.</b> 1680 enum PROGRESSIVE_DN 1681 { 1682 PROGRESSIVE_DN_UNNAMED0 = 0, //!< DN assumes interlaced video and filters alternate lines together 1683 PROGRESSIVE_DN_UNNAMED1 = 1, //!< DN assumes progressive video and filters neighboring lines together 1684 }; 1685 1686 //! \brief BLOCK_NOISE_ESTIMATE_EDGE_THRESHOLD 1687 //! \details 1688 //! Threshold for detecting an edge in block noise estimate. 1689 enum BLOCK_NOISE_ESTIMATE_EDGE_THRESHOLD 1690 { 1691 BLOCK_NOISE_ESTIMATE_EDGE_THRESHOLD_UNNAMED16 = 16, //!< No additional details 1692 BLOCK_NOISE_ESTIMATE_EDGE_THRESHOLD_UNNAMED255 = 255, //!< Maximium Value 1693 }; 1694 1695 enum CHROMA_DENOISE_ENABLE 1696 { 1697 CHROMA_DENOISE_ENABLE_UNNAMED0 = 0, //!< The U and V channels will be passed to the next stage after DN unchanged. 1698 CHROMA_DENOISE_ENABLE_UNNAMED1 = 1, //!< The U and V chroma channels will be denoise filtered. 1699 }; 1700 1701 enum SAD_TIGHT_THRESHOLD 1702 { 1703 SAD_TIGHT_THRESHOLD_UNNAMED5 = 5, //!< No additional details 1704 }; 1705 1706 //! \brief CONTENT_ADAPTIVE_THRESHOLD_SLOPE 1707 //! \details 1708 //! Determines the slope of the Content Adaptive Threshold. 1709 enum CONTENT_ADAPTIVE_THRESHOLD_SLOPE 1710 { 1711 CONTENT_ADAPTIVE_THRESHOLD_SLOPE_UNNAMED9 = 9, //!< CAT_slope value = 10 1712 }; 1713 1714 enum STMM_BLENDING_CONSTANT_SELECT 1715 { 1716 STMM_BLENDING_CONSTANT_SELECT_UNNAMED0 = 0, //!< Use the blending constant for small values of STMM for stmm_md_th 1717 STMM_BLENDING_CONSTANT_SELECT_UNNAMED1 = 1, //!< Use the blending constant for large values of STMM for stmm_md_th 1718 }; 1719 1720 //! \brief STMM_SHIFT_UP 1721 //! \details 1722 //! Amount to shift STMM up (set range). 1723 enum STMM_SHIFT_UP 1724 { 1725 STMM_SHIFT_UP_SHIFTBY6 = 0, //!< No additional details 1726 STMM_SHIFT_UP_SHIFTBY7 = 1, //!< No additional details 1727 STMM_SHIFT_UP_SHIFTBY8 = 2, //!< No additional details 1728 }; 1729 1730 //! \brief STMM_SHIFT_DOWN 1731 //! \details 1732 //! Amount to shift STMM down (quantize to fewer bits) 1733 enum STMM_SHIFT_DOWN 1734 { 1735 STMM_SHIFT_DOWN_SHIFTBY4 = 0, //!< No additional details 1736 STMM_SHIFT_DOWN_SHIFTBY5 = 1, //!< No additional details 1737 STMM_SHIFT_DOWN_SHIFTBY6 = 2, //!< No additional details 1738 }; 1739 1740 //! \brief DNDI_TOP_FIRST 1741 //! \details 1742 //! Indicates the top field is first in sequence, otherwise bottom is first. 1743 enum DNDI_TOP_FIRST 1744 { 1745 DNDI_TOP_FIRST_UNNAMED0 = 0, //!< Bottom field occurs first in sequence 1746 DNDI_TOP_FIRST_UNNAMED1 = 1, //!< Top field occurs first in sequence 1747 }; 1748 1749 enum CAT_THRESHOLD 1750 { 1751 CAT_THRESHOLD_UNNAMED0 = 0, //!< No additional details 1752 }; 1753 1754 enum SAD_THA 1755 { 1756 SAD_THA_UNNAMED5 = 5, //!< No additional details 1757 }; 1758 1759 enum SAD_THB 1760 { 1761 SAD_THB_UNNAMED10 = 10, //!< No additional details 1762 }; 1763 1764 enum PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_1ST_FIELD_OF_CURRENT_FRAME 1765 { 1766 PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_1ST_FIELD_OF_CURRENT_FRAME_DEINTERLACE = 0, //!< No additional details 1767 PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_1ST_FIELD_OF_CURRENT_FRAME_PUTTOGETHERWITHPREVIOUSFIELDINSEQUENCE = 1, //!< 2^nd field of previous frame 1768 PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_1ST_FIELD_OF_CURRENT_FRAME_PUTTOGETHERWITHNEXTFIELDINSEQUENCE = 2, //!< 2^nd field of current frame 1769 }; 1770 1771 enum MC_PIXEL_CONSISTENCY_THRESHOLD 1772 { 1773 MC_PIXEL_CONSISTENCY_THRESHOLD_UNNAMED25 = 25, //!< No additional details 1774 }; 1775 1776 enum PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_2ND_FIELD_OF_PREVIOUS_FRAME 1777 { 1778 PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_2ND_FIELD_OF_PREVIOUS_FRAME_DEINTERLACE = 0, //!< No additional details 1779 PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_2ND_FIELD_OF_PREVIOUS_FRAME_PUTTOGETHERWITHPREVIOUSFIELDINSEQUENCE = 1, //!< 1^st field of previous frame 1780 PROGRESSIVE_CADENCE_RECONSTRUCTION_FOR_2ND_FIELD_OF_PREVIOUS_FRAME_PUTTOGETHERWITHNEXTFIELDINSEQUENCE = 2, //!< 1^st field of current frame 1781 }; 1782 1783 enum NEIGHBOR_PIXEL_THRESHOLD 1784 { 1785 NEIGHBOR_PIXEL_THRESHOLD_UNNAMED10 = 10, //!< No additional details 1786 }; 1787 1788 //! \name Initializations 1789 1790 //! \brief Explicit member initialization function 1791 VEBOX_DNDI_STATE_CMD(); 1792 1793 static const size_t dwSize = 18; 1794 static const size_t byteSize = 72; 1795 }; 1796 1797 //! 1798 //! \brief VEBOX_FRONT_END_CSC_STATE 1799 //! \details 1800 //! This state structure contains the IECP State Table Contents for 1801 //! Front-end CSC state. 1802 //! 1803 struct VEBOX_FRONT_END_CSC_STATE_CMD 1804 { 1805 union 1806 { 1807 //!< DWORD 0 1808 struct 1809 { 1810 uint32_t FecscC0TransformCoefficient : __CODEGEN_BITFIELD( 0, 18) ; //!< FECSC_C0_TRANSFORM_COEFFICIENT 1811 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 30) ; //!< Reserved 1812 uint32_t FrontEndCscTransformEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Front End CSC Transform Enable 1813 }; 1814 uint32_t Value; 1815 } DW0; 1816 union 1817 { 1818 //!< DWORD 1 1819 struct 1820 { 1821 uint32_t FecscC1TransformCoefficient : __CODEGEN_BITFIELD( 0, 18) ; //!< FECSC_C1_TRANSFORM_COEFFICIENT 1822 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1823 }; 1824 uint32_t Value; 1825 } DW1; 1826 union 1827 { 1828 //!< DWORD 2 1829 struct 1830 { 1831 uint32_t FecscC2TransformCoefficient : __CODEGEN_BITFIELD( 0, 18) ; //!< FECSC_C2_TRANSFORM_COEFFICIENT 1832 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1833 }; 1834 uint32_t Value; 1835 } DW2; 1836 union 1837 { 1838 //!< DWORD 3 1839 struct 1840 { 1841 uint32_t FecscC3TransformCoefficient : __CODEGEN_BITFIELD( 0, 18) ; //!< FECSC_C3_TRANSFORM_COEFFICIENT 1842 uint32_t Reserved115 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1843 }; 1844 uint32_t Value; 1845 } DW3; 1846 union 1847 { 1848 //!< DWORD 4 1849 struct 1850 { 1851 uint32_t FecscC4TransformCoefficient : __CODEGEN_BITFIELD( 0, 18) ; //!< FECSC_C4_TRANSFORM_COEFFICIENT 1852 uint32_t Reserved147 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1853 }; 1854 uint32_t Value; 1855 } DW4; 1856 union 1857 { 1858 //!< DWORD 5 1859 struct 1860 { 1861 uint32_t FecscC5TransformCoefficient : __CODEGEN_BITFIELD( 0, 18) ; //!< FECSC_C5_TRANSFORM_COEFFICIENT 1862 uint32_t Reserved179 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1863 }; 1864 uint32_t Value; 1865 } DW5; 1866 union 1867 { 1868 //!< DWORD 6 1869 struct 1870 { 1871 uint32_t FecscC6TransformCoefficient : __CODEGEN_BITFIELD( 0, 18) ; //!< FECSC_C6_TRANSFORM_COEFFICIENT 1872 uint32_t Reserved211 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1873 }; 1874 uint32_t Value; 1875 } DW6; 1876 union 1877 { 1878 //!< DWORD 7 1879 struct 1880 { 1881 uint32_t FecscC7TransformCoefficient : __CODEGEN_BITFIELD( 0, 18) ; //!< FECSC_C7_TRANSFORM_COEFFICIENT 1882 uint32_t Reserved243 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1883 }; 1884 uint32_t Value; 1885 } DW7; 1886 union 1887 { 1888 //!< DWORD 8 1889 struct 1890 { 1891 uint32_t FecscC8TransformCoefficient : __CODEGEN_BITFIELD( 0, 18) ; //!< FECSC_C8_TRANSFORM_COEFFICIENT 1892 uint32_t Reserved275 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 1893 }; 1894 uint32_t Value; 1895 } DW8; 1896 union 1897 { 1898 //!< DWORD 9 1899 struct 1900 { 1901 uint32_t FecScOffsetIn1OffsetInForYR : __CODEGEN_BITFIELD( 0, 15) ; //!< FEC_SC_OFFSET_IN_1_OFFSET_IN_FOR_YR 1902 uint32_t FecScOffsetOut1OffsetOutForYR : __CODEGEN_BITFIELD(16, 31) ; //!< FEC_SC_OFFSET_OUT_1_OFFSET_OUT_FOR_YR 1903 }; 1904 uint32_t Value; 1905 } DW9; 1906 union 1907 { 1908 //!< DWORD 10 1909 struct 1910 { 1911 uint32_t FecScOffsetIn2OffsetOutForUG : __CODEGEN_BITFIELD( 0, 15) ; //!< FEC_SC_OFFSET_IN_2_OFFSET_OUT_FOR_UG 1912 uint32_t FecScOffsetOut2OffsetOutForUG : __CODEGEN_BITFIELD(16, 31) ; //!< FEC_SC_OFFSET_OUT_2_OFFSET_OUT_FOR_UG 1913 }; 1914 uint32_t Value; 1915 } DW10; 1916 union 1917 { 1918 //!< DWORD 11 1919 struct 1920 { 1921 uint32_t FecScOffsetIn3OffsetOutForVB : __CODEGEN_BITFIELD( 0, 15) ; //!< FEC_SC_OFFSET_IN_3_OFFSET_OUT_FOR_VB 1922 uint32_t FecScOffsetOut3OffsetOutForVB : __CODEGEN_BITFIELD(16, 31) ; //!< FEC_SC_OFFSET_OUT_3_OFFSET_OUT_FOR_VB 1923 }; 1924 uint32_t Value; 1925 } DW11; 1926 1927 //! \name Local enumerations 1928 1929 enum FECSC_C0_TRANSFORM_COEFFICIENT 1930 { 1931 FECSC_C0_TRANSFORM_COEFFICIENT_OR10 = 65536, //!< No additional details 1932 }; 1933 1934 enum FECSC_C1_TRANSFORM_COEFFICIENT 1935 { 1936 FECSC_C1_TRANSFORM_COEFFICIENT_OR00 = 0, //!< No additional details 1937 }; 1938 1939 enum FECSC_C2_TRANSFORM_COEFFICIENT 1940 { 1941 FECSC_C2_TRANSFORM_COEFFICIENT_OR00 = 0, //!< No additional details 1942 }; 1943 1944 enum FECSC_C3_TRANSFORM_COEFFICIENT 1945 { 1946 FECSC_C3_TRANSFORM_COEFFICIENT_OR00 = 0, //!< No additional details 1947 }; 1948 1949 enum FECSC_C4_TRANSFORM_COEFFICIENT 1950 { 1951 FECSC_C4_TRANSFORM_COEFFICIENT_OR10 = 65536, //!< No additional details 1952 }; 1953 1954 enum FECSC_C5_TRANSFORM_COEFFICIENT 1955 { 1956 FECSC_C5_TRANSFORM_COEFFICIENT_OR00 = 0, //!< No additional details 1957 }; 1958 1959 enum FECSC_C6_TRANSFORM_COEFFICIENT 1960 { 1961 FECSC_C6_TRANSFORM_COEFFICIENT_OR00 = 0, //!< No additional details 1962 }; 1963 1964 enum FECSC_C7_TRANSFORM_COEFFICIENT 1965 { 1966 FECSC_C7_TRANSFORM_COEFFICIENT_OR00 = 0, //!< No additional details 1967 }; 1968 1969 enum FECSC_C8_TRANSFORM_COEFFICIENT 1970 { 1971 FECSC_C8_TRANSFORM_COEFFICIENT_OR10 = 65536, //!< No additional details 1972 }; 1973 1974 //! \brief FEC_SC_OFFSET_IN_1_OFFSET_IN_FOR_YR 1975 //! \details 1976 //! The offset value is multiplied by 2 before being added to the output. 1977 enum FEC_SC_OFFSET_IN_1_OFFSET_IN_FOR_YR 1978 { 1979 FEC_SC_OFFSET_IN_1_OFFSET_IN_FOR_YR_UNNAMED0 = 0, //!< No additional details 1980 }; 1981 1982 //! \brief FEC_SC_OFFSET_OUT_1_OFFSET_OUT_FOR_YR 1983 //! \details 1984 //! The offset value is multiplied by 2 before being added to the output. 1985 enum FEC_SC_OFFSET_OUT_1_OFFSET_OUT_FOR_YR 1986 { 1987 FEC_SC_OFFSET_OUT_1_OFFSET_OUT_FOR_YR_UNNAMED0 = 0, //!< No additional details 1988 }; 1989 1990 //! \brief FEC_SC_OFFSET_IN_2_OFFSET_OUT_FOR_UG 1991 //! \details 1992 //! The offset value is multiplied by 2 before being added to the output. 1993 enum FEC_SC_OFFSET_IN_2_OFFSET_OUT_FOR_UG 1994 { 1995 FEC_SC_OFFSET_IN_2_OFFSET_OUT_FOR_UG_UNNAMED0 = 0, //!< No additional details 1996 }; 1997 1998 //! \brief FEC_SC_OFFSET_OUT_2_OFFSET_OUT_FOR_UG 1999 //! \details 2000 //! The offset value is multiplied by 2 before being added to the output. 2001 enum FEC_SC_OFFSET_OUT_2_OFFSET_OUT_FOR_UG 2002 { 2003 FEC_SC_OFFSET_OUT_2_OFFSET_OUT_FOR_UG_UNNAMED0 = 0, //!< No additional details 2004 }; 2005 2006 //! \brief FEC_SC_OFFSET_IN_3_OFFSET_OUT_FOR_VB 2007 //! \details 2008 //! The offset value is multiplied by 2 before being added to the output. 2009 enum FEC_SC_OFFSET_IN_3_OFFSET_OUT_FOR_VB 2010 { 2011 FEC_SC_OFFSET_IN_3_OFFSET_OUT_FOR_VB_UNNAMED0 = 0, //!< No additional details 2012 }; 2013 2014 //! \brief FEC_SC_OFFSET_OUT_3_OFFSET_OUT_FOR_VB 2015 //! \details 2016 //! The offset value is multiplied by 2 before being added to the output. 2017 enum FEC_SC_OFFSET_OUT_3_OFFSET_OUT_FOR_VB 2018 { 2019 FEC_SC_OFFSET_OUT_3_OFFSET_OUT_FOR_VB_UNNAMED0 = 0, //!< No additional details 2020 }; 2021 2022 //! \name Initializations 2023 2024 //! \brief Explicit member initialization function 2025 VEBOX_FRONT_END_CSC_STATE_CMD(); 2026 2027 static const size_t dwSize = 12; 2028 static const size_t byteSize = 48; 2029 }; 2030 2031 //! 2032 //! \brief VEBOX_GAMUT_STATE 2033 //! \details 2034 //! 2035 //! 2036 struct VEBOX_GAMUT_STATE_CMD 2037 { 2038 union 2039 { 2040 //!< DWORD 0 2041 struct 2042 { 2043 uint32_t CmW : __CODEGEN_BITFIELD( 0, 9) ; //!< CM(w) 2044 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 14) ; //!< Reserved 2045 uint32_t GlobalModeEnable : __CODEGEN_BITFIELD(15, 15) ; //!< GLOBAL_MODE_ENABLE 2046 uint32_t AR : __CODEGEN_BITFIELD(16, 24) ; //!< AR 2047 uint32_t Reserved25 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 2048 }; 2049 uint32_t Value; 2050 } DW0; 2051 union 2052 { 2053 //!< DWORD 1 2054 struct 2055 { 2056 uint32_t AB : __CODEGEN_BITFIELD( 0, 6) ; //!< A(b) 2057 uint32_t Reserved39 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 2058 uint32_t AG : __CODEGEN_BITFIELD( 8, 14) ; //!< A(g) 2059 uint32_t Reserved47 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2060 uint32_t CmS : __CODEGEN_BITFIELD(16, 25) ; //!< CM(s) 2061 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2062 }; 2063 uint32_t Value; 2064 } DW1; 2065 union 2066 { 2067 //!< DWORD 2 2068 struct 2069 { 2070 uint32_t RI : __CODEGEN_BITFIELD( 0, 7) ; //!< R(i) 2071 uint32_t CmI : __CODEGEN_BITFIELD( 8, 15) ; //!< CM(i) 2072 uint32_t RS : __CODEGEN_BITFIELD(16, 25) ; //!< R(s) 2073 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2074 }; 2075 uint32_t Value; 2076 } DW2; 2077 union 2078 { 2079 //!< DWORD 3 2080 struct 2081 { 2082 uint32_t C0 : __CODEGEN_BITFIELD( 0, 14) ; //!< C0 2083 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2084 uint32_t C1 : __CODEGEN_BITFIELD(16, 30) ; //!< C1 2085 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2086 }; 2087 uint32_t Value; 2088 } DW3; 2089 union 2090 { 2091 //!< DWORD 4 2092 struct 2093 { 2094 uint32_t C2 : __CODEGEN_BITFIELD( 0, 14) ; //!< C2 2095 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2096 uint32_t C3 : __CODEGEN_BITFIELD(16, 30) ; //!< C3 2097 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2098 }; 2099 uint32_t Value; 2100 } DW4; 2101 union 2102 { 2103 //!< DWORD 5 2104 struct 2105 { 2106 uint32_t C4 : __CODEGEN_BITFIELD( 0, 14) ; //!< C4 2107 uint32_t Reserved175 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2108 uint32_t C5 : __CODEGEN_BITFIELD(16, 30) ; //!< C5 2109 uint32_t Reserved191 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2110 }; 2111 uint32_t Value; 2112 } DW5; 2113 union 2114 { 2115 //!< DWORD 6 2116 struct 2117 { 2118 uint32_t C6 : __CODEGEN_BITFIELD( 0, 14) ; //!< C6 2119 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2120 uint32_t C7 : __CODEGEN_BITFIELD(16, 30) ; //!< C7 2121 uint32_t Reserved223 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2122 }; 2123 uint32_t Value; 2124 } DW6; 2125 union 2126 { 2127 //!< DWORD 7 2128 struct 2129 { 2130 uint32_t C8 : __CODEGEN_BITFIELD( 0, 14) ; //!< C8 2131 uint32_t Reserved239 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 2132 }; 2133 uint32_t Value; 2134 } DW7; 2135 union 2136 { 2137 //!< DWORD 8 2138 struct 2139 { 2140 uint32_t PwlGammaPoint1 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_GAMMA_POINT_1 2141 uint32_t PwlGammaPoint2 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_GAMMA_POINT_2 2142 uint32_t PwlGammaPoint3 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_GAMMA_POINT_3 2143 uint32_t PwlGammaPoint4 : __CODEGEN_BITFIELD(24, 31) ; //!< PWL_GAMMA_POINT_4 2144 }; 2145 uint32_t Value; 2146 } DW8; 2147 union 2148 { 2149 //!< DWORD 9 2150 struct 2151 { 2152 uint32_t PwlGammaPoint5 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_GAMMA_POINT_5 2153 uint32_t PwlGammaPoint6 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_GAMMA_POINT_6 2154 uint32_t PwlGammaPoint7 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_GAMMA_POINT_7 2155 uint32_t PwlGammaPoint8 : __CODEGEN_BITFIELD(24, 31) ; //!< PWL_GAMMA_POINT_8 2156 }; 2157 uint32_t Value; 2158 } DW9; 2159 union 2160 { 2161 //!< DWORD 10 2162 struct 2163 { 2164 uint32_t PwlGammaPoint9 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_GAMMA_POINT_9 2165 uint32_t PwlGammaPoint10 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_GAMMA_POINT_10 2166 uint32_t PwlGammaPoint11 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_GAMMA_POINT_11 2167 uint32_t Reserved344 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2168 }; 2169 uint32_t Value; 2170 } DW10; 2171 union 2172 { 2173 //!< DWORD 11 2174 struct 2175 { 2176 uint32_t PwlGammaBias1 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_GAMMA_BIAS_1 2177 uint32_t PwlGammaBias2 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_GAMMA_BIAS_2 2178 uint32_t PwlGammaBias3 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_GAMMA_BIAS_3 2179 uint32_t PwlGammaBias4 : __CODEGEN_BITFIELD(24, 31) ; //!< PWL_GAMMA_BIAS_4 2180 }; 2181 uint32_t Value; 2182 } DW11; 2183 union 2184 { 2185 //!< DWORD 12 2186 struct 2187 { 2188 uint32_t PwlGammaBias5 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_GAMMA_BIAS_5 2189 uint32_t PwlGammaBias6 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_GAMMA_BIAS_6 2190 uint32_t PwlGammaBias7 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_GAMMA_BIAS_7 2191 uint32_t PwlGammaBias8 : __CODEGEN_BITFIELD(24, 31) ; //!< PWL_GAMMA_BIAS_8 2192 }; 2193 uint32_t Value; 2194 } DW12; 2195 union 2196 { 2197 //!< DWORD 13 2198 struct 2199 { 2200 uint32_t PwlGammaBias9 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_GAMMA_BIAS_9 2201 uint32_t PwlGammaBias10 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_GAMMA_BIAS_10 2202 uint32_t PwlGammaBias11 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_GAMMA_BIAS_11 2203 uint32_t Reserved440 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2204 }; 2205 uint32_t Value; 2206 } DW13; 2207 union 2208 { 2209 //!< DWORD 14 2210 struct 2211 { 2212 uint32_t PwlGammaSlope0 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_Gamma_ Slope_0 2213 uint32_t Reserved460 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2214 uint32_t PwlGammaSlope1 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_Gamma_ Slope_1 2215 uint32_t Reserved476 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2216 }; 2217 uint32_t Value; 2218 } DW14; 2219 union 2220 { 2221 //!< DWORD 15 2222 struct 2223 { 2224 uint32_t PwlGammaSlope2 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_Gamma_ Slope_2 2225 uint32_t Reserved492 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2226 uint32_t PwlGammaSlope3 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_Gamma_ Slope_3 2227 uint32_t Reserved508 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2228 }; 2229 uint32_t Value; 2230 } DW15; 2231 union 2232 { 2233 //!< DWORD 16 2234 struct 2235 { 2236 uint32_t PwlGammaSlope4 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_Gamma_ Slope_4 2237 uint32_t Reserved524 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2238 uint32_t PwlGammaSlope5 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_Gamma_ Slope_5 2239 uint32_t Reserved540 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2240 }; 2241 uint32_t Value; 2242 } DW16; 2243 union 2244 { 2245 //!< DWORD 17 2246 struct 2247 { 2248 uint32_t PwlGammaSlope6 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_Gamma_ Slope_6 2249 uint32_t Reserved556 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2250 uint32_t PwlGammaSlope7 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_Gamma_ Slope_7 2251 uint32_t Reserved572 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2252 }; 2253 uint32_t Value; 2254 } DW17; 2255 union 2256 { 2257 //!< DWORD 18 2258 struct 2259 { 2260 uint32_t PwlGammaSlope8 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_Gamma_ Slope_8 2261 uint32_t Reserved588 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2262 uint32_t PwlGammaSlope9 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_Gamma_ Slope_9 2263 uint32_t Reserved604 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2264 }; 2265 uint32_t Value; 2266 } DW18; 2267 union 2268 { 2269 //!< DWORD 19 2270 struct 2271 { 2272 uint32_t PwlGammaSlope10 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_Gamma_ Slope_10 2273 uint32_t Reserved620 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2274 uint32_t PwlGammaSlope11 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_Gamma_ Slope_11 2275 uint32_t Reserved636 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2276 }; 2277 uint32_t Value; 2278 } DW19; 2279 union 2280 { 2281 //!< DWORD 20 2282 struct 2283 { 2284 uint32_t PwlInvGammaPoint1 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_INV_GAMMA_POINT_1 2285 uint32_t PwlInvGammaPoint2 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_INV_GAMMA_POINT_2 2286 uint32_t PwlInvGammaPoint3 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_INV_GAMMA_POINT_3 2287 uint32_t PwlInvGammaPoint4 : __CODEGEN_BITFIELD(24, 31) ; //!< PWL_INV_GAMMA_POINT_4 2288 }; 2289 uint32_t Value; 2290 } DW20; 2291 union 2292 { 2293 //!< DWORD 21 2294 struct 2295 { 2296 uint32_t PwlInvGammaPoint5 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_INV_GAMMA_POINT_5 2297 uint32_t PwlInvGammaPoint6 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_INV_GAMMA_POINT_6 2298 uint32_t PwlInvGammaPoint7 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_INV_GAMMA_POINT_7 2299 uint32_t PwlInvGammaPoint8 : __CODEGEN_BITFIELD(24, 31) ; //!< PWL_INV_GAMMA_POINT_8 2300 }; 2301 uint32_t Value; 2302 } DW21; 2303 union 2304 { 2305 //!< DWORD 22 2306 struct 2307 { 2308 uint32_t PwlInvGammaPoint9 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_INV_GAMMA_POINT_9 2309 uint32_t PwlInvGammaPoint10 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_INV_GAMMA_POINT_10 2310 uint32_t PwlInvGammaPoint11 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_INV_GAMMA_POINT_11 2311 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2312 }; 2313 uint32_t Value; 2314 } DW22; 2315 union 2316 { 2317 //!< DWORD 23 2318 struct 2319 { 2320 uint32_t PwlInvGammaBias1 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_INV_GAMMA_BIAS_1 2321 uint32_t PwlInvGammaBias2 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_INV_GAMMA_BIAS_2 2322 uint32_t PwlInvGammaBias3 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_INV_GAMMA_BIAS_3 2323 uint32_t PwlInvGammaBias4 : __CODEGEN_BITFIELD(24, 31) ; //!< PWL_INV_GAMMA_BIAS_4 2324 }; 2325 uint32_t Value; 2326 } DW23; 2327 union 2328 { 2329 //!< DWORD 24 2330 struct 2331 { 2332 uint32_t PwlInvGammaBias5 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_INV_GAMMA_BIAS_5 2333 uint32_t PwlInvGammaBias6 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_INV_GAMMA_BIAS_6 2334 uint32_t PwlInvGammaBias7 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_INV_GAMMA_BIAS_7 2335 uint32_t PwlInvGammaBias8 : __CODEGEN_BITFIELD(24, 31) ; //!< PWL_INV_GAMMA_BIAS_8 2336 }; 2337 uint32_t Value; 2338 } DW24; 2339 union 2340 { 2341 //!< DWORD 25 2342 struct 2343 { 2344 uint32_t PwlInvGammaBias9 : __CODEGEN_BITFIELD( 0, 7) ; //!< PWL_INV_GAMMA_BIAS_9 2345 uint32_t PwlInvGammaBias10 : __CODEGEN_BITFIELD( 8, 15) ; //!< PWL_INV_GAMMA_BIAS_10 2346 uint32_t PwlInvGammaBias11 : __CODEGEN_BITFIELD(16, 23) ; //!< PWL_INV_GAMMA_BIAS_11 2347 uint32_t Reserved824 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2348 }; 2349 uint32_t Value; 2350 } DW25; 2351 union 2352 { 2353 //!< DWORD 26 2354 struct 2355 { 2356 uint32_t PwlInvGammaSlope0 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_INV_GAMMA_ Slope_0 2357 uint32_t Reserved844 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2358 uint32_t PwlInvGammaSlope1 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_INV_GAMMA_ Slope_1 2359 uint32_t Reserved860 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2360 }; 2361 uint32_t Value; 2362 } DW26; 2363 union 2364 { 2365 //!< DWORD 27 2366 struct 2367 { 2368 uint32_t PwlInvGammaSlope2 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_INV_GAMMA_ Slope_2 2369 uint32_t Reserved876 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2370 uint32_t PwlInvGammaSlope3 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_INV_GAMMA_ Slope_3 2371 uint32_t Reserved892 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2372 }; 2373 uint32_t Value; 2374 } DW27; 2375 union 2376 { 2377 //!< DWORD 28 2378 struct 2379 { 2380 uint32_t PwlInvGammaSlope4 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_INV_GAMMA_ Slope_4 2381 uint32_t Reserved908 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2382 uint32_t PwlInvGammaSlope5 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_INV_GAMMA_ Slope_5 2383 uint32_t Reserved924 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2384 }; 2385 uint32_t Value; 2386 } DW28; 2387 union 2388 { 2389 //!< DWORD 29 2390 struct 2391 { 2392 uint32_t PwlInvGammaSlope6 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_INV_GAMMA_ Slope_6 2393 uint32_t Reserved940 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2394 uint32_t PwlInvGammaSlope7 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_INV_GAMMA_ Slope_7 2395 uint32_t Reserved956 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2396 }; 2397 uint32_t Value; 2398 } DW29; 2399 union 2400 { 2401 //!< DWORD 30 2402 struct 2403 { 2404 uint32_t PwlInvGammaSlope8 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_INV_GAMMA_ Slope_8 2405 uint32_t Reserved972 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2406 uint32_t PwlInvGammaSlope9 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_INV_GAMMA_ Slope_9 2407 uint32_t Reserved988 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2408 }; 2409 uint32_t Value; 2410 } DW30; 2411 union 2412 { 2413 //!< DWORD 31 2414 struct 2415 { 2416 uint32_t PwlInvGammaSlope10 : __CODEGEN_BITFIELD( 0, 11) ; //!< PWL_INV_GAMMA_ Slope_10 2417 uint32_t Reserved1004 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2418 uint32_t PwlInvGammaSlope11 : __CODEGEN_BITFIELD(16, 27) ; //!< PWL_INV_GAMMA_ Slope_11 2419 uint32_t Reserved1020 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2420 }; 2421 uint32_t Value; 2422 } DW31; 2423 union 2424 { 2425 //!< DWORD 32 2426 struct 2427 { 2428 uint32_t OffsetInR : __CODEGEN_BITFIELD( 0, 14) ; //!< OFFSET_IN_R 2429 uint32_t Reserved1039 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2430 uint32_t OffsetInG : __CODEGEN_BITFIELD(16, 30) ; //!< OFFSET_IN_G 2431 uint32_t Reserved1055 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2432 }; 2433 uint32_t Value; 2434 } DW32; 2435 union 2436 { 2437 //!< DWORD 33 2438 struct 2439 { 2440 uint32_t OffsetInB : __CODEGEN_BITFIELD( 0, 14) ; //!< OFFSET_IN_B 2441 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2442 uint32_t OffsetOutB : __CODEGEN_BITFIELD(16, 30) ; //!< Offset_out_B 2443 uint32_t Reserved1087 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2444 }; 2445 uint32_t Value; 2446 } DW33; 2447 union 2448 { 2449 //!< DWORD 34 2450 struct 2451 { 2452 uint32_t OffsetOutR : __CODEGEN_BITFIELD( 0, 14) ; //!< Offset_out_R 2453 uint32_t Reserved1103 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2454 uint32_t OffsetOutG : __CODEGEN_BITFIELD(16, 30) ; //!< Offset_out_G 2455 uint32_t Reserved1119 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2456 }; 2457 uint32_t Value; 2458 } DW34; 2459 union 2460 { 2461 //!< DWORD 35 2462 struct 2463 { 2464 uint32_t D1Out : __CODEGEN_BITFIELD( 0, 9) ; //!< D1OUT 2465 uint32_t DOutDefault : __CODEGEN_BITFIELD(10, 19) ; //!< DOUT_DEFAULT 2466 uint32_t DInDefault : __CODEGEN_BITFIELD(20, 29) ; //!< DINDEFAULT 2467 uint32_t Fullrangemappingenable : __CODEGEN_BITFIELD(30, 30) ; //!< FULLRANGEMAPPINGENABLE 2468 uint32_t Reserved1151 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2469 }; 2470 uint32_t Value; 2471 } DW35; 2472 union 2473 { 2474 //!< DWORD 36 2475 struct 2476 { 2477 uint32_t D1In : __CODEGEN_BITFIELD( 0, 9) ; //!< D1IN 2478 uint32_t Reserved1162 : __CODEGEN_BITFIELD(10, 27) ; //!< Reserved 2479 uint32_t Compressionlineshift : __CODEGEN_BITFIELD(28, 30) ; //!< COMPRESSIONLINESHIFT 2480 uint32_t Xvyccdecencenable : __CODEGEN_BITFIELD(31, 31) ; //!< XVYCCDECENCENABLE 2481 }; 2482 uint32_t Value; 2483 } DW36; 2484 union 2485 { 2486 //!< DWORD 37 2487 struct 2488 { 2489 uint32_t CpiOverride : __CODEGEN_BITFIELD( 0, 0) ; //!< CPI_OVERRIDE 2490 uint32_t Reserved1185 : __CODEGEN_BITFIELD( 1, 10) ; //!< Reserved 2491 uint32_t Basicmodescalingfactor : __CODEGEN_BITFIELD(11, 24) ; //!< BasicModeScalingFactor 2492 uint32_t Reserved1209 : __CODEGEN_BITFIELD(25, 28) ; //!< Reserved 2493 uint32_t Lumachormaonlycorrection : __CODEGEN_BITFIELD(29, 29) ; //!< LUMACHORMAONLYCORRECTION 2494 uint32_t GccBasicmodeselection : __CODEGEN_BITFIELD(30, 31) ; //!< GCC_BASICMODESELECTION 2495 }; 2496 uint32_t Value; 2497 } DW37; 2498 2499 //! \name Local enumerations 2500 2501 //! \brief GLOBAL_MODE_ENABLE 2502 //! \details 2503 //! The gain factor derived from state CM(w) 2504 enum GLOBAL_MODE_ENABLE 2505 { 2506 GLOBAL_MODE_ENABLE_ADVANCEMODE = 0, //!< No additional details 2507 GLOBAL_MODE_ENABLE_BASICMODE = 1, //!< No additional details 2508 }; 2509 2510 //! \brief AR 2511 //! \details 2512 //! Gain_factor_R (default: 436, preferred range: 256-511) 2513 enum AR 2514 { 2515 AR_UNNAMED436 = 436, //!< No additional details 2516 }; 2517 2518 //! \brief PWL_GAMMA_POINT_1 2519 //! \details 2520 //! Point 1 for PWL for gamma correction 2521 enum PWL_GAMMA_POINT_1 2522 { 2523 PWL_GAMMA_POINT_1_UNNAMED1 = 1, //!< No additional details 2524 }; 2525 2526 //! \brief PWL_GAMMA_POINT_2 2527 //! \details 2528 //! Point 2 for PWL for gamma correction 2529 enum PWL_GAMMA_POINT_2 2530 { 2531 PWL_GAMMA_POINT_2_UNNAMED2 = 2, //!< No additional details 2532 }; 2533 2534 //! \brief PWL_GAMMA_POINT_3 2535 //! \details 2536 //! Point 3 for PWL for gamma correction 2537 enum PWL_GAMMA_POINT_3 2538 { 2539 PWL_GAMMA_POINT_3_UNNAMED5 = 5, //!< No additional details 2540 }; 2541 2542 //! \brief PWL_GAMMA_POINT_4 2543 //! \details 2544 //! Point 4 for PWL for gamma correction 2545 enum PWL_GAMMA_POINT_4 2546 { 2547 PWL_GAMMA_POINT_4_UNNAMED9 = 9, //!< No additional details 2548 }; 2549 2550 //! \brief PWL_GAMMA_POINT_5 2551 //! \details 2552 //! Point 5 for PWL for gamma correction 2553 enum PWL_GAMMA_POINT_5 2554 { 2555 PWL_GAMMA_POINT_5_UNNAMED16 = 16, //!< No additional details 2556 }; 2557 2558 //! \brief PWL_GAMMA_POINT_6 2559 //! \details 2560 //! Point 6 for PWL for gamma correction 2561 enum PWL_GAMMA_POINT_6 2562 { 2563 PWL_GAMMA_POINT_6_UNNAMED26 = 26, //!< No additional details 2564 }; 2565 2566 //! \brief PWL_GAMMA_POINT_7 2567 //! \details 2568 //! Point 7 for PWL for gamma correction 2569 enum PWL_GAMMA_POINT_7 2570 { 2571 PWL_GAMMA_POINT_7_UNNAMED42 = 42, //!< No additional details 2572 }; 2573 2574 //! \brief PWL_GAMMA_POINT_8 2575 //! \details 2576 //! Point 8 for PWL for gamma correction 2577 enum PWL_GAMMA_POINT_8 2578 { 2579 PWL_GAMMA_POINT_8_UNNAMED65 = 65, //!< No additional details 2580 }; 2581 2582 //! \brief PWL_GAMMA_POINT_9 2583 //! \details 2584 //! Point 9 for PWL for gamma correction 2585 enum PWL_GAMMA_POINT_9 2586 { 2587 PWL_GAMMA_POINT_9_UNNAMED96 = 96, //!< No additional details 2588 }; 2589 2590 //! \brief PWL_GAMMA_POINT_10 2591 //! \details 2592 //! Point 10 for PWL for gamma correction 2593 enum PWL_GAMMA_POINT_10 2594 { 2595 PWL_GAMMA_POINT_10_UNNAMED136 = 136, //!< No additional details 2596 }; 2597 2598 //! \brief PWL_GAMMA_POINT_11 2599 //! \details 2600 //! Point 11 for PWL for gamma correction 2601 enum PWL_GAMMA_POINT_11 2602 { 2603 PWL_GAMMA_POINT_11_UNNAMED187 = 187, //!< No additional details 2604 }; 2605 2606 //! \brief PWL_GAMMA_BIAS_1 2607 //! \details 2608 //! Bias 1 for PWL for gamma correction 2609 enum PWL_GAMMA_BIAS_1 2610 { 2611 PWL_GAMMA_BIAS_1_UNNAMED13 = 13, //!< No additional details 2612 }; 2613 2614 //! \brief PWL_GAMMA_BIAS_2 2615 //! \details 2616 //! Bias 2 for PWL for gamma correction 2617 enum PWL_GAMMA_BIAS_2 2618 { 2619 PWL_GAMMA_BIAS_2_UNNAMED23 = 23, //!< No additional details 2620 }; 2621 2622 //! \brief PWL_GAMMA_BIAS_3 2623 //! \details 2624 //! Bias 3 for PWL for gamma correction 2625 enum PWL_GAMMA_BIAS_3 2626 { 2627 PWL_GAMMA_BIAS_3_UNNAMED38 = 38, //!< No additional details 2628 }; 2629 2630 //! \brief PWL_GAMMA_BIAS_4 2631 //! \details 2632 //! Bias 4 for PWL for gamma correction 2633 enum PWL_GAMMA_BIAS_4 2634 { 2635 PWL_GAMMA_BIAS_4_UNNAMED53 = 53, //!< No additional details 2636 }; 2637 2638 //! \brief PWL_GAMMA_BIAS_5 2639 //! \details 2640 //! Bias 5 for PWL for gamma correction 2641 enum PWL_GAMMA_BIAS_5 2642 { 2643 PWL_GAMMA_BIAS_5_UNNAMED71 = 71, //!< No additional details 2644 }; 2645 2646 //! \brief PWL_GAMMA_BIAS_6 2647 //! \details 2648 //! Bias 6 for PWL for gamma correction 2649 enum PWL_GAMMA_BIAS_6 2650 { 2651 PWL_GAMMA_BIAS_6_UNNAMED91 = 91, //!< No additional details 2652 }; 2653 2654 //! \brief PWL_GAMMA_BIAS_7 2655 //! \details 2656 //! Bias 7 for PWL for gamma correction 2657 enum PWL_GAMMA_BIAS_7 2658 { 2659 PWL_GAMMA_BIAS_7_UNNAMED114 = 114, //!< No additional details 2660 }; 2661 2662 //! \brief PWL_GAMMA_BIAS_8 2663 //! \details 2664 //! Bias 8 for PWL for gamma correction 2665 enum PWL_GAMMA_BIAS_8 2666 { 2667 PWL_GAMMA_BIAS_8_UNNAMED139 = 139, //!< No additional details 2668 }; 2669 2670 //! \brief PWL_GAMMA_BIAS_9 2671 //! \details 2672 //! Bias 9 for PWL for gamma correction 2673 enum PWL_GAMMA_BIAS_9 2674 { 2675 PWL_GAMMA_BIAS_9_UNNAMED165 = 165, //!< No additional details 2676 }; 2677 2678 //! \brief PWL_GAMMA_BIAS_10 2679 //! \details 2680 //! Bias 10 for PWL for gamma correction 2681 enum PWL_GAMMA_BIAS_10 2682 { 2683 PWL_GAMMA_BIAS_10_UNNAMED193 = 193, //!< No additional details 2684 }; 2685 2686 //! \brief PWL_GAMMA_BIAS_11 2687 //! \details 2688 //! Bias 11 for PWL for gamma correction 2689 enum PWL_GAMMA_BIAS_11 2690 { 2691 PWL_GAMMA_BIAS_11_UNNAMED223 = 223, //!< No additional details 2692 }; 2693 2694 //! \brief PWL_INV_GAMMA_POINT_1 2695 //! \details 2696 //! Point 1 for PWL for inverse gamma correction 2697 enum PWL_INV_GAMMA_POINT_1 2698 { 2699 PWL_INV_GAMMA_POINT_1_UNNAMED30 = 30, //!< No additional details 2700 }; 2701 2702 //! \brief PWL_INV_GAMMA_POINT_2 2703 //! \details 2704 //! Point 2 for PWL for inverse gamma correction 2705 enum PWL_INV_GAMMA_POINT_2 2706 { 2707 PWL_INV_GAMMA_POINT_2_UNNAMED55 = 55, //!< No additional details 2708 }; 2709 2710 //! \brief PWL_INV_GAMMA_POINT_3 2711 //! \details 2712 //! Point 3 for PWL for inverse gamma correction 2713 enum PWL_INV_GAMMA_POINT_3 2714 { 2715 PWL_INV_GAMMA_POINT_3_UNNAMED79 = 79, //!< No additional details 2716 }; 2717 2718 //! \brief PWL_INV_GAMMA_POINT_4 2719 //! \details 2720 //! Point 4 for PWL for inverse gamma correction 2721 enum PWL_INV_GAMMA_POINT_4 2722 { 2723 PWL_INV_GAMMA_POINT_4_UNNAMED101 = 101, //!< No additional details 2724 }; 2725 2726 //! \brief PWL_INV_GAMMA_POINT_5 2727 //! \details 2728 //! Point 5 for PWL for inverse gamma correction 2729 enum PWL_INV_GAMMA_POINT_5 2730 { 2731 PWL_INV_GAMMA_POINT_5_UNNAMED122 = 122, //!< No additional details 2732 }; 2733 2734 //! \brief PWL_INV_GAMMA_POINT_6 2735 //! \details 2736 //! Point 6 for PWL for inverse gamma correction 2737 enum PWL_INV_GAMMA_POINT_6 2738 { 2739 PWL_INV_GAMMA_POINT_6_UNNAMED141 = 141, //!< No additional details 2740 }; 2741 2742 //! \brief PWL_INV_GAMMA_POINT_7 2743 //! \details 2744 //! Point 7 for PWL for inverse gamma correction 2745 enum PWL_INV_GAMMA_POINT_7 2746 { 2747 PWL_INV_GAMMA_POINT_7_UNNAMED162 = 162, //!< No additional details 2748 }; 2749 2750 //! \brief PWL_INV_GAMMA_POINT_8 2751 //! \details 2752 //! Point 8 for PWL for inverse gamma correction 2753 enum PWL_INV_GAMMA_POINT_8 2754 { 2755 PWL_INV_GAMMA_POINT_8_UNNAMED181 = 181, //!< No additional details 2756 }; 2757 2758 //! \brief PWL_INV_GAMMA_POINT_9 2759 //! \details 2760 //! Point 9 for PWL for inverse gamma correction 2761 enum PWL_INV_GAMMA_POINT_9 2762 { 2763 PWL_INV_GAMMA_POINT_9_UNNAMED200 = 200, //!< No additional details 2764 }; 2765 2766 //! \brief PWL_INV_GAMMA_POINT_10 2767 //! \details 2768 //! Point 10 for PWL for inverse gamma correction 2769 enum PWL_INV_GAMMA_POINT_10 2770 { 2771 PWL_INV_GAMMA_POINT_10_UNNAMED219 = 219, //!< No additional details 2772 }; 2773 2774 //! \brief PWL_INV_GAMMA_POINT_11 2775 //! \details 2776 //! Point 11 for PWL for inverse gamma correction 2777 enum PWL_INV_GAMMA_POINT_11 2778 { 2779 PWL_INV_GAMMA_POINT_11_UNNAMED237 = 237, //!< No additional details 2780 }; 2781 2782 //! \brief PWL_INV_GAMMA_BIAS_1 2783 //! \details 2784 //! Bias 1 for PWL for inverse gamma correction 2785 enum PWL_INV_GAMMA_BIAS_1 2786 { 2787 PWL_INV_GAMMA_BIAS_1_UNNAMED3 = 3, //!< No additional details 2788 }; 2789 2790 //! \brief PWL_INV_GAMMA_BIAS_2 2791 //! \details 2792 //! Bias 2 for PWL for inverse gamma correction 2793 enum PWL_INV_GAMMA_BIAS_2 2794 { 2795 PWL_INV_GAMMA_BIAS_2_UNNAMED10 = 10, //!< No additional details 2796 }; 2797 2798 //! \brief PWL_INV_GAMMA_BIAS_3 2799 //! \details 2800 //! Bias 3 for PWL for inverse gamma correction 2801 enum PWL_INV_GAMMA_BIAS_3 2802 { 2803 PWL_INV_GAMMA_BIAS_3_UNNAMED20 = 20, //!< No additional details 2804 }; 2805 2806 //! \brief PWL_INV_GAMMA_BIAS_4 2807 //! \details 2808 //! Bias 4 for PWL for inverse gamma correction 2809 enum PWL_INV_GAMMA_BIAS_4 2810 { 2811 PWL_INV_GAMMA_BIAS_4_UNNAMED33 = 33, //!< No additional details 2812 }; 2813 2814 //! \brief PWL_INV_GAMMA_BIAS_5 2815 //! \details 2816 //! Bias 5 for PWL for inverse gamma correction 2817 enum PWL_INV_GAMMA_BIAS_5 2818 { 2819 PWL_INV_GAMMA_BIAS_5_UNNAMED49 = 49, //!< No additional details 2820 }; 2821 2822 //! \brief PWL_INV_GAMMA_BIAS_6 2823 //! \details 2824 //! Bias 6 for PWL for inverse gamma correction 2825 enum PWL_INV_GAMMA_BIAS_6 2826 { 2827 PWL_INV_GAMMA_BIAS_6_UNNAMED67 = 67, //!< No additional details 2828 }; 2829 2830 //! \brief PWL_INV_GAMMA_BIAS_7 2831 //! \details 2832 //! Bias 7 for PWL for inverse gamma correction 2833 enum PWL_INV_GAMMA_BIAS_7 2834 { 2835 PWL_INV_GAMMA_BIAS_7_UNNAMED92 = 92, //!< No additional details 2836 }; 2837 2838 //! \brief PWL_INV_GAMMA_BIAS_8 2839 //! \details 2840 //! Bias 8 for PWL for inverse gamma correction 2841 enum PWL_INV_GAMMA_BIAS_8 2842 { 2843 PWL_INV_GAMMA_BIAS_8_UNNAMED117 = 117, //!< No additional details 2844 }; 2845 2846 //! \brief PWL_INV_GAMMA_BIAS_9 2847 //! \details 2848 //! Bias 9 for PWL for inverse gamma correction 2849 enum PWL_INV_GAMMA_BIAS_9 2850 { 2851 PWL_INV_GAMMA_BIAS_9_UNNAMED147 = 147, //!< No additional details 2852 }; 2853 2854 //! \brief PWL_INV_GAMMA_BIAS_10 2855 //! \details 2856 //! Bias 10 for PWL for inverse gamma correction 2857 enum PWL_INV_GAMMA_BIAS_10 2858 { 2859 PWL_INV_GAMMA_BIAS_10_UNNAMED180 = 180, //!< No additional details 2860 }; 2861 2862 //! \brief PWL_INV_GAMMA_BIAS_11 2863 //! \details 2864 //! Bias 11 for PWL for inverse gamma correction 2865 enum PWL_INV_GAMMA_BIAS_11 2866 { 2867 PWL_INV_GAMMA_BIAS_11_UNNAMED215 = 215, //!< No additional details 2868 }; 2869 2870 //! \brief OFFSET_IN_R 2871 //! \details 2872 //! The input offset for red component 2873 enum OFFSET_IN_R 2874 { 2875 OFFSET_IN_R_UNNAMED0 = 0, //!< No additional details 2876 }; 2877 2878 //! \brief OFFSET_IN_G 2879 //! \details 2880 //! The input offset for green component 2881 enum OFFSET_IN_G 2882 { 2883 OFFSET_IN_G_UNNAMED0 = 0, //!< No additional details 2884 }; 2885 2886 //! \brief OFFSET_IN_B 2887 //! \details 2888 //! The input offset for red component 2889 enum OFFSET_IN_B 2890 { 2891 OFFSET_IN_B_UNNAMED0 = 0, //!< No additional details 2892 }; 2893 2894 //! \brief D1OUT 2895 //! \details 2896 //! OuterTriangleMappingLengthBelow 2897 enum D1OUT 2898 { 2899 D1OUT_UNNAMED287 = 287, //!< No additional details 2900 }; 2901 2902 //! \brief DOUT_DEFAULT 2903 //! \details 2904 //! OuterTriangleMappingLength 2905 enum DOUT_DEFAULT 2906 { 2907 DOUT_DEFAULT_UNNAMED164 = 164, //!< No additional details 2908 }; 2909 2910 //! \brief DINDEFAULT 2911 //! \details 2912 //! InnerTriangleMappingLength 2913 enum DINDEFAULT 2914 { 2915 DINDEFAULT_UNNAMED205 = 205, //!< No additional details 2916 }; 2917 2918 enum FULLRANGEMAPPINGENABLE 2919 { 2920 FULLRANGEMAPPINGENABLE_BASICMODE = 0, //!< No additional details 2921 FULLRANGEMAPPINGENABLE_ADVANCEMODE = 1, //!< No additional details 2922 }; 2923 2924 //! \brief D1IN 2925 //! \details 2926 //! InnerTriangleMappingLengthBelow 2927 enum D1IN 2928 { 2929 D1IN_UNNAMED820 = 820, //!< No additional details 2930 }; 2931 2932 enum COMPRESSIONLINESHIFT 2933 { 2934 COMPRESSIONLINESHIFT_UNNAMED3 = 3, //!< No additional details 2935 }; 2936 2937 //! \brief XVYCCDECENCENABLE 2938 //! \details 2939 //! This bit is valid only when ColorGamutCompressionnEnable is on. 2940 enum XVYCCDECENCENABLE 2941 { 2942 XVYCCDECENCENABLE_TODISABLEBOTHXVYCCDECODEANDXVYCCENCODE = 0, //!< No additional details 2943 XVYCCDECENCENABLE_BOTHXVYCCDECODEANDXVYCCENCODEAREENABLED = 1, //!< No additional details 2944 }; 2945 2946 enum CPI_OVERRIDE 2947 { 2948 CPI_OVERRIDE_UNNAMED0 = 0, //!< No additional details 2949 CPI_OVERRIDE_OVERRIDECPICALCULATION = 1, //!< No additional details 2950 }; 2951 2952 enum LUMACHORMAONLYCORRECTION 2953 { 2954 LUMACHORMAONLYCORRECTION_LUMAONLYCORRECTION = 0, //!< No additional details 2955 LUMACHORMAONLYCORRECTION_CHORMAONLYCORRECTION = 1, //!< No additional details 2956 }; 2957 2958 enum GCC_BASICMODESELECTION 2959 { 2960 GCC_BASICMODESELECTION_DEFAULT = 0, //!< No additional details 2961 GCC_BASICMODESELECTION_SCALINGFACTOR = 1, //!< Used along with Dword66 Bits 28:11 2962 GCC_BASICMODESELECTION_SINGLEAXISGAMMACORRECTION = 2, //!< Used along with Dword67 Bit 29 2963 GCC_BASICMODESELECTION_SCALINGFACTORWITHFIXEDLUMA = 3, //!< Used along with Dword37 Bits 28:11 2964 }; 2965 2966 //! \name Initializations 2967 2968 //! \brief Explicit member initialization function 2969 VEBOX_GAMUT_STATE_CMD(); 2970 2971 static const size_t dwSize = 38; 2972 static const size_t byteSize = 152; 2973 }; 2974 2975 //! 2976 //! \brief VEBOX_STD_STE_STATE 2977 //! \details 2978 //! This state structure contains the state used by the STD/STE function. 2979 //! 2980 struct VEBOX_STD_STE_STATE_CMD 2981 { 2982 union 2983 { 2984 struct 2985 { 2986 uint32_t StdEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< STD Enable 2987 uint32_t SteEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< STE Enable 2988 uint32_t OutputControl : __CODEGEN_BITFIELD( 2, 2) ; //!< OUTPUT_CONTROL 2989 uint32_t Reserved3 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 2990 uint32_t SatMax : __CODEGEN_BITFIELD( 4, 9) ; //!< SAT_MAX 2991 uint32_t HueMax : __CODEGEN_BITFIELD(10, 15) ; //!< HUE_MAX 2992 uint32_t UMid : __CODEGEN_BITFIELD(16, 23) ; //!< U_MID 2993 uint32_t VMid : __CODEGEN_BITFIELD(24, 31) ; //!< V_MID 2994 }; 2995 uint32_t Value; 2996 } DW0; 2997 union 2998 { 2999 struct 3000 { 3001 uint32_t Sin : __CODEGEN_BITFIELD( 0, 7) ; //!< SIN 3002 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 9) ; //!< Reserved 3003 uint32_t Cos : __CODEGEN_BITFIELD(10, 17) ; //!< COS 3004 uint32_t HsMargin : __CODEGEN_BITFIELD(18, 20) ; //!< HS_MARGIN 3005 uint32_t DiamondDu : __CODEGEN_BITFIELD(21, 27) ; //!< DIAMOND_DU 3006 uint32_t DiamondMargin : __CODEGEN_BITFIELD(28, 30) ; //!< DIAMOND_MARGIN 3007 uint32_t StdScoreOutput : __CODEGEN_BITFIELD(31, 31) ; //!< STD Score Output 3008 }; 3009 uint32_t Value; 3010 } DW1; 3011 union 3012 { 3013 struct 3014 { 3015 uint32_t DiamondDv : __CODEGEN_BITFIELD( 0, 6) ; //!< DIAMOND_DV 3016 uint32_t DiamondTh : __CODEGEN_BITFIELD( 7, 12) ; //!< DIAMOND_TH 3017 uint32_t DiamondAlpha : __CODEGEN_BITFIELD(13, 20) ; //!< DIAMOND_ALPHA 3018 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 3019 }; 3020 uint32_t Value; 3021 } DW2; 3022 union 3023 { 3024 struct 3025 { 3026 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 3027 uint32_t VyStdEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< VY_STD_Enable 3028 uint32_t YPoint1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y_POINT_1 3029 uint32_t YPoint2 : __CODEGEN_BITFIELD(16, 23) ; //!< Y_POINT_2 3030 uint32_t YPoint3 : __CODEGEN_BITFIELD(24, 31) ; //!< Y_POINT_3 3031 }; 3032 uint32_t Value; 3033 } DW3; 3034 union 3035 { 3036 struct 3037 { 3038 uint32_t YPoint4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y_POINT_4 3039 uint32_t YSlope1 : __CODEGEN_BITFIELD( 8, 12) ; //!< Y_SLOPE_1 3040 uint32_t YSlope2 : __CODEGEN_BITFIELD(13, 17) ; //!< Y_SLOPE_2 3041 uint32_t Reserved146 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 3042 }; 3043 uint32_t Value; 3044 } DW4; 3045 union 3046 { 3047 struct 3048 { 3049 uint32_t InvMarginVyl : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYL 3050 uint32_t InvSkinTypesMargin : __CODEGEN_BITFIELD(16, 31) ; //!< INV_SKIN_TYPES_MARGIN 3051 }; 3052 uint32_t Value; 3053 } DW5; 3054 union 3055 { 3056 struct 3057 { 3058 uint32_t InvMarginVyu : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_MARGIN_VYU 3059 uint32_t P0L : __CODEGEN_BITFIELD(16, 23) ; //!< P0L 3060 uint32_t P1L : __CODEGEN_BITFIELD(24, 31) ; //!< P1L 3061 }; 3062 uint32_t Value; 3063 } DW6; 3064 union 3065 { 3066 struct 3067 { 3068 uint32_t P2L : __CODEGEN_BITFIELD( 0, 7) ; //!< P2L 3069 uint32_t P3L : __CODEGEN_BITFIELD( 8, 15) ; //!< P3L 3070 uint32_t B0L : __CODEGEN_BITFIELD(16, 23) ; //!< B0L 3071 uint32_t B1L : __CODEGEN_BITFIELD(24, 31) ; //!< B1L 3072 }; 3073 uint32_t Value; 3074 } DW7; 3075 union 3076 { 3077 struct 3078 { 3079 uint32_t B2L : __CODEGEN_BITFIELD( 0, 7) ; //!< B2L 3080 uint32_t B3L : __CODEGEN_BITFIELD( 8, 15) ; //!< B3L 3081 uint32_t S0L : __CODEGEN_BITFIELD(16, 26) ; //!< S0L 3082 uint32_t Reserved283 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3083 }; 3084 uint32_t Value; 3085 } DW8; 3086 union 3087 { 3088 struct 3089 { 3090 uint32_t S1L : __CODEGEN_BITFIELD( 0, 10) ; //!< S1L 3091 uint32_t S2L : __CODEGEN_BITFIELD(11, 21) ; //!< S2L 3092 uint32_t Reserved310 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 3093 }; 3094 uint32_t Value; 3095 } DW9; 3096 union 3097 { 3098 struct 3099 { 3100 uint32_t S3L : __CODEGEN_BITFIELD( 0, 10) ; //!< S3L 3101 uint32_t P0U : __CODEGEN_BITFIELD(11, 18) ; //!< P0U 3102 uint32_t P1U : __CODEGEN_BITFIELD(19, 26) ; //!< P1U 3103 uint32_t Reserved347 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3104 }; 3105 uint32_t Value; 3106 } DW10; 3107 union 3108 { 3109 struct 3110 { 3111 uint32_t P2U : __CODEGEN_BITFIELD( 0, 7) ; //!< P2U 3112 uint32_t P3U : __CODEGEN_BITFIELD( 8, 15) ; //!< P3U 3113 uint32_t B0U : __CODEGEN_BITFIELD(16, 23) ; //!< B0U 3114 uint32_t B1U : __CODEGEN_BITFIELD(24, 31) ; //!< B1U 3115 }; 3116 uint32_t Value; 3117 } DW11; 3118 union 3119 { 3120 struct 3121 { 3122 uint32_t B2U : __CODEGEN_BITFIELD( 0, 7) ; //!< B2U 3123 uint32_t B3U : __CODEGEN_BITFIELD( 8, 15) ; //!< B3U 3124 uint32_t S0U : __CODEGEN_BITFIELD(16, 26) ; //!< S0U 3125 uint32_t Reserved411 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3126 }; 3127 uint32_t Value; 3128 } DW12; 3129 union 3130 { 3131 struct 3132 { 3133 uint32_t S1U : __CODEGEN_BITFIELD( 0, 10) ; //!< S1U 3134 uint32_t S2U : __CODEGEN_BITFIELD(11, 21) ; //!< S2U 3135 uint32_t Reserved438 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 3136 }; 3137 uint32_t Value; 3138 } DW13; 3139 union 3140 { 3141 struct 3142 { 3143 uint32_t S3U : __CODEGEN_BITFIELD( 0, 10) ; //!< S3U 3144 uint32_t SkinTypesEnable : __CODEGEN_BITFIELD(11, 11) ; //!< SKIN_TYPES_ENABLE 3145 uint32_t SkinTypesThresh : __CODEGEN_BITFIELD(12, 19) ; //!< SKIN_TYPES_THRESH 3146 uint32_t SkinTypesMargin : __CODEGEN_BITFIELD(20, 27) ; //!< SKIN_TYPES_MARGIN 3147 uint32_t Reserved476 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 3148 }; 3149 uint32_t Value; 3150 } DW14; 3151 union 3152 { 3153 struct 3154 { 3155 uint32_t Satp1 : __CODEGEN_BITFIELD( 0, 6) ; //!< SATP1 3156 uint32_t Satp2 : __CODEGEN_BITFIELD( 7, 13) ; //!< SATP2 3157 uint32_t Satp3 : __CODEGEN_BITFIELD(14, 20) ; //!< SATP3 3158 uint32_t Satb1 : __CODEGEN_BITFIELD(21, 30) ; //!< SATB1 3159 uint32_t Reserved511 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3160 }; 3161 uint32_t Value; 3162 } DW15; 3163 union 3164 { 3165 struct 3166 { 3167 uint32_t Satb2 : __CODEGEN_BITFIELD( 0, 9) ; //!< SATB2 3168 uint32_t Satb3 : __CODEGEN_BITFIELD(10, 19) ; //!< SATB3 3169 uint32_t Sats0 : __CODEGEN_BITFIELD(20, 30) ; //!< SATS0 3170 uint32_t Reserved543 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3171 }; 3172 uint32_t Value; 3173 } DW16; 3174 union 3175 { 3176 struct 3177 { 3178 uint32_t Sats1 : __CODEGEN_BITFIELD( 0, 10) ; //!< SATS1 3179 uint32_t Sats2 : __CODEGEN_BITFIELD(11, 21) ; //!< SATS2 3180 uint32_t Reserved566 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 3181 }; 3182 uint32_t Value; 3183 } DW17; 3184 union 3185 { 3186 struct 3187 { 3188 uint32_t Sats3 : __CODEGEN_BITFIELD( 0, 10) ; //!< SATS3 3189 uint32_t Huep1 : __CODEGEN_BITFIELD(11, 17) ; //!< HUEP1 3190 uint32_t Huep2 : __CODEGEN_BITFIELD(18, 24) ; //!< HUEP2 3191 uint32_t Huep3 : __CODEGEN_BITFIELD(25, 31) ; //!< HUEP3 3192 }; 3193 uint32_t Value; 3194 } DW18; 3195 union 3196 { 3197 struct 3198 { 3199 uint32_t Hueb1 : __CODEGEN_BITFIELD( 0, 9) ; //!< HUEB1 3200 uint32_t Hueb2 : __CODEGEN_BITFIELD(10, 19) ; //!< HUEB2 3201 uint32_t Hueb3 : __CODEGEN_BITFIELD(20, 29) ; //!< HUEB3 3202 uint32_t Reserved638 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3203 }; 3204 uint32_t Value; 3205 } DW19; 3206 union 3207 { 3208 struct 3209 { 3210 uint32_t Hues0 : __CODEGEN_BITFIELD( 0, 10) ; //!< HUES0 3211 uint32_t Hues1 : __CODEGEN_BITFIELD(11, 21) ; //!< HUES1 3212 uint32_t Reserved662 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 3213 }; 3214 uint32_t Value; 3215 } DW20; 3216 union 3217 { 3218 struct 3219 { 3220 uint32_t Hues2 : __CODEGEN_BITFIELD( 0, 10) ; //!< HUES2 3221 uint32_t Hues3 : __CODEGEN_BITFIELD(11, 21) ; //!< HUES3 3222 uint32_t Reserved694 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 3223 }; 3224 uint32_t Value; 3225 } DW21; 3226 union 3227 { 3228 struct 3229 { 3230 uint32_t Satp1Dark : __CODEGEN_BITFIELD( 0, 6) ; //!< SATP1_DARK 3231 uint32_t Satp2Dark : __CODEGEN_BITFIELD( 7, 13) ; //!< SATP2_DARK 3232 uint32_t Satp3Dark : __CODEGEN_BITFIELD(14, 20) ; //!< SATP3_DARK 3233 uint32_t Satb1Dark : __CODEGEN_BITFIELD(21, 30) ; //!< SATB1_DARK 3234 uint32_t Reserved735 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3235 }; 3236 uint32_t Value; 3237 } DW22; 3238 union 3239 { 3240 struct 3241 { 3242 uint32_t Satb2Dark : __CODEGEN_BITFIELD( 0, 9) ; //!< SATB2_DARK 3243 uint32_t Satb3Dark : __CODEGEN_BITFIELD(10, 19) ; //!< SATB3_DARK 3244 uint32_t Sats0Dark : __CODEGEN_BITFIELD(20, 30) ; //!< SATS0_DARK 3245 uint32_t Reserved767 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3246 }; 3247 uint32_t Value; 3248 } DW23; 3249 union 3250 { 3251 struct 3252 { 3253 uint32_t Sats1Dark : __CODEGEN_BITFIELD( 0, 10) ; //!< SATS1_DARK 3254 uint32_t Sats2Dark : __CODEGEN_BITFIELD(11, 21) ; //!< SATS2_DARK 3255 uint32_t Reserved790 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 3256 }; 3257 uint32_t Value; 3258 } DW24; 3259 union 3260 { 3261 struct 3262 { 3263 uint32_t Sats3Dark : __CODEGEN_BITFIELD( 0, 10) ; //!< SATS3_DARK 3264 uint32_t Huep1Dark : __CODEGEN_BITFIELD(11, 17) ; //!< HUEP1_DARK 3265 uint32_t Huep2Dark : __CODEGEN_BITFIELD(18, 24) ; //!< HUEP2_DARK 3266 uint32_t Huep3Dark : __CODEGEN_BITFIELD(25, 31) ; //!< HUEP3_DARK 3267 }; 3268 uint32_t Value; 3269 } DW25; 3270 union 3271 { 3272 struct 3273 { 3274 uint32_t Hueb1Dark : __CODEGEN_BITFIELD( 0, 9) ; //!< HUEB1_DARK 3275 uint32_t Hueb2Dark : __CODEGEN_BITFIELD(10, 19) ; //!< HUEB2_DARK 3276 uint32_t Hueb3Dark : __CODEGEN_BITFIELD(20, 29) ; //!< HUEB3_DARK 3277 uint32_t Reserved862 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3278 }; 3279 uint32_t Value; 3280 } DW26; 3281 union 3282 { 3283 struct 3284 { 3285 uint32_t Hues0Dark : __CODEGEN_BITFIELD( 0, 10) ; //!< HUES0_DARK 3286 uint32_t Hues1Dark : __CODEGEN_BITFIELD(11, 21) ; //!< HUES1_DARK 3287 uint32_t Reserved886 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 3288 }; 3289 uint32_t Value; 3290 } DW27; 3291 union 3292 { 3293 struct 3294 { 3295 uint32_t Hues2Dark : __CODEGEN_BITFIELD( 0, 10) ; //!< HUES2_DARK 3296 uint32_t Hues3Dark : __CODEGEN_BITFIELD(11, 21) ; //!< HUES3_DARK 3297 uint32_t Reserved918 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 3298 }; 3299 uint32_t Value; 3300 } DW28; 3301 3302 //! \name Local enumerations 3303 3304 enum OUTPUT_CONTROL 3305 { 3306 OUTPUT_CONTROL_OUTPUTPIXELS = 0, //!< No additional details 3307 OUTPUT_CONTROL_OUTPUTSTDDECISIONS = 1, //!< No additional details 3308 }; 3309 3310 //! \brief SAT_MAX 3311 //! \details 3312 //! Rectangle half length. 3313 enum SAT_MAX 3314 { 3315 SAT_MAX_UNNAMED31 = 31, //!< No additional details 3316 }; 3317 3318 //! \brief HUE_MAX 3319 //! \details 3320 //! Rectangle half width. 3321 enum HUE_MAX 3322 { 3323 HUE_MAX_UNNAMED14 = 14, //!< No additional details 3324 }; 3325 3326 //! \brief U_MID 3327 //! \details 3328 //! Rectangle middle-point U coordinate. 3329 enum U_MID 3330 { 3331 U_MID_UNNAMED110 = 110, //!< No additional details 3332 }; 3333 3334 //! \brief V_MID 3335 //! \details 3336 //! Rectangle middle-point V coordinate. 3337 enum V_MID 3338 { 3339 V_MID_UNNAMED154 = 154, //!< No additional details 3340 }; 3341 3342 //! \brief SIN 3343 //! \details 3344 //! The default is 101/128 3345 enum SIN 3346 { 3347 SIN_UNNAMED101 = 101, //!< No additional details 3348 }; 3349 3350 //! \brief COS 3351 //! \details 3352 //! The default is 79/128 3353 enum COS 3354 { 3355 COS_UNNAMED79 = 79, //!< No additional details 3356 }; 3357 3358 //! \brief HS_MARGIN 3359 //! \details 3360 //! Defines rectangle margin. 3361 enum HS_MARGIN 3362 { 3363 HS_MARGIN_UNNAMED3 = 3, //!< No additional details 3364 }; 3365 3366 //! \brief DIAMOND_DU 3367 //! \details 3368 //! Rhombus center shift in the sat-direction, relative to the rectangle 3369 //! center. 3370 enum DIAMOND_DU 3371 { 3372 DIAMOND_DU_UNNAMED0 = 0, //!< No additional details 3373 }; 3374 3375 enum DIAMOND_MARGIN 3376 { 3377 DIAMOND_MARGIN_UNNAMED4 = 4, //!< No additional details 3378 }; 3379 3380 //! \brief DIAMOND_DV 3381 //! \details 3382 //! Rhombus center shift in the hue-direction, relative to the rectangle 3383 //! center. 3384 enum DIAMOND_DV 3385 { 3386 DIAMOND_DV_UNNAMED0 = 0, //!< No additional details 3387 }; 3388 3389 //! \brief DIAMOND_TH 3390 //! \details 3391 //! Half length of the rhombus axis in the sat-direction. 3392 enum DIAMOND_TH 3393 { 3394 DIAMOND_TH_UNNAMED35 = 35, //!< No additional details 3395 }; 3396 3397 //! \brief DIAMOND_ALPHA 3398 //! \details 3399 //! 1/tan(β) 3400 //! The default is 100/64 3401 enum DIAMOND_ALPHA 3402 { 3403 DIAMOND_ALPHA_UNNAMED100 = 100, //!< No additional details 3404 }; 3405 3406 //! \brief Y_POINT_1 3407 //! \details 3408 //! First point of the Y piecewise linear membership function. 3409 enum Y_POINT_1 3410 { 3411 Y_POINT_1_UNNAMED46 = 46, //!< No additional details 3412 }; 3413 3414 //! \brief Y_POINT_2 3415 //! \details 3416 //! Second point of the Y piecewise linear membership function. 3417 enum Y_POINT_2 3418 { 3419 Y_POINT_2_UNNAMED47 = 47, //!< No additional details 3420 }; 3421 3422 //! \brief Y_POINT_3 3423 //! \details 3424 //! Third point of the Y piecewise linear membership function. 3425 enum Y_POINT_3 3426 { 3427 Y_POINT_3_UNNAMED254 = 254, //!< No additional details 3428 }; 3429 3430 //! \brief Y_POINT_4 3431 //! \details 3432 //! Fourth point of the Y piecewise linear membership function. 3433 enum Y_POINT_4 3434 { 3435 Y_POINT_4_UNNAMED255 = 255, //!< No additional details 3436 }; 3437 3438 //! \brief Y_SLOPE_1 3439 //! \details 3440 //! Slope between points Y1 and Y2. 3441 enum Y_SLOPE_1 3442 { 3443 Y_SLOPE_1_UNNAMED31 = 31, //!< No additional details 3444 }; 3445 3446 //! \brief Y_SLOPE_2 3447 //! \details 3448 //! Slope between points Y3 and Y4. 3449 enum Y_SLOPE_2 3450 { 3451 Y_SLOPE_2_UNNAMED31 = 31, //!< No additional details 3452 }; 3453 3454 //! \brief INV_SKIN_TYPES_MARGIN 3455 //! \details 3456 //! 1/(2* Skin_types_margin) 3457 enum INV_SKIN_TYPES_MARGIN 3458 { 3459 INV_SKIN_TYPES_MARGIN_SKINTYPEMARGIN = 20, //!< No additional details 3460 INV_SKIN_TYPES_MARGIN_UNNAMED1638 = 1638, //!< No additional details 3461 }; 3462 3463 //! \brief INV_MARGIN_VYU 3464 //! \details 3465 //! 1 / Margin_VYU = 1600/65536 3466 enum INV_MARGIN_VYU 3467 { 3468 INV_MARGIN_VYU_UNNAMED1600 = 1600, //!< No additional details 3469 }; 3470 3471 //! \brief P0L 3472 //! \details 3473 //! Y Point 0 of the lower part of the detection PWLF. 3474 enum P0L 3475 { 3476 P0L_UNNAMED46 = 46, //!< No additional details 3477 }; 3478 3479 //! \brief P1L 3480 //! \details 3481 //! Y Point 1 of the lower part of the detection PWLF. 3482 enum P1L 3483 { 3484 P1L_UNNAMED216 = 216, //!< No additional details 3485 }; 3486 3487 //! \brief P2L 3488 //! \details 3489 //! Y Point 2 of the lower part of the detection PWLF. 3490 enum P2L 3491 { 3492 P2L_UNNAMED236 = 236, //!< No additional details 3493 }; 3494 3495 //! \brief P3L 3496 //! \details 3497 //! Y Point 3 of the lower part of the detection PWLF. 3498 enum P3L 3499 { 3500 P3L_UNNAMED236 = 236, //!< No additional details 3501 }; 3502 3503 //! \brief B0L 3504 //! \details 3505 //! V Bias 0 of the lower part of the detection PWLF. 3506 enum B0L 3507 { 3508 B0L_UNNAMED133 = 133, //!< No additional details 3509 }; 3510 3511 //! \brief B1L 3512 //! \details 3513 //! V Bias 1 of the lower part of the detection PWLF. 3514 enum B1L 3515 { 3516 B1L_UNNAMED130 = 130, //!< No additional details 3517 }; 3518 3519 //! \brief B2L 3520 //! \details 3521 //! V Bias 2 of the lower part of the detection PWLF. 3522 enum B2L 3523 { 3524 B2L_UNNAMED130 = 130, //!< No additional details 3525 }; 3526 3527 //! \brief B3L 3528 //! \details 3529 //! V Bias 3 of the lower part of the detection PWLF. 3530 enum B3L 3531 { 3532 B3L_UNNAMED130 = 130, //!< No additional details 3533 }; 3534 3535 //! \brief S0L 3536 //! \details 3537 //! Slope 0 of the lower part of the detection PWLF. 3538 enum S0L 3539 { 3540 S0L_UNNAMED2043 = 2043, //!< No additional details 3541 }; 3542 3543 //! \brief S1L 3544 //! \details 3545 //! Slope 1 of the lower part of the detection PWLF. 3546 enum S1L 3547 { 3548 S1L_UNNAMED0 = 0, //!< No additional details 3549 }; 3550 3551 //! \brief S2L 3552 //! \details 3553 //! The default is 0/256 3554 enum S2L 3555 { 3556 S2L_UNNAMED0 = 0, //!< No additional details 3557 }; 3558 3559 //! \brief S3L 3560 //! \details 3561 //! Slope 3 of the lower part of the detection PWLF. 3562 enum S3L 3563 { 3564 S3L_UNNAMED0 = 0, //!< No additional details 3565 }; 3566 3567 //! \brief P0U 3568 //! \details 3569 //! Y Point 0 of the upper part of the detection PWLF. 3570 enum P0U 3571 { 3572 P0U_UNNAMED46 = 46, //!< No additional details 3573 }; 3574 3575 //! \brief P1U 3576 //! \details 3577 //! Y Point 1 of the upper part of the detection PWLF. 3578 enum P1U 3579 { 3580 P1U_UNNAMED66 = 66, //!< No additional details 3581 }; 3582 3583 //! \brief P2U 3584 //! \details 3585 //! Y Point 2 of the upper part of the detection PWLF. 3586 enum P2U 3587 { 3588 P2U_UNNAMED150 = 150, //!< No additional details 3589 }; 3590 3591 //! \brief P3U 3592 //! \details 3593 //! Y Point 3 of the upper part of the detection PWLF. 3594 enum P3U 3595 { 3596 P3U_UNNAMED236 = 236, //!< No additional details 3597 }; 3598 3599 //! \brief B0U 3600 //! \details 3601 //! V Bias 0 of the upper part of the detection PWLF. 3602 enum B0U 3603 { 3604 B0U_UNNAMED143 = 143, //!< No additional details 3605 }; 3606 3607 //! \brief B1U 3608 //! \details 3609 //! V Bias 1 of the upper part of the detection PWLF. 3610 enum B1U 3611 { 3612 B1U_UNNAMED163 = 163, //!< No additional details 3613 }; 3614 3615 //! \brief B2U 3616 //! \details 3617 //! V Bias 2 of the upper part of the detection PWLF. 3618 enum B2U 3619 { 3620 B2U_UNNAMED200 = 200, //!< No additional details 3621 }; 3622 3623 //! \brief B3U 3624 //! \details 3625 //! V Bias 3 of the upper part of the detection PWLF. 3626 enum B3U 3627 { 3628 B3U_UNNAMED140 = 140, //!< No additional details 3629 B3U_UNNAMED200 = 200, //!< No additional details 3630 }; 3631 3632 //! \brief S0U 3633 //! \details 3634 //! Slope 0 of the upper part of the detection PWLF. 3635 enum S0U 3636 { 3637 S0U_UNNAMED256 = 256, //!< No additional details 3638 }; 3639 3640 //! \brief S1U 3641 //! \details 3642 //! Slope 1 of the upper part of the detection PWLF. 3643 enum S1U 3644 { 3645 S1U_UNNAMED113 = 113, //!< No additional details 3646 }; 3647 3648 //! \brief S2U 3649 //! \details 3650 //! Slope 2 of the upper part of the detection PWLF. 3651 enum S2U 3652 { 3653 S2U_UNNAMED1869 = 1869, //!< No additional details 3654 }; 3655 3656 //! \brief S3U 3657 //! \details 3658 //! Slope 3 of the upper part of the detection PWLF. 3659 enum S3U 3660 { 3661 S3U_UNNAMED0 = 0, //!< No additional details 3662 }; 3663 3664 //! \brief SKIN_TYPES_ENABLE 3665 //! \details 3666 //! Treat differently bright and dark skin types 3667 enum SKIN_TYPES_ENABLE 3668 { 3669 SKIN_TYPES_ENABLE_DISABLE = 0, //!< No additional details 3670 }; 3671 3672 //! \brief SKIN_TYPES_THRESH 3673 //! \details 3674 //! Skin types Y margin 3675 //! Restrict Skin_types_thresh >= Skin_types_margin > 0 3676 //! Restrict (Skin_types_thresh + Skin_types_margin) <= 255 3677 enum SKIN_TYPES_THRESH 3678 { 3679 SKIN_TYPES_THRESH_UNNAMED120 = 120, //!< No additional details 3680 }; 3681 3682 //! \brief SKIN_TYPES_MARGIN 3683 //! \details 3684 //! Skin types Y margin 3685 //! Restrict Skin_types_thresh >= Skin_types_margin > 0 3686 //! Restrict (Skin_types_thresh + Skin_types_margin) <= 255 3687 enum SKIN_TYPES_MARGIN 3688 { 3689 SKIN_TYPES_MARGIN_UNNAMED20 = 20, //!< No additional details 3690 }; 3691 3692 //! \brief SATP1 3693 //! \details 3694 //! First point for the saturation PWLF (bright skin). 3695 //! The default numerical valueis -6/64. 3696 enum SATP1 3697 { 3698 SATP1_UNNAMED122 = 122, //!< No additional details 3699 }; 3700 3701 //! \brief SATP2 3702 //! \details 3703 //! Second point for the saturation PWLF (bright skin). 3704 enum SATP2 3705 { 3706 SATP2_UNNAMED6 = 6, //!< No additional details 3707 }; 3708 3709 //! \brief SATP3 3710 //! \details 3711 //! Third point for the saturation PWLF (bright skin). 3712 enum SATP3 3713 { 3714 SATP3_UNNAMED31 = 31, //!< No additional details 3715 }; 3716 3717 //! \brief SATB1 3718 //! \details 3719 //! First bias for the saturation PWLF (bright skin). 3720 enum SATB1 3721 { 3722 SATB1_UNNAMED1016 = 1016, //!< No additional details 3723 }; 3724 3725 //! \brief SATB2 3726 //! \details 3727 //! Second bias for the saturation PWLF (bright skin) 3728 enum SATB2 3729 { 3730 SATB2_UNNAMED8 = 8, //!< No additional details 3731 }; 3732 3733 //! \brief SATB3 3734 //! \details 3735 //! Third bias for the saturation PWLF (bright skin) 3736 enum SATB3 3737 { 3738 SATB3_UNNAMED124 = 124, //!< No additional details 3739 }; 3740 3741 //! \brief SATS0 3742 //! \details 3743 //! Zeroth slope for the saturation PWLF (bright skin) 3744 enum SATS0 3745 { 3746 SATS0_UNNAMED297 = 297, //!< No additional details 3747 }; 3748 3749 //! \brief SATS1 3750 //! \details 3751 //! First slope for the saturation PWLF (bright skin) 3752 enum SATS1 3753 { 3754 SATS1_UNNAMED85 = 85, //!< No additional details 3755 }; 3756 3757 //! \brief SATS2 3758 //! \details 3759 //! Second slope for the saturation PWLF (bright skin) 3760 enum SATS2 3761 { 3762 SATS2_UNNAMED297 = 297, //!< No additional details 3763 }; 3764 3765 //! \brief SATS3 3766 //! \details 3767 //! Third slope for the saturation PWLF (bright skin) 3768 enum SATS3 3769 { 3770 SATS3_UNNAMED256 = 256, //!< No additional details 3771 }; 3772 3773 //! \brief HUEP1 3774 //! \details 3775 //! First point for the hue PWLF (bright skin) 3776 enum HUEP1 3777 { 3778 HUEP1_6 = 122, //!< No additional details 3779 }; 3780 3781 //! \brief HUEP2 3782 //! \details 3783 //! Second point for the hue PWLF (bright skin) 3784 enum HUEP2 3785 { 3786 HUEP2_UNNAMED6 = 6, //!< No additional details 3787 }; 3788 3789 //! \brief HUEP3 3790 //! \details 3791 //! Third point for the hue PWLF (bright skin) 3792 enum HUEP3 3793 { 3794 HUEP3_UNNAMED14 = 14, //!< No additional details 3795 }; 3796 3797 //! \brief HUEB1 3798 //! \details 3799 //! First bias for the hue PWLF (bright skin) 3800 enum HUEB1 3801 { 3802 HUEB1_UNNAMED8 = 8, //!< No additional details 3803 HUEB1_UNNAMED248 = 248, //!< No additional details 3804 }; 3805 3806 //! \brief HUEB2 3807 //! \details 3808 //! Second bias for the hue PWLF (bright skin) 3809 enum HUEB2 3810 { 3811 HUEB2_UNNAMED8 = 8, //!< No additional details 3812 }; 3813 3814 //! \brief HUEB3 3815 //! \details 3816 //! Third bias for the hue PWLF (bright skin) 3817 enum HUEB3 3818 { 3819 HUEB3_UNNAMED56 = 56, //!< No additional details 3820 }; 3821 3822 //! \brief HUES0 3823 //! \details 3824 //! Zeroth slope for the hue PWLF (bright skin) 3825 enum HUES0 3826 { 3827 HUES0_UNNAMED384 = 384, //!< No additional details 3828 }; 3829 3830 //! \brief HUES1 3831 //! \details 3832 //! First slope for the hue PWLF (bright skin) 3833 enum HUES1 3834 { 3835 HUES1_UNNAMED85 = 85, //!< No additional details 3836 }; 3837 3838 //! \brief HUES2 3839 //! \details 3840 //! Second slope for the hue PWLF (bright skin) 3841 enum HUES2 3842 { 3843 HUES2_UNNAMED384 = 384, //!< No additional details 3844 }; 3845 3846 //! \brief HUES3 3847 //! \details 3848 //! Third slope for the hue PWLF (bright skin) 3849 enum HUES3 3850 { 3851 HUES3_UNNAMED256 = 256, //!< No additional details 3852 }; 3853 3854 //! \brief SATP1_DARK 3855 //! \details 3856 //! First point for the saturation PWLF (dark skin) Default Value: -5 3857 enum SATP1_DARK 3858 { 3859 SATP1_DARK_UNNAMED123 = 123, //!< No additional details 3860 }; 3861 3862 //! \brief SATP2_DARK 3863 //! \details 3864 //! Second point for the saturation PWLF (dark skin) 3865 enum SATP2_DARK 3866 { 3867 SATP2_DARK_UNNAMED31 = 31, //!< No additional details 3868 }; 3869 3870 //! \brief SATP3_DARK 3871 //! \details 3872 //! Third point for the saturation PWLF (dark skin) 3873 enum SATP3_DARK 3874 { 3875 SATP3_DARK_UNNAMED31 = 31, //!< No additional details 3876 }; 3877 3878 //! \brief SATB1_DARK 3879 //! \details 3880 //! First bias for the saturation PWLF (dark skin) 3881 enum SATB1_DARK 3882 { 3883 SATB1_DARK_UNNAMED0 = 0, //!< No additional details 3884 }; 3885 3886 //! \brief SATB2_DARK 3887 //! \details 3888 //! Second bias for the saturation PWLF (dark skin) 3889 enum SATB2_DARK 3890 { 3891 SATB2_DARK_UNNAMED124 = 124, //!< No additional details 3892 }; 3893 3894 //! \brief SATB3_DARK 3895 //! \details 3896 //! Third bias for the saturation PWLF (dark skin) 3897 enum SATB3_DARK 3898 { 3899 SATB3_DARK_UNNAMED124 = 124, //!< No additional details 3900 }; 3901 3902 //! \brief SATS0_DARK 3903 //! \details 3904 //! Zeroth slope for the saturation PWLF (dark skin) 3905 enum SATS0_DARK 3906 { 3907 SATS0_DARK_UNNAMED397 = 397, //!< No additional details 3908 }; 3909 3910 //! \brief SATS1_DARK 3911 //! \details 3912 //! First slope for the saturation PWLF (dark skin) 3913 enum SATS1_DARK 3914 { 3915 SATS1_DARK_UNNAMED189 = 189, //!< No additional details 3916 }; 3917 3918 //! \brief SATS2_DARK 3919 //! \details 3920 //! Second slope for the saturation PWLF (dark skin) 3921 enum SATS2_DARK 3922 { 3923 SATS2_DARK_UNNAMED256 = 256, //!< No additional details 3924 }; 3925 3926 //! \brief SATS3_DARK 3927 //! \details 3928 //! Third slope for the saturation PWLF (dark skin) 3929 enum SATS3_DARK 3930 { 3931 SATS3_DARK_UNNAMED256 = 256, //!< No additional details 3932 }; 3933 3934 //! \brief HUEP1_DARK 3935 //! \details 3936 //! First point for the hue PWLF (dark skin). 3937 enum HUEP1_DARK 3938 { 3939 HUEP1_DARK_UNNAMED0 = 0, //!< No additional details 3940 }; 3941 3942 //! \brief HUEP2_DARK 3943 //! \details 3944 //! Second point for the hue PWLF (dark skin). 3945 enum HUEP2_DARK 3946 { 3947 HUEP2_DARK_UNNAMED2 = 2, //!< No additional details 3948 }; 3949 3950 //! \brief HUEP3_DARK 3951 //! \details 3952 //! Third point for the hue PWLF (dark skin). 3953 enum HUEP3_DARK 3954 { 3955 HUEP3_DARK_UNNAMED14 = 14, //!< No additional details 3956 }; 3957 3958 //! \brief HUEB1_DARK 3959 //! \details 3960 //! First bias for the hue PWLF (dark skin). 3961 enum HUEB1_DARK 3962 { 3963 HUEB1_DARK_UNNAMED0 = 0, //!< No additional details 3964 }; 3965 3966 //! \brief HUEB2_DARK 3967 //! \details 3968 //! Second bias for the hue PWLF (dark skin). 3969 enum HUEB2_DARK 3970 { 3971 HUEB2_DARK_UNNAMED0 = 0, //!< No additional details 3972 }; 3973 3974 //! \brief HUEB3_DARK 3975 //! \details 3976 //! Third bias for the hue PWLF (dark skin). 3977 enum HUEB3_DARK 3978 { 3979 HUEB3_DARK_UNNAMED56 = 56, //!< No additional details 3980 }; 3981 3982 //! \brief HUES0_DARK 3983 //! \details 3984 //! Zeroth slope for the hue PWLF (dark skin). 3985 enum HUES0_DARK 3986 { 3987 HUES0_DARK_UNNAMED256 = 256, //!< No additional details 3988 HUES0_DARK_UNNAMED299 = 299, //!< No additional details 3989 }; 3990 3991 //! \brief HUES1_DARK 3992 //! \details 3993 //! First slope for the hue PWLF (dark skin). 3994 enum HUES1_DARK 3995 { 3996 HUES1_DARK_UNNAMED256 = 256, //!< No additional details 3997 }; 3998 3999 //! \brief HUES2_DARK 4000 //! \details 4001 //! Second slope for the hue PWLF (dark skin). 4002 enum HUES2_DARK 4003 { 4004 HUES2_DARK_UNNAMED299 = 299, //!< No additional details 4005 }; 4006 4007 //! \brief HUES3_DARK 4008 //! \details 4009 //! Third slope for the hue PWLF (dark skin). 4010 enum HUES3_DARK 4011 { 4012 HUES3_DARK_UNNAMED256 = 256, //!< No additional details 4013 }; 4014 4015 //! \name Initializations 4016 4017 //! \brief Explicit member initialization function 4018 VEBOX_STD_STE_STATE_CMD(); 4019 4020 static const size_t dwSize = 29; 4021 static const size_t byteSize = 116; 4022 }; 4023 4024 //! 4025 //! \brief VEBOX_TCC_STATE 4026 //! \details 4027 //! This state structure contains the IECP State Table Contents for TCC 4028 //! state. 4029 //! 4030 struct VEBOX_TCC_STATE_CMD 4031 { 4032 union 4033 { 4034 //!< DWORD 0 4035 struct 4036 { 4037 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 4038 uint32_t TccEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< TCC Enable 4039 uint32_t Satfactor1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SATFACTOR1 4040 uint32_t Satfactor2 : __CODEGEN_BITFIELD(16, 23) ; //!< SATFACTOR2 4041 uint32_t Satfactor3 : __CODEGEN_BITFIELD(24, 31) ; //!< SATFACTOR3 4042 }; 4043 uint32_t Value; 4044 } DW0; 4045 union 4046 { 4047 //!< DWORD 1 4048 struct 4049 { 4050 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 4051 uint32_t Satfactor4 : __CODEGEN_BITFIELD( 8, 15) ; //!< SATFACTOR4 4052 uint32_t Satfactor5 : __CODEGEN_BITFIELD(16, 23) ; //!< SATFACTOR5 4053 uint32_t Satfactor6 : __CODEGEN_BITFIELD(24, 31) ; //!< SATFACTOR6 4054 }; 4055 uint32_t Value; 4056 } DW1; 4057 union 4058 { 4059 //!< DWORD 2 4060 struct 4061 { 4062 uint32_t Basecolor1 : __CODEGEN_BITFIELD( 0, 9) ; //!< BASECOLOR1 4063 uint32_t Basecolor2 : __CODEGEN_BITFIELD(10, 19) ; //!< BASECOLOR2 4064 uint32_t Basecolor3 : __CODEGEN_BITFIELD(20, 29) ; //!< BASECOLOR3 4065 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 4066 }; 4067 uint32_t Value; 4068 } DW2; 4069 union 4070 { 4071 //!< DWORD 3 4072 struct 4073 { 4074 uint32_t Basecolo4 : __CODEGEN_BITFIELD( 0, 9) ; //!< BASECOLO4 4075 uint32_t Basecolor5 : __CODEGEN_BITFIELD(10, 19) ; //!< BASECOLOR5 4076 uint32_t Basecolor6 : __CODEGEN_BITFIELD(20, 29) ; //!< BASECOLOR6 4077 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 4078 }; 4079 uint32_t Value; 4080 } DW3; 4081 union 4082 { 4083 //!< DWORD 4 4084 struct 4085 { 4086 uint32_t Colortransitslope2 : __CODEGEN_BITFIELD( 0, 15) ; //!< COLORTRANSITSLOPE2 4087 uint32_t Colortransitslope23 : __CODEGEN_BITFIELD(16, 31) ; //!< COLORTRANSITSLOPE23 4088 }; 4089 uint32_t Value; 4090 } DW4; 4091 union 4092 { 4093 //!< DWORD 5 4094 struct 4095 { 4096 uint32_t Colortransitslope34 : __CODEGEN_BITFIELD( 0, 15) ; //!< COLORTRANSITSLOPE34 4097 uint32_t Colortransitslope45 : __CODEGEN_BITFIELD(16, 31) ; //!< COLORTRANSITSLOPE45 4098 }; 4099 uint32_t Value; 4100 } DW5; 4101 union 4102 { 4103 //!< DWORD 6 4104 struct 4105 { 4106 uint32_t Colortransitslope56 : __CODEGEN_BITFIELD( 0, 15) ; //!< COLORTRANSITSLOPE56 4107 uint32_t Colortransitslope61 : __CODEGEN_BITFIELD(16, 31) ; //!< COLORTRANSITSLOPE61 4108 }; 4109 uint32_t Value; 4110 } DW6; 4111 union 4112 { 4113 //!< DWORD 7 4114 struct 4115 { 4116 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 4117 uint32_t Colorbias1 : __CODEGEN_BITFIELD( 2, 11) ; //!< COLORBIAS1 4118 uint32_t Colorbias2 : __CODEGEN_BITFIELD(12, 21) ; //!< COLORBIAS2 4119 uint32_t Colorbias3 : __CODEGEN_BITFIELD(22, 31) ; //!< COLORBIAS3 4120 }; 4121 uint32_t Value; 4122 } DW7; 4123 union 4124 { 4125 //!< DWORD 8 4126 struct 4127 { 4128 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 4129 uint32_t Colorbias4 : __CODEGEN_BITFIELD( 2, 11) ; //!< COLORBIAS4 4130 uint32_t Colorbias5 : __CODEGEN_BITFIELD(12, 21) ; //!< COLORBIAS5 4131 uint32_t Colorbias6 : __CODEGEN_BITFIELD(22, 31) ; //!< COLORBIAS6 4132 }; 4133 uint32_t Value; 4134 } DW8; 4135 union 4136 { 4137 //!< DWORD 9 4138 struct 4139 { 4140 uint32_t SteSlopeBits : __CODEGEN_BITFIELD( 0, 2) ; //!< STE_SLOPE_BITS 4141 uint32_t Reserved291 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 4142 uint32_t SteThreshold : __CODEGEN_BITFIELD( 8, 12) ; //!< STE_THRESHOLD 4143 uint32_t Reserved301 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 4144 uint32_t UvThresholdBits : __CODEGEN_BITFIELD(16, 18) ; //!< UV_THRESHOLD_BITS 4145 uint32_t Reserved307 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 4146 uint32_t UvThreshold : __CODEGEN_BITFIELD(24, 30) ; //!< UV_THRESHOLD 4147 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 4148 }; 4149 uint32_t Value; 4150 } DW9; 4151 union 4152 { 4153 //!< DWORD 10 4154 struct 4155 { 4156 uint32_t Uvmaxcolor : __CODEGEN_BITFIELD( 0, 8) ; //!< UVMAXCOLOR 4157 uint32_t Reserved329 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 4158 uint32_t InvUvmaxcolor : __CODEGEN_BITFIELD(16, 31) ; //!< INV_UVMAXCOLOR 4159 }; 4160 uint32_t Value; 4161 } DW10; 4162 4163 //! \name Local enumerations 4164 4165 //! \brief SATFACTOR1 4166 //! \details 4167 //! The saturation factor for magenta. 4168 enum SATFACTOR1 4169 { 4170 SATFACTOR1_UNNAMED220 = 220, //!< No additional details 4171 }; 4172 4173 //! \brief SATFACTOR2 4174 //! \details 4175 //! The saturation factor for red. 4176 enum SATFACTOR2 4177 { 4178 SATFACTOR2_UNNAMED220 = 220, //!< No additional details 4179 }; 4180 4181 //! \brief SATFACTOR3 4182 //! \details 4183 //! The saturation factor for yellow. 4184 enum SATFACTOR3 4185 { 4186 SATFACTOR3_UNNAMED220 = 220, //!< No additional details 4187 }; 4188 4189 //! \brief SATFACTOR4 4190 //! \details 4191 //! The saturation factor for green. 4192 enum SATFACTOR4 4193 { 4194 SATFACTOR4_UNNAMED220 = 220, //!< No additional details 4195 }; 4196 4197 //! \brief SATFACTOR5 4198 //! \details 4199 //! The saturation factor for cyan. 4200 enum SATFACTOR5 4201 { 4202 SATFACTOR5_UNNAMED220 = 220, //!< No additional details 4203 }; 4204 4205 //! \brief SATFACTOR6 4206 //! \details 4207 //! The saturation factor for blue. 4208 enum SATFACTOR6 4209 { 4210 SATFACTOR6_UNNAMED220 = 220, //!< No additional details 4211 }; 4212 4213 //! \brief BASECOLOR1 4214 //! \details 4215 //! Base Color 1 4216 enum BASECOLOR1 4217 { 4218 BASECOLOR1_UNNAMED145 = 145, //!< No additional details 4219 }; 4220 4221 //! \brief BASECOLOR2 4222 //! \details 4223 //! Base Color 2 - this value must be greater than BaseColor1 4224 enum BASECOLOR2 4225 { 4226 BASECOLOR2_UNNAMED307 = 307, //!< No additional details 4227 }; 4228 4229 //! \brief BASECOLOR3 4230 //! \details 4231 //! Base Color 3 - this value must be greater than BaseColor2 4232 enum BASECOLOR3 4233 { 4234 BASECOLOR3_UNNAMED483 = 483, //!< No additional details 4235 }; 4236 4237 //! \brief BASECOLO4 4238 //! \details 4239 //! Base Color 4 - this value must be greater than BaseColor3 4240 enum BASECOLO4 4241 { 4242 BASECOLO4_UNNAMED657 = 657, //!< No additional details 4243 }; 4244 4245 //! \brief BASECOLOR5 4246 //! \details 4247 //! Base Color 5 - this value must be greater than BaseColor4 4248 enum BASECOLOR5 4249 { 4250 BASECOLOR5_UNNAMED819 = 819, //!< No additional details 4251 }; 4252 4253 //! \brief BASECOLOR6 4254 //! \details 4255 //! Base Color 6 - this value must be greater than BaseColor5 4256 enum BASECOLOR6 4257 { 4258 BASECOLOR6_UNNAMED995 = 995, //!< No additional details 4259 }; 4260 4261 //! \brief COLORTRANSITSLOPE2 4262 //! \details 4263 //! The calculation result of 1 / (BC2 - BC1) [1/57] 4264 enum COLORTRANSITSLOPE2 4265 { 4266 COLORTRANSITSLOPE2_UNNAMED405 = 405, //!< No additional details 4267 }; 4268 4269 //! \brief COLORTRANSITSLOPE23 4270 //! \details 4271 //! The calculation result of 1 / (BC3 - BC2) [1/62] 4272 enum COLORTRANSITSLOPE23 4273 { 4274 COLORTRANSITSLOPE23_UNNAMED744 = 744, //!< No additional details 4275 }; 4276 4277 //! \brief COLORTRANSITSLOPE34 4278 //! \details 4279 //! The calculation result of 1 / (BC4 - BC3) [1/61] 4280 enum COLORTRANSITSLOPE34 4281 { 4282 COLORTRANSITSLOPE34_UNNAMED1131 = 1131, //!< No additional details 4283 }; 4284 4285 //! \brief COLORTRANSITSLOPE45 4286 //! \details 4287 //! The calculation result of 1 / (BC5 - BC4) [1/57] 4288 enum COLORTRANSITSLOPE45 4289 { 4290 COLORTRANSITSLOPE45_UNNAMED407 = 407, //!< No additional details 4291 }; 4292 4293 //! \brief COLORTRANSITSLOPE56 4294 //! \details 4295 //! The calculation result of 1 / (BC6 - BC5) [1/62] 4296 enum COLORTRANSITSLOPE56 4297 { 4298 COLORTRANSITSLOPE56_UNNAMED372 = 372, //!< No additional details 4299 }; 4300 4301 //! \brief COLORTRANSITSLOPE61 4302 //! \details 4303 //! The calculation result of 1 / (BC1 - BC6) [1/62] 4304 enum COLORTRANSITSLOPE61 4305 { 4306 COLORTRANSITSLOPE61_UNNAMED377 = 377, //!< No additional details 4307 }; 4308 4309 //! \brief COLORBIAS1 4310 //! \details 4311 //! Color bias for BaseColor1. 4312 enum COLORBIAS1 4313 { 4314 COLORBIAS1_UNNAMED0 = 0, //!< No additional details 4315 }; 4316 4317 //! \brief COLORBIAS2 4318 //! \details 4319 //! Color bias for BaseColor2. 4320 enum COLORBIAS2 4321 { 4322 COLORBIAS2_UNNAMED150 = 150, //!< No additional details 4323 }; 4324 4325 //! \brief COLORBIAS3 4326 //! \details 4327 //! Color bias for BaseColor3. 4328 enum COLORBIAS3 4329 { 4330 COLORBIAS3_UNNAMED0 = 0, //!< No additional details 4331 }; 4332 4333 //! \brief COLORBIAS4 4334 //! \details 4335 //! Color bias for BaseColor4. 4336 enum COLORBIAS4 4337 { 4338 COLORBIAS4_UNNAMED0 = 0, //!< No additional details 4339 }; 4340 4341 //! \brief COLORBIAS5 4342 //! \details 4343 //! Color bias for BaseColor5. 4344 enum COLORBIAS5 4345 { 4346 COLORBIAS5_UNNAMED0 = 0, //!< No additional details 4347 }; 4348 4349 //! \brief COLORBIAS6 4350 //! \details 4351 //! Color bias for BaseColor6. 4352 enum COLORBIAS6 4353 { 4354 COLORBIAS6_UNNAMED0 = 0, //!< No additional details 4355 }; 4356 4357 //! \brief STE_SLOPE_BITS 4358 //! \details 4359 //! Skin tone pixels enhancement slope bits. 4360 enum STE_SLOPE_BITS 4361 { 4362 STE_SLOPE_BITS_UNNAMED0 = 0, //!< No additional details 4363 }; 4364 4365 //! \brief STE_THRESHOLD 4366 //! \details 4367 //! Skin tone pixels enhancement threshold. 4368 enum STE_THRESHOLD 4369 { 4370 STE_THRESHOLD_UNNAMED0 = 0, //!< No additional details 4371 }; 4372 4373 //! \brief UV_THRESHOLD_BITS 4374 //! \details 4375 //! Low UV transition width bits. 4376 enum UV_THRESHOLD_BITS 4377 { 4378 UV_THRESHOLD_BITS_UNNAMED3 = 3, //!< No additional details 4379 }; 4380 4381 //! \brief UV_THRESHOLD 4382 //! \details 4383 //! Low UV threshold. 4384 enum UV_THRESHOLD 4385 { 4386 UV_THRESHOLD_UNNAMED3 = 3, //!< No additional details 4387 }; 4388 4389 //! \brief UVMAXCOLOR 4390 //! \details 4391 //! The maximum absolute value of the legal UV pixels. Used for the SFs2 4392 //! calculation. 4393 enum UVMAXCOLOR 4394 { 4395 UVMAXCOLOR_UNNAMED448 = 448, //!< No additional details 4396 }; 4397 4398 //! \brief INV_UVMAXCOLOR 4399 //! \details 4400 //! 1 / UVMaxColor. Used for the SFs2 calculation. 4401 enum INV_UVMAXCOLOR 4402 { 4403 INV_UVMAXCOLOR_UNNAMED146 = 146, //!< No additional details 4404 }; 4405 4406 //! \name Initializations 4407 4408 //! \brief Explicit member initialization function 4409 VEBOX_TCC_STATE_CMD(); 4410 4411 static const size_t dwSize = 11; 4412 static const size_t byteSize = 44; 4413 }; 4414 4415 //! 4416 //! \brief VEBOX_PROCAMP_STATE 4417 //! \details 4418 //! This state structure contains the IECP State Table Contents for ProcAmp 4419 //! state. 4420 //! 4421 struct VEBOX_PROCAMP_STATE_CMD 4422 { 4423 union 4424 { 4425 //!< DWORD 0 4426 struct 4427 { 4428 uint32_t ProcampEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< PROCAMP_ENABLE 4429 uint32_t Brightness : __CODEGEN_BITFIELD( 1, 12) ; //!< BRIGHTNESS 4430 uint32_t Reserved13 : __CODEGEN_BITFIELD(13, 16) ; //!< Reserved 4431 uint32_t Contrast : __CODEGEN_BITFIELD(17, 27) ; //!< CONTRAST 4432 uint32_t Reserved28 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 4433 }; 4434 uint32_t Value; 4435 } DW0; 4436 union 4437 { 4438 //!< DWORD 1 4439 struct 4440 { 4441 uint32_t SinCS : __CODEGEN_BITFIELD( 0, 15) ; //!< SIN_C_S 4442 uint32_t CosCS : __CODEGEN_BITFIELD(16, 31) ; //!< COS_C_S 4443 }; 4444 uint32_t Value; 4445 } DW1; 4446 4447 //! \name Local enumerations 4448 4449 enum PROCAMP_ENABLE 4450 { 4451 PROCAMP_ENABLE_UNNAMED1 = 1, //!< No additional details 4452 }; 4453 4454 //! \brief BRIGHTNESS 4455 //! \details 4456 //! Brightness magnitude. 4457 enum BRIGHTNESS 4458 { 4459 BRIGHTNESS_OR00 = 0, //!< No additional details 4460 }; 4461 4462 //! \brief CONTRAST 4463 //! \details 4464 //! Contrast magnitude. 4465 enum CONTRAST 4466 { 4467 CONTRAST_10INFIXEDPOINTU47 = 128, //!< No additional details 4468 }; 4469 4470 //! \brief SIN_C_S 4471 //! \details 4472 //! UV multiplication sine factor. 4473 enum SIN_C_S 4474 { 4475 SIN_C_S_UNNAMED0 = 0, //!< No additional details 4476 }; 4477 4478 //! \brief COS_C_S 4479 //! \details 4480 //! UV multiplication cosine factor. 4481 enum COS_C_S 4482 { 4483 COS_C_S_UNNAMED256 = 256, //!< No additional details 4484 }; 4485 4486 //! \name Initializations 4487 4488 //! \brief Explicit member initialization function 4489 VEBOX_PROCAMP_STATE_CMD(); 4490 4491 static const size_t dwSize = 2; 4492 static const size_t byteSize = 8; 4493 }; 4494 4495 //! 4496 //! \brief VEBOX_IECP_STATE 4497 //! \details 4498 //! 4499 //! 4500 struct VEBOX_IECP_STATE_CMD 4501 { 4502 VEBOX_STD_STE_STATE_CMD StdSteState ; ///< VEBOX_STD_STE_STATE 4503 VEBOX_ACE_LACE_STATE_CMD AceState ; ///< VEBOX_ACE_LACE_STATE 4504 VEBOX_TCC_STATE_CMD TccState ; ///< VEBOX_TCC_STATE 4505 VEBOX_PROCAMP_STATE_CMD ProcampState ; ///< VEBOX_PROCAMP_STATE 4506 VEBOX_CSC_STATE_CMD CscState ; ///< VEBOX_CSC_STATE 4507 VEBOX_ALPHA_AOI_STATE_CMD AlphaAoiState ; ///< VEBOX_ALPHA_AOI_STATE 4508 VEBOX_CCM_STATE_CMD CcmState ; ///< VEBOX_CCM_STATE 4509 VEBOX_FRONT_END_CSC_STATE_CMD FrontEndCsc ; ///< VEBOX_FRONT_END_CSC_STATE 4510 4511 //! \name Local enumerations 4512 4513 //! \name Initializations 4514 4515 //! \brief Explicit member initialization function 4516 VEBOX_IECP_STATE_CMD(); 4517 4518 static const size_t DW_SIZE = 91; 4519 static const size_t BYTE_SIZE = 364; 4520 }; 4521 4522 //! 4523 //! \brief VEBOX_STATE 4524 //! \details 4525 //! This command controls the internal functions of the VEBOX. This command 4526 //! has a set of indirect state buffers: DN/DI state 4527 //! IECP general state 4528 //! IECP Gamut Expansion/Compression state 4529 //! IECP Gamut Vertex Table state 4530 //! Capture Pipe state 4531 //! 4532 //! 4533 //! [DevSKL+]: Adds the LACE LUT Table as an indirect state buffer. 4534 //! 4535 struct VEBOX_STATE_CMD 4536 { 4537 union 4538 { 4539 //!< DWORD 0 4540 struct 4541 { 4542 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4543 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4544 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 4545 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 4546 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 4547 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4548 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4549 }; 4550 uint32_t Value; 4551 } DW0; 4552 union 4553 { 4554 //!< DWORD 1 4555 struct 4556 { 4557 uint32_t ColorGamutExpansionEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Color Gamut Expansion Enable 4558 uint32_t ColorGamutCompressionEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Color Gamut Compression Enable 4559 uint32_t GlobalIecpEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Global IECP Enable 4560 uint32_t DnEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< DN_ENABLE 4561 uint32_t DiEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< DI_ENABLE 4562 uint32_t DnDiFirstFrame : __CODEGEN_BITFIELD( 5, 5) ; //!< DNDI_FIRST_FRAME 4563 uint32_t DownsampleMethod422to420 : __CODEGEN_BITFIELD( 6, 6) ; //!< _422__420_DOWNSAMPLE_METHOD 4564 uint32_t DownsampleMethod444to422 : __CODEGEN_BITFIELD( 7, 7) ; //!< _444__422_DOWNSAMPLE_METHOD 4565 uint32_t DiOutputFrames : __CODEGEN_BITFIELD( 8, 9) ; //!< DI_OUTPUT_FRAMES 4566 uint32_t DemosaicEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Demosaic Enable 4567 uint32_t VignetteEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Vignette Enable 4568 uint32_t AlphaPlaneEnable : __CODEGEN_BITFIELD(12, 12) ; //!< Alpha Plane Enable 4569 uint32_t HotPixelFilteringEnable : __CODEGEN_BITFIELD(13, 13) ; //!< Hot Pixel Filtering Enable 4570 uint32_t SingleSliceVeboxEnable : __CODEGEN_BITFIELD(14, 15) ; //!< SINGLE_SLICE_VEBOX_ENABLE 4571 uint32_t LaceCorrectionEnable : __CODEGEN_BITFIELD(16, 16) ; //!< LACE Correction Enable 4572 uint32_t DisableEncoderStatistics : __CODEGEN_BITFIELD(17, 17) ; //!< Disable Encoder Statistics 4573 uint32_t DisableTemporalDenoiseFilter : __CODEGEN_BITFIELD(18, 18) ; //!< Disable Temporal Denoise Filter 4574 uint32_t SinglePipeEnable : __CODEGEN_BITFIELD(19, 19) ; //!< SINGLE_PIPE_ENABLE 4575 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 20) ; //!< Reserved 4576 uint32_t ForwardGammaCorrectionEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Forward Gamma Correction Enable 4577 uint32_t Reserved54 : __CODEGEN_BITFIELD(22, 24) ; //!< Reserved 4578 uint32_t StateSurfaceControlBits : __CODEGEN_BITFIELD(25, 31) ; //!< State Surface Control Bits 4579 }; 4580 uint32_t Value; 4581 } DW1; 4582 union 4583 { 4584 //!< DWORD 2 4585 struct 4586 { 4587 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 4588 uint32_t DnDiStatePointerLow : __CODEGEN_BITFIELD(12, 31) ; //!< DN/DI State Pointer Low 4589 }; 4590 uint32_t Value; 4591 } DW2; 4592 union 4593 { 4594 //!< DWORD 3 4595 struct 4596 { 4597 uint32_t DnDiStatePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< DN/DI State Pointer High 4598 uint32_t Reserved112 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4599 }; 4600 uint32_t Value; 4601 } DW3; 4602 union 4603 { 4604 //!< DWORD 4 4605 struct 4606 { 4607 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 4608 uint32_t IecpStatePointerLow : __CODEGEN_BITFIELD(12, 31) ; //!< IECP State Pointer Low 4609 }; 4610 uint32_t Value; 4611 } DW4; 4612 union 4613 { 4614 //!< DWORD 5 4615 struct 4616 { 4617 uint32_t IecpStatePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< IECP State Pointer High 4618 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4619 }; 4620 uint32_t Value; 4621 } DW5; 4622 union 4623 { 4624 //!< DWORD 6 4625 struct 4626 { 4627 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 4628 uint32_t GamutStatePointerLow : __CODEGEN_BITFIELD(12, 31) ; //!< Gamut State Pointer Low 4629 }; 4630 uint32_t Value; 4631 } DW6; 4632 union 4633 { 4634 //!< DWORD 7 4635 struct 4636 { 4637 uint32_t GamutStatePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Gamut State Pointer High 4638 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4639 }; 4640 uint32_t Value; 4641 } DW7; 4642 union 4643 { 4644 //!< DWORD 8 4645 struct 4646 { 4647 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 4648 uint32_t VertexTableStatePointerLow : __CODEGEN_BITFIELD(12, 31) ; //!< Vertex Table State Pointer Low 4649 }; 4650 uint32_t Value; 4651 } DW8; 4652 union 4653 { 4654 //!< DWORD 9 4655 struct 4656 { 4657 uint32_t VertexTableStatePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertex Table State Pointer High 4658 uint32_t Reserved304 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4659 }; 4660 uint32_t Value; 4661 } DW9; 4662 union 4663 { 4664 //!< DWORD 10 4665 struct 4666 { 4667 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 4668 uint32_t CapturePipeStatePointerLow : __CODEGEN_BITFIELD(12, 31) ; //!< Capture Pipe State Pointer Low 4669 }; 4670 uint32_t Value; 4671 } DW10; 4672 union 4673 { 4674 //!< DWORD 11 4675 struct 4676 { 4677 uint32_t CapturePipeStatePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Capture Pipe State Pointer High 4678 uint32_t Reserved368 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4679 }; 4680 uint32_t Value; 4681 } DW11; 4682 union 4683 { 4684 //!< DWORD 12 4685 struct 4686 { 4687 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 4688 uint32_t LaceLutTableStatePointerLow : __CODEGEN_BITFIELD(12, 31) ; //!< LACE LUT Table State Pointer Low 4689 }; 4690 uint32_t Value; 4691 } DW12; 4692 union 4693 { 4694 //!< DWORD 13 4695 struct 4696 { 4697 uint32_t LaceLutTableStatePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< LACE LUT Table State Pointer High 4698 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 4699 uint32_t ArbitrationPriorityControlForLaceLut : __CODEGEN_BITFIELD(30, 31) ; //!< ARBITRATION_PRIORITY_CONTROL__FOR_LACE_LUT 4700 }; 4701 uint32_t Value; 4702 } DW13; 4703 union 4704 { 4705 //!< DWORD 14..15 4706 struct 4707 { 4708 uint64_t Reserved448 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 4709 uint64_t GammaCorrectionValuesAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Gamma Correction Values Address 4710 }; 4711 uint32_t Value[2]; 4712 } DW14_15; 4713 4714 //! \name Local enumerations 4715 4716 enum SUBOPCODE_B 4717 { 4718 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 4719 }; 4720 4721 enum SUBOPCODE_A 4722 { 4723 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 4724 }; 4725 4726 enum COMMAND_OPCODE 4727 { 4728 COMMAND_OPCODE_VEBOX = 4, //!< No additional details 4729 }; 4730 4731 enum PIPELINE 4732 { 4733 PIPELINE_MEDIA = 2, //!< No additional details 4734 }; 4735 4736 enum COMMAND_TYPE 4737 { 4738 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4739 }; 4740 4741 //! \brief DN_ENABLE 4742 //! \details 4743 //! Denoise is bypassed if this is low - BNE is still calculated and output, 4744 //! but the denoised fields are not. VDI does not read in the denoised 4745 //! previous frame but uses the pointer for the original previous frame. 4746 enum DN_ENABLE 4747 { 4748 DN_ENABLE_DONOTDENOISEFRAME = 0, //!< No additional details 4749 DN_ENABLE_DENOISEFRAME = 1, //!< No additional details 4750 }; 4751 4752 //! \brief DI_ENABLE 4753 //! \details 4754 //! Deinterlacer is bypassed if this is disabled: the output is the same as 4755 //! the input (same as a 2:2 cadence). 4756 //! FMD and STMM are not calculated and the values in the response 4757 //! message are 0. 4758 enum DI_ENABLE 4759 { 4760 DI_ENABLE_DONOTCALCULATEDI = 0, //!< No additional details 4761 DI_ENABLE_CALCULATEDI = 1, //!< No additional details 4762 }; 4763 4764 //! \brief DNDI_FIRST_FRAME 4765 //! \details 4766 //! Indicates that this is the first frame of the stream, so previous clean 4767 //! is not available. 4768 enum DNDI_FIRST_FRAME 4769 { 4770 DNDI_FIRST_FRAME_NOTFIRSTFIELD_PREVIOUSCLEANSURFACESTATEISVALID = 0, //!< No additional details 4771 DNDI_FIRST_FRAME_FIRSTFIELD_PREVIOUSCLEANSURFACESTATEISINVALID = 1, //!< No additional details 4772 }; 4773 4774 //! \brief _422__420_DOWNSAMPLE_METHOD 4775 //! \details 4776 //! To enable averaging in case of 420 (NV12/P016) output formats, 4777 //! 444->422 and 422->420 should be set. 4778 enum _422__420_DOWNSAMPLE_METHOD 4779 { 4780 _422_420_DOWNSAMPLE_METHOD_DROPLOWERCHROMAOFTHEPAIR = 0, //!< No additional details 4781 _422_420_DOWNSAMPLE_METHOD_AVERAGEVERTICALLYALIGNEDCHROMAS = 1, //!< No additional details 4782 }; 4783 4784 //! \brief _444__422_DOWNSAMPLE_METHOD 4785 //! \details 4786 //! <table border="1"> 4787 //! <tr> 4788 //! <td>444->422</td> 4789 //! <td>422->420</td> 4790 //! <td>Description</td> 4791 //! </tr> 4792 //! <tr> 4793 //! <td>0</td> 4794 //! <td>0</td> 4795 //! <td>No averaging, only down sampling</td> 4796 //! </tr> 4797 //! <tr> 4798 //! <td>0</td> 4799 //! <td>1</td> 4800 //! <td>Not Supported</td> 4801 //! </tr> 4802 //! <tr> 4803 //! <td>1</td> 4804 //! <td>0</td> 4805 //! <td>Only Horizontal averaging</td> 4806 //! </tr> 4807 //! <tr> 4808 //! <td>1</td> 4809 //! <td>1</td> 4810 //! <td>Horizontal and Vertical averaging</td> 4811 //! </tr> 4812 //! </table> 4813 enum _444__422_DOWNSAMPLE_METHOD 4814 { 4815 _444_422_DOWNSAMPLE_METHOD_DROPRIGHTCHROMAOFTHEPAIR = 0, //!< No additional details 4816 _444_422_DOWNSAMPLE_METHOD_AVERAGEHORIZONTALLYALIGNEDCHROMAS = 1, //!< No additional details 4817 }; 4818 4819 //! \brief DI_OUTPUT_FRAMES 4820 //! \details 4821 //! Indicates which frames to output in DI mode. 4822 enum DI_OUTPUT_FRAMES 4823 { 4824 DI_OUTPUT_FRAMES_OUTPUTBOTHFRAMES = 0, //!< No additional details 4825 DI_OUTPUT_FRAMES_OUTPUTPREVIOUSFRAMEONLY = 1, //!< No additional details 4826 DI_OUTPUT_FRAMES_OUTPUTCURRENTFRAMEONLY = 2, //!< No additional details 4827 }; 4828 4829 //! \brief SINGLE_SLICE_VEBOX_ENABLE 4830 //! \details 4831 //! For products that have 2 entire VEBOXes that automatically split the 4832 //! frame, this enable emulates a 1 VEBOX product, running at 1/2 speed and 4833 //! only outputting a single set of per command statistics. 4834 enum SINGLE_SLICE_VEBOX_ENABLE 4835 { 4836 SINGLE_SLICE_VEBOX_ENABLE_BOTHSLICESENABLED = 0, //!< No additional details 4837 SINGLE_SLICE_VEBOX_ENABLE_SLICE0ENABLED = 1, //!< No additional details 4838 SINGLE_SLICE_VEBOX_ENABLE_SLICE1ENABLES = 2, //!< No additional details 4839 }; 4840 4841 //! \brief SINGLE_PIPE_ENABLE 4842 //! \details 4843 //! Indicates that the Capture Pipe features that only exist in a single 4844 //! pipe can be enabled. 4845 enum SINGLE_PIPE_ENABLE 4846 { 4847 SINGLE_PIPE_ENABLE_DEFAULT = 0, //!< No additional details 4848 SINGLE_PIPE_ENABLE_ENABLE = 1, //!< No additional details 4849 }; 4850 4851 //! \brief ARBITRATION_PRIORITY_CONTROL__FOR_LACE_LUT 4852 //! \details 4853 //! This field controls the priority of arbitration used in the GAC/GAM 4854 //! pipeline for this surface. 4855 enum ARBITRATION_PRIORITY_CONTROL__FOR_LACE_LUT 4856 { 4857 ARBITRATION_PRIORITY_CONTROL_FOR_LACE_LUT_HIGHESTPRIORITY = 0, //!< No additional details 4858 ARBITRATION_PRIORITY_CONTROL_FOR_LACE_LUT_SECONDHIGHESTPRIORITY = 1, //!< No additional details 4859 ARBITRATION_PRIORITY_CONTROL_FOR_LACE_LUT_THIRDHIGHESTPRIORITY = 2, //!< No additional details 4860 ARBITRATION_PRIORITY_CONTROL_FOR_LACE_LUT_LOWESTPRIORITY = 3, //!< No additional details 4861 }; 4862 4863 //! \name Initializations 4864 4865 //! \brief Explicit member initialization function 4866 VEBOX_STATE_CMD(); 4867 4868 static const size_t dwSize = 16; 4869 static const size_t byteSize = 64; 4870 }; 4871 4872 //! 4873 //! \brief VEBOX_SURFACE_STATE 4874 //! \details 4875 //! The input and output data containers accessed are called "surfaces". 4876 //! Surface state is sent to VEBOX via an inline state command rather than 4877 //! using binding tables. SURFACE_STATE contains the parameters defining 4878 //! each surface to be accessed, including its size, format, and offsets to 4879 //! its subsurfaces. The surface's base address is in the execution command. 4880 //! Despite having multiple input and output surfaces, we limit the number 4881 //! of surface states to one for input surfaces and one for output surfaces. 4882 //! The other surfaces are derived from the input/output surface states. 4883 //! 4884 //! The Current Frame Input surface uses the Input SURFACE_STATE 4885 //! 4886 //! The Previous Denoised Input surface uses the Input SURFACE_STATE. (For 4887 //! 16-bit Bayer pattern inputs this will be 16-bit.) 4888 //! 4889 //! The Current Denoised Output surface uses the Input SURFACE_STATE. (For 4890 //! 16-bit Bayer pattern inputs this will be 16-bit.) 4891 //! 4892 //! The STMM/Noise History Input surface uses the Input SURFACE_STATE with 4893 //! Tile-Y and Width/Height a multiple of 4. 4894 //! 4895 //! The STMM/Noise History Output surface uses the Input SURFACE_STATE with 4896 //! Tile-Y and Width/Height a multiple of 4. 4897 //! 4898 //! The Current Deinterlaced/IECP Frame Output surface uses the Output 4899 //! SURFACE_STATE. 4900 //! 4901 //! The Previous Deinterlaced/IECP Frame Output surface uses the Output 4902 //! SURFACE_STATE. 4903 //! 4904 //! The FMD per block output / per Frame Output surface uses the Linear 4905 //! SURFACE_STATE (see note below). 4906 //! 4907 //! The Alpha surface uses the Linear A8 SURFACE_STATE with Width/Height 4908 //! equal to Input Surface. Pitch is width rounded to next 64. 4909 //! 4910 //! The Skin Score surface uses the Output SURFACE_STATE. 4911 //! 4912 //! The STMM height is the same as the Input Surface height except when the 4913 //! input Surface Format is Bayer Pattern and the Bayer Pattern Offset is 10 4914 //! or 11, in which case the height is the input height + 4. For Bayer 4915 //! pattern inputs when the Bayer Pattern Offset is 10 or 11, the Current 4916 //! Denoised Output/Previous Denoised Input will also have a height which is 4917 //! the input height + 4. For Bayer pattern inputs only the Current Denoised 4918 //! Output/Previous Denoised Input are in Tile-Y. 4919 //! 4920 //! The linear surface for FMD statistics is linear (not tiled). The height 4921 //! of the per block statistics is (Input Height +3)/4 - the Input Surface 4922 //! height in pixels is rounded up to the next even 4 and divided by 4. The 4923 //! width of the per block section in bytes is equal to the width of the 4924 //! Input Surface in pixels rounded up to the next 16 bytes. The pitch of 4925 //! the per block section in bytes is equal to the width of the Input 4926 //! Surface in pixels rounded up to the next 64 bytes. 4927 //! 4928 //! The STMM surfaces must be identical to the Input surface except for the 4929 //! tiling mode must be Tile-Y and the pitch is specified in DW7. The pitch 4930 //! for the Current Denoised Output/Previous Denoised Input is specified in 4931 //! DW7. The width and height must be a multiple of 4 rounded up from the 4932 //! input height. 4933 //! 4934 //! The Vignette Correction surface uses the Linear 16-bit SURFACE_STATE 4935 //! with : 4936 //! Width=(Ceil(Image Width / 4) +1) * 4 4937 //! Height= Ceil(Image Height / 4) +1 4938 //! Pitch in bytes is (vignette width *2) rounded to the next 64 4939 //! 4940 //! VEBOX may write to memory between the surface width and the surface 4941 //! pitch for output surfaces. 4942 //! 4943 //! VEBOX can support a frame level X/Y offset which allows processing of 2 4944 //! side-by-side frames for certain 3D video formats. 4945 //! 4946 //! The X/Y Offset for Frame state applies only to the Current Frame Input 4947 //! and the Current Deinterlaced/IECP Frame Output and Previous 4948 //! Deinterlaced/IECP Frame Output. The statistics surfaces, the denoise 4949 //! feedback surfaces and the alpha/vignette surfaces have no X/Y offsets. 4950 //! 4951 //! For 8bit Alpha input, when converted to 16bit output, the 8 bit alpha 4952 //! value is replicated to both the upper and lower 8 bits to form the 16 4953 //! bit alpha value. 4954 //! 4955 //! Skin Score Output Surface uses the same tiling format as the Output 4956 //! surface. 4957 //! 4958 struct VEBOX_SURFACE_STATE_CMD 4959 { 4960 union 4961 { 4962 //!< DWORD 0 4963 struct 4964 { 4965 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4966 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4967 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 4968 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 4969 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 4970 uint32_t MediaCommandPipeline : __CODEGEN_BITFIELD(27, 28) ; //!< MEDIA_COMMAND_PIPELINE 4971 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4972 }; 4973 uint32_t Value; 4974 } DW0; 4975 union 4976 { 4977 //!< DWORD 1 4978 struct 4979 { 4980 uint32_t SurfaceIdentification : __CODEGEN_BITFIELD( 0, 0) ; //!< SURFACE_IDENTIFICATION 4981 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 4982 }; 4983 uint32_t Value; 4984 } DW1; 4985 union 4986 { 4987 //!< DWORD 2 4988 struct 4989 { 4990 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 4991 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 4992 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 4993 }; 4994 uint32_t Value; 4995 } DW2; 4996 union 4997 { 4998 //!< DWORD 3 4999 struct 5000 { 5001 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 5002 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 5003 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 5004 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 5005 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 23) ; //!< Reserved 5006 uint32_t BayerPatternFormat : __CODEGEN_BITFIELD(24, 24) ; //!< BAYER_PATTERN_FORMAT 5007 uint32_t BayerPatternOffset : __CODEGEN_BITFIELD(25, 26) ; //!< BAYER_PATTERN_OFFSET 5008 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(27, 27) ; //!< Interleave Chroma 5009 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_FORMAT 5010 }; 5011 uint32_t Value; 5012 } DW3; 5013 union 5014 { 5015 //!< DWORD 4 5016 struct 5017 { 5018 uint32_t YOffsetForU : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U 5019 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 5020 uint32_t XOffsetForU : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for U 5021 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5022 }; 5023 uint32_t Value; 5024 } DW4; 5025 union 5026 { 5027 //!< DWORD 5 5028 struct 5029 { 5030 uint32_t YOffsetForV : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for V 5031 uint32_t Reserved175 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 5032 uint32_t XOffsetForV : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V 5033 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5034 }; 5035 uint32_t Value; 5036 } DW5; 5037 union 5038 { 5039 //!< DWORD 6 5040 struct 5041 { 5042 uint32_t YOffsetForFrame : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for Frame 5043 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 5044 uint32_t XOffsetForFrame : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for Frame 5045 uint32_t Reserved223 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 5046 }; 5047 uint32_t Value; 5048 } DW6; 5049 union 5050 { 5051 //!< DWORD 7 5052 struct 5053 { 5054 uint32_t DerivedSurfacePitch : __CODEGEN_BITFIELD( 0, 16) ; //!< Derived Surface Pitch 5055 uint32_t Reserved241 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 5056 }; 5057 uint32_t Value; 5058 } DW7; 5059 union 5060 { 5061 //!< DWORD 8 5062 struct 5063 { 5064 uint32_t SurfacePitchForSkinScoreOutputSurfaces : __CODEGEN_BITFIELD( 0, 16) ; //!< Surface Pitch for Skin Score Output Surfaces 5065 uint32_t Reserved273 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 5066 }; 5067 uint32_t Value; 5068 } DW8; 5069 5070 //! \name Local enumerations 5071 5072 enum SUBOPCODE_B 5073 { 5074 SUBOPCODE_B_VEBOX = 0, //!< No additional details 5075 }; 5076 5077 enum SUBOPCODE_A 5078 { 5079 SUBOPCODE_A_VEBOX = 0, //!< No additional details 5080 }; 5081 5082 enum MEDIA_COMMAND_OPCODE 5083 { 5084 MEDIA_COMMAND_OPCODE_VEBOX = 4, //!< No additional details 5085 }; 5086 5087 enum MEDIA_COMMAND_PIPELINE 5088 { 5089 MEDIA_COMMAND_PIPELINE_MEDIA = 2, //!< No additional details 5090 }; 5091 5092 enum COMMAND_TYPE 5093 { 5094 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5095 }; 5096 5097 //! \brief SURFACE_IDENTIFICATION 5098 //! \details 5099 //! Specifies which set of surfaces this command refers to: 5100 enum SURFACE_IDENTIFICATION 5101 { 5102 SURFACE_IDENTIFICATION_INPUTSURFACEANDDENOISEDCURRENTOUTPUTSURFACE = 0, //!< No additional details 5103 SURFACE_IDENTIFICATION_OUTPUTSURFACE_ALLEXCEPTTHEDENOISEDCURRENTOUTPUTSURFACE = 1, //!< No additional details 5104 }; 5105 5106 //! \brief TILE_WALK 5107 //! \details 5108 //! This field specifies the type of memory tiling (XMajor or YMajor) 5109 //! employed to tile this surface. See <em>Memory Interface Functions</em> 5110 //! for details on memory tiling and restrictions. 5111 //! This field is ignored when the surface is linear. 5112 enum TILE_WALK 5113 { 5114 TILE_WALK_TILEWALKXMAJOR = 0, //!< No additional details 5115 TILE_WALK_TILEWALKYMAJOR = 1, //!< No additional details 5116 }; 5117 5118 //! \brief TILED_SURFACE 5119 //! \details 5120 //! This field specifies whether the surface is tiled. 5121 enum TILED_SURFACE 5122 { 5123 TILED_SURFACE_FALSE = 0, //!< Linear 5124 TILED_SURFACE_TRUE = 1, //!< Tiled 5125 }; 5126 5127 //! \brief BAYER_PATTERN_FORMAT 5128 //! \details 5129 //! Specifies the format of the Bayer Pattern: 5130 enum BAYER_PATTERN_FORMAT 5131 { 5132 BAYER_PATTERN_FORMAT_8_BITINPUTATA8_BITSTRIDE = 0, //!< No additional details 5133 BAYER_PATTERN_FORMAT_16_BITINPUTATA16_BITSTRIDE = 1, //!< No additional details 5134 }; 5135 5136 //! \brief BAYER_PATTERN_OFFSET 5137 //! \details 5138 //! Specifies the starting pixel offset for the Bayer pattern used for 5139 //! Capture Pipe. 5140 enum BAYER_PATTERN_OFFSET 5141 { 5142 BAYER_PATTERN_OFFSET_PIXELATX0_Y0ISBLUE = 0, //!< No additional details 5143 BAYER_PATTERN_OFFSET_PIXELATX0_Y0ISRED = 1, //!< No additional details 5144 BAYER_PATTERN_OFFSET_PIXELATX0_Y0ISGREEN_PIXELATX1_Y0ISRED = 2, //!< No additional details 5145 BAYER_PATTERN_OFFSET_PIXELATX0_Y0ISGREEN_PIXELATX1_Y0ISBLUE = 3, //!< No additional details 5146 }; 5147 5148 //! \brief SURFACE_FORMAT 5149 //! \details 5150 //! Specifies the format of the surface. All of the Y and G channels will 5151 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1. 5152 enum SURFACE_FORMAT 5153 { 5154 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 5155 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 5156 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 5157 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 5158 SURFACE_FORMAT_PLANAR4208 = 4, //!< NV12 with Interleave Chroma set 5159 SURFACE_FORMAT_PACKED444A8 = 5, //!< IECP input/output only 5160 SURFACE_FORMAT_PACKED42216 = 6, //!< IECP input/output only 5161 SURFACE_FORMAT_R10G10B10A2UNORMR10G10B10A2UNORMSRGB = 7, //!< IECP output only 5162 SURFACE_FORMAT_R8G8B8A8UNORMR8G8B8A8UNORMSRGB = 8, //!< Hot Pixel/Denoise and/or IECP input/output 5163 SURFACE_FORMAT_PACKED44416 = 9, //!< IECP input/output only 5164 SURFACE_FORMAT_PLANAR42216 = 10, //!< IECP input/output only 5165 SURFACE_FORMAT_Y8UNORM = 11, //!< No additional details 5166 SURFACE_FORMAT_PLANAR42016 = 12, //!< IECP input/output only 5167 SURFACE_FORMAT_R16G16B16A16 = 13, //!< Hot Pixel/Denoise and/or IECP input/output 5168 SURFACE_FORMAT_BAYERPATTERN = 14, //!< Demosaic input only 5169 SURFACE_FORMAT_Y16UNORM = 15, //!< Denoise/IECP input/output 5170 }; 5171 5172 //! \name Initializations 5173 5174 //! \brief Explicit member initialization function 5175 VEBOX_SURFACE_STATE_CMD(); 5176 5177 static const size_t dwSize = 9; 5178 static const size_t byteSize = 36; 5179 }; 5180 5181 //! 5182 //! \brief VEBOX_TILING_CONVERT 5183 //! \details 5184 //! This command takes the input surface and writes directly to the output 5185 //! surface at high speed. The surface format and width/height of the input 5186 //! and output must be the same, only the tiling mode and pitch can change. 5187 //! 5188 struct VEBOX_TILING_CONVERT_CMD 5189 { 5190 union 5191 { 5192 //!< DWORD 0 5193 struct 5194 { 5195 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5196 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5197 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5198 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5199 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 5200 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5201 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5202 }; 5203 uint32_t Value; 5204 } DW0; 5205 union 5206 { 5207 //!< DWORD 1..2 5208 struct 5209 { 5210 uint64_t InputSurfaceControlBits : __CODEGEN_BITFIELD( 0, 10) ; //!< Input Surface Control Bits 5211 uint64_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 5212 uint64_t InputAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Input Address 5213 }; 5214 uint32_t Value[2]; 5215 } DW1_2; 5216 union 5217 { 5218 //!< DWORD 3..4 5219 struct 5220 { 5221 uint64_t OutputSurfaceControlBits : __CODEGEN_BITFIELD( 0, 10) ; //!< Output Surface Control Bits 5222 uint64_t Reserved107 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 5223 uint64_t OutputAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Output Address 5224 }; 5225 uint32_t Value[2]; 5226 } DW3_4; 5227 5228 //! \name Local enumerations 5229 5230 enum SUBOPCODE_B 5231 { 5232 SUBOPCODE_B_UNNAMED1 = 1, ///< 5233 }; 5234 enum SUBOPCODE_A 5235 { 5236 SUBOPCODE_A_UNNAMED0 = 0, ///< 5237 }; 5238 enum COMMAND_OPCODE 5239 { 5240 COMMAND_OPCODE_VEBOX = 4, ///< 5241 }; 5242 enum PIPELINE 5243 { 5244 PIPELINE_MEDIA = 2, ///< 5245 }; 5246 enum COMMAND_TYPE 5247 { 5248 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, ///< 5249 }; 5250 5251 //! \name Initializations 5252 5253 //! \brief Explicit member initialization function 5254 VEBOX_TILING_CONVERT_CMD(); 5255 5256 static const size_t dwSize = 5; 5257 static const size_t byteSize = 20; 5258 }; 5259 5260 //! 5261 //! \brief VEB_DI_IECP 5262 //! \details 5263 //! The VEB_DI_IECP command causes the VEBOX to start processing the frames 5264 //! specified by VEB_SURFACE_STATE using the parameters specified by 5265 //! VEB_DI_STATE and VEB_IECP_STATE. The processing can start and end at 5266 //! any 64 pixel column in the frame. If Starting X and Ending X are used to 5267 //! split the frame into sections, it should not be split into more than 4 5268 //! sections. 5269 //! Each VEB_DI_IECP command should be preceded by a VEB_STATE command and 5270 //! the input/output VEB_SURFACE_STATE commands. 5271 //! 5272 //! When DI is enabled, only the Current Frame skin scores are outputted to 5273 //! the Skin Score Output surface. 5274 //! 5275 struct VEB_DI_IECP_CMD 5276 { 5277 union 5278 { 5279 //!< DWORD 0 5280 struct 5281 { 5282 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5283 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5284 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 5285 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPA 5286 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26) ; //!< OPCODE 5287 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5288 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5289 }; 5290 uint32_t Value; 5291 } DW0; 5292 union 5293 { 5294 //!< DWORD 1 5295 struct 5296 { 5297 uint32_t EndingX : __CODEGEN_BITFIELD( 0, 13) ; //!< Ending X 5298 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5299 uint32_t StartingX : __CODEGEN_BITFIELD(16, 29) ; //!< Starting X 5300 uint32_t Reserved62 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5301 }; 5302 uint32_t Value; 5303 } DW1; 5304 union 5305 { 5306 //!< DWORD 2 5307 struct 5308 { 5309 uint32_t CurrentFrameSurfaceControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5310 uint32_t CurrentFrameSurfaceControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5311 uint32_t CurrentFrameSurfaceControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5312 uint32_t CurrentFrameSurfaceControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5313 uint32_t CurrentFrameSurfaceControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5314 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5315 uint32_t CurrentFrameInputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5316 }; 5317 uint32_t Value; 5318 } DW2; 5319 union 5320 { 5321 //!< DWORD 3 5322 struct 5323 { 5324 uint32_t CurrentFrameInputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; ///< GraphicsAddress 5325 uint32_t Reserved112 : __CODEGEN_BITFIELD(16, 29) ; ///< U14 5326 uint32_t CurrentFrameInputSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; ///< U2 5327 }; 5328 uint32_t Value; 5329 } DW3; 5330 union 5331 { 5332 //!< DWORD 4 5333 struct 5334 { 5335 uint32_t PreviousFrameSurfaceControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5336 uint32_t PreviousFrameSurfaceControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5337 uint32_t PreviousFrameSurfaceControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5338 uint32_t PreviousFrameSurfaceControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5339 uint32_t PreviousFrameSurfaceControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5340 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5341 uint32_t PreviousFrameInputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5342 }; 5343 uint32_t Value; 5344 } DW4; 5345 union 5346 { 5347 //!< DWORD 5 5348 struct 5349 { 5350 uint32_t PreviousFrameInputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; ///< GraphicsAddress 5351 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 29) ; ///< U14 5352 uint32_t PreviousFrameInputSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; ///< U2 5353 }; 5354 uint32_t Value; 5355 } DW5; 5356 union 5357 { 5358 //!< DWORD 6 5359 struct 5360 { 5361 uint32_t StmmInputSurfaceControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5362 uint32_t StmmInputSurfaceControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5363 uint32_t StmmInputSurfaceControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5364 uint32_t StmmInputSurfaceControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5365 uint32_t StmmInputSurfaceControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5366 uint32_t Reserved203 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5367 uint32_t StmmInputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5368 }; 5369 uint32_t Value; 5370 } DW6; 5371 union 5372 { 5373 //!< DWORD 7 5374 struct 5375 { 5376 uint32_t StmmInputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; ///< GraphicsAddress 5377 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 29) ; ///< U14 5378 uint32_t StmmInputSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; ///< U2 5379 }; 5380 uint32_t Value; 5381 } DW7; 5382 union 5383 { 5384 //!< DWORD 8 5385 struct 5386 { 5387 uint32_t StmmOutputSurfaceControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5388 uint32_t StmmOutputSurfaceControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5389 uint32_t StmmOutputSurfaceControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5390 uint32_t StmmOutputSurfaceControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5391 uint32_t StmmOutputSurfaceControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5392 uint32_t Reserved267 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5393 uint32_t StmmOutputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5394 }; 5395 uint32_t Value; 5396 } DW8; 5397 union 5398 { 5399 //!< DWORD 9 5400 struct 5401 { 5402 uint32_t StmmOutputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; ///< GraphicsAddress 5403 uint32_t Reserved304 : __CODEGEN_BITFIELD(16, 29) ; ///< U14 5404 uint32_t StmmOutputSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; ///< U2 5405 }; 5406 uint32_t Value; 5407 } DW9; 5408 union 5409 { 5410 //!< DWORD 10 5411 struct 5412 { 5413 uint32_t DenoisedCurrentOutputSurfaceControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5414 uint32_t DenoisedCurrentOutputSurfaceControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5415 uint32_t DenoisedCurrentOutputSurfaceControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5416 uint32_t DenoisedCurrentOutputSurfaceControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5417 uint32_t DenoisedCurrentOutputSurfaceControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5418 uint32_t Reserved331 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5419 uint32_t DenoisedCurrentFrameOutputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5420 }; 5421 uint32_t Value; 5422 } DW10; 5423 union 5424 { 5425 //!< DWORD 11 5426 struct 5427 { 5428 uint32_t DenoisedCurrentFrameOutputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; ///< GraphicsAddress 5429 uint32_t Reserved368 : __CODEGEN_BITFIELD(16, 29) ; ///< U14 5430 uint32_t DenoisedCurrentOutputSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; ///< U2 5431 }; 5432 uint32_t Value; 5433 } DW11; 5434 union 5435 { 5436 //!< DWORD 12 5437 struct 5438 { 5439 uint32_t CurrentFrameOutputSurfaceControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5440 uint32_t CurrentFrameOutputSurfaceControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5441 uint32_t CurrentFrameOutputSurfaceControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5442 uint32_t CurrentFrameOutputSurfaceControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5443 uint32_t CurrentFrameOutputSurfaceControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5444 uint32_t Reserved395 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5445 uint32_t CurrentFrameOutputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5446 }; 5447 uint32_t Value; 5448 } DW12; 5449 union 5450 { 5451 //!< DWORD 13 5452 struct 5453 { 5454 uint32_t CurrentFrameOutputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Current Frame Output Address High 5455 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 5456 uint32_t CurrentFrameOutputSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; //!< CURRENT_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5457 }; 5458 uint32_t Value; 5459 } DW13; 5460 union 5461 { 5462 //!< DWORD 14 5463 struct 5464 { 5465 uint32_t PreviousFrameOutputSurfaceControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5466 uint32_t PreviousFrameOutputSurfaceControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5467 uint32_t PreviousFrameOutputSurfaceControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5468 uint32_t PreviousFrameOutputSurfaceControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5469 uint32_t PreviousFrameOutputSurfaceControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5470 uint32_t Reserved459 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5471 uint32_t PreviousFrameOutputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5472 }; 5473 uint32_t Value; 5474 } DW14; 5475 union 5476 { 5477 //!< DWORD 15 5478 struct 5479 { 5480 uint32_t PreviousFrameOutputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; ///< GraphicsAddress 5481 uint32_t Reserved496 : __CODEGEN_BITFIELD(16, 29) ; ///< U14 5482 uint32_t PreviousFrameOutputSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; ///< U2 5483 }; 5484 uint32_t Value; 5485 } DW15; 5486 union 5487 { 5488 //!< DWORD 16 5489 struct 5490 { 5491 uint32_t StatisticsOutputSurfaceControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5492 uint32_t StatisticsOutputSurfaceControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5493 uint32_t StatisticsOutputSurfaceControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5494 uint32_t StatisticsOutputSurfaceControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5495 uint32_t StatisticsOutputSurfaceControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5496 uint32_t Reserved523 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5497 uint32_t StatisticsOutputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5498 }; 5499 uint32_t Value; 5500 } DW16; 5501 union 5502 { 5503 //!< DWORD 17 5504 struct 5505 { 5506 uint32_t StatisticsOutputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Statistics Output Address High 5507 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 5508 uint32_t StatisticsOutputSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; //!< STATISTICS_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5509 }; 5510 uint32_t Value; 5511 } DW17; 5512 union 5513 { 5514 //!< DWORD 18 5515 struct 5516 { 5517 uint32_t AlphaVignetteControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5518 uint32_t AlphaVignetteControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5519 uint32_t AlphaVignetteControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5520 uint32_t AlphaVignetteControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5521 uint32_t AlphaVignetteControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5522 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5523 uint32_t AlphaVignetteCorrectionAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5524 }; 5525 uint32_t Value; 5526 } DW18; 5527 union 5528 { 5529 //!< DWORD 19 5530 struct 5531 { 5532 uint32_t AlphaVignetteCorrectionAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Alpha/Vignette Correction Address High 5533 uint32_t Reserved624 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 5534 uint32_t AlphaVignetteCorrectionSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; //!< ALPHAVIGNETTE_CORRECTION_SURFACE_ARBITRATION_PRIORITY_CONTROL 5535 }; 5536 uint32_t Value; 5537 } DW19; 5538 union 5539 { 5540 //!< DWORD 20 5541 struct 5542 { 5543 uint32_t LaceAceRgbHistogramControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5544 uint32_t LaceAceRgbHistogramControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5545 uint32_t LaceAceRgbHistogramControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5546 uint32_t LaceAceRgbHistogramControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5547 uint32_t LaceAceRgbHistogramControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5548 uint32_t Reserved651 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5549 uint32_t LaceAceRgbHistogramOutputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5550 }; 5551 uint32_t Value; 5552 } DW20; 5553 union 5554 { 5555 //!< DWORD 21 5556 struct 5557 { 5558 uint32_t LaceAceRgbHistogramOutputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; ///< GraphicsAddress 5559 uint32_t Reserved688 : __CODEGEN_BITFIELD(16, 29) ; ///< U14 5560 uint32_t LaceAceRgbHistogramSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; ///< U2 5561 }; 5562 uint32_t Value; 5563 } DW21; 5564 union 5565 { 5566 //!< DWORD 22 5567 struct 5568 { 5569 uint32_t SkinScoreOutputControlBitsReserved0 : __CODEGEN_BITFIELD( 0, 0) ; ///< Sub-structure 5570 uint32_t SkinScoreOutputControlBitsIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; ///< Sub-structure 5571 uint32_t SkinScoreOutputControlBitsMemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; ///< Sub-structure 5572 uint32_t SkinScoreOutputControlBitsMemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; ///< Sub-structure 5573 uint32_t SkinScoreOutputControlBitsTiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; ///< Sub-structure 5574 uint32_t Reserved715 : __CODEGEN_BITFIELD(11, 11) ; ///< U1 5575 uint32_t SkinScoreOutputAddress : __CODEGEN_BITFIELD(12, 31) ; ///< GraphicsAddress 5576 }; 5577 uint32_t Value; 5578 } DW22; 5579 union 5580 { 5581 //!< DWORD 23 5582 struct 5583 { 5584 uint32_t SkinScoreOutputAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; ///< GraphicsAddress 5585 uint32_t Reserved752 : __CODEGEN_BITFIELD(16, 29) ; ///< U14 5586 uint32_t SkinScoreOutputSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD(30, 31) ; ///< U2 5587 }; 5588 uint32_t Value; 5589 } DW23; 5590 5591 //! \name Local enumerations 5592 5593 enum SUBOPB 5594 { 5595 SUBOPB_VEBDIIECP = 3, //!< No additional details 5596 }; 5597 5598 enum SUBOPA 5599 { 5600 SUBOPA_VEBDIIECP = 0, //!< No additional details 5601 }; 5602 5603 enum OPCODE 5604 { 5605 OPCODE_VEBOX = 4, //!< No additional details 5606 }; 5607 5608 enum PIPELINE 5609 { 5610 PIPELINE_MEDIA = 2, //!< No additional details 5611 }; 5612 5613 enum COMMAND_TYPE 5614 { 5615 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5616 }; 5617 5618 //! \brief CURRENT_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5619 //! \details 5620 //! This field controls the priority of arbitration used in the GAC/GAM 5621 //! pipeline for this surface. 5622 enum CURRENT_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5623 { 5624 CURRENT_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5625 CURRENT_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5626 CURRENT_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5627 CURRENT_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5628 }; 5629 5630 //! \brief PREVIOUS_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5631 //! \details 5632 //! This field controls the priority of arbitration used in the GAC/GAM 5633 //! pipeline for this surface. 5634 enum PREVIOUS_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5635 { 5636 PREVIOUS_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5637 PREVIOUS_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5638 PREVIOUS_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5639 PREVIOUS_FRAME_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5640 }; 5641 5642 //! \brief STMM_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5643 //! \details 5644 //! This field controls the priority of arbitration used in the GAC/GAM 5645 //! pipeline for this surface. 5646 enum STMM_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5647 { 5648 STMM_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5649 STMM_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5650 STMM_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5651 STMM_INPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5652 }; 5653 5654 //! \brief STMM_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5655 //! \details 5656 //! This field controls the priority of arbitration used in the GAC/GAM 5657 //! pipeline for this surface. 5658 enum STMM_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5659 { 5660 STMM_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5661 STMM_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5662 STMM_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5663 STMM_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5664 }; 5665 5666 //! \brief DENOISED_CURRENT_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5667 //! \details 5668 //! This field controls the priority of arbitration used in the GAC/GAM 5669 //! pipeline for this surface. 5670 enum DENOISED_CURRENT_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5671 { 5672 DENOISED_CURRENT_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5673 DENOISED_CURRENT_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5674 DENOISED_CURRENT_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5675 DENOISED_CURRENT_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5676 }; 5677 5678 //! \brief CURRENT_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5679 //! \details 5680 //! This field controls the priority of arbitration used in the GAC/GAM 5681 //! pipeline for this surface. 5682 enum CURRENT_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5683 { 5684 CURRENT_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5685 CURRENT_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5686 CURRENT_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5687 CURRENT_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5688 }; 5689 5690 //! \brief PREVIOUS_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5691 //! \details 5692 //! This field controls the priority of arbitration used in the GAC/GAM 5693 //! pipeline for this surface. 5694 enum PREVIOUS_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5695 { 5696 PREVIOUS_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5697 PREVIOUS_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5698 PREVIOUS_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5699 PREVIOUS_FRAME_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5700 }; 5701 5702 //! \brief STATISTICS_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5703 //! \details 5704 //! This field controls the priority of arbitration used in the GAC/GAM 5705 //! pipeline for this surface. 5706 enum STATISTICS_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5707 { 5708 STATISTICS_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5709 STATISTICS_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5710 STATISTICS_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5711 STATISTICS_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5712 }; 5713 5714 //! \brief ALPHAVIGNETTE_CORRECTION_SURFACE_ARBITRATION_PRIORITY_CONTROL 5715 //! \details 5716 //! This field controls the priority of arbitration used in the GAC/GAM 5717 //! pipeline for this surface. 5718 enum ALPHAVIGNETTE_CORRECTION_SURFACE_ARBITRATION_PRIORITY_CONTROL 5719 { 5720 ALPHAVIGNETTE_CORRECTION_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5721 ALPHAVIGNETTE_CORRECTION_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5722 ALPHAVIGNETTE_CORRECTION_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5723 ALPHAVIGNETTE_CORRECTION_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5724 }; 5725 5726 //! \brief LACEACERGB_HISTOGRAM_SURFACE_ARBITRATION_PRIORITY_CONTROL 5727 //! \details 5728 //! This field controls the priority of arbitration used in the GAC/GAM 5729 //! pipeline for this surface. 5730 enum LACEACERGB_HISTOGRAM_SURFACE_ARBITRATION_PRIORITY_CONTROL 5731 { 5732 LACEACERGB_HISTOGRAM_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5733 LACEACERGB_HISTOGRAM_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5734 LACEACERGB_HISTOGRAM_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5735 LACEACERGB_HISTOGRAM_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5736 }; 5737 5738 //! \brief SKIN_SCORE_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5739 //! \details 5740 //! This field controls the priority of arbitration used in the GAC/GAM 5741 //! pipeline for this surface. 5742 enum SKIN_SCORE_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL 5743 { 5744 SKIN_SCORE_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 5745 SKIN_SCORE_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 5746 SKIN_SCORE_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 5747 SKIN_SCORE_OUTPUT_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 5748 }; 5749 5750 //! \name Initializations 5751 5752 //! \brief Explicit member initialization function 5753 VEB_DI_IECP_CMD(); 5754 5755 static const size_t dwSize = 24; 5756 static const size_t byteSize = 96; 5757 }; 5758 5759 //! 5760 //! \brief VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS 5761 //! \details 5762 //! 5763 //! 5764 struct VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS_CMD 5765 { 5766 union 5767 { 5768 //!< DWORD 0 5769 struct 5770 { 5771 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 0) ; //!< Protected Data 5772 uint32_t IndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Index to Memory Object Control State (MOCS) Tables 5773 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Memory Compression Enable 5774 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD( 8, 8) ; //!< MEMORY_COMPRESSION_MODE 5775 uint32_t TiledResourceModeForOutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD( 9, 10) ; //!< TILED_RESOURCE_MODE_FOR_OUTPUT_FRAME_SURFACE_BASE_ADDRESS 5776 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 5777 }; 5778 uint32_t Value; 5779 } DW0; 5780 //! \name Local enumerations 5781 5782 //! \brief MEMORY_COMPRESSION_MODE 5783 //! \details 5784 //! Distinguishes Vertical from Horizontal compression. 5785 enum MEMORY_COMPRESSION_MODE 5786 { 5787 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 5788 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 5789 }; 5790 5791 //! \brief TILED_RESOURCE_MODE_FOR_OUTPUT_FRAME_SURFACE_BASE_ADDRESS 5792 //! \details 5793 //! <b>For Media Surfaces:</b> 5794 //! This field specifies the tiled resource mode. 5795 enum TILED_RESOURCE_MODE_FOR_OUTPUT_FRAME_SURFACE_BASE_ADDRESS 5796 { 5797 TILED_RESOURCE_MODE_FOR_OUTPUT_FRAME_SURFACE_BASE_ADDRESS_TRMODENONE = 0, //!< No tiled resource 5798 TILED_RESOURCE_MODE_FOR_OUTPUT_FRAME_SURFACE_BASE_ADDRESS_TRMODETILEYF = 1, //!< 4KB tiled resources 5799 TILED_RESOURCE_MODE_FOR_OUTPUT_FRAME_SURFACE_BASE_ADDRESS_TRMODETILEYS = 2, //!< 64KB tiled resources 5800 }; 5801 5802 //! \name Initializations 5803 5804 //! \brief Explicit member initialization function 5805 VEB_DI_IECP_COMMAND_SURFACE_CONTROL_BITS_CMD(); 5806 5807 static const size_t dwSize = 1; 5808 static const size_t byteSize = 4; 5809 }; 5810 5811 //! 5812 //! \brief VEBOX_VERTEX_TABLE_ENTRY 5813 //! \details 5814 //! 5815 //! 5816 struct VEBOX_VERTEX_TABLE_ENTRY 5817 { 5818 union 5819 { 5820 //!< DWORD 0 5821 struct 5822 { 5823 uint32_t Vertextableentry0_Cv : __CODEGEN_BITFIELD(0, 11); //!< Vertex table entry 0 - Cv(12 bits) 5824 uint32_t : __CODEGEN_BITFIELD(12, 15); //!< Reserved 5825 uint32_t Vertextableentry0_Lv : __CODEGEN_BITFIELD(16, 27); //!< Vertex table entry 0 - Lv(12 bits) 5826 uint32_t : __CODEGEN_BITFIELD(28, 31); //!< Reserved 5827 }; 5828 uint32_t Value; 5829 } DW0; 5830 5831 static const size_t dwSize = 1; 5832 static const size_t byteSize = 4; 5833 5834 }; 5835 5836 //! 5837 //! \brief VEBOX_VERTEX_TABLE 5838 //! \details 5839 //! 5840 //! 5841 struct VEBOX_VERTEX_TABLE_CMD 5842 { 5843 VEBOX_VERTEX_TABLE_ENTRY VertexTableEntry[512]; 5844 5845 static const size_t dwSize = 512; 5846 static const size_t byteSize = 2048; 5847 }; 5848 5849 }; 5850 5851 #pragma pack() 5852 5853 #endif // __MHW_VEBOX_HWCMD_G9_X_H__