1 /*===================== begin_copyright_notice ================================== 2 3 # Copyright (c) 2022, Intel Corporation 4 5 # Permission is hereby granted, free of charge, to any person obtaining a 6 # copy of this software and associated documentation files (the "Software"), 7 # to deal in the Software without restriction, including without limitation 8 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 # and/or sell copies of the Software, and to permit persons to whom the 10 # Software is furnished to do so, subject to the following conditions: 11 12 # The above copyright notice and this permission notice shall be included 13 # in all copies or substantial portions of the Software. 14 15 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 # OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_xe_lpm_plus_base.h 26 //! \brief Defines structures used for constructing VDBox commands on Xe_LPM_plus+ platforms 27 //! 28 29 #ifndef _MHW_VDBOX_XE_LPM_PLUS_BASE_H_ 30 #define _MHW_VDBOX_XE_LPM_PLUS_BASE_H_ 31 32 #include "mos_os.h" 33 #include "mhw_vdbox.h" 34 35 #define MmcEnable(x) ((x) == MOS_MEMCOMP_RC || (x) == MOS_MEMCOMP_MC) 36 #define MmcIsRc(x) ((x) == MOS_MEMCOMP_RC) 37 38 namespace mhw 39 { 40 namespace vdbox 41 { 42 namespace xe_lpm_plus_base 43 { 44 // Meta/MV, DeBlock, SAO, VDEnc, HSAO 45 const bool RowStoreCacheEnableHEVC[16][5] = 46 { 47 { 1, 1, 1, 0, 1 }, { 1, 1, 1, 1, 1 }, { 1, 1, 0, 0, 0 }, { 1, 1, 0, 1, 0 }, 48 { 1, 1, 1, 1, 1 }, { 1, 1, 0, 0, 1 }, { 1, 1, 1, 0, 0 }, { 1, 0, 1, 0, 1 }, 49 { 1, 1, 1, 0, 0 }, { 1, 0, 1, 0, 1 }, { 1, 1, 1, 1, 1 }, { 1, 1, 0, 1, 1 }, 50 { 1, 1, 1, 1, 1 }, { 1, 0, 1, 1, 1 }, { 1, 1, 1, 1, 1 }, { 1, 0, 1, 1, 1 } 51 }; 52 53 const uint32_t RowStoreCacheAddrHEVC[16][5] = 54 { 55 { 0, 256, 1280, 0, 2048 }, { 0, 256, 1280, 1824, 1792 }, { 0, 512, 0, 0, 0 }, { 0, 256, 0, 2304, 0 }, 56 { 0, 256, 1024, 0, 1792 }, { 0, 512, 0, 0, 2048 }, { 0, 256, 1792, 0, 0 }, { 0, 0, 512, 0, 2048 }, 57 { 0, 256, 1792, 0, 0 }, { 0, 0, 256, 0, 1792 }, { 0, 256, 1024, 1568, 1536 }, { 0, 512, 0, 2112, 2048 }, 58 { 0, 256, 1792, 2336, 2304 }, { 0, 0, 512, 1600, 1536 }, { 0, 128, 1664, 2336, 2304 }, { 0, 0, 256, 1600, 1536 } 59 }; 60 61 // HVD, Meta/MV, DeBlock, VDEnc 62 const bool RowStoreCacheEnableVP9[13][4] = 63 { 64 { 1, 1, 1, 1 }, { 0, 0, 1, 1 }, { 1, 0, 1, 1 }, { 1, 1, 0, 1 }, 65 { 1, 1, 1, 1 }, { 0, 0, 1, 1 }, { 0, 0, 1, 0 }, { 1, 1, 0, 1 }, 66 { 1, 1, 1, 1 }, { 1, 1, 0, 1 }, { 1, 1, 1, 1 }, { 1, 1, 0, 1 }, 67 { 1, 1, 0, 1 } 68 }; 69 70 const uint32_t RowStoreCacheAddrVP9[13][4] = 71 { 72 { 0, 64, 384, 1536, }, { 0, 0, 0, 2304, }, { 0, 0, 64, 2368, }, { 0, 128, 0, 768, }, 73 { 0, 64, 384, 1536, }, { 0, 0, 0, 2304, }, { 0, 0, 0, 0, }, { 0, 128, 0, 768, }, 74 { 0, 64, 384, 2112, }, { 0, 128, 0, 768, }, { 0, 32, 192, 1920, }, { 0, 128, 0, 768, }, 75 { 0, 128, 0, 768, } 76 }; 77 78 struct MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_XE_LPM_PLUS_BASE : public MHW_VDBOX_PIPE_MODE_SELECT_PARAMS 79 { 80 // GEN11+ specific 81 MHW_VDBOX_HCP_PIPE_WORK_MODE PipeWorkMode = MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY; 82 MHW_VDBOX_HCP_MULTI_ENGINE_MODE MultiEngineMode = MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY; 83 84 // GEN12 specific 85 bool bTileBasedReplayMode = false; 86 bool bWirelessEncodeEnabled = false; 87 uint8_t ucWirelessSessionId = 0; 88 bool bRGBEncodingMode = false; 89 uint8_t ucPhaseIndicator = 0; 90 bool bBRCEnabled = false; 91 bool bHEVCSeparateTileProgramming = false; 92 bool bStreamingBufferEnabled = false; 93 bool bIsRandomAccess = false; 94 bool bLookaheadPass = false; 95 uint8_t tuMinus1 = 3; 96 uint8_t ucQuantizationPrecision = 1; 97 uint8_t tuSettingsRevision = 0; 98 }; 99 using PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS_XE_LPM_PLUS_BASE = MHW_VDBOX_PIPE_MODE_SELECT_PARAMS_XE_LPM_PLUS_BASE *; 100 101 struct MHW_VDBOX_STATE_CMDSIZE_PARAMS_XE_LPM_PLUS_BASE : public MHW_VDBOX_STATE_CMDSIZE_PARAMS 102 { 103 bool bScalableMode = 0; 104 }; 105 using PMHW_VDBOX_STATE_CMDSIZE_PARAMS_XE_LPM_PLUS_BASE = MHW_VDBOX_STATE_CMDSIZE_PARAMS_XE_LPM_PLUS_BASE *; 106 107 struct MHW_VDBOX_HCP_TILE_CODING_PARAMS_XE_LPM_PLUS_BASE 108 { 109 uint32_t NumOfTilesInFrame; 110 uint32_t NumOfTileColumnsInFrame; 111 uint32_t TileStartLCUX; 112 uint32_t TileStartLCUY; 113 uint16_t TileHeightInMinCbMinus1; 114 uint16_t TileWidthInMinCbMinus1; 115 bool IsLastTileofColumn; 116 bool IsLastTileofRow; 117 uint32_t TileRowStoreSelect; 118 uint32_t TileColumnStoreSelect; 119 uint32_t Mode; 120 bool IsFirstPass; 121 bool IsLastPass; 122 bool bTileReplayEnable; 123 124 // Offsets for scalability 125 uint32_t NumberOfActiveBePipes; 126 uint32_t BitstreamByteOffset; 127 uint32_t PakTileStatisticsOffset; 128 uint32_t CuLevelStreamoutOffset; 129 uint32_t SliceSizeStreamoutOffset; 130 uint32_t CuRecordOffset; 131 uint32_t SseRowstoreOffset; 132 uint32_t SaoRowstoreOffset; 133 uint32_t TileSizeStreamoutOffset; 134 uint32_t Vp9ProbabilityCounterStreamoutOffset; 135 uint32_t TileStreaminOffset; 136 uint32_t CumulativeCUTileOffset; 137 uint32_t TileLCUStreamOutOffset; 138 139 PMOS_RESOURCE presHcpSyncBuffer; // this buffer is not used for either HEVC/VP9 encoder and decoder. 140 141 //Decode specific sparameters 142 uint8_t ucNumDecodePipes; 143 uint8_t ucPipeIdx; 144 }; 145 using PMHW_VDBOX_HCP_TILE_CODING_PARAMS_XE_LPM_PLUS_BASE = MHW_VDBOX_HCP_TILE_CODING_PARAMS_XE_LPM_PLUS_BASE *; 146 147 struct MHW_VDBOX_VD_PIPE_FLUSH_PARAMS_XE_LPM_PLUS_BASE 148 { 149 union 150 { 151 struct 152 { 153 uint16_t bWaitDoneHEVC : 1; 154 uint16_t bWaitDoneVDENC : 1; 155 uint16_t bWaitDoneMFL : 1; 156 uint16_t bWaitDoneMFX : 1; 157 uint16_t bWaitDoneVDCmdMsgParser : 1; 158 uint16_t bFlushHEVC : 1; 159 uint16_t bFlushVDENC : 1; 160 uint16_t bFlushMFL : 1; 161 uint16_t bFlushMFX : 1; 162 uint16_t bWaitDoneAV1 : 1; 163 uint16_t bFlushAV1 : 1; 164 uint16_t : 5; 165 }; 166 struct 167 { 168 uint16_t Value; 169 }; 170 }Flags; 171 }; 172 using PMHW_VDBOX_VD_PIPE_FLUSH_PARAMS_XE_LPM_PLUS_BASE = MHW_VDBOX_VD_PIPE_FLUSH_PARAMS_XE_LPM_PLUS_BASE *; 173 } // namespace xe_lpm_plus_base 174 } // namespace vdbox 175 } // namespace mhw 176 #endif // _MHW_VDBOX_XE_LPM_PLUS_BASE_H_ 177