1 /* 2 * Copyright (c) 2020-2022, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_vdenc_itf.h 24 //! \brief MHW VDBOX VDENC interface common base 25 //! \details 26 //! 27 28 #ifndef __MHW_VDBOX_VDENC_ITF_H__ 29 #define __MHW_VDBOX_VDENC_ITF_H__ 30 31 #include "mhw_itf.h" 32 #include "mhw_vdbox_vdenc_cmdpar.h" 33 #include "mhw_utilities.h" 34 #include "mhw_vdbox.h" 35 36 #define _VDENC_CMD_DEF(DEF) \ 37 DEF(VDENC_CONTROL_STATE); \ 38 DEF(VDENC_PIPE_MODE_SELECT); \ 39 DEF(VDENC_SRC_SURFACE_STATE); \ 40 DEF(VDENC_REF_SURFACE_STATE); \ 41 DEF(VDENC_DS_REF_SURFACE_STATE); \ 42 DEF(VDENC_PIPE_BUF_ADDR_STATE); \ 43 DEF(VDENC_WEIGHTSOFFSETS_STATE); \ 44 DEF(VDENC_HEVC_VP9_TILE_SLICE_STATE); \ 45 DEF(VDENC_WALKER_STATE); \ 46 DEF(VD_PIPELINE_FLUSH); \ 47 DEF(VDENC_AVC_SLICE_STATE); \ 48 DEF(VDENC_AVC_IMG_STATE); \ 49 DEF(VDENC_CMD1); \ 50 DEF(VDENC_CMD2); \ 51 DEF(VDENC_CMD3) 52 53 namespace mhw 54 { 55 namespace vdbox 56 { 57 namespace vdenc 58 { 59 class Itf 60 { 61 public: 62 enum CommandsNumberOfAddresses 63 { 64 VDENC_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 21 65 }; 66 67 class ParSetting 68 { 69 public: 70 virtual ~ParSetting() = default; 71 72 _VDENC_CMD_DEF(_MHW_SETPAR_DEF); 73 }; 74 75 virtual ~Itf() = default; 76 77 virtual MOS_STATUS SetRowstoreCachingOffsets(const RowStorePar &par) = 0; 78 79 virtual MOS_STATUS SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS settings[MOS_CODEC_RESOURCE_USAGE_END_CODEC]) = 0; 80 81 virtual bool IsPerfModeSupported() = 0; 82 83 virtual bool IsRhoDomainStatsEnabled() = 0; 84 85 virtual MmioRegistersVdbox *GetMmioRegisters(MHW_VDBOX_NODE_IND index) = 0; 86 87 //! 88 //! \brief Convert from Vdbox mmio registers to MI mmio register 89 //! 90 //! \param [in] index 91 //! mmio registers index. 92 //! \param [in] mmioRegister 93 //! reference to MHW_MI_MMIOREGISTERS. 94 //! 95 //! \return [out] bool 96 //! return true if mmio register if found, otherwise return false 97 //! ConvertToMiRegister(MHW_VDBOX_NODE_IND index,MHW_MI_MMIOREGISTERS & mmioRegister)98 virtual inline bool ConvertToMiRegister(MHW_VDBOX_NODE_IND index, MHW_MI_MMIOREGISTERS &mmioRegister) 99 { 100 MmioRegistersVdbox *vdboxMmioReg = GetMmioRegisters(index); 101 if (vdboxMmioReg) 102 { 103 mmioRegister.generalPurposeRegister0LoOffset = vdboxMmioReg->generalPurposeRegister0LoOffset; 104 mmioRegister.generalPurposeRegister0HiOffset = vdboxMmioReg->generalPurposeRegister0HiOffset; 105 mmioRegister.generalPurposeRegister4LoOffset = vdboxMmioReg->generalPurposeRegister4LoOffset; 106 mmioRegister.generalPurposeRegister4HiOffset = vdboxMmioReg->generalPurposeRegister4HiOffset; 107 mmioRegister.generalPurposeRegister11LoOffset = vdboxMmioReg->generalPurposeRegister11LoOffset; 108 mmioRegister.generalPurposeRegister11HiOffset = vdboxMmioReg->generalPurposeRegister11HiOffset; 109 mmioRegister.generalPurposeRegister12LoOffset = vdboxMmioReg->generalPurposeRegister12LoOffset; 110 mmioRegister.generalPurposeRegister12HiOffset = vdboxMmioReg->generalPurposeRegister12HiOffset; 111 return true; 112 } 113 else 114 return false; 115 } 116 117 _VDENC_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_ITF); 118 119 bool m_perfModeSupported = false; 120 bool m_rhoDomainStatsEnabled = false; 121 MHW_VDBOX_NODE_IND m_maxVdboxIndex = MHW_VDBOX_NODE_1; //!< max vdbox index 122 123 MEDIA_CLASS_DEFINE_END(mhw__vdbox__vdenc__Itf) 124 }; 125 } // namespace vdenc 126 } // namespace vdbox 127 } // namespace mhw 128 129 #endif // __MHW_VDBOX_VDENC_ITF_H__ 130