1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_vdenc_hwcmd_g11_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g11_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_VDBOX_VDENC_HWCMD_G11_X_H__ 29 #define __MHW_VDBOX_VDENC_HWCMD_G11_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_vdbox_vdenc_g11_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief VDENC_64B_Aligned_Lower_Address 50 //! \details 51 //! 52 //! 53 struct VDENC_64B_Aligned_Lower_Address_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 61 uint32_t Address : __CODEGEN_BITFIELD( 6, 31) ; //!< Address 62 }; 63 uint32_t Value; 64 } DW0; 65 66 //! \name Local enumerations 67 68 //! \name Initializations 69 70 //! \brief Explicit member initialization function 71 VDENC_64B_Aligned_Lower_Address_CMD(); 72 73 static const size_t dwSize = 1; 74 static const size_t byteSize = 4; 75 }; 76 77 //! 78 //! \brief VDENC_64B_Aligned_Upper_Address 79 //! \details 80 //! 81 //! 82 struct VDENC_64B_Aligned_Upper_Address_CMD 83 { 84 union 85 { 86 //!< DWORD 0 87 struct 88 { 89 uint32_t AddressUpperDword : __CODEGEN_BITFIELD( 0, 15) ; //!< Address Upper DWord 90 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 91 }; 92 uint32_t Value; 93 } DW0; 94 95 //! \name Local enumerations 96 97 //! \name Initializations 98 99 //! \brief Explicit member initialization function 100 VDENC_64B_Aligned_Upper_Address_CMD(); 101 102 static const size_t dwSize = 1; 103 static const size_t byteSize = 4; 104 }; 105 106 //! 107 //! \brief VDENC_Surface_Control_Bits 108 //! \details 109 //! 110 //! 111 struct VDENC_Surface_Control_Bits_CMD 112 { 113 union 114 { 115 //!< DWORD 0 116 struct 117 { 118 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Index to Memory Object Control State (MOCS) Tables: 119 uint32_t ArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< ARBITRATION_PRIORITY_CONTROL 120 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MEMORY_COMPRESSION_ENABLE 121 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< MEMORY_COMPRESSION_MODE 122 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 123 uint32_t CacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< CACHE_SELECT 124 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< TILED_RESOURCE_MODE 125 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 126 }; 127 uint32_t Value; 128 } DW0; 129 130 //! \name Local enumerations 131 132 //! \brief ARBITRATION_PRIORITY_CONTROL 133 //! \details 134 //! This field controls the priority of arbitration used in the GAC/GAM 135 //! pipeline for this surface. 136 enum ARBITRATION_PRIORITY_CONTROL 137 { 138 ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 139 ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 140 ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 141 ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 142 }; 143 144 //! \brief MEMORY_COMPRESSION_ENABLE 145 //! \details 146 //! Memory compression will be attempted for this surface. 147 enum MEMORY_COMPRESSION_ENABLE 148 { 149 MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 150 MEMORY_COMPRESSION_ENABLE_ENABLE = 1, //!< No additional details 151 }; 152 153 //! \brief MEMORY_COMPRESSION_MODE 154 //! \details 155 //! Distinguishes Vertical from Horizontal compression. Please refer to 156 //! vol1a <b>Memory Data</b>. 157 enum MEMORY_COMPRESSION_MODE 158 { 159 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 160 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 161 }; 162 163 //! \brief CACHE_SELECT 164 //! \details 165 //! This field controls if the Row Store is going to store inside Media 166 //! Cache (rowstore cache) or to LLC. 167 enum CACHE_SELECT 168 { 169 CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 170 CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 171 }; 172 173 //! \brief TILED_RESOURCE_MODE 174 //! \details 175 //! <b>For Media Surfaces</b>: This field specifies the tiled resource mode. 176 enum TILED_RESOURCE_MODE 177 { 178 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource. 179 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 180 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 181 }; 182 183 //! \name Initializations 184 185 //! \brief Explicit member initialization function 186 VDENC_Surface_Control_Bits_CMD(); 187 188 static const size_t dwSize = 1; 189 static const size_t byteSize = 4; 190 }; 191 192 //! 193 //! \brief VDENC_Sub_Mb_Pred_Mode 194 //! \details 195 //! 196 //! 197 struct VDENC_Sub_Mb_Pred_Mode_CMD 198 { 199 union 200 { 201 //!< WORD 0 202 struct 203 { 204 uint8_t Submbpredmode0 : __CODEGEN_BITFIELD( 0, 1) ; //!< SubMbPredMode[0] 205 uint8_t Submbpredmode1 : __CODEGEN_BITFIELD( 2, 3) ; //!< SubMbPredMode[1] 206 uint8_t Submbpredmode2 : __CODEGEN_BITFIELD( 4, 5) ; //!< SubMbPredMode[2] 207 uint8_t Submbpredmode3 : __CODEGEN_BITFIELD( 6, 7) ; //!< SubMbPredMode[3] 208 }; 209 uint8_t Value; 210 } DW0; 211 212 //! \name Local enumerations 213 214 //! \name Initializations 215 216 //! \brief Explicit member initialization function 217 VDENC_Sub_Mb_Pred_Mode_CMD(); 218 219 static const size_t dwSize = 0; 220 static const size_t byteSize = 1; 221 }; 222 223 //! 224 //! \brief VDENC_Block_8x8_4 225 //! \details 226 //! 227 //! 228 struct VDENC_Block_8x8_4_CMD 229 { 230 union 231 { 232 //!< WORD 0 233 struct 234 { 235 uint16_t Block8X80 : __CODEGEN_BITFIELD( 0, 3) ; //!< Block8x8[0] 236 uint16_t Block8X81 : __CODEGEN_BITFIELD( 4, 7) ; //!< Block8x8[1] 237 uint16_t Block8X82 : __CODEGEN_BITFIELD( 8, 11) ; //!< Block8x8[2] 238 uint16_t Block8X83 : __CODEGEN_BITFIELD(12, 15) ; //!< Block8x8[3] 239 }; 240 uint16_t Value; 241 } DW0; 242 243 //! \name Local enumerations 244 245 //! \name Initializations 246 247 //! \brief Explicit member initialization function 248 VDENC_Block_8x8_4_CMD(); 249 250 static const size_t dwSize = 0; 251 static const size_t byteSize = 2; 252 }; 253 254 //! 255 //! \brief VDENC_Delta_MV_XY 256 //! \details 257 //! 258 //! 259 //! Calculates the difference between the actual MV for the Sub Macroblock 260 //! and the predicted MV based on the availability of the neighbors. 261 //! 262 //! This is calculated and populated for Inter frames only. In case of an 263 //! Intra MB in Inter frames, this value should be 0. 264 //! 265 struct VDENC_Delta_MV_XY_CMD 266 { 267 union 268 { 269 //!< DWORD 0 270 struct 271 { 272 uint32_t X0 : __CODEGEN_BITFIELD( 0, 15) ; //!< X0 273 uint32_t Y0 : __CODEGEN_BITFIELD(16, 31) ; //!< Y0 274 }; 275 uint32_t Value; 276 } DW0; 277 union 278 { 279 //!< DWORD 1 280 struct 281 { 282 uint32_t X1 : __CODEGEN_BITFIELD( 0, 15) ; //!< X1 283 uint32_t Y1 : __CODEGEN_BITFIELD(16, 31) ; //!< Y1 284 }; 285 uint32_t Value; 286 } DW1; 287 union 288 { 289 //!< DWORD 2 290 struct 291 { 292 uint32_t X2 : __CODEGEN_BITFIELD( 0, 15) ; //!< X2 293 uint32_t Y2 : __CODEGEN_BITFIELD(16, 31) ; //!< Y2 294 }; 295 uint32_t Value; 296 } DW2; 297 union 298 { 299 //!< DWORD 3 300 struct 301 { 302 uint32_t X3 : __CODEGEN_BITFIELD( 0, 15) ; //!< X3 303 uint32_t Y3 : __CODEGEN_BITFIELD(16, 31) ; //!< Y3 304 }; 305 uint32_t Value; 306 } DW3; 307 308 //! \name Local enumerations 309 310 //! \brief X0 311 //! \details 312 enum X0 313 { 314 X0_UNNAMED0 = 0, //!< No additional details 315 }; 316 317 //! \brief Y0 318 //! \details 319 enum Y0 320 { 321 Y0_UNNAMED0 = 0, //!< No additional details 322 }; 323 324 //! \brief X1 325 //! \details 326 enum X1 327 { 328 X1_UNNAMED0 = 0, //!< No additional details 329 }; 330 331 //! \brief Y1 332 //! \details 333 enum Y1 334 { 335 Y1_UNNAMED0 = 0, //!< No additional details 336 }; 337 338 //! \brief X2 339 //! \details 340 enum X2 341 { 342 X2_UNNAMED0 = 0, //!< No additional details 343 }; 344 345 //! \brief Y2 346 //! \details 347 enum Y2 348 { 349 Y2_UNNAMED0 = 0, //!< No additional details 350 }; 351 352 //! \brief X3 353 //! \details 354 enum X3 355 { 356 X3_UNNAMED0 = 0, //!< No additional details 357 }; 358 359 //! \brief Y3 360 //! \details 361 enum Y3 362 { 363 Y3_UNNAMED0 = 0, //!< No additional details 364 }; 365 366 //! \name Initializations 367 368 //! \brief Explicit member initialization function 369 VDENC_Delta_MV_XY_CMD(); 370 371 static const size_t dwSize = 4; 372 static const size_t byteSize = 16; 373 }; 374 375 //! 376 //! \brief VDENC_Colocated_MV_Picture 377 //! \details 378 //! 379 //! 380 struct VDENC_Colocated_MV_Picture_CMD 381 { 382 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 383 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 384 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 385 386 //! \name Local enumerations 387 388 //! \name Initializations 389 390 //! \brief Explicit member initialization function 391 VDENC_Colocated_MV_Picture_CMD(); 392 393 static const size_t dwSize = 3; 394 static const size_t byteSize = 12; 395 }; 396 397 //! 398 //! \brief VDENC_Down_Scaled_Reference_Picture 399 //! \details 400 //! 401 //! 402 struct VDENC_Down_Scaled_Reference_Picture_CMD 403 { 404 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 405 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 406 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 407 408 //! \name Local enumerations 409 410 //! \name Initializations 411 412 //! \brief Explicit member initialization function 413 VDENC_Down_Scaled_Reference_Picture_CMD(); 414 415 static const size_t dwSize = 3; 416 static const size_t byteSize = 12; 417 }; 418 419 //! 420 //! \brief VDENC_FRAME_BASED_STATISTICS_STREAMOUT 421 //! \details 422 //! 423 //! 424 struct VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD 425 { 426 union 427 { 428 //!< DWORD 0 429 struct 430 { 431 uint32_t SumSadHaarForBestMbChoice ; //!< Sum sad\haar for best MB choice 432 }; 433 uint32_t Value; 434 } DW0; 435 union 436 { 437 //!< DWORD 1 438 struct 439 { 440 uint32_t IntraIso16X16MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 16x16 MB count 441 uint32_t IntraMbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra MB count 442 }; 443 uint32_t Value; 444 } DW1; 445 union 446 { 447 //!< DWORD 2 448 struct 449 { 450 uint32_t IntraIso4X4MbCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra iso 4x4 MB count 451 uint32_t IntraIso8X8MbCount : __CODEGEN_BITFIELD(16, 31) ; //!< Intra iso 8x8 MB count 452 }; 453 uint32_t Value; 454 } DW2; 455 union 456 { 457 //!< DWORD 3 458 struct 459 { 460 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 0 461 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 1 462 }; 463 uint32_t Value; 464 } DW3; 465 union 466 { 467 //!< DWORD 4 468 struct 469 { 470 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD( 0, 15) ; //!< segment map count 2 471 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD(16, 31) ; //!< segment map count 3 472 }; 473 uint32_t Value; 474 } DW4; 475 476 uint32_t Reserved160[12]; //!< Reserved 477 478 union 479 { 480 //!< DWORD 17 481 struct 482 { 483 uint32_t SumSadHaarForBestMbChoiceBottomHalfPopulation ; //!< Sum sad\haar for best MB choice bottom half population 484 }; 485 uint32_t Value; 486 } DW17; 487 union 488 { 489 //!< DWORD 18 490 struct 491 { 492 uint32_t SumSadHaarForBestMbChoiceTopHalfPopulation ; //!< Sum sad\haar for best MB choice top half population 493 }; 494 uint32_t Value; 495 } DW18; 496 union 497 { 498 //!< DWORD 19 499 struct 500 { 501 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD( 0, 15) ; //!< Sum top half population occurrences 502 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31) ; //!< Sum bottom half population occurrences 503 }; 504 uint32_t Value; 505 } DW19; 506 507 //! \name Local enumerations 508 509 //! \name Initializations 510 511 //! \brief Explicit member initialization function 512 VDENC_FRAME_BASED_STATISTICS_STREAMOUT_CMD(); 513 514 static const size_t dwSize = 20; 515 static const size_t byteSize = 80; 516 }; 517 518 //! 519 //! \brief VDENC_Mode_StreamOut_Data 520 //! \details 521 //! 522 //! 523 struct VDENC_Mode_StreamOut_Data_CMD 524 { 525 union 526 { 527 //!< DWORD 0 528 struct 529 { 530 uint32_t MbX : __CODEGEN_BITFIELD( 0, 7) ; //!< MB.X 531 uint32_t MbY : __CODEGEN_BITFIELD( 8, 15) ; //!< MB.Y 532 uint32_t MinimalDistortion : __CODEGEN_BITFIELD(16, 31) ; //!< Minimal Distortion 533 }; 534 uint32_t Value; 535 } DW0; 536 union 537 { 538 //!< DWORD 1 539 struct 540 { 541 uint32_t Skiprawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< SkipRawDistortion 542 uint32_t Interrawdistortion : __CODEGEN_BITFIELD(16, 31) ; //!< InterRawDistortion 543 }; 544 uint32_t Value; 545 } DW1; 546 union 547 { 548 //!< DWORD 2 549 struct 550 { 551 uint32_t Bestintrarawdistortion : __CODEGEN_BITFIELD( 0, 15) ; //!< BestIntraRawDistortion 552 uint32_t IntermbmodeChromaPredictionMode : __CODEGEN_BITFIELD(16, 17) ; //!< INTERMBMODECHROMA_PREDICTION_MODE 553 uint32_t Intrambmode : __CODEGEN_BITFIELD(18, 19) ; //!< INTRAMBMODE 554 uint32_t Intrambflag : __CODEGEN_BITFIELD(20, 20) ; //!< INTRAMBFLAG 555 uint32_t Lastmbflag : __CODEGEN_BITFIELD(21, 21) ; //!< LASTMBFLAG 556 uint32_t CoefficientClampOccurred : __CODEGEN_BITFIELD(22, 22) ; //!< Coefficient Clamp Occurred 557 uint32_t ConformanceViolation : __CODEGEN_BITFIELD(23, 23) ; //!< Conformance Violation 558 uint32_t Submbpredmode : __CODEGEN_BITFIELD(24, 31) ; //!< SubMbPredMode 559 }; 560 uint32_t Value; 561 } DW2; 562 union 563 { 564 //!< DWORD 3 565 struct 566 { 567 uint32_t Lumaintramode0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[0] 568 uint32_t Lumaintramode1 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[1] 569 }; 570 uint32_t Value; 571 } DW3; 572 union 573 { 574 //!< DWORD 4 575 struct 576 { 577 uint32_t Lumaintramode2 : __CODEGEN_BITFIELD( 0, 15) ; //!< LumaIntraMode[2] 578 uint32_t Lumaintramode3 : __CODEGEN_BITFIELD(16, 31) ; //!< LumaIntraMode[3] 579 }; 580 uint32_t Value; 581 } DW4; 582 VDENC_Delta_MV_XY_CMD DeltaMv0 ; //!< Delta MV0 583 VDENC_Delta_MV_XY_CMD DeltaMv1 ; //!< Delta MV1 584 union 585 { 586 //!< DWORD 13 587 struct 588 { 589 uint32_t FwdRefids : __CODEGEN_BITFIELD( 0, 15) ; //!< FWD REFIDs 590 uint32_t BwdRefids : __CODEGEN_BITFIELD(16, 31) ; //!< BWD REFIDs 591 }; 592 uint32_t Value; 593 } DW13; 594 union 595 { 596 //!< DWORD 14 597 struct 598 { 599 uint32_t QpY : __CODEGEN_BITFIELD( 0, 5) ; //!< QP_y 600 uint32_t MbBitCount : __CODEGEN_BITFIELD( 6, 18) ; //!< MB_Bit_Count 601 uint32_t MbHeaderCount : __CODEGEN_BITFIELD(19, 31) ; //!< MB_Header_Count 602 }; 603 uint32_t Value; 604 } DW14; 605 union 606 { 607 //!< DWORD 15 608 struct 609 { 610 uint32_t MbType : __CODEGEN_BITFIELD( 0, 4) ; //!< MB Type 611 uint32_t BlockCbp : __CODEGEN_BITFIELD( 5, 30) ; //!< Block CBP 612 uint32_t Skipmbflag : __CODEGEN_BITFIELD(31, 31) ; //!< SkipMbFlag 613 }; 614 uint32_t Value; 615 } DW15; 616 617 //! \name Local enumerations 618 619 //! \brief INTERMBMODECHROMA_PREDICTION_MODE 620 //! \details 621 //! This field indicates the InterMB Parition type for Inter MB. 622 //! <br>OR</br> 623 //! This field indicates Chroma Prediction Mode for Intra MB. 624 enum INTERMBMODECHROMA_PREDICTION_MODE 625 { 626 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED0 = 0, //!< 16x16 627 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED1 = 1, //!< 16x8 628 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED2 = 2, //!< 8x16 629 INTERMBMODECHROMA_PREDICTION_MODE_UNNAMED3 = 3, //!< 8x8 630 }; 631 632 //! \brief INTRAMBMODE 633 //! \details 634 //! This field indicates the Best Intra Partition. 635 enum INTRAMBMODE 636 { 637 INTRAMBMODE_UNNAMED0 = 0, //!< 16x16 638 INTRAMBMODE_UNNAMED1 = 1, //!< 8x8 639 INTRAMBMODE_UNNAMED2 = 2, //!< 4x4 640 }; 641 642 //! \brief INTRAMBFLAG 643 //! \details 644 //! This field specifies whether the current macroblock is an Intra (I) 645 //! macroblock. 646 enum INTRAMBFLAG 647 { 648 INTRAMBFLAG_INTER = 0, //!< inter macroblock 649 INTRAMBFLAG_INTRA = 1, //!< intra macroblock 650 }; 651 652 enum LASTMBFLAG 653 { 654 LASTMBFLAG_NOTLAST = 0, //!< The current MB is not the last MB in the current Slice. 655 LASTMBFLAG_LAST = 1, //!< The current MB is the last MB in the current Slice. 656 }; 657 658 //! \name Initializations 659 660 //! \brief Explicit member initialization function 661 VDENC_Mode_StreamOut_Data_CMD(); 662 663 static const size_t dwSize = 16; 664 static const size_t byteSize = 64; 665 }; 666 667 //! 668 //! \brief VDENC_Original_Uncompressed_Picture 669 //! \details 670 //! 671 //! 672 struct VDENC_Original_Uncompressed_Picture_CMD 673 { 674 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 675 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 676 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 677 678 //! \name Local enumerations 679 680 //! \name Initializations 681 682 //! \brief Explicit member initialization function 683 VDENC_Original_Uncompressed_Picture_CMD(); 684 685 static const size_t dwSize = 3; 686 static const size_t byteSize = 12; 687 }; 688 689 //! 690 //! \brief VDENC_Reference_Picture 691 //! \details 692 //! 693 //! 694 struct VDENC_Reference_Picture_CMD 695 { 696 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 697 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 698 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 699 700 //! \name Local enumerations 701 702 //! \name Initializations 703 704 //! \brief Explicit member initialization function 705 VDENC_Reference_Picture_CMD(); 706 707 static const size_t dwSize = 3; 708 static const size_t byteSize = 12; 709 }; 710 711 //! 712 //! \brief VDENC_Row_Store_Scratch_Buffer_Picture 713 //! \details 714 //! 715 //! 716 struct VDENC_Row_Store_Scratch_Buffer_Picture_CMD 717 { 718 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 719 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 720 VDENC_Surface_Control_Bits_CMD BufferPictureFields ; //!< Buffer Picture Fields 721 722 //! \name Local enumerations 723 724 //! \name Initializations 725 726 //! \brief Explicit member initialization function 727 VDENC_Row_Store_Scratch_Buffer_Picture_CMD(); 728 729 static const size_t dwSize = 3; 730 static const size_t byteSize = 12; 731 }; 732 733 //! 734 //! \brief VDENC_Statistics_Streamout 735 //! \details 736 //! 737 //! 738 struct VDENC_Statistics_Streamout_CMD 739 { 740 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 741 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 742 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 743 744 //! \name Local enumerations 745 746 //! \name Initializations 747 748 //! \brief Explicit member initialization function 749 VDENC_Statistics_Streamout_CMD(); 750 751 static const size_t dwSize = 3; 752 static const size_t byteSize = 12; 753 }; 754 755 //! 756 //! \brief VDENC_Streamin_Data_Picture 757 //! \details 758 //! 759 //! 760 struct VDENC_Streamin_Data_Picture_CMD 761 { 762 VDENC_64B_Aligned_Lower_Address_CMD LowerAddress ; //!< Lower Address 763 VDENC_64B_Aligned_Upper_Address_CMD UpperAddress ; //!< Upper Address 764 VDENC_Surface_Control_Bits_CMD PictureFields ; //!< Picture Fields 765 766 //! \name Local enumerations 767 768 //! \name Initializations 769 770 //! \brief Explicit member initialization function 771 VDENC_Streamin_Data_Picture_CMD(); 772 773 static const size_t dwSize = 3; 774 static const size_t byteSize = 12; 775 }; 776 777 //! 778 //! \brief VDENC_STREAMIN_STATE 779 //! \details 780 //! 781 //! 782 struct VDENC_STREAMIN_STATE_CMD 783 { 784 union 785 { 786 //!< DWORD 0 787 struct 788 { 789 uint32_t RegionOfInterestRoiSelection : __CODEGEN_BITFIELD( 0, 7) ; //!< Region of Interest (ROI) Selection 790 uint32_t Forceintra : __CODEGEN_BITFIELD( 8, 8) ; //!< FORCEINTRA 791 uint32_t Forceskip : __CODEGEN_BITFIELD( 9, 9) ; //!< FORCESKIP 792 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 793 }; 794 uint32_t Value; 795 } DW0; 796 union 797 { 798 //!< DWORD 1 799 struct 800 { 801 uint32_t Qpprimey : __CODEGEN_BITFIELD( 0, 7) ; //!< QPPRIMEY 802 uint32_t Targetsizeinword : __CODEGEN_BITFIELD( 8, 15) ; //!< TargetSizeInWord 803 uint32_t Maxsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< MaxSizeInWord 804 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 805 }; 806 uint32_t Value; 807 } DW1; 808 union 809 { 810 //!< DWORD 2 811 struct 812 { 813 uint32_t FwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Fwd Predictor.X 814 uint32_t FwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Fwd Predictor.Y 815 }; 816 uint32_t Value; 817 } DW2; 818 union 819 { 820 //!< DWORD 3 821 struct 822 { 823 uint32_t BwdPredictorX : __CODEGEN_BITFIELD( 0, 15) ; //!< Bwd Predictor.X 824 uint32_t BwdPredictorY : __CODEGEN_BITFIELD(16, 31) ; //!< Bwd Predictor.Y 825 }; 826 uint32_t Value; 827 } DW3; 828 union 829 { 830 //!< DWORD 4 831 struct 832 { 833 uint32_t FwdRefid0 : __CODEGEN_BITFIELD( 0, 3) ; //!< Fwd RefID0 834 uint32_t BwdRefid0 : __CODEGEN_BITFIELD( 4, 7) ; //!< Bwd RefID0 835 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 836 }; 837 uint32_t Value; 838 } DW4; 839 840 uint32_t Reserved160[11]; //!< Reserved 841 842 843 //! \name Local enumerations 844 845 //! \brief FORCEINTRA 846 //! \details 847 //! This field specifies whether current macroblock should be coded as an 848 //! intra macroblock. 849 //! It is illegal to enable both ForceSkip and ForceIntra for 850 //! the same macroblock. 851 //! This should be disabled if Rolling-I is enabled in the 852 //! VDEnc Image State. 853 enum FORCEINTRA 854 { 855 FORCEINTRA_DISABLE = 0, //!< VDEnc determined macroblock type 856 FORCEINTRA_ENABLE = 1, //!< Force to be coded as an intra macroblock 857 }; 858 859 //! \brief FORCESKIP 860 //! \details 861 //! This field specifies whether current macroblock should be coded as a 862 //! skipped macroblock. 863 //! It is illegal to enable both ForceSkip and ForceIntra for 864 //! the same macroblock. 865 //! This should be disabled if Rolling-I is enabled in the 866 //! VDEnc Image State. 867 //! It is illegal to enable ForceSkip for I-Frames. 868 enum FORCESKIP 869 { 870 FORCESKIP_DISABLE = 0, //!< VDEnc determined macroblock type 871 FORCESKIP_ENABLE = 1, //!< Force to be coded as a skipped macroblock 872 }; 873 874 //! \brief QPPRIMEY 875 //! \details 876 //! Quantization parameter for Y. 877 enum QPPRIMEY 878 { 879 QPPRIMEY_UNNAMED0 = 0, //!< No additional details 880 QPPRIMEY_UNNAMED51 = 51, //!< No additional details 881 }; 882 883 //! \name Initializations 884 885 //! \brief Explicit member initialization function 886 VDENC_STREAMIN_STATE_CMD(); 887 888 static const size_t dwSize = 16; 889 static const size_t byteSize = 64; 890 }; 891 892 //! 893 //! \brief VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT 894 //! \details 895 //! 896 //! 897 struct VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD 898 { 899 union 900 { 901 //!< DWORD 0 902 struct 903 { 904 uint32_t SumSadHaarForBestModeDecision ; //!< Sum sad\haar for best mode decision 905 }; 906 uint32_t Value; 907 } DW0; 908 union 909 { 910 //!< DWORD 1 911 struct 912 { 913 uint32_t IntraCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Intra CU count normalized 914 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 915 }; 916 uint32_t Value; 917 } DW1; 918 union 919 { 920 //!< DWORD 2 921 struct 922 { 923 uint32_t NonSkipInterCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Non-skip Inter CU count normalized 924 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 925 }; 926 uint32_t Value; 927 } DW2; 928 union 929 { 930 //!< DWORD 3 931 struct 932 { 933 uint32_t SegmentMapCount0 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 0 934 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 935 }; 936 uint32_t Value; 937 } DW3; 938 union 939 { 940 //!< DWORD 4 941 struct 942 { 943 uint32_t SegmentMapCount1 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 1 944 uint32_t Reserved148 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 945 }; 946 uint32_t Value; 947 } DW4; 948 union 949 { 950 //!< DWORD 5 951 struct 952 { 953 uint32_t SegmentMapCount2 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 2 954 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 955 }; 956 uint32_t Value; 957 } DW5; 958 union 959 { 960 //!< DWORD 6 961 struct 962 { 963 uint32_t SegmentMapCount3 : __CODEGEN_BITFIELD( 0, 19) ; //!< segment map count 3 964 uint32_t Reserved212 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 965 }; 966 uint32_t Value; 967 } DW6; 968 union 969 { 970 //!< DWORD 7 971 struct 972 { 973 uint32_t MvXGlobalMeSample025X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 0 (.25x,.25x) 974 uint32_t MvYGlobalMeSample025X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 0 (.25x,.25x) 975 }; 976 uint32_t Value; 977 } DW7; 978 union 979 { 980 //!< DWORD 8 981 struct 982 { 983 uint32_t MvXGlobalMeSample125X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 1 (.25x,.25x) 984 uint32_t MvYGlobalMeSample125X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 1 (.25x,.25x) 985 }; 986 uint32_t Value; 987 } DW8; 988 union 989 { 990 //!< DWORD 9 991 struct 992 { 993 uint32_t MvXGlobalMeSample225X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 2 (.25x,.25x) 994 uint32_t MvYGlobalMeSample225X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 2 (.25x,.25x) 995 }; 996 uint32_t Value; 997 } DW9; 998 union 999 { 1000 //!< DWORD 10 1001 struct 1002 { 1003 uint32_t MvXGlobalMeSample325X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 3 (.25x,.25x) 1004 uint32_t MvYGlobalMeSample325X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 3 (.25x,.25x) 1005 }; 1006 uint32_t Value; 1007 } DW10; 1008 union 1009 { 1010 //!< DWORD 11 1011 struct 1012 { 1013 uint32_t MvXGlobalMeSample425X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 4 (.25x,.25x) 1014 uint32_t MvYGlobalMeSample425X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 4 (.25x,.25x) 1015 }; 1016 uint32_t Value; 1017 } DW11; 1018 union 1019 { 1020 //!< DWORD 12 1021 struct 1022 { 1023 uint32_t MvXGlobalMeSample525X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 5 (.25x,.25x) 1024 uint32_t MvYGlobalMeSample525X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 5 (.25x,.25x) 1025 }; 1026 uint32_t Value; 1027 } DW12; 1028 union 1029 { 1030 //!< DWORD 13 1031 struct 1032 { 1033 uint32_t MvXGlobalMeSample625X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 6 (.25x,.25x) 1034 uint32_t MvYGlobalMeSample625X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 6 (.25x,.25x) 1035 }; 1036 uint32_t Value; 1037 } DW13; 1038 union 1039 { 1040 //!< DWORD 14 1041 struct 1042 { 1043 uint32_t MvXGlobalMeSample725X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 7 (.25x,.25x) 1044 uint32_t MvYGlobalMeSample725X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 7 (.25x,.25x) 1045 }; 1046 uint32_t Value; 1047 } DW14; 1048 union 1049 { 1050 //!< DWORD 15 1051 struct 1052 { 1053 uint32_t MvXGlobalMeSample825X25X : __CODEGEN_BITFIELD( 0, 15) ; //!< MV.x Global ME sample 8 (.25x,.25x) 1054 uint32_t MvYGlobalMeSample825X25X : __CODEGEN_BITFIELD(16, 31) ; //!< MV.y Global ME sample 8 (.25x,.25x) 1055 }; 1056 uint32_t Value; 1057 } DW15; 1058 union 1059 { 1060 //!< DWORD 16 1061 struct 1062 { 1063 uint32_t RefidForGlobalmeSample0 : __CODEGEN_BITFIELD( 0, 1) ; //!< RefID for GlobalME sample 0 1064 uint32_t RefidForGlobalmeSample18 : __CODEGEN_BITFIELD( 2, 17) ; //!< RefID for GlobalME sample 1-8 1065 uint32_t Reserved530 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 1066 }; 1067 uint32_t Value; 1068 } DW16; 1069 union 1070 { 1071 //!< DWORD 17 1072 struct 1073 { 1074 uint32_t PaletteCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< Palette CU Count Normalized 1075 uint32_t Reserved564 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1076 }; 1077 uint32_t Value; 1078 } DW17; 1079 union 1080 { 1081 //!< DWORD 18 1082 struct 1083 { 1084 uint32_t IbcCuCountNormalized : __CODEGEN_BITFIELD( 0, 19) ; //!< IBC CU Count Normalized 1085 uint32_t Reserved596 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1086 }; 1087 uint32_t Value; 1088 } DW18; 1089 union 1090 { 1091 //!< DWORD 19 1092 struct 1093 { 1094 uint32_t NumberOfSecondaryColorsChannel1 : __CODEGEN_BITFIELD( 0, 15) ; //!< Number of secondary colors (Channel1) 1095 uint32_t NumberOfPrimaryColorsChannel0 : __CODEGEN_BITFIELD(16, 31) ; //!< Number of primary colors (Channel0) 1096 }; 1097 uint32_t Value; 1098 } DW19; 1099 union 1100 { 1101 //!< DWORD 20 1102 struct 1103 { 1104 uint32_t NumberOfSecondaryColorsChannel2 : __CODEGEN_BITFIELD( 0, 15) ; //!< Number of secondary colors (Channel2) 1105 uint32_t Reserved656 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1106 }; 1107 uint32_t Value; 1108 } DW20; 1109 union 1110 { 1111 //!< DWORD 21 1112 struct 1113 { 1114 uint32_t Reserved672 ; //!< Reserved 1115 }; 1116 uint32_t Value; 1117 } DW21; 1118 union 1119 { 1120 //!< DWORD 22 1121 struct 1122 { 1123 uint32_t PositionOfTimerExpiration : __CODEGEN_BITFIELD( 0, 15) ; //!< Position of Timer expiration 1124 uint32_t TimerExpireStatus : __CODEGEN_BITFIELD(16, 16) ; //!< Timer Expire status 1125 uint32_t Reserved721 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1126 }; 1127 uint32_t Value; 1128 } DW22; 1129 union 1130 { 1131 //!< DWORD 23 1132 struct 1133 { 1134 uint32_t LocationOfPanic : __CODEGEN_BITFIELD( 0, 15) ; //!< Location of panic 1135 uint32_t PanicDetected : __CODEGEN_BITFIELD(16, 16) ; //!< Panic detected 1136 uint32_t Reserved753 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1137 }; 1138 uint32_t Value; 1139 } DW23; 1140 1141 uint32_t Reserved768[5]; //!< Reserved 1142 1143 union 1144 { 1145 //!< DWORD 29 1146 struct 1147 { 1148 uint32_t SumSadHaarForBestModeDecisionBottomHalfPopulation ; //!< Sum sad\haar for best mode decision bottom half population 1149 }; 1150 uint32_t Value; 1151 } DW29; 1152 union 1153 { 1154 //!< DWORD 30 1155 struct 1156 { 1157 uint32_t SumSadHaarForBestModeDecisionTopHalfPopulation ; //!< Sum sad\haar for best mode decision top half population 1158 }; 1159 uint32_t Value; 1160 } DW30; 1161 union 1162 { 1163 //!< DWORD 31 1164 struct 1165 { 1166 uint32_t SumTopHalfPopulationOccurrences : __CODEGEN_BITFIELD( 0, 15) ; //!< Sum top half population occurrences 1167 uint32_t SumBottomHalfPopulationOccurrences : __CODEGEN_BITFIELD(16, 31) ; //!< Sum bottom half population occurrences 1168 }; 1169 uint32_t Value; 1170 } DW31; 1171 1172 //! \name Local enumerations 1173 1174 //! \name Initializations 1175 1176 //! \brief Explicit member initialization function 1177 VDENC_HEVC_VP9_FRAME_BASED_STATISTICS_STREAMOUT_CMD(); 1178 1179 static const size_t dwSize = 32; 1180 static const size_t byteSize = 128; 1181 }; 1182 1183 //! 1184 //! \brief VDENC_HEVC_VP9_STREAMIN_STATE 1185 //! \details 1186 //! For the NumMergeCandidate paramaters [64x64/32x32/16x16/8x8], only the 1187 //! following configurations are valid. 1188 //! Normal Mode without force mv or force intra: 4321 [64x64 --> 16x16]. 1189 //! Speed Mode without force mv or force intra: 2220, 2110, 1210, 2200, 1110 1190 //! [64x64 --> 16x16]. 1191 //! 1192 struct VDENC_HEVC_VP9_STREAMIN_STATE_CMD 1193 { 1194 union 1195 { 1196 //!< DWORD 0 1197 struct 1198 { 1199 uint32_t Roi32X32016X1603 : __CODEGEN_BITFIELD( 0, 7) ; //!< ROI 32x32_0 16x16_03 1200 uint32_t Maxtusize : __CODEGEN_BITFIELD( 8, 9) ; //!< MaxTUSize 1201 uint32_t Maxcusize : __CODEGEN_BITFIELD(10, 11) ; //!< MaxCUSize 1202 uint32_t Numimepredictors : __CODEGEN_BITFIELD(12, 15) ; //!< NUMIMEPREDICTORS 1203 uint32_t PuType32X32016X1603 : __CODEGEN_BITFIELD(24, 31) ; //!< PU Type 32x32_0 16x16_03 1204 }; 1205 uint32_t Value; 1206 } DW0; 1207 union 1208 { 1209 //!< DWORD 1 1210 struct 1211 { 1212 uint32_t ForceMvX32X32016X160 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_0 1213 uint32_t ForceMvY32X32016X160 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_0 1214 }; 1215 uint32_t Value; 1216 } DW1; 1217 union 1218 { 1219 //!< DWORD 2 1220 struct 1221 { 1222 uint32_t ForceMvX32X32016X161 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_1 1223 uint32_t ForceMvY32X32016X161 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_1 1224 }; 1225 uint32_t Value; 1226 } DW2; 1227 union 1228 { 1229 //!< DWORD 3 1230 struct 1231 { 1232 uint32_t ForceMvX32X32016X162 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_2 1233 uint32_t ForceMvY32X32016X162 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_2 1234 }; 1235 uint32_t Value; 1236 } DW3; 1237 union 1238 { 1239 //!< DWORD 4 1240 struct 1241 { 1242 uint32_t ForceMvX32X32016X163 : __CODEGEN_BITFIELD( 0, 15) ; //!< force_mv.x 32x32_0 16x16_3 1243 uint32_t ForceMvY32X32016X163 : __CODEGEN_BITFIELD(16, 31) ; //!< force_mv.y 32x32_0 16x16_3 1244 }; 1245 uint32_t Value; 1246 } DW4; 1247 union 1248 { 1249 //!< DWORD 5 1250 struct 1251 { 1252 uint32_t Reserved160 ; //!< Reserved 1253 }; 1254 uint32_t Value; 1255 } DW5; 1256 union 1257 { 1258 //!< DWORD 6 1259 struct 1260 { 1261 uint32_t ForceMvRefidx32X32016X160 : __CODEGEN_BITFIELD( 0, 3) ; //!< force_mv refidx 32x32_0 16x16_0 1262 uint32_t ForceMvRefidx32X32016X1613 : __CODEGEN_BITFIELD( 4, 15) ; //!< force_mv refidx 32x32_0 16x16_1-3 1263 uint32_t Nummergecandidatecu8X8 : __CODEGEN_BITFIELD(16, 19) ; //!< NumMergeCandidateCU8x8 1264 uint32_t Nummergecandidatecu16X16 : __CODEGEN_BITFIELD(20, 23) ; //!< NumMergeCandidateCU16x16 1265 uint32_t Nummergecandidatecu32X32 : __CODEGEN_BITFIELD(24, 27) ; //!< NumMergeCandidateCU32x32 1266 uint32_t Nummergecandidatecu64X64 : __CODEGEN_BITFIELD(28, 31) ; //!< NumMergeCandidateCU64x64 1267 }; 1268 uint32_t Value; 1269 } DW6; 1270 union 1271 { 1272 //!< DWORD 7 1273 struct 1274 { 1275 uint32_t Segid32X32016X1603Vp9Only : __CODEGEN_BITFIELD( 0, 15) ; //!< SegID 32x32_0 16x16_03 (VP9 only) 1276 uint32_t QpEn32X32016X1603 : __CODEGEN_BITFIELD(16, 19) ; //!< QP_En 32x32_0 16x16_03 1277 uint32_t SegidEnable : __CODEGEN_BITFIELD(20, 20) ; //!< SegID Enable 1278 uint32_t Reserved245 : __CODEGEN_BITFIELD(21, 22) ; //!< Reserved 1279 uint32_t ForceRefidEnable32X320 : __CODEGEN_BITFIELD(23, 23) ; //!< Force Refid Enable (32x32_0) 1280 uint32_t ImePredictorRefidSelect0332X320 : __CODEGEN_BITFIELD(24, 31) ; //!< IME predictor/refid Select0-3 32x32_0 1281 }; 1282 uint32_t Value; 1283 } DW7; 1284 union 1285 { 1286 //!< DWORD 8 1287 struct 1288 { 1289 uint32_t ImePredictor0X32X320 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_0 1290 uint32_t ImePredictor0Y32X320 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_0 1291 }; 1292 uint32_t Value; 1293 } DW8; 1294 union 1295 { 1296 //!< DWORD 9 1297 struct 1298 { 1299 uint32_t ImePredictor0X32X321 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_1 1300 uint32_t ImePredictor0Y32X321 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_1 1301 }; 1302 uint32_t Value; 1303 } DW9; 1304 union 1305 { 1306 //!< DWORD 10 1307 struct 1308 { 1309 uint32_t ImePredictor0X32X322 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_2 1310 uint32_t ImePredictor0Y32X322 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_2 1311 }; 1312 uint32_t Value; 1313 } DW10; 1314 union 1315 { 1316 //!< DWORD 11 1317 struct 1318 { 1319 uint32_t ImePredictor0X32X323 : __CODEGEN_BITFIELD( 0, 15) ; //!< ime_predictor0.x 32x32_3 1320 uint32_t ImePredictor0Y32X323 : __CODEGEN_BITFIELD(16, 31) ; //!< ime_predictor0.y 32x32_3 1321 }; 1322 uint32_t Value; 1323 } DW11; 1324 union 1325 { 1326 //!< DWORD 12 1327 struct 1328 { 1329 uint32_t ImePredictor0Refidx32X320 : __CODEGEN_BITFIELD( 0, 3) ; //!< ime_predictor0 refidx 32x32_0 1330 uint32_t ImePredictor13Refidx32X3213 : __CODEGEN_BITFIELD( 4, 15) ; //!< ime_predictor1-3 refidx 32x32_1-3 1331 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1332 }; 1333 uint32_t Value; 1334 } DW12; 1335 union 1336 { 1337 //!< DWORD 13 1338 struct 1339 { 1340 uint32_t Panicmodelcuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< PanicModeLCUThreshold 1341 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1342 }; 1343 uint32_t Value; 1344 } DW13; 1345 union 1346 { 1347 //!< DWORD 14 1348 struct 1349 { 1350 uint32_t ForceQpValue16X160 : __CODEGEN_BITFIELD( 0, 7) ; //!< Force QP Value 16x16_0 1351 uint32_t ForceQpValue16X161 : __CODEGEN_BITFIELD( 8, 15) ; //!< Force QP Value 16x16_1 1352 uint32_t ForceQpValue16X162 : __CODEGEN_BITFIELD(16, 23) ; //!< Force QP Value 16x16_2 1353 uint32_t ForceQpValue16X163 : __CODEGEN_BITFIELD(24, 31) ; //!< Force QP Value 16x16_3 1354 }; 1355 uint32_t Value; 1356 } DW14; 1357 union 1358 { 1359 //!< DWORD 15 1360 struct 1361 { 1362 uint32_t Reserved480 ; //!< Reserved 1363 }; 1364 uint32_t Value; 1365 } DW15; 1366 1367 //! \name Local enumerations 1368 1369 //! \brief NUMIMEPREDICTORS 1370 //! \details 1371 //! <p>This parameter specifes the number of IME predictors to be processed 1372 //! in stage3 IME.</p> 1373 //! <p></p> 1374 enum NUMIMEPREDICTORS 1375 { 1376 NUMIMEPREDICTORS_UNNAMED0 = 0, //!< No additional details 1377 NUMIMEPREDICTORS_UNNAMED4 = 4, //!< No additional details 1378 NUMIMEPREDICTORS_UNNAMED8 = 8, //!< No additional details 1379 NUMIMEPREDICTORS_UNNAMED12 = 12, //!< No additional details 1380 }; 1381 1382 //! \name Initializations 1383 1384 //! \brief Explicit member initialization function 1385 VDENC_HEVC_VP9_STREAMIN_STATE_CMD(); 1386 1387 static const size_t dwSize = 16; 1388 static const size_t byteSize = 64; 1389 }; 1390 1391 //! 1392 //! \brief VDENC_Surface_State_Fields 1393 //! \details 1394 //! 1395 //! 1396 struct VDENC_Surface_State_Fields_CMD 1397 { 1398 union 1399 { 1400 //!< DWORD 0 1401 struct 1402 { 1403 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< Cr(V)/Cb(U) Pixel Offset V Direction 1404 uint32_t SurfaceFormatByteSwizzle : __CODEGEN_BITFIELD( 2, 2) ; //!< Surface Format Byte Swizzle 1405 uint32_t ColorSpaceSelection : __CODEGEN_BITFIELD( 3, 3) ; //!< Color space selection 1406 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1407 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1408 }; 1409 uint32_t Value; 1410 } DW0; 1411 union 1412 { 1413 //!< DWORD 1 1414 struct 1415 { 1416 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 1417 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 1418 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< HALF_PITCH_FOR_CHROMA 1419 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 1420 uint32_t ChromaDownsampleFilterControl : __CODEGEN_BITFIELD(20, 22) ; //!< Chroma Downsample Filter Control 1421 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 26) ; //!< Reserved 1422 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 1423 }; 1424 uint32_t Value; 1425 } DW1; 1426 union 1427 { 1428 //!< DWORD 2 1429 struct 1430 { 1431 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) 1432 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1433 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for U(Cb) 1434 uint32_t Reserved95 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1435 }; 1436 uint32_t Value; 1437 } DW2; 1438 union 1439 { 1440 //!< DWORD 3 1441 struct 1442 { 1443 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 15) ; //!< Y Offset for V(Cr) 1444 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V(Cr) 1445 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1446 }; 1447 uint32_t Value; 1448 } DW3; 1449 1450 //! \name Local enumerations 1451 1452 //! \brief TILE_WALK 1453 //! \details 1454 //! (This field must be set to 1: TILEWALK_YMAJOR.) This field specifies the 1455 //! type of memory tiling 1456 //! (XMajor or YMajor) employed to tile this surface. See Memory 1457 //! Interface Functions for details 1458 //! on memory tiling and restrictions.This field is ignored when the 1459 //! surface is linear. Internally 1460 //! H/W always treats this as set to 1 for all VDEnc usage. 1461 enum TILE_WALK 1462 { 1463 TILE_WALK_XMAJOR = 0, //!< TILEWALK_XMAJOR 1464 TILE_WALK_YMAJOR = 1, //!< TILEWALK_YMAJOR 1465 }; 1466 1467 //! \brief TILED_SURFACE 1468 //! \details 1469 //! (This field must be set to TRUE: Tiled.) This field specifies whether 1470 //! the surface is tiled. 1471 //! This field is ignored by VDEnc usage. 1472 enum TILED_SURFACE 1473 { 1474 TILED_SURFACE_FALSE = 0, //!< Linear 1475 TILED_SURFACE_TRUE = 1, //!< Tiled 1476 }; 1477 1478 //! \brief HALF_PITCH_FOR_CHROMA 1479 //! \details 1480 //! (This field must be set to Disable.) This field indicates that the 1481 //! chroma plane(s) will use a pitch equal 1482 //! to half the value specified in the Surface Pitch field. This field 1483 //! is only used for PLANAR surface formats. 1484 //! This field is igored by VDEnc (unless we support YV12). 1485 enum HALF_PITCH_FOR_CHROMA 1486 { 1487 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< No additional details 1488 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< No additional details 1489 }; 1490 1491 //! \brief SURFACE_FORMAT 1492 //! \details 1493 //! Specifies the format of the surface. 1494 enum SURFACE_FORMAT 1495 { 1496 SURFACE_FORMAT_YUV422 = 0, //!< YUYV/YUY2 (8:8:8:8 MSB V0 Y1 U0 Y0) 1497 SURFACE_FORMAT_RGBA4444 = 1, //!< RGBA 32-bit 4:4:4:4 packed (8:8:8:8 MSB-X:B:G:R) 1498 SURFACE_FORMAT_YUV444 = 2, //!< YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-A:Y:U:V) 1499 SURFACE_FORMAT_Y8UNORM = 3, //!< No additional details 1500 SURFACE_FORMAT_PLANAR_420_8 = 4, //!< (NV12, IMC1,2,3,4, YV12) 1501 SURFACE_FORMAT_YCRCB_SWAPY_422 = 5, //!< UYVY (8:8:8:8 MSB Y1 V0 Y0 U0) 1502 SURFACE_FORMAT_YCRCB_SWAPUV_422 = 6, //!< YVYU (8:8:8:8 MSB U0 Y1 V0 Y0) 1503 SURFACE_FORMAT_YCRCB_SWAPUVY_422 = 7, //!< VYUY (8:8:8:8 MSB Y1 U0 Y0 V0) 1504 SURFACE_FORMAT_P010 = 8, //!< 10 - bit planar 420 (Tile - Y / Linear / Tile - X) 1505 SURFACE_FORMAT_RGBA_10_10_10_2 = 9, //!< Need to convert to YUV. 2 bits Alpha, 10 bits R 10 bits G 10 bits B 1506 SURFACE_FORMAT_Y410 = 10, //!< 10 bit 4:4:4 packed 1507 SURFACE_FORMAT_NV21 = 11, //!< 8-bit, same as NV12 but UV interleave is reversed 1508 SURFACE_FORMAT_P010_VARIANT = 12, //!< >8 bit planar 420 with MSB together and LSB at an offset in x direction 1509 }; 1510 1511 //! \name Initializations 1512 1513 //! \brief Explicit member initialization function 1514 VDENC_Surface_State_Fields_CMD(); 1515 1516 static const size_t dwSize = 4; 1517 static const size_t byteSize = 16; 1518 }; 1519 1520 //! 1521 //! \brief VD_PIPELINE_FLUSH 1522 //! \details 1523 //! 1524 //! 1525 struct VD_PIPELINE_FLUSH_CMD 1526 { 1527 union 1528 { 1529 //!< DWORD 0 1530 struct 1531 { 1532 uint32_t DwordCountN : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_COUNT_N 1533 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1534 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1535 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1536 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1537 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1538 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1539 }; 1540 uint32_t Value; 1541 } DW0; 1542 union 1543 { 1544 //!< DWORD 1 1545 struct 1546 { 1547 uint32_t HevcPipelineDone : __CODEGEN_BITFIELD( 0, 0) ; //!< HEVC pipeline Done 1548 uint32_t VdencPipelineDone : __CODEGEN_BITFIELD( 1, 1) ; //!< VD-ENC pipeline Done 1549 uint32_t MflPipelineDone : __CODEGEN_BITFIELD( 2, 2) ; //!< MFL pipeline Done 1550 uint32_t MfxPipelineDone : __CODEGEN_BITFIELD( 3, 3) ; //!< MFX pipeline Done 1551 uint32_t VdCommandMessageParserDone : __CODEGEN_BITFIELD( 4, 4) ; //!< VD command/message parser Done 1552 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 1553 uint32_t HevcPipelineCommandFlush : __CODEGEN_BITFIELD(16, 16) ; //!< HEVC pipeline command flush 1554 uint32_t VdencPipelineCommandFlush : __CODEGEN_BITFIELD(17, 17) ; //!< VD-ENC pipeline command flush 1555 uint32_t MflPipelineCommandFlush : __CODEGEN_BITFIELD(18, 18) ; //!< MFL pipeline command flush 1556 uint32_t MfxPipelineCommandFlush : __CODEGEN_BITFIELD(19, 19) ; //!< MFX pipeline command flush 1557 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 1558 }; 1559 uint32_t Value; 1560 } DW1; 1561 1562 //! \name Local enumerations 1563 1564 //! \brief DWORD_COUNT_N 1565 //! \details 1566 //! Total Length - 2 1567 enum DWORD_COUNT_N 1568 { 1569 DWORD_COUNT_N_EXCLUDESDWORD_0 = 0, //!< No additional details 1570 }; 1571 1572 enum SUBOPCODEB 1573 { 1574 SUBOPCODEB_UNNAMED0 = 0, //!< No additional details 1575 }; 1576 1577 enum SUBOPCODEA 1578 { 1579 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 1580 }; 1581 1582 enum MEDIA_COMMAND_OPCODE 1583 { 1584 MEDIA_COMMAND_OPCODE_EXTENDEDCOMMAND = 15, //!< No additional details 1585 }; 1586 1587 enum PIPELINE 1588 { 1589 PIPELINE_MEDIA = 2, //!< No additional details 1590 }; 1591 1592 enum COMMAND_TYPE 1593 { 1594 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1595 }; 1596 1597 //! \name Initializations 1598 1599 //! \brief Explicit member initialization function 1600 VD_PIPELINE_FLUSH_CMD(); 1601 1602 static const size_t dwSize = 2; 1603 static const size_t byteSize = 8; 1604 }; 1605 1606 //! 1607 //! \brief VDENC_WEIGHTSOFFSETS_STATE 1608 //! \details 1609 //! 1610 //! 1611 struct VDENC_WEIGHTSOFFSETS_STATE_CMD 1612 { 1613 union 1614 { 1615 //!< DWORD 0 1616 struct 1617 { 1618 uint32_t DwLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DW_LENGTH 1619 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1620 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1621 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1622 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1623 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1624 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1625 }; 1626 uint32_t Value; 1627 } DW0; 1628 union 1629 { 1630 //!< DWORD 1 1631 struct 1632 { 1633 uint32_t WeightsForwardReference0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Weights Forward Reference0 1634 uint32_t OffsetForwardReference0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Offset Forward Reference0 1635 uint32_t WeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23) ; //!< Weights Forward Reference1 1636 uint32_t OffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31) ; //!< Offset Forward Reference1 1637 }; 1638 uint32_t Value; 1639 } DW1; 1640 union 1641 { 1642 //!< DWORD 2 1643 struct 1644 { 1645 uint32_t WeightsForwardReference2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Weights Forward Reference2 1646 uint32_t OffsetForwardReference2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Offset Forward Reference2 1647 uint32_t HevcVp9WeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23) ; //!< HEVC/VP9 Weights Backward Reference0 1648 uint32_t HevcVp9OffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31) ; //!< HEVC/VP9 Offset Backward Reference0 1649 }; 1650 uint32_t Value; 1651 } DW2; 1652 union 1653 { 1654 //!< DWORD 3 1655 struct 1656 { 1657 uint32_t HevcVp9WeightsForwardReference0 : __CODEGEN_BITFIELD( 0, 7) ; //!< HEVC/VP9 Weights Forward Reference0 1658 uint32_t HevcVp9OffsetForwardReference0 : __CODEGEN_BITFIELD( 8, 15) ; //!< HEVC/VP9 Offset Forward Reference0 1659 uint32_t HevcVp9WeightsForwardReference1 : __CODEGEN_BITFIELD(16, 23) ; //!< HEVC/VP9 Weights Forward Reference1 1660 uint32_t HevcVp9OffsetForwardReference1 : __CODEGEN_BITFIELD(24, 31) ; //!< HEVC/VP9 Offset Forward Reference1 1661 }; 1662 uint32_t Value; 1663 } DW3; 1664 union 1665 { 1666 //!< DWORD 4 1667 struct 1668 { 1669 uint32_t HevcVp9WeightsForwardReference2 : __CODEGEN_BITFIELD( 0, 7) ; //!< HEVC/VP9 Weights Forward Reference2 1670 uint32_t HevcVp9OffsetForwardReference2 : __CODEGEN_BITFIELD( 8, 15) ; //!< HEVC/VP9 Offset Forward Reference2 1671 uint32_t HevcVp9WeightsBackwardReference0 : __CODEGEN_BITFIELD(16, 23) ; //!< HEVC/VP9 Weights Backward Reference0 1672 uint32_t HevcVp9OffsetBackwardReference0 : __CODEGEN_BITFIELD(24, 31) ; //!< HEVC/VP9 Offset Backward Reference0 1673 }; 1674 uint32_t Value; 1675 } DW4; 1676 1677 //! \name Local enumerations 1678 1679 //! \brief DW_LENGTH 1680 //! \details 1681 //! Total Length - 2 1682 enum DW_LENGTH 1683 { 1684 DW_LENGTH_DWORDCOUNTN = 1, //!< Excludes DWord (0,1) 1685 }; 1686 1687 enum SUBOPB 1688 { 1689 SUBOPB_VDENCAVCWEIGHTSOFFSETSTATE = 8, //!< No additional details 1690 }; 1691 1692 enum SUBOPA 1693 { 1694 SUBOPA_UNNAMED0 = 0, //!< No additional details 1695 }; 1696 1697 enum OPCODE 1698 { 1699 OPCODE_VDENCPIPE = 1, //!< No additional details 1700 }; 1701 1702 enum PIPELINE 1703 { 1704 PIPELINE_MFXCOMMON = 2, //!< No additional details 1705 }; 1706 1707 enum COMMAND_TYPE 1708 { 1709 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1710 }; 1711 1712 //! \name Initializations 1713 1714 //! \brief Explicit member initialization function 1715 VDENC_WEIGHTSOFFSETS_STATE_CMD(); 1716 1717 static const size_t dwSize = 5; 1718 static const size_t byteSize = 20; 1719 }; 1720 1721 //! 1722 //! \brief VDENC_CONST_QPT_STATE 1723 //! \details 1724 //! This commands provides the tables for frame constants to the VDEnc HW. 1725 //! The specific parameter value is picked by the VDEnc HW based on the 1726 //! frame level QP. The QP Lambda array for costing (motion-vectors and mode 1727 //! costs) has 42 entires. Skip Threshold tables has 27 entries. 7 FTQ 1728 //! thresholds [0-6] are programmed using 4 sets of tables with 27 entires 1729 //! each. 1730 //! 1731 struct VDENC_CONST_QPT_STATE_CMD 1732 { 1733 union 1734 { 1735 //!< DWORD 0 1736 struct 1737 { 1738 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1739 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1740 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1741 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1742 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1743 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1744 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1745 }; 1746 uint32_t Value; 1747 } DW0; 1748 union { 1749 //!< DWORD 1..10 1750 struct { 1751 uint8_t QpLambdaArrayIndex[40]; //!< QP Lambda Array Index[n] 1752 }; 1753 uint32_t Value[10]; 1754 } DW1_10; 1755 union { 1756 //!< DWORD 11 1757 struct { 1758 uint32_t QpLambdaArrayIndex40 : __CODEGEN_BITFIELD(0, 7); 1759 uint32_t QpLambdaArrayIndex41 : __CODEGEN_BITFIELD(8, 15); 1760 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1761 }; 1762 uint32_t Value; 1763 } DW11; 1764 union { 1765 //!< DWORD 12..24 1766 struct { 1767 uint16_t SkipThresholdArrayIndex[26]; //!< Skip Threshold Array Index[n] 1768 }; 1769 uint32_t Value[13]; 1770 } DW12_24; 1771 union { 1772 //!< DWORD 25 1773 struct { 1774 uint32_t SkipThresholdArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1775 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1776 }; 1777 uint32_t Value; 1778 } DW25; 1779 union { 1780 //!< DWORD 26..38 1781 struct { 1782 uint16_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex[26]; //!< SIC Forward Transform Coeff Threshold Matrix0 Array Index[n] 1783 }; 1784 uint32_t Value[13]; 1785 } DW26_38; 1786 union { 1787 //!< DWORD 39 1788 struct { 1789 uint32_t SicForwardTransformCoeffThresholdMatrix0ArrayIndex26 : __CODEGEN_BITFIELD(0, 15); 1790 uint32_t Reserved : __CODEGEN_BITFIELD(16, 31); 1791 }; 1792 uint32_t Value; 1793 } DW39; 1794 union { 1795 //!< DWORD 40..45 1796 struct { 1797 uint8_t SicForwardTransformCoeffThresholdMatrix135ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix1/3/5 Array Index[n] 1798 }; 1799 uint32_t Value[6]; 1800 } DW40_45; 1801 union { 1802 //!< DWORD 46 1803 struct { 1804 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1805 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1806 uint32_t SicForwardTransformCoeffThresholdMatrix135ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1807 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1808 }; 1809 uint32_t Value; 1810 } DW46; 1811 union { 1812 //!< DWORD 47..52 1813 struct { 1814 uint8_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex[24]; //!< SIC Forward Transform Coeff Threshold Matrix2 Array Index[n] 1815 }; 1816 uint32_t Value[6]; 1817 } DW47_52; 1818 union { 1819 //!< DWORD 53 1820 struct { 1821 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1822 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1823 uint32_t SicForwardTransformCoeffThresholdMatrix2ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1824 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1825 }; 1826 uint32_t Value; 1827 } DW53; 1828 union { 1829 //!< DWORD 54..59 1830 struct { 1831 uint8_t SicForwardTransformCoeffThresholdMatrix46ArrayIndexN[24]; //!< SIC Forward Transform Coeff Threshold Matrix4/6 Array Index[n] 1832 }; 1833 uint32_t Value[6]; 1834 } DW54_59; 1835 union { 1836 //!< DWORD 60 1837 struct { 1838 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex24 : __CODEGEN_BITFIELD(0, 7); 1839 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex25 : __CODEGEN_BITFIELD(8, 15); 1840 uint32_t SicForwardTransformCoeffThresholdMatrix46ArrayIndex26 : __CODEGEN_BITFIELD(16, 23); 1841 uint32_t Reserved : __CODEGEN_BITFIELD(24, 31); 1842 }; 1843 uint32_t Value; 1844 } DW60; 1845 1846 //! \name Local enumerations 1847 1848 enum SUBOPB 1849 { 1850 SUBOPB_VDENCCONSTQPTSTATE = 6, //!< No additional details 1851 }; 1852 1853 enum SUBOPA 1854 { 1855 SUBOPA_UNNAMED0 = 0, //!< No additional details 1856 }; 1857 1858 enum OPCODE 1859 { 1860 OPCODE_VDENCPIPE = 1, //!< No additional details 1861 }; 1862 1863 enum PIPELINE 1864 { 1865 PIPELINE_MFXCOMMON = 2, //!< No additional details 1866 }; 1867 1868 enum COMMAND_TYPE 1869 { 1870 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1871 }; 1872 1873 //! \name Initializations 1874 1875 //! \brief Explicit member initialization function 1876 VDENC_CONST_QPT_STATE_CMD(); 1877 1878 static const size_t dwSize = 61; 1879 static const size_t byteSize = 244; 1880 }; 1881 1882 //! 1883 //! \brief VDENC_DS_REF_SURFACE_STATE 1884 //! \details 1885 //! This command specifies the surface state parameters for the downscaled 1886 //! reference surfaces. 1887 //! 1888 struct VDENC_DS_REF_SURFACE_STATE_CMD 1889 { 1890 union 1891 { 1892 //!< DWORD 0 1893 struct 1894 { 1895 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1896 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1897 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1898 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1899 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1900 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1901 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1902 }; 1903 uint32_t Value; 1904 } DW0; 1905 union 1906 { 1907 //!< DWORD 1 1908 struct 1909 { 1910 uint32_t Reserved32 ; //!< Reserved 1911 }; 1912 uint32_t Value; 1913 } DW1; 1914 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 1915 VDENC_Surface_State_Fields_CMD Dwords69 ; //!< Dwords 6..9 1916 1917 //! \name Local enumerations 1918 1919 enum SUBOPB 1920 { 1921 SUBOPB_VDENCDSREFSURFACESTATE = 3, //!< No additional details 1922 }; 1923 1924 enum SUBOPA 1925 { 1926 SUBOPA_UNNAMED0 = 0, //!< No additional details 1927 }; 1928 1929 enum OPCODE 1930 { 1931 OPCODE_VDENCPIPE = 1, //!< No additional details 1932 }; 1933 1934 enum PIPELINE 1935 { 1936 PIPELINE_MFXCOMMON = 2, //!< No additional details 1937 }; 1938 1939 enum COMMAND_TYPE 1940 { 1941 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1942 }; 1943 1944 //! \name Initializations 1945 1946 //! \brief Explicit member initialization function 1947 VDENC_DS_REF_SURFACE_STATE_CMD(); 1948 1949 static const size_t dwSize = 10; 1950 static const size_t byteSize = 40; 1951 }; 1952 1953 //! 1954 //! \brief VDENC_IMG_STATE 1955 //! \details 1956 //! This command programs the frame level parameters required by the VDEnc 1957 //! pipeline. 1958 //! 1959 struct VDENC_IMG_STATE_CMD 1960 { 1961 union 1962 { 1963 //!< DWORD 0 1964 struct 1965 { 1966 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1967 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1968 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 1969 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 1970 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 1971 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1972 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1973 }; 1974 uint32_t Value; 1975 } DW0; 1976 union 1977 { 1978 //!< DWORD 1 1979 struct 1980 { 1981 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1982 uint32_t BidirectionalMixDisable : __CODEGEN_BITFIELD( 2, 2) ; //!< BIDIRECTIONAL_MIX_DISABLE 1983 uint32_t VdencPerfmode : __CODEGEN_BITFIELD( 3, 3) ; //!< VDENC_PERFMODE 1984 uint32_t TimeBudgetOverflowCheck : __CODEGEN_BITFIELD( 4, 4) ; //!< TIME_BUDGET_OVERFLOW_CHECK 1985 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 5) ; //!< Reserved 1986 uint32_t VdencExtendedPakObjCmdEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 1987 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD( 7, 7) ; //!< TRANSFORM_8X8_FLAG 1988 uint32_t VdencL1CachePriority : __CODEGEN_BITFIELD( 8, 9) ; //!< VDENC_L1_CACHE_PRIORITY 1989 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1990 uint32_t LambdaValueForTrellis : __CODEGEN_BITFIELD(16, 31) ; //!< Lambda value for Trellis 1991 }; 1992 uint32_t Value; 1993 } DW1; 1994 union 1995 { 1996 //!< DWORD 2 1997 struct 1998 { 1999 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 2000 uint32_t BidirectionalWeight : __CODEGEN_BITFIELD(16, 21) ; //!< BIDIRECTIONAL_WEIGHT 2001 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 27) ; //!< Reserved 2002 uint32_t UnidirectionalMixDisable : __CODEGEN_BITFIELD(28, 28) ; //!< Unidirectional Mix Disable 2003 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2004 }; 2005 uint32_t Value; 2006 } DW2; 2007 union 2008 { 2009 //!< DWORD 3 2010 struct 2011 { 2012 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 2013 uint32_t PictureWidth : __CODEGEN_BITFIELD(16, 31) ; //!< Picture Width 2014 }; 2015 uint32_t Value; 2016 } DW3; 2017 union 2018 { 2019 //!< DWORD 4 2020 struct 2021 { 2022 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 2023 uint32_t SubPelMode : __CODEGEN_BITFIELD(12, 13) ; //!< SUB_PEL_MODE 2024 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 16) ; //!< Reserved 2025 uint32_t ForwardTransformSkipCheckEnable : __CODEGEN_BITFIELD(17, 17) ; //!< FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2026 uint32_t BmeDisableForFbrMessage : __CODEGEN_BITFIELD(18, 18) ; //!< BME_DISABLE_FOR_FBR_MESSAGE 2027 uint32_t BlockBasedSkipEnabled : __CODEGEN_BITFIELD(19, 19) ; //!< BLOCK_BASED_SKIP_ENABLED 2028 uint32_t InterSadMeasureAdjustment : __CODEGEN_BITFIELD(20, 21) ; //!< INTER_SAD_MEASURE_ADJUSTMENT 2029 uint32_t IntraSadMeasureAdjustment : __CODEGEN_BITFIELD(22, 23) ; //!< INTRA_SAD_MEASURE_ADJUSTMENT 2030 uint32_t SubMacroblockSubPartitionMask : __CODEGEN_BITFIELD(24, 30) ; //!< SUB_MACROBLOCK_SUB_PARTITION_MASK 2031 uint32_t BlockBasedSkipType : __CODEGEN_BITFIELD(31, 31) ; //!< BLOCK_BASED_SKIP_TYPE 2032 }; 2033 uint32_t Value; 2034 } DW4; 2035 union 2036 { 2037 //!< DWORD 5 2038 struct 2039 { 2040 uint32_t PictureHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Picture Height Minus One 2041 uint32_t CrePrefetchEnable : __CODEGEN_BITFIELD(16, 16) ; //!< CRE_PREFETCH_ENABLE 2042 uint32_t HmeRef1Disable : __CODEGEN_BITFIELD(17, 17) ; //!< HME_REF1_DISABLE 2043 uint32_t MbSliceThresholdValue : __CODEGEN_BITFIELD(18, 21) ; //!< MB Slice Threshold Value 2044 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 25) ; //!< Reserved 2045 uint32_t ConstrainedIntraPredictionFlag : __CODEGEN_BITFIELD(26, 26) ; //!< CONSTRAINED_INTRA_PREDICTION_FLAG 2046 uint32_t Reserved187 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 2047 uint32_t PictureType : __CODEGEN_BITFIELD(29, 30) ; //!< PICTURE_TYPE 2048 uint32_t Reserved191 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 2049 }; 2050 uint32_t Value; 2051 } DW5; 2052 union 2053 { 2054 //!< DWORD 6 2055 struct 2056 { 2057 uint32_t SliceMacroblockHeightMinusOne : __CODEGEN_BITFIELD( 0, 15) ; //!< Slice Macroblock Height Minus One 2058 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2059 }; 2060 uint32_t Value; 2061 } DW6; 2062 union 2063 { 2064 //!< DWORD 7 2065 struct 2066 { 2067 uint32_t Hme0XOffset : __CODEGEN_BITFIELD( 0, 7) ; //!< HME0 X Offset 2068 uint32_t Hme0YOffset : __CODEGEN_BITFIELD( 8, 15) ; //!< HME0 Y Offset 2069 uint32_t Hme1XOffset : __CODEGEN_BITFIELD(16, 23) ; //!< HME1 X Offset 2070 uint32_t Hme1YOffset : __CODEGEN_BITFIELD(24, 31) ; //!< HME1 Y Offset 2071 }; 2072 uint32_t Value; 2073 } DW7; 2074 union 2075 { 2076 //!< DWORD 8 2077 struct 2078 { 2079 uint32_t LumaIntraPartitionMask : __CODEGEN_BITFIELD( 0, 4) ; //!< LUMA_INTRA_PARTITION_MASK 2080 uint32_t NonSkipZeroMvCostAdded : __CODEGEN_BITFIELD( 5, 5) ; //!< Non Skip Zero MV Cost Added 2081 uint32_t NonSkipMbModeCostAdded : __CODEGEN_BITFIELD( 6, 6) ; //!< Non Skip MB Mode Cost Added 2082 uint32_t Reserved263 : __CODEGEN_BITFIELD( 7, 15) ; //!< Reserved 2083 uint32_t MvCostScalingFactor : __CODEGEN_BITFIELD(16, 17) ; //!< MV_COST_SCALING_FACTOR 2084 uint32_t BilinearFilterEnable : __CODEGEN_BITFIELD(18, 18) ; //!< BiLinear Filter Enable 2085 uint32_t Reserved275 : __CODEGEN_BITFIELD(19, 21) ; //!< Reserved 2086 uint32_t RefidCostModeSelect : __CODEGEN_BITFIELD(22, 22) ; //!< REFID_COST_MODE_SELECT 2087 uint32_t Reserved279 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 2088 }; 2089 uint32_t Value; 2090 } DW8; 2091 union 2092 { 2093 //!< DWORD 9 2094 struct 2095 { 2096 uint32_t Mode0Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 0 Cost 2097 uint32_t Mode1Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 1 Cost 2098 uint32_t Mode2Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 2 Cost 2099 uint32_t Mode3Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 3 Cost 2100 }; 2101 uint32_t Value; 2102 } DW9; 2103 union 2104 { 2105 //!< DWORD 10 2106 struct 2107 { 2108 uint32_t Mode4Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 4 Cost 2109 uint32_t Mode5Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 5 Cost 2110 uint32_t Mode6Cost : __CODEGEN_BITFIELD(16, 23) ; //!< Mode 6 Cost 2111 uint32_t Mode7Cost : __CODEGEN_BITFIELD(24, 31) ; //!< Mode 7 Cost 2112 }; 2113 uint32_t Value; 2114 } DW10; 2115 union 2116 { 2117 //!< DWORD 11 2118 struct 2119 { 2120 uint32_t Mode8Cost : __CODEGEN_BITFIELD( 0, 7) ; //!< Mode 8 Cost 2121 uint32_t Mode9Cost : __CODEGEN_BITFIELD( 8, 15) ; //!< Mode 9 Cost 2122 uint32_t RefIdCost : __CODEGEN_BITFIELD(16, 23) ; //!< RefID Cost 2123 uint32_t ChromaIntraModeCost : __CODEGEN_BITFIELD(24, 31) ; //!< Chroma Intra Mode Cost 2124 }; 2125 uint32_t Value; 2126 } DW11; 2127 union 2128 { 2129 //!< DWORD 12 2130 struct 2131 { 2132 uint32_t MvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 0 2133 uint32_t MvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 1 2134 uint32_t MvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 2 2135 uint32_t MvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 3 2136 }; 2137 uint32_t Value; 2138 } DW12; 2139 union 2140 { 2141 //!< DWORD 13 2142 struct 2143 { 2144 uint32_t MvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< MvCost 4 2145 uint32_t MvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< MvCost 5 2146 uint32_t MvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< MvCost 6 2147 uint32_t MvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< MvCost 7 2148 }; 2149 uint32_t Value; 2150 } DW13; 2151 union 2152 { 2153 //!< DWORD 14 2154 struct 2155 { 2156 uint32_t QpPrimeY : __CODEGEN_BITFIELD( 0, 7) ; //!< QpPrimeY 2157 uint32_t Reserved456 : __CODEGEN_BITFIELD( 8, 23) ; //!< Reserved 2158 uint32_t TargetSizeInWord : __CODEGEN_BITFIELD(24, 31) ; //!< TargetSizeInWord 2159 }; 2160 uint32_t Value; 2161 } DW14; 2162 union 2163 { 2164 //!< DWORD 15 2165 struct 2166 { 2167 uint32_t Reserved480 ; //!< Reserved 2168 }; 2169 uint32_t Value; 2170 } DW15; 2171 union 2172 { 2173 //!< DWORD 16 2174 struct 2175 { 2176 uint32_t Reserved512 ; //!< Reserved 2177 }; 2178 uint32_t Value; 2179 } DW16; 2180 union 2181 { 2182 //!< DWORD 17 2183 struct 2184 { 2185 uint32_t AvcIntra4X4ModeMask : __CODEGEN_BITFIELD( 0, 8) ; //!< AVC Intra 4x4 Mode Mask 2186 uint32_t Reserved553 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2187 uint32_t AvcIntra8X8ModeMask : __CODEGEN_BITFIELD(16, 24) ; //!< AVC Intra 8x8 Mode Mask 2188 uint32_t Reserved569 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 2189 }; 2190 uint32_t Value; 2191 } DW17; 2192 union 2193 { 2194 //!< DWORD 18 2195 struct 2196 { 2197 uint32_t AvcIntra16X16ModeMask : __CODEGEN_BITFIELD( 0, 3) ; //!< AVC_INTRA_16X16_MODE_MASK 2198 uint32_t AvcIntraChromaModeMask : __CODEGEN_BITFIELD( 4, 7) ; //!< AVC_INTRA_CHROMA_MODE_MASK 2199 uint32_t IntraComputeTypeIntracomputetype : __CODEGEN_BITFIELD( 8, 9) ; //!< INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2200 uint32_t Reserved586 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 2201 }; 2202 uint32_t Value; 2203 } DW18; 2204 union 2205 { 2206 //!< DWORD 19 2207 struct 2208 { 2209 uint32_t Reserved608 ; //!< Reserved 2210 }; 2211 uint32_t Value; 2212 } DW19; 2213 union 2214 { 2215 //!< DWORD 20 2216 struct 2217 { 2218 uint32_t PenaltyForIntra16X16NondcPrediction : __CODEGEN_BITFIELD( 0, 7) ; //!< Penalty for Intra16x16 NonDC Prediction. 2219 uint32_t PenaltyForIntra8X8NondcPrediction : __CODEGEN_BITFIELD( 8, 15) ; //!< Penalty for Intra8x8 NonDC Prediction. 2220 uint32_t PenaltyForIntra4X4NondcPrediction : __CODEGEN_BITFIELD(16, 23) ; //!< Penalty for Intra4x4 NonDC Prediction. 2221 uint32_t Reserved664 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2222 }; 2223 uint32_t Value; 2224 } DW20; 2225 union 2226 { 2227 //!< DWORD 21 2228 struct 2229 { 2230 uint32_t IntraRefreshMBPos : __CODEGEN_BITFIELD( 0, 7) ; //!< IntraRefreshMBPos 2231 uint32_t IntraRefreshMBSizeMinusOne : __CODEGEN_BITFIELD( 8, 15) ; //!< IntraRefreshMBSizeMinusOne 2232 uint32_t IntraRefreshEnableRollingIEnable : __CODEGEN_BITFIELD(16, 16) ; //!< INTRAREFRESHENABLE_ROLLING_I_ENABLE 2233 uint32_t IntraRefreshMode : __CODEGEN_BITFIELD(17, 17) ; //!< INTRAREFRESHMODE 2234 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 23) ; //!< Reserved 2235 uint32_t QpAdjustmentForRollingI : __CODEGEN_BITFIELD(24, 31) ; //!< QP adjustment for Rolling-I 2236 }; 2237 uint32_t Value; 2238 } DW21; 2239 union 2240 { 2241 //!< DWORD 22 2242 struct 2243 { 2244 uint32_t Panicmodembthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< PanicModeMBThreshold 2245 uint32_t Smallmbsizeinword : __CODEGEN_BITFIELD(16, 23) ; //!< SmallMbSizeInWord 2246 uint32_t Largembsizeinword : __CODEGEN_BITFIELD(24, 31) ; //!< LargeMbSizeInWord 2247 }; 2248 uint32_t Value; 2249 } DW22; 2250 union 2251 { 2252 //!< DWORD 23 2253 struct 2254 { 2255 uint32_t L0NumberOfReferencesMinusOne : __CODEGEN_BITFIELD( 0, 7) ; //!< L0 number of references Minus one 2256 uint32_t Reserved744 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 2257 uint32_t L1NumberOfReferencesMinusOne : __CODEGEN_BITFIELD(16, 23) ; //!< L1 number of references Minus One 2258 uint32_t Reserved760 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 2259 }; 2260 uint32_t Value; 2261 } DW23; 2262 union 2263 { 2264 //!< DWORD 24 2265 struct 2266 { 2267 uint32_t MacroblockBudget : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock Budget 2268 uint32_t InitialTime : __CODEGEN_BITFIELD(16, 31) ; //!< Initial Time 2269 }; 2270 uint32_t Value; 2271 } DW24; 2272 union 2273 { 2274 //!< DWORD 25 2275 struct 2276 { 2277 uint32_t Reserved800 ; //!< Reserved 2278 }; 2279 uint32_t Value; 2280 } DW25; 2281 union 2282 { 2283 //!< DWORD 26 2284 struct 2285 { 2286 uint32_t Reserved832 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 2287 uint32_t HmeRefWindowsCombiningThreshold : __CODEGEN_BITFIELD( 8, 15) ; //!< HME_REF_WINDOWS_COMBINING_THRESHOLD 2288 uint32_t Reserved848 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2289 }; 2290 uint32_t Value; 2291 } DW26; 2292 union 2293 { 2294 //!< DWORD 27 2295 struct 2296 { 2297 uint32_t MaxHmvR : __CODEGEN_BITFIELD( 0, 15) ; //!< MAXHMVR 2298 uint32_t MaxVmvR : __CODEGEN_BITFIELD(16, 31) ; //!< MAXVMVR 2299 }; 2300 uint32_t Value; 2301 } DW27; 2302 union 2303 { 2304 //!< DWORD 28 2305 struct 2306 { 2307 uint32_t HmeMvCost0 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 0 2308 uint32_t HmeMvCost1 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 1 2309 uint32_t HmeMvCost2 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 2 2310 uint32_t HmeMvCost3 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 3 2311 }; 2312 uint32_t Value; 2313 } DW28; 2314 union 2315 { 2316 //!< DWORD 29 2317 struct 2318 { 2319 uint32_t HmeMvCost4 : __CODEGEN_BITFIELD( 0, 7) ; //!< HmeMvCost 4 2320 uint32_t HmeMvCost5 : __CODEGEN_BITFIELD( 8, 15) ; //!< HmeMvCost 5 2321 uint32_t HmeMvCost6 : __CODEGEN_BITFIELD(16, 23) ; //!< HmeMvCost 6 2322 uint32_t HmeMvCost7 : __CODEGEN_BITFIELD(24, 31) ; //!< HmeMvCost 7 2323 }; 2324 uint32_t Value; 2325 } DW29; 2326 union 2327 { 2328 //!< DWORD 30 2329 struct 2330 { 2331 uint32_t RoiQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< ROI QP adjustment for Zone0 2332 uint32_t RoiQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< ROI QP adjustment for Zone1 2333 uint32_t RoiQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< ROI QP adjustment for Zone2 2334 uint32_t RoiQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< ROI QP adjustment for Zone3 2335 uint32_t QpAdjustmentForShapeBestIntra4X4Winner : __CODEGEN_BITFIELD(16, 19) ; //!< QP adjustment for shape best intra 4x4 winner 2336 uint32_t QpAdjustmentForShapeBestIntra8X8Winner : __CODEGEN_BITFIELD(20, 23) ; //!< QP adjustment for shape best intra 8x8 winner 2337 uint32_t QpAdjustmentForShapeBestIntra16X16Winner : __CODEGEN_BITFIELD(24, 27) ; //!< QP adjustment for shape best intra 16x16 winner 2338 uint32_t Reserved988 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2339 }; 2340 uint32_t Value; 2341 } DW30; 2342 union 2343 { 2344 //!< DWORD 31 2345 struct 2346 { 2347 uint32_t BestdistortionQpAdjustmentForZone0 : __CODEGEN_BITFIELD( 0, 3) ; //!< BestDistortion QP adjustment for Zone0 2348 uint32_t BestdistortionQpAdjustmentForZone1 : __CODEGEN_BITFIELD( 4, 7) ; //!< BestDistortion QP adjustment for Zone1 2349 uint32_t BestdistortionQpAdjustmentForZone2 : __CODEGEN_BITFIELD( 8, 11) ; //!< BestDistortion QP adjustment for Zone2 2350 uint32_t BestdistortionQpAdjustmentForZone3 : __CODEGEN_BITFIELD(12, 15) ; //!< BestDistortion QP adjustment for Zone3 2351 uint32_t SadHaarThreshold0 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_0 2352 }; 2353 uint32_t Value; 2354 } DW31; 2355 union 2356 { 2357 //!< DWORD 32 2358 struct 2359 { 2360 uint32_t SadHaarThreshold1 : __CODEGEN_BITFIELD( 0, 15) ; //!< Sad/Haar_Threshold_1 2361 uint32_t SadHaarThreshold2 : __CODEGEN_BITFIELD(16, 31) ; //!< Sad/Haar_Threshold_2 2362 }; 2363 uint32_t Value; 2364 } DW32; 2365 union 2366 { 2367 //!< DWORD 33 2368 struct 2369 { 2370 uint32_t MaxQp : __CODEGEN_BITFIELD( 0, 7) ; //!< MaxQP 2371 uint32_t MinQp : __CODEGEN_BITFIELD( 8, 15) ; //!< MinQP 2372 uint32_t Reserved1072 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 2373 uint32_t Maxdeltaqp : __CODEGEN_BITFIELD(24, 27) ; //!< MaxDeltaQP 2374 uint32_t Reserved1084 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 2375 }; 2376 uint32_t Value; 2377 } DW33; 2378 union 2379 { 2380 //!< DWORD 34 2381 struct 2382 { 2383 uint32_t RoiEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< ROI_Enable 2384 uint32_t FwdPredictor0MvEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Fwd/Predictor0 MV Enable 2385 uint32_t BwdPredictor1MvEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Bwd/Predictor1 MV Enable 2386 uint32_t MbLevelQpEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< MB Level QP Enable 2387 uint32_t TargetsizeinwordsmbMaxsizeinwordsmbEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< TargetSizeinWordsMB/MaxSizeinWordsMB Enable 2388 uint32_t Reserverd : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserverd 2389 uint32_t PpmvDisable : __CODEGEN_BITFIELD( 8, 8) ; //!< PPMV_DISABLE 2390 uint32_t CoefficientClampEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Coefficient Clamp Enable 2391 uint32_t LongtermReferenceFrameBwdRef0Indicator : __CODEGEN_BITFIELD(10, 10) ; //!< LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2392 uint32_t LongtermReferenceFrameFwdRef2Indicator : __CODEGEN_BITFIELD(11, 11) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2393 uint32_t LongtermReferenceFrameFwdRef1Indicator : __CODEGEN_BITFIELD(12, 12) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2394 uint32_t LongtermReferenceFrameFwdRef0Indicator : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2395 uint32_t Reserved1102 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2396 uint32_t MidpointSadHaar : __CODEGEN_BITFIELD(16, 31) ; //!< Midpoint sad/haar 2397 }; 2398 uint32_t Value; 2399 } DW34; 2400 2401 //! \name Local enumerations 2402 2403 enum SUBOPB 2404 { 2405 SUBOPB_VDENCIMGSTATE = 5, //!< No additional details 2406 }; 2407 2408 enum SUBOPA 2409 { 2410 SUBOPA_UNNAMED0 = 0, //!< No additional details 2411 }; 2412 2413 enum OPCODE 2414 { 2415 OPCODE_VDENCPIPE = 1, //!< No additional details 2416 }; 2417 2418 enum PIPELINE 2419 { 2420 PIPELINE_MFXCOMMON = 2, //!< No additional details 2421 }; 2422 2423 enum COMMAND_TYPE 2424 { 2425 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2426 }; 2427 2428 enum BIDIRECTIONAL_MIX_DISABLE 2429 { 2430 BIDIRECTIONAL_MIX_DISABLE_SUBBLOCKENABLED = 0, //!< Bidirectional decision on subblock level that bidirectional mode is enabled. 2431 BIDIRECTIONAL_MIX_DISABLE_WHOLEMACROBLOCKENABLED = 1, //!< Bidirectional decision on whole macroblock. 2432 }; 2433 2434 //! \brief VDENC_PERFMODE 2435 //! \details 2436 //! This bit indicates if VDEnc is configured for normal or speed mode of 2437 //! operation. 2438 enum VDENC_PERFMODE 2439 { 2440 VDENC_PERFMODE_NORMAL = 0, //!< VDEnc is running in normal mode. IME Search: 3x3 SU per each reference. HME Search: 88x92 search window per HME instance (0 & 1). 2441 VDENC_PERFMODE_SPEED = 1, //!< VDEnc is configured for speed mode. IME Search: 2x2 SU per each reference. HME Search: 48x92 search window per HME instance (0 & 1). 2442 }; 2443 2444 //! \brief TIME_BUDGET_OVERFLOW_CHECK 2445 //! \details 2446 //! <p>This bit enables the frame time budget detection in VDEnc.</p> 2447 //! <p>To detect if a Time Budget Overflow happened in a frame, SW 2448 //! can read "PAK_Stream-Out Report (Errors)" register in MFX. When Time 2449 //! budget overflow condition happens in the frame, this register bits 15:8 2450 //! indicate MB y position and bits 7:0 indicate MB x position where Time 2451 //! budget overflow occured. When there is no time budget overflow in a 2452 //! frame, "<span style="line-height: 20.7999992370605px;">PAK_Stream-Out 2453 //! Report (Errors)" register reads zero.</span></p> 2454 enum TIME_BUDGET_OVERFLOW_CHECK 2455 { 2456 TIME_BUDGET_OVERFLOW_CHECK_DISABLED = 0, //!< No additional details 2457 TIME_BUDGET_OVERFLOW_CHECK_ENABLED = 1, //!< No additional details 2458 }; 2459 2460 //! \brief VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 2461 //! \details 2462 //! This bit enables the distortion data to be populated in the VDenc PAK 2463 //! Obj inline data. 2464 enum VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE 2465 { 2466 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_DISABLE = 0, //!< The extra two DWS from VDEnc (MDC) to PAK will be Zero. 2467 VDENC_EXTENDED_PAK_OBJ_CMD_ENABLE_ENABLE = 1, //!< The last two DWs from VDEnc (MDC) to PAK will be populated with distortion data. (Defined in the PAK Object command DW 22,23.) 2468 }; 2469 2470 //! \brief TRANSFORM_8X8_FLAG 2471 //! \details 2472 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flag specifies 8x8 IDCT 2473 //! transform may be used in this 2474 //! picture. It is set to the value of the syntax element in the 2475 //! current active PPS. 2476 enum TRANSFORM_8X8_FLAG 2477 { 2478 TRANSFORM_8X8_FLAG_DISABLED = 0, //!< No 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present. 2479 TRANSFORM_8X8_FLAG_ENABLED = 1, //!< 8x8 Transform is allowed. 2480 }; 2481 2482 //! \brief VDENC_L1_CACHE_PRIORITY 2483 //! \details 2484 //! L1 Cache inside VDEnc has 3 clients - IME, CRE and VMC. These bits 2485 //! indicate the priority order for 2486 //! L1 cache to service the client requests. 2487 enum VDENC_L1_CACHE_PRIORITY 2488 { 2489 VDENC_L1_CACHE_PRIORITY_UNNAMED0 = 0, //!< CRE High Priority, VMC and IME round robin. 2490 VDENC_L1_CACHE_PRIORITY_UNNAMED1 = 1, //!< CRE and VMC round robin, IME low priority. 2491 VDENC_L1_CACHE_PRIORITY_UNNAMED2 = 2, //!< CRE High Priority, IME Medium, VMC Low. 2492 VDENC_L1_CACHE_PRIORITY_UNNAMED3 = 3, //!< VMC High Priority, CRE Medium, IME low. 2493 }; 2494 2495 //! \brief BIDIRECTIONAL_WEIGHT 2496 //! \details 2497 //! Default value: Depends on the distance between the B and reference 2498 //! pictures. 2499 enum BIDIRECTIONAL_WEIGHT 2500 { 2501 BIDIRECTIONAL_WEIGHT_UNNAMED16 = 16, //!< No additional details 2502 BIDIRECTIONAL_WEIGHT_UNNAMED21 = 21, //!< No additional details 2503 BIDIRECTIONAL_WEIGHT_UNNAMED32 = 32, //!< No additional details 2504 BIDIRECTIONAL_WEIGHT_UNNAMED43 = 43, //!< No additional details 2505 BIDIRECTIONAL_WEIGHT_UNNAMED48 = 48, //!< No additional details 2506 }; 2507 2508 //! \brief SUB_PEL_MODE 2509 //! \details 2510 //! This field defines the half/quarter pel modes. The mode is inclusive, 2511 //! i.e., higher precision mode samples lower precision locations. 2512 enum SUB_PEL_MODE 2513 { 2514 SUB_PEL_MODE_UNNAMED0 = 0, //!< Integer mode searching. 2515 SUB_PEL_MODE_UNNAMED1 = 1, //!< Half-pel mode searching. 2516 SUB_PEL_MODE_UNNAMED3 = 3, //!< Quarter-pel mode searching. 2517 }; 2518 2519 //! \brief FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2520 //! \details 2521 //! This field enables the forward transform calculation for skip check. It 2522 //! does not override the other 2523 //! skip calculations but it does decrease the performance marginally 2524 //! so don't enable it unless the transform is necessary. 2525 enum FORWARD_TRANSFORM_SKIP_CHECK_ENABLE 2526 { 2527 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTDISABLED = 0, //!< No additional details 2528 FORWARD_TRANSFORM_SKIP_CHECK_ENABLE_FTENABLED = 1, //!< No additional details 2529 }; 2530 2531 //! \brief BME_DISABLE_FOR_FBR_MESSAGE 2532 //! \details 2533 //! FBR messages that do not want bidirectional motion estimation performed 2534 //! will set this bit and VME will 2535 //! only perform fractional refinement on the shapes identified by 2536 //! subpredmode. Note: only the LSB of the 2537 //! subpredmode for each shape will be considered in FBR (a shape is 2538 //! either FWD or BWD as input of FBR, 2539 //! output however could change to BI if BME is enabled). 2540 enum BME_DISABLE_FOR_FBR_MESSAGE 2541 { 2542 BME_DISABLE_FOR_FBR_MESSAGE_BMEENABLED = 0, //!< No additional details 2543 BME_DISABLE_FOR_FBR_MESSAGE_BMEDISABLED = 1, //!< No additional details 2544 }; 2545 2546 //! \brief BLOCK_BASED_SKIP_ENABLED 2547 //! \details 2548 //! When this field is set on the skip thresholding passing criterion will 2549 //! be based on the maximal distortion 2550 //! of individual blocks (8x8's or 4x4's) instead of their sum (i.e. 2551 //! the distortion of 16x16). 2552 enum BLOCK_BASED_SKIP_ENABLED 2553 { 2554 BLOCK_BASED_SKIP_ENABLED_UNNAMED0 = 0, //!< 16x16 Block Based Skip threshold check. 2555 BLOCK_BASED_SKIP_ENABLED_BLOCK_BASEDSKIPTYPE = 1, //!< Parameter indicates 8x8 vs. 4x4 based check. 2556 }; 2557 2558 //! \brief INTER_SAD_MEASURE_ADJUSTMENT 2559 //! \details 2560 //! This field specifies distortion measure adjustments used for the motion 2561 //! search SAD comparison. 2562 //! This field applies to both luma and chroma inter measurement. 2563 enum INTER_SAD_MEASURE_ADJUSTMENT 2564 { 2565 INTER_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 2566 INTER_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 2567 }; 2568 2569 //! \brief INTRA_SAD_MEASURE_ADJUSTMENT 2570 //! \details 2571 //! This field specifies distortion measure adjustments used for the motion 2572 //! search SAD comparison. 2573 //! This field applies to both luma and chroma intra measurement. 2574 enum INTRA_SAD_MEASURE_ADJUSTMENT 2575 { 2576 INTRA_SAD_MEASURE_ADJUSTMENT_NONE = 0, //!< No additional details 2577 INTRA_SAD_MEASURE_ADJUSTMENT_HAARTRANSFORMADJUSTED = 2, //!< No additional details 2578 }; 2579 2580 //! \brief SUB_MACROBLOCK_SUB_PARTITION_MASK 2581 //! \details 2582 //! This field defines the bit-mask for disabling 2583 //! <ul> 2584 //! <li>sub-partition (minor partition [30:28]) modes</li> 2585 //! <li>sub-macroblock (major partition [27:24]) modes</li> 2586 //! </ul> 2587 enum SUB_MACROBLOCK_SUB_PARTITION_MASK 2588 { 2589 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED113 = 113, //!< 16x16 sub-macroblock disabled 2590 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED114 = 114, //!< 2x(16x8) sub-macroblock within 16x16 disabled 2591 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED116 = 116, //!< 2x(8x16) sub-macroblock within 16x16 disabled 2592 SUB_MACROBLOCK_SUB_PARTITION_MASK_UNNAMED120 = 120, //!< 1x(8x8) sub-partition for 4x(8x8) within 16x16 disabled 2593 }; 2594 2595 //! \brief BLOCK_BASED_SKIP_TYPE 2596 //! \details 2597 //! The skip thresholding passing criterion will be based on the maximal 2598 //! distortion of individual blocks 2599 //! (8x8's or 4x4's) instead of their sum (i.e. the distortion of 2600 //! 16x16). This field is only valid when 2601 //! <b>Block-Based Skip Enabled</b> = 1. 2602 enum BLOCK_BASED_SKIP_TYPE 2603 { 2604 BLOCK_BASED_SKIP_TYPE_UNNAMED0 = 0, //!< 4x4 block-based skip threshold check. 2605 BLOCK_BASED_SKIP_TYPE_UNNAMED1 = 1, //!< 8x8 block-based skip threshold check. 2606 }; 2607 2608 //! \brief CRE_PREFETCH_ENABLE 2609 //! \details 2610 //! This field determines if IME will prefetch the fractional CLs that are 2611 //! required by CRE ahead of time 2612 //! while fetching the reference windows around the IME predictors. The 2613 //! recommendation for driver is to 2614 //! always program this bit to 1 unless some usages restrict SubPelMode 2615 //! to be "<i>Integer mode searching</i>". 2616 enum CRE_PREFETCH_ENABLE 2617 { 2618 CRE_PREFETCH_ENABLE_UNNAMED0 = 0, //!< Disable 2619 CRE_PREFETCH_ENABLE_UNNAMED1 = 1, //!< Enable 2620 }; 2621 2622 //! \brief HME_REF1_DISABLE 2623 //! \details 2624 //! This field indicates if HME is disabled for reference 1 (second forward 2625 //! reference). 2626 enum HME_REF1_DISABLE 2627 { 2628 HME_REF1_DISABLE_UNNAMED0 = 0, //!< HME search is performed on forward reference 1. 2629 HME_REF1_DISABLE_UNNAMED1 = 1, //!< HME search is disabled on forward reference 1. 2630 }; 2631 2632 enum CONSTRAINED_INTRA_PREDICTION_FLAG 2633 { 2634 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED0 = 0, //!< Allows both intra and inter neighboring MB to be used in the intra-prediction decoding of the current MB. 2635 CONSTRAINED_INTRA_PREDICTION_FLAG_UNNAMED1 = 1, //!< Allows only to use neighboring Intra MBs in the intra-prediction decoding of the current MB.If the neighbor is an inter MB, it is considered as not available. 2636 }; 2637 2638 //! \brief PICTURE_TYPE 2639 //! \details 2640 //! This field specifies how the current picture is predicted. (It might be 2641 //! redundant from the kernel type.) 2642 enum PICTURE_TYPE 2643 { 2644 PICTURE_TYPE_I = 0, //!< No additional details 2645 PICTURE_TYPE_P = 1, //!< No additional details 2646 }; 2647 2648 //! \brief LUMA_INTRA_PARTITION_MASK 2649 //! \details 2650 //! This field specifies which Luma Intra partition is enabled/disabled for 2651 //! intra mode decision. 2652 enum LUMA_INTRA_PARTITION_MASK 2653 { 2654 LUMA_INTRA_PARTITION_MASK_UNNAMED1 = 1, //!< luma_intra_16x16 disabled 2655 LUMA_INTRA_PARTITION_MASK_UNNAMED2 = 2, //!< luma_intra_8x8 disabled 2656 LUMA_INTRA_PARTITION_MASK_UNNAMED4 = 4, //!< luma_intra_4x4 disabled 2657 }; 2658 2659 enum MV_COST_SCALING_FACTOR 2660 { 2661 MV_COST_SCALING_FACTOR_QPEL = 0, //!< Qpel difference between MV and cost center: eff cost range 0-15pel 2662 MV_COST_SCALING_FACTOR_HPEL = 1, //!< Hpel difference between MV and cost center: eff cost range 0-31pel 2663 MV_COST_SCALING_FACTOR_PEL = 2, //!< Pel difference between MV and cost center: eff cost range 0-63pel 2664 MV_COST_SCALING_FACTOR_2PEL = 3, //!< 2Pel difference between MV and cost center: eff cost range 0-127pel 2665 }; 2666 2667 enum REFID_COST_MODE_SELECT 2668 { 2669 REFID_COST_MODE_SELECT_MODE0 = 0, //!< AVC 2670 REFID_COST_MODE_SELECT_MODE1 = 1, //!< Linear 2671 }; 2672 2673 enum AVC_INTRA_16X16_MODE_MASK 2674 { 2675 AVC_INTRA_16X16_MODE_MASK_VERT = 1, //!< No additional details 2676 AVC_INTRA_16X16_MODE_MASK_HORZ = 2, //!< No additional details 2677 AVC_INTRA_16X16_MODE_MASK_DC = 4, //!< No additional details 2678 AVC_INTRA_16X16_MODE_MASK_PLANAR = 8, //!< No additional details 2679 }; 2680 2681 enum AVC_INTRA_CHROMA_MODE_MASK 2682 { 2683 AVC_INTRA_CHROMA_MODE_MASK_VERT = 1, //!< No additional details 2684 AVC_INTRA_CHROMA_MODE_MASK_HORZ = 2, //!< No additional details 2685 AVC_INTRA_CHROMA_MODE_MASK_DC = 4, //!< No additional details 2686 AVC_INTRA_CHROMA_MODE_MASK_PLANAR = 8, //!< No additional details 2687 }; 2688 2689 //! \brief INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2690 //! \details 2691 //! This field specifies the pixel components measured for Intra prediction. 2692 enum INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE 2693 { 2694 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED0 = 0, //!< Luma+Chroma enabled. 2695 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED1 = 1, //!< Luma Only. 2696 INTRA_COMPUTE_TYPE_INTRACOMPUTETYPE_UNNAMED2 = 2, //!< Intra Disabled. 2697 }; 2698 2699 //! \brief INTRAREFRESHENABLE_ROLLING_I_ENABLE 2700 //! \details 2701 //! <p>This parameter indicates if the IntraRefresh is enabled or 2702 //! disabled.</p> 2703 //! 2704 //! <p>This must be disabled on I-Frames.</p> 2705 enum INTRAREFRESHENABLE_ROLLING_I_ENABLE 2706 { 2707 INTRAREFRESHENABLE_ROLLING_I_ENABLE_DISABLE = 0, //!< No additional details 2708 INTRAREFRESHENABLE_ROLLING_I_ENABLE_ENABLE = 1, //!< No additional details 2709 }; 2710 2711 //! \brief INTRAREFRESHMODE 2712 //! \details 2713 //! This parameter indicates if the IntraRefresh is row based or column 2714 //! based. 2715 enum INTRAREFRESHMODE 2716 { 2717 INTRAREFRESHMODE_ROWBASED = 0, //!< No additional details 2718 INTRAREFRESHMODE_COLUMNBASED = 1, //!< No additional details 2719 }; 2720 2721 //! \brief HME_REF_WINDOWS_COMBINING_THRESHOLD 2722 //! \details 2723 //! When the reference windows of the HME refinement VME call and the 2724 //! regular VME call are overlapped 2725 //! and the difference of the locations is within this threshold in 2726 //! quarter pixel unit, the two calls 2727 //! are merged to a single call. 2728 enum HME_REF_WINDOWS_COMBINING_THRESHOLD 2729 { 2730 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED0 = 0, //!< No additional details 2731 HME_REF_WINDOWS_COMBINING_THRESHOLD_UNNAMED255 = 255, //!< No additional details 2732 }; 2733 2734 //! \brief MAXHMVR 2735 //! \details 2736 //! Horizontal MV component range. The MV range is restricted to 2737 //! [-MaxHmvR+1, MaxHmvR-1] in luma quarter pel unit, 2738 //! which corresponds to [-MaxHmvR/4 + 0.25, MaxHmvR/4-0.25] in luma 2739 //! integer pel unit. 2740 enum MAXHMVR 2741 { 2742 MAXHMVR_UNNAMED256 = 256, //!< No additional details 2743 MAXHMVR_UNNAMED512 = 512, //!< No additional details 2744 MAXHMVR_UNNAMED1024 = 1024, //!< No additional details 2745 MAXHMVR_UNNAMED2048 = 2048, //!< No additional details 2746 MAXHMVR_UNNAMED4096 = 4096, //!< No additional details 2747 MAXHMVR_UNNAMED8192 = 8192, //!< No additional details 2748 }; 2749 2750 //! \brief MAXVMVR 2751 //! \details 2752 //! Vertical MV component range defined in the AVC Spec Annex A. The MV 2753 //! range is restricted to [-MaxVmvR+1, MaxVmvR-1] 2754 //! in luma quarter pel unit, which corresponds to [-MaxVmvR/4 + 0.25, 2755 //! MaxVmvR/4-0.25] in luma integer pel unit. 2756 enum MAXVMVR 2757 { 2758 MAXVMVR_UNNAMED256 = 256, //!< No additional details 2759 MAXVMVR_UNNAMED512 = 512, //!< No additional details 2760 MAXVMVR_UNNAMED1024 = 1024, //!< No additional details 2761 MAXVMVR_UNNAMED2048 = 2048, //!< No additional details 2762 }; 2763 2764 //! \brief PPMV_DISABLE 2765 //! \details 2766 //! This bit forces the IME to use the actual PMV predictor for the IME 2767 //! search. 2768 enum PPMV_DISABLE 2769 { 2770 PPMV_DISABLE_UNNAMED0 = 0, //!< Use PPMV based IME search. 2771 PPMV_DISABLE_UNNAMED1 = 1, //!< Use PMV based IME search. 2772 }; 2773 2774 //! \brief LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2775 //! \details 2776 //! Indicates whether the reference frame is a long or short term reference. 2777 enum LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR 2778 { 2779 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2780 LONGTERM_REFERENCE_FRAME_BWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2781 }; 2782 2783 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2784 //! \details 2785 //! Indicates whether the reference frame is a long or short term reference. 2786 enum LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR 2787 { 2788 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2789 LONGTERM_REFERENCE_FRAME_FWD_REF2_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2790 }; 2791 2792 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2793 //! \details 2794 //! Indicates whether the reference frame is a long or short term reference. 2795 enum LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR 2796 { 2797 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2798 LONGTERM_REFERENCE_FRAME_FWD_REF1_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2799 }; 2800 2801 //! \brief LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2802 //! \details 2803 //! Indicates whether the reference frame is a long or short term reference. 2804 enum LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR 2805 { 2806 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_SHORT_TERMREFERENCE = 0, //!< No additional details 2807 LONGTERM_REFERENCE_FRAME_FWD_REF0_INDICATOR_LONG_TERMREFERENCE = 1, //!< No additional details 2808 }; 2809 2810 //! \name Initializations 2811 2812 //! \brief Explicit member initialization function 2813 VDENC_IMG_STATE_CMD(); 2814 2815 static const size_t dwSize = 35; 2816 static const size_t byteSize = 140; 2817 }; 2818 2819 //! 2820 //! \brief VDENC_PIPE_BUF_ADDR_STATE 2821 //! \details 2822 //! This state command provides the memory base addresses for all row 2823 //! stores, Streamin/StreamOut, DMV buffer along with the uncompressed 2824 //! source, reference pictures and downscaled reference pictures required by 2825 //! the VDENC pipeline. All reference pixel surfaces in the Encoder are 2826 //! programmed with the same surface state (NV12 and TileY format), except 2827 //! each has its own frame buffer base address. Same holds true for the 2828 //! down-scaled reference pictures too. In the tile format, there is no need 2829 //! to provide buffer offset for each slice; since from each MB address, the 2830 //! hardware can calculated the corresponding memory location within the 2831 //! frame buffer directly. VDEnc supports 3 Downscaled reference frames ( 2 2832 //! fwd, 1 bwd) and 4 normal reference frames ( 3 fwd, 1 bwd). The driver 2833 //! will sort out the base address from the DPB table and populate the base 2834 //! addresses that map to the corresponding reference index for both DS 2835 //! references and normal reference frames. Each of the individual DS ref/ 2836 //! Normal ref frames have their own MOCS DW that corresponds to the 2837 //! respective base address. The only thing that is different in the MOCS DW 2838 //! amongst the DS reference frames is the MMCD controls (specified in bits 2839 //! [10:9] of the MOCS DW). Driver needs to ensure that the other bits need 2840 //! to be the same across the different DS ref frames. The same is 2841 //! applicable for the normal reference frames. 2842 //! 2843 struct VDENC_PIPE_BUF_ADDR_STATE_CMD 2844 { 2845 union 2846 { 2847 //!< DWORD 0 2848 struct 2849 { 2850 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2851 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2852 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2853 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2854 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2855 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2856 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2857 }; 2858 uint32_t Value; 2859 } DW0; 2860 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef0 ; //!< DS FWD REF0 2861 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef1 ; //!< DS FWD REF1 2862 VDENC_Down_Scaled_Reference_Picture_CMD DsBwdRef0 ; //!< DS BWD REF0 2863 VDENC_Original_Uncompressed_Picture_CMD OriginalUncompressedPicture ; //!< Original Uncompressed Picture 2864 VDENC_Streamin_Data_Picture_CMD StreaminDataPicture ; //!< Streamin Data Picture 2865 VDENC_Row_Store_Scratch_Buffer_Picture_CMD RowStoreScratchBuffer ; //!< Row Store Scratch Buffer 2866 VDENC_Colocated_MV_Picture_CMD ColocatedMv ; //!< Colocated MV 2867 VDENC_Reference_Picture_CMD FwdRef0 ; //!< FWD REF0 2868 VDENC_Reference_Picture_CMD FwdRef1 ; //!< FWD REF1 2869 VDENC_Reference_Picture_CMD FwdRef2 ; //!< FWD REF2 2870 VDENC_Reference_Picture_CMD BwdRef0 ; //!< BWD REF0 2871 VDENC_Statistics_Streamout_CMD VdencStatisticsStreamout ; //!< VDEnc Statistics Streamout 2872 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef04X ; //!< DS FWD REF0 4X 2873 VDENC_Down_Scaled_Reference_Picture_CMD DsFwdRef14X ; //!< DS FWD REF1 4X 2874 VDENC_Colocated_MV_Picture_CMD VdencCuRecordStreamOutBuffer ; //!< VDEnc CuRecord stream-out buffer 2875 VDENC_Colocated_MV_Picture_CMD VdencLcuPakObjCmdBuffer ; //!< VDEnc LCU PAK OBJ CMD Buffer 2876 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurface8X ; //!< Scaled Reference Surface 8X 2877 VDENC_Down_Scaled_Reference_Picture_CMD ScaledReferenceSurface4X ; //!< Scaled Reference Surface 4X 2878 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreaminBuffer ; //!< VP9 Segmentation Map Streamin Buffer 2879 VDENC_Colocated_MV_Picture_CMD Vp9SegmentationMapStreamoutBuffer ; //!< VP9 Segmentation Map Streamout Buffer 2880 union 2881 { 2882 //!< DWORD 61 2883 struct 2884 { 2885 uint32_t WeightsHistogramStreamoutOffset ; //!< Weights Histogram Streamout offset 2886 }; 2887 uint32_t Value; 2888 } DW61; 2889 2890 //! \name Local enumerations 2891 2892 enum SUBOPB 2893 { 2894 SUBOPB_VDENCPIPEBUFADDRSTATE = 4, //!< No additional details 2895 }; 2896 2897 enum SUBOPA 2898 { 2899 SUBOPA_UNNAMED0 = 0, //!< No additional details 2900 }; 2901 2902 enum OPCODE 2903 { 2904 OPCODE_VDENCPIPE = 1, //!< No additional details 2905 }; 2906 2907 enum PIPELINE 2908 { 2909 PIPELINE_MFXCOMMON = 2, //!< No additional details 2910 }; 2911 2912 enum COMMAND_TYPE 2913 { 2914 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2915 }; 2916 2917 //! \name Initializations 2918 2919 //! \brief Explicit member initialization function 2920 VDENC_PIPE_BUF_ADDR_STATE_CMD(); 2921 2922 static const size_t dwSize = 62; 2923 static const size_t byteSize = 248; 2924 }; 2925 2926 //! 2927 //! \brief VDENC_PIPE_MODE_SELECT 2928 //! \details 2929 //! Specifies which codec and hardware module is being used to encode/decode 2930 //! the video data, on a per-frame basis. The VDENC_PIPE_MODE_SELECT command 2931 //! specifies which codec and hardware module is being used to encode/decode 2932 //! the video data, on a per-frame basis. It also configures the hardware 2933 //! pipeline according to the active encoder/decoder operating mode for 2934 //! encoding/decoding the current picture. 2935 //! 2936 struct VDENC_PIPE_MODE_SELECT_CMD 2937 { 2938 union 2939 { 2940 //!< DWORD 0 2941 struct 2942 { 2943 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2944 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2945 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 2946 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 2947 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 2948 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2949 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2950 }; 2951 uint32_t Value; 2952 } DW0; 2953 union 2954 { 2955 //!< DWORD 1 2956 struct 2957 { 2958 uint32_t StandardSelect : __CODEGEN_BITFIELD( 0, 3) ; //!< STANDARD_SELECT 2959 uint32_t ScalabilityMode : __CODEGEN_BITFIELD( 4, 4) ; //!< Scalability Mode 2960 uint32_t FrameStatisticsStreamOutEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< FRAME_STATISTICS_STREAM_OUT_ENABLE 2961 uint32_t VdencPakObjCmdStreamOutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< VDEnc PAK_OBJ_CMD Stream-Out Enable 2962 uint32_t TlbPrefetchEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< TLB_PREFETCH_ENABLE 2963 uint32_t PakThresholdCheckEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< PAK_THRESHOLD_CHECK_ENABLE 2964 uint32_t VdencStreamInEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< VDENC_STREAM_IN_ENABLE 2965 uint32_t Downscaled8XWriteDisable : __CODEGEN_BITFIELD(10, 10) ; //!< DownScaled 8x write Disable 2966 uint32_t Downscaled4XWriteDisable : __CODEGEN_BITFIELD(11, 11) ; //!< DownScaled 4x write Disable 2967 uint32_t BitDepth : __CODEGEN_BITFIELD(12, 14) ; //!< BIT_DEPTH 2968 uint32_t PakChromaSubSamplingType : __CODEGEN_BITFIELD(15, 16) ; //!< PAK_CHROMA_SUB_SAMPLING_TYPE 2969 uint32_t OutputRangeControlAfterColorSpaceConversion : __CODEGEN_BITFIELD(17, 17) ; //!< output range control after color space conversion 2970 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 2971 uint32_t DisableSpeedModeFetchOptimization : __CODEGEN_BITFIELD(31, 31) ; //!< Disable Speed Mode fetch optimization 2972 }; 2973 uint32_t Value; 2974 } DW1; 2975 2976 //! \name Local enumerations 2977 2978 enum SUBOPB 2979 { 2980 SUBOPB_VDENCPIPEMODESELECT = 0, //!< No additional details 2981 }; 2982 2983 enum SUBOPA 2984 { 2985 SUBOPA_UNNAMED0 = 0, //!< No additional details 2986 }; 2987 2988 enum OPCODE 2989 { 2990 OPCODE_VDENCPIPE = 1, //!< No additional details 2991 }; 2992 2993 enum PIPELINE 2994 { 2995 PIPELINE_MFXCOMMON = 2, //!< No additional details 2996 }; 2997 2998 enum COMMAND_TYPE 2999 { 3000 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3001 }; 3002 3003 enum STANDARD_SELECT 3004 { 3005 STANDARD_SELECT_AVC = 2, //!< No additional details 3006 }; 3007 3008 //! \brief FRAME_STATISTICS_STREAM_OUT_ENABLE 3009 //! \details 3010 //! This field controls whether the frame statistics stream-out is enabled. 3011 enum FRAME_STATISTICS_STREAM_OUT_ENABLE 3012 { 3013 FRAME_STATISTICS_STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 3014 FRAME_STATISTICS_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 3015 }; 3016 3017 //! \brief TLB_PREFETCH_ENABLE 3018 //! \details 3019 //! This field controls whether TLB prefetching is enabled. 3020 enum TLB_PREFETCH_ENABLE 3021 { 3022 TLB_PREFETCH_ENABLE_DISABLE = 0, //!< No additional details 3023 TLB_PREFETCH_ENABLE_ENABLE = 1, //!< No additional details 3024 }; 3025 3026 //! \brief PAK_THRESHOLD_CHECK_ENABLE 3027 //! \details 3028 //! <p>For AVC standard: This field controls whether VDEnc will check the 3029 //! PAK indicator for bits overflow and terminates the slice. This mode is 3030 //! called Dynamic Slice Mode. When this field is disabled, VDEnc is in 3031 //! Static Slice Mode. It uses the driver programmed Slice Macroblock Height 3032 //! Minus One to terminate the slice. This feature is also referred to as 3033 //! slice size conformance.</p> 3034 //! <p>For HEVC standard: This bit is used to enable dynamic slice size 3035 //! control.</p> 3036 enum PAK_THRESHOLD_CHECK_ENABLE 3037 { 3038 PAK_THRESHOLD_CHECK_ENABLE_DISABLESTATICSLICEMODE = 0, //!< No additional details 3039 PAK_THRESHOLD_CHECK_ENABLE_ENABLEDYNAMICSLICEMODE = 1, //!< No additional details 3040 }; 3041 3042 //! \brief VDENC_STREAM_IN_ENABLE 3043 //! \details 3044 //! <p>This field controls whether VDEnc will read the stream-in surface 3045 //! that is programmed. Currently the stream-in surface has MB level QP, 3046 //! ROI, predictors and MaxSize/TargetSizeinWordsMB parameters. The 3047 //! individual enables for each of the fields is programmed in the 3048 //! VDENC_IMG_STATE.</p> 3049 //! <p>(ROI_Enable, Fwd/Predictor0 MV Enable, Bwd/Predictor1 MV Enable, MB 3050 //! Level QP Enable, TargetSizeinWordsMB/MaxSizeinWordsMB Enable).</p> 3051 //! <p>This bit is valid only in AVC mode. In HEVC / VP9 mode this bit is 3052 //! reserved and should be set to zero.</p> 3053 enum VDENC_STREAM_IN_ENABLE 3054 { 3055 VDENC_STREAM_IN_ENABLE_DISABLE = 0, //!< No additional details 3056 VDENC_STREAM_IN_ENABLE_ENABLE = 1, //!< No additional details 3057 }; 3058 3059 //! \brief BIT_DEPTH 3060 //! \details 3061 //! <p>This parameter indicates the PAK bit depth. The valid values for this 3062 //! are 0 / 2 in HEVC / VP9 standard. In AVC standard this field should be 3063 //! set to 0.</p> 3064 //! <p></p> 3065 enum BIT_DEPTH 3066 { 3067 BIT_DEPTH_8BIT = 0, //!< No additional details 3068 BIT_DEPTH_10BIT = 2, //!< No additional details 3069 BIT_DEPTH_12BIT = 3, //!< No additional details 3070 }; 3071 3072 //! \brief PAK_CHROMA_SUB_SAMPLING_TYPE 3073 //! \details 3074 //! <p>This field is applicable only in HEVC and VP9. In AVC, this field is 3075 //! ignored.</p> 3076 //! <p></p> 3077 enum PAK_CHROMA_SUB_SAMPLING_TYPE 3078 { 3079 PAK_CHROMA_SUB_SAMPLING_TYPE_420 = 1, //!< Used for Main8 and Main10 HEVC, VP9 profile0, AVC. 3080 PAK_CHROMA_SUB_SAMPLING_TYPE_444 = 3, //!< HEVC RExt 444, VP9 444 profiles. 3081 }; 3082 3083 //! \name Initializations 3084 3085 //! \brief Explicit member initialization function 3086 VDENC_PIPE_MODE_SELECT_CMD(); 3087 3088 static const size_t dwSize = 2; 3089 static const size_t byteSize = 8; 3090 }; 3091 3092 //! 3093 //! \brief VDENC_REF_SURFACE_STATE 3094 //! \details 3095 //! This command specifies the surface state parameters for the normal 3096 //! reference surfaces. 3097 //! 3098 struct VDENC_REF_SURFACE_STATE_CMD 3099 { 3100 union 3101 { 3102 //!< DWORD 0 3103 struct 3104 { 3105 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3106 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3107 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3108 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3109 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3110 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3111 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3112 }; 3113 uint32_t Value; 3114 } DW0; 3115 union 3116 { 3117 //!< DWORD 1 3118 struct 3119 { 3120 uint32_t SurfaceId : __CODEGEN_BITFIELD(0, 2) ; //!< Surface ID 3121 uint32_t Reserved : __CODEGEN_BITFIELD(3, 31) ; //!< Reserved 3122 }; 3123 uint32_t Value; 3124 } DW1; 3125 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 3126 3127 //! \name Local enumerations 3128 3129 enum SUBOPB 3130 { 3131 SUBOPB_VDENCREFSURFACESTATE = 2, //!< No additional details 3132 }; 3133 3134 enum SUBOPA 3135 { 3136 SUBOPA_UNNAMED0 = 0, //!< No additional details 3137 }; 3138 3139 enum OPCODE 3140 { 3141 OPCODE_VDENCPIPE = 1, //!< No additional details 3142 }; 3143 3144 enum PIPELINE 3145 { 3146 PIPELINE_MFXCOMMON = 2, //!< No additional details 3147 }; 3148 3149 enum COMMAND_TYPE 3150 { 3151 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3152 }; 3153 3154 //! \name Initializations 3155 3156 //! \brief Explicit member initialization function 3157 VDENC_REF_SURFACE_STATE_CMD(); 3158 3159 static const size_t dwSize = 6; 3160 static const size_t byteSize = 24; 3161 }; 3162 3163 //! 3164 //! \brief VDENC_SRC_SURFACE_STATE 3165 //! \details 3166 //! This command specifies the uncompressed original input picture to be 3167 //! encoded. The actual base address is defined in the 3168 //! VDENC_PIPE_BUF_ADDR_STATE. Pitch can be wider than the Picture Width in 3169 //! pixels and garbage will be there at the end of each line. The following 3170 //! describes all the different formats that are supported in WLV+ VDEnc: 3171 //! NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V offset is set to 3172 //! 0 (the only format supported for video codec); vertical UV offset is MB 3173 //! aligned; UV xoffsets = 0. 3174 //! This surface state here is identical to the Surface State for 3175 //! deinterlace and sample_8x8 messages described in the Shared Function 3176 //! Volume and Sampler Chapter. For non pixel data, such as row stores, DMV 3177 //! and streamin/out, a linear buffer is employed. For row stores, the H/W 3178 //! is designed to guarantee legal memory accesses (read and write). For the 3179 //! remaining cases, indirect object base address, indirect object address 3180 //! upper bound, object data start address (offset) and object data length 3181 //! are used to fully specified their corresponding buffer. This mechanism 3182 //! is chosen over the pixel surface type because of their variable record 3183 //! sizes. All row store surfaces are linear surface. Their addresses are 3184 //! programmed in VDEnc_Pipe_Buf_Base_State. 3185 //! 3186 struct VDENC_SRC_SURFACE_STATE_CMD 3187 { 3188 union 3189 { 3190 //!< DWORD 0 3191 struct 3192 { 3193 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3194 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3195 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3196 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3197 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3198 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3199 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3200 }; 3201 uint32_t Value; 3202 } DW0; 3203 union 3204 { 3205 //!< DWORD 1 3206 struct 3207 { 3208 uint32_t Reserved32 ; //!< Reserved 3209 }; 3210 uint32_t Value; 3211 } DW1; 3212 VDENC_Surface_State_Fields_CMD Dwords25 ; //!< Dwords 2..5 3213 3214 //! \name Local enumerations 3215 3216 enum SUBOPB 3217 { 3218 SUBOPB_VDENCSRCSURFACESTATE = 1, //!< No additional details 3219 }; 3220 3221 enum SUBOPA 3222 { 3223 SUBOPA_UNNAMED0 = 0, //!< No additional details 3224 }; 3225 3226 enum OPCODE 3227 { 3228 OPCODE_VDENCPIPE = 1, //!< No additional details 3229 }; 3230 3231 enum PIPELINE 3232 { 3233 PIPELINE_MFXCOMMON = 2, //!< No additional details 3234 }; 3235 3236 enum COMMAND_TYPE 3237 { 3238 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3239 }; 3240 3241 //! \name Initializations 3242 3243 //! \brief Explicit member initialization function 3244 VDENC_SRC_SURFACE_STATE_CMD(); 3245 3246 static const size_t dwSize = 6; 3247 static const size_t byteSize = 24; 3248 }; 3249 3250 //! 3251 //! \brief VDENC_WALKER_STATE 3252 //! \details 3253 //! This command provides the macroblock start location for the VDEnc 3254 //! walker. Current programming to always have this command at the frame 3255 //! level, hence the macroblock X,Y location need to be programmed to 0,0 to 3256 //! always start at frame origin. Once the hardware receives this command 3257 //! packet, it internally starts the VDEnc pipeline. This should be the last 3258 //! command that is programmed for the VDEnc pipeline. 3259 //! 3260 //! This command is programmed per super-slice. The X location always needs 3261 //! to be programmed to 0. The Y location needs to be programmed to the 3262 //! starting point of the current super-slice. The programming needs to 3263 //! ensure that all super-slices are contiguous. It is illegal to have gaps 3264 //! between the super-slices. 3265 //! 3266 struct VDENC_WALKER_STATE_CMD 3267 { 3268 union 3269 { 3270 //!< DWORD 0 3271 struct 3272 { 3273 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3274 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3275 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3276 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3277 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3278 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3279 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3280 }; 3281 uint32_t Value; 3282 } DW0; 3283 union 3284 { 3285 //!< DWORD 1 3286 struct 3287 { 3288 uint32_t MbLcuStartYPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< MB/LCU Start Y Position 3289 uint32_t Reserved41 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 3290 uint32_t MbLcuStartXPosition : __CODEGEN_BITFIELD(16, 24) ; //!< MB/LCU Start X Position 3291 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 27) ; //!< Reserved 3292 uint32_t FirstSuperSlice : __CODEGEN_BITFIELD(28, 28) ; //!< First Super Slice 3293 uint32_t Reserved61 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3294 }; 3295 uint32_t Value; 3296 } DW1; 3297 union 3298 { 3299 //!< DWORD 2 3300 struct 3301 { 3302 uint32_t NextsliceMbStartYPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSlice MB Start Y Position 3303 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 3304 uint32_t NextsliceMbLcuStartXPosition : __CODEGEN_BITFIELD(16, 25) ; //!< NextSlice MB/LCU Start X Position 3305 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 3306 }; 3307 uint32_t Value; 3308 } DW2; 3309 union 3310 { 3311 //!< DWORD 3 3312 struct 3313 { 3314 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD( 0, 2) ; //!< Log 2 Weight Denom Luma 3315 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 3316 uint32_t HevcLog2WeightDemonLuma : __CODEGEN_BITFIELD( 4, 6) ; //!< HevcLog2WeightDemonLuma 3317 uint32_t Reserved78 : __CODEGEN_BITFIELD( 7, 8) ; //!< Reserved 3318 uint32_t NumParEngine : __CODEGEN_BITFIELD( 9, 10) ; //!< NUM_PAR_ENGINE 3319 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 23) ; //!< Reserved 3320 uint32_t TileNumber : __CODEGEN_BITFIELD(24, 31) ; //!< Tile number 3321 }; 3322 uint32_t Value; 3323 } DW3; 3324 union 3325 { 3326 //!< DWORD 4 3327 struct 3328 { 3329 uint32_t TileStartCtbY : __CODEGEN_BITFIELD( 0, 15) ; //!< Tile Start CTB-Y 3330 uint32_t TileStartCtbX : __CODEGEN_BITFIELD(16, 31) ; //!< Tile Start CTB-X 3331 }; 3332 uint32_t Value; 3333 } DW4; 3334 union 3335 { 3336 //!< DWORD 5 3337 struct 3338 { 3339 uint32_t TileWidth : __CODEGEN_BITFIELD( 0, 15) ; //!< Tile Width 3340 uint32_t TileHeight : __CODEGEN_BITFIELD(16, 31) ; //!< Tile Height 3341 }; 3342 uint32_t Value; 3343 } DW5; 3344 union 3345 { 3346 //!< DWORD 6 3347 struct 3348 { 3349 uint32_t StreaminOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Streamin Offset enable 3350 uint32_t Reserved193 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3351 uint32_t TileStreaminOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Streamin Offset 3352 }; 3353 uint32_t Value; 3354 } DW6; 3355 union 3356 { 3357 //!< DWORD 7 3358 struct 3359 { 3360 uint32_t RowStoreOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Row store Offset enable 3361 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3362 uint32_t TileRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Rowstore Offset 3363 }; 3364 uint32_t Value; 3365 } DW7; 3366 union 3367 { 3368 //!< DWORD 8 3369 struct 3370 { 3371 uint32_t TileStreamoutOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Tile streamout offset enable 3372 uint32_t Reserved257 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3373 uint32_t TileStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile streamout offset 3374 }; 3375 uint32_t Value; 3376 } DW8; 3377 union 3378 { 3379 //!< DWORD 9 3380 struct 3381 { 3382 uint32_t LcuStreamOutOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< LCU stream out offset enable 3383 uint32_t Reserved289 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 3384 uint32_t TileLcuStreamOutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile LCU stream out offset 3385 }; 3386 uint32_t Value; 3387 } DW9; 3388 3389 //! \name Local enumerations 3390 3391 enum SUBOPB 3392 { 3393 SUBOPB_VDENCWALKERSTATE = 7, //!< No additional details 3394 }; 3395 3396 enum SUBOPA 3397 { 3398 SUBOPA_UNNAMED0 = 0, //!< No additional details 3399 }; 3400 3401 enum OPCODE 3402 { 3403 OPCODE_VDENCPIPE = 1, //!< No additional details 3404 }; 3405 3406 enum PIPELINE 3407 { 3408 PIPELINE_MFXCOMMON = 2, //!< No additional details 3409 }; 3410 3411 enum COMMAND_TYPE 3412 { 3413 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3414 }; 3415 3416 //! \name Initializations 3417 3418 //! \brief Explicit member initialization function 3419 VDENC_WALKER_STATE_CMD(); 3420 3421 static const size_t dwSize = 10; 3422 static const size_t byteSize = 40; 3423 }; 3424 3425 }; 3426 3427 #pragma pack() 3428 3429 #endif // __MHW_VDBOX_VDENC_HWCMD_G11_X_H__ 3430