1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_mfx_hwcmd_g9_skl.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g9_skl as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_VDBOX_MFX_HWCMD_G9_SKL_H__ 29 #define __MHW_VDBOX_MFX_HWCMD_G9_SKL_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_vdbox_mfx_g9_skl 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH( x ) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MFX_QM_STATE 50 //! \details 51 //! This is a common state command for AVC encoder modes. For encoder, it 52 //! represents both the forward QM matrices as well as the decoding QM 53 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 54 //! application are being sent to the hardware. The driver is responsible 55 //! for determining the final set of scaling lists to be used for decoding 56 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 57 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 58 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 59 //! order. But the Forward Q scaling lists are sent in column-wise raster 60 //! order (column-by-column) to simplify the H/W. Driver will perform all 61 //! the scan order conversion for both ForwardQ and IQ. 62 //! 63 struct MFX_QM_STATE_CMD 64 { 65 union 66 { 67 //!< DWORD 0 68 struct 69 { 70 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 71 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 72 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 73 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 74 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 75 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 76 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 77 }; 78 uint32_t Value; 79 } DW0; 80 union 81 { 82 //!< DWORD 1 83 struct 84 { 85 uint32_t Avc : __CODEGEN_BITFIELD( 0, 1) ; //!< AVC, AVC- Decoder Only 86 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, AVC- Decoder Only 87 } Obj0; 88 struct 89 { 90 uint32_t Mpeg2 : __CODEGEN_BITFIELD( 0, 1) ; //!< MPEG2, MPEG2- Decoder Only 91 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, MPEG2- Decoder Only 92 } Obj1; 93 struct 94 { 95 uint32_t Jpeg : __CODEGEN_BITFIELD( 0, 1) ; //!< JPEG, JPEG- Encoder Only 96 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 97 }Obj2; 98 uint32_t Value; 99 } DW1; 100 101 uint32_t ForwardQuantizerMatrix[16]; //!< Forward Quantizer Matrix 102 103 //! \name Local enumerations 104 105 enum SUBOPCODE_B 106 { 107 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 108 }; 109 110 enum SUBOPCODE_A 111 { 112 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 113 }; 114 115 enum MEDIA_COMMAND_OPCODE 116 { 117 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 118 }; 119 120 enum PIPELINE 121 { 122 PIPELINE_MFXMULTIDW = 2, //!< No additional details 123 }; 124 125 enum COMMAND_TYPE 126 { 127 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 128 }; 129 130 //! \brief AVC 131 //! \details 132 //! <b>For AVC QM Type</b>: This field specifies which Quantizer Matrix is 133 //! loaded. 134 enum AVC 135 { 136 AVC_AVC_4X_4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 137 AVC_AVC_4X_4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 138 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 139 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 140 }; 141 142 //! \brief MPEG2 143 //! \details 144 //! <b>For MPEG2 QM Type</b>: This field specifies which Quantizer Matrix is 145 //! loaded. 146 enum MPEG2 147 { 148 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 149 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 150 }; 151 152 //! \brief JPEG 153 //! \details 154 //! <b> For JPEG QM Type</b>:This field specifies which Quantizer Matrix is 155 //! loaded. 156 enum JPEG 157 { 158 JPEG_JPEGLUMAYQUANTIZERMATRIXORR = 0, //!< No additional details 159 JPEG_JPEGCHROMACBQUANTIZERMATRIXORG = 1, //!< No additional details 160 JPEG_JPEGCHROMACRQUANTIZERMATRIXORB = 2, //!< No additional details 161 }; 162 163 //! \name Initializations 164 165 //! \brief Explicit member initialization function 166 MFX_QM_STATE_CMD(); 167 168 static const size_t dwSize = 18; 169 static const size_t byteSize = 72; 170 }; 171 172 //! 173 //! \brief MFX_FQM_STATE 174 //! \details 175 //! This is a common state command for AVC encoder modes. For encoder, it 176 //! represents both the forward QM matrices as well as the decoding QM 177 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 178 //! application are being sent to the hardware. The driver is responsible 179 //! for determining the final set of scaling lists to be used for decoding 180 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 181 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 182 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 183 //! order. But the Forward Q scaling lists are sent in column-wise raster 184 //! order (column-by-column) to simplify the H/W. Driver will perform all 185 //! the scan order conversion for both ForwardQ and IQ. 186 //! 187 struct MFX_FQM_STATE_CMD 188 { 189 union 190 { 191 //!< DWORD 0 192 struct 193 { 194 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 195 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 196 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 197 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 198 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 199 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 200 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 201 }; 202 uint32_t Value; 203 } DW0; 204 union 205 { 206 //!< DWORD 1 207 struct 208 { 209 uint32_t Avc : __CODEGEN_BITFIELD( 0, 1) ; //!< AVC, AVC- Decoder Only 210 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, AVC- Decoder Only 211 } Obj0; 212 struct 213 { 214 uint32_t Mpeg2 : __CODEGEN_BITFIELD( 0, 1) ; //!< MPEG2, MPEG2- Decoder Only 215 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, MPEG2- Decoder Only 216 } Obj1; 217 struct 218 { 219 uint32_t Jpeg : __CODEGEN_BITFIELD( 0, 1) ; //!< JPEG, JPEG- Encoder Only 220 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 221 }Obj2; 222 uint32_t Value; 223 } DW1; 224 225 uint32_t ForwardQuantizerMatrix[32]; //!< Forward Quantizer Matrix 226 227 //! \name Local enumerations 228 229 enum SUBOPCODE_B 230 { 231 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 232 }; 233 234 enum SUBOPCODE_A 235 { 236 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 237 }; 238 239 enum MEDIA_COMMAND_OPCODE 240 { 241 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 242 }; 243 244 enum PIPELINE 245 { 246 PIPELINE_MFXMULTIDW = 2, //!< No additional details 247 }; 248 249 enum COMMAND_TYPE 250 { 251 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 252 }; 253 254 //! \brief AVC 255 //! \details 256 //! <b>For AVC QM Type</b>: This field specifies which Quantizer Matrix is 257 //! loaded. 258 enum AVC 259 { 260 AVC_AVC_4X_4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 261 AVC_AVC_4X_4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 262 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 263 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 264 }; 265 266 //! \brief MPEG2 267 //! \details 268 //! <b>For MPEG2 QM Type</b>: This field specifies which Quantizer Matrix is 269 //! loaded. 270 enum MPEG2 271 { 272 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 273 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 274 }; 275 276 //! \brief JPEG 277 //! \details 278 //! <b> For JPEG QM Type</b>:This field specifies which Quantizer Matrix is 279 //! loaded. 280 enum JPEG 281 { 282 JPEG_JPEGLUMAYQUANTIZERMATRIXORR = 0, //!< No additional details 283 JPEG_JPEGCHROMACBQUANTIZERMATRIXORG = 1, //!< No additional details 284 JPEG_JPEGCHROMACRQUANTIZERMATRIXORB = 2, //!< No additional details 285 }; 286 287 //! \name Initializations 288 289 //! \brief Explicit member initialization function 290 MFX_FQM_STATE_CMD(); 291 292 static const size_t dwSize = 34; 293 static const size_t byteSize = 136; 294 }; 295 296 //! 297 //! \brief MFX_PIPE_MODE_SELECT 298 //! \details 299 //! Specifies which codec and hardware module is being used to encode/decode 300 //! the video data, on a per-frame basis. The MFX_PIPE_MODE_SELECT command 301 //! specifies which codec and hardware module is being used to encode/decode 302 //! the video data, on a per-frame basis. It also configures the hardware 303 //! pipeline according to the active encoder/decoder operating mode for 304 //! encoding/decoding the current picture. Commands issued specifically for 305 //! AVC and MPEG2 are ignored when VC1 is the active codec. 306 //! 307 struct MFX_PIPE_MODE_SELECT_CMD 308 { 309 union 310 { 311 //!< DWORD 0 312 struct 313 { 314 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 315 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 316 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 317 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPA 318 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26) ; //!< OPCODE 319 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 320 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 321 }; 322 uint32_t Value; 323 } DW0; 324 union 325 { 326 //!< DWORD 1 327 struct 328 { 329 uint32_t StandardSelect : __CODEGEN_BITFIELD( 0, 3) ; //!< STANDARD_SELECT 330 uint32_t CodecSelect : __CODEGEN_BITFIELD( 4, 4) ; //!< CODEC_SELECT 331 uint32_t StitchMode : __CODEGEN_BITFIELD( 5, 5) ; //!< STITCH_MODE 332 uint32_t FrameStatisticsStreamoutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< FRAME_STATISTICS_STREAMOUT_ENABLE 333 uint32_t ScaledSurfaceEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< SCALED_SURFACE_ENABLE 334 uint32_t PreDeblockingOutputEnablePredeblockoutenable : __CODEGEN_BITFIELD( 8, 8) ; //!< PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 335 uint32_t PostDeblockingOutputEnablePostdeblockoutenable : __CODEGEN_BITFIELD( 9, 9) ; //!< POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 336 uint32_t StreamOutEnable : __CODEGEN_BITFIELD(10, 10) ; //!< STREAM_OUT_ENABLE 337 uint32_t PicErrorStatusReportEnable : __CODEGEN_BITFIELD(11, 11) ; //!< PIC_ERRORSTATUS_REPORT_ENABLE 338 uint32_t DeblockerStreamOutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< DEBLOCKER_STREAM_OUT_ENABLE 339 uint32_t VdencMode : __CODEGEN_BITFIELD(13, 13) ; //!< VDENC_MODE 340 uint32_t StandaloneVdencModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< STANDALONE_VDENC_MODE_ENABLE 341 uint32_t DecoderModeSelect : __CODEGEN_BITFIELD(15, 16) ; //!< DECODER_MODE_SELECT 342 uint32_t DecoderShortFormatMode : __CODEGEN_BITFIELD(17, 17) ; //!< DECODER_SHORT_FORMAT_MODE 343 uint32_t ExtendedStreamOutEnable : __CODEGEN_BITFIELD(18, 18) ; //!< Extended stream out enable 344 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 345 }; 346 uint32_t Value; 347 } DW1; 348 union 349 { 350 //!< DWORD 2 351 struct 352 { 353 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 354 uint32_t VdsIldbCalculation : __CODEGEN_BITFIELD( 3, 3) ; //!< VDS_ILDB_CALCULATION 355 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 5) ; //!< Reserved 356 uint32_t ClockGateEnableAtSliceLevel : __CODEGEN_BITFIELD( 6, 6) ; //!< CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 357 uint32_t Reserved71 : __CODEGEN_BITFIELD( 7, 9) ; //!< Reserved 358 uint32_t MpcPref08X8DisableFlagDefault0 : __CODEGEN_BITFIELD(10, 10) ; //!< MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 359 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13) ; //!< Reserved 360 uint32_t Vlf720IOddHeightInVc1Mode : __CODEGEN_BITFIELD(14, 14) ; //!< VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 361 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 362 uint32_t VmbSvcTlbDummyFetchDisableForPerformance : __CODEGEN_BITFIELD(27, 27) ; //!< VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 363 uint32_t VmbSvcMvReplicationFor8X8EnableErrorHandling : __CODEGEN_BITFIELD(28, 28) ; //!< VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 364 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 365 }; 366 uint32_t Value; 367 } DW2; 368 union 369 { 370 //!< DWORD 3 371 struct 372 { 373 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 374 }; 375 uint32_t Value; 376 } DW3; 377 union 378 { 379 //!< DWORD 4 380 struct 381 { 382 uint32_t Reserved128 ; //!< Reserved 383 }; 384 uint32_t Value; 385 } DW4; 386 387 //! \name Local enumerations 388 389 enum SUBOPB 390 { 391 SUBOPB_MFXPIPEMODESELECT = 0, //!< No additional details 392 }; 393 394 enum SUBOPA 395 { 396 SUBOPA_UNNAMED0 = 0, //!< No additional details 397 }; 398 399 enum OPCODE 400 { 401 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 402 }; 403 404 enum PIPELINE 405 { 406 PIPELINE_MFXCOMMON = 2, //!< No additional details 407 }; 408 409 enum COMMAND_TYPE 410 { 411 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 412 }; 413 414 enum STANDARD_SELECT 415 { 416 STANDARD_SELECT_MPEG2 = 0, //!< No additional details 417 STANDARD_SELECT_VC1 = 1, //!< No additional details 418 STANDARD_SELECT_AVC = 2, //!< Covers both AVC and MVC 419 STANDARD_SELECT_JPEG = 3, //!< No additional details 420 STANDARD_SELECT_SVC = 4, //!< No additional details 421 STANDARD_SELECT_VP8 = 5, //!< Decoder starting from BDW, Encoder starting from CHV 422 STANDARD_SELECT_UVLD = 15, //!< SW decoder w/ embedded micro-controller and co-processor 423 }; 424 425 enum CODEC_SELECT 426 { 427 CODEC_SELECT_DECODE = 0, //!< No additional details 428 CODEC_SELECT_ENCODE = 1, //!< Valid only if StandardSel is AVC, MPEG2 and SVC) 429 }; 430 431 enum STITCH_MODE 432 { 433 STITCH_MODE_NOTINSTITCHMODE = 0, //!< No additional details 434 STITCH_MODE_INTHESPECIALSTITCHMODE = 1, //!< This mode can be used for any Codec as long as bitfield conditions are met. 435 }; 436 437 //! \brief FRAME_STATISTICS_STREAMOUT_ENABLE 438 //! \details 439 //! This field controls the frame level statistics streamout from the PAK. 440 //! <p><b>Note</b>: This field needs to be always "Enabled" in VD_Enc 441 //! mode. In case of non-VDEnc mode, 442 //! this can be used to control the frame statistics output from the 443 //! PAK.</p> 444 enum FRAME_STATISTICS_STREAMOUT_ENABLE 445 { 446 FRAME_STATISTICS_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 447 FRAME_STATISTICS_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 448 }; 449 450 //! \brief SCALED_SURFACE_ENABLE 451 //! \details 452 //! This field indicates if the scaled surface is enabled. This field 453 //! enables the 4x HME downscalar of the reconstructed image. Only 454 //! supported for AVC and VP8 formats. 455 enum SCALED_SURFACE_ENABLE 456 { 457 SCALED_SURFACE_ENABLE_DISABLE = 0, //!< No additional details 458 SCALED_SURFACE_ENABLE_ENABLE = 1, //!< No additional details 459 }; 460 461 //! \brief PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 462 //! \details 463 //! This field controls the output write for the reconstructed pixels BEFORE 464 //! the deblocking filter. 465 enum PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 466 { 467 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 468 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 469 }; 470 471 //! \brief POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 472 //! \details 473 //! This field controls the output write for the reconstructed pixels AFTER 474 //! the deblocking filter.In MPEG2 decoding mode, if this is enabled, VC1 475 //! deblocking filter is used. 476 enum POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 477 { 478 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 479 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 480 }; 481 482 //! \brief STREAM_OUT_ENABLE 483 //! \details 484 //! This field controls whether the macroblock parameter stream-out is 485 //! enabled during VLD decoding for transcoding purpose. 486 enum STREAM_OUT_ENABLE 487 { 488 STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 489 STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 490 }; 491 492 //! \brief PIC_ERRORSTATUS_REPORT_ENABLE 493 //! \details 494 //! <p>This field control whether the error/status reporting is enable or 495 //! not.0: Disable1: EnableIn decoder modes: Error reporting is written out 496 //! once per frame. The Error Report frame ID listed in DW3 along with the 497 //! VLD/IT error status bits are packed into one cache and written to the 498 //! "Decoded Picture Error/Status Buffer address" listed in the 499 //! MFX_PIPE_BUF_ADDR_STATE Command. Note: driver shall program different 500 //! error buffer addresses between pictrues; otherwise, hardware might 501 //! overwrite previous written data if driver does not read it fast 502 //! enough.In encoder modes: Not used</p> 503 //! <p>Please refer to "Media VDBOX -> Video Codec -> Other Codec 504 //! Functions -> MFX Error Handling -> Decoder" session for the output 505 //! format.</p> 506 enum PIC_ERRORSTATUS_REPORT_ENABLE 507 { 508 PIC_ERRORSTATUS_REPORT_ENABLE_DISABLE = 0, //!< No additional details 509 PIC_ERRORSTATUS_REPORT_ENABLE_ENABLE = 1, //!< No additional details 510 }; 511 512 //! \brief DEBLOCKER_STREAM_OUT_ENABLE 513 //! \details 514 //! This field indicates if Deblocker information is going to be streamout 515 //! during VLD decoding. 516 //! For AVC, it is needed to enable the deblocker streamout as the AVC 517 //! Disable_DLKFilterIdc is a slice level parameters. Driver needs to 518 //! determine ahead of time if at least one slice of the current frame/ has 519 //! deblocker ON. 520 //! For SVC, there are two deblocking control streamout buffers 521 //! (specified in MFX_BUF_ADDR State Command). This field is still 522 //! associated with the slice level SVC Disable.DLK_Filter_Idc. 523 enum DEBLOCKER_STREAM_OUT_ENABLE 524 { 525 DEBLOCKER_STREAM_OUT_ENABLE_DISABLE = 0, //!< Disable streamout of deblocking control information for standalone deblocker operation.It needs other fields to determine one or two SVC deblocking surface streamout (Post Deblocking Output Enable, Pre Deblocking Output Enable, interlayer idc and regular deblock idc). 526 DEBLOCKER_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 527 }; 528 529 //! \brief VDENC_MODE 530 //! \details 531 //! This field indicates if PAK is working in legacy MBEnc mode or the VDEnc 532 //! mode. 533 enum VDENC_MODE 534 { 535 VDENC_MODE_MBENCMODE = 0, //!< PAK is working in legacy mode 536 VDENC_MODE_VDENCMODE = 1, //!< PAK is working in VDEnc mode 537 }; 538 539 //! \brief STANDALONE_VDENC_MODE_ENABLE 540 //! \details 541 //! This field indicates to PAK if this is standalone VDEnc mode. This is 542 //! primarily a validation mode. 543 enum STANDALONE_VDENC_MODE_ENABLE 544 { 545 STANDALONE_VDENC_MODE_ENABLE_VDENCPAK = 0, //!< No additional details 546 STANDALONE_VDENC_MODE_ENABLE_PAKONLY = 1, //!< No additional details 547 }; 548 549 //! \brief DECODER_MODE_SELECT 550 //! \details 551 //! Each coding standard supports two entry points: VLD entry point and IT 552 //! (IDCT) entry point. This field selects which one is in use.This field is 553 //! only valid if Codec Select is 0 (decoder). 554 enum DECODER_MODE_SELECT 555 { 556 DECODER_MODE_SELECT_VLDMODE = 0, //!< All codec minimum must support this mode Configure the MFD Engine for VLD ModeNote: All codec minimum must support this mode 557 DECODER_MODE_SELECT_ITMODE = 1, //!< Configure the MFD Engine for IT ModeNote: Only VC1 and MPEG2 support this mode 558 DECODER_MODE_SELECT_DEBLOCKERMODE = 2, //!< Configure the MFD Engine for Standalone Deblocker Mode. Require streamout AVC edge control information from preceeding decoding pass.Note: [HSW, EXCLUDE(HSW:GT3:A, HSW:GT3:B, HSW:GT2:B)] Only AVC, MPEG2 and SVC are supported. 559 DECODER_MODE_SELECT_INTERLAYERMODE = 3, //!< Configure the MFX Engine for standalone SVC interlayer upsampling for motion info, residual and reconstructed pixel. Require information being streamout from the preceding encoding and decoding pass of a reference layer.> 560 }; 561 562 //! \brief DECODER_SHORT_FORMAT_MODE 563 //! \details 564 //! For IT mode, this bit must be 0. 565 enum DECODER_SHORT_FORMAT_MODE 566 { 567 DECODER_SHORT_FORMAT_MODE_SHORTFORMATDRIVERINTERFACE = 0, //!< AVC/VC1/MVC/SVC/VP8 Short Format Mode is in useNote: There is no Short Format for SVC and VP8 yet, so this field must be set to 1 for SVC and VP8. 568 DECODER_SHORT_FORMAT_MODE_LONGFORMATDRIVERINTERFACE = 1, //!< AVC/VC1/MVC/SVC/VP8 Long Format Mode is in use. 569 }; 570 571 //! \brief VDS_ILDB_CALCULATION 572 //! \details 573 //! This bit forces all MB into INTRA MBs before doing ILDB control 574 //! generation in VDS. 575 enum VDS_ILDB_CALCULATION 576 { 577 VDS_ILDB_CALCULATION_DISABLE = 0, //!< Use original definition for ILDB calculation. 578 VDS_ILDB_CALCULATION_ENABLE = 1, //!< Force neighbor Intra MB = 1 on ILDB BS calculation. 579 }; 580 581 //! \brief CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 582 //! \details 583 //! BitFieldDesc: 584 enum CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 585 { 586 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_DISABLE = 0, //!< Disable Slice-level Clock gating, Unit-level Clock gating will apply 587 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_ENABLE = 1, //!< Enable Slice-level Clock gating, overrides any Unit level Clock gating 588 }; 589 590 enum MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 591 { 592 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_DISABLE = 0, //!< No additional details 593 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_ENABLE = 1, //!< No additional details 594 }; 595 596 //! \brief VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 597 //! \details 598 //! This bit indicates VLF write out VC1 picture with odd height (in MBs). 599 enum VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 600 { 601 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_DISABLE = 0, //!< No additional details 602 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ENABLE = 1, //!< 720i Enable 603 }; 604 605 //! \brief VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 606 //! \details 607 //! This bit disables TLB dummy fetch in SVC mode in VMB. 608 enum VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 609 { 610 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_ENABLE = 0, //!< Enable VMB TLB Dummy Fetch for Performance 611 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_DISABLE = 1, //!< Disable VMB TLB Dummy Fetch 612 }; 613 614 //! \brief VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 615 //! \details 616 //! This bit enables Motion Vector replication on 8x8 level during SVC mode 617 //! for error handling. 618 enum VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 619 { 620 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_DISABLE = 0, //!< Disable MV 8x8 replication in SVC mode 621 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_ENABLE = 1, //!< Enable MV 8x8 Replication in SVC Mode 622 }; 623 624 //! \brief PIC_STATUSERROR_REPORT_ID 625 //! \details 626 //! In decoder modes: Error reporting is written out once per frame. This 627 //! field along with the VLD error status bits are packed into one cache and 628 //! written to the memory location specified by "Decoded Picture 629 //! Error/Status Buffer address" listed in the MFX_PIPE_BUF_ADDR_STATE 630 //! Command. 631 enum PIC_STATUSERROR_REPORT_ID 632 { 633 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 634 }; 635 636 //! \name Initializations 637 638 //! \brief Explicit member initialization function 639 MFX_PIPE_MODE_SELECT_CMD(); 640 641 static const size_t dwSize = 5; 642 static const size_t byteSize = 20; 643 }; 644 645 //! 646 //! \brief MFX_SURFACE_STATE 647 //! \details 648 //! This command is common for all encoding/decoding modes, to specify the 649 //! uncompressed YUV picture (i.e. destination surface) or intermediate 650 //! streamout in/out surface (e.g. coefficient/residual) (field, frame or 651 //! interleaved frame) format for reading and writing: Uncompressed, 652 //! original input picture to be encoded 653 //! Reconstructed non-filtered/filtered display picturec(becoming reference 654 //! pictures as well for subsequent temporal inter-prediction) 655 //! Residual in SVC 656 //! Reconstructed Intra pixel in SVC 657 //! CoeffPred in SVC 658 //! Since there is only one media surface state being active during the 659 //! entire encoding/decoding process, all the uncompressed/reconstructed 660 //! pictures are defined to have the same surface state. For each media 661 //! object call (decoding or encoding), multiple SVC surfaces can be active 662 //! concurrently, to distinguish among them, a surfaceID is added to 663 //! specify for each type of surface. The primary difference among picture 664 //! surface states is their individual programmed base addresses, which are 665 //! provided by other state commands and not included in this command. MFX 666 //! engine is making the association of surface states and corresponding 667 //! buffer base addresses. MFX engine currently supports only one media 668 //! surface type for video and that is the NV12 (Planar YUV420 with 669 //! interleaved U (Cb) and V (Cr). For optimizing memory efficiency based on 670 //! access patterns, only TileY is supported. For JPEG decoder, only IMC1 671 //! and IMC3 are supported. Pitch can be wider than the Picture Width in 672 //! pixels and garbage will be there at the end of each line. The following 673 //! describes all the different formats that are supported and not supported 674 //! in Gen7 MFX : NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V 675 //! offset is set to 0 (the only format supported for video codec); vertical 676 //! UV offset is MB aligned; UV xoffsets = 0. JPEG does not support NV12 677 //! format because non-interleave JPEG has performance issue with partial 678 //! write (in interleaved UV format) 679 //! IMC 1 & 3 - Full Pitch, U and V are separate plane; (JPEG only; U 680 //! plane + garbage first in full pitch followed by V plane + garbage in 681 //! full pitch). U and V vertical offsets are block aligned; U and V xoffset 682 //! = 0; there is no gap between Y, U and V planes. IMC1 and IMC3 are 683 //! different by a swap of U and V. This is the only format supported in 684 //! JPEG for all video subsampling types (4:4:4, 4:2:2 and 4:2:0) 685 //! We are not supporting IMC 2 & 4 - Full Pitch, U and V are separate 686 //! plane (JPEG only; U plane first in full pitch followed by V plane in 687 //! full pitch - U and V plane are side-by-side). U and V vertical offsets 688 //! are 16-pixel aligned; V xoffset is half-pitch aligned; U xoffset is 0; 689 //! there is no gap between Y, U and V planes. IMC2 and IMC4 are different 690 //! by a swap of U and V. 691 //! We are not supporting YV12 - half pitch for each U and V plane, and 692 //! separate planes for Y, U and V (U plane first in half pitch followed by 693 //! V plane in half pitch). For YV12, U and V vertical offsets are block 694 //! aligned; U and V xoffset = 0; there is no gap between Y, U and V planes 695 //! Note that the following data structures are not specified through the 696 //! media surface state 1D buffers for row-store and other miscellaneous 697 //! information. 698 //! 2D buffers for per-MB data-structures (e.g. DMV biffer, MB info record, 699 //! ILDB Control and Tcoeff/Stocoeff). 700 //! This surface state here is identical to the Surface State for 701 //! deinterlace and sample_8x8 messages described in the Shared Function 702 //! Volume and Sampler Chapter. For non pixel data, such as row stores, 703 //! indirect data (Compressed Slice Data, AVC MV record, Coeff record and 704 //! AVC ILDB record) and streamin/out and output compressed bitstream, a 705 //! linear buffer is employed. For row stores, the H/W is designed to 706 //! guarantee legal memory accesses (read and write). For the remaining 707 //! cases, indirect object base address, indirect object address upper 708 //! bound, object data start address (offset) and object data length are 709 //! used to fully specified their corresponding buffer. This mechanism is 710 //! chosen over the pixel surface type because of their variable record 711 //! sizes. All row store surfaces are linear surface. Their addresses are 712 //! programmed in Pipe_Buf_Base_State or Bsp_Buf_Base_Addr_State 713 //! 714 //! VC1 I picture scaling: Even though VC1 allows I reconstructed picture 715 //! scaling (via RESPIC), as such scaling is only allowed at I picture. All 716 //! subsequent P (and B) pictures must have the same picture dimensions with 717 //! the preceding I picture. Therefore, all reference pictures for P or B 718 //! picture can share the same surface state with the current P and B 719 //! picture. Note : H/W is not processing RESPIC. Application is no longer 720 //! expecting intel decoder pipelineand kernel to perform this function, it 721 //! is going to be done in the video post-processing scaler or display 722 //! controller scale as a separate step and controller. 723 //! 724 //! All video codec surfaces must be NV12 Compliant, except JPEG. U/V 725 //! vertical must be MB aligned for all video codec (further contrained for 726 //! field picture), but JPEG can be block aligned. All video codec and JPEG 727 //! uses Tiled - Y format only, for uncompressed pixel surfaces. 728 //! 729 //! Even for JPEG planar 420 surface, application may provide only 1 730 //! buffers, but there is still only one single surface state for all of 731 //! them. If IMC equal to 1, 2, 3 or 4, U and V have the pitch same as Y. 732 //! And U and V will have different offset, each offset is block aligned. 733 //! 734 struct MFX_SURFACE_STATE_CMD 735 { 736 union 737 { 738 //!< DWORD 0 739 struct 740 { 741 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 742 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 743 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 744 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPA 745 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26) ; //!< OPCODE 746 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 747 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 748 }; 749 uint32_t Value; 750 } DW0; 751 union 752 { 753 //!< DWORD 1 754 struct 755 { 756 uint32_t SurfaceId : __CODEGEN_BITFIELD( 0, 3) ; //!< SURFACE_ID 757 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 758 }; 759 uint32_t Value; 760 } DW1; 761 union 762 { 763 //!< DWORD 2 764 struct 765 { 766 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< Cr(V)/Cb(U) Pixel Offset V Direction 767 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 768 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 769 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 770 }; 771 uint32_t Value; 772 } DW2; 773 union 774 { 775 //!< DWORD 3 776 struct 777 { 778 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 779 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 780 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 781 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 782 uint32_t Reserved116 : __CODEGEN_BITFIELD(20, 26) ; //!< Reserved 783 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(27, 27) ; //!< INTERLEAVE_CHROMA_ 784 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_FORMAT 785 }; 786 uint32_t Value; 787 } DW3; 788 union 789 { 790 //!< DWORD 4 791 struct 792 { 793 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) 794 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 795 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for U(Cb) 796 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 797 }; 798 uint32_t Value; 799 } DW4; 800 union 801 { 802 //!< DWORD 5 803 struct 804 { 805 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 15) ; //!< Y Offset for V(Cr) 806 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V(Cr) 807 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 808 }; 809 uint32_t Value; 810 } DW5; 811 812 //! \name Local enumerations 813 814 enum SUBOPB 815 { 816 SUBOPB_UNNAMED1 = 1, //!< No additional details 817 }; 818 819 enum SUBOPA 820 { 821 SUBOPA_UNNAMED0 = 0, //!< No additional details 822 }; 823 824 enum OPCODE 825 { 826 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 827 }; 828 829 enum PIPELINE 830 { 831 PIPELINE_MFXCOMMON = 2, //!< No additional details 832 }; 833 834 enum COMMAND_TYPE 835 { 836 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 837 }; 838 839 enum SURFACE_ID 840 { 841 SURFACE_ID_DECODEDPICTUREANDREFERENCEPICTURES_SVCUPSAMPLINGSTREAMOUTRECONSTRUCTEDPIXELSCOEFFPREDUPPERLAYERSIZE = 0, //!< 8-bit uncompressed data 842 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMOUTSURFACEUPPERLAYERSIZE = 1, //!< 16-bit uncompressed data 843 SURFACE_ID_SVCRECONSTRUCTEDPIXELANDCOEFFPREDUPSAMPLINGSTREAMINSURFACELOWERLAYERSIZE = 2, //!< 8-bit uncompressed data. 844 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMINSURFACELOWERLAYERSIZE = 3, //!< 16-bit uncompressed data 845 SURFACE_ID_SOURCEINPUTPICTUREENCODER = 4, //!< 8-bit uncompressed data 846 SURFACE_ID_RECONSTRUCTEDSCALEDREFERENCEPICTURE = 5, //!< 8-bit data 847 }; 848 849 //! \brief TILE_WALK 850 //! \details 851 //! (This field must be set to 1: TILEWALK_YMAJOR)This field specifies the 852 //! type of memory tiling (XMajor or YMajor) employed to tile this surface. 853 //! See Memory Interface Functions for details on memory tiling and 854 //! restrictions.This field is ignored when the surface is linear.This field 855 //! is ignored by MFX. Internally H/W is always treated this set to 1 for 856 //! all video codec and for JPEG. 857 enum TILE_WALK 858 { 859 TILE_WALK_XMAJOR = 0, //!< TILEWALK_XMAJOR 860 TILE_WALK_YMAJOR = 1, //!< TILEWALK_YMAJOR 861 }; 862 863 //! \brief TILED_SURFACE 864 //! \details 865 //! (This field must be set to TRUE: Tiled)This field specifies whether the 866 //! surface is tiled.This field is ignored by MFX 867 enum TILED_SURFACE 868 { 869 TILED_SURFACE_FALSE = 0, //!< Linear 870 TILED_SURFACE_TRUE = 1, //!< Tiled 871 }; 872 873 //! \brief INTERLEAVE_CHROMA_ 874 //! \details 875 //! This field indicates that the chroma fields are interleaved in a single 876 //! plane rather than stored as two separate planes. This field is only used 877 //! for PLANAR surface formats.For AVC/VC1/MPEG VLD and IT modes : set to 878 //! Enable to support interleave U/V only.For JPEG : set to Disable for all 879 //! formats (including 4:2:0) - because JPEG does not support NV12. (This 880 //! field is needed only if JPEG will support NV12; otherwise is ignored.) 881 enum INTERLEAVE_CHROMA_ 882 { 883 INTERLEAVE_CHROMA_DISABLE = 0, //!< No additional details 884 INTERLEAVE_CHROMA_ENABLE = 1, //!< No additional details 885 }; 886 887 //! \brief SURFACE_FORMAT 888 //! \details 889 //! Specifies the format of the surface. All of the Y and G channels will 890 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1.Usage: 891 //! For 420 planar YUV surface, use 4; for monochrome surfaces, use 12. For 892 //! monochrome surfaces, hardware ignores control fields for Chroma 893 //! planes.This field must be set to 4 - PLANAR_420_8, or 12 - Y8_UNORMNot 894 //! used for MFX, and is ignored. But for JPEG decoding, this field should 895 //! be programmed to the same format as JPEG_PIC_STATE. For video codec, it 896 //! should set to 4 always. 897 enum SURFACE_FORMAT 898 { 899 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 900 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 901 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 902 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 903 SURFACE_FORMAT_PLANAR_4208 = 4, //!< (NV12, IMC1,2,3,4, YV12) 904 SURFACE_FORMAT_PLANAR_4118 = 5, //!< Deinterlace Only 905 SURFACE_FORMAT_PLANAR_4228 = 6, //!< Deinterlace Only 906 SURFACE_FORMAT_STMMDNSTATISTICS = 7, //!< Deinterlace Only 907 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 Only 908 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 Only 909 SURFACE_FORMAT_R8B8UNORMCRCB = 10, //!< Sample_8x8 Only 910 SURFACE_FORMAT_R8UNORMCRCB = 11, //!< Sample_8x8 Only 911 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 Only 912 }; 913 914 //! \name Initializations 915 916 //! \brief Explicit member initialization function 917 MFX_SURFACE_STATE_CMD(); 918 919 static const size_t dwSize = 6; 920 static const size_t byteSize = 24; 921 }; 922 923 //! 924 //! \brief MFX_IND_OBJ_BASE_ADDR_STATE 925 //! \details 926 //! This state command provides the memory base addresses for all row 927 //! stores, StreamOut buffer and reconstructed picture output buffers 928 //! required by the MFD or MFC Engine (that are in addition to the row 929 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 930 //! reference picture buffers). This is a picture level state command and is 931 //! common among all codec standards and for both encoder and decoder 932 //! operating modes. However, some fields may only applicable to a specific 933 //! codec standard. All Pixel Surfaces (original, reference frame and 934 //! reconstructed frame) in the Encoder are programmed with the same surface 935 //! state (NV12 and TileY format), except each has its own frame buffer base 936 //! address. In the tile format, there is no need to provide buffer offset 937 //! for each slice; since from each MB address, the hardware can calculated 938 //! the corresponding memory location within the frame buffer directly. 939 //! 940 //! The MFX_IND_OBJ_BASE_ADDR command sets the memory base address pointers 941 //! for the corresponding Indirect Object Data Start Addresses (Offsets) 942 //! specified in each OBJECT commands. The characteristic of these indirect 943 //! object data is their variable size (per MB or per Slice). Hence, each 944 //! OBJECT command must specify the indirect object data offset from the 945 //! base address to start fetching or writing object data. 946 //! 947 //! While the use of base address is unconditional, the indirection can be 948 //! effectively disabled by setting the base address to zero. For decoder, 949 //! there are: 1 read-only per-slice indirect object in the BSD_OBJECT 950 //! Command, and 951 //! 2 read-only per-MB indirect objects in the IT_OBJECT Command. 952 //! For decoder: the Video Command Streamer (VCS) will perform the memory 953 //! access bound check automatically using the corresponding MFC Indirect 954 //! Object Access Upper Bound specification. If any access is at or beyond 955 //! the upper bound, zero value is returned. The request to memory is still 956 //! being sent, but the corresponding codec's BSD unit will detect this 957 //! condition and perform the zeroing return. If the Upper Bound is turned 958 //! off, the beyond bound request will return whatever on the bus (invalid 959 //! data). For encoder, there are: 1 read-only per-MB indirect object in 960 //! the PAK_OBJECT Command, and 961 //! 1 write-only per-slice indirect object in the PAK Slice_State Command 962 //! For encoder: whenever an out of bound address accessing request is 963 //! generated, VMX will detect such requests and snap the address to the 964 //! corresponding [indirect object base address + indirect data start 965 //! address]. VMX will return all 0s as the data to the requestor. 966 //! NotationDefinitionPhysicalAddress[n:m] Corresponding bits of a physical 967 //! graphics memory byte address (not mapped by a GTT) GraphicsAddress[n:m] 968 //! Corresponding bits of an absolute, virtual graphics memory byte address 969 //! (mapped by a GTT). 970 //! 971 struct MFX_IND_OBJ_BASE_ADDR_STATE_CMD 972 { 973 union 974 { 975 //!< DWORD 0 976 struct 977 { 978 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 979 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 980 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 981 uint32_t SubOpcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODEA 982 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMON_OPCODE 983 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 984 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 985 }; 986 uint32_t Value; 987 } DW0; 988 union 989 { 990 //!< DWORD 1 991 struct 992 { 993 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 994 uint32_t MfxIndirectBitstreamObjectBaseAddressDecoderAndStitchModes : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect Bitstream Object - Base Address (Decoder and Stitch Modes) 995 }; 996 uint32_t Value; 997 } DW1; 998 union 999 { 1000 //!< DWORD 2 1001 struct 1002 { 1003 uint32_t MfxIndirectBitstreamObjectDestinationAddressDecoderAndStitchModes4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect Bitstream Object - Destination Address (Decoder and Stitch Modes)[47:32] 1004 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1005 }; 1006 uint32_t Value; 1007 } DW2; 1008 union 1009 { 1010 //!< DWORD 3 1011 struct 1012 { 1013 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1014 uint32_t MfxIndirectBitstreamObjectbaseArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1015 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1016 uint32_t MfxIndirectBitstreamObjectTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1017 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1018 }; 1019 uint32_t Value; 1020 } DW3; 1021 union 1022 { 1023 //!< DWORD 4 1024 struct 1025 { 1026 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1027 uint32_t MfxIndirectBitstreamObjectAccessUpperBoundDecoderAndStitchModes : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect Bitstream Object - Access Upper Bound (Decoder and Stitch Modes) 1028 }; 1029 uint32_t Value; 1030 } DW4; 1031 union 1032 { 1033 //!< DWORD 5 1034 struct 1035 { 1036 uint32_t MfxIndirectBitstreamObjectUpperboundDecoderAndStitchModes4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect Bitstream Object UpperBound (Decoder and Stitch Modes)[47:32] 1037 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1038 }; 1039 uint32_t Value; 1040 } DW5; 1041 union 1042 { 1043 //!< DWORD 6 1044 struct 1045 { 1046 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1047 uint32_t MfxIndirectMvObjectBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect MV Object - Base Address 1048 }; 1049 uint32_t Value; 1050 } DW6; 1051 union 1052 { 1053 //!< DWORD 7 1054 struct 1055 { 1056 uint32_t MfxIndirectMvObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect MV Object Base Address [47:32] 1057 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1058 }; 1059 uint32_t Value; 1060 } DW7; 1061 union 1062 { 1063 //!< DWORD 8 1064 struct 1065 { 1066 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1067 uint32_t MfxIndirectMvObjectArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1068 uint32_t Reserved265 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1069 uint32_t MfxIndirectMvObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1070 uint32_t Reserved271 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1071 }; 1072 uint32_t Value; 1073 } DW8; 1074 union 1075 { 1076 //!< DWORD 9 1077 struct 1078 { 1079 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1080 uint32_t MfxIndirectMvObjectAccessUpperBound : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect MV Object Access Upper Bound 1081 }; 1082 uint32_t Value; 1083 } DW9; 1084 union 1085 { 1086 //!< DWORD 10 1087 struct 1088 { 1089 uint32_t MfxIndirectMvObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect MV Object UpperBound [47:32] 1090 uint32_t Reserved336 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1091 }; 1092 uint32_t Value; 1093 } DW10; 1094 union 1095 { 1096 //!< DWORD 11 1097 struct 1098 { 1099 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1100 uint32_t MfdIndirectItCoeffObjectBaseAddressDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-COEFF Object - Base Address (Decoder Only) 1101 }; 1102 uint32_t Value; 1103 } DW11; 1104 union 1105 { 1106 //!< DWORD 12 1107 struct 1108 { 1109 uint32_t MfdIndirectItCoeffObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-COEFF Object Base Address [47:32] 1110 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1111 }; 1112 uint32_t Value; 1113 } DW12; 1114 union 1115 { 1116 //!< DWORD 13 1117 struct 1118 { 1119 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1120 uint32_t MfdIndirectItCoeffObjectDesitnationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1121 uint32_t Reserved425 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1122 uint32_t MfdIndirectItCoeffTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1123 uint32_t Reserved431 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1124 }; 1125 uint32_t Value; 1126 } DW13; 1127 union 1128 { 1129 //!< DWORD 14 1130 struct 1131 { 1132 uint32_t Reserved448 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1133 uint32_t MfdIndirectItCoeffObjectAccessUpperBoundDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-COEFF Object - Access Upper Bound (Decoder Only) 1134 }; 1135 uint32_t Value; 1136 } DW14; 1137 union 1138 { 1139 //!< DWORD 15 1140 struct 1141 { 1142 uint32_t MfdIndirectItCoeffObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-COEFF Object UpperBound [47:32] 1143 uint32_t Reserved496 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1144 }; 1145 uint32_t Value; 1146 } DW15; 1147 union 1148 { 1149 //!< DWORD 16 1150 struct 1151 { 1152 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1153 uint32_t MfdIndirectItDblkObjectBaseAddressDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-DBLK Object - Base Address (Decoder Only) 1154 }; 1155 uint32_t Value; 1156 } DW16; 1157 union 1158 { 1159 //!< DWORD 17 1160 struct 1161 { 1162 uint32_t MfdIndirectItDblkObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-DBLK Object Base Address [47:32] 1163 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1164 }; 1165 uint32_t Value; 1166 } DW17; 1167 union 1168 { 1169 //!< DWORD 18 1170 struct 1171 { 1172 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1173 uint32_t MfdIndirectItDblkObjectArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1174 uint32_t Reserved585 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1175 uint32_t MfdIndirectItDblkObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1176 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1177 }; 1178 uint32_t Value; 1179 } DW18; 1180 union 1181 { 1182 //!< DWORD 19 1183 struct 1184 { 1185 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1186 uint32_t MfdIndirectItDblkObjectAccessUpperBoundDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-DBLK Object - Access Upper Bound (Decoder Only) 1187 }; 1188 uint32_t Value; 1189 } DW19; 1190 union 1191 { 1192 //!< DWORD 20 1193 struct 1194 { 1195 uint32_t MfdIndirectItDblkObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-DBLK Object UpperBound [47:32] 1196 uint32_t Reserved656 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1197 }; 1198 uint32_t Value; 1199 } DW20; 1200 union 1201 { 1202 //!< DWORD 21 1203 struct 1204 { 1205 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1206 uint32_t MfcIndirectPakBseObjectBaseAddressEncoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFC Indirect PAK-BSE Object - Base Address (Encoder Only) 1207 }; 1208 uint32_t Value; 1209 } DW21; 1210 union 1211 { 1212 //!< DWORD 22 1213 struct 1214 { 1215 uint32_t MfcIndirectPakBseObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFC Indirect PAK-BSE Object Base Address [47:32] 1216 uint32_t Reserved720 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1217 }; 1218 uint32_t Value; 1219 } DW22; 1220 union 1221 { 1222 //!< DWORD 23 1223 struct 1224 { 1225 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1226 uint32_t MfcIndirectPakBseObjectDesitnationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1227 uint32_t Reserved745 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1228 uint32_t MfcIndirectPakBseObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1229 uint32_t Reserved751 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1230 }; 1231 uint32_t Value; 1232 } DW23; 1233 union 1234 { 1235 //!< DWORD 24 1236 struct 1237 { 1238 uint32_t Reserved768 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1239 uint32_t MfcIndirectPakBseObjectAccessUpperBoundEecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFC Indirect PAK-BSE Object - Access Upper Bound (Eecoder Only) 1240 }; 1241 uint32_t Value; 1242 } DW24; 1243 union 1244 { 1245 //!< DWORD 25 1246 struct 1247 { 1248 uint32_t MfcIndirectPakBseObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFC Indirect PAK-BSE Object UpperBound [47:32] 1249 uint32_t Reserved816 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1250 }; 1251 uint32_t Value; 1252 } DW25; 1253 1254 //! \name Local enumerations 1255 1256 enum SUBOPCODEB 1257 { 1258 SUBOPCODEB_MFXINDOBJBASEADDRSTATE = 3, //!< No additional details 1259 }; 1260 1261 enum SUB_OPCODEA 1262 { 1263 SUB_OPCODEA_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1264 }; 1265 1266 enum COMMON_OPCODE 1267 { 1268 COMMON_OPCODE_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1269 }; 1270 1271 enum PIPELINE 1272 { 1273 PIPELINE_MFXINDOBJBASEADDRSTATE = 2, //!< No additional details 1274 }; 1275 1276 enum COMMAND_TYPE 1277 { 1278 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1279 }; 1280 1281 //! \brief MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1282 //! \details 1283 //! This field controls the priority of arbitration used in the GAC/GAM 1284 //! pipeline for this surface. 1285 enum MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1286 { 1287 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1288 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1289 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1290 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1291 }; 1292 1293 //! \brief MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1294 //! \details 1295 //! <b>For Media Surfaces:</b> 1296 //! This field specifies the tiled resource mode. 1297 enum MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1298 { 1299 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1300 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1301 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1302 }; 1303 1304 //! \brief MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1305 //! \details 1306 //! This field controls the priority of arbitration used in the GAC/GAM 1307 //! pipeline for this surface. 1308 enum MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1309 { 1310 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1311 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1312 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1313 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1314 }; 1315 1316 //! \brief MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1317 //! \details 1318 //! <b>For Media Surfaces:</b> 1319 //! This field specifies the tiled resource mode. 1320 enum MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1321 { 1322 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1323 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1324 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1325 }; 1326 1327 //! \brief MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1328 //! \details 1329 //! This field controls the priority of arbitration used in the GAC/GAM 1330 //! pipeline for this surface. 1331 enum MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1332 { 1333 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1334 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1335 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1336 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1337 }; 1338 1339 //! \brief MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1340 //! \details 1341 //! <b>For Media Surfaces:</b> 1342 //! This field specifies the tiled resource mode. 1343 enum MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1344 { 1345 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1346 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1347 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1348 }; 1349 1350 //! \brief MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1351 //! \details 1352 //! This field controls the priority of arbitration used in the GAC/GAM 1353 //! pipeline for this surface. 1354 enum MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1355 { 1356 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1357 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1358 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1359 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1360 }; 1361 1362 //! \brief MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1363 //! \details 1364 //! <b>For Media Surfaces:</b> 1365 //! This field specifies the tiled resource mode. 1366 enum MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1367 { 1368 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1369 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1370 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1371 }; 1372 1373 //! \brief MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1374 //! \details 1375 //! This field controls the priority of arbitration used in the GAC/GAM 1376 //! pipeline for this surface. 1377 enum MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1378 { 1379 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1380 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1381 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1382 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1383 }; 1384 1385 //! \brief MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1386 //! \details 1387 //! <b>For Media Surfaces:</b> 1388 //! This field specifies the tiled resource mode. 1389 enum MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1390 { 1391 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1392 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1393 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1394 }; 1395 1396 //! \name Initializations 1397 1398 //! \brief Explicit member initialization function 1399 MFX_IND_OBJ_BASE_ADDR_STATE_CMD(); 1400 1401 static const size_t dwSize = 26; 1402 static const size_t byteSize = 104; 1403 }; 1404 1405 //! 1406 //! \brief MFX_BSP_BUF_BASE_ADDR_STATE 1407 //! \details 1408 //! This frame-level state command is used to specify all the buffer base 1409 //! addresses needed for the operation of the AVC Bit Stream Processing 1410 //! Units (for decoder, it is BSD Unit; for encoder, it is BSE Unit) For 1411 //! both encoder and decoder, currently it is assumed that all codec 1412 //! standards can share the same BSP_BUF_BASE_STATE. The simplicity of this 1413 //! command is the result of moving all the direct MV related processing 1414 //! into the ENC Subsystem. Since all implicit weight calculations and 1415 //! directMV calculations are done in ENC and all picture buffer management 1416 //! are done in the Host, there is no need to provide POC (POC List - 1417 //! FieldOrderCntList, CurrPic POC - CurrFieldOrderCnt) information to PAK. 1418 //! For decoder, all the direct mode information are sent in a separate 1419 //! slice-level command (AVC_DIRECTMODE_STATE command). In addition, in 1420 //! Encoder, the row stores for CABAC encoding and MB Parameters 1421 //! Construction (MPC) are combined into one single row store. The row 1422 //! stores specified in this command do not combine with those specified in 1423 //! the MFC_PIPE_BUF_ADDR_STATE command for hardware simplification reason. 1424 //! 1425 struct MFX_BSP_BUF_BASE_ADDR_STATE_CMD 1426 { 1427 union 1428 { 1429 //!< DWORD 0 1430 struct 1431 { 1432 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1433 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1434 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1435 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1436 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1437 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1438 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1439 }; 1440 uint32_t Value; 1441 } DW0; 1442 union 1443 { 1444 //!< DWORD 1 1445 struct 1446 { 1447 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1448 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite : __CODEGEN_BITFIELD( 6, 31) ; //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write 1449 }; 1450 uint32_t Value; 1451 } DW1; 1452 union 1453 { 1454 //!< DWORD 2 1455 struct 1456 { 1457 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write [47:32] 1458 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1459 }; 1460 uint32_t Value; 1461 } DW2; 1462 union 1463 { 1464 //!< DWORD 3 1465 struct 1466 { 1467 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1468 uint32_t BsdMpcRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1469 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 11) ; //!< Reserved 1470 uint32_t BsdMpcRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1471 uint32_t BsdMpcRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1472 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1473 }; 1474 uint32_t Value; 1475 } DW3; 1476 union 1477 { 1478 //!< DWORD 4 1479 struct 1480 { 1481 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1482 uint32_t MprRowStoreScratchBufferBaseAddressReadWriteDecoderOnly : __CODEGEN_BITFIELD( 6, 31) ; //!< MPR Row Store Scratch Buffer Base Address - Read/Write (Decoder Only) 1483 }; 1484 uint32_t Value; 1485 } DW4; 1486 union 1487 { 1488 //!< DWORD 5 1489 struct 1490 { 1491 uint32_t MprRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MPR Row Store Scratch Buffer Base Address - Read/Write [47:32] 1492 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1493 }; 1494 uint32_t Value; 1495 } DW5; 1496 union 1497 { 1498 //!< DWORD 6 1499 struct 1500 { 1501 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1502 uint32_t MprRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1503 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 11) ; //!< Reserved 1504 uint32_t MprRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1505 uint32_t MprRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1506 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1507 }; 1508 uint32_t Value; 1509 } DW6; 1510 union 1511 { 1512 //!< DWORD 7 1513 struct 1514 { 1515 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1516 uint32_t BitplaneReadBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitplane Read Buffer Base Address 1517 }; 1518 uint32_t Value; 1519 } DW7; 1520 union 1521 { 1522 //!< DWORD 8 1523 struct 1524 { 1525 uint32_t BitplaneReadBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Bitplane Read Buffer Base Address - Read/Write [47:32] 1526 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1527 }; 1528 uint32_t Value; 1529 } DW8; 1530 union 1531 { 1532 //!< DWORD 9 1533 struct 1534 { 1535 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1536 uint32_t BitplaneReadBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1537 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1538 uint32_t BitplaneReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1539 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1540 }; 1541 uint32_t Value; 1542 } DW9; 1543 1544 //! \name Local enumerations 1545 1546 enum SUBOPCODE_B 1547 { 1548 SUBOPCODE_B_UNNAMED_4 = 4, //!< No additional details 1549 }; 1550 1551 enum SUBOPCODE_A 1552 { 1553 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 1554 }; 1555 1556 enum MEDIA_COMMAND_OPCODE 1557 { 1558 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 1559 }; 1560 1561 enum PIPELINE 1562 { 1563 PIPELINE_PIPELINE = 2, //!< No additional details 1564 }; 1565 1566 enum COMMAND_TYPE 1567 { 1568 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1569 }; 1570 1571 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1572 //! \details 1573 //! This field controls the priority of arbitration used in the GAC/GAM 1574 //! pipeline for this surface. 1575 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1576 { 1577 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1578 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1579 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1580 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1581 }; 1582 1583 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1584 //! \details 1585 //! This field controls if Intra Row Store is going to store inside Media 1586 //! Internal Storage or to LLC. 1587 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1588 { 1589 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1590 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1591 }; 1592 1593 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1594 //! \details 1595 //! <b>For Media Surfaces:</b> 1596 //! This field specifies the tiled resource mode. 1597 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1598 { 1599 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1600 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1601 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1602 }; 1603 1604 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1605 //! \details 1606 //! This field controls the priority of arbitration used in the GAC/GAM 1607 //! pipeline for this surface. 1608 enum MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1609 { 1610 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1611 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1612 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1613 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1614 }; 1615 1616 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1617 //! \details 1618 //! This field controls if Intra Row Store is going to store inside Media 1619 //! Internal Storage or to LLC. 1620 enum MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1621 { 1622 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1623 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1624 }; 1625 1626 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1627 //! \details 1628 //! <b>For Media Surfaces:</b> 1629 //! This field specifies the tiled resource mode. 1630 enum MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1631 { 1632 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1633 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1634 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1635 }; 1636 1637 //! \brief BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1638 //! \details 1639 //! This field controls the priority of arbitration used in the GAC/GAM 1640 //! pipeline for this surface. 1641 enum BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1642 { 1643 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1644 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1645 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1646 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1647 }; 1648 1649 //! \brief BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1650 //! \details 1651 //! <b>For Media Surfaces:</b> 1652 //! This field specifies the tiled resource mode. 1653 enum BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1654 { 1655 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1656 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1657 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1658 }; 1659 1660 //! \name Initializations 1661 1662 //! \brief Explicit member initialization function 1663 MFX_BSP_BUF_BASE_ADDR_STATE_CMD(); 1664 1665 static const size_t dwSize = 10; 1666 static const size_t byteSize = 40; 1667 }; 1668 1669 //! 1670 //! \brief MFD_AVC_PICID_STATE 1671 //! \details 1672 //! This is a frame level state command used for both AVC Long and Short 1673 //! Format in VLD mode.PictureID[16] contains the pictureID of each 1674 //! reference picture (16 maximum) so hardware can uniquely identify the 1675 //! reference picture across frames (this will be used for DMV 1676 //! operation).This command will be needed for both short and long format. 1677 //! 1678 struct MFD_AVC_PICID_STATE_CMD 1679 { 1680 union 1681 { 1682 //!< DWORD 0 1683 struct 1684 { 1685 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1686 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1687 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1688 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1689 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1690 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1691 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1692 }; 1693 uint32_t Value; 1694 } DW0; 1695 union 1696 { 1697 //!< DWORD 1 1698 struct 1699 { 1700 uint32_t PictureidRemappingDisable : __CODEGEN_BITFIELD( 0, 0) ; //!< PICTUREID_REMAPPING_DISABLE 1701 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 1702 }; 1703 uint32_t Value; 1704 } DW1; 1705 1706 uint32_t Pictureidlist1616Bits[8]; //!< PictureIDList[16][16 bits] 1707 1708 //! \name Local enumerations 1709 1710 enum SUBOPCODE_B 1711 { 1712 SUBOPCODE_B_MEDIA = 5, //!< No additional details 1713 }; 1714 1715 enum SUBOPCODE_A 1716 { 1717 SUBOPCODE_A_DEC = 1, //!< No additional details 1718 }; 1719 1720 enum MEDIA_COMMAND_OPCODE 1721 { 1722 MEDIA_COMMAND_OPCODE_MFDAVCDPBSTATE = 1, //!< No additional details 1723 }; 1724 1725 enum PIPELINE 1726 { 1727 PIPELINE_MFXMULTIDW = 2, //!< No additional details 1728 }; 1729 1730 enum COMMAND_TYPE 1731 { 1732 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1733 }; 1734 1735 //! \brief PICTUREID_REMAPPING_DISABLE 1736 //! \details 1737 //! If Picture ID Remapping Disable is "1", PictureIDList will not be used. 1738 enum PICTUREID_REMAPPING_DISABLE 1739 { 1740 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE16BITSPICTUREIDTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURE = 0, //!< Desc 1741 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE_4BITSFRAMESTOREIDINDEXTOREFFRAMELISTTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURETHISCAUSESDMVLOGICTOFUNCTIONTHESAMEINPROJECTIVBANDBEFORE = 1, //!< Desc 1742 }; 1743 1744 //! \name Initializations 1745 1746 //! \brief Explicit member initialization function 1747 MFD_AVC_PICID_STATE_CMD(); 1748 1749 static const size_t dwSize = 10; 1750 static const size_t byteSize = 40; 1751 }; 1752 1753 //! 1754 //! \brief MFX_AVC_IMG_STATE 1755 //! \details 1756 //! This must be the very first command to issue after the surface state, 1757 //! the pipe select and base address setting commands. This command supports 1758 //! both Long and Short VLD and IT AVC Decoding Interface. 1759 //! 1760 struct MFX_AVC_IMG_STATE_CMD 1761 { 1762 union 1763 { 1764 //!< DWORD 0 1765 struct 1766 { 1767 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1768 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1769 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1770 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1771 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1772 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1773 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1774 }; 1775 uint32_t Value; 1776 } DW0; 1777 union 1778 { 1779 //!< DWORD 1 1780 struct 1781 { 1782 uint32_t FrameSize : __CODEGEN_BITFIELD( 0, 15) ; //!< Frame Size 1783 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1784 }; 1785 uint32_t Value; 1786 } DW1; 1787 union 1788 { 1789 //!< DWORD 2 1790 struct 1791 { 1792 uint32_t FrameWidth : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Width 1793 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1794 uint32_t FrameHeight : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Height 1795 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1796 }; 1797 uint32_t Value; 1798 } DW2; 1799 union 1800 { 1801 //!< DWORD 3 1802 struct 1803 { 1804 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1805 uint32_t ImgstructImageStructureImgStructure10 : __CODEGEN_BITFIELD( 8, 9) ; //!< IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 1806 uint32_t WeightedBipredIdc : __CODEGEN_BITFIELD(10, 11) ; //!< WEIGHTED_BIPRED_IDC 1807 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(12, 12) ; //!< WEIGHTED_PRED_FLAG 1808 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD(13, 13) ; //!< RHODOMAIN_RATE_CONTROL_ENABLE 1809 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1810 uint32_t FirstChromaQpOffset : __CODEGEN_BITFIELD(16, 20) ; //!< First Chroma QP Offset 1811 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 1812 uint32_t SecondChromaQpOffset : __CODEGEN_BITFIELD(24, 28) ; //!< Second Chroma QP Offset 1813 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1814 }; 1815 uint32_t Value; 1816 } DW3; 1817 union 1818 { 1819 //!< DWORD 4 1820 struct 1821 { 1822 uint32_t Fieldpicflag : __CODEGEN_BITFIELD( 0, 0) ; //!< FIELDPICFLAG 1823 uint32_t Mbaffflameflag : __CODEGEN_BITFIELD( 1, 1) ; //!< MBAFFFLAMEFLAG 1824 uint32_t Framembonlyflag : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMEMBONLYFLAG 1825 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD( 3, 3) ; //!< TRANSFORM8X8FLAG 1826 uint32_t Direct8X8Infflag : __CODEGEN_BITFIELD( 4, 4) ; //!< DIRECT8X8INFFLAG 1827 uint32_t Constrainedipredflag : __CODEGEN_BITFIELD( 5, 5) ; //!< CONSTRAINEDIPREDFLAG 1828 uint32_t Imgdisposableflag : __CODEGEN_BITFIELD( 6, 6) ; //!< IMGDISPOSABLEFLAG 1829 uint32_t Entropycodingflag : __CODEGEN_BITFIELD( 7, 7) ; //!< ENTROPYCODINGFLAG 1830 uint32_t Mbmvformatflag : __CODEGEN_BITFIELD( 8, 8) ; //!< MBMVFORMATFLAG 1831 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1832 uint32_t Chromaformatidc : __CODEGEN_BITFIELD(10, 11) ; //!< CHROMAFORMATIDC 1833 uint32_t Mvunpackedflag : __CODEGEN_BITFIELD(12, 12) ; //!< MVUNPACKEDFLAG 1834 uint32_t Reserved141 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 1835 uint32_t Loadslicepointerflag : __CODEGEN_BITFIELD(14, 14) ; //!< LOADSLICEPOINTERFLAG 1836 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15) ; //!< MBSTATENABLED 1837 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31) ; //!< MINFRAMEWSIZE 1838 }; 1839 uint32_t Value; 1840 } DW4; 1841 union 1842 { 1843 //!< DWORD 5 1844 struct 1845 { 1846 uint32_t IntrambmaxbitflagIntrambmaxsizereportmask : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 1847 uint32_t IntermbmaxbitflagIntermbmaxsizereportmask : __CODEGEN_BITFIELD( 1, 1) ; //!< INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 1848 uint32_t FrameszoverflagFramebitratemaxreportmask : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 1849 uint32_t FrameszunderflagFramebitrateminreportmask : __CODEGEN_BITFIELD( 3, 3) ; //!< FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 1850 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 6) ; //!< Reserved 1851 uint32_t IntraIntermbipcmflagForceipcmcontrolmask : __CODEGEN_BITFIELD( 7, 7) ; //!< INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 1852 uint32_t Reserved168 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 1853 uint32_t MbratectrlflagMbLevelRateControlEnablingFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 1854 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11) ; //!< MINFRAMEWSIZEUNITS 1855 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1856 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 1857 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 26) ; //!< Reserved 1858 uint32_t TrellisQuantizationChromaDisableTqchromadisable : __CODEGEN_BITFIELD(27, 27) ; //!< TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 1859 uint32_t TrellisQuantizationRoundingTqr : __CODEGEN_BITFIELD(28, 30) ; //!< TRELLIS_QUANTIZATION_ROUNDING_TQR 1860 uint32_t TrellisQuantizationEnabledTqenb : __CODEGEN_BITFIELD(31, 31) ; //!< TRELLIS_QUANTIZATION_ENABLED_TQENB 1861 }; 1862 uint32_t Value; 1863 } DW5; 1864 union 1865 { 1866 //!< DWORD 6 1867 struct 1868 { 1869 uint32_t Intrambmaxsz : __CODEGEN_BITFIELD( 0, 11) ; //!< IntraMbMaxSz 1870 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1871 uint32_t Intermbmaxsz : __CODEGEN_BITFIELD(16, 27) ; //!< InterMbMaxSz 1872 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1873 }; 1874 uint32_t Value; 1875 } DW6; 1876 union 1877 { 1878 //!< DWORD 7 1879 struct 1880 { 1881 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSL_TOP_MB_TRANS8X8FLAG 1882 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 15) ; //!< Reserved 1883 uint32_t BspEncoderEcoEnable : __CODEGEN_BITFIELD(16, 16) ; //!< BSP_ENCODER_ECO_ENABLE 1884 uint32_t Reserved241 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1885 }; 1886 uint32_t Value; 1887 } DW7; 1888 union 1889 { 1890 //!< DWORD 8 1891 struct 1892 { 1893 uint32_t Slicedeltaqppmax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQpPMax[0] 1894 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQpMax[1] 1895 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQpMax[2] 1896 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQpMax[3] 1897 }; 1898 uint32_t Value; 1899 } DW8; 1900 union 1901 { 1902 //!< DWORD 9 1903 struct 1904 { 1905 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQpMin[0] 1906 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQpMin[1] 1907 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQpMin[2] 1908 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQpMin[3] 1909 }; 1910 uint32_t Value; 1911 } DW9; 1912 union 1913 { 1914 //!< DWORD 10 1915 struct 1916 { 1917 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1918 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14) ; //!< FRAMEBITRATEMINUNITMODE 1919 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15) ; //!< FRAMEBITRATEMINUNIT 1920 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29) ; //!< FrameBitRateMax 1921 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30) ; //!< FRAMEBITRATEMAXUNITMODE 1922 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT_ 1923 }; 1924 uint32_t Value; 1925 } DW10; 1926 union 1927 { 1928 //!< DWORD 11 1929 struct 1930 { 1931 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FrameBitRateMinDelta 1932 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1933 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1934 uint32_t SliceStatsStreamoutEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Slice Stats Streamout Enable 1935 }; 1936 uint32_t Value; 1937 } DW11; 1938 union 1939 { 1940 //!< DWORD 12 1941 struct 1942 { 1943 uint32_t Reserved384 ; //!< Reserved 1944 }; 1945 uint32_t Value; 1946 } DW12; 1947 union 1948 { 1949 //!< DWORD 13 1950 struct 1951 { 1952 uint32_t InitialQpValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Initial QP Value 1953 uint32_t NumberOfActiveReferencePicturesFromL0 : __CODEGEN_BITFIELD( 8, 13) ; //!< Number of Active Reference Pictures from L0 1954 uint32_t Reserved430 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1955 uint32_t NumberOfActiveReferencePicturesFromL1 : __CODEGEN_BITFIELD(16, 21) ; //!< Number of Active Reference Pictures from L1 1956 uint32_t Reserved438 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 1957 uint32_t NumberOfReferenceFrames : __CODEGEN_BITFIELD(24, 28) ; //!< Number of Reference Frames 1958 uint32_t CurrentPictureHasPerformedMmco5 : __CODEGEN_BITFIELD(29, 29) ; //!< Current Picture Has Performed MMCO5 1959 uint32_t Reserved446 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1960 }; 1961 uint32_t Value; 1962 } DW13; 1963 union 1964 { 1965 //!< DWORD 14 1966 struct 1967 { 1968 uint32_t PicOrderPresentFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< Pic_order_present_flag 1969 uint32_t DeltaPicOrderAlwaysZeroFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< Delta_pic_order_always_zero_flag 1970 uint32_t PicOrderCntType : __CODEGEN_BITFIELD( 2, 3) ; //!< Pic_order_cnt_type 1971 uint32_t Reserved452 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 1972 uint32_t SliceGroupMapType : __CODEGEN_BITFIELD( 8, 10) ; //!< slice_group_map_type 1973 uint32_t RedundantPicCntPresentFlag : __CODEGEN_BITFIELD(11, 11) ; //!< redundant_pic_cnt_present_flag 1974 uint32_t NumSliceGroupsMinus1 : __CODEGEN_BITFIELD(12, 14) ; //!< num_slice_groups_minus1 1975 uint32_t DeblockingFilterControlPresentFlag : __CODEGEN_BITFIELD(15, 15) ; //!< deblocking_filter_control_present_flag 1976 uint32_t Log2MaxFrameNumMinus4 : __CODEGEN_BITFIELD(16, 23) ; //!< Log2_max_frame_num_minus4 1977 uint32_t Log2MaxPicOrderCntLsbMinus4 : __CODEGEN_BITFIELD(24, 31) ; //!< Log2_max_pic_order_cnt_lsb_minus4 1978 }; 1979 uint32_t Value; 1980 } DW14; 1981 union 1982 { 1983 //!< DWORD 15 1984 struct 1985 { 1986 uint32_t SliceGroupChangeRate : __CODEGEN_BITFIELD( 0, 15) ; //!< Slice Group Change Rate 1987 uint32_t CurrPicFrameNum : __CODEGEN_BITFIELD(16, 31) ; //!< Curr Pic Frame Num 1988 }; 1989 uint32_t Value; 1990 } DW15; 1991 union 1992 { 1993 //!< DWORD 16..17 1994 struct 1995 { 1996 uint64_t CurrentFrameViewId : __CODEGEN_BITFIELD( 0, 9) ; //!< Current Frame View ID 1997 uint64_t Reserved522 : __CODEGEN_BITFIELD(10, 11) ; //!< Reserved 1998 uint64_t MaxViewIdxl0 : __CODEGEN_BITFIELD(12, 15) ; //!< Max View IDXL0 1999 uint64_t Reserved528 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 2000 uint64_t MaxViewIdxl1 : __CODEGEN_BITFIELD(18, 21) ; //!< Max View IDXL1 2001 uint64_t Reserved534 : __CODEGEN_BITFIELD(22, 30) ; //!< Reserved 2002 uint64_t InterViewOrderDisable : __CODEGEN_BITFIELD(31, 31) ; //!< INTER_VIEW_ORDER_DISABLE 2003 uint64_t Reserved544 : __CODEGEN_BITFIELD(32, 39) ; //!< Reserved 2004 uint64_t ExtendedRhodomainStatisticsEnable : __CODEGEN_BITFIELD(40, 40) ; //!< ExtendedRhodomainStatisticsEnable 2005 uint64_t Reserved554 : __CODEGEN_BITFIELD(41, 47) ; //!< Reserved 2006 uint64_t RhodomainAveragemacroblockqp : __CODEGEN_BITFIELD(48, 53) ; //!< RhoDomain AverageMacroblockQP 2007 uint64_t Reserved566 : __CODEGEN_BITFIELD(54, 63) ; //!< Reserved 2008 }; 2009 uint32_t Value[2]; 2010 } DW16_17; 2011 union 2012 { 2013 //!< DWORD 18 2014 struct 2015 { 2016 uint32_t Reserved576 ; //!< Reserved 2017 }; 2018 uint32_t Value; 2019 } DW18; 2020 union 2021 { 2022 //!< DWORD 19 2023 struct 2024 { 2025 uint32_t ThresholdSizeInBytes ; //!< Threshold Size in Bytes 2026 }; 2027 uint32_t Value; 2028 } DW19; 2029 union 2030 { 2031 //!< DWORD 20 2032 struct 2033 { 2034 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 2035 }; 2036 uint32_t Value; 2037 } DW20; 2038 2039 //! \name Local enumerations 2040 2041 enum SUBOPCODE_B 2042 { 2043 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 2044 }; 2045 2046 enum SUBOPCODE_A 2047 { 2048 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2049 }; 2050 2051 enum MEDIA_COMMAND_OPCODE 2052 { 2053 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2054 }; 2055 2056 enum PIPELINE 2057 { 2058 PIPELINE_MFXAVCIMGSTATE = 2, //!< No additional details 2059 }; 2060 2061 enum COMMAND_TYPE 2062 { 2063 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2064 }; 2065 2066 //! \brief IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 2067 //! \details 2068 //! The current encoding picture structure can only takes on 3 possible 2069 //! values 2070 enum IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 2071 { 2072 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_FRAMEPICTURE = 0, //!< No additional details 2073 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_TOPFIELDPICTURE = 1, //!< No additional details 2074 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_INVALID_NOTALLOWED = 2, //!< No additional details 2075 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_BOTTOMFIELDPICTURE = 3, //!< No additional details 2076 }; 2077 2078 //! \brief WEIGHTED_BIPRED_IDC 2079 //! \details 2080 //! (This field is defined differently from DevSNB; DevIVB follows strictly AVC interface.) 2081 enum WEIGHTED_BIPRED_IDC 2082 { 2083 WEIGHTED_BIPRED_IDC_DEFAULT = 0, //!< Specifies that the default weighted prediction is used for B slices 2084 WEIGHTED_BIPRED_IDC_EXPLICIT = 1, //!< Specifies that explicit weighted prediction is used for B slices 2085 WEIGHTED_BIPRED_IDC_IMPLICIT = 2, //!< Specifies that implicit weighted prediction is used for B slices. 2086 }; 2087 2088 //! \brief WEIGHTED_PRED_FLAG 2089 //! \details 2090 //! (This field is defined differently from Gen6, Gen7 follows strictly AVC interface.) 2091 enum WEIGHTED_PRED_FLAG 2092 { 2093 WEIGHTED_PRED_FLAG_DISABLE = 0, //!< specifies that weighted prediction is not used for P and SP slices 2094 WEIGHTED_PRED_FLAG_ENABLE = 1, //!< specifies that weighted prediction is used for P and SP slices 2095 }; 2096 2097 //! \brief RHODOMAIN_RATE_CONTROL_ENABLE 2098 //! \details 2099 //! This field indicates if RhoDomain related parameters are present in the 2100 //! MFX_AVC_IMAGE_STATE. (AverageMacroblockQP). It enables the Rho Domain 2101 //! statistics collection. 2102 enum RHODOMAIN_RATE_CONTROL_ENABLE 2103 { 2104 RHODOMAIN_RATE_CONTROL_ENABLE_DISABLE = 0, //!< RhoDomain rate control parameters are not present in MFX_AVC_IMAGE_STATE 2105 RHODOMAIN_RATE_CONTROL_ENABLE_ENABLE = 1, //!< RhoDomain rate control parameters are present in MFX_AVC_IMAGE_STATE. 2106 }; 2107 2108 //! \brief FIELDPICFLAG 2109 //! \details 2110 //! Field picture flag, field_pic_flag, specifies the current slice is a 2111 //! coded field or not.It is set to the same value as the syntax element in 2112 //! the Slice Header. It must be consistent with the img_structure[1:0] and 2113 //! the frame_mbs_only_flag settings.Although field_pic_flag is a Slice 2114 //! Header parameter, its value is expected to be the same for all the 2115 //! slices of a picture. 2116 enum FIELDPICFLAG 2117 { 2118 FIELDPICFLAG_FRAME = 0, //!< a slice of a coded frame 2119 FIELDPICFLAG_FIELD = 1, //!< a slice of a coded field 2120 }; 2121 2122 //! \brief MBAFFFLAMEFLAG 2123 //! \details 2124 //! MBAFF mode is active, mbaff_frame_flag.It is derived from MbaffFrameFlag 2125 //! = (mb_adaptive_frame_field_flag && ! field_pic_flag ). 2126 //! mb_adaptive_frame_field_flag is a syntax element in the current active 2127 //! SPS and field_pic_flag is a syntax element in the current Slice Header. 2128 //! They both are present only if frame_mbs_only_flag is 0. Although 2129 //! mbaff_frame_flag is a Slice Header parameter, its value is expected to 2130 //! be the same for all the slices of a picture.It must be consistent with 2131 //! the mb_adaptive_frame_field_flag, the field_pic_flag and the 2132 //! frame_mbs_only_flag settings.This bit is valid only when the 2133 //! img_structure[1:0] indicates the current picture is a frame. 2134 enum MBAFFFLAMEFLAG 2135 { 2136 MBAFFFLAMEFLAG_FALSE = 0, //!< not in MBAFF mode 2137 MBAFFFLAMEFLAG_TRUE = 1, //!< in MBAFF mode 2138 }; 2139 2140 //! \brief FRAMEMBONLYFLAG 2141 //! \details 2142 //! Frame MB only flag, frame_mbs_only_flagIt is set to the value of the 2143 //! syntax element in the current active SPS. 2144 enum FRAMEMBONLYFLAG 2145 { 2146 FRAMEMBONLYFLAG_FALSE = 0, //!< not true ; effectively enables the possibility of MBAFF mode. 2147 FRAMEMBONLYFLAG_TRUE = 1, //!< true, only frame MBs can occur in this sequence, hence disallows the MBAFF mode and field picture. 2148 }; 2149 2150 //! \brief TRANSFORM8X8FLAG 2151 //! \details 2152 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flagSpecifies 8x8 IDCT 2153 //! transform may be used in this pictureIt is set to the value of the 2154 //! syntax element in the current active PPS. 2155 enum TRANSFORM8X8FLAG 2156 { 2157 TRANSFORM8X8FLAG_4X_4 = 0, //!< no 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present 2158 TRANSFORM8X8FLAG_8X8 = 1, //!< 8x8 Transform is allowed 2159 }; 2160 2161 //! \brief DIRECT8X8INFFLAG 2162 //! \details 2163 //! Direct 8x8 Inference Flag, direct_8x8_inference_flagIt is set to the 2164 //! value of the syntax element in the current active SPS.It specifies the 2165 //! derivation process for luma motion vectors in the Direct MV coding modes 2166 //! (B_Skip, B_Direct_16x16 and B_Direct_8x8). When frame_mbs_only_flag is 2167 //! equal to 0, direct_8x8_inference_flag shall be equal to 1.It must be 2168 //! consistent with the frame_mbs_only_flag and transform_8x8_mode_flag 2169 //! settings. 2170 enum DIRECT8X8INFFLAG 2171 { 2172 DIRECT8X8INFFLAG_SUBBLOCK = 0, //!< allows subpartitioning to go below 8x8 block size (i.e. 4x4, 8x4 or 4x8) 2173 DIRECT8X8INFFLAG_BLOCK = 1, //!< allows processing only at 8x8 block size. MB Info is stored for 8x8 block size. 2174 }; 2175 2176 //! \brief CONSTRAINEDIPREDFLAG 2177 //! \details 2178 //! Constrained Intra Prediction Flag, constrained_ipred_flagIt is set to 2179 //! the value of the syntax element in the current active PPS. 2180 enum CONSTRAINEDIPREDFLAG 2181 { 2182 CONSTRAINEDIPREDFLAG_INTRAANDINTER = 0, //!< allows both intra and inter neighboring MB to be used in the intra-prediction encoding of the current MB. 2183 CONSTRAINEDIPREDFLAG_INTRAONLY = 1, //!< allows only to use neighboring Intra MBs in the intra-prediction encoding of the current MB. If the neighbor is an inter MB, it is considered as not available. 2184 }; 2185 2186 //! \brief IMGDISPOSABLEFLAG 2187 //! \details 2188 //! Current Img Disposable Flag or Non-Reference Picture Flag 2189 enum IMGDISPOSABLEFLAG 2190 { 2191 IMGDISPOSABLEFLAG_REFERENCE = 0, //!< the current decoding picture may be used as a reference picture for others 2192 IMGDISPOSABLEFLAG_DISPOSABLE = 1, //!< the current decoding picture is not used as a reference picture (e.g. a B-picture cannot be a reference picture for any subsequent decoding) 2193 }; 2194 2195 //! \brief ENTROPYCODINGFLAG 2196 //! \details 2197 //! Entropy Coding Flag, entropy_coding_flag 2198 enum ENTROPYCODINGFLAG 2199 { 2200 ENTROPYCODINGFLAG_CAVLCBIT_SERIALENCODINGMODE = 0, //!< Desc 2201 ENTROPYCODINGFLAG_CABACBIT_SERIALENCODINGMODE = 1, //!< Desc 2202 }; 2203 2204 //! \brief MBMVFORMATFLAG 2205 //! \details 2206 //! Use MB level MvFormat flag (Encoder Only)(This bit must be set to zero 2207 //! in IVB:GT2:A0) 2208 enum MBMVFORMATFLAG 2209 { 2210 MBMVFORMATFLAG_IGNORE = 0, //!< HW PAK ignore MvFormat in the MB data. When bit 12 == 0, all MBs use packed MV formatWhen bit 12 == 1, each MB data must use unpacked MV format, 8MV when there is no minor MV involved, and 32MV if there are some minor motin vectors. 2211 MBMVFORMATFLAG_FOLLOW = 1, //!< HW PAK will follow MvFormat value set within each MB data. 2212 }; 2213 2214 //! \brief CHROMAFORMATIDC 2215 //! \details 2216 //! Chroma Format IDC, ChromaFormatIdc[1:0]It specifies the sampling of 2217 //! chroma component (Cb, Cr) in the current picture as follows : 2218 enum CHROMAFORMATIDC 2219 { 2220 CHROMAFORMATIDC_MONOCHROMEPICTURE = 0, //!< Desc 2221 CHROMAFORMATIDC_420PICTURE = 1, //!< Desc 2222 CHROMAFORMATIDC_422PICTURENOTSUPPORTED = 2, //!< No additional details 2223 CHROMAFORMATIDC_4_4_4PICTURENOTSUPPORTED = 3, //!< No additional details 2224 }; 2225 2226 //! \brief MVUNPACKEDFLAG 2227 //! \details 2228 //! MVUnPackedEnable (Encoder Only)This field is reserved in Decode mode. 2229 enum MVUNPACKEDFLAG 2230 { 2231 MVUNPACKEDFLAG_PACKED = 0, //!< use packed MV format 2232 MVUNPACKEDFLAG_UNPACKED = 1, //!< use unpacked 8MV/32MV format only 2233 }; 2234 2235 //! \brief LOADSLICEPOINTERFLAG 2236 //! \details 2237 //! LoadBitStreamPointerPerSlice (Encoder-only)To support multiple slice 2238 //! picture and additional header/data insertion before and after an encoded 2239 //! slice.When this field is set to 0, bitstream pointer is only loaded once 2240 //! for the first slice of a frame. For subsequent slices in the frame, 2241 //! bitstream data are stitched together to form a single output data 2242 //! stream.When this field is set to 1, bitstream pointer is loaded for each 2243 //! slice of a frame. Basically bitstream data for different slices of a 2244 //! frame will be written to different memory locations. 2245 enum LOADSLICEPOINTERFLAG 2246 { 2247 LOADSLICEPOINTERFLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame 2248 LOADSLICEPOINTERFLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 2249 }; 2250 2251 //! \brief MBSTATENABLED 2252 //! \details 2253 //! <p>Enable reading in MB status buffer (a.k.a. encoding stream-out 2254 //! buffer) Note: For multi-pass encoder, all passes except the first one 2255 //! need to set this value to 1. By setting the first pass to 0, it does 2256 //! save some memory bandwidth.</p> 2257 //! <p><span style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 2258 //! line-height: normal;">In VDenc mode this must be set to zero as no MB 2259 //! level rate control is used. </span></p> 2260 enum MBSTATENABLED 2261 { 2262 MBSTATENABLED_DISABLE = 0, //!< Disable Reading of Macroblock Status Buffer 2263 MBSTATENABLED_ENABLE = 1, //!< Enable Reading of Macroblock Status Buffer 2264 }; 2265 2266 //! \brief MINFRAMEWSIZE 2267 //! \details 2268 //! <p><b>Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)</b> 2269 //! Mininum Frame Size is specified to compensate for intel Rate 2270 //! Control Currently zero fill (no need to perform emulation byte 2271 //! insertion) is done 2272 //! only to the end of the CABAC_ZERO_WORD insertion (if any) at the 2273 //! last slice of a 2274 //! picture. Intel encoder parameter. The caller 2275 //! should always make 2276 //! sure that the value, represented by Mininum Frame Size, is always 2277 //! less than maximum 2278 //! frame size <b>FrameBitRateMax (DWORD 10 bits</b> 29:16).This field 2279 //! is reserved in 2280 //! Decode mode.</p> 2281 //! <p>The programmable range 0…2^18-1</p> 2282 //! <p>When MinFrameWSizeUnits is 00.</p> 2283 //! <p>Programmable range is 0…2^20-1 when MinFrameWSizeUnits is 2284 //! 01.</p> 2285 //! <p>Programmable range is 0…2^26-1 when MinFrameWSizeUnits is 2286 //! 10.</p> 2287 //! <p>Programmable range is 0…2^32-1 when MinFrameWSizeUnits is 2288 //! 11.</p> 2289 enum MINFRAMEWSIZE 2290 { 2291 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 2292 }; 2293 2294 //! \brief INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 2295 //! \details 2296 //! This is a mask bit controlling if the condition of any intra MB in the 2297 //! frame exceeds IntraMBMaxSize. 2298 enum INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 2299 { 2300 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2301 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_ENABLE = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 2302 }; 2303 2304 //! \brief INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 2305 //! \details 2306 //! This is a mask bit controlling if the condition of any inter MB in the 2307 //! frame exceeds InterMBMaxSize. 2308 enum INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 2309 { 2310 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2311 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_ENABLE = 1, //!< Set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 2312 }; 2313 2314 //! \brief FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 2315 //! \details 2316 //! This is a mask bit controlling if the condition of frame level bit count 2317 //! exceeds FrameBitRateMax. 2318 enum FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 2319 { 2320 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2321 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 2322 }; 2323 2324 //! \brief FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 2325 //! \details 2326 //! This is a mask bit controlling if the condition of frame level bit count 2327 //! is less than FrameBitRateMin 2328 enum FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 2329 { 2330 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2331 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 2332 }; 2333 2334 //! \brief INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 2335 //! \details 2336 //! This field is to Force <b>IPCM</b> for Intra or Inter Macroblock size 2337 //! conformance mask. 2338 enum INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 2339 { 2340 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_DISABLE = 0, //!< Do not change intra or Inter macroblocks even 2341 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_ENABLE = 1, //!< Change intra or Inter macroblocks MB_type to IPCM 2342 }; 2343 2344 //! \brief MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2345 //! \details 2346 //! <p>MB Rate Control conformance mask</p> 2347 //! <p>In VDenc mode, this field must be zero as frame level rate control is 2348 //! used.</p> 2349 enum MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2350 { 2351 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_DISABLE = 0, //!< Apply accumulative delta QP for consecutive passes on top of the macroblock QP values in inline data 2352 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_ENABLE = 1, //!< Apply RC QP delta to suggested QP values in Macroblock Status Buffer except the first pass. 2353 }; 2354 2355 //! \brief MINFRAMEWSIZEUNITS 2356 //! \details 2357 //! This field is the Minimum Frame Size Units 2358 enum MINFRAMEWSIZEUNITS 2359 { 2360 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 2361 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 2362 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 2363 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 2364 }; 2365 2366 //! \brief NONFIRSTPASSFLAG 2367 //! \details 2368 //! This signals the current pass is not the first pass. It will imply 2369 //! designate HW behavior: e.g 2370 enum NONFIRSTPASSFLAG 2371 { 2372 NONFIRSTPASSFLAG_DISABLE = 0, //!< Always use the MbQpY from initial PAK inline object for all passes of PAK 2373 NONFIRSTPASSFLAG_ENABLE = 1, //!< Use MbQpY from stream-out buffer if MbRateCtrlFlag is set to 1 2374 }; 2375 2376 //! \brief TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2377 //! \details 2378 //! This signal is used to disable chroma TQ. To enable TQ for both luma and 2379 //! chroma, TQEnb=1, TQChromaDisable=0. To enable TQ only for luma, TQEnb=1, 2380 //! TQChromaDisable=1. 2381 enum TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2382 { 2383 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_UNNAMED0 = 0, //!< Enable Trellis Quantization chroma 2384 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_DEFAULT = 1, //!< Disable Trellis Quantization chroma 2385 }; 2386 2387 //! \brief TRELLIS_QUANTIZATION_ROUNDING_TQR 2388 //! \details 2389 //! This rounding scheme is only applied to the quantized coefficients 2390 //! ranging from 0 to 1 when TQEnb is set to 1 in AVC CABAC mode. One of the 2391 //! following values is added to quantized coefficients before truncating 2392 //! fractional part. 2393 enum TRELLIS_QUANTIZATION_ROUNDING_TQR 2394 { 2395 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED0 = 0, //!< Add 1/8 2396 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED1 = 1, //!< Add 2/8 2397 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED2 = 2, //!< Add 3/8 2398 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED3 = 3, //!< Add 4/8 (rounding 0.5) 2399 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED_4 = 4, //!< Add 5/8 2400 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED5 = 5, //!< Add 6/8 2401 TRELLIS_QUANTIZATION_ROUNDING_TQR_DEFAULT = 6, //!< Add 7/8 (Default rounding 0.875) 2402 }; 2403 2404 //! \brief TRELLIS_QUANTIZATION_ENABLED_TQENB 2405 //! \details 2406 //! The TQ improves output video quality of AVC CABAC encoder by selecting 2407 //! quantized values for each non-zero coefficient so as to minimize the 2408 //! total R-D cost.This flag is only valid AVC CABAC mode. Otherwise, this 2409 //! flag should be disabled. 2410 enum TRELLIS_QUANTIZATION_ENABLED_TQENB 2411 { 2412 TRELLIS_QUANTIZATION_ENABLED_TQENB_DISABLE = 0, //!< Use Normal 2413 TRELLIS_QUANTIZATION_ENABLED_TQENB_ENABLE = 1, //!< Use Trellis quantization 2414 }; 2415 2416 enum VSL_TOP_MB_TRANS8X8FLAG 2417 { 2418 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 2419 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 2420 }; 2421 2422 //! \brief BSP_ENCODER_ECO_ENABLE 2423 //! \details 2424 //! <p>Enable AVC Encoder BSP Bit Outstanding ECO 2425 //! fix.</p> 2426 //! <p>This bit must be same as bit9 of Dword2 of MFX_PIPE_MODE_SELECT</p> 2427 enum BSP_ENCODER_ECO_ENABLE 2428 { 2429 BSP_ENCODER_ECO_ENABLE_DISABLE = 0, //!< No additional details 2430 BSP_ENCODER_ECO_ENABLE_ENABLE = 1, //!< No additional details 2431 }; 2432 2433 //! \brief FRAMEBITRATEMINUNITMODE 2434 //! \details 2435 //! This field is the Frame Bitrate Minimum Limit Units. 2436 enum FRAMEBITRATEMINUNITMODE 2437 { 2438 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2439 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2440 }; 2441 2442 //! \brief FRAMEBITRATEMINUNIT 2443 //! \details 2444 //! This field is the Frame Bitrate Minimum Limit Units. 2445 enum FRAMEBITRATEMINUNIT 2446 { 2447 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 2448 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2449 }; 2450 2451 //! \brief FRAMEBITRATEMAXUNITMODE 2452 //! \details 2453 //! This field is the Frame Bitrate Maximum Limit Units. 2454 enum FRAMEBITRATEMAXUNITMODE 2455 { 2456 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2457 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2458 }; 2459 2460 //! \brief FRAMEBITRATEMAXUNIT_ 2461 //! \details 2462 //! This field is the Frame Bitrate Maximum Limit Units. 2463 enum FRAMEBITRATEMAXUNIT_ 2464 { 2465 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 2466 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2467 }; 2468 2469 //! \brief FRAMEBITRATEMAXDELTA 2470 //! \details 2471 //! This field is used to select the slice delta QP when FrameBitRateMax Is 2472 //! exceeded. It shares the same FrameBitrateMaxUnit. When 2473 //! FrameBitrateMaxUnitMode is 0(compatibility mode) bits 16:27 should be 2474 //! used, bits 28, 29 and 30 should be 0. 2475 enum FRAMEBITRATEMAXDELTA 2476 { 2477 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 2478 }; 2479 2480 enum VAD_ERROR_LOGIC 2481 { 2482 VAD_ERROR_LOGIC_ENABLE = 0, //!< Error reporting ON in case of premature Slice done 2483 VAD_ERROR_LOGIC_DISABLE = 1, //!< CABAC Engine will auto decode the bitstream in case of premature slice done. 2484 }; 2485 2486 //! \brief INTER_VIEW_ORDER_DISABLE 2487 //! \details 2488 //! It indicates how to append inter-view picture into initial sorted 2489 //! reference list. (due to ambiguity in the MVC Spec) 2490 enum INTER_VIEW_ORDER_DISABLE 2491 { 2492 INTER_VIEW_ORDER_DISABLE_DEFAULT = 0, //!< View Order Ascending 2493 INTER_VIEW_ORDER_DISABLE_DISABLE = 1, //!< View ID Ascending 2494 }; 2495 2496 //! \name Initializations 2497 2498 //! \brief Explicit member initialization function 2499 MFX_AVC_IMG_STATE_CMD(); 2500 2501 static const size_t dwSize = 21; 2502 static const size_t byteSize = 84; 2503 }; 2504 2505 //! 2506 //! \brief MFX_AVC_REF_IDX_STATE 2507 //! \details 2508 //! This is a slice level command and can be issued multiple times within a 2509 //! picture that is comprised of multiple slices. The same command is used 2510 //! for AVC encoder (PAK mode) and decoder (VLD mode); it is not need in 2511 //! decoder IT mode. The inline data of this command is interpreted 2512 //! differently for encoder as for decoder. For decoder, it is interpreted 2513 //! as RefIdx List L0/L1 as in AVC spec., and it matches with the AVC 2514 //! API data structure for decoder in VLD mode : RefPicList[2][32] (L0:L1, 2515 //! 0:31 RefPic). But for encoder, it is interpreted as a Reference Index 2516 //! Mapping Table for L0 and L1 reference pictures. For packing the bits at 2517 //! the output of PAK, the syntax elements must follow the definition of 2518 //! RefIdxL0/L1 list according to the AVC spec. However, the decoder 2519 //! pipeline was designed to use a variation of that standard definition, as 2520 //! such a conversion (mapping) is needed to support the hardware design. 2521 //! The Reference lists are needed in processing both P and B slice in AVC 2522 //! codec. For P-MB, only L0 list is used; for B-MB both L0 and L1 lists are 2523 //! needed. For a B-MB that is coded in L1-only Prediction, only L1 list is 2524 //! used. 2525 //! 2526 //! An application will create the RefPicList L0 and L1 2527 //! and pass onto the driver. The content of each entry of RefPicList 2528 //! L0/L1[ ] is a 7-bit picture index. This picture index is the same as 2529 //! that of RefFrameList[ ] content. This picture index, however, is not 2530 //! defined the same as the frame store ID (0 to 16, 5-bits) we have 2531 //! implemented in H/W. Hence, driver is required to manage a table to 2532 //! convert between picture index and intel frame store ID. As such, 2533 //! the final RefPicList L0/L1[ ] that the driver passes onto the H/W is not 2534 //! the same as that defined. 2535 //! 2536 struct MFX_AVC_REF_IDX_STATE_CMD 2537 { 2538 union 2539 { 2540 //!< DWORD 0 2541 struct 2542 { 2543 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2544 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2545 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2546 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 2547 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 2548 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2549 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2550 }; 2551 uint32_t Value; 2552 } DW0; 2553 union 2554 { 2555 //!< DWORD 1 2556 struct 2557 { 2558 uint32_t RefpiclistSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLIST_SELECT 2559 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2560 }; 2561 uint32_t Value; 2562 } DW1; 2563 2564 uint32_t ReferenceListEntry[8]; //!< Reference List Entry 2565 2566 //! \name Local enumerations 2567 2568 enum SUBOPCODEB 2569 { 2570 SUBOPCODEB_MFXAVCREFIDXSTATE = 4, //!< No additional details 2571 }; 2572 2573 enum SUBOPCODEA 2574 { 2575 SUBOPCODEA_MFXAVCREFIDXSTATE = 0, //!< No additional details 2576 }; 2577 2578 enum COMMAND_OPCODE 2579 { 2580 COMMAND_OPCODE_AVC = 1, //!< No additional details 2581 }; 2582 2583 enum PIPELINE 2584 { 2585 PIPELINE_MFXAVCREFIDXSTATE = 2, //!< No additional details 2586 }; 2587 2588 enum COMMAND_TYPE 2589 { 2590 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2591 }; 2592 2593 //! \brief REFPICLIST_SELECT 2594 //! \details 2595 //! <p>Num_ref_idx_l1_active is resulted from the specifications in both PPS 2596 //! and Slice Header for the current slice. However, since the full 2597 //! reference list L0 and/or L1 are always sent, only present flags are 2598 //! specified instead.</p> 2599 //! <p>This parameter is specified for Intel interface only.</p> 2600 enum REFPICLIST_SELECT 2601 { 2602 REFPICLIST_SELECT_REFPICLIST0 = 0, //!< The list that followed represents RefList L0 (Decoder VLD mode) or Ref Idx Mapping Table L0 (Encoder PAK mode) 2603 REFPICLIST_SELECT_REFPICLIST1 = 1, //!< The list that followed represents RefList L1 (Decoder VLD mode) or Ref Idx Mapping Table L1 (Encoder PAK mode) 2604 }; 2605 2606 //! \name Initializations 2607 2608 //! \brief Explicit member initialization function 2609 MFX_AVC_REF_IDX_STATE_CMD(); 2610 2611 static const size_t dwSize = 10; 2612 static const size_t byteSize = 40; 2613 }; 2614 2615 //! 2616 //! \brief MFX_AVC_WEIGHTOFFSET_STATE 2617 //! \details 2618 //! This is a slice level command and can be issued multiple times within a 2619 //! picture that is comprised of multiple slices. The same command is used 2620 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). However, 2621 //! since for AVC decoder VLD and IT modes, and AVC encoder mode, the 2622 //! implicit weights are computed in hardware, this command is not issued. 2623 //! For encoder, regardless of the type of weight calculation is active for 2624 //! the current slice (default, implicit or explicit), they are all sent to 2625 //! the PAK as if they were all in explicit mode. However, for implicit 2626 //! weight and offset, each entry contains only a 16-bit weight and no 2627 //! offset (offset = 0 always in implicit mode and can be hard-coded inside 2628 //! the hardware).The weights (and offsets) are needed in processing both P 2629 //! and B slice in AVC codec. For P-MB, at most only L0 list is used; for 2630 //! B-MB both L0 and L1 lists may be needed. For a B-MB that is coded in 2631 //! L1-only Prediction, only L1 list is sent.The content of this command 2632 //! matches with the AVC API data structure for explicit prediction 2633 //! mode only : Weights[2][32][3][2] (L0:L1, 0:31 RefPic, Y:Cb:Cr, W:0) 2634 //! 2635 struct MFX_AVC_WEIGHTOFFSET_STATE_CMD 2636 { 2637 union 2638 { 2639 //!< DWORD 0 2640 struct 2641 { 2642 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2643 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2644 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 2645 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 2646 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 2647 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2648 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2649 }; 2650 uint32_t Value; 2651 } DW0; 2652 union 2653 { 2654 //!< DWORD 1 2655 struct 2656 { 2657 uint32_t WeightAndOffsetSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< WEIGHT_AND_OFFSET_SELECT 2658 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2659 }; 2660 uint32_t Value; 2661 } DW1; 2662 2663 uint32_t Weightoffset[96]; //!< WeightOffset 2664 2665 //! \name Local enumerations 2666 2667 enum SUBOPCODE_B 2668 { 2669 SUBOPCODE_B_UNNAMED5 = 5, //!< No additional details 2670 }; 2671 2672 enum SUBOPCODE_A 2673 { 2674 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2675 }; 2676 2677 enum MEDIA_COMMAND_OPCODE 2678 { 2679 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2680 }; 2681 2682 enum PIPELINE 2683 { 2684 PIPELINE_MFXAVCWEIGHTOFFSETSTATE = 2, //!< No additional details 2685 }; 2686 2687 enum COMMAND_TYPE 2688 { 2689 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2690 }; 2691 2692 //! \brief WEIGHT_AND_OFFSET_SELECT 2693 //! \details 2694 //! It must be set in consistent with the WeightedPredFlag and 2695 //! WeightedBiPredIdc in the Img_State command. 2696 //! This parameter is specified for Intel interface only. 2697 //! For implicit even though only one entry may be used, still loading 2698 //! the whole 32-entry table. 2699 enum WEIGHT_AND_OFFSET_SELECT 2700 { 2701 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL0TABLE = 0, //!< The list that followed is associated with the weight and offset for RefPicList L0 2702 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL1TABLE = 1, //!< The list that followed is associated with the weight and offset for RefPicList L1 2703 }; 2704 2705 //! \name Initializations 2706 2707 //! \brief Explicit member initialization function 2708 MFX_AVC_WEIGHTOFFSET_STATE_CMD(); 2709 2710 static const size_t dwSize = 98; 2711 static const size_t byteSize = 392; 2712 }; 2713 2714 //! 2715 //! \brief MFX_AVC_SLICE_STATE 2716 //! \details 2717 //! This is a slice level command and can be issued multiple times within a 2718 //! picture that is comprised of multiple slices. The same command is used 2719 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). 2720 //! 2721 //! In VDEnc mode, this command is programmed only once at the beginning of 2722 //! the frame. All the slices in the frame use the same values. 2723 //! 2724 //! MFX_AVC_SLICE_STATE command is not issued for AVC Short Format 2725 //! Bitstream decode, instead MFD_AVC_SLICEADDR command is executed to 2726 //! retrieve the next slice MB Start Address X and Y by H/W itself. 2727 //! 2728 struct MFX_AVC_SLICE_STATE_CMD 2729 { 2730 union 2731 { 2732 //!< DWORD 0 2733 struct 2734 { 2735 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2736 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2737 uint32_t CommandSubopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< COMMAND_SUBOPCODEB 2738 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 2739 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 2740 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2741 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2742 }; 2743 uint32_t Value; 2744 } DW0; 2745 union 2746 { 2747 //!< DWORD 1 2748 struct 2749 { 2750 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 3) ; //!< SLICE_TYPE 2751 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 2752 }; 2753 uint32_t Value; 2754 } DW1; 2755 union 2756 { 2757 //!< DWORD 2 2758 struct 2759 { 2760 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD( 0, 2) ; //!< Log 2 Weight Denom Luma 2761 uint32_t Reserved67 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2762 uint32_t Log2WeightDenomChroma : __CODEGEN_BITFIELD( 8, 10) ; //!< Log 2 Weight Denom Chroma 2763 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 2764 uint32_t NumberOfReferencePicturesInInterPredictionList0 : __CODEGEN_BITFIELD(16, 21) ; //!< Number of Reference Pictures in Inter-prediction List 0 2765 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2766 uint32_t NumberOfReferencePicturesInInterPredictionList1 : __CODEGEN_BITFIELD(24, 29) ; //!< Number of Reference Pictures in Inter-prediction List 1 2767 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2768 }; 2769 uint32_t Value; 2770 } DW2; 2771 union 2772 { 2773 //!< DWORD 3 2774 struct 2775 { 2776 uint32_t SliceAlphaC0OffsetDiv2 : __CODEGEN_BITFIELD( 0, 3) ; //!< Slice Alpha C0 Offset Div2 2777 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 2778 uint32_t SliceBetaOffsetDiv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< Slice Beta Offset Div2 2779 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2780 uint32_t SliceQuantizationParameter : __CODEGEN_BITFIELD(16, 21) ; //!< Slice Quantization Parameter 2781 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2782 uint32_t CabacInitIdc10 : __CODEGEN_BITFIELD(24, 25) ; //!< Cabac Init Idc[1:0] 2783 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 2784 uint32_t DisableDeblockingFilterIndicator : __CODEGEN_BITFIELD(27, 28) ; //!< DISABLE_DEBLOCKING_FILTER_INDICATOR 2785 uint32_t DirectPredictionType : __CODEGEN_BITFIELD(29, 29) ; //!< DIRECT_PREDICTION_TYPE 2786 uint32_t WeightedPredictionIndicator : __CODEGEN_BITFIELD(30, 31) ; //!< Weighted Prediction Indicator 2787 }; 2788 uint32_t Value; 2789 } DW3; 2790 union 2791 { 2792 //!< DWORD 4 2793 struct 2794 { 2795 uint32_t SliceStartMbNum : __CODEGEN_BITFIELD( 0, 14) ; //!< Slice Start Mb Num 2796 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2797 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Horizontal Position 2798 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(24, 31) ; //!< Slice Vertical Position 2799 }; 2800 uint32_t Value; 2801 } DW4; 2802 union 2803 { 2804 //!< DWORD 5 2805 struct 2806 { 2807 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< Next Slice Horizontal Position 2808 uint32_t Reserved168 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2809 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(16, 24) ; //!< Next Slice Vertical Position 2810 uint32_t Reserved184 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 2811 }; 2812 uint32_t Value; 2813 } DW5; 2814 union 2815 { 2816 //!< DWORD 6 2817 struct 2818 { 2819 uint32_t StreamId10 : __CODEGEN_BITFIELD( 0, 1) ; //!< Stream ID [1:0] 2820 uint32_t Reserved194 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 2821 uint32_t SliceId30 : __CODEGEN_BITFIELD( 4, 7) ; //!< Slice ID [3:0] 2822 uint32_t Reserved200 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 2823 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD(12, 12) ; //!< CABACZEROWORDINSERTIONENABLE 2824 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD(13, 13) ; //!< EMULATIONBYTESLICEINSERTENABLE 2825 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 2826 uint32_t TailInsertionPresentInBitstream : __CODEGEN_BITFIELD(15, 15) ; //!< TAIL_INSERTION_PRESENT_IN_BITSTREAM 2827 uint32_t SlicedataInsertionPresentInBitstream : __CODEGEN_BITFIELD(16, 16) ; //!< SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2828 uint32_t HeaderInsertionPresentInBitstream : __CODEGEN_BITFIELD(17, 17) ; //!< HEADER_INSERTION_PRESENT_IN_BITSTREAM 2829 uint32_t Reserved210 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 2830 uint32_t IsLastSlice : __CODEGEN_BITFIELD(19, 19) ; //!< IS_LAST_SLICE 2831 uint32_t MbTypeSkipConversionDisable : __CODEGEN_BITFIELD(20, 20) ; //!< MB_TYPE_SKIP_CONVERSION_DISABLE 2832 uint32_t MbTypeDirectConversionDisable : __CODEGEN_BITFIELD(21, 21) ; //!< MB_TYPE_DIRECT_CONVERSION_DISABLE 2833 uint32_t RcPanicType : __CODEGEN_BITFIELD(22, 22) ; //!< RC_PANIC_TYPE 2834 uint32_t RcPanicEnable : __CODEGEN_BITFIELD(23, 23) ; //!< RC_PANIC_ENABLE 2835 uint32_t RcStableTolerance : __CODEGEN_BITFIELD(24, 27) ; //!< RC Stable Tolerance 2836 uint32_t RcTriggleMode : __CODEGEN_BITFIELD(28, 29) ; //!< RC_TRIGGLE_MODE 2837 uint32_t Resetratecontrolcounter : __CODEGEN_BITFIELD(30, 30) ; //!< RESETRATECONTROLCOUNTER 2838 uint32_t RateControlCounterEnable : __CODEGEN_BITFIELD(31, 31) ; //!< RATE_CONTROL_COUNTER_ENABLE 2839 }; 2840 uint32_t Value; 2841 } DW6; 2842 union 2843 { 2844 //!< DWORD 7 2845 struct 2846 { 2847 uint32_t IndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect PAK-BSE Data Start Address (Write) 2848 uint32_t Reserved253 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2849 }; 2850 uint32_t Value; 2851 } DW7; 2852 union 2853 { 2854 //!< DWORD 8 2855 struct 2856 { 2857 uint32_t GrowParamGrowInit : __CODEGEN_BITFIELD( 0, 3) ; //!< Grow Param - Grow Init 2858 uint32_t GrowParamGrowResistance : __CODEGEN_BITFIELD( 4, 7) ; //!< Grow Param - Grow Resistance 2859 uint32_t ShrinkParamShrinkInit : __CODEGEN_BITFIELD( 8, 11) ; //!< Shrink Param - Shrink Init 2860 uint32_t ShrinkParamShrinkResistance : __CODEGEN_BITFIELD(12, 15) ; //!< Shrink Param - Shrink Resistance 2861 uint32_t MagnitudeOfQpMaxPositiveModifier : __CODEGEN_BITFIELD(16, 23) ; //!< Magnitude of QP Max Positive Modifier 2862 uint32_t MagnitudeOfQpMaxNegativeModifier : __CODEGEN_BITFIELD(24, 31) ; //!< Magnitude of QP Max Negative Modifier 2863 }; 2864 uint32_t Value; 2865 } DW8; 2866 union 2867 { 2868 //!< DWORD 9 2869 struct 2870 { 2871 uint32_t Correct1 : __CODEGEN_BITFIELD( 0, 3) ; //!< Correct 1 2872 uint32_t Correct2 : __CODEGEN_BITFIELD( 4, 7) ; //!< Correct 2 2873 uint32_t Correct3 : __CODEGEN_BITFIELD( 8, 11) ; //!< Correct 3 2874 uint32_t Correct4 : __CODEGEN_BITFIELD(12, 15) ; //!< Correct 4 2875 uint32_t Correct5 : __CODEGEN_BITFIELD(16, 19) ; //!< Correct 5 2876 uint32_t Correct6 : __CODEGEN_BITFIELD(20, 23) ; //!< Correct 6 2877 uint32_t Roundintra : __CODEGEN_BITFIELD(24, 26) ; //!< ROUNDINTRA 2878 uint32_t Roundintraenable : __CODEGEN_BITFIELD(27, 27) ; //!< RoundIntraEnable 2879 uint32_t Roundinter : __CODEGEN_BITFIELD(28, 30) ; //!< ROUNDINTER 2880 uint32_t Roundinterenable : __CODEGEN_BITFIELD(31, 31) ; //!< RoundInterEnable 2881 }; 2882 uint32_t Value; 2883 } DW9; 2884 union 2885 { 2886 //!< DWORD 10 2887 struct 2888 { 2889 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 2890 uint32_t Cv1 : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 2891 uint32_t Cv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 2892 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 2893 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 2894 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 2895 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 2896 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31) ; //!< ClampValues - CV7 2897 }; 2898 uint32_t Value; 2899 } DW10; 2900 2901 //! \name Local enumerations 2902 2903 enum COMMAND_SUBOPCODEB 2904 { 2905 COMMAND_SUBOPCODEB_MFXAVCSLICESTATE = 3, //!< No additional details 2906 }; 2907 2908 enum SUBOPCODEA 2909 { 2910 SUBOPCODEA_MFXAVCSLICESTATE = 0, //!< No additional details 2911 }; 2912 2913 enum COMMAND_OPCODE 2914 { 2915 COMMAND_OPCODE_AVC = 1, //!< No additional details 2916 }; 2917 2918 enum PIPELINE 2919 { 2920 PIPELINE_MFXAVCSLICESTATE = 2, //!< No additional details 2921 }; 2922 2923 enum COMMAND_TYPE 2924 { 2925 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2926 }; 2927 2928 //! \brief SLICE_TYPE 2929 //! \details 2930 //! It is set to the value of the syntax element read from the Slice Header. 2931 enum SLICE_TYPE 2932 { 2933 SLICE_TYPE_PSLICE = 0, //!< No additional details 2934 SLICE_TYPE_BSLICE = 1, //!< No additional details 2935 SLICE_TYPE_ISLICE = 2, //!< No additional details 2936 }; 2937 2938 enum DISABLE_DEBLOCKING_FILTER_INDICATOR 2939 { 2940 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED0 = 0, //!< FilterInternalEdgesFlag is set equal to 1 2941 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED1 = 1, //!< Disable all deblocking operation, no deblocking parameter syntax element is read; filterInternalEdgesFlag is set equal to 0 2942 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED2 = 2, //!< Macroblocks in different slices are considered not available; filterInternalEdgesFlag is set equal to 1 2943 }; 2944 2945 //! \brief DIRECT_PREDICTION_TYPE 2946 //! \details 2947 //! Type of direct prediction used for B Slices. This field is valid only 2948 //! for Slice_Type = B Slice; otherwise, it must be set to 0. 2949 enum DIRECT_PREDICTION_TYPE 2950 { 2951 DIRECT_PREDICTION_TYPE_TEMPORAL = 0, //!< No additional details 2952 DIRECT_PREDICTION_TYPE_SPATIAL = 1, //!< No additional details 2953 }; 2954 2955 //! \brief CABACZEROWORDINSERTIONENABLE 2956 //! \details 2957 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2958 //! requirement. 2959 enum CABACZEROWORDINSERTIONENABLE 2960 { 2961 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion 2962 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP(effectively can be used as an indicator for last slice of a picture, if the assumption is only the last slice of a picture needs to insert CABAC_ZERO_WORDs. 2963 }; 2964 2965 //! \brief EMULATIONBYTESLICEINSERTENABLE 2966 //! \details 2967 //! To have PAK outputting SODB or EBSP to the output bitstream buffer 2968 enum EMULATIONBYTESLICEINSERTENABLE 2969 { 2970 EMULATIONBYTESLICEINSERTENABLE_UNNAMED0 = 0, //!< outputting RBSP 2971 EMULATIONBYTESLICEINSERTENABLE_UNNAMED1 = 1, //!< outputting EBSP 2972 }; 2973 2974 enum TAIL_INSERTION_PRESENT_IN_BITSTREAM 2975 { 2976 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits 2977 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 2978 }; 2979 2980 enum SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2981 { 2982 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No Slice Data insertion into the output bitstream buffer 2983 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Slice Data insertion into the output bitstream buffer is present. 2984 }; 2985 2986 //! \brief HEADER_INSERTION_PRESENT_IN_BITSTREAM 2987 //! \details 2988 //! Note: In VDEnc mode, the slice header PAK object maximum size is 25 DWs. 2989 enum HEADER_INSERTION_PRESENT_IN_BITSTREAM 2990 { 2991 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, in front of the current slice encoded bits. 2992 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 2993 }; 2994 2995 //! \brief IS_LAST_SLICE 2996 //! \details 2997 //! It is used by the zero filling in the Minimum Frame Size test. 2998 enum IS_LAST_SLICE 2999 { 3000 IS_LAST_SLICE_UNNAMED0 = 0, //!< Current slice is NOT the last slice of a picture 3001 IS_LAST_SLICE_UNNAMED1 = 1, //!< Current slice is the last slice of a picture 3002 }; 3003 3004 //! \brief MB_TYPE_SKIP_CONVERSION_DISABLE 3005 //! \details 3006 //! For all Macroblock type conversions in different slices, refer to 3007 //! Section "Macroblock Type Conversion Rules" in the same volume. 3008 enum MB_TYPE_SKIP_CONVERSION_DISABLE 3009 { 3010 MB_TYPE_SKIP_CONVERSION_DISABLE_ENABLESKIPTYPECONVERSION = 0, //!< No additional details 3011 MB_TYPE_SKIP_CONVERSION_DISABLE_DISABLESKIPTYPECONVERSION = 1, //!< No additional details 3012 }; 3013 3014 //! \brief MB_TYPE_DIRECT_CONVERSION_DISABLE 3015 //! \details 3016 //! For all Macroblock type conversions in different slices, refer to 3017 //! Section "Macroblock Type Conversion Rules" in the same volume. 3018 enum MB_TYPE_DIRECT_CONVERSION_DISABLE 3019 { 3020 MB_TYPE_DIRECT_CONVERSION_DISABLE_ENABLEDIRECTMODECONVERSION = 0, //!< No additional details 3021 MB_TYPE_DIRECT_CONVERSION_DISABLE_DISABLEDIRECTMODECONVERSION = 1, //!< No additional details 3022 }; 3023 3024 //! \brief RC_PANIC_TYPE 3025 //! \details 3026 //! This field selects between two RC Panic methods 3027 enum RC_PANIC_TYPE 3028 { 3029 RC_PANIC_TYPE_QPPANIC = 0, //!< No additional details 3030 RC_PANIC_TYPE_CBPPANIC = 1, //!< No additional details 3031 }; 3032 3033 //! \brief RC_PANIC_ENABLE 3034 //! \details 3035 //! If this field is set to 1, RC enters panic mode when sum_act > 3036 //! sum_max. RC Panic Type field controls what type of panic behavior is 3037 //! invoked. 3038 enum RC_PANIC_ENABLE 3039 { 3040 RC_PANIC_ENABLE_DISABLE = 0, //!< No additional details 3041 RC_PANIC_ENABLE_ENABLE = 1, //!< No additional details 3042 }; 3043 3044 enum RC_TRIGGLE_MODE 3045 { 3046 RC_TRIGGLE_MODE_ALWAYSRATECONTROL = 0, //!< Whereas RC becomes active if sum_act > sum_target or sum_act < sum_target 3047 RC_TRIGGLE_MODE_GENTLERATECONTROL = 1, //!< whereas RC becomes active if sum_act > upper_midpt or sum_act < lower_midpt 3048 RC_TRIGGLE_MODE_LOOSERATECONTROL = 2, //!< whereas RC becomes active if sum_act > sum_max or sum_act < sum_min 3049 }; 3050 3051 //! \brief RESETRATECONTROLCOUNTER 3052 //! \details 3053 //! To reset the bit allocation accumulation counter to 0 to restart the 3054 //! rate control. 3055 enum RESETRATECONTROLCOUNTER 3056 { 3057 RESETRATECONTROLCOUNTER_NOTRESET = 0, //!< No additional details 3058 RESETRATECONTROLCOUNTER_RESET = 1, //!< No additional details 3059 }; 3060 3061 //! \brief RATE_CONTROL_COUNTER_ENABLE 3062 //! \details 3063 //! To enable the accumulation of bit allocation for rate control 3064 //! This field enables hardware Rate Control logic. The rest of the RC 3065 //! control fields are only valid when this field is set to 1. Otherwise, 3066 //! hardware ignores these fields. 3067 enum RATE_CONTROL_COUNTER_ENABLE 3068 { 3069 RATE_CONTROL_COUNTER_ENABLE_DISABLE = 0, //!< No additional details 3070 RATE_CONTROL_COUNTER_ENABLE_ENABLE = 1, //!< No additional details 3071 }; 3072 3073 //! \brief ROUNDINTRA 3074 //! \details 3075 //! Rounding precision for Intra quantized coefficients 3076 enum ROUNDINTRA 3077 { 3078 ROUNDINTRA_116 = 0, //!< No additional details 3079 ROUNDINTRA_216 = 1, //!< No additional details 3080 ROUNDINTRA_316 = 2, //!< No additional details 3081 ROUNDINTRA_416 = 3, //!< No additional details 3082 ROUNDINTRA_516 = 4, //!< No additional details 3083 ROUNDINTRA_616 = 5, //!< No additional details 3084 ROUNDINTRA_716 = 6, //!< No additional details 3085 ROUNDINTRA_816 = 7, //!< No additional details 3086 }; 3087 3088 //! \brief ROUNDINTER 3089 //! \details 3090 //! Rounding precision for Inter quantized coefficients 3091 enum ROUNDINTER 3092 { 3093 ROUNDINTER_116 = 0, //!< No additional details 3094 ROUNDINTER_216 = 1, //!< No additional details 3095 ROUNDINTER_316 = 2, //!< No additional details 3096 ROUNDINTER_416 = 3, //!< No additional details 3097 ROUNDINTER_516 = 4, //!< No additional details 3098 ROUNDINTER_616 = 5, //!< No additional details 3099 ROUNDINTER_716 = 6, //!< No additional details 3100 ROUNDINTER_816 = 7, //!< No additional details 3101 }; 3102 3103 //! \name Initializations 3104 3105 //! \brief Explicit member initialization function 3106 MFX_AVC_SLICE_STATE_CMD(); 3107 3108 static const size_t dwSize = 11; 3109 static const size_t byteSize = 44; 3110 }; 3111 3112 //! 3113 //! \brief MFD_AVC_DPB_STATE 3114 //! \details 3115 //! This is a frame level state command used only in AVC Short Slice 3116 //! Bitstream Format VLD mode. RefFrameList[16] of interface is 3117 //! replaced with intel Reference Picture Addresses[16] of 3118 //! MFX_PIPE_BUF_ADDR_STATE command. The LongTerm Picture flag indicator of 3119 //! all reference pictures are collected into LongTermPic_Flag[16]. 3120 //! FieldOrderCntList[16][2] and CurrFieldOrderCnt[2] of interface are 3121 //! replaced with intel POCList[34] of MFX_AVC_DIRECTMODE_STATE command. 3122 //! 3123 struct MFD_AVC_DPB_STATE_CMD 3124 { 3125 union 3126 { 3127 //!< DWORD 0 3128 struct 3129 { 3130 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3131 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3132 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3133 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3134 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3135 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3136 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3137 }; 3138 uint32_t Value; 3139 } DW0; 3140 union 3141 { 3142 //!< DWORD 1 3143 struct 3144 { 3145 uint32_t NonExistingframeFlag161Bit : __CODEGEN_BITFIELD( 0, 15) ; //!< NON_EXISTINGFRAME_FLAG161_BIT 3146 uint32_t LongtermframeFlag161Bit : __CODEGEN_BITFIELD(16, 31) ; //!< LONGTERMFRAME_FLAG161_BIT 3147 }; 3148 uint32_t Value; 3149 } DW1; 3150 union 3151 { 3152 //!< DWORD 2 3153 struct 3154 { 3155 uint32_t UsedforreferenceFlag162Bits ; //!< USEDFORREFERENCE_FLAG162_BITS 3156 }; 3157 uint32_t Value; 3158 } DW2; 3159 3160 uint32_t Ltstframenumlist1616Bits[8]; //!< LTSTFRAMENUMLIST1616_BITS 3161 3162 uint32_t Viewidlist1616Bits[8]; //!< ViewIDList[16][16 bits] 3163 3164 uint32_t Vieworderlistl0168Bits[4]; //!< ViewOrderListL0[16][8 bits] 3165 3166 uint32_t Vieworderlistl1168Bits[4]; //!< ViewOrderListL1[16][8 bits] 3167 3168 //! \name Local enumerations 3169 3170 enum SUBOPCODE_B 3171 { 3172 SUBOPCODE_B_UNNAMED6 = 6, //!< No additional details 3173 }; 3174 3175 enum SUBOPCODE_A 3176 { 3177 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3178 }; 3179 3180 enum MEDIA_COMMAND_OPCODE 3181 { 3182 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3183 }; 3184 3185 enum PIPELINE 3186 { 3187 PIPELINE_MFXMULTIDW = 2, //!< No additional details 3188 }; 3189 3190 enum COMMAND_TYPE 3191 { 3192 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3193 }; 3194 3195 //! \brief NON_EXISTINGFRAME_FLAG161_BIT 3196 //! \details 3197 //! One-to-one correspondence with the entries of the Intel 3198 //! RefFrameList[16]. 1 bit per reference frame. 3199 enum NON_EXISTINGFRAME_FLAG161_BIT 3200 { 3201 NON_EXISTINGFRAME_FLAG161_BIT_VALID = 0, //!< the reference picture in that entry of RefFrameList[] is a valid reference 3202 NON_EXISTINGFRAME_FLAG161_BIT_INVALID = 1, //!< the reference picture in that entry of RefFrameList[] does not exist anymore. 3203 }; 3204 3205 //! \brief LONGTERMFRAME_FLAG161_BIT 3206 //! \details 3207 //! One-to-one correspondence with the entries of the Intel 3208 //! RefFrameList[16]. 1 bit per reference frame. 3209 enum LONGTERMFRAME_FLAG161_BIT 3210 { 3211 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISASHORTTERMREFERENCEPICTURE = 0, //!< No additional details 3212 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISALONGTERMREFERENCEPICTURE = 1, //!< No additional details 3213 }; 3214 3215 //! \brief USEDFORREFERENCE_FLAG162_BITS 3216 //! \details 3217 //! One-to-one correspondence with the entries of the Intel 3218 //! RefFrameList[16]. 2 bits per reference frame. 3219 enum USEDFORREFERENCE_FLAG162_BITS 3220 { 3221 USEDFORREFERENCE_FLAG162_BITS_NOTREFERENCE = 0, //!< indicates a frame is "not used for reference". 3222 USEDFORREFERENCE_FLAG162_BITS_TOPFIELD = 1, //!< bit[0] indicates that the top field of a frame is marked as "used for reference". 3223 USEDFORREFERENCE_FLAG162_BITS_BOTTOMFIELD = 2, //!< bit[1] indicates that the bottom field of a frame is marked as "used for reference". 3224 USEDFORREFERENCE_FLAG162_BITS_FRAME = 3, //!< bit[1:0] indicates that a frame (or field pair) is marked as "used for reference". 3225 }; 3226 3227 //! \brief LTSTFRAMENUMLIST1616_BITS 3228 //! \details 3229 //! One-to-one correspondence with the entries of the Intel 3230 //! RefFrameList[16]. 16 bits per reference frame.Depending on the 3231 //! corresponding LongTermFrame_Flag[], the content of this field is 3232 //! interpreted differently. 3233 enum LTSTFRAMENUMLIST1616_BITS 3234 { 3235 LTSTFRAMENUMLIST1616_BITS_SHORTTERMFRAMEFLAGI = 0, //!< LTSTFrameNumList[i]represent Short Term Picture FrameNum. 3236 LTSTFRAMENUMLIST1616_BITS_LONGTERMFRAMEFLAGI = 1, //!< LTSTFrameNumList[i] represent LongTermFrameIdx. 3237 }; 3238 3239 //! \name Initializations 3240 3241 //! \brief Explicit member initialization function 3242 MFD_AVC_DPB_STATE_CMD(); 3243 3244 static const size_t dwSize = 27; 3245 static const size_t byteSize = 108; 3246 }; 3247 3248 //! 3249 //! \brief MFD_AVC_SLICEADDR 3250 //! \details 3251 //! This is a Slice level command used only for AVC Short Slice 3252 //! Bitstream Format VLD mode.When decoding a slice, H/W needs to know the 3253 //! last MB of the slice has reached in order to start decoding the next 3254 //! slice. It also needs to know if a slice is terminated but the last MB 3255 //! has not reached, error conealment should be invoked to generate those 3256 //! missing MBs. For AVC Short Format, the only way to know the last 3257 //! MB position of the current slice, H/W needs to snoop into the next 3258 //! slice's start MB address (a linear address encoded in the Slice Header). 3259 //! Since each BSD Object command can have only one indirect bitstream 3260 //! buffer address, this command is added to help H/W to snoop into the next 3261 //! slice's slice header and retrieve its Start MB Address. This command 3262 //! will take the next slice's bitstream buffer address as input (exactly 3263 //! the same way as a BSD Object command), and parse only the 3264 //! first_mb_in_slice syntax element. The result will stored inside the H/W, 3265 //! and will be used to decode the current slice specified in the BSD Object 3266 //! command.Only the very first few bytes (max 5 bytes for a max 4K picture) 3267 //! of the Slice Header will be decoded, the rest of the bitstream are don't 3268 //! care. This is because the first_mb_in_slice is encoded in Exponential 3269 //! Golomb, and will take 33 bits to represent the max 256 x 256 = 64K-1 3270 //! value. The indirect data of MFD_AVC_SLICEADDR is a valid BSD object and 3271 //! is decoded as in BSD OBJECT command.The next Slice Start MB Address is 3272 //! also exposed to the MMIO interface.The Slice Start MB Address 3273 //! (first_mb_in_slice) is a linear MB address count; but it is translated 3274 //! into the corresponding 2D MB X and Y raster position, and are stored 3275 //! internally as NextSliceMbY and NextSliceMbX. 3276 //! 3277 struct MFD_AVC_SLICEADDR_CMD 3278 { 3279 union 3280 { 3281 //!< DWORD 0 3282 struct 3283 { 3284 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3285 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3286 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3287 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3288 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3289 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3290 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3291 }; 3292 uint32_t Value; 3293 } DW0; 3294 union 3295 { 3296 //!< DWORD 1 3297 struct 3298 { 3299 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3300 }; 3301 uint32_t Value; 3302 } DW1; 3303 union 3304 { 3305 //!< DWORD 2 3306 struct 3307 { 3308 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect BSD Data Start Address 3309 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3310 }; 3311 uint32_t Value; 3312 } DW2; 3313 3314 //! \name Local enumerations 3315 3316 enum SUBOPCODE_B 3317 { 3318 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 3319 }; 3320 3321 enum SUBOPCODE_A 3322 { 3323 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3324 }; 3325 3326 enum MEDIA_COMMAND_OPCODE 3327 { 3328 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3329 }; 3330 3331 enum PIPELINE 3332 { 3333 PIPELINE_MFDAVCSLICEADDR = 2, //!< No additional details 3334 }; 3335 3336 enum COMMAND_TYPE 3337 { 3338 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3339 }; 3340 3341 //! \name Initializations 3342 3343 //! \brief Explicit member initialization function 3344 MFD_AVC_SLICEADDR_CMD(); 3345 3346 static const size_t dwSize = 3; 3347 static const size_t byteSize = 12; 3348 }; 3349 3350 //! 3351 //! \brief MFD_AVC_BSD_OBJECT 3352 //! \details 3353 //! The MFD_AVC_BSD_OBJECT command is the only primitive command for the AVC 3354 //! Decoding Pipeline. The same command is used for both CABAC and CAVLD 3355 //! modes. The Slice Data portion of the bitstream is loaded as indirect 3356 //! data object.Before issuing a MFD_AVC_BSD_OBJECT command, all AVC states 3357 //! of the MFD Engine need to be valid. Therefore the commands used to set 3358 //! these states need to have been issued prior to the issue of a 3359 //! MFD_AVC_BSD_OBJECT command. 3360 //! 3361 //! Context switch interrupt is not supported by this command. 3362 //! 3363 struct MFD_AVC_BSD_OBJECT_CMD 3364 { 3365 union 3366 { 3367 //!< DWORD 0 3368 struct 3369 { 3370 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3371 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3372 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3373 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3374 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3375 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3376 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3377 }; 3378 uint32_t Value; 3379 } DW0; 3380 union 3381 { 3382 //!< DWORD 1 3383 struct 3384 { 3385 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3386 }; 3387 uint32_t Value; 3388 } DW1; 3389 union 3390 { 3391 //!< DWORD 2 3392 struct 3393 { 3394 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect BSD Data Start Address 3395 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3396 }; 3397 uint32_t Value; 3398 } DW2; 3399 union 3400 { 3401 //!< DWORD 3 3402 struct 3403 { 3404 uint32_t MbErrorConcealmentPSliceWeightPredictionDisableFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3405 uint32_t MbErrorConcealmentPSliceMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3406 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 3407 uint32_t MbErrorConcealmentBSpatialWeightPredictionDisableFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3408 uint32_t MbErrorConcealmentBSpatialMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3409 uint32_t Reserved101 : __CODEGEN_BITFIELD( 5, 5) ; //!< Reserved 3410 uint32_t MbErrorConcealmentBSpatialPredictionMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3411 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD( 8, 8) ; //!< MB_HEADER_ERROR_HANDLING_ 3412 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 3413 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10) ; //!< ENTROPY_ERROR_HANDLING 3414 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 3415 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3416 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 3417 uint32_t BsdPrematureCompleteErrorHandling : __CODEGEN_BITFIELD(14, 14) ; //!< BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3418 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3419 uint32_t ConcealmentPictureId : __CODEGEN_BITFIELD(16, 21) ; //!< Concealment Picture ID 3420 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3421 uint32_t MbErrorConcealmentBTemporalWeightPredictionDisableFlag : __CODEGEN_BITFIELD(24, 24) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3422 uint32_t MbErrorConcealmentBTemporalMotionVectorsOverrideEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3423 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 3424 uint32_t MbErrorConcealmentBTemporalPredictionMode : __CODEGEN_BITFIELD(27, 28) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3425 uint32_t IntraPredmode4X48X8LumaErrorControlBit : __CODEGEN_BITFIELD(29, 29) ; //!< INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3426 uint32_t InitCurrentMbNumber : __CODEGEN_BITFIELD(30, 30) ; //!< Init Current MB Number 3427 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31) ; //!< CONCEALMENT_METHOD 3428 }; 3429 uint32_t Value; 3430 } DW3; 3431 union 3432 { 3433 //!< DWORD 4 3434 struct 3435 { 3436 uint32_t FirstMacroblockMbBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< First Macroblock (MB)Bit Offset 3437 uint32_t LastsliceFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< LASTSLICE_FLAG 3438 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD( 4, 4) ; //!< EMULATION_PREVENTION_BYTE_PRESENT 3439 uint32_t Reserved133 : __CODEGEN_BITFIELD( 5, 6) ; //!< Reserved 3440 uint32_t FixPrevMbSkipped : __CODEGEN_BITFIELD( 7, 7) ; //!< Fix Prev Mb Skipped 3441 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3442 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31) ; //!< First MB Byte Offset of Slice Data or Slice Header 3443 }; 3444 uint32_t Value; 3445 } DW4; 3446 union 3447 { 3448 //!< DWORD 5 3449 struct 3450 { 3451 uint32_t IntraPredictionErrorControlBitAppliedToIntra16X16Intra8X8Intra4X4LumaAndChroma : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3452 uint32_t Intra8X84X4PredictionErrorConcealmentControlBit : __CODEGEN_BITFIELD( 1, 1) ; //!< INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3453 uint32_t Reserved162 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 3454 uint32_t BSliceTemporalInterConcealmentMode : __CODEGEN_BITFIELD( 4, 6) ; //!< B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3455 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3456 uint32_t BSliceSpatialInterConcealmentMode : __CODEGEN_BITFIELD( 8, 10) ; //!< B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3457 uint32_t Reserved171 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 3458 uint32_t BSliceInterDirectTypeConcealmentMode : __CODEGEN_BITFIELD(12, 13) ; //!< B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3459 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 3460 uint32_t BSliceConcealmentMode : __CODEGEN_BITFIELD(15, 15) ; //!< B_SLICE_CONCEALMENT_MODE 3461 uint32_t PSliceInterConcealmentMode : __CODEGEN_BITFIELD(16, 18) ; //!< P_SLICE_INTER_CONCEALMENT_MODE 3462 uint32_t Reserved179 : __CODEGEN_BITFIELD(19, 22) ; //!< Reserved 3463 uint32_t PSliceConcealmentMode : __CODEGEN_BITFIELD(23, 23) ; //!< P_SLICE_CONCEALMENT_MODE 3464 uint32_t ConcealmentReferencePictureFieldBit : __CODEGEN_BITFIELD(24, 29) ; //!< Concealment Reference Picture + Field Bit 3465 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 3466 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31) ; //!< I_SLICE_CONCEALMENT_MODE 3467 }; 3468 uint32_t Value; 3469 } DW5; 3470 3471 //! \name Local enumerations 3472 3473 enum SUBOPCODE_B 3474 { 3475 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3476 }; 3477 3478 enum SUBOPCODE_A 3479 { 3480 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3481 }; 3482 3483 enum MEDIA_COMMAND_OPCODE 3484 { 3485 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3486 }; 3487 3488 enum PIPELINE 3489 { 3490 PIPELINE_MFDAVCBSDOBJECT = 2, //!< No additional details 3491 }; 3492 3493 enum COMMAND_TYPE 3494 { 3495 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3496 }; 3497 3498 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3499 //! \details 3500 //! During MB Error Concealment on P slice, weight prediction is disabled to 3501 //! improve image quality. 3502 //! This bit can be set to preserve the original weight prediction. 3503 //! This bit does not affect normal decoded MB. 3504 enum MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3505 { 3506 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3507 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3508 }; 3509 3510 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3511 //! \details 3512 //! During MB Error Concealment on P slice, motion vectors are forced to 0 3513 //! to improve image quality. 3514 //! This bit can be set to use the predicted motion vectors instead. 3515 //! This bit does not affect normal decoded MB. 3516 enum MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3517 { 3518 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3519 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3520 }; 3521 3522 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3523 //! \details 3524 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3525 //! weight prediction is disabled to improve image quality. 3526 //! This bit can be set to preserve the original weight prediction. 3527 //! This bit does not affect normal decoded MB. 3528 enum MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3529 { 3530 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3531 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3532 }; 3533 3534 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3535 //! \details 3536 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3537 //! motion vectors are forced to 0 to improve image quality. 3538 //! This bit can be set to use the predicted motion vectors instead. 3539 //! This bit does not affect normal decoded MB. 3540 enum MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3541 { 3542 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3543 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3544 }; 3545 3546 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3547 //! \details 3548 //! These two bits control how the reference L0/L1 are overridden in B 3549 //! spatial slice. 3550 enum MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3551 { 3552 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3553 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3554 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3555 }; 3556 3557 //! \brief MB_HEADER_ERROR_HANDLING_ 3558 //! \details 3559 //! Software must follow the action for each Value as follow: 3560 enum MB_HEADER_ERROR_HANDLING_ 3561 { 3562 MB_HEADER_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error concealment. 3563 MB_HEADER_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3564 }; 3565 3566 //! \brief ENTROPY_ERROR_HANDLING 3567 //! \details 3568 //! Software must follow the action for each Value as follow: 3569 enum ENTROPY_ERROR_HANDLING 3570 { 3571 ENTROPY_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error handling. 3572 ENTROPY_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3573 }; 3574 3575 //! \brief MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3576 //! \details 3577 //! Software must follow the action for each Value as follow: 3578 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3579 { 3580 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3581 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3582 }; 3583 3584 //! \brief BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3585 //! \details 3586 //! BSD Premature Complete Error occurs in situation where the Slice decode 3587 //! is completed but there are still data in the bitstream. 3588 enum BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3589 { 3590 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3591 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3592 }; 3593 3594 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3595 //! \details 3596 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3597 //! weight prediction is disabled to improve image quality. 3598 //! This bit can be set to preserve the original weight prediction. 3599 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3600 { 3601 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment 3602 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment 3603 }; 3604 3605 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3606 //! \details 3607 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3608 //! motion vectors are forced to 0 to improve image quality. 3609 //! This bit can be set to preserve the original weight prediction. 3610 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3611 { 3612 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED0 = 0, //!< Predicted Motion Vectors are used during MB Concealment 3613 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED1 = 1, //!< Motion Vectors are Overridden to 0 during MB Concealment 3614 }; 3615 3616 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3617 //! \details 3618 //! These two bits control how the reference L0/L1 are overridden in B 3619 //! temporal slice. 3620 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3621 { 3622 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3623 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3624 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3625 }; 3626 3627 //! \brief INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3628 //! \details 3629 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3630 //! decoded value is incorrect according to MB position 3631 enum INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3632 { 3633 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will detect and fix IntraPredMode (4x4/8x8 Luma) Errors. 3634 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will NOT detect IntraPredMode (4x4/8x8 Luma) Errors. The wrong IntraPredMode value will be retaind. 3635 }; 3636 3637 //! \brief CONCEALMENT_METHOD 3638 //! \details 3639 //! This field specifies the method used for concealment when error is 3640 //! detected. If set, a copy from collocated macroblock location is 3641 //! performed from the concealment reference indicated by the ConCeal_Pic_Id 3642 //! field. If it is not set, a copy from the current picture is performed 3643 //! using Intra 16x16 Prediction method. 3644 enum CONCEALMENT_METHOD 3645 { 3646 CONCEALMENT_METHOD_UNNAMED0 = 0, //!< Intra 16x16 Prediction 3647 CONCEALMENT_METHOD_UNNAMED1 = 1, //!< Inter P Copy 3648 }; 3649 3650 //! \brief LASTSLICE_FLAG 3651 //! \details 3652 //! It is needed for both error concealment at the end of a picture (so, no 3653 //! more phantom slice as in DevSNB). It is also needed to know to set the 3654 //! last MB in a picture correctly. 3655 enum LASTSLICE_FLAG 3656 { 3657 LASTSLICE_FLAG_UNNAMED0 = 0, //!< If the current Slice to be decoded is any slice other than the very last slice of the current picture 3658 LASTSLICE_FLAG_UNNAMED1 = 1, //!< If the current Slice to be decoded is the very last slice of the current picture. 3659 }; 3660 3661 enum EMULATION_PREVENTION_BYTE_PRESENT 3662 { 3663 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 3664 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 3665 }; 3666 3667 //! \brief INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3668 //! \details 3669 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3670 //! decoded value is incorrect according to MB position. 3671 enum INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3672 { 3673 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED0 = 0, //!< AVC decoder will detect and fix Intra Prediction Mode Errors. 3674 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED1 = 1, //!< AVC decoder will retain the Intra Prediction value decoded from bitstream. 3675 }; 3676 3677 //! \brief INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3678 //! \details 3679 //! This field controls if AVC goes into MB concealment mode (next MB) when 3680 //! an error is detected on Intra8x8/4x4 Prediction Mode (these 2 modes have 3681 //! fixed coding so it may not affect the bitstream. 3682 enum INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3683 { 3684 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will NOT go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3685 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3686 }; 3687 3688 //! \brief B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3689 //! \details 3690 //! This field controls how AVC decoder select reference picture for 3691 //! Temporal Inter Concealment in B Slice 3692 enum B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3693 { 3694 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1) 3695 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3696 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using B-Skip Algorithm) 3697 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< " Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3698 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< First Long Term Picture in Reference List L0/L1(If no long term picture available, use Temporal Closest Picture) 3699 }; 3700 3701 //! \brief B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3702 //! \details 3703 //! This field controls how AVC decoder select reference picture for Spatial 3704 //! Inter Concealment in B Slice. 3705 enum B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3706 { 3707 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1). 3708 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3709 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3710 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< " First Long Term Picture in Reference List L0/L1 (If no long term picture available, use Temporal Closest Picture) 3711 }; 3712 3713 //! \brief B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3714 //! \details 3715 //! AVC decoder can use Spatial or Temporal Direct for B Skip/Direct. 3716 //! This field determine can override the mode on how AVC decoder 3717 //! handles MB concealment in B slice. 3718 enum B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3719 { 3720 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Use Default Direct Type (slice programmed direct type) 3721 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Forced to Spatial Direct Only 3722 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Forced to Temporal Direct Only 3723 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Spatial Direct without Temporal Componenet (MovingBlock information) 3724 }; 3725 3726 //! \brief B_SLICE_CONCEALMENT_MODE 3727 //! \details 3728 //! This field controls how AVC decoder handle MB concealment in B Slice 3729 enum B_SLICE_CONCEALMENT_MODE 3730 { 3731 B_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3732 B_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3733 }; 3734 3735 //! \brief P_SLICE_INTER_CONCEALMENT_MODE 3736 //! \details 3737 //! This field controls how AVC decoder select reference picture for 3738 //! Concealment in P Slice. 3739 enum P_SLICE_INTER_CONCEALMENT_MODE 3740 { 3741 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0 (Use top entry of Reference List L0) 3742 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3743 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using P-Skip Algorithm) 3744 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC] 3745 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< First Long Term Picture in Reference List L0 (If no long term picture available, use Temporal Closest Picture) 3746 }; 3747 3748 //! \brief P_SLICE_CONCEALMENT_MODE 3749 //! \details 3750 //! This field controls how AVC decoder handle MB concealment in P Slice 3751 enum P_SLICE_CONCEALMENT_MODE 3752 { 3753 P_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3754 P_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3755 }; 3756 3757 //! \brief I_SLICE_CONCEALMENT_MODE 3758 //! \details 3759 //! This field controls how AVC decoder handle MB concealment in I Slice 3760 enum I_SLICE_CONCEALMENT_MODE 3761 { 3762 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< No additional details 3763 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< No additional details 3764 }; 3765 3766 //! \name Initializations 3767 3768 //! \brief Explicit member initialization function 3769 MFD_AVC_BSD_OBJECT_CMD(); 3770 3771 static const size_t dwSize = 6; 3772 static const size_t byteSize = 24; 3773 }; 3774 3775 //! 3776 //! \brief MFX_PAK_INSERT_OBJECT 3777 //! \details 3778 //! The MFX_PAK_INSERT_OBJECT command is the first primitive command for the 3779 //! AVC, MPEG2, JPEG, SVC and VP8 Encoding Pipeline. 3780 //! 3781 //! This command is issued to setup the control and parameters of inserting 3782 //! a chunk of compressed/encoded bits into the current bitstream output 3783 //! buffer starting at the specified bit locationto perform the actual 3784 //! insertion by transferring the command inline data to the output buffer 3785 //! max, 32 bits at a time. It is a variable length command as the data to 3786 //! be inserted are presented as inline data of this command. It is a 3787 //! multiple of 32-bit (1 DW), as the data bus to the bitstream buffer is 3788 //! 32-bit wide. Multiple insertion commands can be issued back to back in a 3789 //! series. It is host software's responsibility to make sure their 3790 //! corresponding data will properly stitch together to form a valid H.264 3791 //! bitstream. Internally, MFX hardware will keep track of the very last two 3792 //! bytes' (the very last byte can be a partial byte) values of the previous 3793 //! insertion. It is required that the next Insertion Object Command or the 3794 //! next PAK Object Command to perform the start code emulation sequence 3795 //! check and prevention 0x03 byte insertion with this end condition of the 3796 //! previous insertion. Hardware will keep track of an output bitstream 3797 //! buffer current byte position and the associated next bit insertion 3798 //! position index. Data to be inserted can be a valid H.264 NAL units or a 3799 //! partial NAL unit. Certain NAL unit has a minimum byte size requirement. 3800 //! As such the hardware will optionally (enabled by STATE Command) 3801 //! determines the number of CABAC_ZERO_WORD to be inserted to the end of 3802 //! the current NAL, based on the minimum byte size of a NAL and the actual 3803 //! bin count of the encoded Slice. Since prior to the CABAC_ZERO_WORD 3804 //! insertion, the RBSP or EBSP is already byte-aligned, so each 3805 //! CABAC_ZERO_WORD insertion is actually a 3-byte sequence 0x00 00 03. The 3806 //! inline data may have already been processed for start code emulation 3807 //! byte insertion, except the possibility of the last 2 bytes plus the very 3808 //! last partial byte (if any). Hence, when hardware performing the 3809 //! concatenation of multiple consecutive insertion commands, or 3810 //! concatenation of an insertion command and a PAK object command, it must 3811 //! check and perform the necessary start code emulation byte insert at the 3812 //! junction.The inline data is required to be byte aligned on the left 3813 //! (first transmitted bit order) and may or may not be byte aligned on the 3814 //! right (last transmitted bits). The command will specify the bit offset 3815 //! of the last valid DW.Each insertion state command defines a chunk of 3816 //! bits (compressed data) to be inserted at a specific location of the 3817 //! output compressed bitstream in the output buffer.Depend on CABAC or 3818 //! CAVLC encoding mode (from Slice State), PAK Object Command is always 3819 //! ended in byte aligned output bitstream except for CABAC header insertion 3820 //! which is bit aligned. In the aligned cases, PAK will perform 0 filling 3821 //! in CAVLC mode, and 1 filling in CABAC mode. Insertion data can 3822 //! include:any encoded syntax elements bit data before the encoded Slice 3823 //! Data (PAK Object Command) of the current SliceSPS NALPPS NALSEI NALOther 3824 //! Non-Slice NALLeading_Zero_8_bits (as many bytes as there is)Start Code 3825 //! PrefixNAL Header ByteSlice HeaderAny encoded syntax elements bit data 3826 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3827 //! and prior to the next encoded Slice Data of the next Slice or prior to 3828 //! the end of the bistream, whichever comes firstCabac_Zero_Word or 3829 //! Trailing_Zero_8bits (as many bytes as there is). Anything listed above 3830 //! before a Slice DataContext switch interrupt is not supported by this 3831 //! command. 3832 //! 3833 struct MFX_PAK_INSERT_OBJECT_CMD 3834 { 3835 union 3836 { 3837 //!< DWORD 0 3838 struct 3839 { 3840 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3841 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3842 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3843 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3844 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3845 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3846 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3847 }; 3848 uint32_t Value; 3849 } DW0; 3850 union 3851 { 3852 //!< DWORD 1 3853 struct 3854 { 3855 uint32_t BitstreamstartresetResetbitstreamstartingpos : __CODEGEN_BITFIELD( 0, 0) ; //!< BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3856 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3857 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3858 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3859 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 3860 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3861 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< SLICE_HEADER_INDICATOR 3862 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3863 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3864 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 3865 }; 3866 uint32_t Value; 3867 } DW1; 3868 3869 //! \name Local enumerations 3870 3871 enum SUBOPCODE_B 3872 { 3873 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3874 }; 3875 3876 enum SUBOPCODE_A 3877 { 3878 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 3879 }; 3880 3881 enum MEDIA_COMMAND_OPCODE 3882 { 3883 MEDIA_COMMAND_OPCODE_MFXCOMMON = 0, //!< No additional details 3884 }; 3885 3886 enum PIPELINE 3887 { 3888 PIPELINE_MFXPAKINSERTOBJECT = 2, //!< No additional details 3889 }; 3890 3891 enum COMMAND_TYPE 3892 { 3893 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3894 }; 3895 3896 //! \brief BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3897 //! \details 3898 //! Must be set to 1 for JPEG encoder 3899 enum BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3900 { 3901 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_INSERT = 0, //!< Insert the current command inline data starting at the current bitstream buffer insertion position 3902 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_RESET = 1, //!< Reset the bitstream buffer insertion position to the bitstream buffer starting position. 3903 }; 3904 3905 //! \brief EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3906 //! \details 3907 //! Must be set to 0 for JPEG encoder 3908 enum EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3909 { 3910 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_NONE = 0, //!< No emulation 3911 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_EMULATE = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between insertion commands, or an insertion command followed by a PAK Object command. 3912 }; 3913 3914 //! \brief SLICE_HEADER_INDICATOR 3915 //! \details 3916 //! This bit indicates if the insert object is a slice header. In the VDEnc 3917 //! mode, PAK only gets this command at the beginning of the frame for slice 3918 //! position X=0, Y=0. It internally generates the header that needs to be 3919 //! inserted per slice. For VDEnc mode, this bit should always be set. 3920 enum SLICE_HEADER_INDICATOR 3921 { 3922 SLICE_HEADER_INDICATOR_LEGACY = 0, //!< Legacy Insertion Object command. The PAK Insertion Object command is not stored in HW. 3923 SLICE_HEADER_INDICATOR_SLICEHEADER = 1, //!< Insertion Object is a Slice Header. The command is stored internally by HW and is used for inserting slice headers. 3924 }; 3925 3926 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 3927 //! \details 3928 //! In case this flag is on, bits are NOT accumulated during current access 3929 //! unit coding neither for Cabac Zero Word insertion bits counting or for 3930 //! output in MMIO register MFC_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER. 3931 //! When using HeaderLenghtExcludeFrmSize for header insertion, the 3932 //! software needs to make sure that data comes already with inserted start 3933 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 3934 //! DWORD1 of MFX_PAK_INSERT_OBJECT). 3935 enum HEADERLENGTHEXCLUDEFRMSIZE_ 3936 { 3937 HEADERLENGTHEXCLUDEFRMSIZE_ACCUMULATE = 0, //!< All bits accumulated 3938 HEADERLENGTHEXCLUDEFRMSIZE_NOACCUMULATION = 1, //!< Bits during current call are not accumulated 3939 }; 3940 3941 //! \name Initializations 3942 3943 //! \brief Explicit member initialization function 3944 MFX_PAK_INSERT_OBJECT_CMD(); 3945 3946 static const size_t dwSize = 2; 3947 static const size_t byteSize = 8; 3948 }; 3949 3950 //! 3951 //! \brief MFX_MPEG2_PIC_STATE 3952 //! \details 3953 //! This must be the very first command to issue after the surface state, 3954 //! the pipe select and base address setting commands. For MPEG-2 the 3955 //! encoder is called per slice-group, however the picture state is called 3956 //! per picture.Notice that a slice-group is a group of consecutive slices 3957 //! that no non-trivial slice headers are inserted in between. 3958 //! 3959 struct MFX_MPEG2_PIC_STATE_CMD 3960 { 3961 union 3962 { 3963 //!< DWORD 0 3964 struct 3965 { 3966 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3967 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3968 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3969 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3970 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3971 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3972 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3973 }; 3974 uint32_t Value; 3975 } DW0; 3976 union 3977 { 3978 //!< DWORD 1 3979 struct 3980 { 3981 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3982 uint32_t ScanOrder : __CODEGEN_BITFIELD( 6, 6) ; //!< SCAN_ORDER 3983 uint32_t IntraVlcFormat : __CODEGEN_BITFIELD( 7, 7) ; //!< Intra VLC Format 3984 uint32_t QuantizerScaleType : __CODEGEN_BITFIELD( 8, 8) ; //!< QUANTIZER_SCALE_TYPE 3985 uint32_t ConcealmentMotionVectorFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< Concealment Motion Vector Flag 3986 uint32_t FramePredictionFrameDct : __CODEGEN_BITFIELD(10, 10) ; //!< Frame Prediction Frame DCT 3987 uint32_t TffTopFieldFirst : __CODEGEN_BITFIELD(11, 11) ; //!< TFF (Top Field First) 3988 uint32_t PictureStructure : __CODEGEN_BITFIELD(12, 13) ; //!< Picture Structure 3989 uint32_t IntraDcPrecision : __CODEGEN_BITFIELD(14, 15) ; //!< Intra DC Precision 3990 uint32_t FCode00 : __CODEGEN_BITFIELD(16, 19) ; //!< f_code[0][0] 3991 uint32_t FCode01 : __CODEGEN_BITFIELD(20, 23) ; //!< f_code[0][1] 3992 uint32_t FCode10 : __CODEGEN_BITFIELD(24, 27) ; //!< f_code[1][0]. 3993 uint32_t FCode11 : __CODEGEN_BITFIELD(28, 31) ; //!< f_code[1][1]. 3994 }; 3995 uint32_t Value; 3996 } DW1; 3997 union 3998 { 3999 //!< DWORD 2 4000 struct 4001 { 4002 uint32_t DisableMismatch : __CODEGEN_BITFIELD( 0, 0) ; //!< Disable Mismatch 4003 uint32_t Mismatchcontroldisabled : __CODEGEN_BITFIELD( 1, 1) ; //!< MISMATCHCONTROLDISABLED 4004 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 8) ; //!< Reserved 4005 uint32_t PictureCodingType : __CODEGEN_BITFIELD( 9, 10) ; //!< PICTURE_CODING_TYPE 4006 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13) ; //!< Reserved 4007 uint32_t LoadslicepointerflagLoadbitstreampointerperslice : __CODEGEN_BITFIELD(14, 14) ; //!< LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4008 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 23) ; //!< Reserved 4009 uint32_t PBSlicePredictedMotionVectorOverrideFinalMvValueOverride : __CODEGEN_BITFIELD(24, 24) ; //!< PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4010 uint32_t PBSlicePredictedBidirMotionTypeOverrideBiDirectionMvTypeOverride : __CODEGEN_BITFIELD(25, 26) ; //!< PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4011 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 27) ; //!< Reserved 4012 uint32_t PBSliceConcealmentMode : __CODEGEN_BITFIELD(28, 29) ; //!< PB_SLICE_CONCEALMENT_MODE_ 4013 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 4014 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31) ; //!< I_SLICE_CONCEALMENT_MODE_ 4015 }; 4016 uint32_t Value; 4017 } DW2; 4018 union 4019 { 4020 //!< DWORD 3 4021 struct 4022 { 4023 uint32_t Framewidthinmbsminus170PictureWidthInMacroblocks : __CODEGEN_BITFIELD( 0, 7) ; //!< FrameWidthInMBsMinus1[7:0] (Picture Width in Macroblocks) 4024 uint32_t Reserved104 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 4025 uint32_t Frameheightinmbsminus170PictureHeightInMacroblocks : __CODEGEN_BITFIELD(16, 23) ; //!< FrameHeightInMBsMinus1[7:0] (Picture Height in Macroblocks) 4026 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 30) ; //!< Reserved 4027 uint32_t SliceConcealmentDisableBit : __CODEGEN_BITFIELD(31, 31) ; //!< SLICE_CONCEALMENT_DISABLE_BIT 4028 }; 4029 uint32_t Value; 4030 } DW3; 4031 union 4032 { 4033 //!< DWORD 4 4034 struct 4035 { 4036 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 4037 uint32_t Roundintradc : __CODEGEN_BITFIELD( 1, 2) ; //!< RoundIntraDC 4038 uint32_t Reserved131 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 4039 uint32_t Roundinterdc : __CODEGEN_BITFIELD( 4, 6) ; //!< RoundInterDC 4040 uint32_t Reserved135 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 4041 uint32_t Roundintraac : __CODEGEN_BITFIELD( 8, 10) ; //!< RoundIntraAC 4042 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 4043 uint32_t Roundinterac : __CODEGEN_BITFIELD(12, 14) ; //!< RoundInterAC, 4044 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15) ; //!< MBSTATENABLED 4045 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31) ; //!< MINFRAMEWSIZE 4046 }; 4047 uint32_t Value; 4048 } DW4; 4049 union 4050 { 4051 //!< DWORD 5 4052 struct 4053 { 4054 uint32_t Intrambmaxsizereportmask : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAMBMAXSIZEREPORTMASK 4055 uint32_t Intermbmaxsizereportmask : __CODEGEN_BITFIELD( 1, 1) ; //!< INTERMBMAXSIZEREPORTMASK 4056 uint32_t Framebitratemaxreportmask : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMEBITRATEMAXREPORTMASK_ 4057 uint32_t Framebitrateminreportmask : __CODEGEN_BITFIELD( 3, 3) ; //!< FRAMEBITRATEMINREPORTMASK 4058 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 8) ; //!< Reserved 4059 uint32_t Mbratecontrolmask : __CODEGEN_BITFIELD( 9, 9) ; //!< MBRATECONTROLMASK 4060 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11) ; //!< MINFRAMEWSIZEUNITS 4061 uint32_t Intermbforcecbpzerocontrolmask : __CODEGEN_BITFIELD(12, 12) ; //!< INTERMBFORCECBPZEROCONTROLMASK 4062 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 4063 uint32_t Framesizecontrolmask : __CODEGEN_BITFIELD(16, 16) ; //!< FRAMESIZECONTROLMASK 4064 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 4065 }; 4066 uint32_t Value; 4067 } DW5; 4068 union 4069 { 4070 //!< DWORD 6 4071 struct 4072 { 4073 uint32_t Intrambmaxsize : __CODEGEN_BITFIELD( 0, 11) ; //!< INTRAMBMAXSIZE 4074 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4075 uint32_t Intermbmaxsize : __CODEGEN_BITFIELD(16, 27) ; //!< INTERMBMAXSIZE 4076 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 4077 }; 4078 uint32_t Value; 4079 } DW6; 4080 union 4081 { 4082 //!< DWORD 7 4083 struct 4084 { 4085 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSL_TOP_MB_TRANS8X8FLAG 4086 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 4087 }; 4088 uint32_t Value; 4089 } DW7; 4090 union 4091 { 4092 //!< DWORD 8 4093 struct 4094 { 4095 uint32_t Slicedeltaqpmax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQPMax[0] 4096 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQPMax[1] 4097 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQPMax[2] 4098 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31) ; //!< SLICEDELTAQPMAX3 4099 }; 4100 uint32_t Value; 4101 } DW8; 4102 union 4103 { 4104 //!< DWORD 9 4105 struct 4106 { 4107 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQPMin[0] 4108 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQPMin[1] 4109 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQPMin[2] 4110 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQPMin[3] 4111 }; 4112 uint32_t Value; 4113 } DW9; 4114 union 4115 { 4116 //!< DWORD 10 4117 struct 4118 { 4119 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 4120 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14) ; //!< FRAMEBITRATEMINUNITMODE 4121 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15) ; //!< FRAMEBITRATEMINUNIT 4122 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29) ; //!< FrameBitRateMax 4123 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30) ; //!< FRAMEBITRATEMAXUNITMODE 4124 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT_ 4125 }; 4126 uint32_t Value; 4127 } DW10; 4128 union 4129 { 4130 //!< DWORD 11 4131 struct 4132 { 4133 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FrameBitRateMinDelta 4134 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 4135 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 4136 uint32_t Reserved383 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 4137 }; 4138 uint32_t Value; 4139 } DW11; 4140 union 4141 { 4142 //!< DWORD 12 4143 struct 4144 { 4145 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4146 }; 4147 uint32_t Value; 4148 } DW12; 4149 4150 //! \name Local enumerations 4151 4152 enum SUBOPCODE_B 4153 { 4154 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 4155 }; 4156 4157 enum SUBOPCODE_A 4158 { 4159 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 4160 }; 4161 4162 enum MEDIA_COMMAND_OPCODE 4163 { 4164 MEDIA_COMMAND_OPCODE_MPEG2COMMON = 3, //!< No additional details 4165 }; 4166 4167 enum PIPELINE 4168 { 4169 PIPELINE_MFXMPEG2PICSTATE = 2, //!< No additional details 4170 }; 4171 4172 enum COMMAND_TYPE 4173 { 4174 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4175 }; 4176 4177 //! \brief SCAN_ORDER 4178 //! \details 4179 //! This field specifies the Inverse Scan method for the DCT-domain 4180 //! coefficients in the blocks of the current picture. 4181 enum SCAN_ORDER 4182 { 4183 SCAN_ORDER_UNNAMED0 = 0, //!< MPEG_ZIGZAG_SCAN 4184 SCAN_ORDER_UNNAMED1 = 1, //!< MPEG_ALTERNATE_VERTICAL_SCAN 4185 }; 4186 4187 //! \brief QUANTIZER_SCALE_TYPE 4188 //! \details 4189 //! This field specifies the quantizer scaling type. 4190 enum QUANTIZER_SCALE_TYPE 4191 { 4192 QUANTIZER_SCALE_TYPE_UNNAMED0 = 0, //!< MPEG_QSCALE_LINEAR 4193 QUANTIZER_SCALE_TYPE_UNNAMED1 = 1, //!< D MPEG_QSCALE_NONLINEAR esc 4194 }; 4195 4196 //! \brief MISMATCHCONTROLDISABLED 4197 //! \details 4198 //! These 2 bits flag disables mismatch control of the inverse 4199 //! transformation for some specific cases during reference reconstruction. 4200 enum MISMATCHCONTROLDISABLED 4201 { 4202 MISMATCHCONTROLDISABLED_UNNAMED0 = 0, //!< Mismatch control applies to all MBs 4203 MISMATCHCONTROLDISABLED_UNNAMED1 = 1, //!< Disable mismatch control to all intra MBs whose all AC-coefficients are zero. 4204 MISMATCHCONTROLDISABLED_UNNAMED2 = 2, //!< Disable mismatch control to all MBs whose all AC-coefficients are zero. 4205 MISMATCHCONTROLDISABLED_UNNAMED3 = 3, //!< Disable mismatch control to all MBs. 4206 }; 4207 4208 //! \brief PICTURE_CODING_TYPE 4209 //! \details 4210 //! This field identifies whether the picture is an intra-coded picture (I), 4211 //! predictive-coded picture (P) or bi-directionally predictive-coded 4212 //! picture (B). See ISO/IEC 13818-2 6.3.9 for details. 4213 enum PICTURE_CODING_TYPE 4214 { 4215 PICTURE_CODING_TYPE_MPEGIPICTURE = 1, //!< No additional details 4216 PICTURE_CODING_TYPE_10MPEGPPICTURE = 2, //!< No additional details 4217 PICTURE_CODING_TYPE_MPEGBPICTURE = 3, //!< No additional details 4218 }; 4219 4220 //! \brief LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4221 //! \details 4222 //! To support multiple slice picture and additional header/data insertion 4223 //! before and after an encoded slice.When this field is set to 0, bitstream 4224 //! pointer is only loaded once for the first slice of a frame. For 4225 //! subsequent slices in the frame, bitstream data are stitched together to 4226 //! form a single output data stream.When this field is set to 1, bitstream 4227 //! pointer is loaded for each slice of a frame. Basically bitstream data 4228 //! for different slices of a frame will be written to different memory 4229 //! locations. 4230 enum LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4231 { 4232 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED0 = 0, //!< Load BitStream Pointer only once for the first slice of a frame 4233 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED1 = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 4234 }; 4235 4236 //! \brief PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4237 //! \details 4238 //! This field is only applicable if the Concealment Motion Vectors are 4239 //! non-zero. 4240 //! It is only possible if "P/B Slice Concealment Mode" is set to "00" 4241 //! or "01" and left MB has non-zero motion vectors). 4242 enum PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4243 { 4244 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_PREDICTED = 0, //!< Motion Vectors use predicted values 4245 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_ZERO = 1, //!< Motion Vectors force to 0 4246 }; 4247 4248 //! \brief PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4249 //! \details 4250 //! This field is only applicable if the Concealment Motion Type is 4251 //! predicted to be Bi-directional. 4252 //! (It is only possible if "P/B Slice Concealment Mode" is set to "00" 4253 //! or "01" and left MB is a bi-directional MB). 4254 enum PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4255 { 4256 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BID = 0, //!< Keep Bi-direction Prediction 4257 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_FWD = 2, //!< Only use Forward Prediction (Backward MV is forced to invalid 4258 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BWD = 3, //!< Only use Backward Prediction (Forward MV is forced to invalid) 4259 }; 4260 4261 //! \brief PB_SLICE_CONCEALMENT_MODE_ 4262 //! \details 4263 //! This field controls how MPEG decoder handles MB concealment in P/B 4264 //! Slice. 4265 enum PB_SLICE_CONCEALMENT_MODE_ 4266 { 4267 PB_SLICE_CONCEALMENT_MODE_INTER = 0, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use forward reference (same polarity for field pic) with MV final values set to 0. 4268 PB_SLICE_CONCEALMENT_MODE_LEFT = 1, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data) 4269 PB_SLICE_CONCEALMENT_MODE_ZERO = 2, //!< Always use forward reference (same polarity for field pic) with MV final values set to 0 (Macroblock is concealed as INTER coded) 4270 PB_SLICE_CONCEALMENT_MODE_INTRA = 3, //!< Use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data 4271 }; 4272 4273 //! \brief I_SLICE_CONCEALMENT_MODE_ 4274 //! \details 4275 //! This field controls how MPEG decoder handles MB concealment in I Slice 4276 enum I_SLICE_CONCEALMENT_MODE_ 4277 { 4278 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< Using Coefficient values to handle MB concealment 4279 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< Using Motion Vectors to handle MB concealment 4280 }; 4281 4282 //! \brief SLICE_CONCEALMENT_DISABLE_BIT 4283 //! \details 4284 //! If VINunit detects the next slice starting position is either 4285 //! out-of-bound or smaller than or equal to the current slice starting 4286 //! position, VIN will set the current slice to be 1 MB and force VMDunit to 4287 //! do slice concealment on the next slice. 4288 //! This bit will disable this feature and the MB data from the next 4289 //! slice will be decoded from bitstream. 4290 enum SLICE_CONCEALMENT_DISABLE_BIT 4291 { 4292 SLICE_CONCEALMENT_DISABLE_BIT_ENABLE = 0, //!< VIN will force next slice to be concealment if detects slice boundary error 4293 SLICE_CONCEALMENT_DISABLE_BIT_DISABLE = 1, //!< VIN will not force next slice to be in concealment 4294 }; 4295 4296 //! \brief MINFRAMEWSIZE 4297 //! \details 4298 //! - Minimum Frame Size [15:0] (16-bit) (Encoder Only)Mininum Frame Size is 4299 //! specified to compensate for intel Rate ControlCurrently zero fill (no 4300 //! need to perform emulation byte insertion) is done only to the end of the 4301 //! CABAC_ZERO_WORD insertion (if any) at the last slice of a picture. Intel 4302 //! encoder parameter. The caller should always make sure 4303 //! that the value, represented by Mininum Frame Size, is always less than 4304 //! maximum frame size FrameBitRateMax (DWORD 10 bits 29:16). This field is 4305 //! reserved in Decode mode. 4306 enum MINFRAMEWSIZE 4307 { 4308 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 4309 }; 4310 4311 //! \brief INTRAMBMAXSIZEREPORTMASK 4312 //! \details 4313 //! This is a mask bit controlling if the condition of any intra MB in the 4314 //! frame exceeds IntraMBMaxSize. 4315 enum INTRAMBMAXSIZEREPORTMASK 4316 { 4317 INTRAMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4318 INTRAMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 4319 }; 4320 4321 //! \brief INTERMBMAXSIZEREPORTMASK 4322 //! \details 4323 //! This is a mask bit controlling if the condition of any inter MB in the 4324 //! frame exceeds InterMBMaxSize. 4325 enum INTERMBMAXSIZEREPORTMASK 4326 { 4327 INTERMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4328 INTERMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 4329 }; 4330 4331 //! \brief FRAMEBITRATEMAXREPORTMASK_ 4332 //! \details 4333 //! This is a mask bit controlling if the condition of frame level bit count 4334 //! exceeds FrameBitRateMax. 4335 enum FRAMEBITRATEMAXREPORTMASK_ 4336 { 4337 FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4338 FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 4339 }; 4340 4341 //! \brief FRAMEBITRATEMINREPORTMASK 4342 //! \details 4343 //! This is a mask bit controlling if the condition of frame level bit count 4344 //! is less than FrameBitRateMin. 4345 enum FRAMEBITRATEMINREPORTMASK 4346 { 4347 FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4348 FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 4349 }; 4350 4351 //! \brief MBRATECONTROLMASK 4352 //! \details 4353 //! MB Rate Control conformance maskThis field is ignored when 4354 //! MacroblockStatEnable is disabled or MB level Rate control flag for the 4355 //! current MB is disable in Macroblock Status Buffer. 4356 enum MBRATECONTROLMASK 4357 { 4358 MBRATECONTROLMASK_UNNAMED0 = 0, //!< Do not change QP values of inter macroblock with suggested QP values in Macroblock Status Buffer 4359 MBRATECONTROLMASK_UNNAMED1 = 1, //!< Apply RC QP delta for all macroblock 4360 }; 4361 4362 //! \brief MINFRAMEWSIZEUNITS 4363 //! \details 4364 //! This field is the Minimum Frame Size Units 4365 enum MINFRAMEWSIZEUNITS 4366 { 4367 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 4368 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 4369 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 4370 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 4371 }; 4372 4373 //! \brief INTERMBFORCECBPZEROCONTROLMASK 4374 //! \details 4375 //! Inter MB Force CBP ZERO mask. 4376 enum INTERMBFORCECBPZEROCONTROLMASK 4377 { 4378 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED0 = 0, //!< No effect 4379 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED1 = 1, //!< Zero out all A/C coefficients for the inter MB violating Inter Confirmance 4380 }; 4381 4382 //! \brief FRAMESIZECONTROLMASK 4383 //! \details 4384 //! Frame size conformance maskThis field is used when MacroblockStatEnable 4385 //! is set to 1. 4386 enum FRAMESIZECONTROLMASK 4387 { 4388 FRAMESIZECONTROLMASK_UNNAMED0 = 0, //!< Do not change Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control 4389 FRAMESIZECONTROLMASK_UNNAMED1 = 1, //!< Replace Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control values in MFC_IMAGE_STATUS control register. 4390 }; 4391 4392 //! \brief INTRAMBMAXSIZE 4393 //! \details 4394 //! This field, Intra MB Conformance Max size limit,indicates the allowed 4395 //! max bit count size for Intra MB 4396 enum INTRAMBMAXSIZE 4397 { 4398 INTRAMBMAXSIZE_UNNAMED_4095 = 4095, //!< No additional details 4399 }; 4400 4401 //! \brief INTERMBMAXSIZE 4402 //! \details 4403 //! This field, Inter MB Conformance Max size limit,indicates the allowed 4404 //! max bit count size for Inter MB 4405 enum INTERMBMAXSIZE 4406 { 4407 INTERMBMAXSIZE_UNNAMED_4095 = 4095, //!< No additional details 4408 }; 4409 4410 enum VSL_TOP_MB_TRANS8X8FLAG 4411 { 4412 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 4413 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 4414 }; 4415 4416 //! \brief SLICEDELTAQPMAX3 4417 //! \details 4418 //! This field is the Slice level delta QP for total 4419 //! bit-count above FrameBitRateMax - first 1/8 regionThis field is 4420 //! used to 4421 //! calculate the suggested slice QP into the MFC_IMAGE_STATUS control 4422 //! register when 4423 //! total bit count for the entire frame exceeds FrameBitRateMax but is 4424 //! within 1/8 4425 //! of FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range 4426 //! of 4427 //! (FrameBitRateMax, (FrameBitRateMax+ 4428 //! FrameBitRateMaxDelta>>3). 4429 enum SLICEDELTAQPMAX3 4430 { 4431 SLICEDELTAQPMAX3_DISABLE = 0, //!< No additional details 4432 SLICEDELTAQPMAX3_ENABLE = 1, //!< No additional details 4433 }; 4434 4435 //! \brief FRAMEBITRATEMINUNITMODE 4436 //! \details 4437 //! This field is the Frame Bitrate Minimum Limit 4438 //! Units.ValueNameDescriptionProject 4439 enum FRAMEBITRATEMINUNITMODE 4440 { 4441 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4442 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4443 }; 4444 4445 //! \brief FRAMEBITRATEMINUNIT 4446 //! \details 4447 //! This field is the Frame Bitrate Minimum Limit Units. 4448 enum FRAMEBITRATEMINUNIT 4449 { 4450 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 4451 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4452 }; 4453 4454 //! \brief FRAMEBITRATEMAXUNITMODE 4455 //! \details 4456 //! BitFiel This field is the Frame Bitrate Maximum Limit Units.dDesc 4457 enum FRAMEBITRATEMAXUNITMODE 4458 { 4459 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4460 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4461 }; 4462 4463 //! \brief FRAMEBITRATEMAXUNIT_ 4464 //! \details 4465 //! This field is the Frame Bitrate Maximum Limit Units. 4466 enum FRAMEBITRATEMAXUNIT_ 4467 { 4468 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 4469 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4470 }; 4471 4472 //! \brief FRAMEBITRATEMAXDELTA 4473 //! \details 4474 //! This field is used to select the slice delta QP when FrameBitRateMax Is 4475 //! exceeded. It shares the same FrameBitrateMaxUnit. 4476 //! The programmable range is either 0- 512KB or 4MBB in 4477 //! FrameBitrateMaxUnit of 128 Bytes or 16KB respectively. 4478 enum FRAMEBITRATEMAXDELTA 4479 { 4480 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 4481 }; 4482 4483 //! \name Initializations 4484 4485 //! \brief Explicit member initialization function 4486 MFX_MPEG2_PIC_STATE_CMD(); 4487 4488 static const size_t dwSize = 13; 4489 static const size_t byteSize = 52; 4490 }; 4491 4492 //! 4493 //! \brief MFD_MPEG2_BSD_OBJECT 4494 //! \details 4495 //! Different from AVC and VC1, MFD_MPEG2_BSD_OBJECT command is pipelinable. 4496 //! This is for performance purpose as in MPEG2 a slice is defined as a 4497 //! group of MBs of any size that must be within a macroblock row.Slice 4498 //! header parameters are passed in as inline data and the bitstream data 4499 //! for the slice is passed in as indirect data. Of the inline data, 4500 //! slice_horizontal_position and slice_vertical_position determines the 4501 //! location within the destination picture of the first macroblock in the 4502 //! slice. The content in this command is identical to that in the 4503 //! MEDIA_OBJECT command in VLD mode described in the Media Chapter. 4504 //! 4505 struct MFD_MPEG2_BSD_OBJECT_CMD 4506 { 4507 union 4508 { 4509 //!< DWORD 0 4510 struct 4511 { 4512 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4513 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4514 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 4515 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 4516 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 4517 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4518 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4519 }; 4520 uint32_t Value; 4521 } DW0; 4522 union 4523 { 4524 //!< DWORD 1 4525 struct 4526 { 4527 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 4528 }; 4529 uint32_t Value; 4530 } DW1; 4531 union 4532 { 4533 //!< DWORD 2 4534 struct 4535 { 4536 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 4537 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4538 }; 4539 uint32_t Value; 4540 } DW2; 4541 union 4542 { 4543 //!< DWORD 3 4544 struct 4545 { 4546 uint32_t FirstMacroblockBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< First Macroblock Bit Offset 4547 uint32_t IsLastMb : __CODEGEN_BITFIELD( 3, 3) ; //!< IS_LAST_MB 4548 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 4549 uint32_t LastPicSlice : __CODEGEN_BITFIELD( 5, 5) ; //!< LAST_PIC_SLICE 4550 uint32_t SliceConcealmentTypeBit : __CODEGEN_BITFIELD( 6, 6) ; //!< SLICE_CONCEALMENT_TYPE_BIT 4551 uint32_t SliceConcealmentOverrideBit : __CODEGEN_BITFIELD( 7, 7) ; //!< SLICE_CONCEALMENT_OVERRIDE_BIT 4552 uint32_t MacroblockCount : __CODEGEN_BITFIELD( 8, 15) ; //!< Macroblock Count 4553 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Vertical Position 4554 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(24, 31) ; //!< Slice Horizontal Position 4555 }; 4556 uint32_t Value; 4557 } DW3; 4558 union 4559 { 4560 //!< DWORD 4 4561 struct 4562 { 4563 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD( 0, 7) ; //!< Next Slice Horizontal Position 4564 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD( 8, 16) ; //!< Next Slice Vertical Position 4565 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 23) ; //!< Reserved 4566 uint32_t QuantizerScaleCode : __CODEGEN_BITFIELD(24, 28) ; //!< Quantizer Scale Code 4567 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4568 }; 4569 uint32_t Value; 4570 } DW4; 4571 4572 //! \name Local enumerations 4573 4574 enum SUBOPCODE_B 4575 { 4576 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 4577 }; 4578 4579 enum SUBOPCODE_A 4580 { 4581 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 4582 }; 4583 4584 enum MEDIA_COMMAND_OPCODE 4585 { 4586 MEDIA_COMMAND_OPCODE_MPEG2DEC = 3, //!< No additional details 4587 }; 4588 4589 enum PIPELINE 4590 { 4591 PIPELINE_MFDMPEG2BSDOBJECT = 2, //!< No additional details 4592 }; 4593 4594 enum COMMAND_TYPE 4595 { 4596 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4597 }; 4598 4599 enum IS_LAST_MB 4600 { 4601 IS_LAST_MB_UNNAMED0 = 0, //!< The current MB is not the last MB in the current Slice 4602 IS_LAST_MB_UNNAMED1 = 1, //!< The current MB is the last MB in the current Slice 4603 }; 4604 4605 //! \brief LAST_PIC_SLICE 4606 //! \details 4607 //! This bit is added to support error concealment at the end of a picture. 4608 enum LAST_PIC_SLICE 4609 { 4610 LAST_PIC_SLICE_UNNAMED0 = 0, //!< The current Slice is not the last Slice of current picture 4611 LAST_PIC_SLICE_UNNAMED1 = 1, //!< The current Slice is the last Slice of the entire picture 4612 }; 4613 4614 //! \brief SLICE_CONCEALMENT_TYPE_BIT 4615 //! \details 4616 //! This bit can be forced by driver ("Slice Concealment Override Bit") or 4617 //! set by VINunit depending on slice boundary errors. 4618 enum SLICE_CONCEALMENT_TYPE_BIT 4619 { 4620 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED0 = 0, //!< VMD will decode MBs from the bitstream until the bitstream is run-out. Then VMD will conceal the remaining MBs. 4621 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED1 = 1, //!< VMD will conceal all MBs of the slice regardless of bitstream. (If driver does not force the value of this bit, VIN will set this bit depending on slice boundary error. If the next slice position of the current slice is out-of-bound or the same or earlier than the current slice start position, VIN will set this bit for the next slice) 4622 }; 4623 4624 //! \brief SLICE_CONCEALMENT_OVERRIDE_BIT 4625 //! \details 4626 //! This bit forces hardware to handle the current slice in Conceal or 4627 //! Deocde Mode. If this bit is set to one, VIN will force the current 4628 //! slice to do concealment or to decode from bitstream regardless if the 4629 //! slice boundary has errors or not. 4630 enum SLICE_CONCEALMENT_OVERRIDE_BIT 4631 { 4632 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED0 = 0, //!< Driver must program "Slice Concealment Type" to '0'. VIN will set "Slice Concealment Type" depending if the slice boundary has error or not 4633 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED1 = 1, //!< VIN will use driver-provided "Slice Concealment Type" regardless of valid slice boundary 4634 }; 4635 4636 //! \name Initializations 4637 4638 //! \brief Explicit member initialization function 4639 MFD_MPEG2_BSD_OBJECT_CMD(); 4640 4641 static const size_t dwSize = 5; 4642 static const size_t byteSize = 20; 4643 }; 4644 4645 //! 4646 //! \brief MFD_IT_OBJECT_MPEG2_INLINE_DATA 4647 //! \details 4648 //! The content in this command is similar to that in the MEDIA_OBJECT 4649 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4650 //! command corresponds to the processing of one macroblock. Macroblock 4651 //! parameters are passed in as inline data and the non-zero DCT coefficient 4652 //! data for the macroblock is passed in as indirect data. Inline data 4653 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4654 //! 4655 struct MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD 4656 { 4657 union 4658 { 4659 //!< DWORD 0 4660 struct 4661 { 4662 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 4663 uint32_t Lastmbinrow : __CODEGEN_BITFIELD( 3, 3) ; //!< LastMBInRow 4664 uint32_t Reserved4 : __CODEGEN_BITFIELD( 4, 5) ; //!< Reserved 4665 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD( 6, 11) ; //!< Coded Block Pattern 4666 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4667 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16) ; //!< MACROBLOCK_INTRA_TYPE 4668 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17) ; //!< MACROBLOCK_MOTION_FORWARD 4669 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18) ; //!< MACROBLOCK_MOTION_BACKWARD 4670 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 20) ; //!< Reserved 4671 uint32_t DctType : __CODEGEN_BITFIELD(21, 21) ; //!< DCT_TYPE 4672 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 4673 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25) ; //!< Motion Type 4674 uint32_t Reserved26 : __CODEGEN_BITFIELD(26, 27) ; //!< Reserved 4675 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31) ; //!< MOTION_VERTICAL_FIELD_SELECT 4676 }; 4677 uint32_t Value; 4678 } DW0; 4679 union 4680 { 4681 //!< DWORD 1 4682 struct 4683 { 4684 uint32_t Horzorigin : __CODEGEN_BITFIELD( 0, 7) ; //!< HorzOrigin 4685 uint32_t Vertorigin : __CODEGEN_BITFIELD( 8, 15) ; //!< VertOrigin 4686 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4687 }; 4688 uint32_t Value; 4689 } DW1; 4690 union 4691 { 4692 //!< DWORD 2 4693 struct 4694 { 4695 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 0, Forward, Horizontal Component 4696 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 0, Forward, Vertical Component 4697 }; 4698 uint32_t Value; 4699 } DW2; 4700 union 4701 { 4702 //!< DWORD 3 4703 struct 4704 { 4705 uint32_t MotionVectorsField0BackwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 0, Backward, Horizontal Component 4706 uint32_t MotionVectorsField0BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 0, Backward, Vertical Component 4707 }; 4708 uint32_t Value; 4709 } DW3; 4710 union 4711 { 4712 //!< DWORD 4 4713 struct 4714 { 4715 uint32_t MotionVectorsField1ForwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 1, Forward, Horizontal Component 4716 uint32_t MotionVectorsField1ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 1, Forward, Vertical Component 4717 }; 4718 uint32_t Value; 4719 } DW4; 4720 union 4721 { 4722 //!< DWORD 5 4723 struct 4724 { 4725 uint32_t MotionVectorsField1BackwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 1, Backward, Horizontal Component 4726 uint32_t MotionVectorsField1BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 1, Backward, Vertical Component 4727 }; 4728 uint32_t Value; 4729 } DW5; 4730 4731 //! \name Local enumerations 4732 4733 //! \brief MACROBLOCK_INTRA_TYPE 4734 //! \details 4735 //! This field specifies if the current macroblock is intra-coded. When set, 4736 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 4737 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 4738 enum MACROBLOCK_INTRA_TYPE 4739 { 4740 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 4741 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 4742 }; 4743 4744 //! \brief MACROBLOCK_MOTION_FORWARD 4745 //! \details 4746 //! This field specifies if the forward motion vector is active. See ISO/IEC 4747 //! 13818-2 Tables B-2 through B-4. 4748 enum MACROBLOCK_MOTION_FORWARD 4749 { 4750 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 4751 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTORS = 1, //!< No additional details 4752 }; 4753 4754 //! \brief MACROBLOCK_MOTION_BACKWARD 4755 //! \details 4756 //! This field specifies if the backward motion vector is active. See 4757 //! ISO/IEC 13818-2 Tables B-2 through B-4. 4758 enum MACROBLOCK_MOTION_BACKWARD 4759 { 4760 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 4761 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTORS = 1, //!< No additional details 4762 }; 4763 4764 //! \brief DCT_TYPE 4765 //! \details 4766 //! This field specifies the DCT type of the current macroblock. The kernel 4767 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 4768 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 4769 //! (no coded blocks present). 4770 enum DCT_TYPE 4771 { 4772 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 4773 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 4774 }; 4775 4776 //! \brief MOTION_VERTICAL_FIELD_SELECT 4777 //! \details 4778 //! A bit-wise representation of a long [2][2] array as defined in 4779 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also #167;7.6.4). 4780 //! <table> 4781 //! <thead> 4782 //! 4783 //! <tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 4784 //! Index</td></tr> 4785 //! </thead> 4786 //! <tbody> 4787 //! <tr><td>28</td><td>0</td><td>0</td><td>0</td></tr> 4788 //! <tr><td>29</td><td>0</td><td>1</td><td>1</td></tr> 4789 //! <tr><td>30</td><td>1</td><td>0</td><td>2</td></tr> 4790 //! <tr><td>31</td><td>1</td><td>1</td><td>3</td></tr> 4791 //! </tbody> 4792 //! </table> 4793 enum MOTION_VERTICAL_FIELD_SELECT 4794 { 4795 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field. 4796 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 4797 }; 4798 4799 //! \name Initializations 4800 4801 //! \brief Explicit member initialization function 4802 MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD(); 4803 4804 static const size_t dwSize = 6; 4805 static const size_t byteSize = 24; 4806 }; 4807 4808 //! 4809 //! \brief MFD_IT_OBJECT_VC1_INLINE_DATA 4810 //! \details 4811 //! The content in this command is similar to that in the MEDIA_OBJECT 4812 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4813 //! command corresponds to the processing of one macroblock. Macroblock 4814 //! parameters are passed in as inline data and the non-zero DCT coefficient 4815 //! data for the macroblock is passed in as indirect data. Inline data 4816 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4817 //! 4818 struct MFD_IT_OBJECT_VC1_INLINE_DATA_CMD 4819 { 4820 union 4821 { 4822 //!< DWORD 0 4823 struct 4824 { 4825 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 4826 uint32_t Lastmbinrow : __CODEGEN_BITFIELD( 3, 3) ; //!< LastMBInRow 4827 uint32_t LastRowFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< Last Row Flag 4828 uint32_t ChromaIntraFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< Chroma Intra Flag 4829 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD( 6, 11) ; //!< Coded Block Pattern 4830 uint32_t LumaIntra8X8Flag : __CODEGEN_BITFIELD(12, 15) ; //!< Luma Intra 8x8 Flag 4831 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16) ; //!< MACROBLOCK_INTRA_TYPE 4832 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17) ; //!< MACROBLOCK_MOTION_FORWARD 4833 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18) ; //!< MACROBLOCK_MOTION_BACKWARD 4834 uint32_t Motion4Mv : __CODEGEN_BITFIELD(19, 19) ; //!< MOTION4MV 4835 uint32_t Overlaptransform : __CODEGEN_BITFIELD(20, 20) ; //!< OVERLAPTRANSFORM 4836 uint32_t DctType : __CODEGEN_BITFIELD(21, 21) ; //!< DCT_TYPE 4837 uint32_t Mvswitch : __CODEGEN_BITFIELD(22, 22) ; //!< MvSwitch 4838 uint32_t Reserved23 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 4839 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25) ; //!< Motion Type 4840 uint32_t Mvfieldselectchroma : __CODEGEN_BITFIELD(26, 26) ; //!< MvFieldSelectChroma 4841 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 27) ; //!< Reserved 4842 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31) ; //!< MOTION_VERTICAL_FIELD_SELECT 4843 }; 4844 uint32_t Value; 4845 } DW0; 4846 union 4847 { 4848 //!< DWORD 1 4849 struct 4850 { 4851 uint32_t Horzorigin : __CODEGEN_BITFIELD( 0, 7) ; //!< HorzOrigin 4852 uint32_t Vertorigin : __CODEGEN_BITFIELD( 8, 15) ; //!< VertOrigin 4853 uint32_t Osedgemaskluma : __CODEGEN_BITFIELD(16, 23) ; //!< OSEdgeMaskLuma 4854 uint32_t Osedgemaskchroma : __CODEGEN_BITFIELD(24, 25) ; //!< OSEdgeMaskChroma 4855 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 4856 }; 4857 uint32_t Value; 4858 } DW1; 4859 union 4860 { 4861 //!< DWORD 2 4862 struct 4863 { 4864 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 0, Forward, Horizontal Component 4865 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 0, Forward, Vertical Component 4866 }; 4867 uint32_t Value; 4868 } DW2; 4869 union 4870 { 4871 //!< DWORD 3 4872 struct 4873 { 4874 uint32_t Motionvector1 ; //!< MotionVector1 4875 }; 4876 uint32_t Value; 4877 } DW3; 4878 union 4879 { 4880 //!< DWORD 4 4881 struct 4882 { 4883 uint32_t Motionvector2 ; //!< MotionVector2 4884 }; 4885 uint32_t Value; 4886 } DW4; 4887 union 4888 { 4889 //!< DWORD 5 4890 struct 4891 { 4892 uint32_t Motionvector3 ; //!< MotionVector3 4893 }; 4894 uint32_t Value; 4895 } DW5; 4896 union 4897 { 4898 //!< DWORD 6 4899 struct 4900 { 4901 uint32_t Motionvectorchroma ; //!< MotionVectorChroma 4902 }; 4903 uint32_t Value; 4904 } DW6; 4905 union 4906 { 4907 //!< DWORD 7 4908 struct 4909 { 4910 uint32_t SubblockCodeForY0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Subblock Code for Y0 4911 uint32_t SubblockCodeForY1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Subblock Code for Y1 4912 uint32_t SubblockCodeForY2 : __CODEGEN_BITFIELD(16, 23) ; //!< Subblock Code for Y2 4913 uint32_t SubblockCodeForY3 : __CODEGEN_BITFIELD(24, 31) ; //!< Subblock Code for Y3 4914 }; 4915 uint32_t Value; 4916 } DW7; 4917 union 4918 { 4919 //!< DWORD 8 4920 struct 4921 { 4922 uint32_t SubblockCodeForCb : __CODEGEN_BITFIELD( 0, 7) ; //!< Subblock Code for Cb 4923 uint32_t SubblockCodeForCr : __CODEGEN_BITFIELD( 8, 15) ; //!< Subblock Code for Cr 4924 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4925 }; 4926 uint32_t Value; 4927 } DW8; 4928 union 4929 { 4930 //!< DWORD 9 4931 struct 4932 { 4933 uint32_t IldbControlDataForBlockY0 : __CODEGEN_BITFIELD( 0, 7) ; //!< ILDB control data for block Y0 4934 uint32_t IldbControlDataForBlockY1 : __CODEGEN_BITFIELD( 8, 15) ; //!< ILDB control data for block Y1 4935 uint32_t IldbControlDataForBlockY2 : __CODEGEN_BITFIELD(16, 23) ; //!< ILDB control data for block Y2 4936 uint32_t IldbControlDataForBlockY3 : __CODEGEN_BITFIELD(24, 31) ; //!< ILDB control data for block Y3 4937 }; 4938 uint32_t Value; 4939 } DW9; 4940 union 4941 { 4942 //!< DWORD 10 4943 struct 4944 { 4945 uint32_t IldbControlDataForCbBlock : __CODEGEN_BITFIELD( 0, 7) ; //!< ILDB control data for Cb block 4946 uint32_t IldbControlDataForCrBlock : __CODEGEN_BITFIELD( 8, 15) ; //!< ILDB control data for Cr block 4947 uint32_t Reserved336 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4948 }; 4949 uint32_t Value; 4950 } DW10; 4951 4952 //! \name Local enumerations 4953 4954 //! \brief MACROBLOCK_INTRA_TYPE 4955 //! \details 4956 //! This field specifies if the current macroblock is intra-coded. When set, 4957 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 4958 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 4959 enum MACROBLOCK_INTRA_TYPE 4960 { 4961 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 4962 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 4963 }; 4964 4965 //! \brief MACROBLOCK_MOTION_FORWARD 4966 //! \details 4967 //! This field specifies if the forward motion vector is active. See ISO/IEC 4968 //! 13818-2 Tables B-2 through B-4. 4969 enum MACROBLOCK_MOTION_FORWARD 4970 { 4971 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 4972 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTORS = 1, //!< No additional details 4973 }; 4974 4975 //! \brief MACROBLOCK_MOTION_BACKWARD 4976 //! \details 4977 //! This field specifies if the backward motion vector is active. See 4978 //! ISO/IEC 13818-2 Tables B-2 through B-4. 4979 enum MACROBLOCK_MOTION_BACKWARD 4980 { 4981 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 4982 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTORS = 1, //!< No additional details 4983 }; 4984 4985 enum MOTION4MV 4986 { 4987 MOTION4MV_1MV_MODE = 0, //!< No additional details 4988 MOTION4MV_4MV_MODE = 1, //!< No additional details 4989 }; 4990 4991 //! \brief OVERLAPTRANSFORM 4992 //! \details 4993 //! Was Overlap Transform - H261 Loop Filter 4994 enum OVERLAPTRANSFORM 4995 { 4996 OVERLAPTRANSFORM_NOOVERLAPSMOOTHINGFILTER = 0, //!< This field indicates whether overlap smoothing filter should be performed on I-block boundaries. 4997 OVERLAPTRANSFORM_OVERLAPSMOOTHINGFILTERPERFORMED = 1, //!< Macroblock is field DCT coded 4998 }; 4999 5000 //! \brief DCT_TYPE 5001 //! \details 5002 //! This field specifies the DCT type of the current macroblock. The kernel 5003 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 5004 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 5005 //! (no coded blocks present). 5006 enum DCT_TYPE 5007 { 5008 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 5009 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 5010 }; 5011 5012 //! \brief MOTION_VERTICAL_FIELD_SELECT 5013 //! \details 5014 //! A bit-wise representation of a long [2][2] array as defined in 5015 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also #167;7.6.4). 5016 //! <table> 5017 //! <thead> 5018 //! 5019 //! <tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 5020 //! Index</td></tr> 5021 //! </thead> 5022 //! <tbody> 5023 //! <tr><td>28</td><td>0</td><td>0</td><td>0</td></tr> 5024 //! <tr><td>29</td><td>0</td><td>1</td><td>1</td></tr> 5025 //! <tr><td>30</td><td>1</td><td>0</td><td>2</td></tr> 5026 //! <tr><td>31</td><td>1</td><td>1</td><td>3</td></tr> 5027 //! </tbody> 5028 //! </table> 5029 enum MOTION_VERTICAL_FIELD_SELECT 5030 { 5031 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field. 5032 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 5033 }; 5034 5035 //! \name Initializations 5036 5037 //! \brief Explicit member initialization function 5038 MFD_IT_OBJECT_VC1_INLINE_DATA_CMD(); 5039 5040 static const size_t dwSize = 11; 5041 static const size_t byteSize = 44; 5042 }; 5043 5044 //! 5045 //! \brief MFD_IT_OBJECT 5046 //! \details 5047 //! All weight mode (default and implicit) are mapped to explicit mode. But 5048 //! the weights come in either as explicit or implicit. 5049 //! 5050 struct MFD_IT_OBJECT_CMD 5051 { 5052 union 5053 { 5054 //!< DWORD 0 5055 struct 5056 { 5057 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5058 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5059 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5060 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5061 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5062 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5063 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5064 }; 5065 uint32_t Value; 5066 } DW0; 5067 union 5068 { 5069 //!< DWORD 1 5070 struct 5071 { 5072 uint32_t IndirectItMvDataLength : __CODEGEN_BITFIELD( 0, 9) ; //!< Indirect IT-MV Data Length 5073 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 5074 }; 5075 uint32_t Value; 5076 } DW1; 5077 union 5078 { 5079 //!< DWORD 2 5080 struct 5081 { 5082 uint32_t IndirectItMvDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-MV Data Start Address Offset 5083 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5084 }; 5085 uint32_t Value; 5086 } DW2; 5087 union 5088 { 5089 //!< DWORD 3 5090 struct 5091 { 5092 uint32_t IndirectItCoeffDataLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Indirect IT-COEFF Data Length 5093 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 5094 }; 5095 uint32_t Value; 5096 } DW3; 5097 union 5098 { 5099 //!< DWORD 4 5100 struct 5101 { 5102 uint32_t IndirectItCoeffDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-COEFF Data Start Address Offset 5103 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5104 }; 5105 uint32_t Value; 5106 } DW4; 5107 union 5108 { 5109 //!< DWORD 5 5110 struct 5111 { 5112 uint32_t IndirectItDblkControlDataLength : __CODEGEN_BITFIELD( 0, 5) ; //!< Indirect IT-DBLK Control Data Length 5113 uint32_t Reserved166 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 5114 }; 5115 uint32_t Value; 5116 } DW5; 5117 union 5118 { 5119 //!< DWORD 6 5120 struct 5121 { 5122 uint32_t IndirectItDblkControlDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-DBLK Control Data Start Address Offset 5123 uint32_t Reserved221 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5124 }; 5125 uint32_t Value; 5126 } DW6; 5127 5128 //! \name Local enumerations 5129 5130 enum SUBOPCODE_B 5131 { 5132 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 5133 }; 5134 5135 enum SUBOPCODE_A 5136 { 5137 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5138 }; 5139 5140 enum MEDIA_COMMAND_OPCODE 5141 { 5142 MEDIA_COMMAND_OPCODE_MFXCOMMONDEC = 0, //!< No additional details 5143 }; 5144 5145 enum PIPELINE 5146 { 5147 PIPELINE_MFDITOBJECT = 2, //!< No additional details 5148 }; 5149 5150 enum COMMAND_TYPE 5151 { 5152 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5153 }; 5154 5155 //! \name Initializations 5156 5157 //! \brief Explicit member initialization function 5158 MFD_IT_OBJECT_CMD(); 5159 5160 static const size_t dwSize = 7; 5161 static const size_t byteSize = 28; 5162 }; 5163 5164 //! 5165 //! \brief MFC_MPEG2_SLICEGROUP_STATE 5166 //! \details 5167 //! This is a slice group level command and can be issued multiple times 5168 //! within a picture that is comprised of multiple slice groups. The same 5169 //! command is used for AVC encoder (PAK mode) and decoder (VLD and IT 5170 //! modes). 5171 //! 5172 struct MFC_MPEG2_SLICEGROUP_STATE_CMD 5173 { 5174 union 5175 { 5176 //!< DWORD 0 5177 struct 5178 { 5179 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5180 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5181 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5182 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5183 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5184 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5185 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5186 }; 5187 uint32_t Value; 5188 } DW0; 5189 union 5190 { 5191 //!< DWORD 1 5192 struct 5193 { 5194 uint32_t Streamid10EncoderOnly : __CODEGEN_BITFIELD( 0, 1) ; //!< StreamID[1:0] (Encoder-only) 5195 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 5196 uint32_t Sliceid30EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< SliceID[3:0] (Encoder-only) 5197 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 5198 uint32_t Intrasliceflag : __CODEGEN_BITFIELD(12, 12) ; //!< IntraSliceFlag 5199 uint32_t Intraslice : __CODEGEN_BITFIELD(13, 13) ; //!< IntraSlice 5200 uint32_t Firstslicehdrdisabled : __CODEGEN_BITFIELD(14, 14) ; //!< FirstSliceHdrDisabled 5201 uint32_t TailpresentflagTailInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(15, 15) ; //!< TAILPRESENTFLAG__TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5202 uint32_t SlicedataPresentflagSlicedataInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(16, 16) ; //!< SLICEDATA_PRESENTFLAG__SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5203 uint32_t HeaderpresentflagHeaderInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(17, 17) ; //!< HEADERPRESENTFLAG__HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5204 uint32_t BitstreamoutputflagCompressedBitstreamOutputDisableFlagEncoderOnly : __CODEGEN_BITFIELD(18, 18) ; //!< BITSTREAMOUTPUTFLAG__COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5205 uint32_t Islastslicegrp : __CODEGEN_BITFIELD(19, 19) ; //!< IsLastSliceGrp 5206 uint32_t SkipconvdisabledMbTypeSkipConversionDisableEncoderOnly : __CODEGEN_BITFIELD(20, 20) ; //!< SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5207 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 5208 uint32_t RatectrlpanictypeRcPanicTypeEncoderOnly : __CODEGEN_BITFIELD(22, 22) ; //!< RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5209 uint32_t RatectrlpanicflagRcPanicEnableEncoderOnly : __CODEGEN_BITFIELD(23, 23) ; //!< RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5210 uint32_t MbratectrlparamRcStableToleranceEncoderOnly : __CODEGEN_BITFIELD(24, 27) ; //!< MbRateCtrlParam- RC Stable Tolerance (Encoder-only) 5211 uint32_t MbratectrlmodeRcTriggleModeEncoderOnly : __CODEGEN_BITFIELD(28, 29) ; //!< MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5212 uint32_t MbratectrlresetResetratecontrolcounterEncoderOnly : __CODEGEN_BITFIELD(30, 30) ; //!< MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5213 uint32_t MbratectrlflagRatecontrolcounterenableEncoderOnly : __CODEGEN_BITFIELD(31, 31) ; //!< MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5214 }; 5215 uint32_t Value; 5216 } DW1; 5217 union 5218 { 5219 //!< DWORD 2 5220 struct 5221 { 5222 uint32_t FirstmbxcntAlsoCurrstarthorzpos : __CODEGEN_BITFIELD( 0, 7) ; //!< FirstMbXcnt - also CurrStartHorzPos 5223 uint32_t FirstmbycntAlsoCurrstartvertpos : __CODEGEN_BITFIELD( 8, 15) ; //!< FirstMbYcnt - also CurrStartVertPos 5224 uint32_t NextsgmbxcntAlsoNextstarthorzpos : __CODEGEN_BITFIELD(16, 23) ; //!< NextSgMbXcnt - also NextStartHorzPos 5225 uint32_t NextsgmbycntAlsoNextstartvertpos : __CODEGEN_BITFIELD(24, 31) ; //!< NextSgMbYcnt - also NextStartVertPos 5226 }; 5227 uint32_t Value; 5228 } DW2; 5229 union 5230 { 5231 //!< DWORD 3 5232 struct 5233 { 5234 uint32_t Slicegroupqp : __CODEGEN_BITFIELD( 0, 5) ; //!< SliceGroupQp 5235 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5236 uint32_t Slicegroupskip : __CODEGEN_BITFIELD( 8, 8) ; //!< SliceGroupSkip 5237 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 5238 }; 5239 uint32_t Value; 5240 } DW3; 5241 union 5242 { 5243 //!< DWORD 4 5244 struct 5245 { 5246 uint32_t BitstreamoffsetIndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD( 0, 28) ; //!< BitstreamOffset - Indirect PAK-BSE Data Start Address (Write) 5247 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5248 }; 5249 uint32_t Value; 5250 } DW4; 5251 union 5252 { 5253 //!< DWORD 5 5254 struct 5255 { 5256 uint32_t GrowparamGrowInitEncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< GrowParam - Grow Init (Encoder-only) 5257 uint32_t GrowparamGrowResistanceEncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< GrowParam - Grow Resistance (Encoder-only) 5258 uint32_t ShrinkaramShrinkInitEncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< Shrinkaram - Shrink Init (Encoder-only) 5259 uint32_t ShrinkparamShrinkResistanceEncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< ShrinkParam - Shrink Resistance (Encoder-only) 5260 uint32_t MaxqpposmodifierMagnitudeOfQpMaxPositiveModifierEncoderOnly : __CODEGEN_BITFIELD(16, 23) ; //!< MaxQpPosModifier - Magnitude of QP Max Positive Modifier (Encoder-only) 5261 uint32_t MaxqpnegmodifierMagnitudeOfQpMaxNegativeModifierEncoderOnly : __CODEGEN_BITFIELD(24, 31) ; //!< MaxQpNegModifier - Magnitude of QP Max Negative Modifier (Encoder-only) 5262 }; 5263 uint32_t Value; 5264 } DW5; 5265 union 5266 { 5267 //!< DWORD 6 5268 struct 5269 { 5270 uint32_t CorrectpointsCorrect1EncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< CorrectPoints - Correct 1 (Encoder-only) 5271 uint32_t CorrectpointsCorrect2EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< CorrectPoints - Correct 2 (Encoder-only) 5272 uint32_t CorrectpointsCorrect3EncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< CorrectPoints - Correct 3 (Encoder-only) 5273 uint32_t CorrectpointsCorrect4EncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< CorrectPoints - Correct 4 (Encoder-only) 5274 uint32_t CorrectpointsCorrect5EncoderOnly : __CODEGEN_BITFIELD(16, 19) ; //!< CorrectPoints - Correct 5 (Encoder-only) 5275 uint32_t CorrectpointsCorrect6EncoderOnly : __CODEGEN_BITFIELD(20, 23) ; //!< CorrectPoints - Correct 6 (Encoder-only) 5276 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 5277 }; 5278 uint32_t Value; 5279 } DW6; 5280 union 5281 { 5282 //!< DWORD 7 5283 struct 5284 { 5285 uint32_t Cv0ClampValue0EncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 (Encoder-only) 5286 uint32_t Cv1ClampValue1EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 - Clamp Value 1 (Encoder-only) 5287 uint32_t Cv2ClampValue2EncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 - Clamp Value 2 (Encoder-only) 5288 uint32_t Cv3ClampValue3EncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 - Clamp Value 3 (Encoder-only) 5289 uint32_t Cv4ClampValue4EncoderOnly : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 - Clamp Value 4 (Encoder-only) 5290 uint32_t Cv5ClampValue5EncoderOnly : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 - Clamp Value 5 (Encoder-only) 5291 uint32_t Cv6ClampValue6EncoderOnly : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 - Clamp Value 6 (Encoder-only) 5292 uint32_t Cv7ClampValue7EncoderOnly : __CODEGEN_BITFIELD(28, 31) ; //!< CV7 - Clamp Value 7 (Encoder-only) 5293 }; 5294 uint32_t Value; 5295 } DW7; 5296 5297 //! \name Local enumerations 5298 5299 enum SUBOPCODE_B 5300 { 5301 SUBOPCODE_B_MEDIA = 3, //!< No additional details 5302 }; 5303 5304 enum SUBOPCODE_A 5305 { 5306 SUBOPCODE_A_MEDIA = 2, //!< No additional details 5307 }; 5308 5309 enum MEDIA_COMMAND_OPCODE 5310 { 5311 MEDIA_COMMAND_OPCODE_MPEG2 = 3, //!< No additional details 5312 }; 5313 5314 enum PIPELINE 5315 { 5316 PIPELINE_MFXMPEG2SLICEGROUPSTATE = 2, //!< No additional details 5317 }; 5318 5319 enum COMMAND_TYPE 5320 { 5321 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5322 }; 5323 5324 enum TAILPRESENTFLAG__TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5325 { 5326 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED0 = 0, //!< no tail insertion into the output bitstream buffer, after the current slice encoded bits 5327 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED1 = 1, //!< tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 5328 }; 5329 5330 enum SLICEDATA_PRESENTFLAG__SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5331 { 5332 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no Slice Data insertion into the output bitstream buffer 5333 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< Slice Data insertion into the output bitstream buffer is present. 5334 }; 5335 5336 enum HEADERPRESENTFLAG__HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5337 { 5338 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no header insertion into the output bitstream buffer, in front of the current slice encoded bits 5339 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 5340 }; 5341 5342 enum BITSTREAMOUTPUTFLAG__COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5343 { 5344 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_ENABLE = 0, //!< enable the writing of the output compressed bitstream 5345 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_DISABLE = 1, //!< disable the writing of the output compressed bitstream 5346 }; 5347 5348 //! \brief SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5349 //! \details 5350 //! This field is only valid for a P or B slice. It must be zero for other 5351 //! slice types. Rules are provided in Section 2.3.3.1.6 5352 enum SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5353 { 5354 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_ENABLE = 0, //!< Enable skip type conversion 5355 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_DISABLE = 1, //!< Disable skip type conversion 5356 }; 5357 5358 //! \brief RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5359 //! \details 5360 //! This field selects between two RC Panic methods. If it is set to 0, in 5361 //! panic mode, the macroblock QP is maxed out, setting to requested QP + 5362 //! QP_max_pos_mod. If it is set to 1, for an intra macroblock, AC CBPs are 5363 //! set to zero (note that DC CBPs are not modified). For inter macroblocks, 5364 //! AC and DC CBPs are forced to zero. 5365 enum RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5366 { 5367 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED0 = 0, //!< QP Panic 5368 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED1 = 1, //!< CBP Panic 5369 }; 5370 5371 //! \brief RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5372 //! \details 5373 //! If this field is set to 1, RC enters panic mode 5374 //! when sum_act > sum_max. RC Panic Type field controls what type 5375 //! of panic 5376 //! behavior is invoked. 5377 enum RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5378 { 5379 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5380 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5381 }; 5382 5383 enum MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5384 { 5385 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED0 = 0, //!< Always Rate Control, whereas RC becomes activeif sum_act > sum_target or sum_act < sum_target 5386 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED1 = 1, //!< Gentle Rate Control, whereas RC becomes activeif sum_act > upper_midpt or sum_act < lower_midpt 5387 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED2 = 2, //!< Loose Rate Control, whereas RC becomes activeif sum_act > sum_max or sum_act < sum_min 5388 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED3 = 3, //!< Reserved 5389 }; 5390 5391 //! \brief MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5392 //! \details 5393 //! To reset the bit allocation accumulation counter to 0 to restart the 5394 //! rate control. 5395 enum MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5396 { 5397 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_DISABLE = 0, //!< Not reset 5398 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_ENABLE = 1, //!< reset 5399 }; 5400 5401 //! \brief MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5402 //! \details 5403 //! To enable the accumulation of bit allocation for rate controlThis field 5404 //! enables hardware Rate Control logic. The rest of the RC control fields 5405 //! are only valid when this field is set to 1. Otherwise, hardware ignores 5406 //! these fields.Note: To reset MB level rate control (QRC), we need to set 5407 //! both bits MbRateCtrlFlag and MbRateCtrlReset to 1 in the new slice 5408 enum MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5409 { 5410 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5411 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5412 }; 5413 5414 //! \name Initializations 5415 5416 //! \brief Explicit member initialization function 5417 MFC_MPEG2_SLICEGROUP_STATE_CMD(); 5418 5419 static const size_t dwSize = 8; 5420 static const size_t byteSize = 32; 5421 }; 5422 5423 //! 5424 //! \brief MFX_VC1_PRED_PIPE_STATE 5425 //! \details 5426 //! This command is used to set the operating states of the MFD Engine 5427 //! beyond the BSD unit. It is used with both VC1 Long and Short 5428 //! format.Driver is responsible to take the intensity compensation enable 5429 //! signal, the LumScale and the LumShift provided from the VC1 5430 //! interface, and maintain a history of these values for reference 5431 //! pictures. Together with these three parameters specified for the current 5432 //! picture being decoded, driver will derive and supply the above sets of 5433 //! LumScaleX, LumShiftX and intensity compensation enable (single or 5434 //! double, forward or backward) signals. H/W is responsible to take these 5435 //! state values, and use them to build the lookup table (including the 5436 //! derivation of iScale and iShift) for remapping the reference frame 5437 //! pixels, as well as perfoming the actual pixel remapping 5438 //! calculations/process. 5439 //! 5440 struct MFX_VC1_PRED_PIPE_STATE_CMD 5441 { 5442 union 5443 { 5444 //!< DWORD 0 5445 struct 5446 { 5447 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5448 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5449 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5450 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5451 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5452 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5453 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5454 }; 5455 uint32_t Value; 5456 } DW0; 5457 union 5458 { 5459 //!< DWORD 1 5460 struct 5461 { 5462 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 5463 uint32_t ReferenceFrameBoundaryReplicationMode : __CODEGEN_BITFIELD( 4, 7) ; //!< Reference Frame Boundary Replication Mode 5464 uint32_t VinIntensitycompSingleBwden : __CODEGEN_BITFIELD( 8, 9) ; //!< vin_intensitycomp_Single_BWDen 5465 uint32_t VinIntensitycompSingleFwden : __CODEGEN_BITFIELD(10, 11) ; //!< vin_intensitycomp_Single_FWDen 5466 uint32_t VinIntensitycompDoubleBwden : __CODEGEN_BITFIELD(12, 13) ; //!< vin_intensitycomp_Double_BWDen 5467 uint32_t VinIntensitycompDoubleFwden : __CODEGEN_BITFIELD(14, 15) ; //!< vin_intensitycomp_Double_FWDen 5468 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 5469 }; 5470 uint32_t Value; 5471 } DW1; 5472 union 5473 { 5474 //!< DWORD 2 5475 struct 5476 { 5477 uint32_t Lumscale1SingleFwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - Single - FWD 5478 uint32_t Reserved70 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5479 uint32_t Lumscale2SingleFwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - single - FWD 5480 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5481 uint32_t Lumshift1SingleFwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - single - FWD 5482 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5483 uint32_t Lumshift2SingleFwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- single - FWD 5484 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5485 }; 5486 uint32_t Value; 5487 } DW2; 5488 union 5489 { 5490 //!< DWORD 3 5491 struct 5492 { 5493 uint32_t Lumscale1DoubleFwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - double - FWD 5494 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5495 uint32_t Lumscale2DoubleFwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - double - FWD 5496 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5497 uint32_t Lumshift1DoubleFwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - double -FWD 5498 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5499 uint32_t Lumshift2DoubleFwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- double - FWD 5500 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5501 }; 5502 uint32_t Value; 5503 } DW3; 5504 union 5505 { 5506 //!< DWORD 4 5507 struct 5508 { 5509 uint32_t Lumscale1SingleBwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - Single - BWD 5510 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5511 uint32_t Lumscale2SingleBwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - single - BWD 5512 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5513 uint32_t Lumshift1SingleBwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - single - BWD 5514 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5515 uint32_t Lumshift2SingleBwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- single - BWD 5516 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5517 }; 5518 uint32_t Value; 5519 } DW4; 5520 union 5521 { 5522 //!< DWORD 5 5523 struct 5524 { 5525 uint32_t Lumscale1DoubleBwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - double - BWD 5526 uint32_t Reserved166 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5527 uint32_t Lumscale2DoubleBwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - double - BWD 5528 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5529 uint32_t Lumshift1DoubleBwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - double -BWD 5530 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5531 uint32_t Lumshift2DoubleBwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- double - BWD 5532 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5533 }; 5534 uint32_t Value; 5535 } DW5; 5536 5537 //! \name Local enumerations 5538 5539 enum SUBOPCODE_B 5540 { 5541 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5542 }; 5543 5544 enum SUBOPCODE_A 5545 { 5546 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 5547 }; 5548 5549 enum MEDIA_COMMAND_OPCODE 5550 { 5551 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 5552 }; 5553 5554 enum PIPELINE 5555 { 5556 PIPELINE_MFXVC1PREDPIPESTATE = 2, //!< No additional details 5557 }; 5558 5559 enum COMMAND_TYPE 5560 { 5561 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5562 }; 5563 5564 //! \name Initializations 5565 5566 //! \brief Explicit member initialization function 5567 MFX_VC1_PRED_PIPE_STATE_CMD(); 5568 5569 static const size_t dwSize = 6; 5570 static const size_t byteSize = 24; 5571 }; 5572 5573 //! 5574 //! \brief MFD_VC1_LONG_PIC_STATE 5575 //! \details 5576 //! MFX_VC1_LONG PIC_STATE command encapsulates the decoding parameters that 5577 //! are read or derived from bitstream syntax elements above (inclusive) 5578 //! picture header layer. These parameters are static for a picture and when 5579 //! slice structure is present, these parameters are not changed from slice 5580 //! to slice of the same picture. Hence, this command is only issued at the 5581 //! beginning of processing a new picture and prior to the VC1_*_OBJECT 5582 //! command. The values set for these state variables are retained 5583 //! internally across slices.Only the parameters needed by hardware (BSD 5584 //! unit) to decode bit sequence for the macroblocks in a picture layer or a 5585 //! slice layer are presented in this command. Other parameters such as the 5586 //! ones used for inverse transform or motion compensation are provided in 5587 //! MFX_VC1_PRED_PIPE_STATE command.This Long interface format is intel 5588 //! proprietary interface. Driver will need to perform addition operations 5589 //! to generate all the fields in this command. 5590 //! 5591 struct MFD_VC1_LONG_PIC_STATE_CMD 5592 { 5593 union 5594 { 5595 //!< DWORD 0 5596 struct 5597 { 5598 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5599 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5600 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5601 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5602 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5603 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5604 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5605 }; 5606 uint32_t Value; 5607 } DW0; 5608 union 5609 { 5610 //!< DWORD 1 5611 struct 5612 { 5613 uint32_t Picturewidthinmbsminus1PictureWidthMinus1InMacroblocks : __CODEGEN_BITFIELD( 0, 7) ; //!< PictureWidthInMBsMinus1 (Picture Width Minus 1 in Macroblocks) 5614 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 5615 uint32_t Pictureheightinmbsminus1PictureHeightMinus1InMacroblocks : __CODEGEN_BITFIELD(16, 23) ; //!< PictureHeightInMBsMinus1 (Picture Height Minus 1 in Macroblocks) 5616 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 5617 }; 5618 uint32_t Value; 5619 } DW1; 5620 union 5621 { 5622 //!< DWORD 2 5623 struct 5624 { 5625 uint32_t Vc1Profile : __CODEGEN_BITFIELD( 0, 0) ; //!< VC1_PROFILE 5626 uint32_t Reserved65 : __CODEGEN_BITFIELD( 1, 2) ; //!< Reserved 5627 uint32_t Secondfield : __CODEGEN_BITFIELD( 3, 3) ; //!< Secondfield 5628 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< OVERLAP_SMOOTHING_ENABLE_FLAG 5629 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< LOOPFILTER_ENABLE_FLAG 5630 uint32_t RangereductionEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RANGEREDUCTION_ENABLE 5631 uint32_t Rangereductionscale : __CODEGEN_BITFIELD( 7, 7) ; //!< RANGEREDUCTIONSCALE 5632 uint32_t MotionVectorMode : __CODEGEN_BITFIELD( 8, 11) ; //!< MOTION_VECTOR_MODE 5633 uint32_t Syncmarker : __CODEGEN_BITFIELD(12, 12) ; //!< SYNCMARKER 5634 uint32_t InterpolationRounderContro : __CODEGEN_BITFIELD(13, 13) ; //!< Interpolation Rounder Contro 5635 uint32_t Implicitquantizer : __CODEGEN_BITFIELD(14, 14) ; //!< ImplicitQuantizer 5636 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15) ; //!< DmvSurfaceValid 5637 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 5638 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31) ; //!< Bitplane Buffer Pitch Minus 1 5639 }; 5640 uint32_t Value; 5641 } DW2; 5642 union 5643 { 5644 //!< DWORD 3 5645 struct 5646 { 5647 uint32_t Bscalefactor : __CODEGEN_BITFIELD( 0, 7) ; //!< BScaleFactor 5648 uint32_t PquantPictureQuantizationValue : __CODEGEN_BITFIELD( 8, 12) ; //!< PQuant (Picture Quantization Value) 5649 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 5650 uint32_t AltpquantAlternativePictureQuantizationValue : __CODEGEN_BITFIELD(16, 20) ; //!< AltPQuant (Alternative Picture Quantization Value) 5651 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 5652 uint32_t FcmFrameCodingMode : __CODEGEN_BITFIELD(24, 25) ; //!< FCM_FRAME_CODING_MODE 5653 uint32_t PictypePictureType : __CODEGEN_BITFIELD(26, 28) ; //!< PicType (Picture Type) 5654 uint32_t Condover : __CODEGEN_BITFIELD(29, 30) ; //!< CONDOVER 5655 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 5656 }; 5657 uint32_t Value; 5658 } DW3; 5659 union 5660 { 5661 //!< DWORD 4 5662 struct 5663 { 5664 uint32_t Pquantuniform : __CODEGEN_BITFIELD( 0, 0) ; //!< PQUANTUNIFORM 5665 uint32_t Halfqp : __CODEGEN_BITFIELD( 1, 1) ; //!< HalfQP 5666 uint32_t AltpquantconfigAlternativePictureQuantizationConfiguration : __CODEGEN_BITFIELD( 2, 3) ; //!< ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5667 uint32_t AltpquantedgemaskAlternativePictureQuantizationEdgeMask : __CODEGEN_BITFIELD( 4, 7) ; //!< AltPQuantEdgeMask (Alternative Picture Quantization Edge Mask) 5668 uint32_t ExtendedmvrangeExtendedMotionVectorRangeFlag : __CODEGEN_BITFIELD( 8, 9) ; //!< EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5669 uint32_t ExtendeddmvrangeExtendedDifferentialMotionVectorRangeFlag : __CODEGEN_BITFIELD(10, 11) ; //!< EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5670 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5671 uint32_t FwdrefdistReferenceDistance : __CODEGEN_BITFIELD(16, 19) ; //!< FwdRefDist (Reference Distance) 5672 uint32_t BwdrefdistReferenceDistance : __CODEGEN_BITFIELD(20, 23) ; //!< BwdRefDist (Reference Distance) 5673 uint32_t NumrefNumberOfReferences : __CODEGEN_BITFIELD(24, 24) ; //!< NUMREF_NUMBER_OF_REFERENCES 5674 uint32_t ReffieldpicpolarityReferenceFieldPicturePolarity : __CODEGEN_BITFIELD(25, 25) ; //!< REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5675 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD(26, 26) ; //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5676 uint32_t FourmvswitchFourMotionVectorSwitch : __CODEGEN_BITFIELD(27, 27) ; //!< FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5677 uint32_t UnifiedmvmodeUnifiedMotionVectorMode : __CODEGEN_BITFIELD(28, 29) ; //!< UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5678 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5679 }; 5680 uint32_t Value; 5681 } DW4; 5682 union 5683 { 5684 //!< DWORD 5 5685 struct 5686 { 5687 uint32_t CbptabCodedBlockPatternTable : __CODEGEN_BITFIELD( 0, 2) ; //!< CbpTab (Coded Block Pattern Table) 5688 uint32_t TransdctabIntraTransformDcTable : __CODEGEN_BITFIELD( 3, 3) ; //!< TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5689 uint32_t TransacuvPictureLevelTransformChromaAcCodingSetIndexTransactable : __CODEGEN_BITFIELD( 4, 5) ; //!< TransAcUV (Picture-level Transform Chroma AC Coding Set Index, TRANSACTABLE) 5690 uint32_t TransacyPictureLevelTransformLumaAcCodingSetIndexTransactable2 : __CODEGEN_BITFIELD( 6, 7) ; //!< TransAcY (Picture-level Transform Luma AC Coding Set Index, TRANSACTABLE2 5691 uint32_t MbmodetabMacroblockModeTable : __CODEGEN_BITFIELD( 8, 10) ; //!< MbModeTab (Macroblock Mode Table) 5692 uint32_t TranstypembflagMacroblockTransformTypeFlag : __CODEGEN_BITFIELD(11, 11) ; //!< TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5693 uint32_t TranstypePictureLevelTransformType : __CODEGEN_BITFIELD(12, 13) ; //!< TransType (Picture-level Transform Type) 5694 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5695 uint32_t Twomvbptab2MvBlockPatternTable : __CODEGEN_BITFIELD(16, 17) ; //!< TwoMvBpTab (2MV Block Pattern Table) 5696 uint32_t Fourmvbptab4MvBlockPatternTable : __CODEGEN_BITFIELD(18, 19) ; //!< FourMvBpTab (4-MV Block Pattern Table) 5697 uint32_t MvtabMotionVectorTable : __CODEGEN_BITFIELD(20, 22) ; //!< MvTab (Motion Vector Table) 5698 uint32_t Reserved183 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 5699 uint32_t Fieldtxraw : __CODEGEN_BITFIELD(24, 24) ; //!< FIELDTXRAW 5700 uint32_t Acpredraw : __CODEGEN_BITFIELD(25, 25) ; //!< ACPREDRAW 5701 uint32_t Overflagsraw : __CODEGEN_BITFIELD(26, 26) ; //!< OVERFLAGSRAW 5702 uint32_t Directmbraw : __CODEGEN_BITFIELD(27, 27) ; //!< DIRECTMBRAW 5703 uint32_t Skipmbraw : __CODEGEN_BITFIELD(28, 28) ; //!< SKIPMBRAW 5704 uint32_t Mvtypembraw : __CODEGEN_BITFIELD(29, 29) ; //!< MVTYPEMBRAW 5705 uint32_t Forwardmbraw : __CODEGEN_BITFIELD(30, 30) ; //!< FORWARDMBRAW 5706 uint32_t BitplanepresentflagBitplaneBufferPresentFlag : __CODEGEN_BITFIELD(31, 31) ; //!< BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5707 }; 5708 uint32_t Value; 5709 } DW5; 5710 5711 //! \name Local enumerations 5712 5713 enum SUBOPCODE_B 5714 { 5715 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5716 }; 5717 5718 enum SUBOPCODE_A 5719 { 5720 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5721 }; 5722 5723 enum MEDIA_COMMAND_OPCODE 5724 { 5725 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 5726 }; 5727 5728 enum PIPELINE 5729 { 5730 PIPELINE_MFDVC1LONGPICSTATE = 2, //!< No additional details 5731 }; 5732 5733 enum COMMAND_TYPE 5734 { 5735 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5736 }; 5737 5738 //! \brief VC1_PROFILE 5739 //! \details 5740 //! specifies the bitstream profile.This field is used in both VLD and IT 5741 //! modes. 5742 enum VC1_PROFILE 5743 { 5744 VC1_PROFILE_DISABLE = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 5745 VC1_PROFILE_ENABLE = 1, //!< current picture is in Advanced Profile 5746 }; 5747 5748 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 5749 //! \details 5750 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 5751 //! if Overlap smoothing is ON at the picture levelThis field is used in 5752 //! both VLD and IT modes. 5753 enum OVERLAP_SMOOTHING_ENABLE_FLAG 5754 { 5755 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 5756 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 5757 }; 5758 5759 //! \brief LOOPFILTER_ENABLE_FLAG 5760 //! \details 5761 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 5762 //! indicates if In-loop Deblocking is ON according to picture level 5763 //! bitstream syntax control. This bit affects BSD unit and also the loop 5764 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 5765 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 5766 //! in-loop deblocking operation follows the VC1 standard - deblocking 5767 //! doesn't cross slice boundary.When this bit is set to 0, but 5768 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 5769 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 5770 //! this case, deblocking operation does cross slice boundary.This field is 5771 //! used in VLD mode only, not in IT mode. 5772 enum LOOPFILTER_ENABLE_FLAG 5773 { 5774 LOOPFILTER_ENABLE_FLAG_DISABLE = 0, //!< Disables loop filter 5775 LOOPFILTER_ENABLE_FLAG_ENABLE = 1, //!< Enables loop filter 5776 }; 5777 5778 //! \brief RANGEREDUCTION_ENABLE 5779 //! \details 5780 //! This field specifies whether on-the-fly pixel value range reduction 5781 //! should be performed for the preceding (or forward) reference picture. 5782 //! Along with RangeReductionScale to specify whether scale up or down 5783 //! should be performed. It is not the same value as RANGEREDFRM Syntax 5784 //! Element (PictureParameters bPicDeblocked bit 5) in the Picture 5785 //! Header. 5786 enum RANGEREDUCTION_ENABLE 5787 { 5788 RANGEREDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 5789 RANGEREDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 5790 }; 5791 5792 //! \brief RANGEREDUCTIONSCALE 5793 //! \details 5794 //! This field specifies whether the reference picture pixel values should 5795 //! be scaled up or scaled down on-the-fly, if RangeReduction is Enabled. 5796 enum RANGEREDUCTIONSCALE 5797 { 5798 RANGEREDUCTIONSCALE_UNNAMED0 = 0, //!< Scale down reference picture by factor of 2 5799 RANGEREDUCTIONSCALE_UNNAMED1 = 1, //!< Scale up reference picture by factor of 2 5800 }; 5801 5802 //! \brief MOTION_VECTOR_MODE 5803 //! \details 5804 //! This field indicates one of the following motion compensation 5805 //! interpolation modes for P and B pictures. The MC interpolation modes 5806 //! apply to prediction values of luminance blocks and are always in 5807 //! quarter-sample. For chrominance blocks, it always performs bilinear 5808 //! interpolation with either half-pel or quarter-pel precision.Before the 5809 //! polarity of Chroma Half-pel or Q-pel is reversed, now I 5810 //! have fixed it to match with VC1 Spec. 5811 enum MOTION_VECTOR_MODE 5812 { 5813 MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Chroma Quarter -pel + Luma bicubic. (can only be 1MV) 5814 MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< Chroma Half-pel + Luma bicubic. (can be 1MV or 4MV) 5815 MOTION_VECTOR_MODE_UNNAMED8 = 8, //!< Chroma Quarter -pel + Luma bilinear. (can only be 1MV) 5816 MOTION_VECTOR_MODE_UNNAMED9 = 9, //!< Chroma Half-pel + Luma bilinear 5817 }; 5818 5819 //! \brief SYNCMARKER 5820 //! \details 5821 //! Indicates whether sync markers are enabled/disabled. If enable, sync 5822 //! markers "may be" present in the current video sequence being decoded. It 5823 //! is a sequence level syntax element and is valid only for Simple and Main 5824 //! Profiles. 5825 enum SYNCMARKER 5826 { 5827 SYNCMARKER_NOTPRESENT = 0, //!< Sync Marker is not present in the bitstream 5828 SYNCMARKER_MAYBEPRESENT = 1, //!< Sync Marker maybe present in the bitstream 5829 }; 5830 5831 //! \brief FCM_FRAME_CODING_MODE 5832 //! \details 5833 //! This is the same as the variable FCM defined in VC1.This field must be 5834 //! set to 0 for Simple and Main ProfilesThis field is unique to intel VC1 5835 //! VLD Long format, and is used in IT mode as well. For VC1 IT mode, 5836 //! driver needs to convert the interface to intel HW VLD Long Format 5837 //! interface. 5838 enum FCM_FRAME_CODING_MODE 5839 { 5840 FCM_FRAME_CODING_MODE_DISABLE = 0, //!< Progressive Frame Picture 5841 FCM_FRAME_CODING_MODE_ENABLE = 1, //!< Interlaced Frame Picture 5842 FCM_FRAME_CODING_MODE_UNNAMED2 = 2, //!< Field Picture with Top Field First 5843 FCM_FRAME_CODING_MODE_UNNAMED3 = 3, //!< Field Picture with Bottom Field First 5844 }; 5845 5846 //! \brief CONDOVER 5847 //! \details 5848 //! This field is the decoded syntax element CONDOVER in a bitstream of 5849 //! advanced profile. It controls the overlap smoothing filter operation for 5850 //! an I frame or an BI frame when the picture level qualization step size 5851 //! PQUANT is 8 or lower.This field is used in intel VC1 VLD mode only, not 5852 //! in VC1 and IT modes. 5853 enum CONDOVER 5854 { 5855 CONDOVER_UNNAMED0 = 0, //!< No overlap smoothing 5856 CONDOVER_UNNAMED1 = 1, //!< Reserved 5857 CONDOVER_UNNAMED2 = 2, //!< Always perform overlap smoothing filter 5858 CONDOVER_UNNAMED3 = 3, //!< Overlap smoothing on a per macroblock basis based on OVERFLAGS 5859 }; 5860 5861 //! \brief PQUANTUNIFORM 5862 //! \details 5863 //! Indicating if uniform quantization applies to the 5864 //! picture. It is used for inverse quantization of the AC 5865 //! coefficients.QUANTIZER 5866 //! 001123PQUANTIZER - 5867 //! -01--PQINDEX>=9<=8----PQuantUniform010201ImplicitQuantizer = 5868 //! 0, and 5869 //! PQuantUniform = 0 is used to represent 2 cases : 1) QUANTIZER=01 5870 //! and 5871 //! PQUANTIZER=0; and 2) QUANTIZER = 10b.ImplicitQuantizer = 0, and 5872 //! PQuantUniform = 5873 //! 1 is used to represent 2 cases : 1) QUANTIZER=01 and PQUANTIZER=1; 5874 //! and 2) 5875 //! QUANTIZER = 11bThis field is unique to intel VC1 VLD Long format 5876 //! mode, and is 5877 //! not used in IT and VC1 modes. 5878 enum PQUANTUNIFORM 5879 { 5880 PQUANTUNIFORM_UNNAMED0 = 0, //!< Non-uniform 5881 PQUANTUNIFORM_UNNAMED1 = 1, //!< Uniform 5882 }; 5883 5884 //! \brief ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5885 //! \details 5886 //! This field specifies the way AltPQuant is used in the picture. It 5887 //! determines how to compute the macroblock quantizer step size, MQUANT. It 5888 //! is derived based on the following variables DQUANT, DQUANTFRM, 5889 //! DQPROFILE, DQSBEDGE, DQDBEDGE, and DQBILEVEL defined in the VC1 5890 //! standard, as shown in Error! Reference source not found..This field is 5891 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 5892 //! VC1 modes. 5893 enum ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5894 { 5895 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED0 = 0, //!< AltPQuant not used 5896 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED1 = 1, //!< AltPQuant is used and applied to edge macroblocks only 5897 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED2 = 2, //!< MQUANT is encoded in macroblock layer 5898 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED3 = 3, //!< AltPQuant and PQuant are selected on macroblock basis 5899 }; 5900 5901 //! \brief EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5902 //! \details 5903 //! This field specifies the motion vector range in quarter-pel or half-pel 5904 //! modes. It is equivalent to the variable MVRANGE in the VC1 standard. 5905 //! This field is unique to intel VC1 VLD Long format mode, and is not used 5906 //! in IT and VC1 modes 5907 enum EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5908 { 5909 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< [-256, 255] x [-128, 127] 5910 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< 512, 511] x [-256, 255] 5911 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< [-2048, 2047] x [-1024, 1023] 5912 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< [-4096, 4095] x [-2048, 2047] 5913 }; 5914 5915 //! \brief EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5916 //! \details 5917 //! This field specifies the differential motion vector range in interlaced 5918 //! pictures. It is equivalent to the variable DMVRANGE in the VC1 standard. 5919 //! This field is unique to intel VC1 VLD Long format mode, and is not used 5920 //! in IT and VC1 modes. 5921 enum EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5922 { 5923 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< No extended range 5924 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< Extended horizontally 5925 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< Extended vertically 5926 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< Extended in both directions 5927 }; 5928 5929 //! \brief NUMREF_NUMBER_OF_REFERENCES 5930 //! \details 5931 //! This field indicates how many reference fields are referenced by the 5932 //! current (field) picture. It is identical to the variable NUMREF in the 5933 //! VC1 standard. This field is only valid for field P picture (FCM = 10 | 5934 //! 11).This field is unique to intel VC1 VLD Long format mode, and is not 5935 //! used in IT and VC1 modes. 5936 enum NUMREF_NUMBER_OF_REFERENCES 5937 { 5938 NUMREF_NUMBER_OF_REFERENCES_UNNAMED0 = 0, //!< One field referenced 5939 NUMREF_NUMBER_OF_REFERENCES_UNNAMED1 = 1, //!< Two fields referenced 5940 }; 5941 5942 //! \brief REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5943 //! \details 5944 //! This field specifies the polarity of the one reference field picture 5945 //! used for a field P picture. It is derived from the variable REFFIELD 5946 //! defined in VC1 standard and is only valid when one field is referenced 5947 //! (NUMREF = 0) for a field P picture.When NUMREF = 0 and REFFIELD = 0, 5948 //! this field is the polarity of the reference I/P field that is temporally 5949 //! closest; When NUMREF = 0 and REFFIELD = 1, this field is the polarity of 5950 //! the reference I/P field that is the second most temporally closest. The 5951 //! distance is measured based on display order but ignoring the repeated 5952 //! field if present (due to RFF = 1).This field is unique to intel VC1 VLD 5953 //! Long format mode, and is not used in IT and VC1 modes. 5954 enum REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5955 { 5956 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED0 = 0, //!< Top (even) field 5957 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED1 = 1, //!< Bottom (odd) field 5958 }; 5959 5960 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5961 //! \details 5962 //! This field specifies whether the motion vectors for 5963 //! UV is rounded to half or full pel position. It is identical to the 5964 //! variable 5965 //! FASTUVMC in VC1 standard.This field is used in both VLD and IT 5966 //! modes.It is 5967 //! derived from FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in 5968 //! both VLD and 5969 //! IT modes, and should have the same value as Motion Vector Mode 5970 //! LSBit. 5971 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5972 { 5973 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 5974 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 5975 }; 5976 5977 //! \brief FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5978 //! \details 5979 //! This field indicates if 4-MV is present for an interlaced frame P 5980 //! picture. It is identical to the variable 4MVSWITCH (4 Motion Vector 5981 //! Switch) in VC1 standard.This field is used in intel VC1 VLD Long Format 5982 //! mode only, it is not used in VC1 VLD and IT modes. 5983 enum FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5984 { 5985 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_DISABLE = 0, //!< only 1-MV 5986 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_ENABLE = 1, //!< 1, 2, or 4 motion vectors 5987 }; 5988 5989 //! \brief UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5990 //! \details 5991 //! This field is a combination of the variables MVMODE and MVMODE2 in the 5992 //! VC1 standard, for parsing Luma MVD from the bitstream. This field is 5993 //! used to signal 1MV vs 4MVallowed (Mixed Mode). This field is also used 5994 //! to signal Q-pel or Half-pel MVD read from the bitstream. The bicubic or 5995 //! bilinear Luma MC interpolation mode is duplicate information from Motion 5996 //! Vector Mode field, and is ignored here.This field is used in intel VC1 5997 //! VLD Long Format mode only, it is not used in VC1 VLD and IT modes. 5998 enum UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5999 { 6000 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Mixed MV, Q-pel bicubic 6001 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< 1-MV, Q-pel bicubic 6002 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED2 = 2, //!< 1-MV half-pel bicubic 6003 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED3 = 3, //!< 1-MV half-pel bilinear 6004 }; 6005 6006 //! \brief TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 6007 //! \details 6008 //! This field specifies whether the low motion tables or the high motion 6009 //! tables are used to decode the Transform DC coefficients in intra-coded 6010 //! blocks. This field is identical to the variable TRANSDCTAB in the VC1 6011 //! standard, section 8.1.1.2.This field is valid for all picture types.This 6012 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6013 //! and VC1 modes. 6014 enum TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 6015 { 6016 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED0 = 0, //!< The high motion tables 6017 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED1 = 1, //!< The low motion tables 6018 }; 6019 6020 //! \brief TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 6021 //! \details 6022 //! This field indicates whether Transform Type is fixed at picture level or 6023 //! variable at macroblock level. It is identical to the variable TTMBF in 6024 //! the VC1 standard, section 7.1.1.40.This field is set to 1 when 6025 //! VSTRANSFORM is 0 in the entry point layer.This field is unique to intel 6026 //! VC1 VLD Long format mode, and is not used in IT and VC1 modes. 6027 enum TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 6028 { 6029 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED0 = 0, //!< variable transform type in macroblock layer 6030 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED1 = 1, //!< use picture level transform type TransType 6031 }; 6032 6033 //! \brief FIELDTXRAW 6034 //! \details 6035 //! This field indicates whether the FIELDTX field is coded in raw or 6036 //! non-raw mode.This field is only valid when PictureType is I or BI.This 6037 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6038 //! and VC1 modes. 6039 enum FIELDTXRAW 6040 { 6041 FIELDTXRAW_DISABLE = 0, //!< Non-Raw Mode 6042 FIELDTXRAW_ENABLE = 1, //!< Raw Mode 6043 }; 6044 6045 //! \brief ACPREDRAW 6046 //! \details 6047 //! This field indicates whether the ACPRED field is coded in raw or non-raw 6048 //! mode.This field is only valid when PictureType is I or BI.This field is 6049 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 6050 //! VC1 modes. 6051 enum ACPREDRAW 6052 { 6053 ACPREDRAW_DISABLE = 0, //!< Non-Raw Mode 6054 ACPREDRAW_ENABLE = 1, //!< Raw Mode 6055 }; 6056 6057 //! \brief OVERFLAGSRAW 6058 //! \details 6059 //! This field indicates whether the OVERFLAGS field is coded in raw or 6060 //! non-raw mode.This field is only valid when PictureType is I or BI.This 6061 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6062 //! and VC1 modes. 6063 enum OVERFLAGSRAW 6064 { 6065 OVERFLAGSRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6066 OVERFLAGSRAW_UNNAMED1 = 1, //!< Raw Mode 6067 }; 6068 6069 //! \brief DIRECTMBRAW 6070 //! \details 6071 //! This field indicates whether the DIRECTMB field is coded in raw or 6072 //! non-raw mode.This field is only valid when PictureType is P or B.This 6073 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6074 //! and VC1 modes. 6075 enum DIRECTMBRAW 6076 { 6077 DIRECTMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6078 DIRECTMBRAW_UNNAMED1 = 1, //!< Raw Mode 6079 }; 6080 6081 //! \brief SKIPMBRAW 6082 //! \details 6083 //! This field indicates whether the SKIPMB field is coded in raw or non-raw 6084 //! mode.This field is only valid when PictureType is P or B.0 = non-raw 6085 //! mode1 = raw modeThis field is unique to intel VC1 VLD Long format mode, 6086 //! and is not used in IT and VC1 modes. 6087 enum SKIPMBRAW 6088 { 6089 SKIPMBRAW_DISABLE = 0, //!< Non-Raw Mode 6090 SKIPMBRAW_ENABLE = 1, //!< Raw Mode 6091 }; 6092 6093 //! \brief MVTYPEMBRAW 6094 //! \details 6095 //! This field indicates whether the MVTYPREMB field is coded in raw or 6096 //! non-raw mode.This field is only valid when PictureType is P.This field 6097 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 6098 //! VC1 modes. 6099 enum MVTYPEMBRAW 6100 { 6101 MVTYPEMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6102 MVTYPEMBRAW_UNNAMED1 = 1, //!< Raw Mode 6103 }; 6104 6105 //! \brief FORWARDMBRAW 6106 //! \details 6107 //! This field indicates whether the FORWARDMB field is coded in raw or 6108 //! non-raw mode.This field is only valid when PictureType is B.This field 6109 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 6110 //! VC1 modes. 6111 enum FORWARDMBRAW 6112 { 6113 FORWARDMBRAW_UNNAMED0 = 0, //!< non-raw mode 6114 FORWARDMBRAW_UNNAMED1 = 1, //!< raw mode 6115 }; 6116 6117 //! \brief BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 6118 //! \details 6119 //! This field indicates whether the bitplane buffer is present for the 6120 //! picture. If set, at least one of the fields listed in bits 22:16 is 6121 //! coded in non-raw mode, and Bitplane Buffer Base Address field in the 6122 //! VC1_BSD_BUF_BASE_STATE command points to the bitplane buffer. Otherwise, 6123 //! all the fields that are applicable for the current picture in bits 22:16 6124 //! must be coded in raw mode.This field is unique to intel VC1 VLD Long 6125 //! format mode, and is not used in IT and VC1 modes. 6126 enum BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 6127 { 6128 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED0 = 0, //!< bitplane buffer is not present 6129 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED1 = 1, //!< bitplane buffer is present 6130 }; 6131 6132 //! \name Initializations 6133 6134 //! \brief Explicit member initialization function 6135 MFD_VC1_LONG_PIC_STATE_CMD(); 6136 6137 static const size_t dwSize = 6; 6138 static const size_t byteSize = 24; 6139 }; 6140 6141 //! 6142 //! \brief MFD_VC1_SHORT_PIC_STATE 6143 //! \details 6144 //! 6145 //! 6146 struct MFD_VC1_SHORT_PIC_STATE_CMD 6147 { 6148 union 6149 { 6150 //!< DWORD 0 6151 struct 6152 { 6153 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6154 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6155 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6156 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6157 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6158 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6159 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6160 }; 6161 uint32_t Value; 6162 } DW0; 6163 union 6164 { 6165 //!< DWORD 1 6166 struct 6167 { 6168 uint32_t PictureWidth : __CODEGEN_BITFIELD( 0, 7) ; //!< Picture Width 6169 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 6170 uint32_t PictureHeight : __CODEGEN_BITFIELD(16, 23) ; //!< Picture Height 6171 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6172 }; 6173 uint32_t Value; 6174 } DW1; 6175 union 6176 { 6177 //!< DWORD 2 6178 struct 6179 { 6180 uint32_t PictureStructure : __CODEGEN_BITFIELD( 0, 1) ; //!< PICTURE_STRUCTURE 6181 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 6182 uint32_t Secondfield : __CODEGEN_BITFIELD( 3, 3) ; //!< SecondField 6183 uint32_t IntraPictureFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< INTRA_PICTURE_FLAG 6184 uint32_t BackwardPredictionPresentFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< Backward Prediction Present Flag 6185 uint32_t Reserved70 : __CODEGEN_BITFIELD( 6, 10) ; //!< Reserved 6186 uint32_t Vc1Profile : __CODEGEN_BITFIELD(11, 11) ; //!< VC1_PROFILE 6187 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 14) ; //!< Reserved 6188 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15) ; //!< DmvSurfaceValid 6189 uint32_t MotionVectorMode : __CODEGEN_BITFIELD(16, 19) ; //!< Motion Vector Mode 6190 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 6191 uint32_t InterpolationRounderControl : __CODEGEN_BITFIELD(23, 23) ; //!< Interpolation Rounder Control 6192 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31) ; //!< Bitplane Buffer Pitch Minus 1 6193 }; 6194 uint32_t Value; 6195 } DW2; 6196 union 6197 { 6198 //!< DWORD 3 6199 struct 6200 { 6201 uint32_t VstransformFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSTRANSFORM_FLAG 6202 uint32_t Dquant : __CODEGEN_BITFIELD( 1, 2) ; //!< DQUANT 6203 uint32_t ExtendedMvPresentFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< EXTENDED_MV_PRESENT_FLAG 6204 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6205 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< LOOPFILTER_ENABLE_FLAG 6206 uint32_t RefdistFlag : __CODEGEN_BITFIELD( 6, 6) ; //!< REFDIST_FLAG 6207 uint32_t PanscanPresentFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< PANSCAN_PRESENT_FLAG 6208 uint32_t Maxbframes : __CODEGEN_BITFIELD( 8, 10) ; //!< MAXBFRAMES 6209 uint32_t RangeredPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(11, 11) ; //!< RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6210 uint32_t SyncmarkerPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(12, 12) ; //!< SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6211 uint32_t MultiresPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(13, 13) ; //!< MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6212 uint32_t Quantizer : __CODEGEN_BITFIELD(14, 15) ; //!< QUANTIZER 6213 uint32_t PPicRefDistance : __CODEGEN_BITFIELD(16, 20) ; //!< P_PIC_REF_DISTANCE 6214 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 6215 uint32_t ProgressivePicType : __CODEGEN_BITFIELD(22, 23) ; //!< PROGRESSIVE_PIC_TYPE 6216 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 27) ; //!< Reserved 6217 uint32_t RangeReductionEnable : __CODEGEN_BITFIELD(28, 28) ; //!< RANGE_REDUCTION_ENABLE 6218 uint32_t RangeReductionScale : __CODEGEN_BITFIELD(29, 29) ; //!< RANGE_REDUCTION_SCALE 6219 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD(30, 30) ; //!< OVERLAP_SMOOTHING_ENABLE_FLAG 6220 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 6221 }; 6222 uint32_t Value; 6223 } DW3; 6224 union 6225 { 6226 //!< DWORD 4 6227 struct 6228 { 6229 uint32_t ExtendedDmvPresentFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< EXTENDED_DMV_PRESENT_FLAG 6230 uint32_t Psf : __CODEGEN_BITFIELD( 1, 1) ; //!< PSF 6231 uint32_t RefpicFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< REFPIC_FLAG 6232 uint32_t Finterflag : __CODEGEN_BITFIELD( 3, 3) ; //!< FINTERFLAG 6233 uint32_t Tfcntrflag : __CODEGEN_BITFIELD( 4, 4) ; //!< TFCNTRFLAG 6234 uint32_t Interlace : __CODEGEN_BITFIELD( 5, 5) ; //!< INTERLACE 6235 uint32_t Pulldown : __CODEGEN_BITFIELD( 6, 6) ; //!< PULLDOWN 6236 uint32_t PostprocFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< POSTPROC Flag 6237 uint32_t _4MvAllowedFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< _4MV Allowed Flag 6238 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 23) ; //!< Reserved 6239 uint32_t BfractionEnumeration : __CODEGEN_BITFIELD(24, 28) ; //!< BFraction Enumeration 6240 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 6241 }; 6242 uint32_t Value; 6243 } DW4; 6244 6245 //! \name Local enumerations 6246 6247 enum SUBOPCODE_B 6248 { 6249 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 6250 }; 6251 6252 enum SUBOPCODE_A 6253 { 6254 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6255 }; 6256 6257 enum MEDIA_COMMAND_OPCODE 6258 { 6259 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6260 }; 6261 6262 enum PIPELINE 6263 { 6264 PIPELINE_MFDVC1SHORTPICSTATE = 2, //!< No additional details 6265 }; 6266 6267 enum COMMAND_TYPE 6268 { 6269 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6270 }; 6271 6272 //! \brief PICTURE_STRUCTURE 6273 //! \details 6274 //! This field is used in both VC1 VLD mode and IT mode. It is the 6275 //! same parameter as bPicStructure in VC1 spec. 6276 //! The Picture Structure and Progressive Pic Type are used to derive 6277 //! the picture structure as specified in FCM, in VC1 VLD and IT mode. 6278 enum PICTURE_STRUCTURE 6279 { 6280 PICTURE_STRUCTURE_UNNAMED0 = 0, //!< illegal 6281 PICTURE_STRUCTURE_UNNAMED1 = 1, //!< top field (bit 0) 6282 PICTURE_STRUCTURE_UNNAMED2 = 2, //!< bottom field (bit 1) 6283 PICTURE_STRUCTURE_UNNAMED3 = 3, //!< frame (both fields are present) 6284 }; 6285 6286 //! \brief INTRA_PICTURE_FLAG 6287 //! \details 6288 //! This field is used in both VC1 VLD mode and IT mode. It is the 6289 //! same parameter as bPicIntra in VC1 spec. 6290 //! The Intra Picture Flag, Backward Prediction Present Flag and 6291 //! RefPicFlag are used to derive the picture type, as specified in PTYPE 6292 //! for a frame, and in FPTYPE for a field, in VC1 VLD and IT mode. 6293 enum INTRA_PICTURE_FLAG 6294 { 6295 INTRA_PICTURE_FLAG_UNNAMED0 = 0, //!< entire picture can have a mixture of intra and inter MB type or just inter MB type. 6296 INTRA_PICTURE_FLAG_UNNAMED1 = 1, //!< entire picture is coded in intra MB type 6297 }; 6298 6299 //! \brief VC1_PROFILE 6300 //! \details 6301 //! specifies the bitstream profile. 6302 //! Note: This is required because 128 is added for intra blocks post 6303 //! inverse transform in advanced profile and also to find out if Motion 6304 //! vectors are adjusted or not. 6305 //! This field is used in both VLD and IT modes. 6306 enum VC1_PROFILE 6307 { 6308 VC1_PROFILE_UNNAMED0 = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 6309 VC1_PROFILE_UNNAMED1 = 1, //!< current picture is in Advanced Profile 6310 }; 6311 6312 enum VSTRANSFORM_FLAG 6313 { 6314 VSTRANSFORM_FLAG_DISABLE = 0, //!< variable-sized transform coding is not enabled 6315 VSTRANSFORM_FLAG_ENABLE = 1, //!< variable-sized transform coding is enabled 6316 }; 6317 6318 //! \brief DQUANT 6319 //! \details 6320 //! Use for Picture Header Parsing of VOPDUANT elements 6321 enum DQUANT 6322 { 6323 DQUANT_UNNAMED0 = 0, //!< no VOPDQUANT elements; Quantizer cannot vary in frame, same quantization step size PQUANT is used for all MBs in the frame 6324 DQUANT_UNNAMED1 = 1, //!< refer to VC1 Spec. for all the MB position dependent quantizer selection 6325 DQUANT_UNNAMED2 = 2, //!< The macroblocks located on the picture edge boundary shall be quantized with ALTPQUANT while the rest of the macroblocks shall be quantized with PQUANT. 6326 }; 6327 6328 //! \brief EXTENDED_MV_PRESENT_FLAG 6329 //! \details 6330 //! BitFieldDesc 6331 enum EXTENDED_MV_PRESENT_FLAG 6332 { 6333 EXTENDED_MV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_MV is not present in the picture header 6334 EXTENDED_MV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_MV is present in the picture header 6335 }; 6336 6337 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6338 //! \details 6339 //! This field specifies whether the motion vectors for 6340 //! UV is rounded to half or full pel position. It is identical to the 6341 //! variable 6342 //! FASTUVMC in VC1 standard.This field is used in both VLD and IT 6343 //! modes.It is 6344 //! derived from FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in 6345 //! both VLD and 6346 //! IT modes, and should have the same value as Motion Vector Mode 6347 //! LSBit. 6348 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6349 { 6350 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 6351 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 6352 }; 6353 6354 //! \brief LOOPFILTER_ENABLE_FLAG 6355 //! \details 6356 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 6357 //! indicates if In-loop Deblocking is ON according to picture level 6358 //! bitstream syntax control. This bit affects BSD unit and also the loop 6359 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 6360 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 6361 //! in-loop deblocking operation follows the VC1 standard - deblocking 6362 //! doesn't cross slice boundary.When this bit is set to 0, but 6363 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 6364 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 6365 //! this case, deblocking operation does cross slice boundary.This field is 6366 //! used in VLD mode only, not in IT mode. 6367 enum LOOPFILTER_ENABLE_FLAG 6368 { 6369 LOOPFILTER_ENABLE_FLAG_UNNAMED0 = 0, //!< In-Loop-Deblocking-Filter is disabled 6370 LOOPFILTER_ENABLE_FLAG_UNNAMED1 = 1, //!< In-Loop-Deblocking-Filter is enabled 6371 }; 6372 6373 enum PANSCAN_PRESENT_FLAG 6374 { 6375 PANSCAN_PRESENT_FLAG_UNNAMED0 = 0, //!< Pan Scan Parameters are not present in the picture header 6376 PANSCAN_PRESENT_FLAG_UNNAMED1 = 1, //!< Pan Scan Parameters are present in the picture header 6377 }; 6378 6379 //! \brief RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6380 //! \details 6381 //! It is needed for Picture Header Parsing.Driver is responsible to keep 6382 //! RangeReductionScale, RangeReduction Enable and RANGERED Present Flag of 6383 //! current picture coherent. 6384 enum RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6385 { 6386 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Range Reduction Parameter (RANGEREDFRM) is not present in the picture header 6387 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Range Reduction Parameter (RANGEREDFRM) is present in the picture header. 6388 }; 6389 6390 enum SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6391 { 6392 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Bitstream for Simple and Main Profile has no sync marker 6393 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Bitstream for Simple and Main Profile may have sync marker(s) 6394 }; 6395 6396 enum MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6397 { 6398 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< RESPIC Parameter is present in the picture header 6399 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< RESPIC Parameter is present in the picture header 6400 }; 6401 6402 enum QUANTIZER 6403 { 6404 QUANTIZER_UNNAMED0 = 0, //!< implicit quantizer at frame leve 6405 QUANTIZER_UNNAMED1 = 1, //!< explicit quantizer at frame level, and use PQUANTIZER SE to specify uniform or non-uniform 6406 QUANTIZER_UNNAMED2 = 2, //!< explicit quantizer, and non-uniform quantizer for all frames 6407 QUANTIZER_UNNAMED3 = 3, //!< explicit quantizer, and uniform quantizer for all frames 6408 }; 6409 6410 //! \brief P_PIC_REF_DISTANCE 6411 //! \details 6412 //! This element defines the number of frames between the current frame and 6413 //! the reference frame. It is the same as the REFDIST SE in VC1 interlaced 6414 //! field picture header. It is present if the entry-level flag REFDIST_FLAG 6415 //! == 1, and if the picture type is not one of the following types: B/B, 6416 //! B/BI, BI/B, BI/BI. If the entry level flag REFDIST_FLAG == 0, REFDIST 6417 //! shall be set to the default value of 0.This field is used in VC1 6418 //! VLD mode only, not used in IT and intel VC1 VLD Long Format modes. 6419 enum P_PIC_REF_DISTANCE 6420 { 6421 P_PIC_REF_DISTANCE_UNNAMED0 = 0, //!< No additional details 6422 }; 6423 6424 //! \brief PROGRESSIVE_PIC_TYPE 6425 //! \details 6426 //! This field is used in both VC1 VLD mode and IT mode. It is the 6427 //! same parameter as bPicExtrapolation in VC1 spec.The Picture 6428 //! Structure and Progressive Pic Type are used to derive the picture 6429 //! structure as specified in FCM, in VC1 VLD and IT mode. 6430 enum PROGRESSIVE_PIC_TYPE 6431 { 6432 PROGRESSIVE_PIC_TYPE_UNNAMED0 = 0, //!< progressive only picture 6433 PROGRESSIVE_PIC_TYPE_UNNAMED1 = 1, //!< progressive only picture 6434 PROGRESSIVE_PIC_TYPE_UNNAMED2 = 2, //!< interlace picture (frame-interlace or field-interlace) 6435 PROGRESSIVE_PIC_TYPE_UNNAMED3 = 3, //!< illegal 6436 }; 6437 6438 //! \brief RANGE_REDUCTION_ENABLE 6439 //! \details 6440 //! This field specifies whether on-the-fly pixel value 6441 //! range reduction should be performed for the preceding (or forward) 6442 //! reference 6443 //! picture. Along with RangeReductionScale to specify whether scale up 6444 //! or down 6445 //! should be performed. It is not the same value as RANGEREDFRM Syntax 6446 //! Element 6447 //! (PictureParameters bPicDeblocked bit 5) in the Picture 6448 //! Header.This field is 6449 //! for Main Profile only. Simple Profile is always disable, and not 6450 //! applicable to 6451 //! Advanced Profile. This field is used in both VLD and IT modes.This 6452 //! is derived by 6453 //! driver from the history of RANGERED and RANGEREDFRM syntax elements 6454 //! (i.e. of 6455 //! forward/preceding reference picture) and those of the current 6456 //! picture.RANGERED 6457 //! is the same as (bPicOverflowBlocks >> 3) & 1. RANGEREDFRM 6458 //! is the same 6459 //! as (bPicDeblocked >> 5) & 1.For the current picture is a 6460 //! B picture, 6461 //! this field represents the state of the forward/preceding reference 6462 //! picture 6463 //! onlyDriver is responsible to keep RangeReductionScale, 6464 //! RangeReduction Enable and 6465 //! RANGERED Present Flag of current picture coherent. 6466 enum RANGE_REDUCTION_ENABLE 6467 { 6468 RANGE_REDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 6469 RANGE_REDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 6470 }; 6471 6472 //! \brief RANGE_REDUCTION_SCALE 6473 //! \details 6474 //! This field specifies whether the reference picture 6475 //! pixel values should be scaled up or scaled down on-the-fly, if 6476 //! RangeReduction is 6477 //! Enabled.NOTE: This bit is derived by driver for Main Profile only. 6478 //! Ignored in 6479 //! Simple and Advanced Profiles. This field is used in both VLD and IT 6480 //! modes.This 6481 //! is derived by driver from the history of RANGERED and RANGEREDFRM 6482 //! syntax 6483 //! elements (i.e. of forward/preceding reference picture) and those of 6484 //! the current 6485 //! picture. RANGERED is the same as (bPicOverflowBlocks >> 3) 6486 //! & 1. 6487 //! RANGEREDFRM is the same as (bPicDeblocked >> 5) & 1. For 6488 //! the current 6489 //! picture is a B picture, this field represents the state of the 6490 //! forward/preceding 6491 //! reference picture onlyDriver is responsible to keep 6492 //! RangeReductionScale, 6493 //! RangeReduction Enable and RANGERED Present Flag of current picture 6494 //! coherent. 6495 enum RANGE_REDUCTION_SCALE 6496 { 6497 RANGE_REDUCTION_SCALE_DISABLE = 0, //!< Scale down reference picture by factor of 2 6498 RANGE_REDUCTION_SCALE_ENABLE = 1, //!< Scale up reference picture by factor of 2 6499 }; 6500 6501 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 6502 //! \details 6503 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 6504 //! if Overlap smoothing is ON at the picture levelThis field is used in 6505 //! both VLD and IT modes 6506 enum OVERLAP_SMOOTHING_ENABLE_FLAG 6507 { 6508 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 6509 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 6510 }; 6511 6512 enum EXTENDED_DMV_PRESENT_FLAG 6513 { 6514 EXTENDED_DMV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_DMV is not present in the picture header 6515 EXTENDED_DMV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_DMV is present in the picture header 6516 }; 6517 6518 //! \brief REFPIC_FLAG 6519 //! \details 6520 //! For a BI picture, REFPIC flag must set to 0For I and P picture, REFPIC 6521 //! flag must set to 0.For a B picture, REFPIC flag must set to 0, except 6522 //! for a B-field in interlaced field mode which can be 0 or 1 (e.g. the top 6523 //! B field can be used as a reference for decoding its corresponding bottom 6524 //! B-field in a field pair).In VLD mode, this flag cannot be used as an 6525 //! optimization signaling for an I or P picture that is not used as a 6526 //! reference picture.This field is used in both VC1 VLD mode and IT 6527 //! mode. It is the same parameter as bPicDeblockConfined[bit2] in VC1 6528 //! spec.The Intra Picture Flag, Backward Prediction Present Flag and 6529 //! RefPicFlag are used to derive the picture type, as specified in PTYPE 6530 //! for a frame, and in FPTYPE for a field, in VC1 VLD and IT mode. 6531 enum REFPIC_FLAG 6532 { 6533 REFPIC_FLAG_UNNAMED0 = 0, //!< the current picture after decoded, will never used as a reference picture 6534 REFPIC_FLAG_UNNAMED1 = 1, //!< the current picture after decoded, will be used as a reference picture later 6535 }; 6536 6537 //! \name Initializations 6538 6539 //! \brief Explicit member initialization function 6540 MFD_VC1_SHORT_PIC_STATE_CMD(); 6541 6542 static const size_t dwSize = 5; 6543 static const size_t byteSize = 20; 6544 }; 6545 6546 //! 6547 //! \brief MFX_VC1_DIRECTMODE_STATE 6548 //! \details 6549 //! This is a picture level command and should be issued only once, even for 6550 //! a multi-slices picture. There is only one DMV buffer for read (when 6551 //! processing a B-picture) and one for write (when processing a P-Picture). 6552 //! Each DMV record is 64 bits per MB, to store the top and bottom field 6553 //! motion vectors (32-bit MVx,y each). 6554 //! 6555 struct MFX_VC1_DIRECTMODE_STATE_CMD 6556 { 6557 union 6558 { 6559 //!< DWORD 0 6560 struct 6561 { 6562 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6563 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6564 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6565 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6566 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6567 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6568 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6569 }; 6570 uint32_t Value; 6571 } DW0; 6572 union 6573 { 6574 //!< DWORD 1 6575 struct 6576 { 6577 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 6578 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPicture : __CODEGEN_BITFIELD( 6, 31) ; //!< Direct MV Write Buffer Base Address for the Current Picture 6579 }; 6580 uint32_t Value; 6581 } DW1; 6582 union 6583 { 6584 //!< DWORD 2 6585 struct 6586 { 6587 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPicture4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Direct MV Write Buffer Base Address for the Current Picture [47:32] 6588 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 6589 }; 6590 uint32_t Value; 6591 } DW2; 6592 union 6593 { 6594 //!< DWORD 3 6595 struct 6596 { 6597 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 6598 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6599 uint32_t DirectMvWriteBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Direct MV Write Buffer - Memory Compression Enable 6600 uint32_t DirectMvWriteBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6601 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 6602 uint32_t DirectMvWriteBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6603 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 6604 }; 6605 uint32_t Value; 6606 } DW3; 6607 union 6608 { 6609 //!< DWORD 4 6610 struct 6611 { 6612 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 6613 uint32_t DirectMvReadBufferBaseAddressForTheReferencePicture : __CODEGEN_BITFIELD( 6, 31) ; //!< Direct MV Read Buffer Base Address for the Reference Picture 6614 }; 6615 uint32_t Value; 6616 } DW4; 6617 union 6618 { 6619 //!< DWORD 5 6620 struct 6621 { 6622 uint32_t DirectMvReadBufferBaseAddressForTheCurrentPicture4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Direct MV Read Buffer Base Address for the Current Picture [47:32] 6623 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 6624 }; 6625 uint32_t Value; 6626 } DW5; 6627 union 6628 { 6629 //!< DWORD 6 6630 struct 6631 { 6632 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 6633 uint32_t DirectMvReadBufferBaseAddressForTheCurrentPictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6634 uint32_t DirectMvReadBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Direct MV Read Buffer - Memory Compression Enable 6635 uint32_t DirectMvReadBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6636 uint32_t Reserved203 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 6637 uint32_t DirectMvReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6638 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 6639 }; 6640 uint32_t Value; 6641 } DW6; 6642 6643 //! \name Local enumerations 6644 6645 enum SUBOPCODE_B 6646 { 6647 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 6648 }; 6649 6650 enum SUBOPCODE_A 6651 { 6652 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 6653 }; 6654 6655 enum MEDIA_COMMAND_OPCODE 6656 { 6657 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 6658 }; 6659 6660 enum PIPELINE 6661 { 6662 PIPELINE_MFXVC1DIRECTMODESTATE = 2, //!< No additional details 6663 }; 6664 6665 enum COMMAND_TYPE 6666 { 6667 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6668 }; 6669 6670 //! \brief DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6671 //! \details 6672 //! This field controls the priority of arbitration used in the GAC/GAM 6673 //! pipeline for this surface. 6674 enum DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6675 { 6676 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 6677 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 6678 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 6679 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 6680 }; 6681 6682 //! \brief DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6683 //! \details 6684 //! Distinguishes Vertical from Horizontal compression. Please refer to 6685 //! vol1a 6686 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 6687 //! section for more details. 6688 enum DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6689 { 6690 DIRECT_MV_WRITE_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 6691 DIRECT_MV_WRITE_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 6692 }; 6693 6694 //! \brief DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6695 //! \details 6696 //! <b>For Media Surfaces:</b> 6697 //! This field specifies the tiled resource mode. 6698 enum DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6699 { 6700 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 6701 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 6702 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 6703 }; 6704 6705 //! \brief DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6706 //! \details 6707 //! This field controls the priority of arbitration used in the GAC/GAM 6708 //! pipeline for this surface. 6709 enum DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6710 { 6711 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 6712 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 6713 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 6714 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 6715 }; 6716 6717 //! \brief DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6718 //! \details 6719 //! Distinguishes Vertical from Horizontal compression. Please refer to 6720 //! vol1a 6721 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 6722 //! section for more details. 6723 enum DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6724 { 6725 DIRECT_MV_READ_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 6726 DIRECT_MV_READ_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 6727 }; 6728 6729 //! \brief DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6730 //! \details 6731 //! <b>For Media Surfaces:</b> 6732 //! This field specifies the tiled resource mode. 6733 enum DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6734 { 6735 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 6736 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 6737 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 6738 }; 6739 6740 //! \name Initializations 6741 6742 //! \brief Explicit member initialization function 6743 MFX_VC1_DIRECTMODE_STATE_CMD(); 6744 6745 static const size_t dwSize = 7; 6746 static const size_t byteSize = 28; 6747 }; 6748 6749 //! 6750 //! \brief MFD_VC1_BSD_OBJECT 6751 //! \details 6752 //! The MFD_VC1_BSD_OBJECT command is the only primitive command for the VC1 6753 //! Decoding Pipeline. The macroblock data portion of the bitstream is 6754 //! loaded as indirect data object.Before issuing a MFD_VC1_BSD_OBJECT 6755 //! command, all VC1 states of the MFD Engine need to be valid. Therefore 6756 //! the commands used to set these states need to have been issued prior to 6757 //! the issue of a MFD_VC1_BSD_OBJECT command.VC1 deblock filter kernel 6758 //! cross the slice boundary if in the last MB row of a slice, so need to 6759 //! know the last MB row of a slice to disable the edge mask. There is why 6760 //! VC1 BSD hardware need to know the end of MB address for the current 6761 //! slice. As such no more phantom slice is needed for VC1, as long as the 6762 //! driver will program both start MB address in the current slice and the 6763 //! start MB address of the next slice. As a result, we can also support 6764 //! multiple picture state commands in between slices. 6765 //! 6766 struct MFD_VC1_BSD_OBJECT_CMD 6767 { 6768 union 6769 { 6770 //!< DWORD 0 6771 struct 6772 { 6773 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6774 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6775 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6776 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6777 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6778 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6779 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6780 }; 6781 uint32_t Value; 6782 } DW0; 6783 union 6784 { 6785 //!< DWORD 1 6786 struct 6787 { 6788 uint32_t IndirectBsdDataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect BSD Data Length 6789 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6790 }; 6791 uint32_t Value; 6792 } DW1; 6793 union 6794 { 6795 //!< DWORD 2 6796 struct 6797 { 6798 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 6799 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 6800 }; 6801 uint32_t Value; 6802 } DW2; 6803 union 6804 { 6805 //!< DWORD 3 6806 struct 6807 { 6808 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< Next Slice Vertical Position 6809 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 6810 uint32_t SliceStartVerticalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Start Vertical Position 6811 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6812 }; 6813 uint32_t Value; 6814 } DW3; 6815 union 6816 { 6817 //!< DWORD 4 6818 struct 6819 { 6820 uint32_t FirstmbbitoffsetFirstMacroblockBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< FirstMbBitOffset (First Macroblock Bit Offset ) 6821 uint32_t Reserved131 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 6822 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD( 4, 4) ; //!< EMULATION_PREVENTION_BYTE_PRESENT 6823 uint32_t Reserved133 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 6824 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31) ; //!< First_MB_Byte_Offset of Slice Data or Slice Header 6825 }; 6826 uint32_t Value; 6827 } DW4; 6828 6829 //! \name Local enumerations 6830 6831 enum SUBOPCODE_B 6832 { 6833 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 6834 }; 6835 6836 enum SUBOPCODE_A 6837 { 6838 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6839 }; 6840 6841 enum MEDIA_COMMAND_OPCODE 6842 { 6843 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6844 }; 6845 6846 enum PIPELINE 6847 { 6848 PIPELINE_MFXMULTIDW = 2, //!< No additional details 6849 }; 6850 6851 enum COMMAND_TYPE 6852 { 6853 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6854 }; 6855 6856 enum EMULATION_PREVENTION_BYTE_PRESENT 6857 { 6858 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 6859 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 6860 }; 6861 6862 //! \name Initializations 6863 6864 //! \brief Explicit member initialization function 6865 MFD_VC1_BSD_OBJECT_CMD(); 6866 6867 static const size_t dwSize = 5; 6868 static const size_t byteSize = 20; 6869 }; 6870 6871 //! 6872 //! \brief MFX_JPEG_PIC_STATE 6873 //! \details 6874 //! 6875 //! 6876 struct MFX_JPEG_PIC_STATE_CMD 6877 { 6878 union 6879 { 6880 //!< DWORD 0 6881 struct 6882 { 6883 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6884 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6885 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6886 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6887 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6888 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6889 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6890 }; 6891 uint32_t Value; 6892 } DW0; 6893 union 6894 { 6895 //!< DWORD 1 6896 struct 6897 { 6898 uint32_t OutputMcuStructure : __CODEGEN_BITFIELD( 0, 2) ; //!< OUTPUT_MCU_STRUCTURE, Encoder Only 6899 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved, Encoder Only 6900 uint32_t InputSurfaceFormatYuv : __CODEGEN_BITFIELD( 8, 11) ; //!< INPUT_SURFACE_FORMAT_YUV, Encoder Only 6901 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 20) ; //!< Reserved, Encoder Only 6902 uint32_t PixelsInVerticalLastMcu : __CODEGEN_BITFIELD(21, 25) ; //!< Pixels In Vertical Last MCU, Encoder Only 6903 uint32_t PixelsInHorizontalLastMcu : __CODEGEN_BITFIELD(26, 30) ; //!< Pixels In Horizontal Last MCU, Encoder Only 6904 uint32_t Reserved63 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, Encoder Only 6905 } Obj0; 6906 struct 6907 { 6908 uint32_t InputFormatYuv : __CODEGEN_BITFIELD( 0, 2) ; //!< INPUT_FORMAT_YUV, Decoder Only 6909 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved, Decoder Only 6910 uint32_t Rotation : __CODEGEN_BITFIELD( 4, 5) ; //!< ROTATION, Decoder Only 6911 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved, Decoder Only 6912 uint32_t OutputFormatYuv : __CODEGEN_BITFIELD( 8, 11) ; //!< OUTPUT_FORMAT_YUV, Decoder Only 6913 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved, Decoder Only 6914 uint32_t AverageDownSampling : __CODEGEN_BITFIELD(16, 16) ; //!< AVERAGE_DOWN_SAMPLING, Decoder Only 6915 uint32_t VerticalDownSamplingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< VERTICAL_DOWN_SAMPLING_ENABLE, Decoder Only 6916 uint32_t HorizontalDownSamplingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< HORIZONTAL_DOWN_SAMPLING_ENABLE, Decoder Only 6917 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved, Decoder Only 6918 uint32_t VerticalUpSamplingEnable : __CODEGEN_BITFIELD(20, 20) ; //!< VERTICAL_UP_SAMPLING_ENABLE, Decoder Only 6919 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved, Decoder Only 6920 } Obj1; 6921 uint32_t Value; 6922 } DW1; 6923 union 6924 { 6925 //!< DWORD 2 6926 struct 6927 { 6928 uint32_t FrameWidthInBlocksMinus1 : __CODEGEN_BITFIELD( 0, 12) ; //!< Frame Width In Blocks Minus 1, Decoder Only 6929 uint32_t Reserved77 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, Decoder Only 6930 uint32_t FrameHeightInBlocksMinus1 : __CODEGEN_BITFIELD(16, 28) ; //!< Frame Height In Blocks Minus 1, Decoder Only 6931 uint32_t OutputPixelNormalize : __CODEGEN_BITFIELD(29, 29) ; //!< OUTPUT_PIXEL_NORMALIZE, Decoder Only 6932 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved, Decoder Only 6933 } Obj0; 6934 struct 6935 { 6936 uint32_t FrameWidthInBlksMinus1 : __CODEGEN_BITFIELD( 0, 12) ; //!< Frame Width In Blks Minus 1, Encoder Only 6937 uint32_t Roundingquant : __CODEGEN_BITFIELD(13, 15) ; //!< ROUNDINGQUANT, Encoder Only 6938 uint32_t FrameHeightInBlksMinus1 : __CODEGEN_BITFIELD(16, 28) ; //!< Frame Height In Blks Minus 1, Encoder Only 6939 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved, Encoder Only 6940 } Obj1; 6941 uint32_t Value; 6942 } DW2; 6943 6944 //! \name Local enumerations 6945 6946 enum SUBOPCODE_B 6947 { 6948 SUBOPCODE_B_MEDIA = 0, //!< No additional details 6949 }; 6950 6951 enum SUBOPCODE_A 6952 { 6953 SUBOPCODE_A_COMMON = 0, //!< No additional details 6954 }; 6955 6956 enum MEDIA_COMMAND_OPCODE 6957 { 6958 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 6959 }; 6960 6961 enum PIPELINE 6962 { 6963 PIPELINE_MFXMULTIDW = 2, //!< No additional details 6964 }; 6965 6966 enum COMMAND_TYPE 6967 { 6968 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6969 }; 6970 6971 //! \brief OUTPUT_MCU_STRUCTURE 6972 //! \details 6973 //! <p></p> 6974 //! Output MCU Structure(<b>OutputMcuStructure</b>) should be set 6975 //! accordingly for each Input Surface Format 6976 //! YUV(<b>InputSurfaceFormatYUV</b>): 6977 //! <ul> 6978 //! <li>If <b>InputSurfaceFormatYUV</b> is set to NV12, 6979 //! <b>OutputMCUStructure</b> is set to YUV420.</li> 6980 //! <li>If <b>InputSurfaceFormatYUV</b> is set to UYVY or YUY2, 6981 //! <b>OutputMCUStructure</b> is set to YUV422H_2Y.</li> 6982 //! <li>If <b>InputSurfaceFormatYUV</b> is set to Y8, 6983 //! <b>OutputMCuStructure</b> is set to YUV400.</li> 6984 //! <li>If <b>InputSurfaceFormatYUV</b> is set to RGB (or GBR, BGR, 6985 //! YUV), <b>OutputMCuStructure</b> is set to RGB.</li> 6986 //! <li>If <b>InputSurfaceFormatYUV</b> is set to RGB, the order of 6987 //! encoded blocks in MCU will be same as the order of input image 6988 //! components. 6989 //! If the order of input image components is RGB (or GBR, BGR, YUV), 6990 //! then the order of blocks will be RGB (or GBR, BGR, YUV 6991 //! respectively).</li> 6992 //! </ul> 6993 //! <p></p> 6994 enum OUTPUT_MCU_STRUCTURE 6995 { 6996 OUTPUT_MCU_STRUCTURE_YUV_400 = 0, //!< Grayscale Image 6997 OUTPUT_MCU_STRUCTURE_YUV_420 = 1, //!< Both horizontally and vertically chroma 2:1 subsampled 6998 OUTPUT_MCU_STRUCTURE_YUV_422H2Y = 2, //!< Horizontally chroma 2:1 subsampled - horizontal 2 Y-blocks, 1 U and 1 V block 6999 OUTPUT_MCU_STRUCTURE_RGB = 3, //!< RGB or YUV444: No subsample 7000 OUTPUT_MCU_STRUCTURE_UNNAMED_4 = 4, //!< No additional details 7001 OUTPUT_MCU_STRUCTURE_UNNAMED5 = 5, //!< No additional details 7002 OUTPUT_MCU_STRUCTURE_UNNAMED6 = 6, //!< No additional details 7003 OUTPUT_MCU_STRUCTURE_UNNAMED7 = 7, //!< No additional details 7004 }; 7005 7006 enum INPUT_FORMAT_YUV 7007 { 7008 INPUT_FORMAT_YUV_UNNAMED0 = 0, //!< YUV400 (grayscale image) 7009 INPUT_FORMAT_YUV_UNNAMED1 = 1, //!< YUV420 7010 INPUT_FORMAT_YUV_UNNAMED2 = 2, //!< YUV422H_2Y (Horizontally chroma 2:1 subsampled) - horizontal 2 Y-block, 1U and 1V 7011 INPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUV444 7012 INPUT_FORMAT_YUV_UNNAMED_4 = 4, //!< YUV411 7013 INPUT_FORMAT_YUV_UNNAMED5 = 5, //!< YUV422V_2Y (Vertically chroma 2:1 subsampled) - vertical 2 Y-blocks, 1U and 1V 7014 INPUT_FORMAT_YUV_UNNAMED6 = 6, //!< YUV422H_4Y - 2x2 Y-blocks, vertical 2U and 2V 7015 INPUT_FORMAT_YUV_UNNAMED7 = 7, //!< YUV422V_4Y - 2x2 Y-blocks, horizontal 2U and 2V 7016 }; 7017 7018 //! \brief ROTATION 7019 //! \details 7020 //! Rotation can be set to 01b, 10b, or 11b when OutputFormatYUV is set to 7021 //! 0000b. For other OutputFormatYUV, Rotation is not allowed. 7022 enum ROTATION 7023 { 7024 ROTATION_UNNAMED0 = 0, //!< no rotation 7025 ROTATION_UNNAMED1 = 1, //!< rotate clockwise 90 degree 7026 ROTATION_UNNAMED2 = 2, //!< rotate counter-clockwise 90 degree (same as rotating 270 degree clockwise) 7027 ROTATION_UNNAMED3 = 3, //!< rotate 180 degree (NOT the same as flipped on the x-axis) 7028 }; 7029 7030 //! \brief OUTPUT_FORMAT_YUV 7031 //! \details 7032 //! This field specifies the surface format to write the decoded JPEG 7033 //! image.Note that any non-interleaved JPEG input should be set to "0000". 7034 //! For the interleaved input Scan data, it can be set either "0000" or the 7035 //! corresponding format. 7036 enum OUTPUT_FORMAT_YUV 7037 { 7038 OUTPUT_FORMAT_YUV_UNNAMED0 = 0, //!< 3 separate plane for Y, U, and V respectively 7039 OUTPUT_FORMAT_YUV_UNNAMED1 = 1, //!< NV12 for chroma 4:2:0 7040 OUTPUT_FORMAT_YUV_UNNAMED2 = 2, //!< UYVY for chroma 4:2:2 7041 OUTPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUY2 for chroma 4:2:2 7042 }; 7043 7044 //! \brief INPUT_SURFACE_FORMAT_YUV 7045 //! \details 7046 //! This field specifies the surface format to read a YUV image data 7047 enum INPUT_SURFACE_FORMAT_YUV 7048 { 7049 INPUT_SURFACE_FORMAT_YUV_UNNAMED0 = 0, //!< Reserved 7050 INPUT_SURFACE_FORMAT_YUV_NV12 = 1, //!< NV12 for chroma 4:2:0 7051 INPUT_SURFACE_FORMAT_YUV_UYVY = 2, //!< UYVY for chroma 4:2:2 7052 INPUT_SURFACE_FORMAT_YUV_YUY2 = 3, //!< YUY2 for chroma 4:2:2 7053 INPUT_SURFACE_FORMAT_YUV_Y8 = 4, //!< Y8 for chroma400 Y-only image 7054 INPUT_SURFACE_FORMAT_YUV_RGB = 5, //!< RGB or YUV for chroma 4:4:4 7055 }; 7056 7057 //! \brief AVERAGE_DOWN_SAMPLING 7058 //! \details 7059 //! This flag is used to select a down-sampling method when 7060 //! <b>VertDownSamplingEnb</b> or <b>HoriDownSamplingEnb</b> is set to 1. 7061 enum AVERAGE_DOWN_SAMPLING 7062 { 7063 AVERAGE_DOWN_SAMPLING_UNNAMED0 = 0, //!< Drop every other line (or column) pixels 7064 AVERAGE_DOWN_SAMPLING_UNNAMED1 = 1, //!< Average neighboring two pixels 7065 }; 7066 7067 //! \brief VERTICAL_DOWN_SAMPLING_ENABLE 7068 //! \details 7069 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 7070 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 7071 //! enable this flag, the input should be interleaved Scan, 7072 //! <b>InputFormatYUV</b> should be set to YUV422H_2Y or YUV422H_4Y, and 7073 //! <b>OutputFormatYUV</b> should be set to NV12. 7074 enum VERTICAL_DOWN_SAMPLING_ENABLE 7075 { 7076 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 7077 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical down-sampling 7078 }; 7079 7080 //! \brief HORIZONTAL_DOWN_SAMPLING_ENABLE 7081 //! \details 7082 //! Only applied to chroma blocks. This flag is used for 2:1 horizontal 7083 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 7084 //! enable this flag, the input should be interleaved Scan, 7085 //! <b>InputFormatYUV</b> should be set to YUV422V_2Y or YUV422V_4Y, and 7086 //! <b>OutputFormatYUV</b> should be set to NV12. 7087 enum HORIZONTAL_DOWN_SAMPLING_ENABLE 7088 { 7089 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 7090 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 horizonatl down-sampling 7091 }; 7092 7093 //! \brief VERTICAL_UP_SAMPLING_ENABLE 7094 //! \details 7095 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 7096 //! up-sampling for chroma 420 and outputting chroma422 YUY2 or UYVY format. 7097 //! To enable this flag, the input should be interleaved Scan, 7098 //! <b>InputFormatYUV</b> should be set to YUV420, and 7099 //! <b>OutputFormatYUV</b> should be set to YUY2 or UYVY. 7100 enum VERTICAL_UP_SAMPLING_ENABLE 7101 { 7102 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no up-sampling 7103 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical up-sampling 7104 }; 7105 7106 //! \brief ROUNDINGQUANT 7107 //! \details 7108 //! Rounding value applied to quantization output 7109 enum ROUNDINGQUANT 7110 { 7111 ROUNDINGQUANT_UNNAMED0 = 0, //!< 1/2 7112 ROUNDINGQUANT_UNNAMED1 = 1, //!< (1/2 - 1/128) 7113 ROUNDINGQUANT_UNNAMED2 = 2, //!< (1/2 + 1/128) 7114 ROUNDINGQUANT_UNNAMED3 = 3, //!< (1/2 - 1/64) 7115 ROUNDINGQUANT_UNNAMED_4 = 4, //!< (1/2 + 1/64) 7116 ROUNDINGQUANT_UNNAMED5 = 5, //!< (1/2 - 1/32) 7117 ROUNDINGQUANT_UNNAMED6 = 6, //!< (1/2 - 1/16) 7118 ROUNDINGQUANT_UNNAMED7 = 7, //!< (1/2 - 1/8) 7119 }; 7120 7121 //! \brief OUTPUT_PIXEL_NORMALIZE 7122 //! \details 7123 //! JPEG decoded output pixels for Y and U/V in order to adjust display YUV 7124 //! range. 7125 enum OUTPUT_PIXEL_NORMALIZE 7126 { 7127 OUTPUT_PIXEL_NORMALIZE_UNNAMED0 = 0, //!< No Normalization 7128 OUTPUT_PIXEL_NORMALIZE_UNNAMED1 = 1, //!< Normalize output pixels from [0,255] to [16,235] 7129 }; 7130 7131 //! \name Initializations 7132 7133 //! \brief Explicit member initialization function 7134 MFX_JPEG_PIC_STATE_CMD(); 7135 7136 static const size_t dwSize = 3; 7137 static const size_t byteSize = 12; 7138 }; 7139 7140 //! 7141 //! \brief MFC_JPEG_HUFF_TABLE_STATE 7142 //! \details 7143 //! This Huffman table commands contains both DC and AC tables for either 7144 //! luma or chroma. Once a Huffman table has been defined for a particular 7145 //! destination, it replaces the previous tables stored in that destination 7146 //! and shall be used in the remaining Scans of the current image. Two 7147 //! Huffman tables for luma and chroma will be sent to H/W, and chroma table 7148 //! is used for both U and V. 7149 //! 7150 struct MFC_JPEG_HUFF_TABLE_STATE_CMD 7151 { 7152 union 7153 { 7154 //!< DWORD 0 7155 struct 7156 { 7157 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7158 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7159 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7160 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7161 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7162 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7163 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7164 }; 7165 uint32_t Value; 7166 } DW0; 7167 union 7168 { 7169 //!< DWORD 1 7170 struct 7171 { 7172 uint32_t HuffTableId : __CODEGEN_BITFIELD( 0, 0) ; //!< HUFF_TABLE_ID 7173 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 7174 }; 7175 uint32_t Value; 7176 } DW1; 7177 7178 uint32_t DcTable[12]; //!< DC_TABLE 7179 7180 uint32_t AcTable[162]; //!< AC_TABLE 7181 7182 //! \name Local enumerations 7183 7184 enum SUBOPCODE_B 7185 { 7186 SUBOPCODE_B_MEDIA = 3, //!< No additional details 7187 }; 7188 7189 enum SUBOPCODE_A 7190 { 7191 SUBOPCODE_A_COMMON = 2, //!< No additional details 7192 }; 7193 7194 enum MEDIA_COMMAND_OPCODE 7195 { 7196 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 7197 }; 7198 7199 enum PIPELINE 7200 { 7201 PIPELINE_MFCJPEGHUFFTABLESTATE = 2, //!< No additional details 7202 }; 7203 7204 enum COMMAND_TYPE 7205 { 7206 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7207 }; 7208 7209 //! \brief HUFF_TABLE_ID 7210 //! \details 7211 //! Huffman table destination identifier will specify one of two 7212 //! destinations at the encoder into which the Huffman table must be stored. 7213 enum HUFF_TABLE_ID 7214 { 7215 HUFF_TABLE_ID_UNNAMED0 = 0, //!< Huffman table 0 7216 HUFF_TABLE_ID_UNNAMED1 = 1, //!< Huffman table 1 7217 }; 7218 7219 //! \name Initializations 7220 7221 //! \brief Explicit member initialization function 7222 MFC_JPEG_HUFF_TABLE_STATE_CMD(); 7223 7224 static const size_t dwSize = 176; 7225 static const size_t byteSize = 704; 7226 }; 7227 7228 //! 7229 //! \brief MFD_JPEG_BSD_OBJECT 7230 //! \details 7231 //! 7232 //! 7233 struct MFD_JPEG_BSD_OBJECT_CMD 7234 { 7235 union 7236 { 7237 //!< DWORD 0 7238 struct 7239 { 7240 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7241 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7242 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7243 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7244 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7245 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7246 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7247 }; 7248 uint32_t Value; 7249 } DW0; 7250 union 7251 { 7252 //!< DWORD 1 7253 struct 7254 { 7255 uint32_t IndirectDataLength ; //!< Indirect Data Length 7256 }; 7257 uint32_t Value; 7258 } DW1; 7259 union 7260 { 7261 //!< DWORD 2 7262 struct 7263 { 7264 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 7265 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 7266 }; 7267 uint32_t Value; 7268 } DW2; 7269 union 7270 { 7271 //!< DWORD 3 7272 struct 7273 { 7274 uint32_t ScanVerticalPosition : __CODEGEN_BITFIELD( 0, 12) ; //!< Scan Vertical Position 7275 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 7276 uint32_t ScanHorizontalPosition : __CODEGEN_BITFIELD(16, 28) ; //!< Scan Horizontal Position 7277 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 7278 }; 7279 uint32_t Value; 7280 } DW3; 7281 union 7282 { 7283 //!< DWORD 4 7284 struct 7285 { 7286 uint32_t McuCount : __CODEGEN_BITFIELD( 0, 25) ; //!< MCU Count 7287 uint32_t Reserved154 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 7288 uint32_t ScanComponents : __CODEGEN_BITFIELD(27, 29) ; //!< Scan Components 7289 uint32_t Interleaved : __CODEGEN_BITFIELD(30, 30) ; //!< INTERLEAVED 7290 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 7291 }; 7292 uint32_t Value; 7293 } DW4; 7294 union 7295 { 7296 //!< DWORD 5 7297 struct 7298 { 7299 uint32_t Restartinterval16Bit : __CODEGEN_BITFIELD( 0, 15) ; //!< RestartInterval(16 bit) 7300 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 7301 }; 7302 uint32_t Value; 7303 } DW5; 7304 7305 //! \name Local enumerations 7306 7307 enum SUBOPCODE_B 7308 { 7309 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 7310 }; 7311 7312 enum SUBOPCODE_A 7313 { 7314 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 7315 }; 7316 7317 enum MEDIA_COMMAND_OPCODE 7318 { 7319 MEDIA_COMMAND_OPCODE_JPEGDEC = 7, //!< No additional details 7320 }; 7321 7322 enum PIPELINE 7323 { 7324 PIPELINE_MFDJPEGBSDOBJECT = 2, //!< No additional details 7325 }; 7326 7327 enum COMMAND_TYPE 7328 { 7329 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7330 }; 7331 7332 enum INTERLEAVED 7333 { 7334 INTERLEAVED_NON_INTERLEAVED = 0, //!< one component in the Scan 7335 INTERLEAVED_INTERLEAVED = 1, //!< multiple components in the Scan 7336 }; 7337 7338 //! \name Initializations 7339 7340 //! \brief Explicit member initialization function 7341 MFD_JPEG_BSD_OBJECT_CMD(); 7342 7343 static const size_t dwSize = 6; 7344 static const size_t byteSize = 24; 7345 }; 7346 7347 //! 7348 //! \brief MFC_JPEG_SCAN_OBJECT 7349 //! \details 7350 //! Encoder Only 7351 //! 7352 struct MFC_JPEG_SCAN_OBJECT_CMD 7353 { 7354 union 7355 { 7356 //!< DWORD 0 7357 struct 7358 { 7359 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7360 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7361 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7362 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7363 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7364 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7365 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7366 }; 7367 uint32_t Value; 7368 } DW0; 7369 union 7370 { 7371 //!< DWORD 1 7372 struct 7373 { 7374 uint32_t McuCount : __CODEGEN_BITFIELD( 0, 25) ; //!< MCU Count 7375 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 7376 }; 7377 uint32_t Value; 7378 } DW1; 7379 union 7380 { 7381 //!< DWORD 2 7382 struct 7383 { 7384 uint32_t RestartInterval : __CODEGEN_BITFIELD( 0, 15) ; //!< Restart Interval 7385 uint32_t IsLastScan : __CODEGEN_BITFIELD(16, 16) ; //!< IS_LAST_SCAN 7386 uint32_t HeadPresentFlag : __CODEGEN_BITFIELD(17, 17) ; //!< HEAD_PRESENT_FLAG 7387 uint32_t HuffmanDcTable : __CODEGEN_BITFIELD(18, 20) ; //!< HUFFMAN_DC_TABLE 7388 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 7389 uint32_t HuffmanAcTable : __CODEGEN_BITFIELD(22, 24) ; //!< HUFFMAN_AC_TABLE 7390 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 7391 }; 7392 uint32_t Value; 7393 } DW2; 7394 7395 //! \name Local enumerations 7396 7397 enum SUBOPCODE_B 7398 { 7399 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 7400 }; 7401 7402 enum SUBOPCODE_A 7403 { 7404 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 7405 }; 7406 7407 enum MEDIA_COMMAND_OPCODE 7408 { 7409 MEDIA_COMMAND_OPCODE_JPEGENC = 7, //!< No additional details 7410 }; 7411 7412 enum PIPELINE 7413 { 7414 PIPELINE_MFCJPEGSCANOBJECT = 2, //!< No additional details 7415 }; 7416 7417 enum COMMAND_TYPE 7418 { 7419 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7420 }; 7421 7422 //! \brief IS_LAST_SCAN 7423 //! \details 7424 //! If this flag is set, then HW will insert EOI (0xFFD9) to the end of Scan 7425 //! encoded bitstream. 7426 enum IS_LAST_SCAN 7427 { 7428 IS_LAST_SCAN_UNNAMED0 = 0, //!< Not the last Scan. 7429 IS_LAST_SCAN_UNNAMED1 = 1, //!< Indicates that the current Scan is the last one. 7430 }; 7431 7432 //! \brief HEAD_PRESENT_FLAG 7433 //! \details 7434 //! If this flag is set to 0, then no MFC_JPEG_PAK_INSERT_OBJECT commands 7435 //! will be sent. 7436 //! If this flag is set to 1, then one or more 7437 //! MFC_JPEG_PAK_INSERT_OBJECT commands will be sent after 7438 //! MFC_JPEG_SCAN_OBJECT command. 7439 enum HEAD_PRESENT_FLAG 7440 { 7441 HEAD_PRESENT_FLAG_UNNAMED0 = 0, //!< No insertion into the output bitstream buffer before Scan encoded bitstream 7442 HEAD_PRESENT_FLAG_UNNAMED1 = 1, //!< Headers, tables, App data insertion into the output bitstream buffer. HW will insert the insertion data before the Scan encoded bitstream. 7443 }; 7444 7445 //! \brief HUFFMAN_DC_TABLE 7446 //! \details 7447 //! DC Huffman table destination selector specifies one of two possible DC 7448 //! table destinations for each Y, U, V, or R, G, B. 7449 //! The DC Huffman tables shall have been loaded in destination 0 and 1 7450 //! by the time of issuing MFC_JPEG_HUFF_TABLE_STATE Command. 7451 enum HUFFMAN_DC_TABLE 7452 { 7453 HUFFMAN_DC_TABLE_BIT20V0 = 0, //!< The third image component must use the DC table 0. 7454 HUFFMAN_DC_TABLE_BIT19U0 = 0, //!< The second image component must use the DC table 0. 7455 HUFFMAN_DC_TABLE_BIT18Y0 = 0, //!< The first image component must use the DC table 0. 7456 HUFFMAN_DC_TABLE_BIT18Y1 = 1, //!< The first image component must use the DC table 1. 7457 HUFFMAN_DC_TABLE_BIT19U1 = 2, //!< The second image component must use the DC table 1. 7458 HUFFMAN_DC_TABLE_BIT20V1 = 4, //!< The third image component must use the DC table 1. 7459 }; 7460 7461 //! \brief HUFFMAN_AC_TABLE 7462 //! \details 7463 //! AC Huffman table destination selector specifies one of two possible AC 7464 //! table destinations for each Y, U, V, or R, G, B. 7465 //! The AC Huffman tables must have been loaded in destination 0 and 1 7466 //! by the time of issuing MFC_JPEG_HUFF_TABLE_STATE Command. 7467 enum HUFFMAN_AC_TABLE 7468 { 7469 HUFFMAN_AC_TABLE_BIT2_4V0 = 0, //!< The third image component must use the AC table 0. 7470 HUFFMAN_AC_TABLE_BIT23U0 = 0, //!< The second image component must use the AC table 0. 7471 HUFFMAN_AC_TABLE_BIT22Y0 = 0, //!< The first image component must use the AC table 0. 7472 HUFFMAN_AC_TABLE_BIT22Y1 = 1, //!< The first image component must use the AC table 1. 7473 HUFFMAN_AC_TABLE_BIT23U1 = 2, //!< The second image component must use the AC table 1. 7474 HUFFMAN_AC_TABLE_BIT2_4V1 = 4, //!< The third image component must use the AC table 1. 7475 }; 7476 7477 //! \name Initializations 7478 7479 //! \brief Explicit member initialization function 7480 MFC_JPEG_SCAN_OBJECT_CMD(); 7481 7482 static const size_t dwSize = 3; 7483 static const size_t byteSize = 12; 7484 }; 7485 7486 //! 7487 //! \brief MFX_VP8_Encoder_CFG 7488 //! \details 7489 //! This must be the very first command to issue after the surface state, 7490 //! the pipe select and base address setting commands and must be issued 7491 //! before MFX_VP8_PIC_STATE. 7492 //! 7493 struct MFX_VP8_Encoder_CFG_CMD 7494 { 7495 union 7496 { 7497 //!< DWORD 0 7498 struct 7499 { 7500 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7501 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7502 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 7503 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 7504 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7505 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7506 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7507 }; 7508 uint32_t Value; 7509 } DW0; 7510 union 7511 { 7512 //!< DWORD 1 7513 struct 7514 { 7515 uint32_t PerformanceCounterEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Performance Counter Enable 7516 uint32_t FinalBitstreamOutputDisable : __CODEGEN_BITFIELD( 1, 1) ; //!< Final Bitstream Output Disable 7517 uint32_t TokenStatisticsOutputEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Output Enable 7518 uint32_t BitstreamStatisticsOutputEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< Bitstream Statistics Output Enable 7519 uint32_t UpdateSegmentFeatureDataFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< Update Segment Feature Data Flag 7520 uint32_t SkipFinalBitstreamWhenOverUnderFlow : __CODEGEN_BITFIELD( 5, 5) ; //!< Skip Final Bitstream when Over / Under flow 7521 uint32_t RateControlInitialPass : __CODEGEN_BITFIELD( 6, 6) ; //!< RATE_CONTROL_INITIAL_PASS 7522 uint32_t PerSegmentDeltaQindexLoopfilterDisable : __CODEGEN_BITFIELD( 7, 7) ; //!< Per Segment Delta Qindex / LoopFilter Disable 7523 uint32_t FinerBrcEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Finer BRC Enable 7524 uint32_t CompressedBitstreamOutputDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Compressed Bitstream Output Disable 7525 uint32_t VbspunitpowerclockGatingDisable : __CODEGEN_BITFIELD(10, 10) ; //!< VBSPunitPowerClock Gating Disable 7526 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 7527 }; 7528 uint32_t Value; 7529 } DW1; 7530 union 7531 { 7532 //!< DWORD 2 7533 struct 7534 { 7535 uint32_t MaxFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD( 0, 0) ; //!< MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7536 uint32_t MinFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD( 1, 1) ; //!< MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7537 uint32_t MaxInterMbBitCountCheckEnableMask : __CODEGEN_BITFIELD( 2, 2) ; //!< Max Inter MB Bit Count Check Enable Mask 7538 uint32_t MaxIntraMbBitCountCheckEnableMask : __CODEGEN_BITFIELD( 3, 3) ; //!< Max Intra MB Bit Count Check Enable Mask 7539 uint32_t IntermediateBitBufferOverrunEnableMask : __CODEGEN_BITFIELD( 4, 4) ; //!< Intermediate Bit Buffer Overrun Enable Mask 7540 uint32_t FinalBistreamBufferOverrunEnableMask : __CODEGEN_BITFIELD( 5, 5) ; //!< Final Bistream Buffer Overrun Enable Mask 7541 uint32_t QindexClampHighMaskForUnderflow : __CODEGEN_BITFIELD( 6, 6) ; //!< Qindex_Clamp_High_mask for underflow 7542 uint32_t QindexClampHighMaskForOverflow : __CODEGEN_BITFIELD( 7, 7) ; //!< Qindex_Clamp_High_mask for overflow 7543 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 7544 }; 7545 uint32_t Value; 7546 } DW2; 7547 union 7548 { 7549 //!< DWORD 3 7550 struct 7551 { 7552 uint32_t MaxInterMbBitCount : __CODEGEN_BITFIELD( 0, 11) ; //!< Max Inter MB bit count 7553 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7554 uint32_t MaxIntraMbBitCountLimit : __CODEGEN_BITFIELD(16, 27) ; //!< Max Intra MB Bit Count Limit 7555 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 7556 }; 7557 uint32_t Value; 7558 } DW3; 7559 union 7560 { 7561 //!< DWORD 4 7562 struct 7563 { 7564 uint32_t FrameBitRateMax : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Bit Rate Max 7565 uint32_t FrameBitRateMaxUnit : __CODEGEN_BITFIELD(14, 14) ; //!< FRAME_BIT_RATE_MAX_UNIT 7566 uint32_t FrameBitrateMaxUnitMode : __CODEGEN_BITFIELD(15, 15) ; //!< FRAME_BITRATE_MAX_UNIT_MODE 7567 uint32_t FrameBitRateMin : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Bit Rate Min 7568 uint32_t FrameBitRateMinUnit : __CODEGEN_BITFIELD(30, 30) ; //!< FRAME_BIT_RATE_MIN_UNIT 7569 uint32_t FrameBitrateMinUnitMode : __CODEGEN_BITFIELD(31, 31) ; //!< FRAME_BITRATE_MIN_UNIT_MODE 7570 }; 7571 uint32_t Value; 7572 } DW4; 7573 union 7574 { 7575 //!< DWORD 5 7576 struct 7577 { 7578 uint32_t FrameDeltaQindexMax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta QIndex Max [0] 7579 uint32_t FrameDeltaQindexMax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta QIndex Max[1] 7580 uint32_t FrameDeltaqIndexMax2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame DeltaQ Index Max[2] 7581 uint32_t FrameDeltaQindexMax3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta QIndex Max[3] 7582 }; 7583 uint32_t Value; 7584 } DW5; 7585 union 7586 { 7587 //!< DWORD 6 7588 struct 7589 { 7590 uint32_t FrameDeltaQindexMin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta QIndex Min[0] 7591 uint32_t FrameDeltaQindexMin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta QIndex Min[1] 7592 uint32_t FrameDeltaQindexMin2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta QIndex Min[2] 7593 uint32_t FrameDeltaQindexMin3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta QIndex Min[3] 7594 }; 7595 uint32_t Value; 7596 } DW6; 7597 union 7598 { 7599 //!< DWORD 7 7600 struct 7601 { 7602 uint32_t PerSegmentFrameDeltaQindexMax1 ; //!< Per Segment Frame Delta QIndex Max[1] 7603 }; 7604 uint32_t Value; 7605 } DW7; 7606 union 7607 { 7608 //!< DWORD 8 7609 struct 7610 { 7611 uint32_t PerSegmentFrameDeltaQindexMin1 ; //!< Per Segment Frame Delta QIndex Min[1] 7612 }; 7613 uint32_t Value; 7614 } DW8; 7615 union 7616 { 7617 //!< DWORD 9 7618 struct 7619 { 7620 uint32_t PerSegmentFrameDeltaQindexMax2 ; //!< Per Segment Frame Delta QIndex Max[2] 7621 }; 7622 uint32_t Value; 7623 } DW9; 7624 union 7625 { 7626 //!< DWORD 10 7627 struct 7628 { 7629 uint32_t PerSegmentFrameDeltaQindexMin2 ; //!< Per Segment Frame Delta QIndex Min[2] 7630 }; 7631 uint32_t Value; 7632 } DW10; 7633 union 7634 { 7635 //!< DWORD 11 7636 struct 7637 { 7638 uint32_t PerSegmentFrameDeltaQindexMax3 ; //!< Per Segment Frame Delta QIndex Max[3] 7639 }; 7640 uint32_t Value; 7641 } DW11; 7642 union 7643 { 7644 //!< DWORD 12 7645 struct 7646 { 7647 uint32_t PerSegmentFrameDeltaQindexMin3 ; //!< Per Segment Frame Delta QIndex Min[3] 7648 }; 7649 uint32_t Value; 7650 } DW12; 7651 union 7652 { 7653 //!< DWORD 13 7654 struct 7655 { 7656 uint32_t FrameDeltaLoopFilterMax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta Loop Filter Max[0] 7657 uint32_t FramEdeltaLoopFilterMax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Fram eDelta Loop Filter Max[1] 7658 uint32_t FrameDeltaLoopFilterMax2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta Loop Filter Max[2] 7659 uint32_t FrameDeltaLoopFilterMax3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta Loop Filter Max[3] 7660 }; 7661 uint32_t Value; 7662 } DW13; 7663 union 7664 { 7665 //!< DWORD 14 7666 struct 7667 { 7668 uint32_t FrameDeltaLoopFilterMin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta Loop Filter Min[0] 7669 uint32_t FrameDeltaLoopFilterMin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta Loop Filter Min[1] 7670 uint32_t FrameDeltaLoopFilterMin2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta Loop Filter Min[2] 7671 uint32_t FrameDeltaLoopFilterMin3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta Loop Filter Min[3] 7672 }; 7673 uint32_t Value; 7674 } DW14; 7675 union 7676 { 7677 //!< DWORD 15 7678 struct 7679 { 7680 uint32_t PerSegmentFrameDeltaLoopfilterMax1 ; //!< Per Segment Frame Delta LoopFilter Max[1] 7681 }; 7682 uint32_t Value; 7683 } DW15; 7684 union 7685 { 7686 //!< DWORD 16 7687 struct 7688 { 7689 uint32_t PerSegmentFrameDeltaLoopfilterMin1 ; //!< Per Segment Frame Delta LoopFilter Min[1] 7690 }; 7691 uint32_t Value; 7692 } DW16; 7693 union 7694 { 7695 //!< DWORD 17 7696 struct 7697 { 7698 uint32_t PerSegmentFrameDeltaLoopfilterMax2 ; //!< Per Segment Frame Delta LoopFilter Max[2] 7699 }; 7700 uint32_t Value; 7701 } DW17; 7702 union 7703 { 7704 //!< DWORD 18 7705 struct 7706 { 7707 uint32_t PerSegmentFrameDeltaLoopfilterMin2 ; //!< Per Segment Frame Delta LoopFilter Min[2] 7708 }; 7709 uint32_t Value; 7710 } DW18; 7711 union 7712 { 7713 //!< DWORD 19 7714 struct 7715 { 7716 uint32_t PerSegmentFrameDeltaLoopfilterMax3 ; //!< Per Segment Frame Delta LoopFilter Max[3] 7717 }; 7718 uint32_t Value; 7719 } DW19; 7720 union 7721 { 7722 //!< DWORD 20 7723 struct 7724 { 7725 uint32_t PerSegmentFrameDeltaLoopfilterMin3 ; //!< Per Segment Frame Delta LoopFilter Min[3] 7726 }; 7727 uint32_t Value; 7728 } DW20; 7729 union 7730 { 7731 //!< DWORD 21 7732 struct 7733 { 7734 uint32_t FrameBitRateMaxDelta : __CODEGEN_BITFIELD( 0, 14) ; //!< Frame Bit Rate Max Delta 7735 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 7736 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(16, 30) ; //!< FrameBitRateMinDelta 7737 uint32_t Reserved703 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 7738 }; 7739 uint32_t Value; 7740 } DW21; 7741 union 7742 { 7743 //!< DWORD 22 7744 struct 7745 { 7746 uint32_t MinFrameWsize : __CODEGEN_BITFIELD( 0, 15) ; //!< Min Frame WSize 7747 uint32_t MinFrameWsizeUnit : __CODEGEN_BITFIELD(16, 17) ; //!< MIN_FRAME_WSIZE_UNIT 7748 uint32_t Reserved722 : __CODEGEN_BITFIELD(18, 19) ; //!< Reserved 7749 uint32_t BitstreamFormatVersion : __CODEGEN_BITFIELD(20, 22) ; //!< Bitstream Format Version 7750 uint32_t ShowFrame : __CODEGEN_BITFIELD(23, 23) ; //!< Show Frame 7751 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 7752 }; 7753 uint32_t Value; 7754 } DW22; 7755 union 7756 { 7757 //!< DWORD 23 7758 struct 7759 { 7760 uint32_t HorizontalSizeCode : __CODEGEN_BITFIELD( 0, 15) ; //!< Horizontal_Size_Code 7761 uint32_t VerticalSizeCode : __CODEGEN_BITFIELD(16, 31) ; //!< Vertical_Size_Code 7762 }; 7763 uint32_t Value; 7764 } DW23; 7765 union 7766 { 7767 //!< DWORD 24 7768 struct 7769 { 7770 uint32_t FrameHeaderBitCount ; //!< Frame Header Bit Count 7771 }; 7772 uint32_t Value; 7773 } DW24; 7774 union 7775 { 7776 //!< DWORD 25 7777 struct 7778 { 7779 uint32_t FrameHeaderBinBufferQindexUpdatePointer ; //!< Frame Header Bin Buffer Qindex Update Pointer 7780 }; 7781 uint32_t Value; 7782 } DW25; 7783 union 7784 { 7785 //!< DWORD 26 7786 struct 7787 { 7788 uint32_t FrameHeaderBinBufferLoopfilterUpdatePointer ; //!< Frame Header Bin Buffer LoopFilter Update Pointer 7789 }; 7790 uint32_t Value; 7791 } DW26; 7792 union 7793 { 7794 //!< DWORD 27 7795 struct 7796 { 7797 uint32_t FrameHeaderBinBufferTokenUpdatePointer ; //!< Frame Header Bin Buffer Token Update Pointer 7798 }; 7799 uint32_t Value; 7800 } DW27; 7801 union 7802 { 7803 //!< DWORD 28 7804 struct 7805 { 7806 uint32_t FrameHeaderBinBufferMvupdatePointer ; //!< Frame Header Bin Buffer MVUpdate Pointer 7807 }; 7808 uint32_t Value; 7809 } DW28; 7810 union 7811 { 7812 //!< DWORD 29 7813 struct 7814 { 7815 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 7816 uint32_t Cv1 : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 7817 uint32_t Cv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 7818 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 7819 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 7820 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 7821 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 7822 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31) ; //!< ClampValues - CV7 7823 }; 7824 uint32_t Value; 7825 } DW29; 7826 7827 //! \name Local enumerations 7828 7829 enum SUB_OPCODE_B 7830 { 7831 SUB_OPCODE_B_MFXVP8ENCODERCFG = 1, //!< No additional details 7832 }; 7833 7834 enum SUB_OPCODE_A 7835 { 7836 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 7837 }; 7838 7839 enum MEDIA_COMMAND_OPCODE 7840 { 7841 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 7842 }; 7843 7844 enum PIPELINE 7845 { 7846 PIPELINE_VIDEOCODEC = 2, //!< No additional details 7847 }; 7848 7849 enum COMMAND_TYPE 7850 { 7851 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7852 }; 7853 7854 enum RATE_CONTROL_INITIAL_PASS 7855 { 7856 RATE_CONTROL_INITIAL_PASS_SUBSEQUENCEPASSES = 0, //!< No additional details 7857 RATE_CONTROL_INITIAL_PASS_INITIALPASS = 1, //!< No additional details 7858 }; 7859 7860 //! \brief MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7861 //! \details 7862 //! Enable Max. Frame Rate Control. 7863 //! This is a mask bit controlling if the condition of frame level bit 7864 //! count is greater than or equal to FrameBitRateMax. 7865 enum MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7866 { 7867 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS control register. 7868 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) >= (Frame Bit Rate Maximum Limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS control register. 7869 }; 7870 7871 //! \brief MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7872 //! \details 7873 //! Enable Min. Frame Rate Control. 7874 //! This is a mask bit controlling if the condition of frame level bit 7875 //! count is less than or equal to FrameBitRateMin. 7876 enum MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7877 { 7878 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS Control Register. 7879 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) =< (Frame Bit Rate Minimum limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS Control Register. 7880 }; 7881 7882 //! \brief FRAME_BIT_RATE_MAX_UNIT 7883 //! \details 7884 //! <i>This field is Frame Bitrate Maximum Mode</i> 7885 enum FRAME_BIT_RATE_MAX_UNIT 7886 { 7887 FRAME_BIT_RATE_MAX_UNIT_32_B = 0, //!< No additional details 7888 FRAME_BIT_RATE_MAX_UNIT_4_KB = 1, //!< No additional details 7889 }; 7890 7891 //! \brief FRAME_BITRATE_MAX_UNIT_MODE 7892 //! \details 7893 //! This field is the Frame Bitrate Maximum Limit Units. 7894 enum FRAME_BITRATE_MAX_UNIT_MODE 7895 { 7896 FRAME_BITRATE_MAX_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Max Unit is in old mode (128b/16Kb) 7897 FRAME_BITRATE_MAX_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Max Unit is in new mode (32byte/4Kb) 7898 }; 7899 7900 //! \brief FRAME_BIT_RATE_MIN_UNIT 7901 //! \details 7902 //! <i>This field is Frame Bitrate Minimum Mode.</i> 7903 enum FRAME_BIT_RATE_MIN_UNIT 7904 { 7905 FRAME_BIT_RATE_MIN_UNIT_32_B = 0, //!< No additional details 7906 FRAME_BIT_RATE_MIN_UNIT_4_KB = 1, //!< No additional details 7907 }; 7908 7909 //! \brief FRAME_BITRATE_MIN_UNIT_MODE 7910 //! \details 7911 //! This field is the Frame Bitrate Minimum Limit Units. 7912 enum FRAME_BITRATE_MIN_UNIT_MODE 7913 { 7914 FRAME_BITRATE_MIN_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Min Unit is in old mode (128b/16Kb) 7915 FRAME_BITRATE_MIN_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Min Unit is in new mode (32byte/4Kb) 7916 }; 7917 7918 enum MIN_FRAME_WSIZE_UNIT 7919 { 7920 MIN_FRAME_WSIZE_UNIT_COMPATIBILITYMODE = 0, //!< MinFrameWSizeUnit is in old mode (128b/16Kb) 7921 MIN_FRAME_WSIZE_UNIT_NEWMODE = 1, //!< MinFrameWSizeUnit is in new mode (32byte/4Kb) 7922 }; 7923 7924 //! \name Initializations 7925 7926 //! \brief Explicit member initialization function 7927 MFX_VP8_Encoder_CFG_CMD(); 7928 7929 static const size_t dwSize = 30; 7930 static const size_t byteSize = 120; 7931 }; 7932 7933 //! 7934 //! \brief MFX_VP8_BSP_BUF_BASE_ADDR_STATE 7935 //! \details 7936 //! 7937 //! 7938 struct MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD 7939 { 7940 union 7941 { 7942 //!< DWORD 0 7943 struct 7944 { 7945 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7946 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7947 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 7948 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 7949 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7950 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7951 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7952 }; 7953 uint32_t Value; 7954 } DW0; 7955 union 7956 { 7957 //!< DWORD 1 7958 struct 7959 { 7960 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 7961 uint32_t FrameHeaderBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Frame Header Base Addr 7962 }; 7963 uint32_t Value; 7964 } DW1; 7965 union 7966 { 7967 //!< DWORD 2 7968 struct 7969 { 7970 uint32_t FrameHeaderBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Frame Header Base Addr - Upper Range 7971 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 7972 }; 7973 uint32_t Value; 7974 } DW2; 7975 union 7976 { 7977 //!< DWORD 3 7978 struct 7979 { 7980 uint32_t FrameHeaderBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 7981 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 7982 uint32_t FrameHeaderBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 7983 uint32_t ForFrameheaderbaseaddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 7984 uint32_t FrameHeaderBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 7985 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 7986 }; 7987 uint32_t Value; 7988 } DW3; 7989 union 7990 { 7991 //!< DWORD 4 7992 struct 7993 { 7994 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 7995 uint32_t IntermediateBufferBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Intermediate Buffer Base Addr 7996 }; 7997 uint32_t Value; 7998 } DW4; 7999 union 8000 { 8001 //!< DWORD 5 8002 struct 8003 { 8004 uint32_t IntermediateBufferBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Intermediate Buffer Base Addr - Upper Range 8005 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8006 }; 8007 uint32_t Value; 8008 } DW5; 8009 union 8010 { 8011 //!< DWORD 6 8012 struct 8013 { 8014 uint32_t IntermediateBufferBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8015 uint32_t Reserved194 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8016 uint32_t IntermediateBufferBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8017 uint32_t IntermediateBufferBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8018 uint32_t IntermediateBufferBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8019 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8020 }; 8021 uint32_t Value; 8022 } DW6; 8023 union 8024 { 8025 //!< DWORD 7 8026 struct 8027 { 8028 uint32_t IntermediateBufferPartition1Offset ; //!< Intermediate Buffer Partition-1 Offset 8029 }; 8030 uint32_t Value; 8031 } DW7; 8032 union 8033 { 8034 //!< DWORD 8 8035 struct 8036 { 8037 uint32_t IntermediateBufferPartition2Offset ; //!< Intermediate Buffer Partition-2 Offset 8038 }; 8039 uint32_t Value; 8040 } DW8; 8041 union 8042 { 8043 //!< DWORD 9 8044 struct 8045 { 8046 uint32_t IntermediateBufferPartition3Offset ; //!< Intermediate Buffer Partition-3 Offset 8047 }; 8048 uint32_t Value; 8049 } DW9; 8050 union 8051 { 8052 //!< DWORD 10 8053 struct 8054 { 8055 uint32_t IntermediateBufferPartition4Offset ; //!< Intermediate Buffer Partition-4 Offset 8056 }; 8057 uint32_t Value; 8058 } DW10; 8059 union 8060 { 8061 //!< DWORD 11 8062 struct 8063 { 8064 uint32_t IntermediateBufferPartition5Offset ; //!< Intermediate Buffer Partition-5 Offset 8065 }; 8066 uint32_t Value; 8067 } DW11; 8068 union 8069 { 8070 //!< DWORD 12 8071 struct 8072 { 8073 uint32_t IntermediateBufferPartition6Offset ; //!< Intermediate Buffer Partition-6 Offset 8074 }; 8075 uint32_t Value; 8076 } DW12; 8077 union 8078 { 8079 //!< DWORD 13 8080 struct 8081 { 8082 uint32_t IntermediateBufferPartition7Offset ; //!< Intermediate Buffer Partition-7 Offset 8083 }; 8084 uint32_t Value; 8085 } DW13; 8086 union 8087 { 8088 //!< DWORD 14 8089 struct 8090 { 8091 uint32_t IntermediateBufferPartition8Offset ; //!< Intermediate Buffer Partition-8 Offset 8092 }; 8093 uint32_t Value; 8094 } DW14; 8095 union 8096 { 8097 //!< DWORD 15 8098 struct 8099 { 8100 uint32_t IntermediateBufferMaxSize ; //!< Intermediate Buffer Max Size 8101 }; 8102 uint32_t Value; 8103 } DW15; 8104 union 8105 { 8106 //!< DWORD 16 8107 struct 8108 { 8109 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8110 uint32_t FinalFrameBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Final Frame Base Addr 8111 }; 8112 uint32_t Value; 8113 } DW16; 8114 union 8115 { 8116 //!< DWORD 17 8117 struct 8118 { 8119 uint32_t FinalFrameBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Final Frame Base Addr - Upper Range 8120 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8121 }; 8122 uint32_t Value; 8123 } DW17; 8124 union 8125 { 8126 //!< DWORD 18 8127 struct 8128 { 8129 uint32_t FinalFrameBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8130 uint32_t Reserved578 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8131 uint32_t FinalFrameBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8132 uint32_t FinalFrameBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8133 uint32_t FinalFrameBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< FINAL_FRAME_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8134 uint32_t Reserved585 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8135 }; 8136 uint32_t Value; 8137 } DW18; 8138 union 8139 { 8140 //!< DWORD 19 8141 struct 8142 { 8143 uint32_t Finalframebyteoffset : __CODEGEN_BITFIELD( 0, 5) ; //!< FinalFrameByteOffset 8144 uint32_t Reserved614 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 8145 }; 8146 uint32_t Value; 8147 } DW19; 8148 union 8149 { 8150 //!< DWORD 20 8151 struct 8152 { 8153 uint32_t StreamoutBaseAddrCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8154 uint32_t StreamoutBaseAddrGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Streamout Base Addr - Graphics Data Type (GFDT) 8155 uint32_t Reserved643 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8156 uint32_t StreamoutBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8157 uint32_t StreamoutBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Streamout Base Addr 8158 }; 8159 uint32_t Value; 8160 } DW20; 8161 union 8162 { 8163 //!< DWORD 21 8164 struct 8165 { 8166 uint32_t StreamoutBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Streamout Base Addr - Upper Range 8167 uint32_t Reserved688 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8168 }; 8169 uint32_t Value; 8170 } DW21; 8171 union 8172 { 8173 //!< DWORD 22 8174 struct 8175 { 8176 uint32_t StreamoutBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8177 uint32_t Reserved706 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8178 uint32_t StreamoutBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8179 uint32_t StreamoutBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8180 uint32_t StreamoutBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8181 uint32_t Reserved713 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8182 }; 8183 uint32_t Value; 8184 } DW22; 8185 union 8186 { 8187 //!< DWORD 23 8188 struct 8189 { 8190 uint32_t CoeffProbsStreaminSurfaceCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8191 uint32_t CoeffProbsStreaminSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Coeff Probs StreamIn Surface - Graphics Data Type (GFDT) 8192 uint32_t Reserved739 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8193 uint32_t CoeffProbsStreaminSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8194 uint32_t CoeffProbsStreaminSurface : __CODEGEN_BITFIELD( 6, 31) ; //!< Coeff Probs StreamIn Surface 8195 }; 8196 uint32_t Value; 8197 } DW23; 8198 union 8199 { 8200 //!< DWORD 24 8201 struct 8202 { 8203 uint32_t CoeffProbsStreaminSurfaceUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Coeff Probs StreamIn Surface - Upper Range 8204 uint32_t Reserved784 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8205 }; 8206 uint32_t Value; 8207 } DW24; 8208 union 8209 { 8210 //!< DWORD 25 8211 struct 8212 { 8213 uint32_t CoeffProbsStreaminSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8214 uint32_t Reserved802 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8215 uint32_t CoeffProbsStreaminSurfaceTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8216 uint32_t CoeffProbsStreaminSurfaceLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8217 uint32_t CoeffProbsStreaminSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL 8218 uint32_t Reserved809 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8219 }; 8220 uint32_t Value; 8221 } DW25; 8222 union 8223 { 8224 //!< DWORD 26 8225 struct 8226 { 8227 uint32_t TokenStatisticsSurfaceCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8228 uint32_t TokenStatisticsSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Surface - Graphics Data Type (GFDT) 8229 uint32_t Reserved835 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8230 uint32_t FrameHeaderBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8231 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 6, 31) ; //!< Token Statistics Surface 8232 }; 8233 uint32_t Value; 8234 } DW26; 8235 union 8236 { 8237 //!< DWORD 27 8238 struct 8239 { 8240 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 0, 15) ; //!< Token Statistics Surface 8241 uint32_t Reserved880 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8242 }; 8243 uint32_t Value; 8244 } DW27; 8245 union 8246 { 8247 //!< DWORD 28 8248 struct 8249 { 8250 uint32_t TokenStatisticsSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8251 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Surface 8252 uint32_t TokenStatisticsSurfaceTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8253 uint32_t MemoryTypeLlcEllcCacheabilityControlLellcccForCoeffprobsStreaminSurface : __CODEGEN_BITFIELD( 5, 6) ; //!< MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8254 uint32_t TokenStatisticsSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8255 uint32_t Reserved905 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8256 }; 8257 uint32_t Value; 8258 } DW28; 8259 union 8260 { 8261 //!< DWORD 29..30 8262 struct 8263 { 8264 uint64_t MpcRowstoreSurfaceCacheabilityControl : __CODEGEN_BITFIELD(0, 1); //!< MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8265 uint64_t MpcRowstoreSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD(2, 2); //!< MPC RowStore Surface Graphics Data Type (GFDT) 8266 uint64_t Reserved931 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 8267 uint64_t MpcRowstoreBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD(4, 5); //!< MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8268 uint64_t MpcRowstoreSurfaceAddressLow : __CODEGEN_BITFIELD(6, 63); //!< MPC RowStore Surface Address Low 8269 }; 8270 uint32_t Value[2]; 8271 } DW29_30; 8272 union 8273 { 8274 //!< DWORD 31 8275 struct 8276 { 8277 uint32_t MpcRowstoreSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8278 uint32_t MpcRowstoreSurface : __CODEGEN_BITFIELD( 2, 2) ; //!< MPC RowStore Surface 8279 uint32_t MpcRowstoreTargetCache : __CODEGEN_BITFIELD( 3, 4) ; //!< MPC_ROWSTORE__TARGET_CACHE 8280 uint32_t MpcRowstoreMemoryTypeLlcEllcCacheabilityControl : __CODEGEN_BITFIELD( 5, 6) ; //!< MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8281 uint32_t MpcRowstoreArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8282 uint32_t Reserved1001 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8283 }; 8284 uint32_t Value; 8285 } DW31; 8286 8287 //! \name Local enumerations 8288 8289 enum SUB_OPCODE_B 8290 { 8291 SUB_OPCODE_B_MFXVP8BSPBUFBASEADDRSTATE = 3, //!< No additional details 8292 }; 8293 8294 enum SUB_OPCODE_A 8295 { 8296 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 8297 }; 8298 8299 enum MEDIA_COMMAND_OPCODE 8300 { 8301 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 8302 }; 8303 8304 enum PIPELINE 8305 { 8306 PIPELINE_VIDEOCODEC = 2, //!< No additional details 8307 }; 8308 8309 enum COMMAND_TYPE 8310 { 8311 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 8312 }; 8313 8314 //! \brief FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8315 //! \details 8316 //! This field allows the selection of AGE parameter for a given surface in 8317 //! LLC or eLLC. . 8318 //! If a particular allocation is done at youngest age ("3") it tends 8319 //! to stay longer in the cache as compared to older age allocations ("2", 8320 //! "1", or "0"). 8321 //! This option is given to driver to be able to decide which surfaces 8322 //! are more likely to generate HITs, hence need to be replaced least often 8323 //! in caches. 8324 enum FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8325 { 8326 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8327 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8328 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8329 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8330 }; 8331 8332 //! \brief FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8333 //! \details 8334 //! This field allows the choice of LLC vs eLLC for caching 8335 enum FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8336 { 8337 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8338 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8339 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8340 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8341 }; 8342 8343 //! \brief FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8344 //! \details 8345 //! This is the field used in GT interface block to determine what type of 8346 //! access need to be generated to uncore. 8347 //! For the cases where the LeLLCCC is set, cacheable transaction are 8348 //! generated to enable LLC usage for particular stream. 8349 enum FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8350 { 8351 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8352 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8353 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8354 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8355 }; 8356 8357 //! \brief FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8358 //! \details 8359 //! This field controls the priority of arbitration used in the GAC/GAM 8360 //! pipeline for this surface. 8361 enum FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8362 { 8363 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8364 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8365 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8366 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8367 }; 8368 8369 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8370 //! \details 8371 //! This field allows the selection of AGE parameter for a given surface in 8372 //! LLC or eLLC. . 8373 //! If a particular allocation is done at youngest age ("3") it tends 8374 //! to stay longer in the cache as compared to older age allocations ("2", 8375 //! "1", or "0"). 8376 //! This option is given to driver to be able to decide which surfaces 8377 //! are more likely to generate HITs, hence need to be replaced least often 8378 //! in caches. 8379 enum INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8380 { 8381 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8382 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8383 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8384 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8385 }; 8386 8387 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8388 //! \details 8389 //! This field allows the choice of LLC vs. eLLC for caching 8390 enum INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8391 { 8392 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8393 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8394 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8395 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8396 }; 8397 8398 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8399 //! \details 8400 //! This is the field used in GT interface block to determine what type of 8401 //! access need to be generated to uncore. 8402 //! For the cases where the LeLLCCC is set, cacheable transaction are 8403 //! generated to enable LLC usage for particular stream. 8404 enum INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8405 { 8406 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8407 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8408 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8409 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8410 }; 8411 8412 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8413 //! \details 8414 //! This field controls the priority of arbitration used in the GAC/GAM 8415 //! pipeline for this surface. 8416 enum INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8417 { 8418 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8419 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8420 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8421 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8422 }; 8423 8424 //! \brief FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8425 //! \details 8426 //! This field allows the selection of AGE parameter for a given surface in 8427 //! LLC or eLLC. . 8428 //! If a particular allocation is done at youngest age ("3") it tends 8429 //! to stay longer in the cache as compared to older age allocations ("2", 8430 //! "1", or "0"). 8431 //! This option is given to driver to be able to decide which surfaces 8432 //! are more likely to generate HITs, hence need to be replaced least often 8433 //! in caches. 8434 enum FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8435 { 8436 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8437 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8438 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8439 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8440 }; 8441 8442 //! \brief FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8443 //! \details 8444 //! This field allows the choice of LLC vs eLLC for caching 8445 enum FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8446 { 8447 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8448 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8449 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8450 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8451 }; 8452 8453 //! \brief FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8454 //! \details 8455 //! This is the field used in GT interface block to determine what type of 8456 //! access need to be generated to uncore. 8457 //! For the cases where the LeLLCCC is set, cacheable transaction are 8458 //! generated to enable LLC usage for particular stream. 8459 enum FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8460 { 8461 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8462 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8463 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8464 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8465 }; 8466 8467 enum FINAL_FRAME_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8468 { 8469 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8470 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8471 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8472 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8473 }; 8474 8475 //! \brief STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8476 //! \details 8477 //! This field controls cacheability in the mid-level cache (MLC) and 8478 //! last-level cache (LLC) 8479 enum STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8480 { 8481 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8482 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8483 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8484 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8485 }; 8486 8487 //! \brief STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8488 //! \details 8489 //! This field controls the priority of arbitration used in the GAC/GAM 8490 //! pipeline for this surface. 8491 enum STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8492 { 8493 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8494 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8495 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8496 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8497 }; 8498 8499 //! \brief STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8500 //! \details 8501 //! This field allows the selection of AGE parameter for a given surface in 8502 //! LLC or eLLC. . 8503 //! If a particular allocation is done at youngest age ("3") it tends 8504 //! to stay longer in the cache as compared to older age allocations ("2", 8505 //! "1", or "0"). 8506 //! This option is given to driver to be able to decide which surfaces 8507 //! are more likely to generate HITs, hence need to be replaced least often 8508 //! in caches. 8509 enum STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8510 { 8511 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8512 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8513 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8514 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8515 }; 8516 8517 //! \brief STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8518 //! \details 8519 //! This field allows the choice of LLC vs eLLC for caching 8520 enum STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8521 { 8522 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8523 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8524 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8525 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8526 }; 8527 8528 //! \brief STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8529 //! \details 8530 //! This is the field used in GT interface block to determine what type of 8531 //! access need to be generated to uncore. 8532 //! For the cases where the LeLLCCC is set, cacheable transaction are 8533 //! generated to enable LLC usage for particular stream. 8534 enum STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8535 { 8536 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8537 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8538 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8539 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8540 }; 8541 8542 //! \brief COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8543 //! \details 8544 //! This field controls cacheability in the mid-level cache (MLC) and 8545 //! last-level cache (LLC) 8546 enum COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8547 { 8548 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8549 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8550 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8551 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8552 }; 8553 8554 //! \brief COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8555 //! \details 8556 //! This field controls the priority of arbitration used in the GAC/GAM 8557 //! pipeline for this surface. 8558 enum COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8559 { 8560 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8561 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8562 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8563 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8564 }; 8565 8566 //! \brief COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8567 //! \details 8568 //! This field allows the selection of AGE parameter for a given surface in 8569 //! LLC or eLLC. . 8570 //! If a particular allocation is done at youngest age ("3") it tends 8571 //! to stay longer in the cache as compared to older age allocations ("2", 8572 //! "1", or "0"). 8573 //! This option is given to driver to be able to decide which surfaces 8574 //! are more likely to generate HITs, hence need to be replaced least often 8575 //! in caches. 8576 enum COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8577 { 8578 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8579 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8580 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8581 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8582 }; 8583 8584 //! \brief COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8585 //! \details 8586 //! This field allows the choice of LLC vs eLLC for caching 8587 enum COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8588 { 8589 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8590 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8591 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8592 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8593 }; 8594 8595 //! \brief COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8596 //! \details 8597 //! This is the field used in GT interface block to determine what type of 8598 //! access need to be generated to uncore. 8599 //! For the cases where the LeLLCCC is set, cacheable transaction are 8600 //! generated to enable LLC usage for particular stream. 8601 enum COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8602 { 8603 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8604 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8605 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8606 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8607 }; 8608 8609 //! \brief TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8610 //! \details 8611 //! This field controls cacheability in the mid-level cache (MLC) and 8612 //! last-level cache (LLC). 8613 enum TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8614 { 8615 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8616 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8617 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8618 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8619 }; 8620 8621 //! \brief TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8622 //! \details 8623 //! This field allows the selection of AGE parameter for a given surface in 8624 //! LLC or eLLC. . If a particular allocation is done at youngest age ("3") 8625 //! it tends to stay longer in the cache as compared to older age 8626 //! allocations ("2", "1", or "0"). 8627 //! This option is given to driver to be able to decide which surfaces 8628 //! are more likely to generate HITs, hence need to be replaced least often 8629 //! in caches. 8630 enum TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8631 { 8632 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 0, //!< No additional details 8633 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 1, //!< No additional details 8634 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 2, //!< No additional details 8635 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 3, //!< No additional details 8636 }; 8637 8638 //! \brief TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8639 //! \details 8640 //! This field allows the choice of LLC vs eLLC for caching. 8641 enum TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8642 { 8643 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGTBDW = 0, //!< No additional details 8644 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8645 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8646 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8647 }; 8648 8649 //! \brief MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8650 //! \details 8651 //! This is the field used in GT interface block to determine what type of 8652 //! access need to be generated to uncore. 8653 //! For the cases where the LeLLCCC is set, cacheable transaction are 8654 //! generated to enable LLC usage for particular stream. 8655 enum MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8656 { 8657 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_USECACHEABILITYCONTROLSFROMPAGETABLEUCWITHFENCEIFCOHERENTCYCLE = 0, //!< No additional details 8658 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_UC = 1, //!< Uncacheable - non-cacheable 8659 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_WT = 2, //!< Writethrough 8660 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_WB = 3, //!< Writeback 8661 }; 8662 8663 //! \brief TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8664 //! \details 8665 //! This field controls the priority of arbitration used in the GAC/GAM 8666 //! pipeline for this surface. 8667 enum TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8668 { 8669 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8670 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8671 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8672 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8673 }; 8674 8675 //! \brief MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8676 //! \details 8677 //! <b>This field controls cacheability in the mid-level cache (MLC) and 8678 //! last-level cache (LLC).</b> 8679 enum MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8680 { 8681 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8682 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8683 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8684 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8685 }; 8686 8687 //! \brief MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8688 //! \details 8689 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8690 //! pipeline for this surface.</b> 8691 enum MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8692 { 8693 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8694 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8695 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8696 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8697 }; 8698 8699 //! \brief MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8700 //! \details 8701 //! <b>This field allows the selection of AGE parameter for a given surface 8702 //! in LLC or eLLC. . If a particular allocation is done at youngest age 8703 //! ("3") it tends to stay longer in the cache as compared to older age 8704 //! allocations ("2", "1", or "0"). 8705 //! This option is given to driver to be able to decide which surfaces 8706 //! are more likely to generate HITs, hence need to be replaced least often 8707 //! in caches.</b> 8708 enum MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8709 { 8710 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 0, //!< No additional details 8711 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 1, //!< No additional details 8712 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 2, //!< No additional details 8713 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 3, //!< No additional details 8714 }; 8715 8716 //! \brief MPC_ROWSTORE__TARGET_CACHE 8717 //! \details 8718 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8719 //! pipeline for this surface.</b> 8720 enum MPC_ROWSTORE__TARGET_CACHE 8721 { 8722 MPC_ROWSTORE_TARGET_CACHE_ELLCONLY = 0, //!< No additional details 8723 MPC_ROWSTORE_TARGET_CACHE_LLCONLY = 1, //!< No additional details 8724 MPC_ROWSTORE_TARGET_CACHE_LLCELLCALLOWED = 2, //!< No additional details 8725 MPC_ROWSTORE_TARGET_CACHE_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8726 }; 8727 8728 //! \brief MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8729 //! \details 8730 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8731 //! pipeline for this surface.</b> 8732 enum MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8733 { 8734 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_USECACHEABILITYCONTROLSFROMPAGETABLEUCWITHFENCEIFCOHERENTCYCLE = 0, //!< No additional details 8735 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_UC = 1, //!< Uncacheable - non-cacheable 8736 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_WT = 2, //!< Writethrough 8737 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_WB = 3, //!< Writeback 8738 }; 8739 8740 //! \brief MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8741 //! \details 8742 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8743 //! pipeline for this surface.</b> 8744 enum MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8745 { 8746 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8747 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8748 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8749 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8750 }; 8751 8752 //! \name Initializations 8753 8754 //! \brief Explicit member initialization function 8755 MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD(); 8756 8757 static const size_t dwSize = 32; 8758 static const size_t byteSize = 128; 8759 }; 8760 8761 //! 8762 //! \brief MFD_VP8_BSD_OBJECT 8763 //! \details 8764 //! The MFD_VP8_BSD_OBJECT command is the only primitive command for the VP8 8765 //! Decoding Pipeline. The Partitions of the bitstream is loaded as indirect 8766 //! data object. Before issuing a MFD_VP8_BSD_OBJECT command, all VP8 frame 8767 //! level states of the MFD Engine need to be valid. Therefore the commands 8768 //! used to set these states need to have been issued prior to the issue of 8769 //! a MFD_VP8_BSD_OBJECT command. Context switch interrupt is not supported 8770 //! by this command. 8771 //! 8772 struct MFD_VP8_BSD_OBJECT_CMD 8773 { 8774 union 8775 { 8776 //!< DWORD 0 8777 struct 8778 { 8779 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 8780 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 8781 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 8782 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 8783 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 8784 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 8785 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 8786 }; 8787 uint32_t Value; 8788 } DW0; 8789 union 8790 { 8791 //!< DWORD 1 8792 struct 8793 { 8794 uint32_t Partition0FirstmbbitoffsetFromFrameHeader : __CODEGEN_BITFIELD( 0, 2) ; //!< Partition0 FirstMBBitOffset from Frame Header 8795 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8796 uint32_t CodedNumOfCoeffTokenPartitions : __CODEGEN_BITFIELD( 4, 5) ; //!< Coded Num of Coeff Token Partitions 8797 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 8798 uint32_t Partition0CpbacEntropyRange : __CODEGEN_BITFIELD( 8, 15) ; //!< Partition0 CPBAC Entropy Range 8799 uint32_t Partition0CpbacEntropyCount : __CODEGEN_BITFIELD(16, 20) ; //!< Partition0 CPBAC Entropy Count 8800 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 8801 }; 8802 uint32_t Value; 8803 } DW1; 8804 union 8805 { 8806 //!< DWORD 2 8807 struct 8808 { 8809 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 23) ; //!< Reserved 8810 uint32_t Partition0CpbacEntropyValue : __CODEGEN_BITFIELD(24, 31) ; //!< Partition0 CPBAC Entropy Value 8811 }; 8812 uint32_t Value; 8813 } DW2; 8814 union 8815 { 8816 //!< DWORD 3 8817 struct 8818 { 8819 uint32_t IndirectPartition0DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition0 Data Length 8820 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8821 }; 8822 uint32_t Value; 8823 } DW3; 8824 union 8825 { 8826 //!< DWORD 4 8827 struct 8828 { 8829 uint32_t IndirectPartition0DataStartOffset ; //!< Indirect Partition0 Data Start Offset 8830 }; 8831 uint32_t Value; 8832 } DW4; 8833 union 8834 { 8835 //!< DWORD 5 8836 struct 8837 { 8838 uint32_t IndirectPartition1DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition1 Data Length 8839 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8840 }; 8841 uint32_t Value; 8842 } DW5; 8843 union 8844 { 8845 //!< DWORD 6 8846 struct 8847 { 8848 uint32_t IndirectPartition1DataStartOffset ; //!< Indirect Partition1 Data Start Offset 8849 }; 8850 uint32_t Value; 8851 } DW6; 8852 union 8853 { 8854 //!< DWORD 7 8855 struct 8856 { 8857 uint32_t IndirectPartition2DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition2 Data Length 8858 uint32_t Reserved248 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8859 }; 8860 uint32_t Value; 8861 } DW7; 8862 union 8863 { 8864 //!< DWORD 8 8865 struct 8866 { 8867 uint32_t IndirectPartition2DataStartOffset ; //!< Indirect Partition2 Data Start Offset 8868 }; 8869 uint32_t Value; 8870 } DW8; 8871 union 8872 { 8873 //!< DWORD 9 8874 struct 8875 { 8876 uint32_t IndirectPartition3DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition3 Data Length 8877 uint32_t Reserved312 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8878 }; 8879 uint32_t Value; 8880 } DW9; 8881 union 8882 { 8883 //!< DWORD 10 8884 struct 8885 { 8886 uint32_t IndirectPartition3DataStartOffset ; //!< Indirect Partition3 Data Start Offset 8887 }; 8888 uint32_t Value; 8889 } DW10; 8890 union 8891 { 8892 //!< DWORD 11 8893 struct 8894 { 8895 uint32_t IndirectPartition4DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition4 Data Length 8896 uint32_t Reserved376 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8897 }; 8898 uint32_t Value; 8899 } DW11; 8900 union 8901 { 8902 //!< DWORD 12 8903 struct 8904 { 8905 uint32_t IndirectPartition4DataStartOffset ; //!< Indirect Partition4 Data Start Offset 8906 }; 8907 uint32_t Value; 8908 } DW12; 8909 union 8910 { 8911 //!< DWORD 13 8912 struct 8913 { 8914 uint32_t IndirectPartition5DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition5 Data Length 8915 uint32_t Reserved440 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8916 }; 8917 uint32_t Value; 8918 } DW13; 8919 union 8920 { 8921 //!< DWORD 14 8922 struct 8923 { 8924 uint32_t IndirectPartition5DataStartOffset ; //!< Indirect Partition5 Data Start Offset 8925 }; 8926 uint32_t Value; 8927 } DW14; 8928 union 8929 { 8930 //!< DWORD 15 8931 struct 8932 { 8933 uint32_t IndirectPartition6DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition6 Data Length 8934 uint32_t Reserved504 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8935 }; 8936 uint32_t Value; 8937 } DW15; 8938 union 8939 { 8940 //!< DWORD 16 8941 struct 8942 { 8943 uint32_t IndirectPartition6DataStartOffset ; //!< Indirect Partition6 Data Start Offset 8944 }; 8945 uint32_t Value; 8946 } DW16; 8947 union 8948 { 8949 //!< DWORD 17 8950 struct 8951 { 8952 uint32_t IndirectPartition7DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition7 Data Length 8953 uint32_t Reserved568 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8954 }; 8955 uint32_t Value; 8956 } DW17; 8957 union 8958 { 8959 //!< DWORD 18 8960 struct 8961 { 8962 uint32_t IndirectPartition7DataStartOffset ; //!< Indirect Partition7 Data Start Offset 8963 }; 8964 uint32_t Value; 8965 } DW18; 8966 union 8967 { 8968 //!< DWORD 19 8969 struct 8970 { 8971 uint32_t IndirectPartition8DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition8 Data Length 8972 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8973 }; 8974 uint32_t Value; 8975 } DW19; 8976 union 8977 { 8978 //!< DWORD 20 8979 struct 8980 { 8981 uint32_t IndirectPartition8DataStartOffset ; //!< Indirect Partition8 Data Start Offset 8982 }; 8983 uint32_t Value; 8984 } DW20; 8985 union 8986 { 8987 //!< DWORD 21 8988 struct 8989 { 8990 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 8991 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD( 8, 8) ; //!< MB_HEADER_ERROR_HANDLING 8992 uint32_t Reserved681 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 8993 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10) ; //!< ENTROPY_ERROR_HANDLING 8994 uint32_t Reserved683 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 8995 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 8996 uint32_t Reserved685 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 8997 uint32_t BsdprematurecompleteErrorHandling : __CODEGEN_BITFIELD(14, 14) ; //!< BSDPREMATURECOMPLETE_ERROR_HANDLING 8998 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 8999 uint32_t ConcealPicIdConcealmentPictureId : __CODEGEN_BITFIELD(16, 17) ; //!< Conceal_Pic_Id (Concealment Picture ID) 9000 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 9001 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31) ; //!< CONCEALMENT_METHOD 9002 }; 9003 uint32_t Value; 9004 } DW21; 9005 9006 //! \name Local enumerations 9007 9008 enum SUBOPCODEB 9009 { 9010 SUBOPCODEB_UNNAMED8 = 8, //!< No additional details 9011 }; 9012 9013 enum SUBOPCODEA 9014 { 9015 SUBOPCODEA_UNNAMED1 = 1, //!< No additional details 9016 }; 9017 9018 enum MEDIA_COMMAND_OPCODE 9019 { 9020 MEDIA_COMMAND_OPCODE_VP8DEC = 4, //!< No additional details 9021 }; 9022 9023 enum PIPELINE 9024 { 9025 PIPELINE_MFDVP8BSDOBJECT = 2, //!< No additional details 9026 }; 9027 9028 enum COMMAND_TYPE 9029 { 9030 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9031 }; 9032 9033 enum MB_HEADER_ERROR_HANDLING 9034 { 9035 MB_HEADER_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9036 MB_HEADER_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9037 }; 9038 9039 enum ENTROPY_ERROR_HANDLING 9040 { 9041 ENTROPY_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9042 ENTROPY_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9043 }; 9044 9045 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 9046 { 9047 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9048 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9049 }; 9050 9051 //! \brief BSDPREMATURECOMPLETE_ERROR_HANDLING 9052 //! \details 9053 //! It occurs in situation where the decode is completed but there are still 9054 //! data in the bitstream. 9055 enum BSDPREMATURECOMPLETE_ERROR_HANDLING 9056 { 9057 BSDPREMATURECOMPLETE_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9058 BSDPREMATURECOMPLETE_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9059 }; 9060 9061 //! \brief CONCEALMENT_METHOD 9062 //! \details 9063 //! This field specifies the method used for concealment when error is 9064 //! detected. 9065 enum CONCEALMENT_METHOD 9066 { 9067 CONCEALMENT_METHOD_INTRA16X16PREDICTION = 0, //!< A copy from the current picture is performed using Intra 16x16 Prediction method. 9068 CONCEALMENT_METHOD_INTERPCOPY = 1, //!< A copy from collocated macroblock location is performed from the concealment reference indicated by the ConCeal_Pic_Id field. 9069 }; 9070 9071 //! \name Initializations 9072 9073 //! \brief Explicit member initialization function 9074 MFD_VP8_BSD_OBJECT_CMD(); 9075 9076 static const size_t dwSize = 22; 9077 static const size_t byteSize = 88; 9078 }; 9079 9080 //! 9081 //! \brief MFX_VP8_PIC_STATE 9082 //! \details 9083 //! This must be the very first command to issue after the surface state, 9084 //! the pipe select and base address setting commands and must be issued 9085 //! before MFX_VP8_IMG_STATE. 9086 //! 9087 struct MFX_VP8_PIC_STATE_CMD 9088 { 9089 union 9090 { 9091 //!< DWORD 0 9092 struct 9093 { 9094 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 9095 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 9096 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 9097 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 9098 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 9099 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 9100 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 9101 }; 9102 uint32_t Value; 9103 } DW0; 9104 union 9105 { 9106 //!< DWORD 1 9107 struct 9108 { 9109 uint32_t FrameWidthMinus1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Width Minus 1 9110 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 9111 uint32_t FrameHeightMinus1 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Height Minus 1 9112 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9113 }; 9114 uint32_t Value; 9115 } DW1; 9116 union 9117 { 9118 //!< DWORD 2 9119 struct 9120 { 9121 uint32_t McFilterSelect : __CODEGEN_BITFIELD(0, 0); //!< MC_FILTER_SELECT, Decoder / Encoder 9122 uint32_t ChromaFullPixelMcFilterMode : __CODEGEN_BITFIELD(1, 1); //!< CHROMA_FULL_PIXEL_MC_FILTER_MODE, Decoder / Encoder 9123 uint32_t Reserved66 : __CODEGEN_BITFIELD(2, 3); //!< Reserved, Decoder / Encoder 9124 uint32_t Dblkfiltertype : __CODEGEN_BITFIELD(4, 4); //!< DBLKFILTERTYPE, Decoder / Encoder 9125 uint32_t Skeyframeflag : __CODEGEN_BITFIELD(5, 5); //!< SKEYFRAMEFLAG, Decoder / Encoder 9126 uint32_t SegmentationIdStreamoutEnable : __CODEGEN_BITFIELD(6, 6); //!< SEGMENTATION_ID_STREAMOUT_ENABLE, Decoder Only 9127 uint32_t SegmentationIdStreaminEnable : __CODEGEN_BITFIELD(7, 7); //!< SEGMENTATION_ID_STREAMIN_ENABLE, Decoder Only 9128 uint32_t SegmentEnableFlag : __CODEGEN_BITFIELD(8, 8); //!< SEGMENT_ENABLE_FLAG, Decoder / Encoder 9129 uint32_t UpdateMbsegmentMapFlag : __CODEGEN_BITFIELD(9, 9); //!< UPDATE_MBSEGMENT_MAP_FLAG, Decoder / Encoder 9130 uint32_t MbNocoeffSkipflag : __CODEGEN_BITFIELD(10, 10); //!< MB_NOCOEFF_SKIPFLAG, Decoder / Encoder 9131 uint32_t ModeReferenceLoopFilterDeltaEnabled : __CODEGEN_BITFIELD(11, 11); //!< MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED, Decoder / Encoder 9132 uint32_t GoldenRefPictureMvSignbiasFlag : __CODEGEN_BITFIELD(12, 12); //!< Golden Ref Picture MV SignBias Flag, Decoder / Encoder 9133 uint32_t AlternateRefPicMvSignbiasFlag : __CODEGEN_BITFIELD(13, 13); //!< Alternate Ref Pic MV SignBias Flag, Decoder / Encoder 9134 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15); //!< Reserved, Decoder / Encoder 9135 uint32_t DeblockSharpnessLevel : __CODEGEN_BITFIELD(16, 18); //!< Deblock Sharpness Level, Decoder / Encoder 9136 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 23); //!< Reserved, Decoder / Encoder 9137 uint32_t Log2NumOfPartition : __CODEGEN_BITFIELD(24, 25); //!< LOG2_NUM_OF_PARTITION, Decoder / Encoder 9138 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 9139 }; 9140 uint32_t Value; 9141 } DW2; 9142 union 9143 { 9144 //!< DWORD 3 9145 struct 9146 { 9147 uint32_t DblkfilterlevelForSegment0 : __CODEGEN_BITFIELD( 0, 5) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT0 9148 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 9149 uint32_t DblkfilterlevelForSegment1 : __CODEGEN_BITFIELD( 8, 13) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT1 9150 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 9151 uint32_t DblkfilterlevelForSegment2 : __CODEGEN_BITFIELD(16, 21) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT2 9152 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 9153 uint32_t DblkfilterlevelForSegment3 : __CODEGEN_BITFIELD(24, 29) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT3 9154 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 9155 }; 9156 uint32_t Value; 9157 } DW3; 9158 union 9159 { 9160 //!< DWORD 4 9161 struct 9162 { 9163 uint32_t QuantizerValue0Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType0=Y1DC], Decoder Only 9164 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9165 uint32_t QuantizerValue0Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType1=Y1AC], Decoder Only 9166 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9167 } dec; 9168 struct 9169 { 9170 uint32_t Seg0Qindex : __CODEGEN_BITFIELD( 0, 6) ; //!< Seg 0 Qindex, Encoder Only 9171 uint32_t Reserved135 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved, Encoder Only 9172 uint32_t Seg1Qindex : __CODEGEN_BITFIELD( 8, 14) ; //!< Seg 1 Qindex, Encoder Only 9173 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved, Encoder Only 9174 uint32_t Seg2Qindex : __CODEGEN_BITFIELD(16, 22) ; //!< Seg 2 Qindex, Encoder Only 9175 uint32_t Reserved151 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved, Encoder Only 9176 uint32_t Seg3Qindex : __CODEGEN_BITFIELD(24, 30) ; //!< Seg 3 Qindex, Encoder Only 9177 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9178 } enc; 9179 uint32_t Value; 9180 } DW4; 9181 union 9182 { 9183 //!< DWORD 5 9184 struct 9185 { 9186 uint32_t QuantizerValue0Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType2=UVDC], Decoder Only 9187 uint32_t Reserved169 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9188 uint32_t QuantizerValue0Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType3=UVAC], Decoder Only 9189 uint32_t Reserved185 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9190 } dec; 9191 struct 9192 { 9193 uint32_t Y2DcQindexDelta : __CODEGEN_BITFIELD( 0, 3) ; //!< Y2dc Qindex Delta, Encoder Only 9194 uint32_t Y2AcQindexDeltaSign : __CODEGEN_BITFIELD( 4, 4) ; //!< Y2ac Qindex Delta Sign , Encoder Only 9195 uint32_t Reserved165 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved, Encoder Only 9196 uint32_t Y2AcQindexDelta : __CODEGEN_BITFIELD( 8, 11) ; //!< Y2ac Qindex Delta , Encoder Only 9197 uint32_t Y2AcQindexSign : __CODEGEN_BITFIELD(12, 12) ; //!< Y2ac Qindex Sign, Encoder Only 9198 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, Encoder Only 9199 uint32_t UvdcQindexDelta : __CODEGEN_BITFIELD(16, 19) ; //!< UVdc Qindex Delta, Encoder Only 9200 uint32_t UvdcQindexDeltaSign : __CODEGEN_BITFIELD(20, 20) ; //!< UVdc Qindex Delta Sign, Encoder Only 9201 uint32_t Reserved181 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved, Encoder Only 9202 uint32_t UvacQindexdelta : __CODEGEN_BITFIELD(24, 27) ; //!< UVac QindexDelta, Encoder Only 9203 uint32_t UvacQindexDeltaSign : __CODEGEN_BITFIELD(28, 28) ; //!< UVac Qindex Delta Sign, Encoder Only 9204 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 9205 } enc; 9206 uint32_t Value; 9207 } DW5; 9208 union 9209 { 9210 //!< DWORD 6 9211 struct 9212 { 9213 uint32_t QuantizerValue0Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType4=Y2DC], Decoder Only 9214 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9215 uint32_t QuantizerValue0Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType5=Y2AC], Decoder Only 9216 uint32_t Reserved217 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9217 } dec; 9218 struct 9219 { 9220 uint32_t Y1DcQindexDelta : __CODEGEN_BITFIELD( 0, 3) ; //!< Y1dc Qindex Delta, Encoder Only 9221 uint32_t Y1DcQindexDeltaSign : __CODEGEN_BITFIELD( 4, 4) ; //!< Y1dc Qindex Delta Sign , Encoder Only 9222 uint32_t Reserved197 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 9223 } enc; 9224 uint32_t Value; 9225 } DW6; 9226 union 9227 { 9228 //!< DWORD 7 9229 struct 9230 { 9231 uint32_t QuantizerValue1Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType0=Y1DC], Decoder Only 9232 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9233 uint32_t QuantizerValue1Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType1=Y1AC], Decoder Only 9234 uint32_t Reserved249 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9235 } dec; 9236 struct 9237 { 9238 uint32_t ClampQindexLow : __CODEGEN_BITFIELD( 0, 6) ; //!< Clamp Qindex Low, Encoder Only 9239 uint32_t Reserved231 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved, Encoder Only 9240 uint32_t ClampQindexHigh : __CODEGEN_BITFIELD( 8, 14) ; //!< Clamp Qindex high, Encoder Only 9241 uint32_t Reserved239 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9242 } enc; 9243 uint32_t Value; 9244 } DW7; 9245 union 9246 { 9247 //!< DWORD 8 9248 struct 9249 { 9250 uint32_t QuantizerValue1Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType2=UVDC], Decoder Only 9251 uint32_t Reserved265 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9252 uint32_t QuantizerValue1Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType3=UVAC], Decoder Only 9253 uint32_t Reserved281 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9254 }; 9255 uint32_t Value; 9256 } DW8; 9257 union 9258 { 9259 //!< DWORD 9 9260 struct 9261 { 9262 uint32_t QuantizerValue1Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType4=Y2DC], Decoder Only 9263 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9264 uint32_t QuantizerValue1Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType5=Y2AC], Decoder Only 9265 uint32_t Reserved313 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9266 }; 9267 uint32_t Value; 9268 } DW9; 9269 union 9270 { 9271 //!< DWORD 10 9272 struct 9273 { 9274 uint32_t QuantizerValue2Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType0=Y1DC], Decoder Only 9275 uint32_t Reserved329 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9276 uint32_t QuantizerValue2Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType1=Y1AC], Decoder Only 9277 uint32_t Reserved345 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9278 }; 9279 uint32_t Value; 9280 } DW10; 9281 union 9282 { 9283 //!< DWORD 11 9284 struct 9285 { 9286 uint32_t QuantizerValue2Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType2=UVDC], Decoder Only 9287 uint32_t Reserved361 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9288 uint32_t QuantizerValue2Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType3=UVAC], Decoder Only 9289 uint32_t Reserved377 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9290 }; 9291 uint32_t Value; 9292 } DW11; 9293 union 9294 { 9295 //!< DWORD 12 9296 struct 9297 { 9298 uint32_t QuantizerValue2Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType4=Y2DC], Decoder Only 9299 uint32_t Reserved393 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9300 uint32_t QuantizerValue2Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType5=Y2AC], Decoder Only 9301 uint32_t Reserved409 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9302 }; 9303 uint32_t Value; 9304 } DW12; 9305 union 9306 { 9307 //!< DWORD 13 9308 struct 9309 { 9310 uint32_t QuantizerValue3Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType0=Y1DC], Decoder Only 9311 uint32_t Reserved425 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9312 uint32_t QuantizerValue3Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType1=Y1AC], Decoder Only 9313 uint32_t Reserved441 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9314 }; 9315 uint32_t Value; 9316 } DW13; 9317 union 9318 { 9319 //!< DWORD 14 9320 struct 9321 { 9322 uint32_t QuantizerValue3Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType2=UVDC], Decoder Only 9323 uint32_t Reserved457 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9324 uint32_t QuantizerValue3Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType3=UVAC], Decoder Only 9325 uint32_t Reserved473 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9326 }; 9327 uint32_t Value; 9328 } DW14; 9329 union 9330 { 9331 //!< DWORD 15 9332 struct 9333 { 9334 uint32_t QuantizerValue3Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType4=Y2DC], Decoder Only 9335 uint32_t Reserved489 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9336 uint32_t QuantizerValue3Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType5=Y2AC], Decoder Only 9337 uint32_t Reserved505 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9338 }; 9339 uint32_t Value; 9340 } DW15; 9341 union 9342 { 9343 //!< DWORD 16 9344 struct 9345 { 9346 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 9347 uint32_t CoeffprobabilityStreaminBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< CoeffProbability StreamIn Base Address, Decoder Only 9348 }; 9349 uint32_t Value; 9350 } DW16; 9351 union 9352 { 9353 //!< DWORD 17 9354 struct 9355 { 9356 uint32_t CoeffprobabilityStreaminAddress : __CODEGEN_BITFIELD( 0, 15) ; //!< CoeffProbability StreamIn Address, Decoder Only 9357 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9358 }; 9359 uint32_t Value; 9360 } DW17; 9361 union 9362 { 9363 //!< DWORD 18 9364 struct 9365 { 9366 uint32_t Reserved576 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 9367 uint32_t CoeffprobabilityStreaminArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL, Decoder Only 9368 uint32_t CoeffprobabilityStreaminMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< CoeffProbability StreamIn - Memory Compression Enable, Decoder Only 9369 uint32_t CoeffprobabilityStreaminMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE, Decoder Only 9370 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved, Decoder Only 9371 uint32_t CoeffprobabilityStreaminTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE, Decoder Only 9372 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9373 }; 9374 uint32_t Value; 9375 } DW18; 9376 union 9377 { 9378 //!< DWORD 19 9379 struct 9380 { 9381 uint32_t Mbsegmentidtreeprobs0 : __CODEGEN_BITFIELD( 0, 7) ; //!< MBSegmentIDTreeProbs[0] 9382 uint32_t Mbsegmentidtreeprobs1 : __CODEGEN_BITFIELD( 8, 15) ; //!< MBSegmentIDTreeProbs[1] 9383 uint32_t Mbsegmentidtreeprobs2 : __CODEGEN_BITFIELD(16, 23) ; //!< MBSegmentIDTreeProbs[2] 9384 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9385 }; 9386 uint32_t Value; 9387 } DW19; 9388 union 9389 { 9390 //!< DWORD 20 9391 struct 9392 { 9393 uint32_t Interpredfromgrefrefprob : __CODEGEN_BITFIELD( 0, 7) ; //!< InterPredFromGRefRefProb 9394 uint32_t Interpredfromlastrefprob : __CODEGEN_BITFIELD( 8, 15) ; //!< InterPredFromLastRefProb 9395 uint32_t Intrambprob : __CODEGEN_BITFIELD(16, 23) ; //!< IntraMBProb 9396 uint32_t Mbnocoeffskipfalseprob : __CODEGEN_BITFIELD(24, 31) ; //!< MBNoCoeffSkipFalseProb 9397 }; 9398 uint32_t Value; 9399 } DW20; 9400 union 9401 { 9402 //!< DWORD 21 9403 struct 9404 { 9405 uint32_t Ymodeprob0 : __CODEGEN_BITFIELD( 0, 7) ; //!< YModeProb[0] 9406 uint32_t Ymodeprob1 : __CODEGEN_BITFIELD( 8, 15) ; //!< YModeProb[1] 9407 uint32_t Ymodeprob2 : __CODEGEN_BITFIELD(16, 23) ; //!< YModeProb[2] 9408 uint32_t Ymodeprob3 : __CODEGEN_BITFIELD(24, 31) ; //!< YModeProb[3] 9409 }; 9410 uint32_t Value; 9411 } DW21; 9412 union 9413 { 9414 //!< DWORD 22 9415 struct 9416 { 9417 uint32_t Uvmodeprob0 : __CODEGEN_BITFIELD( 0, 7) ; //!< UVModeProb[0] 9418 uint32_t Uvmodeprob1 : __CODEGEN_BITFIELD( 8, 15) ; //!< UVModeProb[1] 9419 uint32_t Uvmodeprob2 : __CODEGEN_BITFIELD(16, 23) ; //!< UVModeProb[2] 9420 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9421 }; 9422 uint32_t Value; 9423 } DW22; 9424 union 9425 { 9426 //!< DWORD 23 9427 struct 9428 { 9429 uint32_t Mvupdateprobs00 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][0] 9430 uint32_t Mvupdateprobs01 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][1] 9431 uint32_t Mvupdateprobs02 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][2] 9432 uint32_t Mvupdateprobs03 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][3] 9433 }; 9434 uint32_t Value; 9435 } DW23; 9436 union 9437 { 9438 //!< DWORD 24 9439 struct 9440 { 9441 uint32_t Mvupdateprobs04 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][4] 9442 uint32_t Mvupdateprobs05 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][5] 9443 uint32_t Mvupdateprobs06 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][6] 9444 uint32_t Mvupdateprobs07 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][7] 9445 }; 9446 uint32_t Value; 9447 } DW24; 9448 union 9449 { 9450 //!< DWORD 25 9451 struct 9452 { 9453 uint32_t Mvupdateprobs08 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][8] 9454 uint32_t Mvupdateprobs09 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][9] 9455 uint32_t Mvupdateprobs010 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][10] 9456 uint32_t Mvupdateprobs011 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][11] 9457 }; 9458 uint32_t Value; 9459 } DW25; 9460 union 9461 { 9462 //!< DWORD 26 9463 struct 9464 { 9465 uint32_t Mvupdateprobs012 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][12] 9466 uint32_t Mvupdateprobs013 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][13] 9467 uint32_t Mvupdateprobs014 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][14] 9468 uint32_t Mvupdateprobs015 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][15] 9469 }; 9470 uint32_t Value; 9471 } DW26; 9472 union 9473 { 9474 //!< DWORD 27 9475 struct 9476 { 9477 uint32_t Mvupdateprobs016 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][16] 9478 uint32_t Mvupdateprobs017 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][17] 9479 uint32_t Mvupdateprobs018 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][18] 9480 uint32_t Reserved888 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9481 }; 9482 uint32_t Value; 9483 } DW27; 9484 union 9485 { 9486 //!< DWORD 28 9487 struct 9488 { 9489 uint32_t Mvupdateprobs10 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][0] 9490 uint32_t Mvupdateprobs11 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][1] 9491 uint32_t Mvupdateprobs12 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][2] 9492 uint32_t Mvupdateprobs13 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][3] 9493 }; 9494 uint32_t Value; 9495 } DW28; 9496 union 9497 { 9498 //!< DWORD 29 9499 struct 9500 { 9501 uint32_t Mvupdateprobs14 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][4] 9502 uint32_t Mvupdateprobs15 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][5] 9503 uint32_t Mvupdateprobs16 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][6] 9504 uint32_t Mvupdateprobs17 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][7] 9505 }; 9506 uint32_t Value; 9507 } DW29; 9508 union 9509 { 9510 //!< DWORD 30 9511 struct 9512 { 9513 uint32_t Mvupdateprobs18 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][8] 9514 uint32_t Mvupdateprobs19 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][9] 9515 uint32_t Mvupdateprobs110 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][10] 9516 uint32_t Mvupdateprobs111 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][11] 9517 }; 9518 uint32_t Value; 9519 } DW30; 9520 union 9521 { 9522 //!< DWORD 31 9523 struct 9524 { 9525 uint32_t Mvupdateprobs112 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][12] 9526 uint32_t Mvupdateprobs113 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][13] 9527 uint32_t Mvupdateprobs114 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][14] 9528 uint32_t Mvupdateprobs115 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][15] 9529 }; 9530 uint32_t Value; 9531 } DW31; 9532 union 9533 { 9534 //!< DWORD 32 9535 struct 9536 { 9537 uint32_t Mvupdateprobs116 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][16] 9538 uint32_t Mvupdateprobs117 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][17] 9539 uint32_t Mvupdateprobs118 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][18] 9540 uint32_t Reserved1048 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9541 }; 9542 uint32_t Value; 9543 } DW32; 9544 union 9545 { 9546 //!< DWORD 33 9547 struct 9548 { 9549 uint32_t Reflfdelta0ForIntraFrame : __CODEGEN_BITFIELD( 0, 6) ; //!< RefLFDelta0 (for INTRA FRAME) 9550 uint32_t Reserved1063 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 9551 uint32_t Reflfdelta1ForLastFrame : __CODEGEN_BITFIELD( 8, 14) ; //!< RefLFDelta1 (for LAST FRAME) 9552 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9553 uint32_t Reflfdelta2ForGoldenFrame : __CODEGEN_BITFIELD(16, 22) ; //!< RefLFDelta2 (for GOLDEN FRAME) 9554 uint32_t Reserved1079 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 9555 uint32_t Reflfdelta3ForAltrefFrame : __CODEGEN_BITFIELD(24, 30) ; //!< RefLFDelta3 (for ALTREF FRAME) 9556 uint32_t Reserved1087 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9557 }; 9558 uint32_t Value; 9559 } DW33; 9560 union 9561 { 9562 //!< DWORD 34 9563 struct 9564 { 9565 uint32_t Modelfdelta0ForBPredMode : __CODEGEN_BITFIELD( 0, 6) ; //!< ModeLFDelta0 (for B_PRED mode) 9566 uint32_t Reserved1095 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 9567 uint32_t Modelfdelta1ForZeromvMode : __CODEGEN_BITFIELD( 8, 14) ; //!< ModeLFDelta1(for ZEROMV mode) 9568 uint32_t Reserved1103 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9569 uint32_t Modelfdelta2ForNearestNearAndNewMode : __CODEGEN_BITFIELD(16, 22) ; //!< ModeLFDelta2 (for Nearest, Near and New mode) 9570 uint32_t Reserved1111 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 9571 uint32_t Modelfdelta3ForSplitmvMode : __CODEGEN_BITFIELD(24, 30) ; //!< ModeLFDelta3 (for SPLITMV mode) 9572 uint32_t Reserved1119 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9573 }; 9574 uint32_t Value; 9575 } DW34; 9576 union 9577 { 9578 //!< DWORD 35 9579 struct 9580 { 9581 uint32_t SegmentationIdStreamBaseAddress ; //!< Segmentation ID Stream Base Address 9582 }; 9583 uint32_t Value; 9584 } DW35; 9585 union 9586 { 9587 //!< DWORD 36 9588 struct 9589 { 9590 uint32_t SegmentationIdStreamBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Segmentation ID Stream Base Address [47:32] 9591 uint32_t Reserved1168 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9592 }; 9593 uint32_t Value; 9594 } DW36; 9595 union 9596 { 9597 //!< DWORD 37 9598 struct 9599 { 9600 uint32_t Reserved1184 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 9601 uint32_t CoeffprobabilityStreaminAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< CoeffProbability StreamIn Address - Index to Memory Object Control State (MOCS) Tables 9602 uint32_t SegmentationIdStreamArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9603 uint32_t SegmentationIdStreamMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Segmentation ID Stream - Memory Compression Enable 9604 uint32_t SegmentationIdStreamMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9605 uint32_t Reserved1195 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 9606 uint32_t SegmentationIdStreamTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9607 uint32_t Reserved1199 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9608 }; 9609 uint32_t Value; 9610 } DW37; 9611 9612 //! \name Local enumerations 9613 9614 enum SUB_OPCODE_B 9615 { 9616 SUB_OPCODE_B_MFXVP8PICSTATE = 0, //!< No additional details 9617 }; 9618 9619 enum SUB_OPCODE_A 9620 { 9621 SUB_OPCODE_A_VP8COMMON = 0, //!< No additional details 9622 }; 9623 9624 enum MEDIA_COMMAND_OPCODE 9625 { 9626 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 9627 }; 9628 9629 enum PIPELINE 9630 { 9631 PIPELINE_VIDEOCODEC = 2, //!< No additional details 9632 }; 9633 9634 enum COMMAND_TYPE 9635 { 9636 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9637 }; 9638 9639 //! \brief MC_FILTER_SELECT 9640 //! \details 9641 //! To specify VP8 Profile of operation. 9642 enum MC_FILTER_SELECT 9643 { 9644 MC_FILTER_SELECT_UNNAMED0 = 0, //!< 6-tap filter (regular filter mode) 9645 MC_FILTER_SELECT_UNNAMED1 = 1, //!< 2-tap bilinear filter (simple profile/version mode) 9646 }; 9647 9648 //! \brief CHROMA_FULL_PIXEL_MC_FILTER_MODE 9649 //! \details 9650 //! To specify VP8 Profile of operation. 9651 enum CHROMA_FULL_PIXEL_MC_FILTER_MODE 9652 { 9653 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED0 = 0, //!< Chroma MC filter operates in sub-pixel mode 9654 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED1 = 1, //!< Chroma MC filter only operates in full pixel position, i.e. no sub-pixel interpolation. 9655 }; 9656 9657 //! \brief DBLKFILTERTYPE 9658 //! \details 9659 //! To specify VP8 Profile of operation. 9660 enum DBLKFILTERTYPE 9661 { 9662 DBLKFILTERTYPE_UNNAMED0 = 0, //!< Use a full feature normal deblocking filter 9663 DBLKFILTERTYPE_UNNAMED1 = 1, //!< Use a simple filter for deblocking 9664 }; 9665 9666 enum SKEYFRAMEFLAG 9667 { 9668 SKEYFRAMEFLAG_NON_KEYFRAMEP_FRAME = 0, //!< No additional details 9669 SKEYFRAMEFLAG_KEYFRAMEI_FRAME = 1, //!< No additional details 9670 }; 9671 9672 //! \brief SEGMENTATION_ID_STREAMOUT_ENABLE 9673 //! \details 9674 //! When 0, no output needed. 9675 enum SEGMENTATION_ID_STREAMOUT_ENABLE 9676 { 9677 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTDISABLED = 0, //!< No additional details 9678 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTENABLED = 1, //!< No additional details 9679 }; 9680 9681 //! \brief SEGMENTATION_ID_STREAMIN_ENABLE 9682 //! \details 9683 //! When 0, no input needed. 9684 enum SEGMENTATION_ID_STREAMIN_ENABLE 9685 { 9686 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINDISABLED = 0, //!< No additional details 9687 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINENABLED = 1, //!< No additional details 9688 }; 9689 9690 enum SEGMENT_ENABLE_FLAG 9691 { 9692 SEGMENT_ENABLE_FLAG_UNNAMED0 = 0, //!< Disable Segmentation processing in the current frame 9693 SEGMENT_ENABLE_FLAG_UNNAMED1 = 1, //!< Enable Segmentation processing in the current frame 9694 }; 9695 9696 enum UPDATE_MBSEGMENT_MAP_FLAG 9697 { 9698 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED0 = 0, //!< Disable segmentation update 9699 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED1 = 1, //!< Enable segmentation update, and to enable reading segment_id for each MB. 9700 }; 9701 9702 //! \brief MB_NOCOEFF_SKIPFLAG 9703 //! \details 9704 //! Frame level control if Skip MB (with no non-zero coefficient) is allowed 9705 //! or not. 9706 enum MB_NOCOEFF_SKIPFLAG 9707 { 9708 MB_NOCOEFF_SKIPFLAG_UNNAMED0 = 0, //!< All MBs will have its MB level signaling mb_skip_coeff forced to 0. That is, no skip of coefficient record in the bitstream (even their values are all 0s) 9709 MB_NOCOEFF_SKIPFLAG_UNNAMED1 = 1, //!< Skip MB is enabled in the per MB record. 9710 }; 9711 9712 enum MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED 9713 { 9714 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED0 = 0, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is disabled. 9715 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED1 = 1, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is enabled. 9716 }; 9717 9718 enum LOG2_NUM_OF_PARTITION 9719 { 9720 LOG2_NUM_OF_PARTITION_1TOKENPARTITION = 0, //!< No additional details 9721 LOG2_NUM_OF_PARTITION_2TOKENPARTITION = 1, //!< No additional details 9722 LOG2_NUM_OF_PARTITION_4TOKENPARTITION = 2, //!< No additional details 9723 LOG2_NUM_OF_PARTITION_8TOKENPARTITION = 3, //!< No additional details 9724 }; 9725 9726 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT0 9727 //! \details 9728 //! There are max 4 segments per frame, each segment can have its own 9729 //! deblocking filter level. When segmentation is disabled, only segment 0 9730 //! parameter is used for the entire frame. 9731 enum DBLKFILTERLEVEL_FOR_SEGMENT0 9732 { 9733 DBLKFILTERLEVEL_FOR_SEGMENT0_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9734 }; 9735 9736 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT1 9737 //! \details 9738 //! There are max 4 segments per frame, each segment can have its own 9739 //! deblocking filter level. When segmentation is disabled, only segment 0 9740 //! parameter is used for the entire frame. 9741 enum DBLKFILTERLEVEL_FOR_SEGMENT1 9742 { 9743 DBLKFILTERLEVEL_FOR_SEGMENT1_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9744 }; 9745 9746 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT2 9747 //! \details 9748 //! There are max 4 segments per frame, each segment can have its own 9749 //! deblocking filter level. When segmentation is disabled, only segment 0 9750 //! parameter is used for the entire frame. 9751 enum DBLKFILTERLEVEL_FOR_SEGMENT2 9752 { 9753 DBLKFILTERLEVEL_FOR_SEGMENT2_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9754 }; 9755 9756 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT3 9757 //! \details 9758 //! There are max 4 segments per frame, each segment can have its own 9759 //! deblocking filter level. When segmentation is disabled, only segment 0 9760 //! parameter is used for the entire frame. 9761 enum DBLKFILTERLEVEL_FOR_SEGMENT3 9762 { 9763 DBLKFILTERLEVEL_FOR_SEGMENT3_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9764 }; 9765 9766 //! \brief COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL 9767 //! \details 9768 //! This field controls the priority of arbitration used in the GAC/GAM 9769 //! pipeline for this surface. 9770 enum COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL 9771 { 9772 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9773 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9774 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9775 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9776 }; 9777 9778 //! \brief COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE 9779 //! \details 9780 //! Distinguishes Vertical from Horizontal compression. Please refer to 9781 //! vol1a 9782 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 9783 //! section for more details. 9784 enum COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE 9785 { 9786 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 9787 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 9788 }; 9789 9790 //! \brief COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE 9791 //! \details 9792 //! <b>For Media Surfaces:</b> 9793 //! This field specifies the tiled resource mode. 9794 enum COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE 9795 { 9796 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 9797 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 9798 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 9799 }; 9800 9801 //! \brief SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9802 //! \details 9803 //! This field controls the priority of arbitration used in the GAC/GAM 9804 //! pipeline for this surface. 9805 enum SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9806 { 9807 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9808 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9809 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9810 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9811 }; 9812 9813 //! \brief SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9814 //! \details 9815 //! Distinguishes Vertical from Horizontal compression. Please refer to 9816 //! vol1a 9817 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 9818 //! section for more details. 9819 enum SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9820 { 9821 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 9822 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 9823 }; 9824 9825 //! \brief SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9826 //! \details 9827 //! <b>For Media Surfaces:</b> 9828 //! This field specifies the tiled resource mode. 9829 enum SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9830 { 9831 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 9832 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 9833 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 9834 }; 9835 9836 //! \name Initializations 9837 9838 //! \brief Explicit member initialization function 9839 MFX_VP8_PIC_STATE_CMD(); 9840 9841 static const size_t dwSize = 38; 9842 static const size_t byteSize = 152; 9843 }; 9844 9845 //! 9846 //! \brief MFX_JPEG_HUFF_TABLE_STATE 9847 //! \details 9848 //! This Huffman table commands contains both DC and AC tables for either 9849 //! luma or chroma. Once a Huffman table has been defined for a particular 9850 //! destination, it replaces the previous tables stored in that destination 9851 //! and shall be used in the remaining Scans of the current image. A Huffman 9852 //! table will be sent to H/W only when it is loaded from bitstream. 9853 //! 9854 struct MFX_JPEG_HUFF_TABLE_STATE_CMD 9855 { 9856 union 9857 { 9858 //!< DWORD 0 9859 struct 9860 { 9861 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 9862 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 9863 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 9864 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 9865 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 9866 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 9867 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 9868 }; 9869 uint32_t Value; 9870 } DW0; 9871 union 9872 { 9873 //!< DWORD 1 9874 struct 9875 { 9876 uint32_t Hufftableid1Bit : __CODEGEN_BITFIELD( 0, 0) ; //!< HUFFTABLEID_1_BIT 9877 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 9878 }; 9879 uint32_t Value; 9880 } DW1; 9881 9882 uint32_t DcBits128BitArray[3]; //!< DC_BITS (12 8-bit array) 9883 9884 uint32_t DcHuffval128BitArray[3]; //!< DC_HUFFVAL (12 8-bit array) 9885 9886 uint32_t AcBits168BitArray[4]; //!< AC_BITS (16 8-bit array) 9887 9888 uint32_t AcHuffval1608BitArray[40]; //!< AC_HUFFVAL (160 8-bit array) 9889 9890 union 9891 { 9892 //!< DWORD 52 9893 struct 9894 { 9895 uint32_t AcHuffval28BitArray : __CODEGEN_BITFIELD( 0, 15) ; //!< AC_HUFFVAL(2-8 bit array) 9896 uint32_t Reserved1680 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9897 }; 9898 uint32_t Value; 9899 } DW52; 9900 9901 //! \name Local enumerations 9902 9903 enum SUBOPCODE_B 9904 { 9905 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 9906 }; 9907 9908 enum SUBOPCODE_A 9909 { 9910 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 9911 }; 9912 9913 enum MEDIA_COMMAND_OPCODE 9914 { 9915 MEDIA_COMMAND_OPCODE_JPEGCOMMON = 7, //!< No additional details 9916 }; 9917 9918 enum PIPELINE 9919 { 9920 PIPELINE_MFXMULTIDW = 2, //!< No additional details 9921 }; 9922 9923 enum COMMAND_TYPE 9924 { 9925 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9926 }; 9927 9928 //! \brief HUFFTABLEID_1_BIT 9929 //! \details 9930 //! Identifies the huffman table. 9931 enum HUFFTABLEID_1_BIT 9932 { 9933 HUFFTABLEID_1_BIT_Y = 0, //!< Huffman table for Y 9934 }; 9935 9936 //! \name Initializations 9937 9938 //! \brief Explicit member initialization function 9939 MFX_JPEG_HUFF_TABLE_STATE_CMD(); 9940 9941 static const size_t dwSize = 53; 9942 static const size_t byteSize = 212; 9943 }; 9944 9945 //! 9946 //! \brief GRAPHICSADDRESS63_6 9947 //! \details 9948 //! This structure is intended to define the upper bits of the 9949 //! GraphicsAddress, when bits 5:0 are already defined in the referring 9950 //! register. So bit 0 of this structure should correspond to bit 6 of the 9951 //! full GraphicsAddress. 9952 //! 9953 struct GRAPHICSADDRESS63_6_CMD 9954 { 9955 union 9956 { 9957 //!< DWORD 0..1 9958 struct 9959 { 9960 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 9961 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD( 6, 47) ; //!< GraphicsAddress47-6 9962 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 9963 }; 9964 uint32_t Value[2]; 9965 } DW0_1; 9966 9967 //! \name Local enumerations 9968 9969 //! \name Initializations 9970 9971 //! \brief Explicit member initialization function 9972 GRAPHICSADDRESS63_6_CMD(); 9973 9974 static const size_t dwSize = 2; 9975 static const size_t byteSize = 8; 9976 }; 9977 9978 //! 9979 //! \brief MFX_PIPE_BUF_ADDR_STATE 9980 //! \details 9981 //! This state command provides the memory base addresses for all row 9982 //! stores, StreamOut buffer and reconstructed picture output buffers 9983 //! required by the MFD or MFC Engine (that are in addition to the row 9984 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 9985 //! reference picture buffers). 9986 //! This is a picture level state command and is common among all codec 9987 //! standards and for both encoder and decoder operating modes. However, 9988 //! some fields may only applicable to a specific codec standard. All Pixel 9989 //! Surfaces (original, reference frame and reconstructed frame) in the 9990 //! Encoder are programmed with the same surface state (NV12 and TileY 9991 //! format), except each has its own frame buffer base address. In the tile 9992 //! format, there is no need to provide buffer offset for each slice; since 9993 //! from each MB address, the hardware can calculated the corresponding 9994 //! memory location within the frame buffer directly. 9995 //! 9996 struct MFX_PIPE_BUF_ADDR_STATE_CMD 9997 { 9998 union 9999 { 10000 //!< DWORD 0 10001 struct 10002 { 10003 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 10004 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 10005 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 10006 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 10007 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMON_OPCODE 10008 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 10009 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 10010 }; 10011 uint32_t Value; 10012 } DW0; 10013 union 10014 { 10015 //!< DWORD 1 10016 struct 10017 { 10018 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10019 uint32_t PreDeblockingDestinationAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Pre Deblocking Destination Address 10020 }; 10021 uint32_t Value; 10022 } DW1; 10023 union 10024 { 10025 //!< DWORD 2 10026 struct 10027 { 10028 uint32_t PreDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Pre Deblocking Destination Address High 10029 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10030 }; 10031 uint32_t Value; 10032 } DW2; 10033 union 10034 { 10035 //!< DWORD 3 10036 struct 10037 { 10038 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10039 uint32_t PreDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10040 uint32_t PreDeblockingMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10041 uint32_t PreDeblockingMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< Pre Deblocking - Memory Compression Mode 10042 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10043 uint32_t PreDeblockingTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< PRE_DEBLOCKING__TILED_RESOURCE_MODE 10044 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10045 }; 10046 uint32_t Value; 10047 } DW3; 10048 union 10049 { 10050 //!< DWORD 4 10051 struct 10052 { 10053 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10054 uint32_t PostDeblockingDestinationAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Post Deblocking Destination Address 10055 }; 10056 uint32_t Value; 10057 } DW4; 10058 union 10059 { 10060 //!< DWORD 5 10061 struct 10062 { 10063 uint32_t PostDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Post Deblocking Destination Address High 10064 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10065 }; 10066 uint32_t Value; 10067 } DW5; 10068 union 10069 { 10070 //!< DWORD 6 10071 struct 10072 { 10073 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10074 uint32_t PostDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10075 uint32_t PostDeblockingMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10076 uint32_t PostDeblockingMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10077 uint32_t Reserved203 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10078 uint32_t PostDeblockingTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< POST_DEBLOCKING__TILED_RESOURCE_MODE 10079 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10080 }; 10081 uint32_t Value; 10082 } DW6; 10083 union 10084 { 10085 //!< DWORD 7 10086 struct 10087 { 10088 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10089 uint32_t OriginalUncompressedPictureSourceAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Original Uncompressed Picture Source Address 10090 }; 10091 uint32_t Value; 10092 } DW7; 10093 union 10094 { 10095 //!< DWORD 8 10096 struct 10097 { 10098 uint32_t OriginalUncompressedPictureSourceAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Original Uncompressed Picture Source Address High 10099 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10100 }; 10101 uint32_t Value; 10102 } DW8; 10103 union 10104 { 10105 //!< DWORD 9 10106 struct 10107 { 10108 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10109 uint32_t OriginalUncompressedPictureSourceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10110 uint32_t OriginalUncompressedPictureMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10111 uint32_t OriginalUncompressedPictureMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10112 uint32_t Reserved299 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10113 uint32_t OriginalUncompressedPictureTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10114 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10115 }; 10116 uint32_t Value; 10117 } DW9; 10118 union 10119 { 10120 //!< DWORD 10 10121 struct 10122 { 10123 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10124 uint32_t StreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< StreamOut Data Destination Base Address 10125 }; 10126 uint32_t Value; 10127 } DW10; 10128 union 10129 { 10130 //!< DWORD 11 10131 struct 10132 { 10133 uint32_t StreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< StreamOut Data Destination Base Address High 10134 uint32_t Reserved368 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10135 }; 10136 uint32_t Value; 10137 } DW11; 10138 union 10139 { 10140 //!< DWORD 12 10141 struct 10142 { 10143 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10144 uint32_t StreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10145 uint32_t StreamoutDataDestinationMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10146 uint32_t StreamoutDataDestinationMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10147 uint32_t Reserved395 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10148 uint32_t StreamoutDataDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10149 uint32_t Reserved399 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10150 }; 10151 uint32_t Value; 10152 } DW12; 10153 union 10154 { 10155 //!< DWORD 13 10156 struct 10157 { 10158 uint32_t Reserved416 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10159 uint32_t IntraRowStoreScratchBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Intra Row Store Scratch Buffer Base Address 10160 }; 10161 uint32_t Value; 10162 } DW13; 10163 union 10164 { 10165 //!< DWORD 14 10166 struct 10167 { 10168 uint32_t IntraRowStoreScratchBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra Row Store Scratch Buffer Base Address High 10169 uint32_t Reserved464 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10170 }; 10171 uint32_t Value; 10172 } DW14; 10173 union 10174 { 10175 //!< DWORD 15 10176 struct 10177 { 10178 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10179 uint32_t IntraRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10180 uint32_t IntraRowStoreScratchBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10181 uint32_t IntraRowStoreScratchBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10182 uint32_t Reserved491 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 10183 uint32_t IntraRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10184 uint32_t IntraRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10185 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10186 }; 10187 uint32_t Value; 10188 } DW15; 10189 union 10190 { 10191 //!< DWORD 16 10192 struct 10193 { 10194 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10195 uint32_t DeblockingFilterRowStoreScratchBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Deblocking Filter Row Store Scratch Base Address 10196 }; 10197 uint32_t Value; 10198 } DW16; 10199 union 10200 { 10201 //!< DWORD 17 10202 struct 10203 { 10204 uint32_t DeblockingFilterRowStoreScratchBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Deblocking Filter Row Store Scratch Base Address High 10205 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10206 }; 10207 uint32_t Value; 10208 } DW17; 10209 union 10210 { 10211 //!< DWORD 18 10212 struct 10213 { 10214 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10215 uint32_t DeblockingFilterRowStoreScratchArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10216 uint32_t DeblockingFilterRowStoreScratchMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10217 uint32_t DeblockingFilterRowStoreScratchMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10218 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 10219 uint32_t DeblockingFilterRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10220 uint32_t DeblockingFilterRowStoreTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10221 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10222 }; 10223 uint32_t Value; 10224 } DW18; 10225 10226 mhw_vdbox_mfx_g9_skl::GRAPHICSADDRESS63_6_CMD Refpicbaseaddr[16]; //!< RefPicBaseAddr 10227 10228 union 10229 { 10230 //!< DWORD 51 10231 struct 10232 { 10233 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10234 uint32_t ReferencePictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10235 uint32_t Reserved1641 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 10236 uint32_t ReferencePictureTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< REFERENCE_PICTURE__TILED_RESOURCE_MODE 10237 uint32_t Reserved1647 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10238 }; 10239 uint32_t Value; 10240 } DW51; 10241 union 10242 { 10243 //!< DWORD 52 10244 struct 10245 { 10246 uint32_t Reserved1664 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10247 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address 10248 }; 10249 uint32_t Value; 10250 } DW52; 10251 union 10252 { 10253 //!< DWORD 53 10254 struct 10255 { 10256 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address High 10257 uint32_t Reserved1712 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10258 }; 10259 uint32_t Value; 10260 } DW53; 10261 union 10262 { 10263 //!< DWORD 54 10264 struct 10265 { 10266 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10267 uint32_t MacroblockStatusBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10268 uint32_t MacroblockStatusBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10269 uint32_t MacroblockStatusBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10270 uint32_t Reserved1739 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10271 uint32_t MacroblockStatusBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10272 uint32_t Reserved1743 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10273 }; 10274 uint32_t Value; 10275 } DW54; 10276 union 10277 { 10278 //!< DWORD 55 10279 struct 10280 { 10281 uint32_t Reserved1760 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10282 uint32_t MacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Macroblock ILDB StreamOut Buffer Base Address 10283 }; 10284 uint32_t Value; 10285 } DW55; 10286 union 10287 { 10288 //!< DWORD 56 10289 struct 10290 { 10291 uint32_t MacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock ILDB StreamOut Buffer Base Address High 10292 uint32_t Reserved1808 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10293 }; 10294 uint32_t Value; 10295 } DW56; 10296 union 10297 { 10298 //!< DWORD 57 10299 struct 10300 { 10301 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10302 uint32_t MacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10303 uint32_t MacroblockIldbStreamoutBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10304 uint32_t MacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10305 uint32_t Reserved1835 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10306 uint32_t MacroblockIldbStreamoutTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10307 uint32_t Reserved1839 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10308 }; 10309 uint32_t Value; 10310 } DW57; 10311 union 10312 { 10313 //!< DWORD 58 10314 struct 10315 { 10316 uint32_t Reserved1856 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10317 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Second Macroblock ILDB StreamOut Buffer Base Address 10318 }; 10319 uint32_t Value; 10320 } DW58; 10321 union 10322 { 10323 //!< DWORD 59 10324 struct 10325 { 10326 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Second Macroblock ILDB StreamOut Buffer Base Address High 10327 uint32_t Reserved1904 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10328 }; 10329 uint32_t Value; 10330 } DW59; 10331 union 10332 { 10333 //!< DWORD 60 10334 struct 10335 { 10336 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10337 uint32_t SecondMacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Second Macroblock ILDB StreamOut Buffer - Arbitration Priority Control 10338 uint32_t SecondMacroblockIldbStreamoutBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10339 uint32_t SecondMacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10340 uint32_t Reserved1931 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10341 uint32_t SecondMacroblockIldbStreamoutBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 10342 uint32_t Reserved1935 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10343 }; 10344 uint32_t Value; 10345 } DW60; 10346 union 10347 { 10348 //!< DWORD 61 10349 struct 10350 { 10351 uint32_t ReferencePicture0MemoryCompressionEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< REFERENCE_PICTURE_0__MEMORY_COMPRESSION_ENABLE 10352 uint32_t ReferencePicture0MemoryCompressionMode : __CODEGEN_BITFIELD( 1, 1) ; //!< REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 10353 uint32_t ReferencePicture1MemoryCompressionEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< REFERENCE_PICTURE_1__MEMORY_COMPRESSION_ENABLE 10354 uint32_t ReferencePicture1MemoryCompressionMode : __CODEGEN_BITFIELD( 3, 3) ; //!< REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 10355 uint32_t ReferencePicture2MemoryCompressionEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< REFERENCE_PICTURE_2__MEMORY_COMPRESSION_ENABLE 10356 uint32_t ReferencePicture2MemoryCompressionMode : __CODEGEN_BITFIELD( 5, 5) ; //!< REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 10357 uint32_t ReferencePicture3MemoryCompressionEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< REFERENCE_PICTURE_3__MEMORY_COMPRESSION_ENABLE 10358 uint32_t ReferencePicture3MemoryCompressionMode : __CODEGEN_BITFIELD( 7, 7) ; //!< REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 10359 uint32_t ReferencePicture4MemoryCompressionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< REFERENCE_PICTURE_4__MEMORY_COMPRESSION_ENABLE 10360 uint32_t ReferencePicture4MemoryCompressionMode : __CODEGEN_BITFIELD( 9, 9) ; //!< REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 10361 uint32_t ReferencePicture5MemoryCompressionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< REFERENCE_PICTURE_5__MEMORY_COMPRESSION_ENABLE 10362 uint32_t ReferencePicture5MemoryCompressionMode : __CODEGEN_BITFIELD(11, 11) ; //!< REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 10363 uint32_t ReferencePicture6MemoryCompressionEnable : __CODEGEN_BITFIELD(12, 12) ; //!< REFERENCE_PICTURE_6__MEMORY_COMPRESSION_ENABLE 10364 uint32_t ReferencePicture6MemoryCompressionMode : __CODEGEN_BITFIELD(13, 13) ; //!< REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 10365 uint32_t ReferencePicture7MemoryCompressionEnable : __CODEGEN_BITFIELD(14, 14) ; //!< REFERENCE_PICTURE_7__MEMORY_COMPRESSION_ENABLE 10366 uint32_t ReferencePicture7MemoryCompressionMode : __CODEGEN_BITFIELD(15, 15) ; //!< REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 10367 uint32_t ReferencePicture8MemoryCompressionEnable : __CODEGEN_BITFIELD(16, 16) ; //!< REFERENCE_PICTURE_8__MEMORY_COMPRESSION_ENABLE 10368 uint32_t ReferencePicture8MemoryCompressionMode : __CODEGEN_BITFIELD(17, 17) ; //!< REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 10369 uint32_t ReferencePicture9MemoryCompressionEnable : __CODEGEN_BITFIELD(18, 18) ; //!< REFERENCE_PICTURE_9__MEMORY_COMPRESSION_ENABLE 10370 uint32_t ReferencePicture9MemoryCompressionMode : __CODEGEN_BITFIELD(19, 19) ; //!< REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 10371 uint32_t ReferencePicture10MemoryCompressionEnable : __CODEGEN_BITFIELD(20, 20) ; //!< REFERENCE_PICTURE_10__MEMORY_COMPRESSION_ENABLE 10372 uint32_t ReferencePicture10MemoryCompressionMode : __CODEGEN_BITFIELD(21, 21) ; //!< REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 10373 uint32_t ReferencePicture11MemoryCompressionEnable : __CODEGEN_BITFIELD(22, 22) ; //!< REFERENCE_PICTURE_11__MEMORY_COMPRESSION_ENABLE 10374 uint32_t ReferencePicture11MemoryCompressionMode : __CODEGEN_BITFIELD(23, 23) ; //!< REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 10375 uint32_t ReferencePicture12MemoryCompressionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< REFERENCE_PICTURE_12__MEMORY_COMPRESSION_ENABLE 10376 uint32_t ReferencePicture12MemoryCompressionMode : __CODEGEN_BITFIELD(25, 25) ; //!< REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 10377 uint32_t ReferencePicture13MemoryCompressionEnable : __CODEGEN_BITFIELD(26, 26) ; //!< REFERENCE_PICTURE_13__MEMORY_COMPRESSION_ENABLE 10378 uint32_t ReferencePicture13MemoryCompressionMode : __CODEGEN_BITFIELD(27, 27) ; //!< REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 10379 uint32_t ReferencePicture14MemoryCompressionEnable : __CODEGEN_BITFIELD(28, 28) ; //!< REFERENCE_PICTURE_14__MEMORY_COMPRESSION_ENABLE 10380 uint32_t ReferencePicture14MemoryCompressionMode : __CODEGEN_BITFIELD(29, 29) ; //!< REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 10381 uint32_t ReferencePicture15MemoryCompressionEnable : __CODEGEN_BITFIELD(30, 30) ; //!< REFERENCE_PICTURE_15__MEMORY_COMPRESSION_ENABLE 10382 uint32_t ReferencePicture15MemoryCompressionMode : __CODEGEN_BITFIELD(31, 31) ; //!< REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 10383 }; 10384 uint32_t Value; 10385 } DW61; 10386 union 10387 { 10388 //!< DWORD 62 10389 struct 10390 { 10391 uint32_t Reserved1984 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10392 uint32_t ScaledReferenceSurfaceBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Scaled Reference Surface Base Address 10393 }; 10394 uint32_t Value; 10395 } DW62; 10396 union 10397 { 10398 //!< DWORD 63 10399 struct 10400 { 10401 uint32_t ScaledReferenceSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Scaled Reference Surface Base Address High 10402 uint32_t Reserved2032 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10403 }; 10404 uint32_t Value; 10405 } DW63; 10406 union 10407 { 10408 //!< DWORD 64 10409 struct 10410 { 10411 uint32_t Reserved2048 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 10412 uint32_t ScaledReferenceSurfaceIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Scaled Reference Surface - Index to Memory Object Control State (MOCS) Tables 10413 uint32_t ScaleReferenceSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 10414 uint32_t ScaledReferenceSurfaceMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Scaled Reference Surface - Memory Compression Enable 10415 uint32_t ScaledReferenceSurfaceMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 10416 uint32_t Reserved2059 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10417 uint32_t ScaledReferenceSurfaceTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 10418 uint32_t Reserved2063 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10419 }; 10420 uint32_t Value; 10421 } DW64; 10422 10423 //! \name Local enumerations 10424 10425 enum SUBOPCODE_B 10426 { 10427 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 10428 }; 10429 10430 enum SUBOPCODE_A 10431 { 10432 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 10433 }; 10434 10435 enum COMMON_OPCODE 10436 { 10437 COMMON_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 10438 }; 10439 10440 enum PIPELINE 10441 { 10442 PIPELINE_MFXPIPEBUFADDRSTATE = 2, //!< No additional details 10443 }; 10444 10445 enum COMMAND_TYPE 10446 { 10447 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 10448 }; 10449 10450 //! \brief PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10451 //! \details 10452 //! This field controls the priority of arbitration used in the GAC/GAM 10453 //! pipeline for this surface. 10454 enum PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10455 { 10456 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10457 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10458 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10459 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10460 }; 10461 10462 //! \brief PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10463 //! \details 10464 //! Memory compression will be attempted for this surface. 10465 enum PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10466 { 10467 PRE_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10468 PRE_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10469 }; 10470 10471 //! \brief PRE_DEBLOCKING__TILED_RESOURCE_MODE 10472 //! \details 10473 //! <b>For Media Surfaces:</b> 10474 //! This field specifies the tiled resource mode. 10475 enum PRE_DEBLOCKING__TILED_RESOURCE_MODE 10476 { 10477 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10478 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10479 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10480 }; 10481 10482 //! \brief POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10483 //! \details 10484 //! This field controls the priority of arbitration used in the GAC/GAM 10485 //! pipeline for this surface. 10486 enum POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10487 { 10488 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10489 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10490 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10491 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10492 }; 10493 10494 //! \brief POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10495 //! \details 10496 //! Memory compression will be attempted for this surface. 10497 enum POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10498 { 10499 POST_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10500 POST_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10501 }; 10502 10503 //! \brief POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10504 //! \details 10505 //! Distinguishes Vertical from Horizontal compression. Please refer to 10506 //! vol1a <b>Memory Data Formats chapter -section</b> Media Memory 10507 //! Compression <b>for more details.</b> 10508 enum POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10509 { 10510 POST_DEBLOCKING_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10511 }; 10512 10513 //! \brief POST_DEBLOCKING__TILED_RESOURCE_MODE 10514 //! \details 10515 //! <b>For Media Surfaces:</b> 10516 //! This field specifies the tiled resource mode. 10517 enum POST_DEBLOCKING__TILED_RESOURCE_MODE 10518 { 10519 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10520 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10521 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10522 }; 10523 10524 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10525 //! \details 10526 //! This field controls the priority of arbitration used in the GAC/GAM 10527 //! pipeline for this surface. 10528 enum ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10529 { 10530 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10531 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10532 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10533 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10534 }; 10535 10536 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10537 //! \details 10538 //! Note: This is a READ Surface. The setting of this bit should match the 10539 //! settings on how this is written out before. 10540 enum ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10541 { 10542 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10543 }; 10544 10545 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10546 //! \details 10547 //! Distinguishes Vertical from Horizontal compression. Please refer to 10548 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10549 //! more details. Note: This bit is not used unless Memory Compression 10550 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10551 //! bit should match the settings on how this is written out before 10552 enum ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10553 { 10554 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10555 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10556 }; 10557 10558 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10559 //! \details 10560 //! <b>For Media Surfaces:</b> 10561 //! This field specifies the tiled resource mode. 10562 enum ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10563 { 10564 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10565 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10566 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10567 }; 10568 10569 //! \brief STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10570 //! \details 10571 //! This field controls the priority of arbitration used in the GAC/GAM 10572 //! pipeline for this surface. 10573 enum STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10574 { 10575 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10576 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10577 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10578 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10579 }; 10580 10581 //! \brief STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10582 //! \details 10583 //! Note: This is a READ Surface. The setting of this bit should match the 10584 //! settings on how this is written out before. 10585 enum STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10586 { 10587 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10588 }; 10589 10590 //! \brief STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10591 //! \details 10592 //! Distinguishes Vertical from Horizontal compression. Please refer to 10593 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10594 //! more details. Note: This bit is not used unless Memory Compression 10595 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10596 //! bit should match the settings on how this is written out before 10597 enum STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10598 { 10599 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10600 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10601 }; 10602 10603 //! \brief STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10604 //! \details 10605 //! <b>For Media Surfaces:</b> 10606 //! This field specifies the tiled resource mode. 10607 enum STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10608 { 10609 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10610 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10611 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10612 }; 10613 10614 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10615 //! \details 10616 //! This field controls the priority of arbitration used in the GAC/GAM 10617 //! pipeline for this surface. 10618 enum INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10619 { 10620 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10621 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10622 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10623 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10624 }; 10625 10626 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10627 //! \details 10628 //! This surface is linear surface. This bit must be set to "0" since only 10629 //! TileY/TileYf/TileYs surface is allowed to be compressed 10630 enum INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10631 { 10632 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10633 }; 10634 10635 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10636 //! \details 10637 //! Distinguishes Vertical from Horizontal compression. Please refer to 10638 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10639 //! more details. Note: This bit is not used unless Memory Compression 10640 //! Enable is set to "1" 10641 enum INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10642 { 10643 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10644 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10645 }; 10646 10647 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10648 //! \details 10649 //! This field controls if Intra Row Store is going to store inside Media 10650 //! Cache or to LLC. 10651 enum INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10652 { 10653 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 10654 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 10655 }; 10656 10657 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10658 //! \details 10659 //! <b>For Media Surfaces:</b> 10660 //! This field specifies the tiled resource mode. 10661 enum INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10662 { 10663 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10664 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10665 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10666 }; 10667 10668 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10669 //! \details 10670 //! This field controls the priority of arbitration used in the GAC/GAM 10671 //! pipeline for this surface. 10672 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10673 { 10674 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10675 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10676 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10677 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10678 }; 10679 10680 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10681 //! \details 10682 //! This surface is linear surface. This bit must be set to "0" since only 10683 //! TileY/TileYf/TileYs surface is allowed to be compressed 10684 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10685 { 10686 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10687 }; 10688 10689 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10690 //! \details 10691 //! Distinguishes Vertical from Horizontal compression. Please refer to 10692 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10693 //! more details. Note: This bit is not used unless Memory Compression 10694 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10695 //! bit should match the settings on how this is written out before. 10696 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10697 { 10698 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10699 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10700 }; 10701 10702 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10703 //! \details 10704 //! This field controls if Intra Row Store is going to store inside Media 10705 //! Internal Storage or to LLC. 10706 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10707 { 10708 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 10709 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Media Internal Storage 10710 }; 10711 10712 //! \brief DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10713 //! \details 10714 //! <b>For Media Surfaces:</b> 10715 //! This field specifies the tiled resource mode. 10716 enum DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10717 { 10718 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10719 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10720 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10721 }; 10722 10723 //! \brief REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10724 //! \details 10725 //! This field controls the priority of arbitration used in the GAC/GAM 10726 //! pipeline for this surface. 10727 enum REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10728 { 10729 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10730 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10731 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10732 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10733 }; 10734 10735 //! \brief REFERENCE_PICTURE__TILED_RESOURCE_MODE 10736 //! \details 10737 //! <b>For Media Surfaces:</b> 10738 //! This field specifies the tiled resource mode. 10739 enum REFERENCE_PICTURE__TILED_RESOURCE_MODE 10740 { 10741 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10742 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10743 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10744 }; 10745 10746 //! \brief MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10747 //! \details 10748 //! This field controls the priority of arbitration used in the GAC/GAM 10749 //! pipeline for this surface. 10750 enum MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10751 { 10752 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10753 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10754 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10755 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10756 }; 10757 10758 //! \brief MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10759 //! \details 10760 //! This surface is linear surface. This bit must be set to "0" since only 10761 //! TileY/TileYf/TileYs surface is allowed to be compressed 10762 enum MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10763 { 10764 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10765 }; 10766 10767 //! \brief MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10768 //! \details 10769 //! Distinguishes Vertical from Horizontal compression. Please refer to 10770 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10771 //! more details. Note: This bit is not used unless Memory Compression 10772 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10773 //! bit should match the settings on how this is written out before. 10774 enum MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10775 { 10776 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10777 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10778 }; 10779 10780 //! \brief MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10781 //! \details 10782 //! <b>For Media Surfaces:</b> 10783 //! This field specifies the tiled resource mode. 10784 enum MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10785 { 10786 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10787 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10788 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10789 }; 10790 10791 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10792 //! \details 10793 //! This field controls the priority of arbitration used in the GAC/GAM 10794 //! pipeline for this surface. 10795 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10796 { 10797 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10798 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10799 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10800 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10801 }; 10802 10803 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10804 //! \details 10805 //! This surface is linear surface. This bit must be set to "0" since only 10806 //! TileY/TileYf/TileYs surface is allowed to be compressed 10807 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10808 { 10809 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10810 }; 10811 10812 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10813 //! \details 10814 //! Distinguishes Vertical from Horizontal compression. Please refer to 10815 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10816 //! more details. Note: This bit is not used unless Memory Compression 10817 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10818 //! bit should match the settings on how this is written out before. 10819 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10820 { 10821 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10822 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10823 }; 10824 10825 //! \brief MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10826 //! \details 10827 //! <b>For Media Surfaces:</b> 10828 //! This field specifies the tiled resource mode. 10829 enum MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10830 { 10831 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10832 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10833 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10834 }; 10835 10836 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10837 //! \details 10838 //! This surface is linear surface. This bit must be set to "0" since only 10839 //! TileY/TileYf/TileYs surface is allowed to be compressed 10840 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10841 { 10842 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10843 }; 10844 10845 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10846 //! \details 10847 //! Distinguishes Vertical from Horizontal compression. Please refer to 10848 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10849 //! more details. Note: This bit is not used unless Memory Compression 10850 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10851 //! bit should match the settings on how this is written out before. 10852 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10853 { 10854 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10855 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10856 }; 10857 10858 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 10859 //! \details 10860 //! <b>For Media Surfaces:</b> 10861 //! This field specifies the tiled resource mode. 10862 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 10863 { 10864 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10865 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10866 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10867 }; 10868 10869 enum REFERENCE_PICTURE_0__MEMORY_COMPRESSION_ENABLE 10870 { 10871 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10872 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10873 }; 10874 10875 //! \brief REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 10876 //! \details 10877 //! Distinguishes Vertical from Horizontal compression. Please refer to 10878 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10879 //! more details. Note: This bit is not used unless Memory Compression 10880 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10881 //! bit should match the settings on how this is written out before. 10882 enum REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 10883 { 10884 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10885 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10886 }; 10887 10888 enum REFERENCE_PICTURE_1__MEMORY_COMPRESSION_ENABLE 10889 { 10890 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10891 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10892 }; 10893 10894 //! \brief REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 10895 //! \details 10896 //! Distinguishes Vertical from Horizontal compression. Please refer to 10897 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10898 //! more details. Note: This bit is not used unless Memory Compression 10899 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10900 //! bit should match the settings on how this is written out before. 10901 enum REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 10902 { 10903 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10904 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10905 }; 10906 10907 enum REFERENCE_PICTURE_2__MEMORY_COMPRESSION_ENABLE 10908 { 10909 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10910 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10911 }; 10912 10913 //! \brief REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 10914 //! \details 10915 //! Distinguishes Vertical from Horizontal compression. Please refer to 10916 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10917 //! more details. Note: This bit is not used unless Memory Compression 10918 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10919 //! bit should match the settings on how this is written out before. 10920 enum REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 10921 { 10922 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10923 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10924 }; 10925 10926 enum REFERENCE_PICTURE_3__MEMORY_COMPRESSION_ENABLE 10927 { 10928 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10929 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10930 }; 10931 10932 //! \brief REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 10933 //! \details 10934 //! Distinguishes Vertical from Horizontal compression. Please refer to 10935 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10936 //! more details. Note: This bit is not used unless Memory Compression 10937 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10938 //! bit should match the settings on how this is written out before. 10939 enum REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 10940 { 10941 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10942 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10943 }; 10944 10945 enum REFERENCE_PICTURE_4__MEMORY_COMPRESSION_ENABLE 10946 { 10947 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10948 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10949 }; 10950 10951 //! \brief REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 10952 //! \details 10953 //! Distinguishes Vertical from Horizontal compression. Please refer to 10954 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10955 //! more details. Note: This bit is not used unless Memory Compression 10956 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10957 //! bit should match the settings on how this is written out before. 10958 enum REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 10959 { 10960 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10961 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10962 }; 10963 10964 enum REFERENCE_PICTURE_5__MEMORY_COMPRESSION_ENABLE 10965 { 10966 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10967 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10968 }; 10969 10970 //! \brief REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 10971 //! \details 10972 //! Distinguishes Vertical from Horizontal compression. Please refer to 10973 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10974 //! more details. Note: This bit is not used unless Memory Compression 10975 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10976 //! bit should match the settings on how this is written out before. 10977 enum REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 10978 { 10979 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10980 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10981 }; 10982 10983 enum REFERENCE_PICTURE_6__MEMORY_COMPRESSION_ENABLE 10984 { 10985 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10986 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10987 }; 10988 10989 //! \brief REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 10990 //! \details 10991 //! Distinguishes Vertical from Horizontal compression. Please refer to 10992 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10993 //! more details. Note: This bit is not used unless Memory Compression 10994 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10995 //! bit should match the settings on how this is written out before. 10996 enum REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 10997 { 10998 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10999 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11000 }; 11001 11002 enum REFERENCE_PICTURE_7__MEMORY_COMPRESSION_ENABLE 11003 { 11004 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11005 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11006 }; 11007 11008 //! \brief REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 11009 //! \details 11010 //! Distinguishes Vertical from Horizontal compression. Please refer to 11011 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11012 //! more details. Note: This bit is not used unless Memory Compression 11013 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11014 //! bit should match the settings on how this is written out before. 11015 enum REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 11016 { 11017 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11018 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11019 }; 11020 11021 enum REFERENCE_PICTURE_8__MEMORY_COMPRESSION_ENABLE 11022 { 11023 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11024 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11025 }; 11026 11027 //! \brief REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 11028 //! \details 11029 //! Distinguishes Vertical from Horizontal compression. Please refer to 11030 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11031 //! more details. Note: This bit is not used unless Memory Compression 11032 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11033 //! bit should match the settings on how this is written out before. 11034 enum REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 11035 { 11036 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11037 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11038 }; 11039 11040 enum REFERENCE_PICTURE_9__MEMORY_COMPRESSION_ENABLE 11041 { 11042 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11043 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11044 }; 11045 11046 //! \brief REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 11047 //! \details 11048 //! Distinguishes Vertical from Horizontal compression. Please refer to 11049 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11050 //! more details. Note: This bit is not used unless Memory Compression 11051 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11052 //! bit should match the settings on how this is written out before. 11053 enum REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 11054 { 11055 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11056 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11057 }; 11058 11059 enum REFERENCE_PICTURE_10__MEMORY_COMPRESSION_ENABLE 11060 { 11061 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11062 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11063 }; 11064 11065 //! \brief REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 11066 //! \details 11067 //! Distinguishes Vertical from Horizontal compression. Please refer to 11068 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11069 //! more details. Note: This bit is not used unless Memory Compression 11070 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11071 //! bit should match the settings on how this is written out before. 11072 enum REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 11073 { 11074 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11075 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11076 }; 11077 11078 enum REFERENCE_PICTURE_11__MEMORY_COMPRESSION_ENABLE 11079 { 11080 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11081 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11082 }; 11083 11084 //! \brief REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 11085 //! \details 11086 //! Distinguishes Vertical from Horizontal compression. Please refer to 11087 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11088 //! more details. 11089 //! Note: This bit is not used unless Memory Compression Enable is set 11090 //! to "1" 11091 //! Note: This is a READ Surface. The setting of this bit should 11092 //! match the settings on how this is written out before. 11093 enum REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 11094 { 11095 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11096 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11097 }; 11098 11099 enum REFERENCE_PICTURE_12__MEMORY_COMPRESSION_ENABLE 11100 { 11101 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11102 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11103 }; 11104 11105 //! \brief REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 11106 //! \details 11107 //! Distinguishes Vertical from Horizontal compression. Please refer to 11108 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11109 //! more details. Note: This bit is not used unless Memory Compression 11110 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11111 //! bit should match the settings on how this is written out before. 11112 enum REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 11113 { 11114 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11115 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11116 }; 11117 11118 enum REFERENCE_PICTURE_13__MEMORY_COMPRESSION_ENABLE 11119 { 11120 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11121 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11122 }; 11123 11124 //! \brief REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 11125 //! \details 11126 //! Distinguishes Vertical from Horizontal compression. Please refer to 11127 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11128 //! more details. Note: This bit is not used unless Memory Compression 11129 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11130 //! bit should match the settings on how this is written out before. 11131 enum REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 11132 { 11133 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11134 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11135 }; 11136 11137 enum REFERENCE_PICTURE_14__MEMORY_COMPRESSION_ENABLE 11138 { 11139 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11140 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11141 }; 11142 11143 //! \brief REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 11144 //! \details 11145 //! Distinguishes Vertical from Horizontal compression. Please refer to 11146 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11147 //! more details. Note: This bit is not used unless Memory Compression 11148 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11149 //! bit should match the settings on how this is written out before. 11150 enum REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 11151 { 11152 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11153 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11154 }; 11155 11156 enum REFERENCE_PICTURE_15__MEMORY_COMPRESSION_ENABLE 11157 { 11158 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11159 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11160 }; 11161 11162 //! \brief REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 11163 //! \details 11164 //! Distinguishes Vertical from Horizontal compression. Please refer to 11165 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11166 //! more details. Note: This bit is not used unless Memory Compression 11167 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11168 //! bit should match the settings on how this is written out before. 11169 enum REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 11170 { 11171 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11172 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11173 }; 11174 11175 //! \brief SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 11176 //! \details 11177 //! This field controls the priority of arbitration used in the GAC/GAM 11178 //! pipeline for this surface. 11179 enum SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 11180 { 11181 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11182 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11183 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11184 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11185 }; 11186 11187 //! \brief SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 11188 //! \details 11189 //! Distinguishes Vertical from Horizontal compression. Please refer to 11190 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11191 //! more details. 11192 enum SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 11193 { 11194 SCALED_REFERENCE_SURFACE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11195 SCALED_REFERENCE_SURFACE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11196 }; 11197 11198 //! \brief SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 11199 //! \details 11200 //! For Media Surfaces: 11201 //! This field specifies the tiled resource mode 11202 enum SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 11203 { 11204 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11205 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< No tiled resource 11206 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< No tiled resource 11207 }; 11208 11209 //! \name Initializations 11210 11211 //! \brief Explicit member initialization function 11212 MFX_PIPE_BUF_ADDR_STATE_CMD(); 11213 11214 static const size_t dwSize = 65; 11215 static const size_t byteSize = 260; 11216 }; 11217 11218 //! 11219 //! \brief MFX_AVC_DIRECTMODE_STATE 11220 //! \details 11221 //! This is a picture level command and is issued once per picture. All DMV 11222 //! buffers are treated as standard media surfaces, in which the lower 6 11223 //! bits are used for conveying surface states.Current Pic POC number is 11224 //! assumed to be available in POCList[32 and 33] of the 11225 //! MFX_AVC_DIRECTMODE_STATE Command.This command is only valid in the AVC 11226 //! decoding in VLD and IT modes, and AVC encoder mode. The same command 11227 //! supports both Long and Short AVC Interface. The DMV buffers are 11228 //! not required to be programmed for encoder mode. 11229 //! 11230 struct MFX_AVC_DIRECTMODE_STATE_CMD 11231 { 11232 union 11233 { 11234 //!< DWORD 0 11235 struct 11236 { 11237 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 11238 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 11239 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 11240 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 11241 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 11242 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 11243 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 11244 }; 11245 uint32_t Value; 11246 } DW0; 11247 11248 mhw_vdbox_mfx_g9_skl::GRAPHICSADDRESS63_6_CMD DirectMvBufferBaseAddress[16]; //!< Direct MV Buffer Base Address 11249 11250 union 11251 { 11252 //!< DWORD 33 11253 struct 11254 { 11255 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 11256 uint32_t DirectMvBufferBaseAddressForReferenceFrameArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11257 uint32_t DirectMvBufferBaseAddressForReferenceFrameMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11258 uint32_t DirectMvBufferBaseAddressForReferenceFrameMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11259 uint32_t Reserved1067 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 11260 uint32_t DirectMvBufferBaseAddressForReferenceFrameTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11261 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 11262 }; 11263 uint32_t Value; 11264 } DW33; 11265 11266 mhw_vdbox_mfx_g9_skl::GRAPHICSADDRESS63_6_CMD DirectMvBufferBaseAddressForWrite[1]; //!< Direct MV Buffer Base Address for Write 11267 11268 union 11269 { 11270 //!< DWORD 36 11271 struct 11272 { 11273 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 11274 uint32_t DirectMvBufferBaseAddressForWriteArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11275 uint32_t DirectMvBufferBaseAddressForWriteMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11276 uint32_t DirectMvBufferBaseAddressForWriteMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11277 uint32_t Reserved1163 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 11278 uint32_t DirectMvBufferBaseAddressForWriteTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11279 uint32_t Reserved1167 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 11280 }; 11281 uint32_t Value; 11282 } DW36; 11283 11284 uint32_t PocList[34]; //!< POC List 11285 11286 //! \name Local enumerations 11287 11288 enum SUBOPCODEB 11289 { 11290 SUBOPCODEB_UNNAMED2 = 2, //!< No additional details 11291 }; 11292 11293 enum SUBOPCODEA 11294 { 11295 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 11296 }; 11297 11298 enum MEDIA_COMMAND_OPCODE 11299 { 11300 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 11301 }; 11302 11303 enum PIPELINE 11304 { 11305 PIPELINE_MFXSINGLEDW = 2, //!< No additional details 11306 }; 11307 11308 enum COMMAND_TYPE 11309 { 11310 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 11311 }; 11312 11313 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11314 //! \details 11315 //! This field controls the priority of arbitration used in the GAC/GAM 11316 //! pipeline for this surface. 11317 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11318 { 11319 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11320 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11321 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11322 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11323 }; 11324 11325 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11326 //! \details 11327 //! This surface is linear surface. This bit must be set to "0" since only 11328 //! TileY/TileYf/TileYs surface is allowed to be compressed 11329 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11330 { 11331 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11332 }; 11333 11334 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11335 //! \details 11336 //! Distinguishes Vertical from Horizontal compression. Please refer to 11337 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11338 //! more details. 11339 //! Note: This bit is not used unless Memory Compression Enable is set 11340 //! to "1" 11341 //! Note: This is a READ Surface. The setting of this bit should 11342 //! match the settings on how this is written out before. 11343 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11344 { 11345 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11346 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11347 }; 11348 11349 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11350 //! \details 11351 //! <b>For Media Surfaces:</b> 11352 //! This field specifies the tiled resource mode. 11353 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11354 { 11355 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11356 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11357 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11358 }; 11359 11360 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11361 //! \details 11362 //! This field controls the priority of arbitration used in the GAC/GAM 11363 //! pipeline for this surface. 11364 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11365 { 11366 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11367 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11368 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11369 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11370 }; 11371 11372 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11373 //! \details 11374 //! This surface is linear surface. This bit must be set to "0" since only 11375 //! TileY/TileYf/TileYs surface is allowed to be compressed 11376 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11377 { 11378 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11379 }; 11380 11381 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11382 //! \details 11383 //! Distinguishes Vertical from Horizontal compression. Please refer to 11384 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11385 //! more details. 11386 //! Note: This bit is not used unless Memory Compression Enable is set 11387 //! to "1" 11388 //! Note: This is a READ Surface. The setting of this bit should 11389 //! match the settings on how this is written out before. 11390 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11391 { 11392 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11393 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11394 }; 11395 11396 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11397 //! \details 11398 //! <b>For Media Surfaces:</b> 11399 //! This field specifies the tiled resource mode. 11400 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11401 { 11402 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11403 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11404 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11405 }; 11406 11407 //! \name Initializations 11408 11409 //! \brief Explicit member initialization function 11410 MFX_AVC_DIRECTMODE_STATE_CMD(); 11411 11412 static const size_t dwSize = 71; 11413 static const size_t byteSize = 284; 11414 }; 11415 11416 }; 11417 11418 #pragma pack() 11419 11420 #endif // __MHW_VDBOX_MFX_HWCMD_G9_SKL_H__ 11421