1 /* 2 * Copyright (c) 2017-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_mfx_hwcmd_g12_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g11_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_VDBOX_MFX_HWCMD_G12_X_H__ 29 #define __MHW_VDBOX_MFX_HWCMD_G12_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_vdbox_mfx_g12_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH( x ) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MFX_QM_STATE 50 //! \details 51 //! This is a common state command for AVC encoder modes. For encoder, it 52 //! represents both the forward QM matrices as well as the decoding QM 53 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 54 //! application are being sent to the hardware. The driver is responsible 55 //! for determining the final set of scaling lists to be used for decoding 56 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 57 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 58 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 59 //! order. But the Forward Q scaling lists are sent in column-wise raster 60 //! order (column-by-column) to simplify the H/W. Driver will perform all 61 //! the scan order conversion for both ForwardQ and IQ. 62 //! 63 struct MFX_QM_STATE_CMD 64 { 65 union 66 { 67 //!< DWORD 0 68 struct 69 { 70 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 71 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 72 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 73 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 74 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 75 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 76 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 77 }; 78 uint32_t Value; 79 } DW0; 80 union 81 { 82 //!< DWORD 1 83 struct 84 { 85 uint32_t Avc : __CODEGEN_BITFIELD( 0, 1) ; //!< AVC, AVC- Decoder Only 86 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, AVC- Decoder Only 87 } Obj0; 88 struct 89 { 90 uint32_t Mpeg2 : __CODEGEN_BITFIELD( 0, 1) ; //!< MPEG2, MPEG2- Decoder Only 91 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, MPEG2- Decoder Only 92 } Obj1; 93 struct 94 { 95 uint32_t Jpeg : __CODEGEN_BITFIELD( 0, 1) ; //!< JPEG, JPEG- Encoder Only 96 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 97 }Obj2; 98 uint32_t Value; 99 } DW1; 100 101 uint32_t ForwardQuantizerMatrix[16]; //!< Forward Quantizer Matrix 102 103 104 //! \name Local enumerations 105 106 enum SUBOPCODE_B 107 { 108 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 109 }; 110 111 enum SUBOPCODE_A 112 { 113 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 114 }; 115 116 enum MEDIA_COMMAND_OPCODE 117 { 118 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 119 }; 120 121 enum PIPELINE 122 { 123 PIPELINE_MFXMULTIDW = 2, //!< No additional details 124 }; 125 126 enum COMMAND_TYPE 127 { 128 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 129 }; 130 131 //! \brief AVC 132 //! \details 133 //! <b>For AVC QM Type</b>: This field specifies which Quantizer Matrix is 134 //! loaded. 135 enum AVC 136 { 137 AVC_AVC_4X_4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 138 AVC_AVC_4X_4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 139 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 140 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 141 }; 142 143 //! \brief MPEG2 144 //! \details 145 //! <b>For MPEG2 QM Type</b>: This field specifies which Quantizer Matrix is 146 //! loaded. 147 enum MPEG2 148 { 149 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 150 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 151 }; 152 153 //! \brief JPEG 154 //! \details 155 //! <b> For JPEG QM Type</b>:This field specifies which Quantizer Matrix is 156 //! loaded. 157 enum JPEG 158 { 159 JPEG_JPEGLUMAYQUANTIZERMATRIXORR = 0, //!< No additional details 160 JPEG_JPEGCHROMACBQUANTIZERMATRIXORG = 1, //!< No additional details 161 JPEG_JPEGCHROMACRQUANTIZERMATRIXORB = 2, //!< No additional details 162 }; 163 164 //! \name Initializations 165 166 //! \brief Explicit member initialization function 167 MFX_QM_STATE_CMD(); 168 169 static const size_t dwSize = 18; 170 static const size_t byteSize = 72; 171 }; 172 173 //! 174 //! \brief MFX_FQM_STATE 175 //! \details 176 //! This is a common state command for AVC encoder modes. For encoder, it 177 //! represents both the forward QM matrices as well as the decoding QM 178 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 179 //! application are being sent to the hardware. The driver is responsible 180 //! for determining the final set of scaling lists to be used for decoding 181 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 182 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 183 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 184 //! order. But the Forward Q scaling lists are sent in column-wise raster 185 //! order (column-by-column) to simplify the H/W. Driver will perform all 186 //! the scan order conversion for both ForwardQ and IQ. 187 //! 188 struct MFX_FQM_STATE_CMD 189 { 190 union 191 { 192 //!< DWORD 0 193 struct 194 { 195 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 196 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 197 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 198 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 199 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 200 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 201 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 202 }; 203 uint32_t Value; 204 } DW0; 205 union 206 { 207 //!< DWORD 1 208 struct 209 { 210 uint32_t Avc : __CODEGEN_BITFIELD( 0, 1) ; //!< AVC, AVC- Decoder Only 211 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, AVC- Decoder Only 212 } Obj0; 213 struct 214 { 215 uint32_t Mpeg2 : __CODEGEN_BITFIELD( 0, 1) ; //!< MPEG2, MPEG2- Decoder Only 216 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, MPEG2- Decoder Only 217 } Obj1; 218 struct 219 { 220 uint32_t Jpeg : __CODEGEN_BITFIELD( 0, 1) ; //!< JPEG, JPEG- Encoder Only 221 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 222 }Obj2; 223 uint32_t Value; 224 } DW1; 225 226 uint32_t ForwardQuantizerMatrix[32]; //!< Forward Quantizer Matrix 227 228 229 //! \name Local enumerations 230 231 enum SUBOPCODE_B 232 { 233 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 234 }; 235 236 enum SUBOPCODE_A 237 { 238 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 239 }; 240 241 enum MEDIA_COMMAND_OPCODE 242 { 243 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 244 }; 245 246 enum PIPELINE 247 { 248 PIPELINE_MFXMULTIDW = 2, //!< No additional details 249 }; 250 251 enum COMMAND_TYPE 252 { 253 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 254 }; 255 256 //! \brief AVC 257 //! \details 258 //! <b>For AVC QM Type</b>: This field specifies which Quantizer Matrix is 259 //! loaded. 260 enum AVC 261 { 262 AVC_AVC_4X_4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 263 AVC_AVC_4X_4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 264 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 265 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 266 }; 267 268 //! \brief MPEG2 269 //! \details 270 //! <b>For MPEG2 QM Type</b>: This field specifies which Quantizer Matrix is 271 //! loaded. 272 enum MPEG2 273 { 274 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 275 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 276 }; 277 278 //! \brief JPEG 279 //! \details 280 //! <b> For JPEG QM Type</b>:This field specifies which Quantizer Matrix is 281 //! loaded. 282 enum JPEG 283 { 284 JPEG_JPEGLUMAYQUANTIZERMATRIXORR = 0, //!< No additional details 285 JPEG_JPEGCHROMACBQUANTIZERMATRIXORG = 1, //!< No additional details 286 JPEG_JPEGCHROMACRQUANTIZERMATRIXORB = 2, //!< No additional details 287 }; 288 289 //! \name Initializations 290 291 //! \brief Explicit member initialization function 292 MFX_FQM_STATE_CMD(); 293 294 static const size_t dwSize = 34; 295 static const size_t byteSize = 136; 296 }; 297 298 //! 299 //! \brief MFX_PIPE_MODE_SELECT 300 //! \details 301 //! Specifies which codec and hardware module is being used to encode/decode 302 //! the video data, on a per-frame basis. The MFX_PIPE_MODE_SELECT command 303 //! specifies which codec and hardware module is being used to encode/decode 304 //! the video data, on a per-frame basis. It also configures the hardware 305 //! pipeline according to the active encoder/decoder operating mode for 306 //! encoding/decoding the current picture. Commands issued specifically for 307 //! AVC and MPEG2 are ignored when VC1 is the active codec. 308 //! 309 struct MFX_PIPE_MODE_SELECT_CMD 310 { 311 union 312 { 313 //!< DWORD 0 314 struct 315 { 316 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 317 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 318 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 319 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPA 320 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26) ; //!< OPCODE 321 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 322 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 323 }; 324 uint32_t Value; 325 } DW0; 326 union 327 { 328 //!< DWORD 1 329 struct 330 { 331 uint32_t StandardSelect : __CODEGEN_BITFIELD( 0, 3) ; //!< STANDARD_SELECT 332 uint32_t CodecSelect : __CODEGEN_BITFIELD( 4, 4) ; //!< CODEC_SELECT 333 uint32_t StitchMode : __CODEGEN_BITFIELD( 5, 5) ; //!< STITCH_MODE 334 uint32_t FrameStatisticsStreamoutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< FRAME_STATISTICS_STREAMOUT_ENABLE 335 uint32_t ScaledSurfaceEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< SCALED_SURFACE_ENABLE 336 uint32_t PreDeblockingOutputEnablePredeblockoutenable : __CODEGEN_BITFIELD( 8, 8) ; //!< PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 337 uint32_t PostDeblockingOutputEnablePostdeblockoutenable : __CODEGEN_BITFIELD( 9, 9) ; //!< POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 338 uint32_t StreamOutEnable : __CODEGEN_BITFIELD(10, 10) ; //!< STREAM_OUT_ENABLE 339 uint32_t PicErrorStatusReportEnable : __CODEGEN_BITFIELD(11, 11) ; //!< PIC_ERRORSTATUS_REPORT_ENABLE 340 uint32_t DeblockerStreamOutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< DEBLOCKER_STREAM_OUT_ENABLE 341 uint32_t VdencMode : __CODEGEN_BITFIELD(13, 13) ; //!< VDENC_MODE 342 uint32_t StandaloneVdencModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< STANDALONE_VDENC_MODE_ENABLE 343 uint32_t DecoderModeSelect : __CODEGEN_BITFIELD(15, 16) ; //!< DECODER_MODE_SELECT 344 uint32_t DecoderShortFormatMode : __CODEGEN_BITFIELD(17, 17) ; //!< DECODER_SHORT_FORMAT_MODE 345 uint32_t ExtendedStreamOutEnable : __CODEGEN_BITFIELD(18, 18) ; //!< Extended stream out enable 346 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 347 }; 348 uint32_t Value; 349 } DW1; 350 union 351 { 352 //!< DWORD 2 353 struct 354 { 355 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 356 uint32_t VdsIldbCalculation : __CODEGEN_BITFIELD( 3, 3) ; //!< VDS_ILDB_CALCULATION 357 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 358 uint32_t ClockGateEnableForSignals : __CODEGEN_BITFIELD( 5, 5) ; //!< Clock gate Enable for signals 359 uint32_t ClockGateEnableAtSliceLevel : __CODEGEN_BITFIELD( 6, 6) ; //!< CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 360 uint32_t Reserved71 : __CODEGEN_BITFIELD( 7, 9) ; //!< Reserved 361 uint32_t MpcPref08X8DisableFlagDefault0 : __CODEGEN_BITFIELD(10, 10) ; //!< MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 362 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13) ; //!< Reserved 363 uint32_t Vlf720IOddHeightInVc1Mode : __CODEGEN_BITFIELD(14, 14) ; //!< VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 364 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 365 uint32_t VmbSvcTlbDummyFetchDisableForPerformance : __CODEGEN_BITFIELD(27, 27) ; //!< VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 366 uint32_t VmbSvcMvReplicationFor8X8EnableErrorHandling : __CODEGEN_BITFIELD(28, 28) ; //!< VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 367 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 368 }; 369 uint32_t Value; 370 } DW2; 371 union 372 { 373 //!< DWORD 3 374 struct 375 { 376 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 377 }; 378 uint32_t Value; 379 } DW3; 380 union 381 { 382 //!< DWORD 4 383 struct 384 { 385 uint32_t MediaSoftResetCounterPer1000Clocks ; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS ; //!< Reserved 386 }; 387 uint32_t Value; 388 } DW4; 389 390 //! \name Local enumerations 391 392 enum SUBOPB 393 { 394 SUBOPB_MFXPIPEMODESELECT = 0, //!< No additional details 395 }; 396 397 enum SUBOPA 398 { 399 SUBOPA_UNNAMED0 = 0, //!< No additional details 400 }; 401 402 enum OPCODE 403 { 404 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 405 }; 406 407 enum PIPELINE 408 { 409 PIPELINE_MFXCOMMON = 2, //!< No additional details 410 }; 411 412 enum COMMAND_TYPE 413 { 414 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 415 }; 416 417 enum STANDARD_SELECT 418 { 419 STANDARD_SELECT_MPEG2 = 0, //!< No additional details 420 STANDARD_SELECT_VC1 = 1, //!< No additional details 421 STANDARD_SELECT_AVC = 2, //!< Covers both AVC and MVC 422 STANDARD_SELECT_JPEG = 3, //!< No additional details 423 STANDARD_SELECT_SVC = 4, //!< No additional details 424 STANDARD_SELECT_VP8 = 5, //!< Decoder starting from BDW, Encoder starting from CHV 425 STANDARD_SELECT_UVLD = 15, //!< SW decoder w/ embedded micro-controller and co-processor 426 }; 427 428 enum CODEC_SELECT 429 { 430 CODEC_SELECT_DECODE = 0, //!< No additional details 431 CODEC_SELECT_ENCODE = 1, //!< Valid only if StandardSel is AVC, MPEG2 and SVC) 432 }; 433 434 enum STITCH_MODE 435 { 436 STITCH_MODE_NOTINSTITCHMODE = 0, //!< No additional details 437 STITCH_MODE_INTHESPECIALSTITCHMODE = 1, //!< This mode can be used for any Codec as long as bitfield conditions are met. 438 }; 439 440 //! \brief FRAME_STATISTICS_STREAMOUT_ENABLE 441 //! \details 442 //! This field controls the frame level statistics streamout from the PAK. 443 //! <p><b>Note</b>: This field needs to be always "Enabled" in VD_Enc 444 //! mode. In case of non-VDEnc mode, 445 //! this can be used to control the frame statistics output from the 446 //! PAK.</p> 447 enum FRAME_STATISTICS_STREAMOUT_ENABLE 448 { 449 FRAME_STATISTICS_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 450 FRAME_STATISTICS_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 451 }; 452 453 //! \brief SCALED_SURFACE_ENABLE 454 //! \details 455 //! This field indicates if the scaled surface is enabled. This field 456 //! enables the 4x HME downscalar of the reconstructed image. Only 457 //! supported for AVC and VP8 formats. 458 enum SCALED_SURFACE_ENABLE 459 { 460 SCALED_SURFACE_ENABLE_DISABLE = 0, //!< No additional details 461 SCALED_SURFACE_ENABLE_ENABLE = 1, //!< No additional details 462 }; 463 464 //! \brief PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 465 //! \details 466 //! This field controls the output write for the reconstructed pixels BEFORE 467 //! the deblocking filter. 468 enum PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 469 { 470 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 471 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 472 }; 473 474 //! \brief POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 475 //! \details 476 //! This field controls the output write for the reconstructed pixels AFTER 477 //! the deblocking filter.In MPEG2 decoding mode, if this is enabled, VC1 478 //! deblocking filter is used. 479 enum POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 480 { 481 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 482 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 483 }; 484 485 //! \brief STREAM_OUT_ENABLE 486 //! \details 487 //! This field controls whether the macroblock parameter stream-out is 488 //! enabled during VLD decoding for transcoding purpose. 489 enum STREAM_OUT_ENABLE 490 { 491 STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 492 STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 493 }; 494 495 //! \brief PIC_ERRORSTATUS_REPORT_ENABLE 496 //! \details 497 //! <p>This field control whether the error/status reporting is enable or 498 //! not.0: Disable1: EnableIn decoder modes: Error reporting is written out 499 //! once per frame. The Error Report frame ID listed in DW3 along with the 500 //! VLD/IT error status bits are packed into one cache and written to the 501 //! "Decoded Picture Error/Status Buffer address" listed in the 502 //! MFX_PIPE_BUF_ADDR_STATE Command. Note: driver shall program different 503 //! error buffer addresses between pictrues; otherwise, hardware might 504 //! overwrite previous written data if driver does not read it fast 505 //! enough.In encoder modes: Not used</p> 506 //! <p>Please refer to "Media VDBOX -> Video Codec -> Other Codec 507 //! Functions -> MFX Error Handling -> Decoder" session for the output 508 //! format.</p> 509 enum PIC_ERRORSTATUS_REPORT_ENABLE 510 { 511 PIC_ERRORSTATUS_REPORT_ENABLE_DISABLE = 0, //!< No additional details 512 PIC_ERRORSTATUS_REPORT_ENABLE_ENABLE = 1, //!< No additional details 513 }; 514 515 //! \brief DEBLOCKER_STREAM_OUT_ENABLE 516 //! \details 517 //! This field indicates if Deblocker information is going to be streamout 518 //! during VLD decoding. 519 //! For AVC, it is needed to enable the deblocker streamout as the AVC 520 //! Disable_DLKFilterIdc is a slice level parameters. Driver needs to 521 //! determine ahead of time if at least one slice of the current frame/ has 522 //! deblocker ON. 523 //! For SVC, there are two deblocking control streamout buffers 524 //! (specified in MFX_BUF_ADDR State Command). This field is still 525 //! associated with the slice level SVC Disable.DLK_Filter_Idc. 526 enum DEBLOCKER_STREAM_OUT_ENABLE 527 { 528 DEBLOCKER_STREAM_OUT_ENABLE_DISABLE = 0, //!< Disable streamout of deblocking control information for standalone deblocker operation.It needs other fields to determine one or two SVC deblocking surface streamout (Post Deblocking Output Enable, Pre Deblocking Output Enable, interlayer idc and regular deblock idc). 529 DEBLOCKER_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 530 }; 531 532 //! \brief VDENC_MODE 533 //! \details 534 //! This field indicates if PAK is working in legacy MBEnc mode or the VDEnc 535 //! mode. 536 enum VDENC_MODE 537 { 538 VDENC_MODE_MBENCMODE = 0, //!< PAK is working in legacy mode 539 VDENC_MODE_VDENCMODE = 1, //!< PAK is working in VDEnc mode 540 }; 541 542 //! \brief STANDALONE_VDENC_MODE_ENABLE 543 //! \details 544 //! This field indicates to PAK if this is standalone VDEnc mode. This is 545 //! primarily a validation mode. 546 enum STANDALONE_VDENC_MODE_ENABLE 547 { 548 STANDALONE_VDENC_MODE_ENABLE_VDENCPAK = 0, //!< No additional details 549 STANDALONE_VDENC_MODE_ENABLE_PAKONLY = 1, //!< No additional details 550 }; 551 552 //! \brief DECODER_MODE_SELECT 553 //! \details 554 //! Each coding standard supports two entry points: VLD entry point and IT 555 //! (IDCT) entry point. This field selects which one is in use.This field is 556 //! only valid if Codec Select is 0 (decoder). 557 enum DECODER_MODE_SELECT 558 { 559 DECODER_MODE_SELECT_VLDMODE = 0, //!< All codec minimum must support this mode Configure the MFD Engine for VLD ModeNote: All codec minimum must support this mode 560 DECODER_MODE_SELECT_ITMODE = 1, //!< Configure the MFD Engine for IT ModeNote: Only VC1 and MPEG2 support this mode 561 DECODER_MODE_SELECT_DEBLOCKERMODE = 2, //!< Configure the MFD Engine for Standalone Deblocker Mode. Require streamout AVC edge control information from preceeding decoding pass.Note: [HSW, EXCLUDE(HSW:GT3:A, HSW:GT3:B, HSW:GT2:B)] Only AVC, MPEG2 and SVC are supported. 562 DECODER_MODE_SELECT_INTERLAYERMODE = 3, //!< Configure the MFX Engine for standalone SVC interlayer upsampling for motion info, residual and reconstructed pixel. Require information being streamout from the preceding encoding and decoding pass of a reference layer.> 563 }; 564 565 //! \brief DECODER_SHORT_FORMAT_MODE 566 //! \details 567 //! For IT mode, this bit must be 0. 568 enum DECODER_SHORT_FORMAT_MODE 569 { 570 DECODER_SHORT_FORMAT_MODE_SHORTFORMATDRIVERINTERFACE = 0, //!< AVC/VC1/MVC/SVC/VP8 Short Format Mode is in useNote: There is no Short Format for SVC and VP8 yet, so this field must be set to 1 for SVC and VP8. 571 DECODER_SHORT_FORMAT_MODE_LONGFORMATDRIVERINTERFACE = 1, //!< AVC/VC1/MVC/SVC/VP8 Long Format Mode is in use. 572 }; 573 574 //! \brief VDS_ILDB_CALCULATION 575 //! \details 576 //! This bit forces all MB into INTRA MBs before doing ILDB control 577 //! generation in VDS. 578 enum VDS_ILDB_CALCULATION 579 { 580 VDS_ILDB_CALCULATION_DISABLE = 0, //!< Use original definition for ILDB calculation. 581 VDS_ILDB_CALCULATION_ENABLE = 1, //!< Force neighbor Intra MB = 1 on ILDB BS calculation. 582 }; 583 584 //! \brief CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 585 //! \details 586 //! BitFieldDesc: 587 enum CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 588 { 589 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_DISABLE = 0, //!< Disable Slice-level Clock gating, Unit-level Clock gating will apply 590 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_ENABLE = 1, //!< Enable Slice-level Clock gating, overrides any Unit level Clock gating 591 }; 592 593 enum MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 594 { 595 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_DISABLE = 0, //!< No additional details 596 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_ENABLE = 1, //!< No additional details 597 }; 598 599 //! \brief VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 600 //! \details 601 //! This bit indicates VLF write out VC1 picture with odd height (in MBs). 602 enum VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 603 { 604 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_DISABLE = 0, //!< No additional details 605 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ENABLE = 1, //!< 720i Enable 606 }; 607 608 //! \brief VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 609 //! \details 610 //! This bit disables TLB dummy fetch in SVC mode in VMB. 611 enum VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 612 { 613 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_ENABLE = 0, //!< Enable VMB TLB Dummy Fetch for Performance 614 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_DISABLE = 1, //!< Disable VMB TLB Dummy Fetch 615 }; 616 617 //! \brief VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 618 //! \details 619 //! This bit enables Motion Vector replication on 8x8 level during SVC mode 620 //! for error handling. 621 enum VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 622 { 623 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_DISABLE = 0, //!< Disable MV 8x8 replication in SVC mode 624 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_ENABLE = 1, //!< Enable MV 8x8 Replication in SVC Mode 625 }; 626 627 //! \brief PIC_STATUSERROR_REPORT_ID 628 //! \details 629 //! In decoder modes: Error reporting is written out once per frame. This 630 //! field along with the VLD error status bits are packed into one cache and 631 //! written to the memory location specified by "Decoded Picture 632 //! Error/Status Buffer address" listed in the MFX_PIPE_BUF_ADDR_STATE 633 //! Command. 634 enum PIC_STATUSERROR_REPORT_ID 635 { 636 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 637 }; 638 639 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 640 //! \details 641 //! In decoder modes, this counter value specifies the number of clocks (per 642 //! 1000) of GAC inactivity 643 //! before a media soft-reset is applied to the HCP and HuC. If counter 644 //! value is set to 0, the media 645 //! soft-reset feature is disabled and no reset will occur. 646 //! <p>In encoder modes, this counter must be set to 0 to disable media 647 //! soft reset. This feature is not 648 //! supported for the encoder.</p> 649 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 650 { 651 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 652 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_ENABLE = 500, //!< number of clocks (per 1000) of GAC inactivity 653 }; 654 655 //! \name Initializations 656 657 //! \brief Explicit member initialization function 658 MFX_PIPE_MODE_SELECT_CMD(); 659 660 static const size_t dwSize = 5; 661 static const size_t byteSize = 20; 662 }; 663 664 //! 665 //! \brief MFX_SURFACE_STATE 666 //! \details 667 //! This command is common for all encoding/decoding modes, to specify the 668 //! uncompressed YUV picture (i.e. destination surface) or intermediate 669 //! streamout in/out surface (e.g. coefficient/residual) (field, frame or 670 //! interleaved frame) format for reading and writing: Uncompressed, 671 //! original input picture to be encoded 672 //! Reconstructed non-filtered/filtered display picturec(becoming reference 673 //! pictures as well for subsequent temporal inter-prediction) 674 //! Residual in SVC 675 //! Reconstructed Intra pixel in SVC 676 //! CoeffPred in SVC 677 //! Since there is only one media surface state being active during the 678 //! entire encoding/decoding process, all the uncompressed/reconstructed 679 //! pictures are defined to have the same surface state. For each media 680 //! object call (decoding or encoding), multiple SVC surfaces can be active 681 //! concurrently, to distinguish among them, a surfaceID is added to 682 //! specify for each type of surface. The primary difference among picture 683 //! surface states is their individual programmed base addresses, which are 684 //! provided by other state commands and not included in this command. MFX 685 //! engine is making the association of surface states and corresponding 686 //! buffer base addresses. MFX engine currently supports only one media 687 //! surface type for video and that is the NV12 (Planar YUV420 with 688 //! interleaved U (Cb) and V (Cr). For optimizing memory efficiency based on 689 //! access patterns, only TileY is supported. For JPEG decoder, only IMC1 690 //! and IMC3 are supported. Pitch can be wider than the Picture Width in 691 //! pixels and garbage will be there at the end of each line. The following 692 //! describes all the different formats that are supported and not supported 693 //! in Gen7 MFX : NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V 694 //! offset is set to 0 (the only format supported for video codec); vertical 695 //! UV offset is MB aligned; UV xoffsets = 0. JPEG does not support NV12 696 //! format because non-interleave JPEG has performance issue with partial 697 //! write (in interleaved UV format) 698 //! IMC 1 & 3 - Full Pitch, U and V are separate plane; (JPEG only; U 699 //! plane + garbage first in full pitch followed by V plane + garbage in 700 //! full pitch). U and V vertical offsets are block aligned; U and V xoffset 701 //! = 0; there is no gap between Y, U and V planes. IMC1 and IMC3 are 702 //! different by a swap of U and V. This is the only format supported in 703 //! JPEG for all video subsampling types (4:4:4, 4:2:2 and 4:2:0) 704 //! We are not supporting IMC 2 & 4 - Full Pitch, U and V are separate 705 //! plane (JPEG only; U plane first in full pitch followed by V plane in 706 //! full pitch - U and V plane are side-by-side). U and V vertical offsets 707 //! are 16-pixel aligned; V xoffset is half-pitch aligned; U xoffset is 0; 708 //! there is no gap between Y, U and V planes. IMC2 and IMC4 are different 709 //! by a swap of U and V. 710 //! We are not supporting YV12 - half pitch for each U and V plane, and 711 //! separate planes for Y, U and V (U plane first in half pitch followed by 712 //! V plane in half pitch). For YV12, U and V vertical offsets are block 713 //! aligned; U and V xoffset = 0; there is no gap between Y, U and V planes 714 //! Note that the following data structures are not specified through the 715 //! media surface state 1D buffers for row-store and other miscellaneous 716 //! information. 717 //! 2D buffers for per-MB data-structures (e.g. DMV biffer, MB info record, 718 //! ILDB Control and Tcoeff/Stocoeff). 719 //! This surface state here is identical to the Surface State for 720 //! deinterlace and sample_8x8 messages described in the Shared Function 721 //! Volume and Sampler Chapter. For non pixel data, such as row stores, 722 //! indirect data (Compressed Slice Data, AVC MV record, Coeff record and 723 //! AVC ILDB record) and streamin/out and output compressed bitstream, a 724 //! linear buffer is employed. For row stores, the H/W is designed to 725 //! guarantee legal memory accesses (read and write). For the remaining 726 //! cases, indirect object base address, indirect object address upper 727 //! bound, object data start address (offset) and object data length are 728 //! used to fully specified their corresponding buffer. This mechanism is 729 //! chosen over the pixel surface type because of their variable record 730 //! sizes. All row store surfaces are linear surface. Their addresses are 731 //! programmed in Pipe_Buf_Base_State or Bsp_Buf_Base_Addr_State 732 //! 733 //! VC1 I picture scaling: Even though VC1 allows I reconstructed picture 734 //! scaling (via RESPIC), as such scaling is only allowed at I picture. All 735 //! subsequent P (and B) pictures must have the same picture dimensions with 736 //! the preceding I picture. Therefore, all reference pictures for P or B 737 //! picture can share the same surface state with the current P and B 738 //! picture. Note : H/W is not processing RESPIC. Application is no longer 739 //! expecting intel decoder pipelineand kernel to perform this function, it 740 //! is going to be done in the video post-processing scaler or display 741 //! controller scale as a separate step and controller. 742 //! 743 //! All video codec surfaces must be NV12 Compliant, except JPEG. U/V 744 //! vertical must be MB aligned for all video codec (further contrained for 745 //! field picture), but JPEG can be block aligned. All video codec and JPEG 746 //! uses Tiled - Y format only, for uncompressed pixel surfaces. 747 //! 748 //! Even for JPEG planar 420 surface, application may provide only 1 749 //! buffers, but there is still only one single surface state for all of 750 //! them. If IMC equal to 1, 2, 3 or 4, U and V have the pitch same as Y. 751 //! And U and V will have different offset, each offset is block aligned. 752 //! 753 struct MFX_SURFACE_STATE_CMD 754 { 755 union 756 { 757 //!< DWORD 0 758 struct 759 { 760 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 761 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 762 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 763 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPA 764 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26) ; //!< OPCODE 765 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 766 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 767 }; 768 uint32_t Value; 769 } DW0; 770 union 771 { 772 //!< DWORD 1 773 struct 774 { 775 uint32_t SurfaceId : __CODEGEN_BITFIELD( 0, 3) ; //!< SURFACE_ID 776 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 777 }; 778 uint32_t Value; 779 } DW1; 780 union 781 { 782 //!< DWORD 2 783 struct 784 { 785 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< Cr(V)/Cb(U) Pixel Offset V Direction 786 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 787 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 788 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 789 }; 790 uint32_t Value; 791 } DW2; 792 union 793 { 794 //!< DWORD 3 795 struct 796 { 797 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 798 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 799 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 800 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 801 uint32_t Reserved116 : __CODEGEN_BITFIELD( 20,26) ; //!< Reserved 802 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(27, 27) ; //!< INTERLEAVE_CHROMA_ 803 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_FORMAT 804 }; 805 uint32_t Value; 806 } DW3; 807 union 808 { 809 //!< DWORD 4 810 struct 811 { 812 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) 813 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 814 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for U(Cb) 815 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 816 }; 817 uint32_t Value; 818 } DW4; 819 union 820 { 821 //!< DWORD 5 822 struct 823 { 824 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 15) ; //!< Y Offset for V(Cr) 825 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V(Cr) 826 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 827 }; 828 uint32_t Value; 829 } DW5; 830 831 //! \name Local enumerations 832 833 enum SUBOPB 834 { 835 SUBOPB_UNNAMED1 = 1, //!< No additional details 836 }; 837 838 enum SUBOPA 839 { 840 SUBOPA_UNNAMED0 = 0, //!< No additional details 841 }; 842 843 enum OPCODE 844 { 845 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 846 }; 847 848 enum PIPELINE 849 { 850 PIPELINE_MFXCOMMON = 2, //!< No additional details 851 }; 852 853 enum COMMAND_TYPE 854 { 855 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 856 }; 857 858 enum SURFACE_ID 859 { 860 SURFACE_ID_DECODEDPICTUREANDREFERENCEPICTURES_SVCUPSAMPLINGSTREAMOUTRECONSTRUCTEDPIXELSCOEFFPREDUPPERLAYERSIZE = 0, //!< 8-bit uncompressed data 861 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMOUTSURFACEUPPERLAYERSIZE = 1, //!< 16-bit uncompressed data 862 SURFACE_ID_SVCRECONSTRUCTEDPIXELANDCOEFFPREDUPSAMPLINGSTREAMINSURFACELOWERLAYERSIZE = 2, //!< 8-bit uncompressed data. 863 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMINSURFACELOWERLAYERSIZE = 3, //!< 16-bit uncompressed data 864 SURFACE_ID_SOURCEINPUTPICTUREENCODER = 4, //!< 8-bit uncompressed data 865 SURFACE_ID_RECONSTRUCTEDSCALEDREFERENCEPICTURE = 5, //!< 8-bit data 866 }; 867 868 //! \brief TILE_WALK 869 //! \details 870 //! (This field must be set to 1: TILEWALK_YMAJOR)This field specifies the 871 //! type of memory tiling (XMajor or YMajor) employed to tile this surface. 872 //! See Memory Interface Functions for details on memory tiling and 873 //! restrictions.This field is ignored when the surface is linear.This field 874 //! is ignored by MFX. Internally H/W is always treated this set to 1 for 875 //! all video codec and for JPEG. 876 enum TILE_WALK 877 { 878 TILE_WALK_XMAJOR = 0, //!< TILEWALK_XMAJOR 879 TILE_WALK_YMAJOR = 1, //!< TILEWALK_YMAJOR 880 }; 881 882 //! \brief TILED_SURFACE 883 //! \details 884 //! (This field must be set to TRUE: Tiled)This field specifies whether the 885 //! surface is tiled.This field is ignored by MFX 886 enum TILED_SURFACE 887 { 888 TILED_SURFACE_FALSE = 0, //!< Linear 889 TILED_SURFACE_TRUE = 1, //!< Tiled 890 }; 891 892 //! \brief INTERLEAVE_CHROMA_ 893 //! \details 894 //! This field indicates that the chroma fields are interleaved in a single 895 //! plane rather than stored as two separate planes. This field is only used 896 //! for PLANAR surface formats.For AVC/VC1/MPEG VLD and IT modes : set to 897 //! Enable to support interleave U/V only.For JPEG : set to Disable for all 898 //! formats (including 4:2:0) - because JPEG does not support NV12. (This 899 //! field is needed only if JPEG will support NV12; otherwise is ignored.) 900 enum INTERLEAVE_CHROMA_ 901 { 902 INTERLEAVE_CHROMA_DISABLE = 0, //!< No additional details 903 INTERLEAVE_CHROMA_ENABLE = 1, //!< No additional details 904 }; 905 906 //! \brief SURFACE_FORMAT 907 //! \details 908 //! Specifies the format of the surface. All of the Y and G channels will 909 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1.Usage: 910 //! For 420 planar YUV surface, use 4; for monochrome surfaces, use 12. For 911 //! monochrome surfaces, hardware ignores control fields for Chroma 912 //! planes.This field must be set to 4 - PLANAR_420_8, or 12 - Y8_UNORMNot 913 //! used for MFX, and is ignored. But for JPEG decoding, this field should 914 //! be programmed to the same format as JPEG_PIC_STATE. For video codec, it 915 //! should set to 4 always. 916 enum SURFACE_FORMAT 917 { 918 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 919 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 920 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 921 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 922 SURFACE_FORMAT_PLANAR_4208 = 4, //!< (NV12, IMC1,2,3,4, YV12) 923 SURFACE_FORMAT_PLANAR_4118 = 5, //!< Deinterlace Only 924 SURFACE_FORMAT_PLANAR_4228 = 6, //!< Deinterlace Only 925 SURFACE_FORMAT_STMMDNSTATISTICS = 7, //!< Deinterlace Only 926 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 Only 927 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 Only 928 SURFACE_FORMAT_R8B8UNORMCRCB = 10, //!< Sample_8x8 Only 929 SURFACE_FORMAT_R8UNORMCRCB = 11, //!< Sample_8x8 Only 930 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 Only 931 }; 932 933 //! \name Initializations 934 935 //! \brief Explicit member initialization function 936 MFX_SURFACE_STATE_CMD(); 937 938 static const size_t dwSize = 6; 939 static const size_t byteSize = 24; 940 }; 941 942 //! 943 //! \brief MFX_IND_OBJ_BASE_ADDR_STATE 944 //! \details 945 //! This state command provides the memory base addresses for all row 946 //! stores, StreamOut buffer and reconstructed picture output buffers 947 //! required by the MFD or MFC Engine (that are in addition to the row 948 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 949 //! reference picture buffers). This is a picture level state command and is 950 //! common among all codec standards and for both encoder and decoder 951 //! operating modes. However, some fields may only applicable to a specific 952 //! codec standard. All Pixel Surfaces (original, reference frame and 953 //! reconstructed frame) in the Encoder are programmed with the same surface 954 //! state (NV12 and TileY format), except each has its own frame buffer base 955 //! address. In the tile format, there is no need to provide buffer offset 956 //! for each slice; since from each MB address, the hardware can calculated 957 //! the corresponding memory location within the frame buffer directly. 958 //! 959 //! The MFX_IND_OBJ_BASE_ADDR command sets the memory base address pointers 960 //! for the corresponding Indirect Object Data Start Addresses (Offsets) 961 //! specified in each OBJECT commands. The characteristic of these indirect 962 //! object data is their variable size (per MB or per Slice). Hence, each 963 //! OBJECT command must specify the indirect object data offset from the 964 //! base address to start fetching or writing object data. 965 //! 966 //! While the use of base address is unconditional, the indirection can be 967 //! effectively disabled by setting the base address to zero. For decoder, 968 //! there are: 1 read-only per-slice indirect object in the BSD_OBJECT 969 //! Command, and 970 //! 2 read-only per-MB indirect objects in the IT_OBJECT Command. 971 //! For decoder: the Video Command Streamer (VCS) will perform the memory 972 //! access bound check automatically using the corresponding MFC Indirect 973 //! Object Access Upper Bound specification. If any access is at or beyond 974 //! the upper bound, zero value is returned. The request to memory is still 975 //! being sent, but the corresponding codec's BSD unit will detect this 976 //! condition and perform the zeroing return. If the Upper Bound is turned 977 //! off, the beyond bound request will return whatever on the bus (invalid 978 //! data). For encoder, there are: 1 read-only per-MB indirect object in 979 //! the PAK_OBJECT Command, and 980 //! 1 write-only per-slice indirect object in the PAK Slice_State Command 981 //! For encoder: whenever an out of bound address accessing request is 982 //! generated, VMX will detect such requests and snap the address to the 983 //! corresponding [indirect object base address + indirect data start 984 //! address]. VMX will return all 0s as the data to the requestor. 985 //! NotationDefinitionPhysicalAddress[n:m] Corresponding bits of a physical 986 //! graphics memory byte address (not mapped by a GTT) GraphicsAddress[n:m] 987 //! Corresponding bits of an absolute, virtual graphics memory byte address 988 //! (mapped by a GTT). 989 //! 990 struct MFX_IND_OBJ_BASE_ADDR_STATE_CMD 991 { 992 union 993 { 994 //!< DWORD 0 995 struct 996 { 997 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 998 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 999 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1000 uint32_t SubOpcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODEA 1001 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMON_OPCODE 1002 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1003 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1004 }; 1005 uint32_t Value; 1006 } DW0; 1007 union 1008 { 1009 //!< DWORD 1 1010 struct 1011 { 1012 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1013 uint32_t MfxIndirectBitstreamObjectBaseAddressDecoderAndStitchModes : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect Bitstream Object - Base Address (Decoder and Stitch Modes) 1014 }; 1015 uint32_t Value; 1016 } DW1; 1017 union 1018 { 1019 //!< DWORD 2 1020 struct 1021 { 1022 uint32_t MfxIndirectBitstreamObjectDestinationAddressDecoderAndStitchModes4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect Bitstream Object - Destination Address (Decoder and Stitch Modes)[47:32] 1023 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1024 }; 1025 uint32_t Value; 1026 } DW2; 1027 union 1028 { 1029 //!< DWORD 3 1030 struct 1031 { 1032 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1033 uint32_t MfxIndirectBitstreamObjectbaseArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1034 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1035 uint32_t MfxIndirectBitstreamObjectTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1036 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1037 }; 1038 uint32_t Value; 1039 } DW3; 1040 union 1041 { 1042 //!< DWORD 4 1043 struct 1044 { 1045 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1046 uint32_t MfxIndirectBitstreamObjectAccessUpperBoundDecoderAndStitchModes : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect Bitstream Object - Access Upper Bound (Decoder and Stitch Modes) 1047 }; 1048 uint32_t Value; 1049 } DW4; 1050 union 1051 { 1052 //!< DWORD 5 1053 struct 1054 { 1055 uint32_t MfxIndirectBitstreamObjectUpperboundDecoderAndStitchModes4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect Bitstream Object UpperBound (Decoder and Stitch Modes)[47:32] 1056 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1057 }; 1058 uint32_t Value; 1059 } DW5; 1060 union 1061 { 1062 //!< DWORD 6 1063 struct 1064 { 1065 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1066 uint32_t MfxIndirectMvObjectBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect MV Object - Base Address 1067 }; 1068 uint32_t Value; 1069 } DW6; 1070 union 1071 { 1072 //!< DWORD 7 1073 struct 1074 { 1075 uint32_t MfxIndirectMvObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect MV Object Base Address [47:32] 1076 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1077 }; 1078 uint32_t Value; 1079 } DW7; 1080 union 1081 { 1082 //!< DWORD 8 1083 struct 1084 { 1085 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1086 uint32_t MfxIndirectMvObjectArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1087 uint32_t Reserved265 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1088 uint32_t MfxIndirectMvObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1089 uint32_t Reserved271 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1090 }; 1091 uint32_t Value; 1092 } DW8; 1093 union 1094 { 1095 //!< DWORD 9 1096 struct 1097 { 1098 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1099 uint32_t MfxIndirectMvObjectAccessUpperBound : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect MV Object Access Upper Bound 1100 }; 1101 uint32_t Value; 1102 } DW9; 1103 union 1104 { 1105 //!< DWORD 10 1106 struct 1107 { 1108 uint32_t MfxIndirectMvObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect MV Object UpperBound [47:32] 1109 uint32_t Reserved336 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1110 }; 1111 uint32_t Value; 1112 } DW10; 1113 union 1114 { 1115 //!< DWORD 11 1116 struct 1117 { 1118 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1119 uint32_t MfdIndirectItCoeffObjectBaseAddressDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-COEFF Object - Base Address (Decoder Only) 1120 }; 1121 uint32_t Value; 1122 } DW11; 1123 union 1124 { 1125 //!< DWORD 12 1126 struct 1127 { 1128 uint32_t MfdIndirectItCoeffObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-COEFF Object Base Address [47:32] 1129 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1130 }; 1131 uint32_t Value; 1132 } DW12; 1133 union 1134 { 1135 //!< DWORD 13 1136 struct 1137 { 1138 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1139 uint32_t MfdIndirectItCoeffObjectDesitnationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1140 uint32_t Reserved425 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1141 uint32_t MfdIndirectItCoeffTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1142 uint32_t Reserved431 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1143 }; 1144 uint32_t Value; 1145 } DW13; 1146 union 1147 { 1148 //!< DWORD 14 1149 struct 1150 { 1151 uint32_t Reserved448 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1152 uint32_t MfdIndirectItCoeffObjectAccessUpperBoundDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-COEFF Object - Access Upper Bound (Decoder Only) 1153 }; 1154 uint32_t Value; 1155 } DW14; 1156 union 1157 { 1158 //!< DWORD 15 1159 struct 1160 { 1161 uint32_t MfdIndirectItCoeffObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-COEFF Object UpperBound [47:32] 1162 uint32_t Reserved496 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1163 }; 1164 uint32_t Value; 1165 } DW15; 1166 union 1167 { 1168 //!< DWORD 16 1169 struct 1170 { 1171 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1172 uint32_t MfdIndirectItDblkObjectBaseAddressDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-DBLK Object - Base Address (Decoder Only) 1173 }; 1174 uint32_t Value; 1175 } DW16; 1176 union 1177 { 1178 //!< DWORD 17 1179 struct 1180 { 1181 uint32_t MfdIndirectItDblkObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-DBLK Object Base Address [47:32] 1182 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1183 }; 1184 uint32_t Value; 1185 } DW17; 1186 union 1187 { 1188 //!< DWORD 18 1189 struct 1190 { 1191 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1192 uint32_t MfdIndirectItDblkObjectArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1193 uint32_t Reserved585 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1194 uint32_t MfdIndirectItDblkObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1195 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1196 }; 1197 uint32_t Value; 1198 } DW18; 1199 union 1200 { 1201 //!< DWORD 19 1202 struct 1203 { 1204 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1205 uint32_t MfdIndirectItDblkObjectAccessUpperBoundDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-DBLK Object - Access Upper Bound (Decoder Only) 1206 }; 1207 uint32_t Value; 1208 } DW19; 1209 union 1210 { 1211 //!< DWORD 20 1212 struct 1213 { 1214 uint32_t MfdIndirectItDblkObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-DBLK Object UpperBound [47:32] 1215 uint32_t Reserved656 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1216 }; 1217 uint32_t Value; 1218 } DW20; 1219 union 1220 { 1221 //!< DWORD 21 1222 struct 1223 { 1224 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1225 uint32_t MfcIndirectPakBseObjectBaseAddressEncoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFC Indirect PAK-BSE Object - Base Address (Encoder Only) 1226 }; 1227 uint32_t Value; 1228 } DW21; 1229 union 1230 { 1231 //!< DWORD 22 1232 struct 1233 { 1234 uint32_t MfcIndirectPakBseObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFC Indirect PAK-BSE Object Base Address [47:32] 1235 uint32_t Reserved720 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1236 }; 1237 uint32_t Value; 1238 } DW22; 1239 union 1240 { 1241 //!< DWORD 23 1242 struct 1243 { 1244 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1245 uint32_t MfcIndirectPakBseObjectDesitnationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1246 uint32_t Reserved745 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1247 uint32_t MfcIndirectPakBseObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1248 uint32_t Reserved751 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1249 }; 1250 uint32_t Value; 1251 } DW23; 1252 union 1253 { 1254 //!< DWORD 24 1255 struct 1256 { 1257 uint32_t Reserved768 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1258 uint32_t MfcIndirectPakBseObjectAccessUpperBoundEecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFC Indirect PAK-BSE Object - Access Upper Bound (Eecoder Only) 1259 }; 1260 uint32_t Value; 1261 } DW24; 1262 union 1263 { 1264 //!< DWORD 25 1265 struct 1266 { 1267 uint32_t MfcIndirectPakBseObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFC Indirect PAK-BSE Object UpperBound [47:32] 1268 uint32_t Reserved816 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1269 }; 1270 uint32_t Value; 1271 } DW25; 1272 1273 //! \name Local enumerations 1274 1275 enum SUBOPCODEB 1276 { 1277 SUBOPCODEB_MFXINDOBJBASEADDRSTATE = 3, //!< No additional details 1278 }; 1279 1280 enum SUB_OPCODEA 1281 { 1282 SUB_OPCODEA_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1283 }; 1284 1285 enum COMMON_OPCODE 1286 { 1287 COMMON_OPCODE_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1288 }; 1289 1290 enum PIPELINE 1291 { 1292 PIPELINE_MFXINDOBJBASEADDRSTATE = 2, //!< No additional details 1293 }; 1294 1295 enum COMMAND_TYPE 1296 { 1297 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1298 }; 1299 1300 //! \brief MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1301 //! \details 1302 //! This field controls the priority of arbitration used in the GAC/GAM 1303 //! pipeline for this surface. 1304 enum MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1305 { 1306 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1307 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1308 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1309 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1310 }; 1311 1312 //! \brief MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1313 //! \details 1314 //! <b>For Media Surfaces:</b> 1315 //! This field specifies the tiled resource mode. 1316 enum MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1317 { 1318 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1319 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1320 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1321 }; 1322 1323 //! \brief MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1324 //! \details 1325 //! This field controls the priority of arbitration used in the GAC/GAM 1326 //! pipeline for this surface. 1327 enum MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1328 { 1329 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1330 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1331 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1332 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1333 }; 1334 1335 //! \brief MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1336 //! \details 1337 //! <b>For Media Surfaces:</b> 1338 //! This field specifies the tiled resource mode. 1339 enum MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1340 { 1341 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1342 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1343 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1344 }; 1345 1346 //! \brief MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1347 //! \details 1348 //! This field controls the priority of arbitration used in the GAC/GAM 1349 //! pipeline for this surface. 1350 enum MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1351 { 1352 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1353 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1354 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1355 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1356 }; 1357 1358 //! \brief MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1359 //! \details 1360 //! <b>For Media Surfaces:</b> 1361 //! This field specifies the tiled resource mode. 1362 enum MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1363 { 1364 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1365 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1366 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1367 }; 1368 1369 //! \brief MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1370 //! \details 1371 //! This field controls the priority of arbitration used in the GAC/GAM 1372 //! pipeline for this surface. 1373 enum MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1374 { 1375 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1376 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1377 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1378 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1379 }; 1380 1381 //! \brief MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1382 //! \details 1383 //! <b>For Media Surfaces:</b> 1384 //! This field specifies the tiled resource mode. 1385 enum MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1386 { 1387 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1388 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1389 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1390 }; 1391 1392 //! \brief MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1393 //! \details 1394 //! This field controls the priority of arbitration used in the GAC/GAM 1395 //! pipeline for this surface. 1396 enum MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1397 { 1398 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1399 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1400 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1401 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1402 }; 1403 1404 //! \brief MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1405 //! \details 1406 //! <b>For Media Surfaces:</b> 1407 //! This field specifies the tiled resource mode. 1408 enum MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1409 { 1410 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1411 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1412 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1413 }; 1414 1415 //! \name Initializations 1416 1417 //! \brief Explicit member initialization function 1418 MFX_IND_OBJ_BASE_ADDR_STATE_CMD(); 1419 1420 static const size_t dwSize = 26; 1421 static const size_t byteSize = 104; 1422 }; 1423 1424 //! 1425 //! \brief MFX_BSP_BUF_BASE_ADDR_STATE 1426 //! \details 1427 //! This frame-level state command is used to specify all the buffer base 1428 //! addresses needed for the operation of the AVC Bit Stream Processing 1429 //! Units (for decoder, it is BSD Unit; for encoder, it is BSE Unit) For 1430 //! both encoder and decoder, currently it is assumed that all codec 1431 //! standards can share the same BSP_BUF_BASE_STATE. The simplicity of this 1432 //! command is the result of moving all the direct MV related processing 1433 //! into the ENC Subsystem. Since all implicit weight calculations and 1434 //! directMV calculations are done in ENC and all picture buffer management 1435 //! are done in the Host, there is no need to provide POC (POC List - 1436 //! FieldOrderCntList, CurrPic POC - CurrFieldOrderCnt) information to PAK. 1437 //! For decoder, all the direct mode information are sent in a separate 1438 //! slice-level command (AVC_DIRECTMODE_STATE command). In addition, in 1439 //! Encoder, the row stores for CABAC encoding and MB Parameters 1440 //! Construction (MPC) are combined into one single row store. The row 1441 //! stores specified in this command do not combine with those specified in 1442 //! the MFC_PIPE_BUF_ADDR_STATE command for hardware simplification reason. 1443 //! 1444 struct MFX_BSP_BUF_BASE_ADDR_STATE_CMD 1445 { 1446 union 1447 { 1448 //!< DWORD 0 1449 struct 1450 { 1451 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1452 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1453 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1454 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1455 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1456 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1457 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1458 }; 1459 uint32_t Value; 1460 } DW0; 1461 union 1462 { 1463 //!< DWORD 1 1464 struct 1465 { 1466 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1467 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite : __CODEGEN_BITFIELD( 6, 31) ; //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write 1468 }; 1469 uint32_t Value; 1470 } DW1; 1471 union 1472 { 1473 //!< DWORD 2 1474 struct 1475 { 1476 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write [47:32] 1477 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1478 }; 1479 uint32_t Value; 1480 } DW2; 1481 union 1482 { 1483 //!< DWORD 3 1484 struct 1485 { 1486 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1487 uint32_t BsdMpcRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1488 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 11) ; //!< Reserved 1489 uint32_t BsdMpcRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1490 uint32_t BsdMpcRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1491 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1492 }; 1493 uint32_t Value; 1494 } DW3; 1495 union 1496 { 1497 //!< DWORD 4 1498 struct 1499 { 1500 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1501 uint32_t MprRowStoreScratchBufferBaseAddressReadWriteDecoderOnly : __CODEGEN_BITFIELD( 6, 31) ; //!< MPR Row Store Scratch Buffer Base Address - Read/Write (Decoder Only) 1502 }; 1503 uint32_t Value; 1504 } DW4; 1505 union 1506 { 1507 //!< DWORD 5 1508 struct 1509 { 1510 uint32_t MprRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MPR Row Store Scratch Buffer Base Address - Read/Write [47:32] 1511 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1512 }; 1513 uint32_t Value; 1514 } DW5; 1515 union 1516 { 1517 //!< DWORD 6 1518 struct 1519 { 1520 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1521 uint32_t MprRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1522 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 11) ; //!< Reserved 1523 uint32_t MprRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1524 uint32_t MprRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1525 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1526 }; 1527 uint32_t Value; 1528 } DW6; 1529 union 1530 { 1531 //!< DWORD 7 1532 struct 1533 { 1534 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1535 uint32_t BitplaneReadBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitplane Read Buffer Base Address 1536 }; 1537 uint32_t Value; 1538 } DW7; 1539 union 1540 { 1541 //!< DWORD 8 1542 struct 1543 { 1544 uint32_t BitplaneReadBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Bitplane Read Buffer Base Address - Read/Write [47:32] 1545 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1546 }; 1547 uint32_t Value; 1548 } DW8; 1549 union 1550 { 1551 //!< DWORD 9 1552 struct 1553 { 1554 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1555 uint32_t BitplaneReadBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1556 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1557 uint32_t BitplaneReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1558 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1559 }; 1560 uint32_t Value; 1561 } DW9; 1562 1563 //! \name Local enumerations 1564 1565 enum SUBOPCODE_B 1566 { 1567 SUBOPCODE_B_UNNAMED_4 = 4, //!< No additional details 1568 }; 1569 1570 enum SUBOPCODE_A 1571 { 1572 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 1573 }; 1574 1575 enum MEDIA_COMMAND_OPCODE 1576 { 1577 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 1578 }; 1579 1580 enum PIPELINE 1581 { 1582 PIPELINE_PIPELINE = 2, //!< No additional details 1583 }; 1584 1585 enum COMMAND_TYPE 1586 { 1587 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1588 }; 1589 1590 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1591 //! \details 1592 //! This field controls the priority of arbitration used in the GAC/GAM 1593 //! pipeline for this surface. 1594 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1595 { 1596 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1597 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1598 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1599 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1600 }; 1601 1602 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1603 //! \details 1604 //! This field controls if Intra Row Store is going to store inside Media 1605 //! Internal Storage or to LLC. 1606 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1607 { 1608 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1609 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1610 }; 1611 1612 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1613 //! \details 1614 //! <b>For Media Surfaces:</b> 1615 //! This field specifies the tiled resource mode. 1616 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1617 { 1618 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1619 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1620 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1621 }; 1622 1623 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1624 //! \details 1625 //! This field controls the priority of arbitration used in the GAC/GAM 1626 //! pipeline for this surface. 1627 enum MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1628 { 1629 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1630 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1631 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1632 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1633 }; 1634 1635 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1636 //! \details 1637 //! This field controls if Intra Row Store is going to store inside Media 1638 //! Internal Storage or to LLC. 1639 enum MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1640 { 1641 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1642 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1643 }; 1644 1645 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1646 //! \details 1647 //! <b>For Media Surfaces:</b> 1648 //! This field specifies the tiled resource mode. 1649 enum MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1650 { 1651 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1652 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1653 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1654 }; 1655 1656 //! \brief BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1657 //! \details 1658 //! This field controls the priority of arbitration used in the GAC/GAM 1659 //! pipeline for this surface. 1660 enum BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1661 { 1662 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1663 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1664 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1665 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1666 }; 1667 1668 //! \brief BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1669 //! \details 1670 //! <b>For Media Surfaces:</b> 1671 //! This field specifies the tiled resource mode. 1672 enum BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1673 { 1674 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1675 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1676 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1677 }; 1678 1679 //! \name Initializations 1680 1681 //! \brief Explicit member initialization function 1682 MFX_BSP_BUF_BASE_ADDR_STATE_CMD(); 1683 1684 static const size_t dwSize = 10; 1685 static const size_t byteSize = 40; 1686 }; 1687 1688 //! 1689 //! \brief MFD_AVC_PICID_STATE 1690 //! \details 1691 //! This is a frame level state command used for both AVC Long and Short 1692 //! Format in VLD mode.PictureID[16] contains the pictureID of each 1693 //! reference picture (16 maximum) so hardware can uniquely identify the 1694 //! reference picture across frames (this will be used for DMV 1695 //! operation).This command will be needed for both short and long format. 1696 //! 1697 struct MFD_AVC_PICID_STATE_CMD 1698 { 1699 union 1700 { 1701 //!< DWORD 0 1702 struct 1703 { 1704 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1705 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1706 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1707 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1708 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1709 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1710 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1711 }; 1712 uint32_t Value; 1713 } DW0; 1714 union 1715 { 1716 //!< DWORD 1 1717 struct 1718 { 1719 uint32_t PictureidRemappingDisable : __CODEGEN_BITFIELD( 0, 0) ; //!< PICTUREID_REMAPPING_DISABLE 1720 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 1721 }; 1722 uint32_t Value; 1723 } DW1; 1724 1725 uint32_t Pictureidlist1616Bits[8]; //!< PictureIDList[16][16 bits] 1726 1727 1728 //! \name Local enumerations 1729 1730 enum SUBOPCODE_B 1731 { 1732 SUBOPCODE_B_MEDIA = 5, //!< No additional details 1733 }; 1734 1735 enum SUBOPCODE_A 1736 { 1737 SUBOPCODE_A_DEC = 1, //!< No additional details 1738 }; 1739 1740 enum MEDIA_COMMAND_OPCODE 1741 { 1742 MEDIA_COMMAND_OPCODE_MFDAVCDPBSTATE = 1, //!< No additional details 1743 }; 1744 1745 enum PIPELINE 1746 { 1747 PIPELINE_MFXMULTIDW = 2, //!< No additional details 1748 }; 1749 1750 enum COMMAND_TYPE 1751 { 1752 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1753 }; 1754 1755 //! \brief PICTUREID_REMAPPING_DISABLE 1756 //! \details 1757 //! If Picture ID Remapping Disable is "1", PictureIDList will not be used. 1758 enum PICTUREID_REMAPPING_DISABLE 1759 { 1760 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE16BITSPICTUREIDTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURE = 0, //!< Desc 1761 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE_4BITSFRAMESTOREIDINDEXTOREFFRAMELISTTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURETHISCAUSESDMVLOGICTOFUNCTIONTHESAMEINPROJECTIVBANDBEFORE = 1, //!< Desc 1762 }; 1763 1764 //! \name Initializations 1765 1766 //! \brief Explicit member initialization function 1767 MFD_AVC_PICID_STATE_CMD(); 1768 1769 static const size_t dwSize = 10; 1770 static const size_t byteSize = 40; 1771 }; 1772 1773 //! 1774 //! \brief MFX_AVC_IMG_STATE 1775 //! \details 1776 //! This must be the very first command to issue after the surface state, 1777 //! the pipe select and base address setting commands. This command supports 1778 //! both Long and Short VLD and IT AVC Decoding Interface. 1779 //! 1780 struct MFX_AVC_IMG_STATE_CMD 1781 { 1782 union 1783 { 1784 //!< DWORD 0 1785 struct 1786 { 1787 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1788 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1789 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1790 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1791 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1792 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1793 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1794 }; 1795 uint32_t Value; 1796 } DW0; 1797 union 1798 { 1799 //!< DWORD 1 1800 struct 1801 { 1802 uint32_t FrameSize : __CODEGEN_BITFIELD( 0, 15) ; //!< Frame Size 1803 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1804 }; 1805 uint32_t Value; 1806 } DW1; 1807 union 1808 { 1809 //!< DWORD 2 1810 struct 1811 { 1812 uint32_t FrameWidth : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Width 1813 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1814 uint32_t FrameHeight : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Height 1815 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1816 }; 1817 uint32_t Value; 1818 } DW2; 1819 union 1820 { 1821 //!< DWORD 3 1822 struct 1823 { 1824 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1825 uint32_t ImgstructImageStructureImgStructure10 : __CODEGEN_BITFIELD( 8, 9) ; //!< IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 1826 uint32_t WeightedBipredIdc : __CODEGEN_BITFIELD(10, 11) ; //!< WEIGHTED_BIPRED_IDC 1827 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(12, 12) ; //!< WEIGHTED_PRED_FLAG 1828 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD(13, 13) ; //!< RHODOMAIN_RATE_CONTROL_ENABLE 1829 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1830 uint32_t FirstChromaQpOffset : __CODEGEN_BITFIELD(16, 20) ; //!< First Chroma QP Offset 1831 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 1832 uint32_t SecondChromaQpOffset : __CODEGEN_BITFIELD(24, 28) ; //!< Second Chroma QP Offset 1833 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1834 }; 1835 uint32_t Value; 1836 } DW3; 1837 union 1838 { 1839 //!< DWORD 4 1840 struct 1841 { 1842 uint32_t Fieldpicflag : __CODEGEN_BITFIELD( 0, 0) ; //!< FIELDPICFLAG 1843 uint32_t Mbaffflameflag : __CODEGEN_BITFIELD( 1, 1) ; //!< MBAFFFLAMEFLAG 1844 uint32_t Framembonlyflag : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMEMBONLYFLAG 1845 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD( 3, 3) ; //!< TRANSFORM8X8FLAG 1846 uint32_t Direct8X8Infflag : __CODEGEN_BITFIELD( 4, 4) ; //!< DIRECT8X8INFFLAG 1847 uint32_t Constrainedipredflag : __CODEGEN_BITFIELD( 5, 5) ; //!< CONSTRAINEDIPREDFLAG 1848 uint32_t Imgdisposableflag : __CODEGEN_BITFIELD( 6, 6) ; //!< IMGDISPOSABLEFLAG 1849 uint32_t Entropycodingflag : __CODEGEN_BITFIELD( 7, 7) ; //!< ENTROPYCODINGFLAG 1850 uint32_t Mbmvformatflag : __CODEGEN_BITFIELD( 8, 8) ; //!< MBMVFORMATFLAG 1851 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1852 uint32_t Chromaformatidc : __CODEGEN_BITFIELD(10, 11) ; //!< CHROMAFORMATIDC 1853 uint32_t Mvunpackedflag : __CODEGEN_BITFIELD(12, 12) ; //!< MVUNPACKEDFLAG 1854 uint32_t Reserved141 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 1855 uint32_t Loadslicepointerflag : __CODEGEN_BITFIELD(14, 14) ; //!< LOADSLICEPOINTERFLAG 1856 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15) ; //!< MBSTATENABLED 1857 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31) ; //!< MINFRAMEWSIZE 1858 }; 1859 uint32_t Value; 1860 } DW4; 1861 union 1862 { 1863 //!< DWORD 5 1864 struct 1865 { 1866 uint32_t IntrambmaxbitflagIntrambmaxsizereportmask : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 1867 uint32_t IntermbmaxbitflagIntermbmaxsizereportmask : __CODEGEN_BITFIELD( 1, 1) ; //!< INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 1868 uint32_t FrameszoverflagFramebitratemaxreportmask : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 1869 uint32_t FrameszunderflagFramebitrateminreportmask : __CODEGEN_BITFIELD( 3, 3) ; //!< FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 1870 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 6) ; //!< Reserved 1871 uint32_t IntraIntermbipcmflagForceipcmcontrolmask : __CODEGEN_BITFIELD( 7, 7) ; //!< INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 1872 uint32_t Reserved168 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 1873 uint32_t MbratectrlflagMbLevelRateControlEnablingFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 1874 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11) ; //!< MINFRAMEWSIZEUNITS 1875 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1876 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 1877 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 26) ; //!< Reserved 1878 uint32_t TrellisQuantizationChromaDisableTqchromadisable : __CODEGEN_BITFIELD(27, 27) ; //!< TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 1879 uint32_t TrellisQuantizationRoundingTqr : __CODEGEN_BITFIELD(28, 30) ; //!< TRELLIS_QUANTIZATION_ROUNDING_TQR 1880 uint32_t TrellisQuantizationEnabledTqenb : __CODEGEN_BITFIELD(31, 31) ; //!< TRELLIS_QUANTIZATION_ENABLED_TQENB 1881 }; 1882 uint32_t Value; 1883 } DW5; 1884 union 1885 { 1886 //!< DWORD 6 1887 struct 1888 { 1889 uint32_t Intrambmaxsz : __CODEGEN_BITFIELD( 0, 11) ; //!< IntraMbMaxSz 1890 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1891 uint32_t Intermbmaxsz : __CODEGEN_BITFIELD(16, 27) ; //!< InterMbMaxSz 1892 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1893 }; 1894 uint32_t Value; 1895 } DW6; 1896 union 1897 { 1898 //!< DWORD 7 1899 struct 1900 { 1901 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSL_TOP_MB_TRANS8X8FLAG 1902 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 15) ; //!< Reserved 1903 uint32_t BspEncoderEcoEnable : __CODEGEN_BITFIELD(16, 16) ; //!< BSP_ENCODER_ECO_ENABLE 1904 uint32_t Reserved241 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1905 }; 1906 uint32_t Value; 1907 } DW7; 1908 union 1909 { 1910 //!< DWORD 8 1911 struct 1912 { 1913 uint32_t Slicedeltaqppmax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQpPMax[0] 1914 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQpMax[1] 1915 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQpMax[2] 1916 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQpMax[3] 1917 }; 1918 uint32_t Value; 1919 } DW8; 1920 union 1921 { 1922 //!< DWORD 9 1923 struct 1924 { 1925 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQpMin[0] 1926 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQpMin[1] 1927 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQpMin[2] 1928 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQpMin[3] 1929 }; 1930 uint32_t Value; 1931 } DW9; 1932 union 1933 { 1934 //!< DWORD 10 1935 struct 1936 { 1937 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1938 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14) ; //!< FRAMEBITRATEMINUNITMODE 1939 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15) ; //!< FRAMEBITRATEMINUNIT 1940 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29) ; //!< FrameBitRateMax 1941 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30) ; //!< FRAMEBITRATEMAXUNITMODE 1942 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT_ 1943 }; 1944 uint32_t Value; 1945 } DW10; 1946 union 1947 { 1948 //!< DWORD 11 1949 struct 1950 { 1951 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FrameBitRateMinDelta 1952 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1953 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1954 uint32_t SliceStatsStreamoutEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Slice Stats Streamout Enable 1955 }; 1956 uint32_t Value; 1957 } DW11; 1958 union 1959 { 1960 //!< DWORD 12 1961 struct 1962 { 1963 uint32_t Reserved384 ; //!< Reserved 1964 }; 1965 uint32_t Value; 1966 } DW12; 1967 union 1968 { 1969 //!< DWORD 13 1970 struct 1971 { 1972 uint32_t InitialQpValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Initial QP Value 1973 uint32_t NumberOfActiveReferencePicturesFromL0 : __CODEGEN_BITFIELD( 8, 13) ; //!< Number of Active Reference Pictures from L0 1974 uint32_t Reserved430 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1975 uint32_t NumberOfActiveReferencePicturesFromL1 : __CODEGEN_BITFIELD(16, 21) ; //!< Number of Active Reference Pictures from L1 1976 uint32_t Reserved438 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 1977 uint32_t NumberOfReferenceFrames : __CODEGEN_BITFIELD(24, 28) ; //!< Number of Reference Frames 1978 uint32_t CurrentPictureHasPerformedMmco5 : __CODEGEN_BITFIELD(29, 29) ; //!< Current Picture Has Performed MMCO5 1979 uint32_t Reserved446 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1980 }; 1981 uint32_t Value; 1982 } DW13; 1983 union 1984 { 1985 //!< DWORD 14 1986 struct 1987 { 1988 uint32_t PicOrderPresentFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< Pic_order_present_flag 1989 uint32_t DeltaPicOrderAlwaysZeroFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< Delta_pic_order_always_zero_flag 1990 uint32_t PicOrderCntType : __CODEGEN_BITFIELD( 2, 3) ; //!< Pic_order_cnt_type 1991 uint32_t Reserved452 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 1992 uint32_t SliceGroupMapType : __CODEGEN_BITFIELD( 8, 10) ; //!< slice_group_map_type 1993 uint32_t RedundantPicCntPresentFlag : __CODEGEN_BITFIELD(11, 11) ; //!< redundant_pic_cnt_present_flag 1994 uint32_t NumSliceGroupsMinus1 : __CODEGEN_BITFIELD(12, 14) ; //!< num_slice_groups_minus1 1995 uint32_t DeblockingFilterControlPresentFlag : __CODEGEN_BITFIELD(15, 15) ; //!< deblocking_filter_control_present_flag 1996 uint32_t Log2MaxFrameNumMinus4 : __CODEGEN_BITFIELD(16, 23) ; //!< Log2_max_frame_num_minus4 1997 uint32_t Log2MaxPicOrderCntLsbMinus4 : __CODEGEN_BITFIELD(24, 31) ; //!< Log2_max_pic_order_cnt_lsb_minus4 1998 }; 1999 uint32_t Value; 2000 } DW14; 2001 union 2002 { 2003 //!< DWORD 15 2004 struct 2005 { 2006 uint32_t SliceGroupChangeRate : __CODEGEN_BITFIELD( 0, 15) ; //!< Slice Group Change Rate 2007 uint32_t CurrPicFrameNum : __CODEGEN_BITFIELD(16, 31) ; //!< Curr Pic Frame Num 2008 }; 2009 uint32_t Value; 2010 } DW15; 2011 union 2012 { 2013 //!< DWORD 16 2014 struct 2015 { 2016 uint32_t CurrentFrameViewId : __CODEGEN_BITFIELD( 0, 9) ; //!< Current Frame View ID 2017 uint32_t Reserved522 : __CODEGEN_BITFIELD(10, 11) ; //!< Reserved 2018 uint32_t MaxViewIdxl0 : __CODEGEN_BITFIELD(12, 15) ; //!< Max View IDXL0 2019 uint32_t Reserved528 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 2020 uint32_t MaxViewIdxl1 : __CODEGEN_BITFIELD(18, 21) ; //!< Max View IDXL1 2021 uint32_t Reserved534 : __CODEGEN_BITFIELD(22, 30) ; //!< Reserved 2022 uint32_t InterViewOrderDisable : __CODEGEN_BITFIELD(31, 31) ; //!< INTER_VIEW_ORDER_DISABLE 2023 }; 2024 uint32_t Value; 2025 } DW16; 2026 union 2027 { 2028 //!< DWORD 17 2029 struct 2030 { 2031 uint32_t FractionalQpInput : __CODEGEN_BITFIELD( 0, 2) ; //!< Fractional QP input 2032 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD( 3, 5) ; //!< Fractional QP offset 2033 uint32_t Reserved550 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 2034 uint32_t ExtendedRhodomainStatisticsEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Extended RhoDomain Statistics Enable 2035 uint32_t Reserved553 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2036 uint32_t RhodomainAveragemacroblockqp : __CODEGEN_BITFIELD(16, 21) ; //!< RhoDomain AverageMacroblockQP 2037 uint32_t Reserved566 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 2038 }; 2039 uint32_t Value; 2040 } DW17; 2041 union 2042 { 2043 //!< DWORD 18 2044 struct 2045 { 2046 uint32_t Reserved576 ; //!< Reserved 2047 }; 2048 uint32_t Value; 2049 } DW18; 2050 union 2051 { 2052 //!< DWORD 19 2053 struct 2054 { 2055 uint32_t ThresholdSizeInBytes ; //!< Threshold Size in Bytes 2056 }; 2057 uint32_t Value; 2058 } DW19; 2059 union 2060 { 2061 //!< DWORD 20 2062 struct 2063 { 2064 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 2065 }; 2066 uint32_t Value; 2067 } DW20; 2068 2069 //! \name Local enumerations 2070 2071 enum SUBOPCODE_B 2072 { 2073 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 2074 }; 2075 2076 enum SUBOPCODE_A 2077 { 2078 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2079 }; 2080 2081 enum MEDIA_COMMAND_OPCODE 2082 { 2083 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2084 }; 2085 2086 enum PIPELINE 2087 { 2088 PIPELINE_MFXAVCIMGSTATE = 2, //!< No additional details 2089 }; 2090 2091 enum COMMAND_TYPE 2092 { 2093 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2094 }; 2095 2096 //! \brief IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 2097 //! \details 2098 //! The current encoding picture structure can only takes on 3 possible 2099 //! values 2100 enum IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 2101 { 2102 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_FRAMEPICTURE = 0, //!< No additional details 2103 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_TOPFIELDPICTURE = 1, //!< No additional details 2104 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_INVALID_NOTALLOWED = 2, //!< No additional details 2105 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_BOTTOMFIELDPICTURE = 3, //!< No additional details 2106 }; 2107 2108 //! \brief WEIGHTED_BIPRED_IDC 2109 //! \details 2110 //! (This field is defined differently from DevSNB; DevIVB follows strictly 2111 //! AVC interface.) 2112 enum WEIGHTED_BIPRED_IDC 2113 { 2114 WEIGHTED_BIPRED_IDC_DEFAULT = 0, //!< Specifies that the default weighted prediction is used for B slices 2115 WEIGHTED_BIPRED_IDC_EXPLICIT = 1, //!< Specifies that explicit weighted prediction is used for B slices 2116 WEIGHTED_BIPRED_IDC_IMPLICIT = 2, //!< Specifies that implicit weighted prediction is used for B slices. 2117 }; 2118 2119 //! \brief WEIGHTED_PRED_FLAG 2120 //! \details 2121 //! (This field is defined differently from Gen6, Gen7 follows strictly 2122 //! AVC interface.) 2123 enum WEIGHTED_PRED_FLAG 2124 { 2125 WEIGHTED_PRED_FLAG_DISABLE = 0, //!< specifies that weighted prediction is not used for P and SP slices 2126 WEIGHTED_PRED_FLAG_ENABLE = 1, //!< specifies that weighted prediction is used for P and SP slices 2127 }; 2128 2129 //! \brief RHODOMAIN_RATE_CONTROL_ENABLE 2130 //! \details 2131 //! This field indicates if RhoDomain related parameters are present in the 2132 //! MFX_AVC_IMAGE_STATE. (AverageMacroblockQP). It enables the Rho Domain 2133 //! statistics collection. 2134 enum RHODOMAIN_RATE_CONTROL_ENABLE 2135 { 2136 RHODOMAIN_RATE_CONTROL_ENABLE_DISABLE = 0, //!< RhoDomain rate control parameters are not present in MFX_AVC_IMAGE_STATE 2137 RHODOMAIN_RATE_CONTROL_ENABLE_ENABLE = 1, //!< RhoDomain rate control parameters are present in MFX_AVC_IMAGE_STATE. 2138 }; 2139 2140 //! \brief FIELDPICFLAG 2141 //! \details 2142 //! Field picture flag, field_pic_flag, specifies the current slice is a 2143 //! coded field or not.It is set to the same value as the syntax element in 2144 //! the Slice Header. It must be consistent with the img_structure[1:0] and 2145 //! the frame_mbs_only_flag settings.Although field_pic_flag is a Slice 2146 //! Header parameter, its value is expected to be the same for all the 2147 //! slices of a picture. 2148 enum FIELDPICFLAG 2149 { 2150 FIELDPICFLAG_FRAME = 0, //!< a slice of a coded frame 2151 FIELDPICFLAG_FIELD = 1, //!< a slice of a coded field 2152 }; 2153 2154 //! \brief MBAFFFLAMEFLAG 2155 //! \details 2156 //! MBAFF mode is active, mbaff_frame_flag.It is derived from MbaffFrameFlag 2157 //! = (mb_adaptive_frame_field_flag && ! field_pic_flag ). 2158 //! mb_adaptive_frame_field_flag is a syntax element in the current active 2159 //! SPS and field_pic_flag is a syntax element in the current Slice Header. 2160 //! They both are present only if frame_mbs_only_flag is 0. Although 2161 //! mbaff_frame_flag is a Slice Header parameter, its value is expected to 2162 //! be the same for all the slices of a picture.It must be consistent with 2163 //! the mb_adaptive_frame_field_flag, the field_pic_flag and the 2164 //! frame_mbs_only_flag settings.This bit is valid only when the 2165 //! img_structure[1:0] indicates the current picture is a frame. 2166 enum MBAFFFLAMEFLAG 2167 { 2168 MBAFFFLAMEFLAG_FALSE = 0, //!< not in MBAFF mode 2169 MBAFFFLAMEFLAG_TRUE = 1, //!< in MBAFF mode 2170 }; 2171 2172 //! \brief FRAMEMBONLYFLAG 2173 //! \details 2174 //! Frame MB only flag, frame_mbs_only_flagIt is set to the value of the 2175 //! syntax element in the current active SPS. 2176 enum FRAMEMBONLYFLAG 2177 { 2178 FRAMEMBONLYFLAG_FALSE = 0, //!< not true ; effectively enables the possibility of MBAFF mode. 2179 FRAMEMBONLYFLAG_TRUE = 1, //!< true, only frame MBs can occur in this sequence, hence disallows the MBAFF mode and field picture. 2180 }; 2181 2182 //! \brief TRANSFORM8X8FLAG 2183 //! \details 2184 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flagSpecifies 8x8 IDCT 2185 //! transform may be used in this pictureIt is set to the value of the 2186 //! syntax element in the current active PPS. 2187 enum TRANSFORM8X8FLAG 2188 { 2189 TRANSFORM8X8FLAG_4X_4 = 0, //!< no 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present 2190 TRANSFORM8X8FLAG_8X8 = 1, //!< 8x8 Transform is allowed 2191 }; 2192 2193 //! \brief DIRECT8X8INFFLAG 2194 //! \details 2195 //! Direct 8x8 Inference Flag, direct_8x8_inference_flagIt is set to the 2196 //! value of the syntax element in the current active SPS.It specifies the 2197 //! derivation process for luma motion vectors in the Direct MV coding modes 2198 //! (B_Skip, B_Direct_16x16 and B_Direct_8x8). When frame_mbs_only_flag is 2199 //! equal to 0, direct_8x8_inference_flag shall be equal to 1.It must be 2200 //! consistent with the frame_mbs_only_flag and transform_8x8_mode_flag 2201 //! settings. 2202 enum DIRECT8X8INFFLAG 2203 { 2204 DIRECT8X8INFFLAG_SUBBLOCK = 0, //!< allows subpartitioning to go below 8x8 block size (i.e. 4x4, 8x4 or 4x8) 2205 DIRECT8X8INFFLAG_BLOCK = 1, //!< allows processing only at 8x8 block size. MB Info is stored for 8x8 block size. 2206 }; 2207 2208 //! \brief CONSTRAINEDIPREDFLAG 2209 //! \details 2210 //! Constrained Intra Prediction Flag, constrained_ipred_flagIt is set to 2211 //! the value of the syntax element in the current active PPS. 2212 enum CONSTRAINEDIPREDFLAG 2213 { 2214 CONSTRAINEDIPREDFLAG_INTRAANDINTER = 0, //!< allows both intra and inter neighboring MB to be used in the intra-prediction encoding of the current MB. 2215 CONSTRAINEDIPREDFLAG_INTRAONLY = 1, //!< allows only to use neighboring Intra MBs in the intra-prediction encoding of the current MB. If the neighbor is an inter MB, it is considered as not available. 2216 }; 2217 2218 //! \brief IMGDISPOSABLEFLAG 2219 //! \details 2220 //! Current Img Disposable Flag or Non-Reference Picture Flag 2221 enum IMGDISPOSABLEFLAG 2222 { 2223 IMGDISPOSABLEFLAG_REFERENCE = 0, //!< the current decoding picture may be used as a reference picture for others 2224 IMGDISPOSABLEFLAG_DISPOSABLE = 1, //!< the current decoding picture is not used as a reference picture (e.g. a B-picture cannot be a reference picture for any subsequent decoding) 2225 }; 2226 2227 //! \brief ENTROPYCODINGFLAG 2228 //! \details 2229 //! Entropy Coding Flag, entropy_coding_flag 2230 enum ENTROPYCODINGFLAG 2231 { 2232 ENTROPYCODINGFLAG_CAVLCBIT_SERIALENCODINGMODE = 0, //!< Desc 2233 ENTROPYCODINGFLAG_CABACBIT_SERIALENCODINGMODE = 1, //!< Desc 2234 }; 2235 2236 //! \brief MBMVFORMATFLAG 2237 //! \details 2238 //! Use MB level MvFormat flag (Encoder Only)(This bit must be set to zero 2239 //! in IVB:GT2:A0) 2240 enum MBMVFORMATFLAG 2241 { 2242 MBMVFORMATFLAG_IGNORE = 0, //!< HW PAK ignore MvFormat in the MB data. When bit 12 == 0, all MBs use packed MV formatWhen bit 12 == 1, each MB data must use unpacked MV format, 8MV when there is no minor MV involved, and 32MV if there are some minor motion vectors. 2243 MBMVFORMATFLAG_FOLLOW = 1, //!< HW PAK will follow MvFormat value set within each MB data. 2244 }; 2245 2246 //! \brief CHROMAFORMATIDC 2247 //! \details 2248 //! Chroma Format IDC, ChromaFormatIdc[1:0]It specifies the sampling of 2249 //! chroma component (Cb, Cr) in the current picture as follows : 2250 enum CHROMAFORMATIDC 2251 { 2252 CHROMAFORMATIDC_MONOCHROMEPICTURE = 0, //!< Desc 2253 CHROMAFORMATIDC_420PICTURE = 1, //!< Desc 2254 CHROMAFORMATIDC_422PICTURENOTSUPPORTED = 2, //!< No additional details 2255 CHROMAFORMATIDC_4_4_4PICTURENOTSUPPORTED = 3, //!< No additional details 2256 }; 2257 2258 //! \brief MVUNPACKEDFLAG 2259 //! \details 2260 //! MVUnPackedEnable (Encoder Only)This field is reserved in Decode mode. 2261 enum MVUNPACKEDFLAG 2262 { 2263 MVUNPACKEDFLAG_PACKED = 0, //!< use packed MV format (compliant to ) 2264 MVUNPACKEDFLAG_UNPACKED = 1, //!< use unpacked 8MV/32MV format only 2265 }; 2266 2267 //! \brief LOADSLICEPOINTERFLAG 2268 //! \details 2269 //! LoadBitStreamPointerPerSlice (Encoder-only)To support multiple slice 2270 //! picture and additional header/data insertion before and after an encoded 2271 //! slice.When this field is set to 0, bitstream pointer is only loaded once 2272 //! for the first slice of a frame. For subsequent slices in the frame, 2273 //! bitstream data are stitched together to form a single output data 2274 //! stream.When this field is set to 1, bitstream pointer is loaded for each 2275 //! slice of a frame. Basically bitstream data for different slices of a 2276 //! frame will be written to different memory locations. 2277 enum LOADSLICEPOINTERFLAG 2278 { 2279 LOADSLICEPOINTERFLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame 2280 LOADSLICEPOINTERFLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 2281 }; 2282 2283 //! \brief MBSTATENABLED 2284 //! \details 2285 //! <p>Enable reading in MB status buffer (a.k.a. encoding stream-out 2286 //! buffer) Note: For multi-pass encoder, all passes except the first one 2287 //! need to set this value to 1. By setting the first pass to 0, it does 2288 //! save some memory bandwidth.</p> 2289 //! <p><span style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 2290 //! line-height: normal;">In VDenc mode this must be set to zero as no MB 2291 //! level rate control is used. </span></p> 2292 enum MBSTATENABLED 2293 { 2294 MBSTATENABLED_DISABLE = 0, //!< Disable Reading of Macroblock Status Buffer 2295 MBSTATENABLED_ENABLE = 1, //!< Enable Reading of Macroblock Status Buffer 2296 }; 2297 2298 //! \brief MINFRAMEWSIZE 2299 //! \details 2300 //! <p><b>Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)</b> 2301 //! Mininum Frame Size is specified to compensate for intel Rate 2302 //! Control Currently zero fill (no need to perform emulation byte 2303 //! insertion) is done 2304 //! only to the end of the CABAC_ZERO_WORD insertion (if any) at the 2305 //! last slice of a 2306 //! picture. Intel encoder parameter, not part of . The caller 2307 //! should always make 2308 //! sure that the value, represented by Mininum Frame Size, is always 2309 //! less than maximum 2310 //! frame size <b>FrameBitRateMax (DWORD 10 bits</b> 29:16).This field 2311 //! is reserved in 2312 //! Decode mode.</p> 2313 //! <p>The programmable range 0…2^18-1</p> 2314 //! <p>When MinFrameWSizeUnits is 00.</p> 2315 //! <p>Programmable range is 0…2^20-1 when MinFrameWSizeUnits is 2316 //! 01.</p> 2317 //! <p>Programmable range is 0…2^26-1 when MinFrameWSizeUnits is 2318 //! 10.</p> 2319 //! <p>Programmable range is 0…2^32-1 when MinFrameWSizeUnits is 2320 //! 11.</p> 2321 enum MINFRAMEWSIZE 2322 { 2323 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 2324 }; 2325 2326 //! \brief INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 2327 //! \details 2328 //! This is a mask bit controlling if the condition of any intra MB in the 2329 //! frame exceeds IntraMBMaxSize. 2330 enum INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 2331 { 2332 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2333 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_ENABLE = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 2334 }; 2335 2336 //! \brief INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 2337 //! \details 2338 //! This is a mask bit controlling if the condition of any inter MB in the 2339 //! frame exceeds InterMBMaxSize. 2340 enum INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 2341 { 2342 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2343 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_ENABLE = 1, //!< Set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 2344 }; 2345 2346 //! \brief FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 2347 //! \details 2348 //! This is a mask bit controlling if the condition of frame level bit count 2349 //! exceeds FrameBitRateMax. 2350 enum FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 2351 { 2352 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2353 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 2354 }; 2355 2356 //! \brief FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 2357 //! \details 2358 //! This is a mask bit controlling if the condition of frame level bit count 2359 //! is less than FrameBitRateMin 2360 enum FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 2361 { 2362 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2363 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 2364 }; 2365 2366 //! \brief INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 2367 //! \details 2368 //! This field is to Force <b>IPCM</b> for Intra or Inter Macroblock size 2369 //! conformance mask. 2370 enum INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 2371 { 2372 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_DISABLE = 0, //!< Do not change intra or Inter macroblocks even 2373 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_ENABLE = 1, //!< Change intra or Inter macroblocks MB_type to IPCM 2374 }; 2375 2376 //! \brief MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2377 //! \details 2378 //! <p>MB Rate Control conformance mask</p> 2379 //! <p>In VDenc mode, this field must be zero as frame level rate control is 2380 //! used.</p> 2381 enum MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2382 { 2383 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_DISABLE = 0, //!< Apply accumulative delta QP for consecutive passes on top of the macroblock QP values in inline data 2384 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_ENABLE = 1, //!< Apply RC QP delta to suggested QP values in Macroblock Status Buffer except the first pass. 2385 }; 2386 2387 //! \brief MINFRAMEWSIZEUNITS 2388 //! \details 2389 //! This field is the Minimum Frame Size Units 2390 enum MINFRAMEWSIZEUNITS 2391 { 2392 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 2393 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 2394 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 2395 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 2396 }; 2397 2398 //! \brief NONFIRSTPASSFLAG 2399 //! \details 2400 //! This signals the current pass is not the first pass. It will imply 2401 //! designate HW behavior: e.g 2402 enum NONFIRSTPASSFLAG 2403 { 2404 NONFIRSTPASSFLAG_DISABLE = 0, //!< Always use the MbQpY from initial PAK inline object for all passes of PAK 2405 NONFIRSTPASSFLAG_ENABLE = 1, //!< Use MbQpY from stream-out buffer if MbRateCtrlFlag is set to 1 2406 }; 2407 2408 //! \brief TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2409 //! \details 2410 //! This signal is used to disable chroma TQ. To enable TQ for both luma and 2411 //! chroma, TQEnb=1, TQChromaDisable=0. To enable TQ only for luma, TQEnb=1, 2412 //! TQChromaDisable=1. 2413 enum TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2414 { 2415 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_UNNAMED0 = 0, //!< Enable Trellis Quantization chroma 2416 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_DEFAULT = 1, //!< Disable Trellis Quantization chroma 2417 }; 2418 2419 //! \brief TRELLIS_QUANTIZATION_ROUNDING_TQR 2420 //! \details 2421 //! This rounding scheme is only applied to the quantized coefficients 2422 //! ranging from 0 to 1 when TQEnb is set to 1 in AVC CABAC mode. One of the 2423 //! following values is added to quantized coefficients before truncating 2424 //! fractional part. 2425 enum TRELLIS_QUANTIZATION_ROUNDING_TQR 2426 { 2427 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED0 = 0, //!< Add 1/8 2428 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED1 = 1, //!< Add 2/8 2429 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED2 = 2, //!< Add 3/8 2430 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED3 = 3, //!< Add 4/8 (rounding 0.5) 2431 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED_4 = 4, //!< Add 5/8 2432 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED5 = 5, //!< Add 6/8 2433 TRELLIS_QUANTIZATION_ROUNDING_TQR_DEFAULT = 6, //!< Add 7/8 (Default rounding 0.875) 2434 }; 2435 2436 //! \brief TRELLIS_QUANTIZATION_ENABLED_TQENB 2437 //! \details 2438 //! The TQ improves output video quality of AVC CABAC encoder by selecting 2439 //! quantized values for each non-zero coefficient so as to minimize the 2440 //! total R-D cost.This flag is only valid AVC CABAC mode. Otherwise, this 2441 //! flag should be disabled. 2442 enum TRELLIS_QUANTIZATION_ENABLED_TQENB 2443 { 2444 TRELLIS_QUANTIZATION_ENABLED_TQENB_DISABLE = 0, //!< Use Normal 2445 TRELLIS_QUANTIZATION_ENABLED_TQENB_ENABLE = 1, //!< Use Trellis quantization 2446 }; 2447 2448 enum VSL_TOP_MB_TRANS8X8FLAG 2449 { 2450 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 2451 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 2452 }; 2453 2454 //! \brief BSP_ENCODER_ECO_ENABLE 2455 //! \details 2456 //! <p>Enable AVC Encoder BSP Bit Outstanding ECO</p> 2457 //! <p>This bit must be same as bit9 of Dword2 of MFX_PIPE_MODE_SELECT</p> 2458 enum BSP_ENCODER_ECO_ENABLE 2459 { 2460 BSP_ENCODER_ECO_ENABLE_DISABLE = 0, //!< No additional details 2461 BSP_ENCODER_ECO_ENABLE_ENABLE = 1, //!< No additional details 2462 }; 2463 2464 //! \brief FRAMEBITRATEMINUNITMODE 2465 //! \details 2466 //! This field is the Frame Bitrate Minimum Limit Units. 2467 enum FRAMEBITRATEMINUNITMODE 2468 { 2469 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2470 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2471 }; 2472 2473 //! \brief FRAMEBITRATEMINUNIT 2474 //! \details 2475 //! This field is the Frame Bitrate Minimum Limit Units. 2476 enum FRAMEBITRATEMINUNIT 2477 { 2478 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 2479 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2480 }; 2481 2482 //! \brief FRAMEBITRATEMAXUNITMODE 2483 //! \details 2484 //! This field is the Frame Bitrate Maximum Limit Units. 2485 enum FRAMEBITRATEMAXUNITMODE 2486 { 2487 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2488 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2489 }; 2490 2491 //! \brief FRAMEBITRATEMAXUNIT_ 2492 //! \details 2493 //! This field is the Frame Bitrate Maximum Limit Units. 2494 enum FRAMEBITRATEMAXUNIT_ 2495 { 2496 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 2497 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2498 }; 2499 2500 //! \brief FRAMEBITRATEMAXDELTA 2501 //! \details 2502 //! This field is used to select the slice delta QP when FrameBitRateMax Is 2503 //! exceeded. It shares the same FrameBitrateMaxUnit. When 2504 //! FrameBitrateMaxUnitMode is 0(compatibility mode) bits 16:27 should be 2505 //! used, bits 28, 29 and 30 should be 0. 2506 enum FRAMEBITRATEMAXDELTA 2507 { 2508 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 2509 }; 2510 2511 enum VAD_ERROR_LOGIC 2512 { 2513 VAD_ERROR_LOGIC_ENABLE = 0, //!< Error reporting ON in case of premature Slice done 2514 VAD_ERROR_LOGIC_DISABLE = 1, //!< CABAC Engine will auto decode the bitstream in case of premature slice done. 2515 }; 2516 2517 //! \brief INTER_VIEW_ORDER_DISABLE 2518 //! \details 2519 //! It indicates how to append inter-view picture into initial sorted 2520 //! reference list. (due to ambiguity in the MVC Spec) 2521 enum INTER_VIEW_ORDER_DISABLE 2522 { 2523 INTER_VIEW_ORDER_DISABLE_DEFAULT = 0, //!< View Order Ascending 2524 INTER_VIEW_ORDER_DISABLE_DISABLE = 1, //!< View ID Ascending 2525 }; 2526 2527 //! \name Initializations 2528 2529 //! \brief Explicit member initialization function 2530 MFX_AVC_IMG_STATE_CMD(); 2531 2532 static const size_t dwSize = 21; 2533 static const size_t byteSize = 84; 2534 }; 2535 2536 //! 2537 //! \brief MFX_AVC_REF_IDX_STATE 2538 //! \details 2539 //! This is a slice level command and can be issued multiple times within a 2540 //! picture that is comprised of multiple slices. The same command is used 2541 //! for AVC encoder (PAK mode) and decoder (VLD mode); it is not need in 2542 //! decoder IT mode. The inline data of this command is interpreted 2543 //! differently for encoder as for decoder. For decoder, it is interpreted 2544 //! as RefIdx List L0/L1 as in AVC spec., and it matches with the AVC 2545 //! API data structure for decoder in VLD mode : RefPicList[2][32] (L0:L1, 2546 //! 0:31 RefPic). But for encoder, it is interpreted as a Reference Index 2547 //! Mapping Table for L0 and L1 reference pictures. For packing the bits at 2548 //! the output of PAK, the syntax elements must follow the definition of 2549 //! RefIdxL0/L1 list according to the AVC spec. However, the decoder 2550 //! pipeline was designed to use a variation of that standard definition, as 2551 //! such a conversion (mapping) is needed to support the hardware design. 2552 //! The Reference lists are needed in processing both P and B slice in AVC 2553 //! codec. For P-MB, only L0 list is used; for B-MB both L0 and L1 lists are 2554 //! needed. For a B-MB that is coded in L1-only Prediction, only L1 list is 2555 //! used. 2556 //! 2557 //! specifies that an application will create the RefPicList L0 and L1 2558 //! and pass onto the driver. The content of each entry of RefPicList 2559 //! L0/L1[ ] is a 7-bit picture index. This picture index is the same as 2560 //! that of RefFrameList[ ] content. This picture index, however, is not 2561 //! defined the same as the frame store ID (0 to 16, 5-bits) we have 2562 //! implemented in H/W. Hence, driver is required to manage a table to 2563 //! convert between picture index and intel frame store ID. As such, 2564 //! the final RefPicList L0/L1[ ] that the driver passes onto the H/W is not 2565 //! the same as that defined. 2566 //! 2567 struct MFX_AVC_REF_IDX_STATE_CMD 2568 { 2569 union 2570 { 2571 //!< DWORD 0 2572 struct 2573 { 2574 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2575 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2576 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2577 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 2578 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 2579 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2580 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2581 }; 2582 uint32_t Value; 2583 } DW0; 2584 union 2585 { 2586 //!< DWORD 1 2587 struct 2588 { 2589 uint32_t RefpiclistSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLIST_SELECT 2590 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2591 }; 2592 uint32_t Value; 2593 } DW1; 2594 2595 uint32_t ReferenceListEntry[8]; //!< Reference List Entry 2596 2597 2598 //! \name Local enumerations 2599 2600 enum SUBOPCODEB 2601 { 2602 SUBOPCODEB_MFXAVCREFIDXSTATE = 4, //!< No additional details 2603 }; 2604 2605 enum SUBOPCODEA 2606 { 2607 SUBOPCODEA_MFXAVCREFIDXSTATE = 0, //!< No additional details 2608 }; 2609 2610 enum COMMAND_OPCODE 2611 { 2612 COMMAND_OPCODE_AVC = 1, //!< No additional details 2613 }; 2614 2615 enum PIPELINE 2616 { 2617 PIPELINE_MFXAVCREFIDXSTATE = 2, //!< No additional details 2618 }; 2619 2620 enum COMMAND_TYPE 2621 { 2622 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2623 }; 2624 2625 //! \brief REFPICLIST_SELECT 2626 //! \details 2627 //! <p>Num_ref_idx_l1_active is resulted from the specifications in both PPS 2628 //! and Slice Header for the current slice. However, since the full 2629 //! reference list L0 and/or L1 are always sent, only present flags are 2630 //! specified instead.</p> 2631 //! <p>This parameter is specified for Intel interface only, not 2632 //! present in the .</p> 2633 enum REFPICLIST_SELECT 2634 { 2635 REFPICLIST_SELECT_REFPICLIST0 = 0, //!< The list that followed represents RefList L0 (Decoder VLD mode) or Ref Idx Mapping Table L0 (Encoder PAK mode) 2636 REFPICLIST_SELECT_REFPICLIST1 = 1, //!< The list that followed represents RefList L1 (Decoder VLD mode) or Ref Idx Mapping Table L1 (Encoder PAK mode) 2637 }; 2638 2639 //! \name Initializations 2640 2641 //! \brief Explicit member initialization function 2642 MFX_AVC_REF_IDX_STATE_CMD(); 2643 2644 static const size_t dwSize = 10; 2645 static const size_t byteSize = 40; 2646 }; 2647 2648 //! 2649 //! \brief MFX_AVC_WEIGHTOFFSET_STATE 2650 //! \details 2651 //! This is a slice level command and can be issued multiple times within a 2652 //! picture that is comprised of multiple slices. The same command is used 2653 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). However, 2654 //! since for AVC decoder VLD and IT modes, and AVC encoder mode, the 2655 //! implicit weights are computed in hardware, this command is not issued. 2656 //! For encoder, regardless of the type of weight calculation is active for 2657 //! the current slice (default, implicit or explicit), they are all sent to 2658 //! the PAK as if they were all in explicit mode. However, for implicit 2659 //! weight and offset, each entry contains only a 16-bit weight and no 2660 //! offset (offset = 0 always in implicit mode and can be hard-coded inside 2661 //! the hardware).The weights (and offsets) are needed in processing both P 2662 //! and B slice in AVC codec. For P-MB, at most only L0 list is used; for 2663 //! B-MB both L0 and L1 lists may be needed. For a B-MB that is coded in 2664 //! L1-only Prediction, only L1 list is sent.The content of this command 2665 //! matches with the AVC API data structure for explicit prediction 2666 //! mode only : Weights[2][32][3][2] (L0:L1, 0:31 RefPic, Y:Cb:Cr, W:0) 2667 //! 2668 struct MFX_AVC_WEIGHTOFFSET_STATE_CMD 2669 { 2670 union 2671 { 2672 //!< DWORD 0 2673 struct 2674 { 2675 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2676 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2677 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 2678 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 2679 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 2680 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2681 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2682 }; 2683 uint32_t Value; 2684 } DW0; 2685 union 2686 { 2687 //!< DWORD 1 2688 struct 2689 { 2690 uint32_t WeightAndOffsetSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< WEIGHT_AND_OFFSET_SELECT 2691 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2692 }; 2693 uint32_t Value; 2694 } DW1; 2695 2696 uint32_t Weightoffset[96]; //!< WeightOffset 2697 2698 2699 //! \name Local enumerations 2700 2701 enum SUBOPCODE_B 2702 { 2703 SUBOPCODE_B_UNNAMED5 = 5, //!< No additional details 2704 }; 2705 2706 enum SUBOPCODE_A 2707 { 2708 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2709 }; 2710 2711 enum MEDIA_COMMAND_OPCODE 2712 { 2713 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2714 }; 2715 2716 enum PIPELINE 2717 { 2718 PIPELINE_MFXAVCWEIGHTOFFSETSTATE = 2, //!< No additional details 2719 }; 2720 2721 enum COMMAND_TYPE 2722 { 2723 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2724 }; 2725 2726 //! \brief WEIGHT_AND_OFFSET_SELECT 2727 //! \details 2728 //! It must be set in consistent with the WeightedPredFlag and 2729 //! WeightedBiPredIdc in the Img_State command. 2730 //! This parameter is specified for Intel interface only, not present 2731 //! in the . 2732 //! For implicit even though only one entry may be used, still loading 2733 //! the whole 32-entry table. 2734 enum WEIGHT_AND_OFFSET_SELECT 2735 { 2736 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL0TABLE = 0, //!< The list that followed is associated with the weight and offset for RefPicList L0 2737 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL1TABLE = 1, //!< The list that followed is associated with the weight and offset for RefPicList L1 2738 }; 2739 2740 //! \name Initializations 2741 2742 //! \brief Explicit member initialization function 2743 MFX_AVC_WEIGHTOFFSET_STATE_CMD(); 2744 2745 static const size_t dwSize = 98; 2746 static const size_t byteSize = 392; 2747 }; 2748 2749 //! 2750 //! \brief MFX_AVC_SLICE_STATE 2751 //! \details 2752 //! This is a slice level command and can be issued multiple times within a 2753 //! picture that is comprised of multiple slices. The same command is used 2754 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). 2755 //! 2756 //! In VDEnc mode, this command is programmed for every super-slice. However 2757 //! not all parameters are allowed to change across super-slices. 2758 //! 2759 //! MFX_AVC_SLICE_STATE command is not issued for AVC Short Format 2760 //! Bitstream decode, instead MFD_AVC_SLICEADDR command is executed to 2761 //! retrieve the next slice MB Start Address X and Y by H/W itself. 2762 //! 2763 struct MFX_AVC_SLICE_STATE_CMD 2764 { 2765 union 2766 { 2767 //!< DWORD 0 2768 struct 2769 { 2770 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2771 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2772 uint32_t CommandSubopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< COMMAND_SUBOPCODEB 2773 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 2774 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 2775 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2776 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2777 }; 2778 uint32_t Value; 2779 } DW0; 2780 union 2781 { 2782 //!< DWORD 1 2783 struct 2784 { 2785 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 3) ; //!< SLICE_TYPE 2786 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 2787 }; 2788 uint32_t Value; 2789 } DW1; 2790 union 2791 { 2792 //!< DWORD 2 2793 struct 2794 { 2795 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD( 0, 2) ; //!< Log 2 Weight Denom Luma 2796 uint32_t Reserved67 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2797 uint32_t Log2WeightDenomChroma : __CODEGEN_BITFIELD( 8, 10) ; //!< Log 2 Weight Denom Chroma 2798 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 2799 uint32_t NumberOfReferencePicturesInInterPredictionList0 : __CODEGEN_BITFIELD(16, 21) ; //!< Number of Reference Pictures in Inter-prediction List 0 2800 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2801 uint32_t NumberOfReferencePicturesInInterPredictionList1 : __CODEGEN_BITFIELD(24, 29) ; //!< Number of Reference Pictures in Inter-prediction List 1 2802 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2803 }; 2804 uint32_t Value; 2805 } DW2; 2806 union 2807 { 2808 //!< DWORD 3 2809 struct 2810 { 2811 uint32_t SliceAlphaC0OffsetDiv2 : __CODEGEN_BITFIELD( 0, 3) ; //!< Slice Alpha C0 Offset Div2 2812 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 2813 uint32_t SliceBetaOffsetDiv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< Slice Beta Offset Div2 2814 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2815 uint32_t SliceQuantizationParameter : __CODEGEN_BITFIELD(16, 21) ; //!< Slice Quantization Parameter 2816 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2817 uint32_t CabacInitIdc10 : __CODEGEN_BITFIELD(24, 25) ; //!< Cabac Init Idc[1:0] 2818 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 2819 uint32_t DisableDeblockingFilterIndicator : __CODEGEN_BITFIELD(27, 28) ; //!< DISABLE_DEBLOCKING_FILTER_INDICATOR 2820 uint32_t DirectPredictionType : __CODEGEN_BITFIELD(29, 29) ; //!< DIRECT_PREDICTION_TYPE 2821 uint32_t WeightedPredictionIndicator : __CODEGEN_BITFIELD(30, 31) ; //!< Weighted Prediction Indicator 2822 }; 2823 uint32_t Value; 2824 } DW3; 2825 union 2826 { 2827 //!< DWORD 4 2828 struct 2829 { 2830 uint32_t SliceStartMbNum : __CODEGEN_BITFIELD( 0, 14) ; //!< Slice Start Mb Num 2831 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2832 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Horizontal Position 2833 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(24, 31) ; //!< Slice Vertical Position 2834 }; 2835 uint32_t Value; 2836 } DW4; 2837 union 2838 { 2839 //!< DWORD 5 2840 struct 2841 { 2842 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< Next Slice Horizontal Position 2843 uint32_t Reserved168 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2844 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(16, 24) ; //!< Next Slice Vertical Position 2845 uint32_t Reserved184 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 2846 }; 2847 uint32_t Value; 2848 } DW5; 2849 union 2850 { 2851 //!< DWORD 6 2852 struct 2853 { 2854 uint32_t StreamId10 : __CODEGEN_BITFIELD( 0, 1) ; //!< Stream ID [1:0] 2855 uint32_t Reserved194 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 2856 uint32_t SliceId30 : __CODEGEN_BITFIELD( 4, 7) ; //!< Slice ID [3:0] 2857 uint32_t Reserved200 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 2858 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD(12, 12) ; //!< CABACZEROWORDINSERTIONENABLE 2859 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD(13, 13) ; //!< EMULATIONBYTESLICEINSERTENABLE 2860 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 2861 uint32_t TailInsertionPresentInBitstream : __CODEGEN_BITFIELD(15, 15) ; //!< TAIL_INSERTION_PRESENT_IN_BITSTREAM 2862 uint32_t SlicedataInsertionPresentInBitstream : __CODEGEN_BITFIELD(16, 16) ; //!< SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2863 uint32_t HeaderInsertionPresentInBitstream : __CODEGEN_BITFIELD(17, 17) ; //!< HEADER_INSERTION_PRESENT_IN_BITSTREAM 2864 uint32_t Reserved210 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 2865 uint32_t IsLastSlice : __CODEGEN_BITFIELD(19, 19) ; //!< IS_LAST_SLICE 2866 uint32_t MbTypeSkipConversionDisable : __CODEGEN_BITFIELD(20, 20) ; //!< MB_TYPE_SKIP_CONVERSION_DISABLE 2867 uint32_t MbTypeDirectConversionDisable : __CODEGEN_BITFIELD(21, 21) ; //!< MB_TYPE_DIRECT_CONVERSION_DISABLE 2868 uint32_t RcPanicType : __CODEGEN_BITFIELD(22, 22) ; //!< RC_PANIC_TYPE 2869 uint32_t RcPanicEnable : __CODEGEN_BITFIELD(23, 23) ; //!< RC_PANIC_ENABLE 2870 uint32_t RcStableTolerance : __CODEGEN_BITFIELD(24, 27) ; //!< RC Stable Tolerance 2871 uint32_t RcTriggleMode : __CODEGEN_BITFIELD(28, 29) ; //!< RC_TRIGGLE_MODE 2872 uint32_t Resetratecontrolcounter : __CODEGEN_BITFIELD(30, 30) ; //!< RESETRATECONTROLCOUNTER 2873 uint32_t RateControlCounterEnable : __CODEGEN_BITFIELD(31, 31) ; //!< RATE_CONTROL_COUNTER_ENABLE 2874 }; 2875 uint32_t Value; 2876 } DW6; 2877 union 2878 { 2879 //!< DWORD 7 2880 struct 2881 { 2882 uint32_t IndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect PAK-BSE Data Start Address (Write) 2883 uint32_t Reserved253 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2884 }; 2885 uint32_t Value; 2886 } DW7; 2887 union 2888 { 2889 //!< DWORD 8 2890 struct 2891 { 2892 uint32_t GrowParamGrowInit : __CODEGEN_BITFIELD( 0, 3) ; //!< Grow Param - Grow Init 2893 uint32_t GrowParamGrowResistance : __CODEGEN_BITFIELD( 4, 7) ; //!< Grow Param - Grow Resistance 2894 uint32_t ShrinkParamShrinkInit : __CODEGEN_BITFIELD( 8, 11) ; //!< Shrink Param - Shrink Init 2895 uint32_t ShrinkParamShrinkResistance : __CODEGEN_BITFIELD(12, 15) ; //!< Shrink Param - Shrink Resistance 2896 uint32_t MagnitudeOfQpMaxPositiveModifier : __CODEGEN_BITFIELD(16, 23) ; //!< Magnitude of QP Max Positive Modifier 2897 uint32_t MagnitudeOfQpMaxNegativeModifier : __CODEGEN_BITFIELD(24, 31) ; //!< Magnitude of QP Max Negative Modifier 2898 }; 2899 uint32_t Value; 2900 } DW8; 2901 union 2902 { 2903 //!< DWORD 9 2904 struct 2905 { 2906 uint32_t Correct1 : __CODEGEN_BITFIELD( 0, 3) ; //!< Correct 1 2907 uint32_t Correct2 : __CODEGEN_BITFIELD( 4, 7) ; //!< Correct 2 2908 uint32_t Correct3 : __CODEGEN_BITFIELD( 8, 11) ; //!< Correct 3 2909 uint32_t Correct4 : __CODEGEN_BITFIELD(12, 15) ; //!< Correct 4 2910 uint32_t Correct5 : __CODEGEN_BITFIELD(16, 19) ; //!< Correct 5 2911 uint32_t Correct6 : __CODEGEN_BITFIELD(20, 23) ; //!< Correct 6 2912 uint32_t Roundintra : __CODEGEN_BITFIELD(24, 26) ; //!< ROUNDINTRA 2913 uint32_t Roundintraenable : __CODEGEN_BITFIELD(27, 27) ; //!< RoundIntraEnable 2914 uint32_t Roundinter : __CODEGEN_BITFIELD(28, 30) ; //!< ROUNDINTER 2915 uint32_t Roundinterenable : __CODEGEN_BITFIELD(31, 31) ; //!< RoundInterEnable 2916 }; 2917 uint32_t Value; 2918 } DW9; 2919 union 2920 { 2921 //!< DWORD 10 2922 struct 2923 { 2924 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 2925 uint32_t Cv1 : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 2926 uint32_t Cv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 2927 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 2928 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 2929 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 2930 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 2931 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31) ; //!< ClampValues - CV7 2932 }; 2933 uint32_t Value; 2934 } DW10; 2935 2936 //! \name Local enumerations 2937 2938 enum COMMAND_SUBOPCODEB 2939 { 2940 COMMAND_SUBOPCODEB_MFXAVCSLICESTATE = 3, //!< No additional details 2941 }; 2942 2943 enum SUBOPCODEA 2944 { 2945 SUBOPCODEA_MFXAVCSLICESTATE = 0, //!< No additional details 2946 }; 2947 2948 enum COMMAND_OPCODE 2949 { 2950 COMMAND_OPCODE_AVC = 1, //!< No additional details 2951 }; 2952 2953 enum PIPELINE 2954 { 2955 PIPELINE_MFXAVCSLICESTATE = 2, //!< No additional details 2956 }; 2957 2958 enum COMMAND_TYPE 2959 { 2960 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2961 }; 2962 2963 //! \brief SLICE_TYPE 2964 //! \details 2965 //! It is set to the value of the syntax element read from the Slice Header. 2966 enum SLICE_TYPE 2967 { 2968 SLICE_TYPE_PSLICE = 0, //!< No additional details 2969 SLICE_TYPE_BSLICE = 1, //!< No additional details 2970 SLICE_TYPE_ISLICE = 2, //!< No additional details 2971 }; 2972 2973 enum DISABLE_DEBLOCKING_FILTER_INDICATOR 2974 { 2975 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED0 = 0, //!< FilterInternalEdgesFlag is set equal to 1 2976 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED1 = 1, //!< Disable all deblocking operation, no deblocking parameter syntax element is read; filterInternalEdgesFlag is set equal to 0 2977 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED2 = 2, //!< Macroblocks in different slices are considered not available; filterInternalEdgesFlag is set equal to 1 2978 }; 2979 2980 //! \brief DIRECT_PREDICTION_TYPE 2981 //! \details 2982 //! Type of direct prediction used for B Slices. This field is valid only 2983 //! for Slice_Type = B Slice; otherwise, it must be set to 0. 2984 enum DIRECT_PREDICTION_TYPE 2985 { 2986 DIRECT_PREDICTION_TYPE_TEMPORAL = 0, //!< No additional details 2987 DIRECT_PREDICTION_TYPE_SPATIAL = 1, //!< No additional details 2988 }; 2989 2990 //! \brief CABACZEROWORDINSERTIONENABLE 2991 //! \details 2992 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2993 //! requirement. 2994 enum CABACZEROWORDINSERTIONENABLE 2995 { 2996 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion 2997 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP(effectively can be used as an indicator for last slice of a picture, if the assumption is only the last slice of a picture needs to insert CABAC_ZERO_WORDs. 2998 }; 2999 3000 //! \brief EMULATIONBYTESLICEINSERTENABLE 3001 //! \details 3002 //! To have PAK outputting SODB or EBSP to the output bitstream buffer 3003 enum EMULATIONBYTESLICEINSERTENABLE 3004 { 3005 EMULATIONBYTESLICEINSERTENABLE_UNNAMED0 = 0, //!< outputting RBSP 3006 EMULATIONBYTESLICEINSERTENABLE_UNNAMED1 = 1, //!< outputting EBSP 3007 }; 3008 3009 //! \brief TAIL_INSERTION_PRESENT_IN_BITSTREAM 3010 //! \details 3011 //! <p>This bit should only be set for the last super slice.</p> 3012 //! <p><span style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 3013 //! line-height: normal;">SKL Restriction: In VDENC mode, SW should insert 3014 //! 1000 </span><b style="color: rgb(0, 0, 0); font-family: Arial, 3015 //! sans-serif; line-height: normal;">VD_PIPELINE_FLUSH commands with 3016 //! VDENC_pipeline_Done set to 1 before inserting tail command. This is for 3017 //! delaying the tail insertion in HW. The HW recommendation is to insert 3018 //! tail only at the end of sequence to avoid performance loss since this 3019 //! restriction potentially cause performance degradation.</b></p> 3020 enum TAIL_INSERTION_PRESENT_IN_BITSTREAM 3021 { 3022 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits 3023 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 3024 }; 3025 3026 //! \brief SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 3027 //! \details 3028 //! <p>This bit should be set for all super-slices.</p> 3029 enum SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 3030 { 3031 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No Slice Data insertion into the output bitstream buffer 3032 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Slice Data insertion into the output bitstream buffer is present. 3033 }; 3034 3035 //! \brief HEADER_INSERTION_PRESENT_IN_BITSTREAM 3036 //! \details 3037 //! Note: In VDEnc mode, the slice header PAK object maximum size is 25 DWs. 3038 enum HEADER_INSERTION_PRESENT_IN_BITSTREAM 3039 { 3040 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, in front of the current slice encoded bits. 3041 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 3042 }; 3043 3044 //! \brief IS_LAST_SLICE 3045 //! \details 3046 //! It is used by the zero filling in the Minimum Frame Size test. 3047 enum IS_LAST_SLICE 3048 { 3049 IS_LAST_SLICE_UNNAMED0 = 0, //!< Current slice is NOT the last slice of a picture 3050 IS_LAST_SLICE_UNNAMED1 = 1, //!< Current slice is the last slice of a picture 3051 }; 3052 3053 //! \brief MB_TYPE_SKIP_CONVERSION_DISABLE 3054 //! \details 3055 //! For all Macroblock type conversions in different slices, refer to 3056 //! Section "Macroblock Type Conversion Rules" in the same volume. 3057 enum MB_TYPE_SKIP_CONVERSION_DISABLE 3058 { 3059 MB_TYPE_SKIP_CONVERSION_DISABLE_ENABLESKIPTYPECONVERSION = 0, //!< No additional details 3060 MB_TYPE_SKIP_CONVERSION_DISABLE_DISABLESKIPTYPECONVERSION = 1, //!< No additional details 3061 }; 3062 3063 //! \brief MB_TYPE_DIRECT_CONVERSION_DISABLE 3064 //! \details 3065 //! For all Macroblock type conversions in different slices, refer to 3066 //! Section "Macroblock Type Conversion Rules" in the same volume. 3067 enum MB_TYPE_DIRECT_CONVERSION_DISABLE 3068 { 3069 MB_TYPE_DIRECT_CONVERSION_DISABLE_ENABLEDIRECTMODECONVERSION = 0, //!< No additional details 3070 MB_TYPE_DIRECT_CONVERSION_DISABLE_DISABLEDIRECTMODECONVERSION = 1, //!< No additional details 3071 }; 3072 3073 //! \brief RC_PANIC_TYPE 3074 //! \details 3075 //! This field selects between two RC Panic methods 3076 enum RC_PANIC_TYPE 3077 { 3078 RC_PANIC_TYPE_QPPANIC = 0, //!< No additional details 3079 RC_PANIC_TYPE_CBPPANIC = 1, //!< No additional details 3080 }; 3081 3082 //! \brief RC_PANIC_ENABLE 3083 //! \details 3084 //! If this field is set to 1, RC enters panic mode when sum_act > 3085 //! sum_max. RC Panic Type field controls what type of panic behavior is 3086 //! invoked. 3087 enum RC_PANIC_ENABLE 3088 { 3089 RC_PANIC_ENABLE_DISABLE = 0, //!< No additional details 3090 RC_PANIC_ENABLE_ENABLE = 1, //!< No additional details 3091 }; 3092 3093 enum RC_TRIGGLE_MODE 3094 { 3095 RC_TRIGGLE_MODE_ALWAYSRATECONTROL = 0, //!< Whereas RC becomes active if sum_act > sum_target or sum_act < sum_target 3096 RC_TRIGGLE_MODE_GENTLERATECONTROL = 1, //!< whereas RC becomes active if sum_act > upper_midpt or sum_act < lower_midpt 3097 RC_TRIGGLE_MODE_LOOSERATECONTROL = 2, //!< whereas RC becomes active if sum_act > sum_max or sum_act < sum_min 3098 }; 3099 3100 //! \brief RESETRATECONTROLCOUNTER 3101 //! \details 3102 //! To reset the bit allocation accumulation counter to 0 to restart the 3103 //! rate control. 3104 enum RESETRATECONTROLCOUNTER 3105 { 3106 RESETRATECONTROLCOUNTER_NOTRESET = 0, //!< No additional details 3107 RESETRATECONTROLCOUNTER_RESET = 1, //!< No additional details 3108 }; 3109 3110 //! \brief RATE_CONTROL_COUNTER_ENABLE 3111 //! \details 3112 //! To enable the accumulation of bit allocation for rate control 3113 //! This field enables hardware Rate Control logic. The rest of the RC 3114 //! control fields are only valid when this field is set to 1. Otherwise, 3115 //! hardware ignores these fields. 3116 enum RATE_CONTROL_COUNTER_ENABLE 3117 { 3118 RATE_CONTROL_COUNTER_ENABLE_DISABLE = 0, //!< No additional details 3119 RATE_CONTROL_COUNTER_ENABLE_ENABLE = 1, //!< No additional details 3120 }; 3121 3122 //! \brief ROUNDINTRA 3123 //! \details 3124 //! Rounding precision for Intra quantized coefficients 3125 enum ROUNDINTRA 3126 { 3127 ROUNDINTRA_116 = 0, //!< No additional details 3128 ROUNDINTRA_216 = 1, //!< No additional details 3129 ROUNDINTRA_316 = 2, //!< No additional details 3130 ROUNDINTRA_416 = 3, //!< No additional details 3131 ROUNDINTRA_516 = 4, //!< No additional details 3132 ROUNDINTRA_616 = 5, //!< No additional details 3133 ROUNDINTRA_716 = 6, //!< No additional details 3134 ROUNDINTRA_816 = 7, //!< No additional details 3135 }; 3136 3137 //! \brief ROUNDINTER 3138 //! \details 3139 //! Rounding precision for Inter quantized coefficients 3140 enum ROUNDINTER 3141 { 3142 ROUNDINTER_116 = 0, //!< No additional details 3143 ROUNDINTER_216 = 1, //!< No additional details 3144 ROUNDINTER_316 = 2, //!< No additional details 3145 ROUNDINTER_416 = 3, //!< No additional details 3146 ROUNDINTER_516 = 4, //!< No additional details 3147 ROUNDINTER_616 = 5, //!< No additional details 3148 ROUNDINTER_716 = 6, //!< No additional details 3149 ROUNDINTER_816 = 7, //!< No additional details 3150 }; 3151 3152 //! \name Initializations 3153 3154 //! \brief Explicit member initialization function 3155 MFX_AVC_SLICE_STATE_CMD(); 3156 3157 static const size_t dwSize = 11; 3158 static const size_t byteSize = 44; 3159 }; 3160 3161 //! 3162 //! \brief MFD_AVC_DPB_STATE 3163 //! \details 3164 //! This is a frame level state command used only in AVC Short Slice 3165 //! Bitstream Format VLD mode. RefFrameList[16] of interface is 3166 //! replaced with intel Reference Picture Addresses[16] of 3167 //! MFX_PIPE_BUF_ADDR_STATE command. The LongTerm Picture flag indicator of 3168 //! all reference pictures are collected into LongTermPic_Flag[16]. 3169 //! FieldOrderCntList[16][2] and CurrFieldOrderCnt[2] of interface are 3170 //! replaced with intel POCList[34] of MFX_AVC_DIRECTMODE_STATE command. 3171 //! 3172 struct MFD_AVC_DPB_STATE_CMD 3173 { 3174 union 3175 { 3176 //!< DWORD 0 3177 struct 3178 { 3179 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3180 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3181 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3182 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3183 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3184 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3185 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3186 }; 3187 uint32_t Value; 3188 } DW0; 3189 union 3190 { 3191 //!< DWORD 1 3192 struct 3193 { 3194 uint32_t NonExistingframeFlag161Bit : __CODEGEN_BITFIELD( 0, 15) ; //!< NON_EXISTINGFRAME_FLAG161_BIT 3195 uint32_t LongtermframeFlag161Bit : __CODEGEN_BITFIELD(16, 31) ; //!< LONGTERMFRAME_FLAG161_BIT 3196 }; 3197 uint32_t Value; 3198 } DW1; 3199 union 3200 { 3201 //!< DWORD 2 3202 struct 3203 { 3204 uint32_t UsedforreferenceFlag162Bits ; //!< USEDFORREFERENCE_FLAG162_BITS 3205 }; 3206 uint32_t Value; 3207 } DW2; 3208 3209 uint32_t Ltstframenumlist1616Bits[8]; //!< LTSTFRAMENUMLIST1616_BITS 3210 3211 3212 uint32_t Viewidlist1616Bits[8]; //!< ViewIDList[16][16 bits] 3213 3214 3215 uint32_t Vieworderlistl0168Bits[4]; //!< ViewOrderListL0[16][8 bits] 3216 3217 3218 uint32_t Vieworderlistl1168Bits[4]; //!< ViewOrderListL1[16][8 bits] 3219 3220 3221 //! \name Local enumerations 3222 3223 enum SUBOPCODE_B 3224 { 3225 SUBOPCODE_B_UNNAMED6 = 6, //!< No additional details 3226 }; 3227 3228 enum SUBOPCODE_A 3229 { 3230 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3231 }; 3232 3233 enum MEDIA_COMMAND_OPCODE 3234 { 3235 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3236 }; 3237 3238 enum PIPELINE 3239 { 3240 PIPELINE_MFXMULTIDW = 2, //!< No additional details 3241 }; 3242 3243 enum COMMAND_TYPE 3244 { 3245 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3246 }; 3247 3248 //! \brief NON_EXISTINGFRAME_FLAG161_BIT 3249 //! \details 3250 //! One-to-one correspondence with the entries of the Intel 3251 //! RefFrameList[16]. 1 bit per reference frame. 3252 enum NON_EXISTINGFRAME_FLAG161_BIT 3253 { 3254 NON_EXISTINGFRAME_FLAG161_BIT_VALID = 0, //!< the reference picture in that entry of RefFrameList[] is a valid reference 3255 NON_EXISTINGFRAME_FLAG161_BIT_INVALID = 1, //!< the reference picture in that entry of RefFrameList[] does not exist anymore. 3256 }; 3257 3258 //! \brief LONGTERMFRAME_FLAG161_BIT 3259 //! \details 3260 //! One-to-one correspondence with the entries of the Intel 3261 //! RefFrameList[16]. 1 bit per reference frame. 3262 enum LONGTERMFRAME_FLAG161_BIT 3263 { 3264 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISASHORTTERMREFERENCEPICTURE = 0, //!< No additional details 3265 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISALONGTERMREFERENCEPICTURE = 1, //!< No additional details 3266 }; 3267 3268 //! \brief USEDFORREFERENCE_FLAG162_BITS 3269 //! \details 3270 //! One-to-one correspondence with the entries of the Intel 3271 //! RefFrameList[16]. 2 bits per reference frame. 3272 enum USEDFORREFERENCE_FLAG162_BITS 3273 { 3274 USEDFORREFERENCE_FLAG162_BITS_NOTREFERENCE = 0, //!< indicates a frame is "not used for reference". 3275 USEDFORREFERENCE_FLAG162_BITS_TOPFIELD = 1, //!< bit[0] indicates that the top field of a frame is marked as "used for reference". 3276 USEDFORREFERENCE_FLAG162_BITS_BOTTOMFIELD = 2, //!< bit[1] indicates that the bottom field of a frame is marked as "used for reference". 3277 USEDFORREFERENCE_FLAG162_BITS_FRAME = 3, //!< bit[1:0] indicates that a frame (or field pair) is marked as "used for reference". 3278 }; 3279 3280 //! \brief LTSTFRAMENUMLIST1616_BITS 3281 //! \details 3282 //! One-to-one correspondence with the entries of the Intel 3283 //! RefFrameList[16]. 16 bits per reference frame.Depending on the 3284 //! corresponding LongTermFrame_Flag[], the content of this field is 3285 //! interpreted differently. 3286 enum LTSTFRAMENUMLIST1616_BITS 3287 { 3288 LTSTFRAMENUMLIST1616_BITS_SHORTTERMFRAMEFLAGI = 0, //!< LTSTFrameNumList[i]represent Short Term Picture FrameNum. 3289 LTSTFRAMENUMLIST1616_BITS_LONGTERMFRAMEFLAGI = 1, //!< LTSTFrameNumList[i] represent LongTermFrameIdx. 3290 }; 3291 3292 //! \name Initializations 3293 3294 //! \brief Explicit member initialization function 3295 MFD_AVC_DPB_STATE_CMD(); 3296 3297 static const size_t dwSize = 27; 3298 static const size_t byteSize = 108; 3299 }; 3300 3301 //! 3302 //! \brief MFD_AVC_SLICEADDR 3303 //! \details 3304 //! This is a Slice level command used only for AVC Short Slice 3305 //! Bitstream Format VLD mode.When decoding a slice, H/W needs to know the 3306 //! last MB of the slice has reached in order to start decoding the next 3307 //! slice. It also needs to know if a slice is terminated but the last MB 3308 //! has not reached, error conealment should be invoked to generate those 3309 //! missing MBs. For AVC Short Format, the only way to know the last 3310 //! MB position of the current slice, H/W needs to snoop into the next 3311 //! slice's start MB address (a linear address encoded in the Slice Header). 3312 //! Since each BSD Object command can have only one indirect bitstream 3313 //! buffer address, this command is added to help H/W to snoop into the next 3314 //! slice's slice header and retrieve its Start MB Address. This command 3315 //! will take the next slice's bitstream buffer address as input (exactly 3316 //! the same way as a BSD Object command), and parse only the 3317 //! first_mb_in_slice syntax element. The result will stored inside the H/W, 3318 //! and will be used to decode the current slice specified in the BSD Object 3319 //! command.Only the very first few bytes (max 5 bytes for a max 4K picture) 3320 //! of the Slice Header will be decoded, the rest of the bitstream are don't 3321 //! care. This is because the first_mb_in_slice is encoded in Exponential 3322 //! Golomb, and will take 33 bits to represent the max 256 x 256 = 64K-1 3323 //! value. The indirect data of MFD_AVC_SLICEADDR is a valid BSD object and 3324 //! is decoded as in BSD OBJECT command.The next Slice Start MB Address is 3325 //! also exposed to the MMIO interface.The Slice Start MB Address 3326 //! (first_mb_in_slice) is a linear MB address count; but it is translated 3327 //! into the corresponding 2D MB X and Y raster position, and are stored 3328 //! internally as NextSliceMbY and NextSliceMbX. 3329 //! 3330 struct MFD_AVC_SLICEADDR_CMD 3331 { 3332 union 3333 { 3334 //!< DWORD 0 3335 struct 3336 { 3337 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3338 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3339 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3340 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3341 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3342 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3343 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3344 }; 3345 uint32_t Value; 3346 } DW0; 3347 union 3348 { 3349 //!< DWORD 1 3350 struct 3351 { 3352 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3353 }; 3354 uint32_t Value; 3355 } DW1; 3356 union 3357 { 3358 //!< DWORD 2 3359 struct 3360 { 3361 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect BSD Data Start Address 3362 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3363 }; 3364 uint32_t Value; 3365 } DW2; 3366 union 3367 { 3368 //!< DWORD 3 3369 struct 3370 { 3371 uint32_t DriverProvidedNalTypeValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Driver Provided NAL Type Value 3372 uint32_t AvcNalTypeFirstByteOverrideBit : __CODEGEN_BITFIELD( 8, 8) ; //!< AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3373 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 3374 }; 3375 uint32_t Value; 3376 } DW3; 3377 3378 //! \name Local enumerations 3379 3380 enum SUBOPCODE_B 3381 { 3382 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 3383 }; 3384 3385 enum SUBOPCODE_A 3386 { 3387 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3388 }; 3389 3390 enum MEDIA_COMMAND_OPCODE 3391 { 3392 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3393 }; 3394 3395 enum PIPELINE 3396 { 3397 PIPELINE_MFDAVCSLICEADDR = 2, //!< No additional details 3398 }; 3399 3400 enum COMMAND_TYPE 3401 { 3402 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3403 }; 3404 3405 //! \brief AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3406 //! \details 3407 //! <p>This bit indicates hardware should use the NAL Type (provided below) 3408 //! programmed by driver instead of using the one from bitstream. The NAL 3409 //! byte from bitstream will not be correct.</p> 3410 enum AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3411 { 3412 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEBITSTREAMDECODEDNALTYPE = 0, //!< NAL Type should come from first byte of decoded bitstream. 3413 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEDRIVERPROGRAMMEDNALTYPE = 1, //!< NAL Type should come from "Driver Provided NAL Type Values" programmed by driver. 3414 }; 3415 3416 //! \name Initializations 3417 3418 //! \brief Explicit member initialization function 3419 MFD_AVC_SLICEADDR_CMD(); 3420 3421 static const size_t dwSize = 4; 3422 static const size_t byteSize = 16; 3423 }; 3424 3425 //! 3426 //! \brief MFD_AVC_BSD_OBJECT 3427 //! \details 3428 //! The MFD_AVC_BSD_OBJECT command is the only primitive command for the AVC 3429 //! Decoding Pipeline. The same command is used for both CABAC and CAVLD 3430 //! modes. The Slice Data portion of the bitstream is loaded as indirect 3431 //! data object.Before issuing a MFD_AVC_BSD_OBJECT command, all AVC states 3432 //! of the MFD Engine need to be valid. Therefore the commands used to set 3433 //! these states need to have been issued prior to the issue of a 3434 //! MFD_AVC_BSD_OBJECT command. 3435 //! 3436 //! Context switch interrupt is not supported by this command. 3437 //! 3438 struct MFD_AVC_BSD_OBJECT_CMD 3439 { 3440 union 3441 { 3442 //!< DWORD 0 3443 struct 3444 { 3445 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3446 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3447 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3448 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3449 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3450 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3451 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3452 }; 3453 uint32_t Value; 3454 } DW0; 3455 union 3456 { 3457 //!< DWORD 1 3458 struct 3459 { 3460 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3461 }; 3462 uint32_t Value; 3463 } DW1; 3464 union 3465 { 3466 //!< DWORD 2 3467 struct 3468 { 3469 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect BSD Data Start Address 3470 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3471 }; 3472 uint32_t Value; 3473 } DW2; 3474 union 3475 { 3476 //!< DWORD 3 3477 struct 3478 { 3479 uint32_t MbErrorConcealmentPSliceWeightPredictionDisableFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3480 uint32_t MbErrorConcealmentPSliceMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3481 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 3482 uint32_t MbErrorConcealmentBSpatialWeightPredictionDisableFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3483 uint32_t MbErrorConcealmentBSpatialMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3484 uint32_t Reserved101 : __CODEGEN_BITFIELD( 5, 5) ; //!< Reserved 3485 uint32_t MbErrorConcealmentBSpatialPredictionMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3486 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD( 8, 8) ; //!< MB_HEADER_ERROR_HANDLING_ 3487 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 3488 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10) ; //!< ENTROPY_ERROR_HANDLING 3489 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 3490 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3491 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 3492 uint32_t BsdPrematureCompleteErrorHandling : __CODEGEN_BITFIELD(14, 14) ; //!< BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3493 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3494 uint32_t ConcealmentPictureId : __CODEGEN_BITFIELD(16, 21) ; //!< Concealment Picture ID 3495 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3496 uint32_t MbErrorConcealmentBTemporalWeightPredictionDisableFlag : __CODEGEN_BITFIELD(24, 24) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3497 uint32_t MbErrorConcealmentBTemporalMotionVectorsOverrideEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3498 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 3499 uint32_t MbErrorConcealmentBTemporalPredictionMode : __CODEGEN_BITFIELD(27, 28) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3500 uint32_t IntraPredmode4X48X8LumaErrorControlBit : __CODEGEN_BITFIELD(29, 29) ; //!< INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3501 uint32_t InitCurrentMbNumber : __CODEGEN_BITFIELD(30, 30) ; //!< Init Current MB Number 3502 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31) ; //!< CONCEALMENT_METHOD 3503 }; 3504 uint32_t Value; 3505 } DW3; 3506 union 3507 { 3508 //!< DWORD 4 3509 struct 3510 { 3511 uint32_t FirstMacroblockMbBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< First Macroblock (MB)Bit Offset 3512 uint32_t LastsliceFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< LASTSLICE_FLAG 3513 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD( 4, 4) ; //!< EMULATION_PREVENTION_BYTE_PRESENT 3514 uint32_t Reserved133 : __CODEGEN_BITFIELD( 5, 6) ; //!< Reserved 3515 uint32_t FixPrevMbSkipped : __CODEGEN_BITFIELD( 7, 7) ; //!< Fix Prev Mb Skipped 3516 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3517 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31) ; //!< First MB Byte Offset of Slice Data or Slice Header 3518 }; 3519 uint32_t Value; 3520 } DW4; 3521 union 3522 { 3523 //!< DWORD 5 3524 struct 3525 { 3526 uint32_t IntraPredictionErrorControlBitAppliedToIntra16X16Intra8X8Intra4X4LumaAndChroma : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3527 uint32_t Intra8X84X4PredictionErrorConcealmentControlBit : __CODEGEN_BITFIELD( 1, 1) ; //!< INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3528 uint32_t Reserved162 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 3529 uint32_t BSliceTemporalInterConcealmentMode : __CODEGEN_BITFIELD( 4, 6) ; //!< B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3530 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3531 uint32_t BSliceSpatialInterConcealmentMode : __CODEGEN_BITFIELD( 8, 10) ; //!< B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3532 uint32_t Reserved171 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 3533 uint32_t BSliceInterDirectTypeConcealmentMode : __CODEGEN_BITFIELD(12, 13) ; //!< B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3534 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 3535 uint32_t BSliceConcealmentMode : __CODEGEN_BITFIELD(15, 15) ; //!< B_SLICE_CONCEALMENT_MODE 3536 uint32_t PSliceInterConcealmentMode : __CODEGEN_BITFIELD(16, 18) ; //!< P_SLICE_INTER_CONCEALMENT_MODE 3537 uint32_t Reserved179 : __CODEGEN_BITFIELD(19, 22) ; //!< Reserved 3538 uint32_t PSliceConcealmentMode : __CODEGEN_BITFIELD(23, 23) ; //!< P_SLICE_CONCEALMENT_MODE 3539 uint32_t ConcealmentReferencePictureFieldBit : __CODEGEN_BITFIELD(24, 29) ; //!< Concealment Reference Picture + Field Bit 3540 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 3541 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31) ; //!< I_SLICE_CONCEALMENT_MODE 3542 }; 3543 uint32_t Value; 3544 } DW5; 3545 union 3546 { 3547 //!< DWORD 6 3548 struct 3549 { 3550 uint32_t DriverProvidedNalTypeValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Driver Provided Nal Type Value 3551 uint32_t AvcNalTypeFirstByteOverrideBit : __CODEGEN_BITFIELD( 8, 8) ; //!< AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3552 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 3553 }; 3554 uint32_t Value; 3555 } DW6; 3556 3557 //! \name Local enumerations 3558 3559 enum SUBOPCODE_B 3560 { 3561 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3562 }; 3563 3564 enum SUBOPCODE_A 3565 { 3566 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3567 }; 3568 3569 enum MEDIA_COMMAND_OPCODE 3570 { 3571 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3572 }; 3573 3574 enum PIPELINE 3575 { 3576 PIPELINE_MFDAVCBSDOBJECT = 2, //!< No additional details 3577 }; 3578 3579 enum COMMAND_TYPE 3580 { 3581 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3582 }; 3583 3584 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3585 //! \details 3586 //! During MB Error Concealment on P slice, weight prediction is disabled to 3587 //! improve image quality. 3588 //! This bit can be set to preserve the original weight prediction. 3589 //! This bit does not affect normal decoded MB. 3590 enum MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3591 { 3592 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3593 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3594 }; 3595 3596 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3597 //! \details 3598 //! During MB Error Concealment on P slice, motion vectors are forced to 0 3599 //! to improve image quality. 3600 //! This bit can be set to use the predicted motion vectors instead. 3601 //! This bit does not affect normal decoded MB. 3602 enum MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3603 { 3604 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3605 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3606 }; 3607 3608 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3609 //! \details 3610 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3611 //! weight prediction is disabled to improve image quality. 3612 //! This bit can be set to preserve the original weight prediction. 3613 //! This bit does not affect normal decoded MB. 3614 enum MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3615 { 3616 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3617 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3618 }; 3619 3620 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3621 //! \details 3622 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3623 //! motion vectors are forced to 0 to improve image quality. 3624 //! This bit can be set to use the predicted motion vectors instead. 3625 //! This bit does not affect normal decoded MB. 3626 enum MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3627 { 3628 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3629 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3630 }; 3631 3632 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3633 //! \details 3634 //! These two bits control how the reference L0/L1 are overridden in B 3635 //! spatial slice. 3636 enum MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3637 { 3638 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3639 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3640 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3641 }; 3642 3643 //! \brief MB_HEADER_ERROR_HANDLING_ 3644 //! \details 3645 //! Software must follow the action for each Value as follow: 3646 enum MB_HEADER_ERROR_HANDLING_ 3647 { 3648 MB_HEADER_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error concealment. 3649 MB_HEADER_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3650 }; 3651 3652 //! \brief ENTROPY_ERROR_HANDLING 3653 //! \details 3654 //! Software must follow the action for each Value as follow: 3655 enum ENTROPY_ERROR_HANDLING 3656 { 3657 ENTROPY_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error handling. 3658 ENTROPY_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3659 }; 3660 3661 //! \brief MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3662 //! \details 3663 //! Software must follow the action for each Value as follow: 3664 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3665 { 3666 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3667 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3668 }; 3669 3670 //! \brief BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3671 //! \details 3672 //! BSD Premature Complete Error occurs in situation where the Slice decode 3673 //! is completed but there are still data in the bitstream. 3674 enum BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3675 { 3676 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3677 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3678 }; 3679 3680 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3681 //! \details 3682 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3683 //! weight prediction is disabled to improve image quality. 3684 //! This bit can be set to preserve the original weight prediction. 3685 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3686 { 3687 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment 3688 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment 3689 }; 3690 3691 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3692 //! \details 3693 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3694 //! motion vectors are forced to 0 to improve image quality. 3695 //! This bit can be set to preserve the original weight prediction. 3696 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3697 { 3698 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED0 = 0, //!< Predicted Motion Vectors are used during MB Concealment 3699 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED1 = 1, //!< Motion Vectors are Overridden to 0 during MB Concealment 3700 }; 3701 3702 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3703 //! \details 3704 //! These two bits control how the reference L0/L1 are overridden in B 3705 //! temporal slice. 3706 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3707 { 3708 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3709 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3710 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3711 }; 3712 3713 //! \brief INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3714 //! \details 3715 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3716 //! decoded value is incorrect according to MB position 3717 enum INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3718 { 3719 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will detect and fix IntraPredMode (4x4/8x8 Luma) Errors. 3720 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will NOT detect IntraPredMode (4x4/8x8 Luma) Errors. The wrong IntraPredMode value will be retaind. 3721 }; 3722 3723 //! \brief CONCEALMENT_METHOD 3724 //! \details 3725 //! This field specifies the method used for concealment when error is 3726 //! detected. If set, a copy from collocated macroblock location is 3727 //! performed from the concealment reference indicated by the ConCeal_Pic_Id 3728 //! field. If it is not set, a copy from the current picture is performed 3729 //! using Intra 16x16 Prediction method. 3730 enum CONCEALMENT_METHOD 3731 { 3732 CONCEALMENT_METHOD_UNNAMED0 = 0, //!< Intra 16x16 Prediction 3733 CONCEALMENT_METHOD_UNNAMED1 = 1, //!< Inter P Copy 3734 }; 3735 3736 //! \brief LASTSLICE_FLAG 3737 //! \details 3738 //! It is needed for both error concealment at the end of a picture (so, no 3739 //! more phantom slice as in DevSNB). It is also needed to know to set the 3740 //! last MB in a picture correctly. 3741 enum LASTSLICE_FLAG 3742 { 3743 LASTSLICE_FLAG_UNNAMED0 = 0, //!< If the current Slice to be decoded is any slice other than the very last slice of the current picture 3744 LASTSLICE_FLAG_UNNAMED1 = 1, //!< If the current Slice to be decoded is the very last slice of the current picture. 3745 }; 3746 3747 enum EMULATION_PREVENTION_BYTE_PRESENT 3748 { 3749 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 3750 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 3751 }; 3752 3753 //! \brief INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3754 //! \details 3755 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3756 //! decoded value is incorrect according to MB position. 3757 enum INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3758 { 3759 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED0 = 0, //!< AVC decoder will detect and fix Intra Prediction Mode Errors. 3760 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED1 = 1, //!< AVC decoder will retain the Intra Prediction value decoded from bitstream. 3761 }; 3762 3763 //! \brief INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3764 //! \details 3765 //! This field controls if AVC goes into MB concealment mode (next MB) when 3766 //! an error is detected on Intra8x8/4x4 Prediction Mode (these 2 modes have 3767 //! fixed coding so it may not affect the bitstream. 3768 enum INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3769 { 3770 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will NOT go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3771 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3772 }; 3773 3774 //! \brief B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3775 //! \details 3776 //! This field controls how AVC decoder select reference picture for 3777 //! Temporal Inter Concealment in B Slice 3778 enum B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3779 { 3780 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1) 3781 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3782 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using B-Skip Algorithm) 3783 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< " Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3784 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< First Long Term Picture in Reference List L0/L1(If no long term picture available, use Temporal Closest Picture) 3785 }; 3786 3787 //! \brief B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3788 //! \details 3789 //! This field controls how AVC decoder select reference picture for Spatial 3790 //! Inter Concealment in B Slice. 3791 enum B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3792 { 3793 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1). 3794 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3795 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3796 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< " First Long Term Picture in Reference List L0/L1 (If no long term picture available, use Temporal Closest Picture) 3797 }; 3798 3799 //! \brief B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3800 //! \details 3801 //! AVC decoder can use Spatial or Temporal Direct for B Skip/Direct. 3802 //! This field determine can override the mode on how AVC decoder 3803 //! handles MB concealment in B slice. 3804 enum B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3805 { 3806 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Use Default Direct Type (slice programmed direct type) 3807 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Forced to Spatial Direct Only 3808 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Forced to Temporal Direct Only 3809 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Spatial Direct without Temporal Componenet (MovingBlock information) 3810 }; 3811 3812 //! \brief B_SLICE_CONCEALMENT_MODE 3813 //! \details 3814 //! This field controls how AVC decoder handle MB concealment in B Slice 3815 enum B_SLICE_CONCEALMENT_MODE 3816 { 3817 B_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3818 B_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3819 }; 3820 3821 //! \brief P_SLICE_INTER_CONCEALMENT_MODE 3822 //! \details 3823 //! This field controls how AVC decoder select reference picture for 3824 //! Concealment in P Slice. 3825 enum P_SLICE_INTER_CONCEALMENT_MODE 3826 { 3827 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0 (Use top entry of Reference List L0) 3828 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3829 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using P-Skip Algorithm) 3830 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC] 3831 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< First Long Term Picture in Reference List L0 (If no long term picture available, use Temporal Closest Picture) 3832 }; 3833 3834 //! \brief P_SLICE_CONCEALMENT_MODE 3835 //! \details 3836 //! This field controls how AVC decoder handle MB concealment in P Slice 3837 enum P_SLICE_CONCEALMENT_MODE 3838 { 3839 P_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3840 P_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3841 }; 3842 3843 //! \brief I_SLICE_CONCEALMENT_MODE 3844 //! \details 3845 //! This field controls how AVC decoder handle MB concealment in I Slice 3846 enum I_SLICE_CONCEALMENT_MODE 3847 { 3848 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< No additional details 3849 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< No additional details 3850 }; 3851 3852 //! \brief AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3853 //! \details 3854 //! <p>This bit indicates hardware should use the NAL Type (provided below) 3855 //! programmed by driver instead of using the one from bitstream. The NAL 3856 //! byte from bitstream will not be correct.</p> 3857 enum AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3858 { 3859 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEBITSTREAMDECODEDNALTYPE = 0, //!< NAL Type should come from the first byte of Decoded Bitstream 3860 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEDRIVERPROGRAMMEDNALTYPE = 1, //!< NAL Type should come from "Driver Provided Nal Type" programmed by driver. 3861 }; 3862 3863 //! \name Initializations 3864 3865 //! \brief Explicit member initialization function 3866 MFD_AVC_BSD_OBJECT_CMD(); 3867 3868 static const size_t dwSize = 7; 3869 static const size_t byteSize = 28; 3870 }; 3871 3872 //! 3873 //! \brief MFX_PAK_INSERT_OBJECT 3874 //! \details 3875 //! The MFX_PAK_INSERT_OBJECT command is the first primitive command for the 3876 //! AVC, MPEG2, JPEG, SVC and VP8 Encoding Pipeline. 3877 //! 3878 //! This command is issued to setup the control and parameters of inserting 3879 //! a chunk of compressed/encoded bits into the current bitstream output 3880 //! buffer starting at the specified bit locationto perform the actual 3881 //! insertion by transferring the command inline data to the output buffer 3882 //! max, 32 bits at a time. It is a variable length command as the data to 3883 //! be inserted are presented as inline data of this command. It is a 3884 //! multiple of 32-bit (1 DW), as the data bus to the bitstream buffer is 3885 //! 32-bit wide. Multiple insertion commands can be issued back to back in a 3886 //! series. It is host software's responsibility to make sure their 3887 //! corresponding data will properly stitch together to form a valid H.264 3888 //! bitstream. Internally, MFX hardware will keep track of the very last two 3889 //! bytes' (the very last byte can be a partial byte) values of the previous 3890 //! insertion. It is required that the next Insertion Object Command or the 3891 //! next PAK Object Command to perform the start code emulation sequence 3892 //! check and prevention 0x03 byte insertion with this end condition of the 3893 //! previous insertion. Hardware will keep track of an output bitstream 3894 //! buffer current byte position and the associated next bit insertion 3895 //! position index. Data to be inserted can be a valid H.264 NAL units or a 3896 //! partial NAL unit. Certain NAL unit has a minimum byte size requirement. 3897 //! As such the hardware will optionally (enabled by STATE Command) 3898 //! determines the number of CABAC_ZERO_WORD to be inserted to the end of 3899 //! the current NAL, based on the minimum byte size of a NAL and the actual 3900 //! bin count of the encoded Slice. Since prior to the CABAC_ZERO_WORD 3901 //! insertion, the RBSP or EBSP is already byte-aligned, so each 3902 //! CABAC_ZERO_WORD insertion is actually a 3-byte sequence 0x00 00 03. The 3903 //! inline data may have already been processed for start code emulation 3904 //! byte insertion, except the possibility of the last 2 bytes plus the very 3905 //! last partial byte (if any). Hence, when hardware performing the 3906 //! concatenation of multiple consecutive insertion commands, or 3907 //! concatenation of an insertion command and a PAK object command, it must 3908 //! check and perform the necessary start code emulation byte insert at the 3909 //! junction.The inline data is required to be byte aligned on the left 3910 //! (first transmitted bit order) and may or may not be byte aligned on the 3911 //! right (last transmitted bits). The command will specify the bit offset 3912 //! of the last valid DW.Each insertion state command defines a chunk of 3913 //! bits (compressed data) to be inserted at a specific location of the 3914 //! output compressed bitstream in the output buffer.Depend on CABAC or 3915 //! CAVLC encoding mode (from Slice State), PAK Object Command is always 3916 //! ended in byte aligned output bitstream except for CABAC header insertion 3917 //! which is bit aligned. In the aligned cases, PAK will perform 0 filling 3918 //! in CAVLC mode, and 1 filling in CABAC mode. Insertion data can 3919 //! include:any encoded syntax elements bit data before the encoded Slice 3920 //! Data (PAK Object Command) of the current SliceSPS NALPPS NALSEI NALOther 3921 //! Non-Slice NALLeading_Zero_8_bits (as many bytes as there is)Start Code 3922 //! PrefixNAL Header ByteSlice HeaderAny encoded syntax elements bit data 3923 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3924 //! and prior to the next encoded Slice Data of the next Slice or prior to 3925 //! the end of the bistream, whichever comes firstCabac_Zero_Word or 3926 //! Trailing_Zero_8bits (as many bytes as there is). Anything listed above 3927 //! before a Slice DataContext switch interrupt is not supported by this 3928 //! command. 3929 //! 3930 struct MFX_PAK_INSERT_OBJECT_CMD 3931 { 3932 union 3933 { 3934 //!< DWORD 0 3935 struct 3936 { 3937 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3938 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3939 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3940 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3941 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3942 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3943 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3944 }; 3945 uint32_t Value; 3946 } DW0; 3947 union 3948 { 3949 //!< DWORD 1 3950 struct 3951 { 3952 uint32_t BitstreamstartresetResetbitstreamstartingpos : __CODEGEN_BITFIELD( 0, 0) ; //!< BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3953 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3954 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3955 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3956 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 3957 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3958 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< SLICE_HEADER_INDICATOR 3959 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3960 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3961 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 3962 }; 3963 uint32_t Value; 3964 } DW1; 3965 3966 //! \name Local enumerations 3967 3968 enum SUBOPCODE_B 3969 { 3970 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3971 }; 3972 3973 enum SUBOPCODE_A 3974 { 3975 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 3976 }; 3977 3978 enum MEDIA_COMMAND_OPCODE 3979 { 3980 MEDIA_COMMAND_OPCODE_MFXCOMMON = 0, //!< No additional details 3981 }; 3982 3983 enum PIPELINE 3984 { 3985 PIPELINE_MFXPAKINSERTOBJECT = 2, //!< No additional details 3986 }; 3987 3988 enum COMMAND_TYPE 3989 { 3990 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3991 }; 3992 3993 //! \brief BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3994 //! \details 3995 //! Must be set to 1 for JPEG encoder 3996 enum BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3997 { 3998 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_INSERT = 0, //!< Insert the current command inline data starting at the current bitstream buffer insertion position 3999 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_RESET = 1, //!< Reset the bitstream buffer insertion position to the bitstream buffer starting position. 4000 }; 4001 4002 //! \brief EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 4003 //! \details 4004 //! Must be set to 0 for JPEG encoder 4005 enum EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 4006 { 4007 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_NONE = 0, //!< No emulation 4008 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_EMULATE = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between insertion commands, or an insertion command followed by a PAK Object command. 4009 }; 4010 4011 //! \brief SLICE_HEADER_INDICATOR 4012 //! \details 4013 //! This bit indicates if the insert object is a slice header. In the VDEnc 4014 //! mode, PAK only gets this command at the beginning of the frame for slice 4015 //! position X=0, Y=0. It internally generates the header that needs to be 4016 //! inserted per slice. For VDEnc mode, this bit should always be set. 4017 enum SLICE_HEADER_INDICATOR 4018 { 4019 SLICE_HEADER_INDICATOR_LEGACY = 0, //!< Legacy Insertion Object command. The PAK Insertion Object command is not stored in HW. 4020 SLICE_HEADER_INDICATOR_SLICEHEADER = 1, //!< Insertion Object is a Slice Header. The command is stored internally by HW and is used for inserting slice headers. 4021 }; 4022 4023 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 4024 //! \details 4025 //! In case this flag is on, bits are NOT accumulated during current access 4026 //! unit coding neither for Cabac Zero Word insertion bits counting or for 4027 //! output in MMIO register MFC_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER. 4028 //! When using HeaderLenghtExcludeFrmSize for header insertion, the 4029 //! software needs to make sure that data comes already with inserted start 4030 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 4031 //! DWORD1 of MFX_PAK_INSERT_OBJECT). 4032 enum HEADERLENGTHEXCLUDEFRMSIZE_ 4033 { 4034 HEADERLENGTHEXCLUDEFRMSIZE_ACCUMULATE = 0, //!< All bits accumulated 4035 HEADERLENGTHEXCLUDEFRMSIZE_NOACCUMULATION = 1, //!< Bits during current call are not accumulated 4036 }; 4037 4038 //! \name Initializations 4039 4040 //! \brief Explicit member initialization function 4041 MFX_PAK_INSERT_OBJECT_CMD(); 4042 4043 static const size_t dwSize = 2; 4044 static const size_t byteSize = 8; 4045 }; 4046 4047 //! 4048 //! \brief MFX_MPEG2_PIC_STATE 4049 //! \details 4050 //! This must be the very first command to issue after the surface state, 4051 //! the pipe select and base address setting commands. For MPEG-2 the 4052 //! encoder is called per slice-group, however the picture state is called 4053 //! per picture.Notice that a slice-group is a group of consecutive slices 4054 //! that no non-trivial slice headers are inserted in between. 4055 //! 4056 struct MFX_MPEG2_PIC_STATE_CMD 4057 { 4058 union 4059 { 4060 //!< DWORD 0 4061 struct 4062 { 4063 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4064 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4065 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 4066 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 4067 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 4068 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4069 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4070 }; 4071 uint32_t Value; 4072 } DW0; 4073 union 4074 { 4075 //!< DWORD 1 4076 struct 4077 { 4078 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4079 uint32_t ScanOrder : __CODEGEN_BITFIELD( 6, 6) ; //!< SCAN_ORDER 4080 uint32_t IntraVlcFormat : __CODEGEN_BITFIELD( 7, 7) ; //!< Intra VLC Format 4081 uint32_t QuantizerScaleType : __CODEGEN_BITFIELD( 8, 8) ; //!< QUANTIZER_SCALE_TYPE 4082 uint32_t ConcealmentMotionVectorFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< Concealment Motion Vector Flag 4083 uint32_t FramePredictionFrameDct : __CODEGEN_BITFIELD(10, 10) ; //!< Frame Prediction Frame DCT 4084 uint32_t TffTopFieldFirst : __CODEGEN_BITFIELD(11, 11) ; //!< TFF (Top Field First) 4085 uint32_t PictureStructure : __CODEGEN_BITFIELD(12, 13) ; //!< Picture Structure 4086 uint32_t IntraDcPrecision : __CODEGEN_BITFIELD(14, 15) ; //!< Intra DC Precision 4087 uint32_t FCode00 : __CODEGEN_BITFIELD(16, 19) ; //!< f_code[0][0] 4088 uint32_t FCode01 : __CODEGEN_BITFIELD(20, 23) ; //!< f_code[0][1] 4089 uint32_t FCode10 : __CODEGEN_BITFIELD(24, 27) ; //!< f_code[1][0]. 4090 uint32_t FCode11 : __CODEGEN_BITFIELD(28, 31) ; //!< f_code[1][1]. 4091 }; 4092 uint32_t Value; 4093 } DW1; 4094 union 4095 { 4096 //!< DWORD 2 4097 struct 4098 { 4099 uint32_t DisableMismatch : __CODEGEN_BITFIELD( 0, 0) ; //!< Disable Mismatch 4100 uint32_t Mismatchcontroldisabled : __CODEGEN_BITFIELD( 1, 1) ; //!< MISMATCHCONTROLDISABLED 4101 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 8) ; //!< Reserved 4102 uint32_t PictureCodingType : __CODEGEN_BITFIELD( 9, 10) ; //!< PICTURE_CODING_TYPE 4103 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13) ; //!< Reserved 4104 uint32_t LoadslicepointerflagLoadbitstreampointerperslice : __CODEGEN_BITFIELD(14, 14) ; //!< LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4105 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 23) ; //!< Reserved 4106 uint32_t PBSlicePredictedMotionVectorOverrideFinalMvValueOverride : __CODEGEN_BITFIELD(24, 24) ; //!< PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4107 uint32_t PBSlicePredictedBidirMotionTypeOverrideBiDirectionMvTypeOverride : __CODEGEN_BITFIELD(25, 26) ; //!< PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4108 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 27) ; //!< Reserved 4109 uint32_t PBSliceConcealmentMode : __CODEGEN_BITFIELD(28, 29) ; //!< PB_SLICE_CONCEALMENT_MODE_ 4110 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 4111 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31) ; //!< I_SLICE_CONCEALMENT_MODE_ 4112 }; 4113 uint32_t Value; 4114 } DW2; 4115 union 4116 { 4117 //!< DWORD 3 4118 struct 4119 { 4120 uint32_t Framewidthinmbsminus170PictureWidthInMacroblocks : __CODEGEN_BITFIELD( 0, 7) ; //!< FrameWidthInMBsMinus1[7:0] (Picture Width in Macroblocks) 4121 uint32_t Reserved104 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 4122 uint32_t Frameheightinmbsminus170PictureHeightInMacroblocks : __CODEGEN_BITFIELD(16, 23) ; //!< FrameHeightInMBsMinus1[7:0] (Picture Height in Macroblocks) 4123 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 30) ; //!< Reserved 4124 uint32_t SliceConcealmentDisableBit : __CODEGEN_BITFIELD(31, 31) ; //!< SLICE_CONCEALMENT_DISABLE_BIT 4125 }; 4126 uint32_t Value; 4127 } DW3; 4128 union 4129 { 4130 //!< DWORD 4 4131 struct 4132 { 4133 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 4134 uint32_t Roundintradc : __CODEGEN_BITFIELD( 1, 2) ; //!< RoundIntraDC 4135 uint32_t Reserved131 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 4136 uint32_t Roundinterdc : __CODEGEN_BITFIELD( 4, 6) ; //!< RoundInterDC 4137 uint32_t Reserved135 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 4138 uint32_t Roundintraac : __CODEGEN_BITFIELD( 8, 10) ; //!< RoundIntraAC 4139 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 4140 uint32_t Roundinterac : __CODEGEN_BITFIELD(12, 14) ; //!< RoundInterAC, 4141 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15) ; //!< MBSTATENABLED 4142 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31) ; //!< MINFRAMEWSIZE 4143 }; 4144 uint32_t Value; 4145 } DW4; 4146 union 4147 { 4148 //!< DWORD 5 4149 struct 4150 { 4151 uint32_t Intrambmaxsizereportmask : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAMBMAXSIZEREPORTMASK 4152 uint32_t Intermbmaxsizereportmask : __CODEGEN_BITFIELD( 1, 1) ; //!< INTERMBMAXSIZEREPORTMASK 4153 uint32_t Framebitratemaxreportmask : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMEBITRATEMAXREPORTMASK_ 4154 uint32_t Framebitrateminreportmask : __CODEGEN_BITFIELD( 3, 3) ; //!< FRAMEBITRATEMINREPORTMASK 4155 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 8) ; //!< Reserved 4156 uint32_t Mbratecontrolmask : __CODEGEN_BITFIELD( 9, 9) ; //!< MBRATECONTROLMASK 4157 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11) ; //!< MINFRAMEWSIZEUNITS 4158 uint32_t Intermbforcecbpzerocontrolmask : __CODEGEN_BITFIELD(12, 12) ; //!< INTERMBFORCECBPZEROCONTROLMASK 4159 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 4160 uint32_t Framesizecontrolmask : __CODEGEN_BITFIELD(16, 16) ; //!< FRAMESIZECONTROLMASK 4161 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 4162 }; 4163 uint32_t Value; 4164 } DW5; 4165 union 4166 { 4167 //!< DWORD 6 4168 struct 4169 { 4170 uint32_t Intrambmaxsize : __CODEGEN_BITFIELD( 0, 11) ; //!< INTRAMBMAXSIZE 4171 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4172 uint32_t Intermbmaxsize : __CODEGEN_BITFIELD(16, 27) ; //!< INTERMBMAXSIZE 4173 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 4174 }; 4175 uint32_t Value; 4176 } DW6; 4177 union 4178 { 4179 //!< DWORD 7 4180 struct 4181 { 4182 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSL_TOP_MB_TRANS8X8FLAG 4183 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 4184 }; 4185 uint32_t Value; 4186 } DW7; 4187 union 4188 { 4189 //!< DWORD 8 4190 struct 4191 { 4192 uint32_t Slicedeltaqpmax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQPMax[0] 4193 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQPMax[1] 4194 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQPMax[2] 4195 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31) ; //!< SLICEDELTAQPMAX3 4196 }; 4197 uint32_t Value; 4198 } DW8; 4199 union 4200 { 4201 //!< DWORD 9 4202 struct 4203 { 4204 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQPMin[0] 4205 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQPMin[1] 4206 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQPMin[2] 4207 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQPMin[3] 4208 }; 4209 uint32_t Value; 4210 } DW9; 4211 union 4212 { 4213 //!< DWORD 10 4214 struct 4215 { 4216 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 4217 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14) ; //!< FRAMEBITRATEMINUNITMODE 4218 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15) ; //!< FRAMEBITRATEMINUNIT 4219 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29) ; //!< FrameBitRateMax 4220 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30) ; //!< FRAMEBITRATEMAXUNITMODE 4221 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT_ 4222 }; 4223 uint32_t Value; 4224 } DW10; 4225 union 4226 { 4227 //!< DWORD 11 4228 struct 4229 { 4230 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FrameBitRateMinDelta 4231 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 4232 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 4233 uint32_t Reserved383 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 4234 }; 4235 uint32_t Value; 4236 } DW11; 4237 union 4238 { 4239 //!< DWORD 12 4240 struct 4241 { 4242 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4243 }; 4244 uint32_t Value; 4245 } DW12; 4246 4247 //! \name Local enumerations 4248 4249 enum SUBOPCODE_B 4250 { 4251 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 4252 }; 4253 4254 enum SUBOPCODE_A 4255 { 4256 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 4257 }; 4258 4259 enum MEDIA_COMMAND_OPCODE 4260 { 4261 MEDIA_COMMAND_OPCODE_MPEG2COMMON = 3, //!< No additional details 4262 }; 4263 4264 enum PIPELINE 4265 { 4266 PIPELINE_MFXMPEG2PICSTATE = 2, //!< No additional details 4267 }; 4268 4269 enum COMMAND_TYPE 4270 { 4271 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4272 }; 4273 4274 //! \brief SCAN_ORDER 4275 //! \details 4276 //! This field specifies the Inverse Scan method for the DCT-domain 4277 //! coefficients in the blocks of the current picture. 4278 enum SCAN_ORDER 4279 { 4280 SCAN_ORDER_UNNAMED0 = 0, //!< MPEG_ZIGZAG_SCAN 4281 SCAN_ORDER_UNNAMED1 = 1, //!< MPEG_ALTERNATE_VERTICAL_SCAN 4282 }; 4283 4284 //! \brief QUANTIZER_SCALE_TYPE 4285 //! \details 4286 //! This field specifies the quantizer scaling type. 4287 enum QUANTIZER_SCALE_TYPE 4288 { 4289 QUANTIZER_SCALE_TYPE_UNNAMED0 = 0, //!< MPEG_QSCALE_LINEAR 4290 QUANTIZER_SCALE_TYPE_UNNAMED1 = 1, //!< D MPEG_QSCALE_NONLINEAR esc 4291 }; 4292 4293 //! \brief MISMATCHCONTROLDISABLED 4294 //! \details 4295 //! These 2 bits flag disables mismatch control of the inverse 4296 //! transformation for some specific cases during reference reconstruction. 4297 enum MISMATCHCONTROLDISABLED 4298 { 4299 MISMATCHCONTROLDISABLED_UNNAMED0 = 0, //!< Mismatch control applies to all MBs 4300 MISMATCHCONTROLDISABLED_UNNAMED1 = 1, //!< Disable mismatch control to all intra MBs whose all AC-coefficients are zero. 4301 MISMATCHCONTROLDISABLED_UNNAMED2 = 2, //!< Disable mismatch control to all MBs whose all AC-coefficients are zero. 4302 MISMATCHCONTROLDISABLED_UNNAMED3 = 3, //!< Disable mismatch control to all MBs. 4303 }; 4304 4305 //! \brief PICTURE_CODING_TYPE 4306 //! \details 4307 //! This field identifies whether the picture is an intra-coded picture (I), 4308 //! predictive-coded picture (P) or bi-directionally predictive-coded 4309 //! picture (B). See ISO/IEC 13818-2 6.3.9 for details. 4310 enum PICTURE_CODING_TYPE 4311 { 4312 PICTURE_CODING_TYPE_MPEGIPICTURE = 1, //!< No additional details 4313 PICTURE_CODING_TYPE_10MPEGPPICTURE = 2, //!< No additional details 4314 PICTURE_CODING_TYPE_MPEGBPICTURE = 3, //!< No additional details 4315 }; 4316 4317 //! \brief LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4318 //! \details 4319 //! To support multiple slice picture and additional header/data insertion 4320 //! before and after an encoded slice.When this field is set to 0, bitstream 4321 //! pointer is only loaded once for the first slice of a frame. For 4322 //! subsequent slices in the frame, bitstream data are stitched together to 4323 //! form a single output data stream.When this field is set to 1, bitstream 4324 //! pointer is loaded for each slice of a frame. Basically bitstream data 4325 //! for different slices of a frame will be written to different memory 4326 //! locations. 4327 enum LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4328 { 4329 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED0 = 0, //!< Load BitStream Pointer only once for the first slice of a frame 4330 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED1 = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 4331 }; 4332 4333 //! \brief PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4334 //! \details 4335 //! This field is only applicable if the Concealment Motion Vectors are 4336 //! non-zero. 4337 //! It is only possible if "P/B Slice Concealment Mode" is set to "00" 4338 //! or "01" and left MB has non-zero motion vectors). 4339 enum PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4340 { 4341 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_PREDICTED = 0, //!< Motion Vectors use predicted values 4342 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_ZERO = 1, //!< Motion Vectors force to 0 4343 }; 4344 4345 //! \brief PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4346 //! \details 4347 //! This field is only applicable if the Concealment Motion Type is 4348 //! predicted to be Bi-directional. 4349 //! (It is only possible if "P/B Slice Concealment Mode" is set to "00" 4350 //! or "01" and left MB is a bi-directional MB). 4351 enum PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4352 { 4353 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BID = 0, //!< Keep Bi-direction Prediction 4354 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_FWD = 2, //!< Only use Forward Prediction (Backward MV is forced to invalid 4355 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BWD = 3, //!< Only use Backward Prediction (Forward MV is forced to invalid) 4356 }; 4357 4358 //! \brief PB_SLICE_CONCEALMENT_MODE_ 4359 //! \details 4360 //! This field controls how MPEG decoder handles MB concealment in P/B 4361 //! Slice. 4362 enum PB_SLICE_CONCEALMENT_MODE_ 4363 { 4364 PB_SLICE_CONCEALMENT_MODE_INTER = 0, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use forward reference (same polarity for field pic) with MV final values set to 0. 4365 PB_SLICE_CONCEALMENT_MODE_LEFT = 1, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data) 4366 PB_SLICE_CONCEALMENT_MODE_ZERO = 2, //!< Always use forward reference (same polarity for field pic) with MV final values set to 0 (Macroblock is concealed as INTER coded) 4367 PB_SLICE_CONCEALMENT_MODE_INTRA = 3, //!< Use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data 4368 }; 4369 4370 //! \brief I_SLICE_CONCEALMENT_MODE_ 4371 //! \details 4372 //! This field controls how MPEG decoder handles MB concealment in I Slice 4373 enum I_SLICE_CONCEALMENT_MODE_ 4374 { 4375 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< Using Coefficient values to handle MB concealment 4376 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< Using Motion Vectors to handle MB concealment 4377 }; 4378 4379 //! \brief SLICE_CONCEALMENT_DISABLE_BIT 4380 //! \details 4381 //! If VINunit detects the next slice starting position is either 4382 //! out-of-bound or smaller than or equal to the current slice starting 4383 //! position, VIN will set the current slice to be 1 MB and force VMDunit to 4384 //! do slice concealment on the next slice. 4385 //! This bit will disable this feature and the MB data from the next 4386 //! slice will be decoded from bitstream. 4387 enum SLICE_CONCEALMENT_DISABLE_BIT 4388 { 4389 SLICE_CONCEALMENT_DISABLE_BIT_ENABLE = 0, //!< VIN will force next slice to be concealment if detects slice boundary error 4390 SLICE_CONCEALMENT_DISABLE_BIT_DISABLE = 1, //!< VIN will not force next slice to be in concealment 4391 }; 4392 4393 //! \brief MINFRAMEWSIZE 4394 //! \details 4395 //! - Minimum Frame Size [15:0] (16-bit) (Encoder Only)Mininum Frame Size is 4396 //! specified to compensate for intel Rate ControlCurrently zero fill (no 4397 //! need to perform emulation byte insertion) is done only to the end of the 4398 //! CABAC_ZERO_WORD insertion (if any) at the last slice of a picture. Intel 4399 //! encoder parameter, not part of . The caller should always make sure 4400 //! that the value, represented by Mininum Frame Size, is always less than 4401 //! maximum frame size FrameBitRateMax (DWORD 10 bits 29:16). This field is 4402 //! reserved in Decode mode. 4403 enum MINFRAMEWSIZE 4404 { 4405 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 4406 }; 4407 4408 //! \brief INTRAMBMAXSIZEREPORTMASK 4409 //! \details 4410 //! This is a mask bit controlling if the condition of any intra MB in the 4411 //! frame exceeds IntraMBMaxSize. 4412 enum INTRAMBMAXSIZEREPORTMASK 4413 { 4414 INTRAMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4415 INTRAMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 4416 }; 4417 4418 //! \brief INTERMBMAXSIZEREPORTMASK 4419 //! \details 4420 //! This is a mask bit controlling if the condition of any inter MB in the 4421 //! frame exceeds InterMBMaxSize. 4422 enum INTERMBMAXSIZEREPORTMASK 4423 { 4424 INTERMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4425 INTERMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 4426 }; 4427 4428 //! \brief FRAMEBITRATEMAXREPORTMASK_ 4429 //! \details 4430 //! This is a mask bit controlling if the condition of frame level bit count 4431 //! exceeds FrameBitRateMax. 4432 enum FRAMEBITRATEMAXREPORTMASK_ 4433 { 4434 FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4435 FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 4436 }; 4437 4438 //! \brief FRAMEBITRATEMINREPORTMASK 4439 //! \details 4440 //! This is a mask bit controlling if the condition of frame level bit count 4441 //! is less than FrameBitRateMin. 4442 enum FRAMEBITRATEMINREPORTMASK 4443 { 4444 FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4445 FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 4446 }; 4447 4448 //! \brief MBRATECONTROLMASK 4449 //! \details 4450 //! MB Rate Control conformance maskThis field is ignored when 4451 //! MacroblockStatEnable is disabled or MB level Rate control flag for the 4452 //! current MB is disable in Macroblock Status Buffer. 4453 enum MBRATECONTROLMASK 4454 { 4455 MBRATECONTROLMASK_UNNAMED0 = 0, //!< Do not change QP values of inter macroblock with suggested QP values in Macroblock Status Buffer 4456 MBRATECONTROLMASK_UNNAMED1 = 1, //!< Apply RC QP delta for all macroblock 4457 }; 4458 4459 //! \brief MINFRAMEWSIZEUNITS 4460 //! \details 4461 //! This field is the Minimum Frame Size Units 4462 enum MINFRAMEWSIZEUNITS 4463 { 4464 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 4465 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 4466 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 4467 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 4468 }; 4469 4470 //! \brief INTERMBFORCECBPZEROCONTROLMASK 4471 //! \details 4472 //! Inter MB Force CBP ZERO mask. 4473 enum INTERMBFORCECBPZEROCONTROLMASK 4474 { 4475 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED0 = 0, //!< No effect 4476 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED1 = 1, //!< Zero out all A/C coefficients for the inter MB violating Inter Confirmance 4477 }; 4478 4479 //! \brief FRAMESIZECONTROLMASK 4480 //! \details 4481 //! Frame size conformance maskThis field is used when MacroblockStatEnable 4482 //! is set to 1. 4483 enum FRAMESIZECONTROLMASK 4484 { 4485 FRAMESIZECONTROLMASK_UNNAMED0 = 0, //!< Do not change Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control 4486 FRAMESIZECONTROLMASK_UNNAMED1 = 1, //!< Replace Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control values in MFC_IMAGE_STATUS control register. 4487 }; 4488 4489 //! \brief INTRAMBMAXSIZE 4490 //! \details 4491 //! This field, Intra MB Conformance Max size limit,indicates the allowed 4492 //! max bit count size for Intra MB 4493 enum INTRAMBMAXSIZE 4494 { 4495 INTRAMBMAXSIZE_UNNAMED_4095 = 4095, //!< No additional details 4496 }; 4497 4498 //! \brief INTERMBMAXSIZE 4499 //! \details 4500 //! This field, Inter MB Conformance Max size limit,indicates the allowed 4501 //! max bit count size for Inter MB 4502 enum INTERMBMAXSIZE 4503 { 4504 INTERMBMAXSIZE_UNNAMED_4095 = 4095, //!< No additional details 4505 }; 4506 4507 enum VSL_TOP_MB_TRANS8X8FLAG 4508 { 4509 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 4510 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 4511 }; 4512 4513 //! \brief SLICEDELTAQPMAX3 4514 //! \details 4515 //! This field is the Slice level delta QP for total 4516 //! bit-count above FrameBitRateMax - first 1/8 regionThis field is 4517 //! used to 4518 //! calculate the suggested slice QP into the MFC_IMAGE_STATUS control 4519 //! register when 4520 //! total bit count for the entire frame exceeds FrameBitRateMax but is 4521 //! within 1/8 4522 //! of FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range 4523 //! of 4524 //! (FrameBitRateMax, (FrameBitRateMax+ 4525 //! FrameBitRateMaxDelta>>3). 4526 enum SLICEDELTAQPMAX3 4527 { 4528 SLICEDELTAQPMAX3_DISABLE = 0, //!< No additional details 4529 SLICEDELTAQPMAX3_ENABLE = 1, //!< No additional details 4530 }; 4531 4532 //! \brief FRAMEBITRATEMINUNITMODE 4533 //! \details 4534 //! This field is the Frame Bitrate Minimum Limit 4535 //! Units.ValueNameDescriptionProject 4536 enum FRAMEBITRATEMINUNITMODE 4537 { 4538 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4539 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4540 }; 4541 4542 //! \brief FRAMEBITRATEMINUNIT 4543 //! \details 4544 //! This field is the Frame Bitrate Minimum Limit Units. 4545 enum FRAMEBITRATEMINUNIT 4546 { 4547 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 4548 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4549 }; 4550 4551 //! \brief FRAMEBITRATEMAXUNITMODE 4552 //! \details 4553 //! BitFiel This field is the Frame Bitrate Maximum Limit Units.dDesc 4554 enum FRAMEBITRATEMAXUNITMODE 4555 { 4556 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4557 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4558 }; 4559 4560 //! \brief FRAMEBITRATEMAXUNIT_ 4561 //! \details 4562 //! This field is the Frame Bitrate Maximum Limit Units. 4563 enum FRAMEBITRATEMAXUNIT_ 4564 { 4565 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 4566 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4567 }; 4568 4569 //! \brief FRAMEBITRATEMAXDELTA 4570 //! \details 4571 //! This field is used to select the slice delta QP when FrameBitRateMax Is 4572 //! exceeded. It shares the same FrameBitrateMaxUnit. 4573 //! The programmable range is either 0- 512KB or 4MBB in 4574 //! FrameBitrateMaxUnit of 128 Bytes or 16KB respectively. 4575 enum FRAMEBITRATEMAXDELTA 4576 { 4577 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 4578 }; 4579 4580 //! \name Initializations 4581 4582 //! \brief Explicit member initialization function 4583 MFX_MPEG2_PIC_STATE_CMD(); 4584 4585 static const size_t dwSize = 13; 4586 static const size_t byteSize = 52; 4587 }; 4588 4589 //! 4590 //! \brief MFD_MPEG2_BSD_OBJECT 4591 //! \details 4592 //! Different from AVC and VC1, MFD_MPEG2_BSD_OBJECT command is pipelinable. 4593 //! This is for performance purpose as in MPEG2 a slice is defined as a 4594 //! group of MBs of any size that must be within a macroblock row.Slice 4595 //! header parameters are passed in as inline data and the bitstream data 4596 //! for the slice is passed in as indirect data. Of the inline data, 4597 //! slice_horizontal_position and slice_vertical_position determines the 4598 //! location within the destination picture of the first macroblock in the 4599 //! slice. The content in this command is identical to that in the 4600 //! MEDIA_OBJECT command in VLD mode described in the Media Chapter. 4601 //! 4602 struct MFD_MPEG2_BSD_OBJECT_CMD 4603 { 4604 union 4605 { 4606 //!< DWORD 0 4607 struct 4608 { 4609 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4610 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4611 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 4612 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 4613 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 4614 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4615 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4616 }; 4617 uint32_t Value; 4618 } DW0; 4619 union 4620 { 4621 //!< DWORD 1 4622 struct 4623 { 4624 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 4625 }; 4626 uint32_t Value; 4627 } DW1; 4628 union 4629 { 4630 //!< DWORD 2 4631 struct 4632 { 4633 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 4634 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4635 }; 4636 uint32_t Value; 4637 } DW2; 4638 union 4639 { 4640 //!< DWORD 3 4641 struct 4642 { 4643 uint32_t FirstMacroblockBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< First Macroblock Bit Offset 4644 uint32_t IsLastMb : __CODEGEN_BITFIELD( 3, 3) ; //!< IS_LAST_MB 4645 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 4646 uint32_t LastPicSlice : __CODEGEN_BITFIELD( 5, 5) ; //!< LAST_PIC_SLICE 4647 uint32_t SliceConcealmentTypeBit : __CODEGEN_BITFIELD( 6, 6) ; //!< SLICE_CONCEALMENT_TYPE_BIT 4648 uint32_t SliceConcealmentOverrideBit : __CODEGEN_BITFIELD( 7, 7) ; //!< SLICE_CONCEALMENT_OVERRIDE_BIT 4649 uint32_t MacroblockCount : __CODEGEN_BITFIELD( 8, 15) ; //!< Macroblock Count 4650 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Vertical Position 4651 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(24, 31) ; //!< Slice Horizontal Position 4652 }; 4653 uint32_t Value; 4654 } DW3; 4655 union 4656 { 4657 //!< DWORD 4 4658 struct 4659 { 4660 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD( 0, 7) ; //!< Next Slice Horizontal Position 4661 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD( 8, 16) ; //!< Next Slice Vertical Position 4662 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 23) ; //!< Reserved 4663 uint32_t QuantizerScaleCode : __CODEGEN_BITFIELD(24, 28) ; //!< Quantizer Scale Code 4664 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4665 }; 4666 uint32_t Value; 4667 } DW4; 4668 4669 //! \name Local enumerations 4670 4671 enum SUBOPCODE_B 4672 { 4673 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 4674 }; 4675 4676 enum SUBOPCODE_A 4677 { 4678 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 4679 }; 4680 4681 enum MEDIA_COMMAND_OPCODE 4682 { 4683 MEDIA_COMMAND_OPCODE_MPEG2DEC = 3, //!< No additional details 4684 }; 4685 4686 enum PIPELINE 4687 { 4688 PIPELINE_MFDMPEG2BSDOBJECT = 2, //!< No additional details 4689 }; 4690 4691 enum COMMAND_TYPE 4692 { 4693 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4694 }; 4695 4696 enum IS_LAST_MB 4697 { 4698 IS_LAST_MB_UNNAMED0 = 0, //!< The current MB is not the last MB in the current Slice 4699 IS_LAST_MB_UNNAMED1 = 1, //!< The current MB is the last MB in the current Slice 4700 }; 4701 4702 //! \brief LAST_PIC_SLICE 4703 //! \details 4704 //! This bit is added to support error concealment at the end of a picture. 4705 enum LAST_PIC_SLICE 4706 { 4707 LAST_PIC_SLICE_UNNAMED0 = 0, //!< The current Slice is not the last Slice of current picture 4708 LAST_PIC_SLICE_UNNAMED1 = 1, //!< The current Slice is the last Slice of the entire picture 4709 }; 4710 4711 //! \brief SLICE_CONCEALMENT_TYPE_BIT 4712 //! \details 4713 //! This bit can be forced by driver ("Slice Concealment Override Bit") or 4714 //! set by VINunit depending on slice boundary errors. 4715 enum SLICE_CONCEALMENT_TYPE_BIT 4716 { 4717 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED0 = 0, //!< VMD will decode MBs from the bitstream until the bitstream is run-out. Then VMD will conceal the remaining MBs. 4718 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED1 = 1, //!< VMD will conceal all MBs of the slice regardless of bitstream. (If driver does not force the value of this bit, VIN will set this bit depending on slice boundary error. If the next slice position of the current slice is out-of-bound or the same or earlier than the current slice start position, VIN will set this bit for the next slice) 4719 }; 4720 4721 //! \brief SLICE_CONCEALMENT_OVERRIDE_BIT 4722 //! \details 4723 //! This bit forces hardware to handle the current slice in Conceal or 4724 //! Deocde Mode. If this bit is set to one, VIN will force the current 4725 //! slice to do concealment or to decode from bitstream regardless if the 4726 //! slice boundary has errors or not. 4727 enum SLICE_CONCEALMENT_OVERRIDE_BIT 4728 { 4729 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED0 = 0, //!< Driver must program "Slice Concealment Type" to '0'. VIN will set "Slice Concealment Type" depending if the slice boundary has error or not 4730 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED1 = 1, //!< VIN will use driver-provided "Slice Concealment Type" regardless of valid slice boundary 4731 }; 4732 4733 //! \name Initializations 4734 4735 //! \brief Explicit member initialization function 4736 MFD_MPEG2_BSD_OBJECT_CMD(); 4737 4738 static const size_t dwSize = 5; 4739 static const size_t byteSize = 20; 4740 }; 4741 4742 //! 4743 //! \brief MFD_IT_OBJECT_MPEG2_INLINE_DATA 4744 //! \details 4745 //! The content in this command is similar to that in the MEDIA_OBJECT 4746 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4747 //! command corresponds to the processing of one macroblock. Macroblock 4748 //! parameters are passed in as inline data and the non-zero DCT coefficient 4749 //! data for the macroblock is passed in as indirect data. Inline data 4750 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4751 //! 4752 struct MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD 4753 { 4754 union 4755 { 4756 //!< DWORD 0 4757 struct 4758 { 4759 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 2); //!< Reserved 4760 uint32_t Lastmbinrow : __CODEGEN_BITFIELD(3, 3); //!< LastMBInRow 4761 uint32_t Reserved4 : __CODEGEN_BITFIELD(4, 5); //!< Reserved 4762 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD(6, 11); //!< Coded Block Pattern 4763 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4764 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16); //!< MACROBLOCK_INTRA_TYPE 4765 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17); //!< MACROBLOCK_MOTION_FORWARD 4766 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18); //!< MACROBLOCK_MOTION_BACKWARD 4767 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 20); //!< Reserved 4768 uint32_t DctType : __CODEGEN_BITFIELD(21, 21); //!< DCT_TYPE 4769 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 4770 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25); //!< Motion Type 4771 uint32_t Reserved26 : __CODEGEN_BITFIELD(26, 27); //!< Reserved 4772 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31); //!< MOTION_VERTICAL_FIELD_SELECT 4773 }; 4774 uint32_t Value; 4775 } DW0; 4776 union 4777 { 4778 //!< DWORD 1 4779 struct 4780 { 4781 uint32_t Horzorigin : __CODEGEN_BITFIELD(0, 7); //!< HorzOrigin 4782 uint32_t Vertorigin : __CODEGEN_BITFIELD(8, 15); //!< VertOrigin 4783 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 4784 }; 4785 uint32_t Value; 4786 } DW1; 4787 union 4788 { 4789 //!< DWORD 2 4790 struct 4791 { 4792 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Forward, Horizontal Component 4793 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Forward, Vertical Component 4794 }; 4795 uint32_t Value; 4796 } DW2; 4797 union 4798 { 4799 //!< DWORD 3 4800 struct 4801 { 4802 uint32_t MotionVectorsField0BackwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Backward, Horizontal Component 4803 uint32_t MotionVectorsField0BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Backward, Vertical Component 4804 }; 4805 uint32_t Value; 4806 } DW3; 4807 union 4808 { 4809 //!< DWORD 4 4810 struct 4811 { 4812 uint32_t MotionVectorsField1ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 1, Forward, Horizontal Component 4813 uint32_t MotionVectorsField1ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 1, Forward, Vertical Component 4814 }; 4815 uint32_t Value; 4816 } DW4; 4817 union 4818 { 4819 //!< DWORD 5 4820 struct 4821 { 4822 uint32_t MotionVectorsField1BackwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 1, Backward, Horizontal Component 4823 uint32_t MotionVectorsField1BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 1, Backward, Vertical Component 4824 }; 4825 uint32_t Value; 4826 } DW5; 4827 4828 //! \name Local enumerations 4829 4830 //! \brief MACROBLOCK_INTRA_TYPE 4831 //! \details 4832 //! This field specifies if the current macroblock is intra-coded. When set, 4833 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 4834 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 4835 enum MACROBLOCK_INTRA_TYPE 4836 { 4837 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 4838 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 4839 }; 4840 4841 //! \brief MACROBLOCK_MOTION_FORWARD 4842 //! \details 4843 //! This field specifies if the forward motion vector is active. See ISO/IEC 4844 //! 13818-2 Tables B-2 through B-4. 4845 enum MACROBLOCK_MOTION_FORWARD 4846 { 4847 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 4848 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTORS = 1, //!< No additional details 4849 }; 4850 4851 //! \brief MACROBLOCK_MOTION_BACKWARD 4852 //! \details 4853 //! This field specifies if the backward motion vector is active. See 4854 //! ISO/IEC 13818-2 Tables B-2 through B-4. 4855 enum MACROBLOCK_MOTION_BACKWARD 4856 { 4857 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 4858 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTORS = 1, //!< No additional details 4859 }; 4860 4861 //! \brief DCT_TYPE 4862 //! \details 4863 //! This field specifies the DCT type of the current macroblock. The kernel 4864 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 4865 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 4866 //! (no coded blocks present). 4867 enum DCT_TYPE 4868 { 4869 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 4870 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 4871 }; 4872 4873 //! \brief MOTION_VERTICAL_FIELD_SELECT 4874 //! \details 4875 //! A bit-wise representation of a long [2][2] array as defined in 4876 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also #167;7.6.4). 4877 //! <table> 4878 //! <thead> 4879 //! 4880 //! <tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 4881 //! Index</td></tr> 4882 //! </thead> 4883 //! <tbody> 4884 //! <tr><td>28</td><td>0</td><td>0</td><td>0</td></tr> 4885 //! <tr><td>29</td><td>0</td><td>1</td><td>1</td></tr> 4886 //! <tr><td>30</td><td>1</td><td>0</td><td>2</td></tr> 4887 //! <tr><td>31</td><td>1</td><td>1</td><td>3</td></tr> 4888 //! </tbody> 4889 //! </table> 4890 enum MOTION_VERTICAL_FIELD_SELECT 4891 { 4892 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field. 4893 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 4894 }; 4895 4896 //! \name Initializations 4897 4898 //! \brief Explicit member initialization function 4899 MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD(); 4900 4901 static const size_t dwSize = 6; 4902 static const size_t byteSize = 24; 4903 }; 4904 4905 //! 4906 //! \brief MFD_IT_OBJECT_VC1_INLINE_DATA 4907 //! \details 4908 //! The content in this command is similar to that in the MEDIA_OBJECT 4909 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4910 //! command corresponds to the processing of one macroblock. Macroblock 4911 //! parameters are passed in as inline data and the non-zero DCT coefficient 4912 //! data for the macroblock is passed in as indirect data. Inline data 4913 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4914 //! 4915 struct MFD_IT_OBJECT_VC1_INLINE_DATA_CMD 4916 { 4917 union 4918 { 4919 //!< DWORD 0 4920 struct 4921 { 4922 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 2); //!< Reserved 4923 uint32_t Lastmbinrow : __CODEGEN_BITFIELD(3, 3); //!< LastMBInRow 4924 uint32_t LastRowFlag : __CODEGEN_BITFIELD(4, 4); //!< Last Row Flag 4925 uint32_t ChromaIntraFlag : __CODEGEN_BITFIELD(5, 5); //!< Chroma Intra Flag 4926 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD(6, 11); //!< Coded Block Pattern 4927 uint32_t LumaIntra8X8Flag : __CODEGEN_BITFIELD(12, 15); //!< Luma Intra 8x8 Flag 4928 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16); //!< MACROBLOCK_INTRA_TYPE 4929 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17); //!< MACROBLOCK_MOTION_FORWARD 4930 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18); //!< MACROBLOCK_MOTION_BACKWARD 4931 uint32_t Motion4Mv : __CODEGEN_BITFIELD(19, 19); //!< MOTION4MV 4932 uint32_t Overlaptransform : __CODEGEN_BITFIELD(20, 20); //!< OVERLAPTRANSFORM 4933 uint32_t DctType : __CODEGEN_BITFIELD(21, 21); //!< DCT_TYPE 4934 uint32_t Mvswitch : __CODEGEN_BITFIELD(22, 22); //!< MvSwitch 4935 uint32_t Reserved23 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 4936 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25); //!< Motion Type 4937 uint32_t Mvfieldselectchroma : __CODEGEN_BITFIELD(26, 26); //!< MvFieldSelectChroma 4938 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 27); //!< Reserved 4939 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31); //!< MOTION_VERTICAL_FIELD_SELECT 4940 }; 4941 uint32_t Value; 4942 } DW0; 4943 union 4944 { 4945 //!< DWORD 1 4946 struct 4947 { 4948 uint32_t Horzorigin : __CODEGEN_BITFIELD(0, 7); //!< HorzOrigin 4949 uint32_t Vertorigin : __CODEGEN_BITFIELD(8, 15); //!< VertOrigin 4950 uint32_t Osedgemaskluma : __CODEGEN_BITFIELD(16, 23); //!< OSEdgeMaskLuma 4951 uint32_t Osedgemaskchroma : __CODEGEN_BITFIELD(24, 25); //!< OSEdgeMaskChroma 4952 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 4953 }; 4954 uint32_t Value; 4955 } DW1; 4956 union 4957 { 4958 //!< DWORD 2 4959 struct 4960 { 4961 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Forward, Horizontal Component 4962 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Forward, Vertical Component 4963 }; 4964 uint32_t Value; 4965 } DW2; 4966 union 4967 { 4968 //!< DWORD 3 4969 struct 4970 { 4971 uint32_t Motionvector1; //!< MotionVector1 4972 }; 4973 uint32_t Value; 4974 } DW3; 4975 union 4976 { 4977 //!< DWORD 4 4978 struct 4979 { 4980 uint32_t Motionvector2; //!< MotionVector2 4981 }; 4982 uint32_t Value; 4983 } DW4; 4984 union 4985 { 4986 //!< DWORD 5 4987 struct 4988 { 4989 uint32_t Motionvector3; //!< MotionVector3 4990 }; 4991 uint32_t Value; 4992 } DW5; 4993 union 4994 { 4995 //!< DWORD 6 4996 struct 4997 { 4998 uint32_t Motionvectorchroma; //!< MotionVectorChroma 4999 }; 5000 uint32_t Value; 5001 } DW6; 5002 union 5003 { 5004 //!< DWORD 7 5005 struct 5006 { 5007 uint32_t SubblockCodeForY0 : __CODEGEN_BITFIELD(0, 7); //!< Subblock Code for Y0 5008 uint32_t SubblockCodeForY1 : __CODEGEN_BITFIELD(8, 15); //!< Subblock Code for Y1 5009 uint32_t SubblockCodeForY2 : __CODEGEN_BITFIELD(16, 23); //!< Subblock Code for Y2 5010 uint32_t SubblockCodeForY3 : __CODEGEN_BITFIELD(24, 31); //!< Subblock Code for Y3 5011 }; 5012 uint32_t Value; 5013 } DW7; 5014 union 5015 { 5016 //!< DWORD 8 5017 struct 5018 { 5019 uint32_t SubblockCodeForCb : __CODEGEN_BITFIELD(0, 7); //!< Subblock Code for Cb 5020 uint32_t SubblockCodeForCr : __CODEGEN_BITFIELD(8, 15); //!< Subblock Code for Cr 5021 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 5022 }; 5023 uint32_t Value; 5024 } DW8; 5025 union 5026 { 5027 //!< DWORD 9 5028 struct 5029 { 5030 uint32_t IldbControlDataForBlockY0 : __CODEGEN_BITFIELD(0, 7); //!< ILDB control data for block Y0 5031 uint32_t IldbControlDataForBlockY1 : __CODEGEN_BITFIELD(8, 15); //!< ILDB control data for block Y1 5032 uint32_t IldbControlDataForBlockY2 : __CODEGEN_BITFIELD(16, 23); //!< ILDB control data for block Y2 5033 uint32_t IldbControlDataForBlockY3 : __CODEGEN_BITFIELD(24, 31); //!< ILDB control data for block Y3 5034 }; 5035 uint32_t Value; 5036 } DW9; 5037 union 5038 { 5039 //!< DWORD 10 5040 struct 5041 { 5042 uint32_t IldbControlDataForCbBlock : __CODEGEN_BITFIELD(0, 7); //!< ILDB control data for Cb block 5043 uint32_t IldbControlDataForCrBlock : __CODEGEN_BITFIELD(8, 15); //!< ILDB control data for Cr block 5044 uint32_t Reserved336 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 5045 }; 5046 uint32_t Value; 5047 } DW10; 5048 5049 //! \name Local enumerations 5050 5051 //! \brief MACROBLOCK_INTRA_TYPE 5052 //! \details 5053 //! This field specifies if the current macroblock is intra-coded. When set, 5054 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 5055 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 5056 enum MACROBLOCK_INTRA_TYPE 5057 { 5058 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 5059 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 5060 }; 5061 5062 //! \brief MACROBLOCK_MOTION_FORWARD 5063 //! \details 5064 //! This field specifies if the forward motion vector is active. See ISO/IEC 5065 //! 13818-2 Tables B-2 through B-4. 5066 enum MACROBLOCK_MOTION_FORWARD 5067 { 5068 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 5069 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTORS = 1, //!< No additional details 5070 }; 5071 5072 //! \brief MACROBLOCK_MOTION_BACKWARD 5073 //! \details 5074 //! This field specifies if the backward motion vector is active. See 5075 //! ISO/IEC 13818-2 Tables B-2 through B-4. 5076 enum MACROBLOCK_MOTION_BACKWARD 5077 { 5078 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 5079 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTORS = 1, //!< No additional details 5080 }; 5081 5082 enum MOTION4MV 5083 { 5084 MOTION4MV_1MV_MODE = 0, //!< No additional details 5085 MOTION4MV_4MV_MODE = 1, //!< No additional details 5086 }; 5087 5088 //! \brief OVERLAPTRANSFORM 5089 //! \details 5090 //! Was Overlap Transform - H261 Loop Filter 5091 enum OVERLAPTRANSFORM 5092 { 5093 OVERLAPTRANSFORM_NOOVERLAPSMOOTHINGFILTER = 0, //!< This field indicates whether overlap smoothing filter should be performed on I-block boundaries. 5094 OVERLAPTRANSFORM_OVERLAPSMOOTHINGFILTERPERFORMED = 1, //!< Macroblock is field DCT coded 5095 }; 5096 5097 //! \brief DCT_TYPE 5098 //! \details 5099 //! This field specifies the DCT type of the current macroblock. The kernel 5100 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 5101 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 5102 //! (no coded blocks present). 5103 enum DCT_TYPE 5104 { 5105 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 5106 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 5107 }; 5108 5109 //! \brief MOTION_VERTICAL_FIELD_SELECT 5110 //! \details 5111 //! A bit-wise representation of a long [2][2] array as defined in 5112 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also #167;7.6.4). 5113 //! <table> 5114 //! <thead> 5115 //! 5116 //! <tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 5117 //! Index</td></tr> 5118 //! </thead> 5119 //! <tbody> 5120 //! <tr><td>28</td><td>0</td><td>0</td><td>0</td></tr> 5121 //! <tr><td>29</td><td>0</td><td>1</td><td>1</td></tr> 5122 //! <tr><td>30</td><td>1</td><td>0</td><td>2</td></tr> 5123 //! <tr><td>31</td><td>1</td><td>1</td><td>3</td></tr> 5124 //! </tbody> 5125 //! </table> 5126 enum MOTION_VERTICAL_FIELD_SELECT 5127 { 5128 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field. 5129 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 5130 }; 5131 5132 //! \name Initializations 5133 5134 //! \brief Explicit member initialization function 5135 MFD_IT_OBJECT_VC1_INLINE_DATA_CMD(); 5136 5137 static const size_t dwSize = 11; 5138 static const size_t byteSize = 44; 5139 }; 5140 5141 //! 5142 //! \brief MFD_IT_OBJECT 5143 //! \details 5144 //! All weight mode (default and implicit) are mapped to explicit mode. But 5145 //! the weights come in either as explicit or implicit. 5146 //! 5147 struct MFD_IT_OBJECT_CMD 5148 { 5149 union 5150 { 5151 //!< DWORD 0 5152 struct 5153 { 5154 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5155 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5156 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5157 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5158 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5159 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5160 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5161 }; 5162 uint32_t Value; 5163 } DW0; 5164 union 5165 { 5166 //!< DWORD 1 5167 struct 5168 { 5169 uint32_t IndirectItMvDataLength : __CODEGEN_BITFIELD( 0, 9) ; //!< Indirect IT-MV Data Length 5170 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 5171 }; 5172 uint32_t Value; 5173 } DW1; 5174 union 5175 { 5176 //!< DWORD 2 5177 struct 5178 { 5179 uint32_t IndirectItMvDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-MV Data Start Address Offset 5180 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5181 }; 5182 uint32_t Value; 5183 } DW2; 5184 union 5185 { 5186 //!< DWORD 3 5187 struct 5188 { 5189 uint32_t IndirectItCoeffDataLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Indirect IT-COEFF Data Length 5190 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 5191 }; 5192 uint32_t Value; 5193 } DW3; 5194 union 5195 { 5196 //!< DWORD 4 5197 struct 5198 { 5199 uint32_t IndirectItCoeffDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-COEFF Data Start Address Offset 5200 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5201 }; 5202 uint32_t Value; 5203 } DW4; 5204 union 5205 { 5206 //!< DWORD 5 5207 struct 5208 { 5209 uint32_t IndirectItDblkControlDataLength : __CODEGEN_BITFIELD( 0, 5) ; //!< Indirect IT-DBLK Control Data Length 5210 uint32_t Reserved166 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 5211 }; 5212 uint32_t Value; 5213 } DW5; 5214 union 5215 { 5216 //!< DWORD 6 5217 struct 5218 { 5219 uint32_t IndirectItDblkControlDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-DBLK Control Data Start Address Offset 5220 uint32_t Reserved221 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5221 }; 5222 uint32_t Value; 5223 } DW6; 5224 5225 //! \name Local enumerations 5226 5227 enum SUBOPCODE_B 5228 { 5229 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 5230 }; 5231 5232 enum SUBOPCODE_A 5233 { 5234 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5235 }; 5236 5237 enum MEDIA_COMMAND_OPCODE 5238 { 5239 MEDIA_COMMAND_OPCODE_MFXCOMMONDEC = 0, //!< No additional details 5240 }; 5241 5242 enum PIPELINE 5243 { 5244 PIPELINE_MFDITOBJECT = 2, //!< No additional details 5245 }; 5246 5247 enum COMMAND_TYPE 5248 { 5249 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5250 }; 5251 5252 //! \name Initializations 5253 5254 //! \brief Explicit member initialization function 5255 MFD_IT_OBJECT_CMD(); 5256 5257 static const size_t dwSize = 7; 5258 static const size_t byteSize = 28; 5259 }; 5260 5261 //! 5262 //! \brief MFC_MPEG2_SLICEGROUP_STATE 5263 //! \details 5264 //! This is a slice group level command and can be issued multiple times 5265 //! within a picture that is comprised of multiple slice groups. The same 5266 //! command is used for AVC encoder (PAK mode) and decoder (VLD and IT 5267 //! modes). 5268 //! 5269 struct MFC_MPEG2_SLICEGROUP_STATE_CMD 5270 { 5271 union 5272 { 5273 //!< DWORD 0 5274 struct 5275 { 5276 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5277 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5278 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5279 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5280 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5281 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5282 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5283 }; 5284 uint32_t Value; 5285 } DW0; 5286 union 5287 { 5288 //!< DWORD 1 5289 struct 5290 { 5291 uint32_t Streamid10EncoderOnly : __CODEGEN_BITFIELD( 0, 1) ; //!< StreamID[1:0] (Encoder-only) 5292 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 5293 uint32_t Sliceid30EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< SliceID[3:0] (Encoder-only) 5294 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 5295 uint32_t Intrasliceflag : __CODEGEN_BITFIELD(12, 12) ; //!< IntraSliceFlag 5296 uint32_t Intraslice : __CODEGEN_BITFIELD(13, 13) ; //!< IntraSlice 5297 uint32_t Firstslicehdrdisabled : __CODEGEN_BITFIELD(14, 14) ; //!< FirstSliceHdrDisabled 5298 uint32_t TailpresentflagTailInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(15, 15) ; //!< TAILPRESENTFLAG__TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5299 uint32_t SlicedataPresentflagSlicedataInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(16, 16) ; //!< SLICEDATA_PRESENTFLAG__SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5300 uint32_t HeaderpresentflagHeaderInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(17, 17) ; //!< HEADERPRESENTFLAG__HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5301 uint32_t BitstreamoutputflagCompressedBitstreamOutputDisableFlagEncoderOnly : __CODEGEN_BITFIELD(18, 18) ; //!< BITSTREAMOUTPUTFLAG__COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5302 uint32_t Islastslicegrp : __CODEGEN_BITFIELD(19, 19) ; //!< IsLastSliceGrp 5303 uint32_t SkipconvdisabledMbTypeSkipConversionDisableEncoderOnly : __CODEGEN_BITFIELD(20, 20) ; //!< SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5304 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 5305 uint32_t RatectrlpanictypeRcPanicTypeEncoderOnly : __CODEGEN_BITFIELD(22, 22) ; //!< RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5306 uint32_t RatectrlpanicflagRcPanicEnableEncoderOnly : __CODEGEN_BITFIELD(23, 23) ; //!< RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5307 uint32_t MbratectrlparamRcStableToleranceEncoderOnly : __CODEGEN_BITFIELD(24, 27) ; //!< MbRateCtrlParam- RC Stable Tolerance (Encoder-only) 5308 uint32_t MbratectrlmodeRcTriggleModeEncoderOnly : __CODEGEN_BITFIELD(28, 29) ; //!< MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5309 uint32_t MbratectrlresetResetratecontrolcounterEncoderOnly : __CODEGEN_BITFIELD(30, 30) ; //!< MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5310 uint32_t MbratectrlflagRatecontrolcounterenableEncoderOnly : __CODEGEN_BITFIELD(31, 31) ; //!< MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5311 }; 5312 uint32_t Value; 5313 } DW1; 5314 union 5315 { 5316 //!< DWORD 2 5317 struct 5318 { 5319 uint32_t FirstmbxcntAlsoCurrstarthorzpos : __CODEGEN_BITFIELD( 0, 7) ; //!< FirstMbXcnt - also CurrStartHorzPos 5320 uint32_t FirstmbycntAlsoCurrstartvertpos : __CODEGEN_BITFIELD( 8, 15) ; //!< FirstMbYcnt - also CurrStartVertPos 5321 uint32_t NextsgmbxcntAlsoNextstarthorzpos : __CODEGEN_BITFIELD(16, 23) ; //!< NextSgMbXcnt - also NextStartHorzPos 5322 uint32_t NextsgmbycntAlsoNextstartvertpos : __CODEGEN_BITFIELD(24, 31) ; //!< NextSgMbYcnt - also NextStartVertPos 5323 }; 5324 uint32_t Value; 5325 } DW2; 5326 union 5327 { 5328 //!< DWORD 3 5329 struct 5330 { 5331 uint32_t Slicegroupqp : __CODEGEN_BITFIELD( 0, 5) ; //!< SliceGroupQp 5332 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5333 uint32_t Slicegroupskip : __CODEGEN_BITFIELD( 8, 8) ; //!< SliceGroupSkip 5334 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 5335 }; 5336 uint32_t Value; 5337 } DW3; 5338 union 5339 { 5340 //!< DWORD 4 5341 struct 5342 { 5343 uint32_t BitstreamoffsetIndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD( 0, 28) ; //!< BitstreamOffset - Indirect PAK-BSE Data Start Address (Write) 5344 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5345 }; 5346 uint32_t Value; 5347 } DW4; 5348 union 5349 { 5350 //!< DWORD 5 5351 struct 5352 { 5353 uint32_t GrowparamGrowInitEncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< GrowParam - Grow Init (Encoder-only) 5354 uint32_t GrowparamGrowResistanceEncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< GrowParam - Grow Resistance (Encoder-only) 5355 uint32_t ShrinkaramShrinkInitEncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< Shrinkaram - Shrink Init (Encoder-only) 5356 uint32_t ShrinkparamShrinkResistanceEncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< ShrinkParam - Shrink Resistance (Encoder-only) 5357 uint32_t MaxqpposmodifierMagnitudeOfQpMaxPositiveModifierEncoderOnly : __CODEGEN_BITFIELD(16, 23) ; //!< MaxQpPosModifier - Magnitude of QP Max Positive Modifier (Encoder-only) 5358 uint32_t MaxqpnegmodifierMagnitudeOfQpMaxNegativeModifierEncoderOnly : __CODEGEN_BITFIELD(24, 31) ; //!< MaxQpNegModifier - Magnitude of QP Max Negative Modifier (Encoder-only) 5359 }; 5360 uint32_t Value; 5361 } DW5; 5362 union 5363 { 5364 //!< DWORD 6 5365 struct 5366 { 5367 uint32_t CorrectpointsCorrect1EncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< CorrectPoints - Correct 1 (Encoder-only) 5368 uint32_t CorrectpointsCorrect2EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< CorrectPoints - Correct 2 (Encoder-only) 5369 uint32_t CorrectpointsCorrect3EncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< CorrectPoints - Correct 3 (Encoder-only) 5370 uint32_t CorrectpointsCorrect4EncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< CorrectPoints - Correct 4 (Encoder-only) 5371 uint32_t CorrectpointsCorrect5EncoderOnly : __CODEGEN_BITFIELD(16, 19) ; //!< CorrectPoints - Correct 5 (Encoder-only) 5372 uint32_t CorrectpointsCorrect6EncoderOnly : __CODEGEN_BITFIELD(20, 23) ; //!< CorrectPoints - Correct 6 (Encoder-only) 5373 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 5374 }; 5375 uint32_t Value; 5376 } DW6; 5377 union 5378 { 5379 //!< DWORD 7 5380 struct 5381 { 5382 uint32_t Cv0ClampValue0EncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 (Encoder-only) 5383 uint32_t Cv1ClampValue1EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 - Clamp Value 1 (Encoder-only) 5384 uint32_t Cv2ClampValue2EncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 - Clamp Value 2 (Encoder-only) 5385 uint32_t Cv3ClampValue3EncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 - Clamp Value 3 (Encoder-only) 5386 uint32_t Cv4ClampValue4EncoderOnly : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 - Clamp Value 4 (Encoder-only) 5387 uint32_t Cv5ClampValue5EncoderOnly : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 - Clamp Value 5 (Encoder-only) 5388 uint32_t Cv6ClampValue6EncoderOnly : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 - Clamp Value 6 (Encoder-only) 5389 uint32_t Cv7ClampValue7EncoderOnly : __CODEGEN_BITFIELD(28, 31) ; //!< CV7 - Clamp Value 7 (Encoder-only) 5390 }; 5391 uint32_t Value; 5392 } DW7; 5393 5394 //! \name Local enumerations 5395 5396 enum SUBOPCODE_B 5397 { 5398 SUBOPCODE_B_MEDIA = 3, //!< No additional details 5399 }; 5400 5401 enum SUBOPCODE_A 5402 { 5403 SUBOPCODE_A_MEDIA = 2, //!< No additional details 5404 }; 5405 5406 enum MEDIA_COMMAND_OPCODE 5407 { 5408 MEDIA_COMMAND_OPCODE_MPEG2 = 3, //!< No additional details 5409 }; 5410 5411 enum PIPELINE 5412 { 5413 PIPELINE_MFXMPEG2SLICEGROUPSTATE = 2, //!< No additional details 5414 }; 5415 5416 enum COMMAND_TYPE 5417 { 5418 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5419 }; 5420 5421 enum TAILPRESENTFLAG__TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5422 { 5423 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED0 = 0, //!< no tail insertion into the output bitstream buffer, after the current slice encoded bits 5424 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED1 = 1, //!< tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 5425 }; 5426 5427 enum SLICEDATA_PRESENTFLAG__SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5428 { 5429 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no Slice Data insertion into the output bitstream buffer 5430 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< Slice Data insertion into the output bitstream buffer is present. 5431 }; 5432 5433 enum HEADERPRESENTFLAG__HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5434 { 5435 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no header insertion into the output bitstream buffer, in front of the current slice encoded bits 5436 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 5437 }; 5438 5439 enum BITSTREAMOUTPUTFLAG__COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5440 { 5441 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_ENABLE = 0, //!< enable the writing of the output compressed bitstream 5442 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_DISABLE = 1, //!< disable the writing of the output compressed bitstream 5443 }; 5444 5445 //! \brief SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5446 //! \details 5447 //! This field is only valid for a P or B slice. It must be zero for other 5448 //! slice types. Rules are provided in Section 2.3.3.1.6 5449 enum SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5450 { 5451 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_ENABLE = 0, //!< Enable skip type conversion 5452 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_DISABLE = 1, //!< Disable skip type conversion 5453 }; 5454 5455 //! \brief RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5456 //! \details 5457 //! This field selects between two RC Panic methods. If it is set to 0, in 5458 //! panic mode, the macroblock QP is maxed out, setting to requested QP + 5459 //! QP_max_pos_mod. If it is set to 1, for an intra macroblock, AC CBPs are 5460 //! set to zero (note that DC CBPs are not modified). For inter macroblocks, 5461 //! AC and DC CBPs are forced to zero. 5462 enum RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5463 { 5464 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED0 = 0, //!< QP Panic 5465 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED1 = 1, //!< CBP Panic 5466 }; 5467 5468 //! \brief RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5469 //! \details 5470 //! If this field is set to 1, RC enters panic mode 5471 //! when sum_act > sum_max. RC Panic Type field controls what type 5472 //! of panic 5473 //! behavior is invoked. 5474 enum RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5475 { 5476 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5477 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5478 }; 5479 5480 enum MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5481 { 5482 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED0 = 0, //!< Always Rate Control, whereas RC becomes activeif sum_act > sum_target or sum_act < sum_target 5483 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED1 = 1, //!< Gentle Rate Control, whereas RC becomes activeif sum_act > upper_midpt or sum_act < lower_midpt 5484 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED2 = 2, //!< Loose Rate Control, whereas RC becomes activeif sum_act > sum_max or sum_act < sum_min 5485 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED3 = 3, //!< Reserved 5486 }; 5487 5488 //! \brief MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5489 //! \details 5490 //! To reset the bit allocation accumulation counter to 0 to restart the 5491 //! rate control. 5492 enum MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5493 { 5494 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_DISABLE = 0, //!< Not reset 5495 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_ENABLE = 1, //!< reset 5496 }; 5497 5498 //! \brief MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5499 //! \details 5500 //! To enable the accumulation of bit allocation for rate controlThis field 5501 //! enables hardware Rate Control logic. The rest of the RC control fields 5502 //! are only valid when this field is set to 1. Otherwise, hardware ignores 5503 //! these fields.Note: To reset MB level rate control (QRC), we need to set 5504 //! both bits MbRateCtrlFlag and MbRateCtrlReset to 1 in the new slice 5505 enum MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5506 { 5507 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5508 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5509 }; 5510 5511 //! \name Initializations 5512 5513 //! \brief Explicit member initialization function 5514 MFC_MPEG2_SLICEGROUP_STATE_CMD(); 5515 5516 static const size_t dwSize = 8; 5517 static const size_t byteSize = 32; 5518 }; 5519 5520 //! 5521 //! \brief MFX_VC1_PRED_PIPE_STATE 5522 //! \details 5523 //! This command is used to set the operating states of the MFD Engine 5524 //! beyond the BSD unit. It is used with both VC1 Long and Short 5525 //! format.Driver is responsible to take the intensity compensation enable 5526 //! signal, the LumScale and the LumShift provided from the VC1 5527 //! interface, and maintain a history of these values for reference 5528 //! pictures. Together with these three parameters specified for the current 5529 //! picture being decoded, driver will derive and supply the above sets of 5530 //! LumScaleX, LumShiftX and intensity compensation enable (single or 5531 //! double, forward or backward) signals. H/W is responsible to take these 5532 //! state values, and use them to build the lookup table (including the 5533 //! derivation of iScale and iShift) for remapping the reference frame 5534 //! pixels, as well as perfoming the actual pixel remapping 5535 //! calculations/process. 5536 //! 5537 struct MFX_VC1_PRED_PIPE_STATE_CMD 5538 { 5539 union 5540 { 5541 //!< DWORD 0 5542 struct 5543 { 5544 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5545 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5546 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5547 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5548 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5549 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5550 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5551 }; 5552 uint32_t Value; 5553 } DW0; 5554 union 5555 { 5556 //!< DWORD 1 5557 struct 5558 { 5559 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 5560 uint32_t ReferenceFrameBoundaryReplicationMode : __CODEGEN_BITFIELD( 4, 7) ; //!< Reference Frame Boundary Replication Mode 5561 uint32_t VinIntensitycompSingleBwden : __CODEGEN_BITFIELD( 8, 9) ; //!< vin_intensitycomp_Single_BWDen 5562 uint32_t VinIntensitycompSingleFwden : __CODEGEN_BITFIELD(10, 11) ; //!< vin_intensitycomp_Single_FWDen 5563 uint32_t VinIntensitycompDoubleBwden : __CODEGEN_BITFIELD(12, 13) ; //!< vin_intensitycomp_Double_BWDen 5564 uint32_t VinIntensitycompDoubleFwden : __CODEGEN_BITFIELD(14, 15) ; //!< vin_intensitycomp_Double_FWDen 5565 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 5566 }; 5567 uint32_t Value; 5568 } DW1; 5569 union 5570 { 5571 //!< DWORD 2 5572 struct 5573 { 5574 uint32_t Lumscale1SingleFwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - Single - FWD 5575 uint32_t Reserved70 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5576 uint32_t Lumscale2SingleFwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - single - FWD 5577 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5578 uint32_t Lumshift1SingleFwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - single - FWD 5579 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5580 uint32_t Lumshift2SingleFwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- single - FWD 5581 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5582 }; 5583 uint32_t Value; 5584 } DW2; 5585 union 5586 { 5587 //!< DWORD 3 5588 struct 5589 { 5590 uint32_t Lumscale1DoubleFwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - double - FWD 5591 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5592 uint32_t Lumscale2DoubleFwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - double - FWD 5593 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5594 uint32_t Lumshift1DoubleFwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - double -FWD 5595 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5596 uint32_t Lumshift2DoubleFwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- double - FWD 5597 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5598 }; 5599 uint32_t Value; 5600 } DW3; 5601 union 5602 { 5603 //!< DWORD 4 5604 struct 5605 { 5606 uint32_t Lumscale1SingleBwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - Single - BWD 5607 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5608 uint32_t Lumscale2SingleBwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - single - BWD 5609 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5610 uint32_t Lumshift1SingleBwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - single - BWD 5611 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5612 uint32_t Lumshift2SingleBwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- single - BWD 5613 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5614 }; 5615 uint32_t Value; 5616 } DW4; 5617 union 5618 { 5619 //!< DWORD 5 5620 struct 5621 { 5622 uint32_t Lumscale1DoubleBwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - double - BWD 5623 uint32_t Reserved166 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5624 uint32_t Lumscale2DoubleBwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - double - BWD 5625 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5626 uint32_t Lumshift1DoubleBwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - double -BWD 5627 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5628 uint32_t Lumshift2DoubleBwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- double - BWD 5629 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5630 }; 5631 uint32_t Value; 5632 } DW5; 5633 5634 //! \name Local enumerations 5635 5636 enum SUBOPCODE_B 5637 { 5638 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5639 }; 5640 5641 enum SUBOPCODE_A 5642 { 5643 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 5644 }; 5645 5646 enum MEDIA_COMMAND_OPCODE 5647 { 5648 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 5649 }; 5650 5651 enum PIPELINE 5652 { 5653 PIPELINE_MFXVC1PREDPIPESTATE = 2, //!< No additional details 5654 }; 5655 5656 enum COMMAND_TYPE 5657 { 5658 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5659 }; 5660 5661 //! \name Initializations 5662 5663 //! \brief Explicit member initialization function 5664 MFX_VC1_PRED_PIPE_STATE_CMD(); 5665 5666 static const size_t dwSize = 6; 5667 static const size_t byteSize = 24; 5668 }; 5669 5670 //! 5671 //! \brief MFD_VC1_LONG_PIC_STATE 5672 //! \details 5673 //! MFX_VC1_LONG PIC_STATE command encapsulates the decoding parameters that 5674 //! are read or derived from bitstream syntax elements above (inclusive) 5675 //! picture header layer. These parameters are static for a picture and when 5676 //! slice structure is present, these parameters are not changed from slice 5677 //! to slice of the same picture. Hence, this command is only issued at the 5678 //! beginning of processing a new picture and prior to the VC1_*_OBJECT 5679 //! command. The values set for these state variables are retained 5680 //! internally across slices.Only the parameters needed by hardware (BSD 5681 //! unit) to decode bit sequence for the macroblocks in a picture layer or a 5682 //! slice layer are presented in this command. Other parameters such as the 5683 //! ones used for inverse transform or motion compensation are provided in 5684 //! MFX_VC1_PRED_PIPE_STATE command.This Long interface format is intel 5685 //! proprietary interface. Driver will need to perform addition operations 5686 //! to generate all the fields in this command. 5687 //! 5688 struct MFD_VC1_LONG_PIC_STATE_CMD 5689 { 5690 union 5691 { 5692 //!< DWORD 0 5693 struct 5694 { 5695 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5696 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5697 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5698 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5699 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5700 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5701 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5702 }; 5703 uint32_t Value; 5704 } DW0; 5705 union 5706 { 5707 //!< DWORD 1 5708 struct 5709 { 5710 uint32_t Picturewidthinmbsminus1PictureWidthMinus1InMacroblocks : __CODEGEN_BITFIELD( 0, 7) ; //!< PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS 5711 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 5712 uint32_t Pictureheightinmbsminus1PictureHeightMinus1InMacroblocks : __CODEGEN_BITFIELD(16, 23) ; //!< PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_ 5713 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 5714 }; 5715 uint32_t Value; 5716 } DW1; 5717 union 5718 { 5719 //!< DWORD 2 5720 struct 5721 { 5722 uint32_t Vc1Profile : __CODEGEN_BITFIELD( 0, 0) ; //!< VC1_PROFILE 5723 uint32_t Reserved65 : __CODEGEN_BITFIELD( 1, 2) ; //!< Reserved 5724 uint32_t Secondfield : __CODEGEN_BITFIELD( 3, 3) ; //!< Secondfield 5725 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< OVERLAP_SMOOTHING_ENABLE_FLAG 5726 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< LOOPFILTER_ENABLE_FLAG 5727 uint32_t RangereductionEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RANGEREDUCTION_ENABLE 5728 uint32_t Rangereductionscale : __CODEGEN_BITFIELD( 7, 7) ; //!< RANGEREDUCTIONSCALE 5729 uint32_t MotionVectorMode : __CODEGEN_BITFIELD( 8, 11) ; //!< MOTION_VECTOR_MODE 5730 uint32_t Syncmarker : __CODEGEN_BITFIELD(12, 12) ; //!< SYNCMARKER 5731 uint32_t InterpolationRounderContro : __CODEGEN_BITFIELD(13, 13) ; //!< Interpolation Rounder Contro 5732 uint32_t Implicitquantizer : __CODEGEN_BITFIELD(14, 14) ; //!< ImplicitQuantizer 5733 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15) ; //!< DmvSurfaceValid 5734 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 5735 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31) ; //!< Bitplane Buffer Pitch Minus 1 5736 }; 5737 uint32_t Value; 5738 } DW2; 5739 union 5740 { 5741 //!< DWORD 3 5742 struct 5743 { 5744 uint32_t Bscalefactor : __CODEGEN_BITFIELD( 0, 7) ; //!< BScaleFactor 5745 uint32_t PquantPictureQuantizationValue : __CODEGEN_BITFIELD( 8, 12) ; //!< PQuant (Picture Quantization Value) 5746 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 5747 uint32_t AltpquantAlternativePictureQuantizationValue : __CODEGEN_BITFIELD(16, 20) ; //!< AltPQuant (Alternative Picture Quantization Value) 5748 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 5749 uint32_t FcmFrameCodingMode : __CODEGEN_BITFIELD(24, 25) ; //!< FCM_FRAME_CODING_MODE 5750 uint32_t PictypePictureType : __CODEGEN_BITFIELD(26, 28) ; //!< PicType (Picture Type) 5751 uint32_t Condover : __CODEGEN_BITFIELD(29, 30) ; //!< CONDOVER 5752 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 5753 }; 5754 uint32_t Value; 5755 } DW3; 5756 union 5757 { 5758 //!< DWORD 4 5759 struct 5760 { 5761 uint32_t Pquantuniform : __CODEGEN_BITFIELD( 0, 0) ; //!< PQUANTUNIFORM 5762 uint32_t Halfqp : __CODEGEN_BITFIELD( 1, 1) ; //!< HalfQP 5763 uint32_t AltpquantconfigAlternativePictureQuantizationConfiguration : __CODEGEN_BITFIELD( 2, 3) ; //!< ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5764 uint32_t AltpquantedgemaskAlternativePictureQuantizationEdgeMask : __CODEGEN_BITFIELD( 4, 7) ; //!< AltPQuantEdgeMask (Alternative Picture Quantization Edge Mask) 5765 uint32_t ExtendedmvrangeExtendedMotionVectorRangeFlag : __CODEGEN_BITFIELD( 8, 9) ; //!< EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5766 uint32_t ExtendeddmvrangeExtendedDifferentialMotionVectorRangeFlag : __CODEGEN_BITFIELD(10, 11) ; //!< EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5767 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5768 uint32_t FwdrefdistReferenceDistance : __CODEGEN_BITFIELD(16, 19) ; //!< FwdRefDist (Reference Distance) 5769 uint32_t BwdrefdistReferenceDistance : __CODEGEN_BITFIELD(20, 23) ; //!< BwdRefDist (Reference Distance) 5770 uint32_t NumrefNumberOfReferences : __CODEGEN_BITFIELD(24, 24) ; //!< NUMREF_NUMBER_OF_REFERENCES 5771 uint32_t ReffieldpicpolarityReferenceFieldPicturePolarity : __CODEGEN_BITFIELD(25, 25) ; //!< REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5772 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD(26, 26) ; //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5773 uint32_t FourmvswitchFourMotionVectorSwitch : __CODEGEN_BITFIELD(27, 27) ; //!< FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5774 uint32_t UnifiedmvmodeUnifiedMotionVectorMode : __CODEGEN_BITFIELD(28, 29) ; //!< UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5775 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5776 }; 5777 uint32_t Value; 5778 } DW4; 5779 union 5780 { 5781 //!< DWORD 5 5782 struct 5783 { 5784 uint32_t CbptabCodedBlockPatternTable : __CODEGEN_BITFIELD( 0, 2) ; //!< CbpTab (Coded Block Pattern Table) 5785 uint32_t TransdctabIntraTransformDcTable : __CODEGEN_BITFIELD( 3, 3) ; //!< TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5786 uint32_t TransacuvPictureLevelTransformChromaAcCodingSetIndexTransactable : __CODEGEN_BITFIELD( 4, 5) ; //!< TransAcUV (Picture-level Transform Chroma AC Coding Set Index, TRANSACTABLE) 5787 uint32_t TransacyPictureLevelTransformLumaAcCodingSetIndexTransactable2 : __CODEGEN_BITFIELD( 6, 7) ; //!< TransAcY (Picture-level Transform Luma AC Coding Set Index, TRANSACTABLE2 5788 uint32_t MbmodetabMacroblockModeTable : __CODEGEN_BITFIELD( 8, 10) ; //!< MbModeTab (Macroblock Mode Table) 5789 uint32_t TranstypembflagMacroblockTransformTypeFlag : __CODEGEN_BITFIELD(11, 11) ; //!< TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5790 uint32_t TranstypePictureLevelTransformType : __CODEGEN_BITFIELD(12, 13) ; //!< TransType (Picture-level Transform Type) 5791 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5792 uint32_t Twomvbptab2MvBlockPatternTable : __CODEGEN_BITFIELD(16, 17) ; //!< TwoMvBpTab (2MV Block Pattern Table) 5793 uint32_t Fourmvbptab4MvBlockPatternTable : __CODEGEN_BITFIELD(18, 19) ; //!< FourMvBpTab (4-MV Block Pattern Table) 5794 uint32_t MvtabMotionVectorTable : __CODEGEN_BITFIELD(20, 22) ; //!< MvTab (Motion Vector Table) 5795 uint32_t Reserved183 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 5796 uint32_t Fieldtxraw : __CODEGEN_BITFIELD(24, 24) ; //!< FIELDTXRAW 5797 uint32_t Acpredraw : __CODEGEN_BITFIELD(25, 25) ; //!< ACPREDRAW 5798 uint32_t Overflagsraw : __CODEGEN_BITFIELD(26, 26) ; //!< OVERFLAGSRAW 5799 uint32_t Directmbraw : __CODEGEN_BITFIELD(27, 27) ; //!< DIRECTMBRAW 5800 uint32_t Skipmbraw : __CODEGEN_BITFIELD(28, 28) ; //!< SKIPMBRAW 5801 uint32_t Mvtypembraw : __CODEGEN_BITFIELD(29, 29) ; //!< MVTYPEMBRAW 5802 uint32_t Forwardmbraw : __CODEGEN_BITFIELD(30, 30) ; //!< FORWARDMBRAW 5803 uint32_t BitplanepresentflagBitplaneBufferPresentFlag : __CODEGEN_BITFIELD(31, 31) ; //!< BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5804 }; 5805 uint32_t Value; 5806 } DW5; 5807 5808 //! \name Local enumerations 5809 5810 enum SUBOPCODE_B 5811 { 5812 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5813 }; 5814 5815 enum SUBOPCODE_A 5816 { 5817 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5818 }; 5819 5820 enum MEDIA_COMMAND_OPCODE 5821 { 5822 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 5823 }; 5824 5825 enum PIPELINE 5826 { 5827 PIPELINE_MFDVC1LONGPICSTATE = 2, //!< No additional details 5828 }; 5829 5830 enum COMMAND_TYPE 5831 { 5832 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5833 }; 5834 5835 //! \brief PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS 5836 //! \details 5837 //! This field indicates the width of the picture in unit of macroblocks. 5838 //! For example, for a 1920x1080 frame picture, PictureWidthInMBs equals 120 5839 //! (1920 divided by 16).This field is used in VLD and IT modes 5840 enum PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS 5841 { 5842 PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS_VALUE255 = 255, //!< No additional details 5843 }; 5844 5845 //! \brief PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_ 5846 //! \details 5847 //! This field indicates the height of the picture in unit of macroblocks. 5848 //! For example, for a 1920x1080 frame picture, PictureHeightInMBs equals 68 5849 //! (1080 divided by 16, and rounded up, i.e. effectively specified as 1088 5850 //! instead).This field is used in VLD and IT modes. 5851 enum PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_ 5852 { 5853 PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_VALUE255 = 255, //!< No additional details 5854 }; 5855 5856 //! \brief VC1_PROFILE 5857 //! \details 5858 //! specifies the bitstream profile.This field is used in both VLD and IT 5859 //! modes. 5860 enum VC1_PROFILE 5861 { 5862 VC1_PROFILE_DISABLE = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 5863 VC1_PROFILE_ENABLE = 1, //!< current picture is in Advanced Profile 5864 }; 5865 5866 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 5867 //! \details 5868 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 5869 //! if Overlap smoothing is ON at the picture levelThis field is used in 5870 //! both VLD and IT modes. 5871 enum OVERLAP_SMOOTHING_ENABLE_FLAG 5872 { 5873 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 5874 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 5875 }; 5876 5877 //! \brief LOOPFILTER_ENABLE_FLAG 5878 //! \details 5879 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 5880 //! indicates if In-loop Deblocking is ON according to picture level 5881 //! bitstream syntax control. This bit affects BSD unit and also the loop 5882 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 5883 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 5884 //! in-loop deblocking operation follows the VC1 standard - deblocking 5885 //! doesn't cross slice boundary.When this bit is set to 0, but 5886 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 5887 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 5888 //! this case, deblocking operation does cross slice boundary.This field is 5889 //! used in VLD mode only, not in IT mode. 5890 enum LOOPFILTER_ENABLE_FLAG 5891 { 5892 LOOPFILTER_ENABLE_FLAG_DISABLE = 0, //!< Disables loop filter 5893 LOOPFILTER_ENABLE_FLAG_ENABLE = 1, //!< Enables loop filter 5894 }; 5895 5896 //! \brief RANGEREDUCTION_ENABLE 5897 //! \details 5898 //! This field specifies whether on-the-fly pixel value range reduction 5899 //! should be performed for the preceding (or forward) reference picture. 5900 //! Along with RangeReductionScale to specify whether scale up or down 5901 //! should be performed. It is not the same value as RANGEREDFRM Syntax 5902 //! Element (_PictureParameters bPicDeblocked bit 5) in the Picture 5903 //! Header. 5904 enum RANGEREDUCTION_ENABLE 5905 { 5906 RANGEREDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 5907 RANGEREDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 5908 }; 5909 5910 //! \brief RANGEREDUCTIONSCALE 5911 //! \details 5912 //! This field specifies whether the reference picture pixel values should 5913 //! be scaled up or scaled down on-the-fly, if RangeReduction is Enabled. 5914 enum RANGEREDUCTIONSCALE 5915 { 5916 RANGEREDUCTIONSCALE_UNNAMED0 = 0, //!< Scale down reference picture by factor of 2 5917 RANGEREDUCTIONSCALE_UNNAMED1 = 1, //!< Scale up reference picture by factor of 2 5918 }; 5919 5920 //! \brief MOTION_VECTOR_MODE 5921 //! \details 5922 //! This field indicates one of the following motion compensation 5923 //! interpolation modes for P and B pictures. The MC interpolation modes 5924 //! apply to prediction values of luminance blocks and are always in 5925 //! quarter-sample. For chrominance blocks, it always performs bilinear 5926 //! interpolation with either half-pel or quarter-pel precision.Before the 5927 //! polarity of Chroma Half-pel or Q-pel is reversed from Spec, now I 5928 //! have fixed it to match with VC1 Spec. 5929 enum MOTION_VECTOR_MODE 5930 { 5931 MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Chroma Quarter -pel + Luma bicubic. (can only be 1MV) 5932 MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< Chroma Half-pel + Luma bicubic. (can be 1MV or 4MV) 5933 MOTION_VECTOR_MODE_UNNAMED8 = 8, //!< Chroma Quarter -pel + Luma bilinear. (can only be 1MV) 5934 MOTION_VECTOR_MODE_UNNAMED9 = 9, //!< Chroma Half-pel + Luma bilinear 5935 }; 5936 5937 //! \brief SYNCMARKER 5938 //! \details 5939 //! Indicates whether sync markers are enabled/disabled. If enable, sync 5940 //! markers "may be" present in the current video sequence being decoded. It 5941 //! is a sequence level syntax element and is valid only for Simple and Main 5942 //! Profiles. 5943 enum SYNCMARKER 5944 { 5945 SYNCMARKER_NOTPRESENT = 0, //!< Sync Marker is not present in the bitstream 5946 SYNCMARKER_MAYBEPRESENT = 1, //!< Sync Marker maybe present in the bitstream 5947 }; 5948 5949 //! \brief FCM_FRAME_CODING_MODE 5950 //! \details 5951 //! This is the same as the variable FCM defined in VC1.This field must be 5952 //! set to 0 for Simple and Main ProfilesThis field is unique to intel VC1 5953 //! VLD Long format, and is used in IT mode as well. For VC1 IT mode, 5954 //! driver needs to convert the interface to intel HW VLD Long Format 5955 //! interface. 5956 enum FCM_FRAME_CODING_MODE 5957 { 5958 FCM_FRAME_CODING_MODE_DISABLE = 0, //!< Progressive Frame Picture 5959 FCM_FRAME_CODING_MODE_ENABLE = 1, //!< Interlaced Frame Picture 5960 FCM_FRAME_CODING_MODE_UNNAMED2 = 2, //!< Field Picture with Top Field First 5961 FCM_FRAME_CODING_MODE_UNNAMED3 = 3, //!< Field Picture with Bottom Field First 5962 }; 5963 5964 //! \brief CONDOVER 5965 //! \details 5966 //! This field is the decoded syntax element CONDOVER in a bitstream of 5967 //! advanced profile. It controls the overlap smoothing filter operation for 5968 //! an I frame or an BI frame when the picture level qualization step size 5969 //! PQUANT is 8 or lower.This field is used in intel VC1 VLD mode only, not 5970 //! in VC1 and IT modes. 5971 enum CONDOVER 5972 { 5973 CONDOVER_UNNAMED0 = 0, //!< No overlap smoothing 5974 CONDOVER_UNNAMED1 = 1, //!< Reserved 5975 CONDOVER_UNNAMED2 = 2, //!< Always perform overlap smoothing filter 5976 CONDOVER_UNNAMED3 = 3, //!< Overlap smoothing on a per macroblock basis based on OVERFLAGS 5977 }; 5978 5979 //! \brief PQUANTUNIFORM 5980 //! \details 5981 //! Indicating if uniform quantization applies to the 5982 //! picture. It is used for inverse quantization of the AC 5983 //! coefficients.QUANTIZER 5984 //! 001123PQUANTIZER - 5985 //! -01--PQINDEX>=9<=8----PQuantUniform010201ImplicitQuantizer = 5986 //! 0, and 5987 //! PQuantUniform = 0 is used to represent 2 cases : 1) QUANTIZER=01 5988 //! and 5989 //! PQUANTIZER=0; and 2) QUANTIZER = 10b.ImplicitQuantizer = 0, and 5990 //! PQuantUniform = 5991 //! 1 is used to represent 2 cases : 1) QUANTIZER=01 and PQUANTIZER=1; 5992 //! and 2) 5993 //! QUANTIZER = 11bThis field is unique to intel VC1 VLD Long format 5994 //! mode, and is 5995 //! not used in IT and VC1 modes. 5996 enum PQUANTUNIFORM 5997 { 5998 PQUANTUNIFORM_UNNAMED0 = 0, //!< Non-uniform 5999 PQUANTUNIFORM_UNNAMED1 = 1, //!< Uniform 6000 }; 6001 6002 //! \brief ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 6003 //! \details 6004 //! This field specifies the way AltPQuant is used in the picture. It 6005 //! determines how to compute the macroblock quantizer step size, MQUANT. It 6006 //! is derived based on the following variables DQUANT, DQUANTFRM, 6007 //! DQPROFILE, DQSBEDGE, DQDBEDGE, and DQBILEVEL defined in the VC1 6008 //! standard, as shown in Error! Reference source not found..This field is 6009 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 6010 //! VC1 modes. 6011 enum ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 6012 { 6013 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED0 = 0, //!< AltPQuant not used 6014 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED1 = 1, //!< AltPQuant is used and applied to edge macroblocks only 6015 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED2 = 2, //!< MQUANT is encoded in macroblock layer 6016 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED3 = 3, //!< AltPQuant and PQuant are selected on macroblock basis 6017 }; 6018 6019 //! \brief EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 6020 //! \details 6021 //! This field specifies the motion vector range in quarter-pel or half-pel 6022 //! modes. It is equivalent to the variable MVRANGE in the VC1 standard. 6023 //! This field is unique to intel VC1 VLD Long format mode, and is not used 6024 //! in IT and VC1 modes 6025 enum EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 6026 { 6027 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< [-256, 255] x [-128, 127] 6028 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< 512, 511] x [-256, 255] 6029 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< [-2048, 2047] x [-1024, 1023] 6030 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< [-4096, 4095] x [-2048, 2047] 6031 }; 6032 6033 //! \brief EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 6034 //! \details 6035 //! This field specifies the differential motion vector range in interlaced 6036 //! pictures. It is equivalent to the variable DMVRANGE in the VC1 standard. 6037 //! This field is unique to intel VC1 VLD Long format mode, and is not used 6038 //! in IT and VC1 modes. 6039 enum EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 6040 { 6041 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< No extended range 6042 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< Extended horizontally 6043 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< Extended vertically 6044 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< Extended in both directions 6045 }; 6046 6047 //! \brief NUMREF_NUMBER_OF_REFERENCES 6048 //! \details 6049 //! This field indicates how many reference fields are referenced by the 6050 //! current (field) picture. It is identical to the variable NUMREF in the 6051 //! VC1 standard. This field is only valid for field P picture (FCM = 10 | 6052 //! 11).This field is unique to intel VC1 VLD Long format mode, and is not 6053 //! used in IT and VC1 modes. 6054 enum NUMREF_NUMBER_OF_REFERENCES 6055 { 6056 NUMREF_NUMBER_OF_REFERENCES_UNNAMED0 = 0, //!< One field referenced 6057 NUMREF_NUMBER_OF_REFERENCES_UNNAMED1 = 1, //!< Two fields referenced 6058 }; 6059 6060 //! \brief REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 6061 //! \details 6062 //! This field specifies the polarity of the one reference field picture 6063 //! used for a field P picture. It is derived from the variable REFFIELD 6064 //! defined in VC1 standard and is only valid when one field is referenced 6065 //! (NUMREF = 0) for a field P picture.When NUMREF = 0 and REFFIELD = 0, 6066 //! this field is the polarity of the reference I/P field that is temporally 6067 //! closest; When NUMREF = 0 and REFFIELD = 1, this field is the polarity of 6068 //! the reference I/P field that is the second most temporally closest. The 6069 //! distance is measured based on display order but ignoring the repeated 6070 //! field if present (due to RFF = 1).This field is unique to intel VC1 VLD 6071 //! Long format mode, and is not used in IT and VC1 modes. 6072 enum REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 6073 { 6074 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED0 = 0, //!< Top (even) field 6075 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED1 = 1, //!< Bottom (odd) field 6076 }; 6077 6078 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6079 //! \details 6080 //! This field specifies whether the motion vectors for 6081 //! UV is rounded to half or full pel position. It is identical to the 6082 //! variable 6083 //! FASTUVMC in VC1 standard.This field is used in both VLD and IT 6084 //! modes.It is 6085 //! derived from FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in 6086 //! both VLD and 6087 //! IT modes, and should have the same value as Motion Vector Mode 6088 //! LSBit. 6089 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6090 { 6091 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 6092 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 6093 }; 6094 6095 //! \brief FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 6096 //! \details 6097 //! This field indicates if 4-MV is present for an interlaced frame P 6098 //! picture. It is identical to the variable 4MVSWITCH (4 Motion Vector 6099 //! Switch) in VC1 standard.This field is used in intel VC1 VLD Long Format 6100 //! mode only, it is not used in VC1 VLD and IT modes. 6101 enum FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 6102 { 6103 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_DISABLE = 0, //!< only 1-MV 6104 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_ENABLE = 1, //!< 1, 2, or 4 motion vectors 6105 }; 6106 6107 //! \brief UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 6108 //! \details 6109 //! This field is a combination of the variables MVMODE and MVMODE2 in the 6110 //! VC1 standard, for parsing Luma MVD from the bitstream. This field is 6111 //! used to signal 1MV vs 4MVallowed (Mixed Mode). This field is also used 6112 //! to signal Q-pel or Half-pel MVD read from the bitstream. The bicubic or 6113 //! bilinear Luma MC interpolation mode is duplicate information from Motion 6114 //! Vector Mode field, and is ignored here.This field is used in intel VC1 6115 //! VLD Long Format mode only, it is not used in VC1 VLD and IT modes. 6116 enum UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 6117 { 6118 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Mixed MV, Q-pel bicubic 6119 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< 1-MV, Q-pel bicubic 6120 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED2 = 2, //!< 1-MV half-pel bicubic 6121 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED3 = 3, //!< 1-MV half-pel bilinear 6122 }; 6123 6124 //! \brief TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 6125 //! \details 6126 //! This field specifies whether the low motion tables or the high motion 6127 //! tables are used to decode the Transform DC coefficients in intra-coded 6128 //! blocks. This field is identical to the variable TRANSDCTAB in the VC1 6129 //! standard, section 8.1.1.2.This field is valid for all picture types.This 6130 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6131 //! and VC1 modes. 6132 enum TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 6133 { 6134 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED0 = 0, //!< The high motion tables 6135 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED1 = 1, //!< The low motion tables 6136 }; 6137 6138 //! \brief TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 6139 //! \details 6140 //! This field indicates whether Transform Type is fixed at picture level or 6141 //! variable at macroblock level. It is identical to the variable TTMBF in 6142 //! the VC1 standard, section 7.1.1.40.This field is set to 1 when 6143 //! VSTRANSFORM is 0 in the entry point layer.This field is unique to intel 6144 //! VC1 VLD Long format mode, and is not used in IT and VC1 modes. 6145 enum TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 6146 { 6147 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED0 = 0, //!< variable transform type in macroblock layer 6148 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED1 = 1, //!< use picture level transform type TransType 6149 }; 6150 6151 //! \brief FIELDTXRAW 6152 //! \details 6153 //! This field indicates whether the FIELDTX field is coded in raw or 6154 //! non-raw mode.This field is only valid when PictureType is I or BI.This 6155 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6156 //! and VC1 modes. 6157 enum FIELDTXRAW 6158 { 6159 FIELDTXRAW_DISABLE = 0, //!< Non-Raw Mode 6160 FIELDTXRAW_ENABLE = 1, //!< Raw Mode 6161 }; 6162 6163 //! \brief ACPREDRAW 6164 //! \details 6165 //! This field indicates whether the ACPRED field is coded in raw or non-raw 6166 //! mode.This field is only valid when PictureType is I or BI.This field is 6167 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 6168 //! VC1 modes. 6169 enum ACPREDRAW 6170 { 6171 ACPREDRAW_DISABLE = 0, //!< Non-Raw Mode 6172 ACPREDRAW_ENABLE = 1, //!< Raw Mode 6173 }; 6174 6175 //! \brief OVERFLAGSRAW 6176 //! \details 6177 //! This field indicates whether the OVERFLAGS field is coded in raw or 6178 //! non-raw mode.This field is only valid when PictureType is I or BI.This 6179 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6180 //! and VC1 modes. 6181 enum OVERFLAGSRAW 6182 { 6183 OVERFLAGSRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6184 OVERFLAGSRAW_UNNAMED1 = 1, //!< Raw Mode 6185 }; 6186 6187 //! \brief DIRECTMBRAW 6188 //! \details 6189 //! This field indicates whether the DIRECTMB field is coded in raw or 6190 //! non-raw mode.This field is only valid when PictureType is P or B.This 6191 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6192 //! and VC1 modes. 6193 enum DIRECTMBRAW 6194 { 6195 DIRECTMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6196 DIRECTMBRAW_UNNAMED1 = 1, //!< Raw Mode 6197 }; 6198 6199 //! \brief SKIPMBRAW 6200 //! \details 6201 //! This field indicates whether the SKIPMB field is coded in raw or non-raw 6202 //! mode.This field is only valid when PictureType is P or B.0 = non-raw 6203 //! mode1 = raw modeThis field is unique to intel VC1 VLD Long format mode, 6204 //! and is not used in IT and VC1 modes. 6205 enum SKIPMBRAW 6206 { 6207 SKIPMBRAW_DISABLE = 0, //!< Non-Raw Mode 6208 SKIPMBRAW_ENABLE = 1, //!< Raw Mode 6209 }; 6210 6211 //! \brief MVTYPEMBRAW 6212 //! \details 6213 //! This field indicates whether the MVTYPREMB field is coded in raw or 6214 //! non-raw mode.This field is only valid when PictureType is P.This field 6215 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 6216 //! VC1 modes. 6217 enum MVTYPEMBRAW 6218 { 6219 MVTYPEMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6220 MVTYPEMBRAW_UNNAMED1 = 1, //!< Raw Mode 6221 }; 6222 6223 //! \brief FORWARDMBRAW 6224 //! \details 6225 //! This field indicates whether the FORWARDMB field is coded in raw or 6226 //! non-raw mode.This field is only valid when PictureType is B.This field 6227 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 6228 //! VC1 modes. 6229 enum FORWARDMBRAW 6230 { 6231 FORWARDMBRAW_UNNAMED0 = 0, //!< non-raw mode 6232 FORWARDMBRAW_UNNAMED1 = 1, //!< raw mode 6233 }; 6234 6235 //! \brief BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 6236 //! \details 6237 //! This field indicates whether the bitplane buffer is present for the 6238 //! picture. If set, at least one of the fields listed in bits 22:16 is 6239 //! coded in non-raw mode, and Bitplane Buffer Base Address field in the 6240 //! VC1_BSD_BUF_BASE_STATE command points to the bitplane buffer. Otherwise, 6241 //! all the fields that are applicable for the current picture in bits 22:16 6242 //! must be coded in raw mode.This field is unique to intel VC1 VLD Long 6243 //! format mode, and is not used in IT and VC1 modes. 6244 enum BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 6245 { 6246 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED0 = 0, //!< bitplane buffer is not present 6247 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED1 = 1, //!< bitplane buffer is present 6248 }; 6249 6250 //! \name Initializations 6251 6252 //! \brief Explicit member initialization function 6253 MFD_VC1_LONG_PIC_STATE_CMD(); 6254 6255 static const size_t dwSize = 6; 6256 static const size_t byteSize = 24; 6257 }; 6258 6259 //! 6260 //! \brief MFD_VC1_SHORT_PIC_STATE 6261 //! \details 6262 //! 6263 //! 6264 struct MFD_VC1_SHORT_PIC_STATE_CMD 6265 { 6266 union 6267 { 6268 //!< DWORD 0 6269 struct 6270 { 6271 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6272 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6273 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6274 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6275 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6276 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6277 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6278 }; 6279 uint32_t Value; 6280 } DW0; 6281 union 6282 { 6283 //!< DWORD 1 6284 struct 6285 { 6286 uint32_t PictureWidth : __CODEGEN_BITFIELD( 0, 7) ; //!< Picture Width 6287 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 6288 uint32_t PictureHeight : __CODEGEN_BITFIELD(16, 23) ; //!< Picture Height 6289 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6290 }; 6291 uint32_t Value; 6292 } DW1; 6293 union 6294 { 6295 //!< DWORD 2 6296 struct 6297 { 6298 uint32_t PictureStructure : __CODEGEN_BITFIELD( 0, 1) ; //!< PICTURE_STRUCTURE 6299 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 6300 uint32_t Secondfield : __CODEGEN_BITFIELD( 3, 3) ; //!< SecondField 6301 uint32_t IntraPictureFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< INTRA_PICTURE_FLAG 6302 uint32_t BackwardPredictionPresentFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< Backward Prediction Present Flag 6303 uint32_t Reserved70 : __CODEGEN_BITFIELD( 6, 10) ; //!< Reserved 6304 uint32_t Vc1Profile : __CODEGEN_BITFIELD(11, 11) ; //!< VC1_PROFILE 6305 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 14) ; //!< Reserved 6306 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15) ; //!< DmvSurfaceValid 6307 uint32_t MotionVectorMode : __CODEGEN_BITFIELD(16, 19) ; //!< Motion Vector Mode 6308 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 6309 uint32_t InterpolationRounderControl : __CODEGEN_BITFIELD(23, 23) ; //!< Interpolation Rounder Control 6310 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31) ; //!< Bitplane Buffer Pitch Minus 1 6311 }; 6312 uint32_t Value; 6313 } DW2; 6314 union 6315 { 6316 //!< DWORD 3 6317 struct 6318 { 6319 uint32_t VstransformFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSTRANSFORM_FLAG 6320 uint32_t Dquant : __CODEGEN_BITFIELD( 1, 2) ; //!< DQUANT 6321 uint32_t ExtendedMvPresentFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< EXTENDED_MV_PRESENT_FLAG 6322 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6323 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< LOOPFILTER_ENABLE_FLAG 6324 uint32_t RefdistFlag : __CODEGEN_BITFIELD( 6, 6) ; //!< REFDIST_FLAG 6325 uint32_t PanscanPresentFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< PANSCAN_PRESENT_FLAG 6326 uint32_t Maxbframes : __CODEGEN_BITFIELD( 8, 10) ; //!< MAXBFRAMES 6327 uint32_t RangeredPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(11, 11) ; //!< RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6328 uint32_t SyncmarkerPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(12, 12) ; //!< SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6329 uint32_t MultiresPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(13, 13) ; //!< MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6330 uint32_t Quantizer : __CODEGEN_BITFIELD(14, 15) ; //!< QUANTIZER 6331 uint32_t PPicRefDistance : __CODEGEN_BITFIELD(16, 20) ; //!< P_PIC_REF_DISTANCE 6332 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 6333 uint32_t ProgressivePicType : __CODEGEN_BITFIELD(22, 23) ; //!< PROGRESSIVE_PIC_TYPE 6334 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 27) ; //!< Reserved 6335 uint32_t RangeReductionEnable : __CODEGEN_BITFIELD(28, 28) ; //!< RANGE_REDUCTION_ENABLE 6336 uint32_t RangeReductionScale : __CODEGEN_BITFIELD(29, 29) ; //!< RANGE_REDUCTION_SCALE 6337 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD(30, 30) ; //!< OVERLAP_SMOOTHING_ENABLE_FLAG 6338 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 6339 }; 6340 uint32_t Value; 6341 } DW3; 6342 union 6343 { 6344 //!< DWORD 4 6345 struct 6346 { 6347 uint32_t ExtendedDmvPresentFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< EXTENDED_DMV_PRESENT_FLAG 6348 uint32_t Psf : __CODEGEN_BITFIELD( 1, 1) ; //!< PSF 6349 uint32_t RefpicFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< REFPIC_FLAG 6350 uint32_t Finterflag : __CODEGEN_BITFIELD( 3, 3) ; //!< FINTERFLAG 6351 uint32_t Tfcntrflag : __CODEGEN_BITFIELD( 4, 4) ; //!< TFCNTRFLAG 6352 uint32_t Interlace : __CODEGEN_BITFIELD( 5, 5) ; //!< INTERLACE 6353 uint32_t Pulldown : __CODEGEN_BITFIELD( 6, 6) ; //!< PULLDOWN 6354 uint32_t PostprocFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< POSTPROC Flag 6355 uint32_t _4MvAllowedFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< _4MV Allowed Flag 6356 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 23) ; //!< Reserved 6357 uint32_t BfractionEnumeration : __CODEGEN_BITFIELD(24, 28) ; //!< BFraction Enumeration 6358 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 6359 }; 6360 uint32_t Value; 6361 } DW4; 6362 6363 //! \name Local enumerations 6364 6365 enum SUBOPCODE_B 6366 { 6367 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 6368 }; 6369 6370 enum SUBOPCODE_A 6371 { 6372 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6373 }; 6374 6375 enum MEDIA_COMMAND_OPCODE 6376 { 6377 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6378 }; 6379 6380 enum PIPELINE 6381 { 6382 PIPELINE_MFDVC1SHORTPICSTATE = 2, //!< No additional details 6383 }; 6384 6385 enum COMMAND_TYPE 6386 { 6387 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6388 }; 6389 6390 //! \brief PICTURE_STRUCTURE 6391 //! \details 6392 //! This field is used in both VC1 VLD mode and IT mode. It is the 6393 //! same parameter as bPicStructure in VC1 spec. 6394 //! The Picture Structure and Progressive Pic Type are used to derive 6395 //! the picture structure as specified in FCM, in VC1 VLD and IT mode. 6396 enum PICTURE_STRUCTURE 6397 { 6398 PICTURE_STRUCTURE_UNNAMED0 = 0, //!< illegal 6399 PICTURE_STRUCTURE_UNNAMED1 = 1, //!< top field (bit 0) 6400 PICTURE_STRUCTURE_UNNAMED2 = 2, //!< bottom field (bit 1) 6401 PICTURE_STRUCTURE_UNNAMED3 = 3, //!< frame (both fields are present) 6402 }; 6403 6404 //! \brief INTRA_PICTURE_FLAG 6405 //! \details 6406 //! This field is used in both VC1 VLD mode and IT mode. It is the 6407 //! same parameter as bPicIntra in VC1 spec. 6408 //! The Intra Picture Flag, Backward Prediction Present Flag and 6409 //! RefPicFlag are used to derive the picture type, as specified in PTYPE 6410 //! for a frame, and in FPTYPE for a field, in VC1 VLD and IT mode. 6411 enum INTRA_PICTURE_FLAG 6412 { 6413 INTRA_PICTURE_FLAG_UNNAMED0 = 0, //!< entire picture can have a mixture of intra and inter MB type or just inter MB type. 6414 INTRA_PICTURE_FLAG_UNNAMED1 = 1, //!< entire picture is coded in intra MB type 6415 }; 6416 6417 //! \brief VC1_PROFILE 6418 //! \details 6419 //! specifies the bitstream profile. 6420 //! Note: This is required because 128 is added for intra blocks post 6421 //! inverse transform in advanced profile and also to find out if Motion 6422 //! vectors are adjusted or not. 6423 //! This field is used in both VLD and IT modes. 6424 enum VC1_PROFILE 6425 { 6426 VC1_PROFILE_UNNAMED0 = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 6427 VC1_PROFILE_UNNAMED1 = 1, //!< current picture is in Advanced Profile 6428 }; 6429 6430 enum VSTRANSFORM_FLAG 6431 { 6432 VSTRANSFORM_FLAG_DISABLE = 0, //!< variable-sized transform coding is not enabled 6433 VSTRANSFORM_FLAG_ENABLE = 1, //!< variable-sized transform coding is enabled 6434 }; 6435 6436 //! \brief DQUANT 6437 //! \details 6438 //! Use for Picture Header Parsing of VOPDUANT elements 6439 enum DQUANT 6440 { 6441 DQUANT_UNNAMED0 = 0, //!< no VOPDQUANT elements; Quantizer cannot vary in frame, same quantization step size PQUANT is used for all MBs in the frame 6442 DQUANT_UNNAMED1 = 1, //!< refer to VC1 Spec. for all the MB position dependent quantizer selection 6443 DQUANT_UNNAMED2 = 2, //!< The macroblocks located on the picture edge boundary shall be quantized with ALTPQUANT while the rest of the macroblocks shall be quantized with PQUANT. 6444 }; 6445 6446 //! \brief EXTENDED_MV_PRESENT_FLAG 6447 //! \details 6448 //! BitFieldDesc 6449 enum EXTENDED_MV_PRESENT_FLAG 6450 { 6451 EXTENDED_MV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_MV is not present in the picture header 6452 EXTENDED_MV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_MV is present in the picture header 6453 }; 6454 6455 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6456 //! \details 6457 //! This field specifies whether the motion vectors for 6458 //! UV is rounded to half or full pel position. It is identical to the 6459 //! variable 6460 //! FASTUVMC in VC1 standard.This field is used in both VLD and IT 6461 //! modes.It is 6462 //! derived from FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in 6463 //! both VLD and 6464 //! IT modes, and should have the same value as Motion Vector Mode 6465 //! LSBit. 6466 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6467 { 6468 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 6469 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 6470 }; 6471 6472 //! \brief LOOPFILTER_ENABLE_FLAG 6473 //! \details 6474 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 6475 //! indicates if In-loop Deblocking is ON according to picture level 6476 //! bitstream syntax control. This bit affects BSD unit and also the loop 6477 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 6478 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 6479 //! in-loop deblocking operation follows the VC1 standard - deblocking 6480 //! doesn't cross slice boundary.When this bit is set to 0, but 6481 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 6482 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 6483 //! this case, deblocking operation does cross slice boundary.This field is 6484 //! used in VLD mode only, not in IT mode. 6485 enum LOOPFILTER_ENABLE_FLAG 6486 { 6487 LOOPFILTER_ENABLE_FLAG_UNNAMED0 = 0, //!< In-Loop-Deblocking-Filter is disabled 6488 LOOPFILTER_ENABLE_FLAG_UNNAMED1 = 1, //!< In-Loop-Deblocking-Filter is enabled 6489 }; 6490 6491 enum PANSCAN_PRESENT_FLAG 6492 { 6493 PANSCAN_PRESENT_FLAG_UNNAMED0 = 0, //!< Pan Scan Parameters are not present in the picture header 6494 PANSCAN_PRESENT_FLAG_UNNAMED1 = 1, //!< Pan Scan Parameters are present in the picture header 6495 }; 6496 6497 //! \brief RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6498 //! \details 6499 //! It is needed for Picture Header Parsing.Driver is responsible to keep 6500 //! RangeReductionScale, RangeReduction Enable and RANGERED Present Flag of 6501 //! current picture coherent. 6502 enum RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6503 { 6504 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Range Reduction Parameter (RANGEREDFRM) is not present in the picture header 6505 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Range Reduction Parameter (RANGEREDFRM) is present in the picture header. 6506 }; 6507 6508 enum SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6509 { 6510 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Bitstream for Simple and Main Profile has no sync marker 6511 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Bitstream for Simple and Main Profile may have sync marker(s) 6512 }; 6513 6514 enum MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6515 { 6516 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< RESPIC Parameter is present in the picture header 6517 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< RESPIC Parameter is present in the picture header 6518 }; 6519 6520 enum QUANTIZER 6521 { 6522 QUANTIZER_UNNAMED0 = 0, //!< implicit quantizer at frame leve 6523 QUANTIZER_UNNAMED1 = 1, //!< explicit quantizer at frame level, and use PQUANTIZER SE to specify uniform or non-uniform 6524 QUANTIZER_UNNAMED2 = 2, //!< explicit quantizer, and non-uniform quantizer for all frames 6525 QUANTIZER_UNNAMED3 = 3, //!< explicit quantizer, and uniform quantizer for all frames 6526 }; 6527 6528 //! \brief P_PIC_REF_DISTANCE 6529 //! \details 6530 //! This element defines the number of frames between the current frame and 6531 //! the reference frame. It is the same as the REFDIST SE in VC1 interlaced 6532 //! field picture header. It is present if the entry-level flag REFDIST_FLAG 6533 //! == 1, and if the picture type is not one of the following types: B/B, 6534 //! B/BI, BI/B, BI/BI. If the entry level flag REFDIST_FLAG == 0, REFDIST 6535 //! shall be set to the default value of 0.This field is used in VC1 6536 //! VLD mode only, not used in IT and intel VC1 VLD Long Format modes. 6537 enum P_PIC_REF_DISTANCE 6538 { 6539 P_PIC_REF_DISTANCE_UNNAMED0 = 0, //!< No additional details 6540 }; 6541 6542 //! \brief PROGRESSIVE_PIC_TYPE 6543 //! \details 6544 //! This field is used in both VC1 VLD mode and IT mode. It is the 6545 //! same parameter as bPicExtrapolation in VC1 spec.The Picture 6546 //! Structure and Progressive Pic Type are used to derive the picture 6547 //! structure as specified in FCM, in VC1 VLD and IT mode. 6548 enum PROGRESSIVE_PIC_TYPE 6549 { 6550 PROGRESSIVE_PIC_TYPE_UNNAMED0 = 0, //!< progressive only picture 6551 PROGRESSIVE_PIC_TYPE_UNNAMED1 = 1, //!< progressive only picture 6552 PROGRESSIVE_PIC_TYPE_UNNAMED2 = 2, //!< interlace picture (frame-interlace or field-interlace) 6553 PROGRESSIVE_PIC_TYPE_UNNAMED3 = 3, //!< illegal 6554 }; 6555 6556 //! \brief RANGE_REDUCTION_ENABLE 6557 //! \details 6558 //! This field specifies whether on-the-fly pixel value 6559 //! range reduction should be performed for the preceding (or forward) 6560 //! reference 6561 //! picture. Along with RangeReductionScale to specify whether scale up 6562 //! or down 6563 //! should be performed. It is not the same value as RANGEREDFRM Syntax 6564 //! Element 6565 //! (_PictureParameters bPicDeblocked bit 5) in the Picture 6566 //! Header.This field is 6567 //! for Main Profile only. Simple Profile is always disable, and not 6568 //! applicable to 6569 //! Advanced Profile. This field is used in both VLD and IT modes.This 6570 //! is derived by 6571 //! driver from the history of RANGERED and RANGEREDFRM syntax elements 6572 //! (i.e. of 6573 //! forward/preceding reference picture) and those of the current 6574 //! picture.RANGERED 6575 //! is the same as (bPicOverflowBlocks >> 3) & 1. RANGEREDFRM 6576 //! is the same 6577 //! as (bPicDeblocked >> 5) & 1.For the current picture is a 6578 //! B picture, 6579 //! this field represents the state of the forward/preceding reference 6580 //! picture 6581 //! onlyDriver is responsible to keep RangeReductionScale, 6582 //! RangeReduction Enable and 6583 //! RANGERED Present Flag of current picture coherent. 6584 enum RANGE_REDUCTION_ENABLE 6585 { 6586 RANGE_REDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 6587 RANGE_REDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 6588 }; 6589 6590 //! \brief RANGE_REDUCTION_SCALE 6591 //! \details 6592 //! This field specifies whether the reference picture 6593 //! pixel values should be scaled up or scaled down on-the-fly, if 6594 //! RangeReduction is 6595 //! Enabled.NOTE: This bit is derived by driver for Main Profile only. 6596 //! Ignored in 6597 //! Simple and Advanced Profiles. This field is used in both VLD and IT 6598 //! modes.This 6599 //! is derived by driver from the history of RANGERED and RANGEREDFRM 6600 //! syntax 6601 //! elements (i.e. of forward/preceding reference picture) and those of 6602 //! the current 6603 //! picture. RANGERED is the same as (bPicOverflowBlocks >> 3) 6604 //! & 1. 6605 //! RANGEREDFRM is the same as (bPicDeblocked >> 5) & 1. For 6606 //! the current 6607 //! picture is a B picture, this field represents the state of the 6608 //! forward/preceding 6609 //! reference picture onlyDriver is responsible to keep 6610 //! RangeReductionScale, 6611 //! RangeReduction Enable and RANGERED Present Flag of current picture 6612 //! coherent. 6613 enum RANGE_REDUCTION_SCALE 6614 { 6615 RANGE_REDUCTION_SCALE_DISABLE = 0, //!< Scale down reference picture by factor of 2 6616 RANGE_REDUCTION_SCALE_ENABLE = 1, //!< Scale up reference picture by factor of 2 6617 }; 6618 6619 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 6620 //! \details 6621 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 6622 //! if Overlap smoothing is ON at the picture levelThis field is used in 6623 //! both VLD and IT modes 6624 enum OVERLAP_SMOOTHING_ENABLE_FLAG 6625 { 6626 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 6627 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 6628 }; 6629 6630 enum EXTENDED_DMV_PRESENT_FLAG 6631 { 6632 EXTENDED_DMV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_DMV is not present in the picture header 6633 EXTENDED_DMV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_DMV is present in the picture header 6634 }; 6635 6636 //! \brief REFPIC_FLAG 6637 //! \details 6638 //! For a BI picture, REFPIC flag must set to 0For I and P picture, REFPIC 6639 //! flag must set to 0.For a B picture, REFPIC flag must set to 0, except 6640 //! for a B-field in interlaced field mode which can be 0 or 1 (e.g. the top 6641 //! B field can be used as a reference for decoding its corresponding bottom 6642 //! B-field in a field pair).In VLD mode, this flag cannot be used as an 6643 //! optimization signaling for an I or P picture that is not used as a 6644 //! reference picture.This field is used in both VC1 VLD mode and IT 6645 //! mode. It is the same parameter as bPicDeblockConfined[bit2] in VC1 6646 //! spec.The Intra Picture Flag, Backward Prediction Present Flag and 6647 //! RefPicFlag are used to derive the picture type, as specified in PTYPE 6648 //! for a frame, and in FPTYPE for a field, in VC1 VLD and IT mode. 6649 enum REFPIC_FLAG 6650 { 6651 REFPIC_FLAG_UNNAMED0 = 0, //!< the current picture after decoded, will never used as a reference picture 6652 REFPIC_FLAG_UNNAMED1 = 1, //!< the current picture after decoded, will be used as a reference picture later 6653 }; 6654 6655 //! \name Initializations 6656 6657 //! \brief Explicit member initialization function 6658 MFD_VC1_SHORT_PIC_STATE_CMD(); 6659 6660 static const size_t dwSize = 5; 6661 static const size_t byteSize = 20; 6662 }; 6663 6664 //! 6665 //! \brief MFX_VC1_DIRECTMODE_STATE 6666 //! \details 6667 //! This is a picture level command and should be issued only once, even for 6668 //! a multi-slices picture. There is only one DMV buffer for read (when 6669 //! processing a B-picture) and one for write (when processing a P-Picture). 6670 //! Each DMV record is 64 bits per MB, to store the top and bottom field 6671 //! motion vectors (32-bit MVx,y each). 6672 //! 6673 struct MFX_VC1_DIRECTMODE_STATE_CMD 6674 { 6675 union 6676 { 6677 //!< DWORD 0 6678 struct 6679 { 6680 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6681 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6682 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6683 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6684 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6685 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6686 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6687 }; 6688 uint32_t Value; 6689 } DW0; 6690 union 6691 { 6692 //!< DWORD 1 6693 struct 6694 { 6695 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 6696 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPicture : __CODEGEN_BITFIELD( 6, 31) ; //!< Direct MV Write Buffer Base Address for the Current Picture 6697 }; 6698 uint32_t Value; 6699 } DW1; 6700 union 6701 { 6702 //!< DWORD 2 6703 struct 6704 { 6705 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPicture4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Direct MV Write Buffer Base Address for the Current Picture [47:32] 6706 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 6707 }; 6708 uint32_t Value; 6709 } DW2; 6710 union 6711 { 6712 //!< DWORD 3 6713 struct 6714 { 6715 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 6716 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6717 uint32_t DirectMvWriteBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Direct MV Write Buffer - Memory Compression Enable 6718 uint32_t DirectMvWriteBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6719 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 6720 uint32_t DirectMvWriteBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6721 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 6722 }; 6723 uint32_t Value; 6724 } DW3; 6725 union 6726 { 6727 //!< DWORD 4 6728 struct 6729 { 6730 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 6731 uint32_t DirectMvReadBufferBaseAddressForTheReferencePicture : __CODEGEN_BITFIELD( 6, 31) ; //!< Direct MV Read Buffer Base Address for the Reference Picture 6732 }; 6733 uint32_t Value; 6734 } DW4; 6735 union 6736 { 6737 //!< DWORD 5 6738 struct 6739 { 6740 uint32_t DirectMvReadBufferBaseAddressForTheCurrentPicture4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Direct MV Read Buffer Base Address for the Current Picture [47:32] 6741 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 6742 }; 6743 uint32_t Value; 6744 } DW5; 6745 union 6746 { 6747 //!< DWORD 6 6748 struct 6749 { 6750 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 6751 uint32_t DirectMvReadBufferBaseAddressForTheCurrentPictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6752 uint32_t DirectMvReadBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Direct MV Read Buffer - Memory Compression Enable 6753 uint32_t DirectMvReadBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6754 uint32_t Reserved203 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 6755 uint32_t DirectMvReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6756 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 6757 }; 6758 uint32_t Value; 6759 } DW6; 6760 6761 //! \name Local enumerations 6762 6763 enum SUBOPCODE_B 6764 { 6765 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 6766 }; 6767 6768 enum SUBOPCODE_A 6769 { 6770 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 6771 }; 6772 6773 enum MEDIA_COMMAND_OPCODE 6774 { 6775 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 6776 }; 6777 6778 enum PIPELINE 6779 { 6780 PIPELINE_MFXVC1DIRECTMODESTATE = 2, //!< No additional details 6781 }; 6782 6783 enum COMMAND_TYPE 6784 { 6785 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6786 }; 6787 6788 //! \brief DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6789 //! \details 6790 //! This field controls the priority of arbitration used in the GAC/GAM 6791 //! pipeline for this surface. 6792 enum DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6793 { 6794 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 6795 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 6796 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 6797 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 6798 }; 6799 6800 //! \brief DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6801 //! \details 6802 //! Distinguishes Vertical from Horizontal compression. Please refer to 6803 //! vol1a 6804 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 6805 //! section for more details. 6806 enum DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6807 { 6808 DIRECT_MV_WRITE_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 6809 DIRECT_MV_WRITE_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 6810 }; 6811 6812 //! \brief DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6813 //! \details 6814 //! <b>For Media Surfaces:</b> 6815 //! This field specifies the tiled resource mode. 6816 enum DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6817 { 6818 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 6819 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 6820 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 6821 }; 6822 6823 //! \brief DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6824 //! \details 6825 //! This field controls the priority of arbitration used in the GAC/GAM 6826 //! pipeline for this surface. 6827 enum DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6828 { 6829 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 6830 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 6831 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 6832 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 6833 }; 6834 6835 //! \brief DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6836 //! \details 6837 //! Distinguishes Vertical from Horizontal compression. Please refer to 6838 //! vol1a 6839 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 6840 //! section for more details. 6841 enum DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6842 { 6843 DIRECT_MV_READ_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 6844 DIRECT_MV_READ_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 6845 }; 6846 6847 //! \brief DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6848 //! \details 6849 //! <b>For Media Surfaces:</b> 6850 //! This field specifies the tiled resource mode. 6851 enum DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6852 { 6853 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 6854 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 6855 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 6856 }; 6857 6858 //! \name Initializations 6859 6860 //! \brief Explicit member initialization function 6861 MFX_VC1_DIRECTMODE_STATE_CMD(); 6862 6863 static const size_t dwSize = 7; 6864 static const size_t byteSize = 28; 6865 }; 6866 6867 //! 6868 //! \brief MFD_VC1_BSD_OBJECT 6869 //! \details 6870 //! The MFD_VC1_BSD_OBJECT command is the only primitive command for the VC1 6871 //! Decoding Pipeline. The macroblock data portion of the bitstream is 6872 //! loaded as indirect data object.Before issuing a MFD_VC1_BSD_OBJECT 6873 //! command, all VC1 states of the MFD Engine need to be valid. Therefore 6874 //! the commands used to set these states need to have been issued prior to 6875 //! the issue of a MFD_VC1_BSD_OBJECT command.VC1 deblock filter kernel 6876 //! cross the slice boundary if in the last MB row of a slice, so need to 6877 //! know the last MB row of a slice to disable the edge mask. There is why 6878 //! VC1 BSD hardware need to know the end of MB address for the current 6879 //! slice. As such no more phantom slice is needed for VC1, as long as the 6880 //! driver will program both start MB address in the current slice and the 6881 //! start MB address of the next slice. As a result, we can also support 6882 //! multiple picture state commands in between slices. 6883 //! 6884 struct MFD_VC1_BSD_OBJECT_CMD 6885 { 6886 union 6887 { 6888 //!< DWORD 0 6889 struct 6890 { 6891 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6892 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6893 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6894 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6895 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6896 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6897 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6898 }; 6899 uint32_t Value; 6900 } DW0; 6901 union 6902 { 6903 //!< DWORD 1 6904 struct 6905 { 6906 uint32_t IndirectBsdDataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect BSD Data Length 6907 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6908 }; 6909 uint32_t Value; 6910 } DW1; 6911 union 6912 { 6913 //!< DWORD 2 6914 struct 6915 { 6916 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 6917 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 6918 }; 6919 uint32_t Value; 6920 } DW2; 6921 union 6922 { 6923 //!< DWORD 3 6924 struct 6925 { 6926 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< Next Slice Vertical Position 6927 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 6928 uint32_t SliceStartVerticalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Start Vertical Position 6929 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6930 }; 6931 uint32_t Value; 6932 } DW3; 6933 union 6934 { 6935 //!< DWORD 4 6936 struct 6937 { 6938 uint32_t FirstmbbitoffsetFirstMacroblockBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< FirstMbBitOffset (First Macroblock Bit Offset ) 6939 uint32_t Reserved131 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 6940 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD( 4, 4) ; //!< EMULATION_PREVENTION_BYTE_PRESENT 6941 uint32_t Reserved133 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 6942 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31) ; //!< First_MB_Byte_Offset of Slice Data or Slice Header 6943 }; 6944 uint32_t Value; 6945 } DW4; 6946 6947 //! \name Local enumerations 6948 6949 enum SUBOPCODE_B 6950 { 6951 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 6952 }; 6953 6954 enum SUBOPCODE_A 6955 { 6956 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6957 }; 6958 6959 enum MEDIA_COMMAND_OPCODE 6960 { 6961 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6962 }; 6963 6964 enum PIPELINE 6965 { 6966 PIPELINE_MFXMULTIDW = 2, //!< No additional details 6967 }; 6968 6969 enum COMMAND_TYPE 6970 { 6971 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6972 }; 6973 6974 enum EMULATION_PREVENTION_BYTE_PRESENT 6975 { 6976 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 6977 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 6978 }; 6979 6980 //! \name Initializations 6981 6982 //! \brief Explicit member initialization function 6983 MFD_VC1_BSD_OBJECT_CMD(); 6984 6985 static const size_t dwSize = 5; 6986 static const size_t byteSize = 20; 6987 }; 6988 6989 //! 6990 //! \brief MFX_JPEG_PIC_STATE 6991 //! \details 6992 //! 6993 //! 6994 struct MFX_JPEG_PIC_STATE_CMD 6995 { 6996 union 6997 { 6998 //!< DWORD 0 6999 struct 7000 { 7001 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7002 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7003 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7004 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7005 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7006 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7007 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7008 }; 7009 uint32_t Value; 7010 } DW0; 7011 union 7012 { 7013 //!< DWORD 1 7014 struct 7015 { 7016 uint32_t OutputMcuStructure : __CODEGEN_BITFIELD( 0, 2) ; //!< OUTPUT_MCU_STRUCTURE, Encoder Only 7017 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved, Encoder Only 7018 uint32_t InputSurfaceFormatYuv : __CODEGEN_BITFIELD( 8, 11) ; //!< INPUT_SURFACE_FORMAT_YUV, Encoder Only 7019 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 20) ; //!< Reserved, Encoder Only 7020 uint32_t PixelsInVerticalLastMcu : __CODEGEN_BITFIELD(21, 25) ; //!< Pixels In Vertical Last MCU, Encoder Only 7021 uint32_t PixelsInHorizontalLastMcu : __CODEGEN_BITFIELD(26, 30) ; //!< Pixels In Horizontal Last MCU, Encoder Only 7022 uint32_t Reserved63 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, Encoder Only 7023 } Obj0; 7024 struct 7025 { 7026 uint32_t InputFormatYuv : __CODEGEN_BITFIELD( 0, 2) ; //!< INPUT_FORMAT_YUV, Decoder Only 7027 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved, Decoder Only 7028 uint32_t Rotation : __CODEGEN_BITFIELD( 4, 5) ; //!< ROTATION, Decoder Only 7029 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved, Decoder Only 7030 uint32_t OutputFormatYuv : __CODEGEN_BITFIELD( 8, 11) ; //!< OUTPUT_FORMAT_YUV, Decoder Only 7031 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved, Decoder Only 7032 uint32_t AverageDownSampling : __CODEGEN_BITFIELD(16, 16) ; //!< AVERAGE_DOWN_SAMPLING, Decoder Only 7033 uint32_t VerticalDownSamplingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< VERTICAL_DOWN_SAMPLING_ENABLE, Decoder Only 7034 uint32_t HorizontalDownSamplingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< HORIZONTAL_DOWN_SAMPLING_ENABLE, Decoder Only 7035 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved, Decoder Only 7036 uint32_t VerticalUpSamplingEnable : __CODEGEN_BITFIELD(20, 20) ; //!< VERTICAL_UP_SAMPLING_ENABLE, Decoder Only 7037 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved, Decoder Only 7038 } Obj1; 7039 uint32_t Value; 7040 } DW1; 7041 union 7042 { 7043 //!< DWORD 2 7044 struct 7045 { 7046 uint32_t FrameWidthInBlocksMinus1 : __CODEGEN_BITFIELD( 0, 12) ; //!< Frame Width In Blocks Minus 1, Decoder Only 7047 uint32_t Reserved77 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, Decoder Only 7048 uint32_t FrameHeightInBlocksMinus1 : __CODEGEN_BITFIELD(16, 28) ; //!< Frame Height In Blocks Minus 1, Decoder Only 7049 uint32_t OutputPixelNormalize : __CODEGEN_BITFIELD(29, 29) ; //!< OUTPUT_PIXEL_NORMALIZE, Decoder Only 7050 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved, Decoder Only 7051 } Obj0; 7052 struct 7053 { 7054 uint32_t FrameWidthInBlksMinus1 : __CODEGEN_BITFIELD( 0, 12) ; //!< Frame Width In Blks Minus 1, Encoder Only 7055 uint32_t Roundingquant : __CODEGEN_BITFIELD(13, 15) ; //!< ROUNDINGQUANT, Encoder Only 7056 uint32_t FrameHeightInBlksMinus1 : __CODEGEN_BITFIELD(16, 28) ; //!< Frame Height In Blks Minus 1, Encoder Only 7057 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved, Encoder Only 7058 } Obj1; 7059 uint32_t Value; 7060 } DW2; 7061 7062 //! \name Local enumerations 7063 7064 enum SUBOPCODE_B 7065 { 7066 SUBOPCODE_B_MEDIA = 0, //!< No additional details 7067 }; 7068 7069 enum SUBOPCODE_A 7070 { 7071 SUBOPCODE_A_COMMON = 0, //!< No additional details 7072 }; 7073 7074 enum MEDIA_COMMAND_OPCODE 7075 { 7076 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 7077 }; 7078 7079 enum PIPELINE 7080 { 7081 PIPELINE_MFXMULTIDW = 2, //!< No additional details 7082 }; 7083 7084 enum COMMAND_TYPE 7085 { 7086 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7087 }; 7088 7089 //! \brief OUTPUT_MCU_STRUCTURE 7090 //! \details 7091 //! <p></p> 7092 //! Output MCU Structure(<b>OutputMcuStructure</b>) should be set 7093 //! accordingly for each Input Surface Format 7094 //! YUV(<b>InputSurfaceFormatYUV</b>): 7095 //! <ul> 7096 //! <li>If <b>InputSurfaceFormatYUV</b> is set to NV12, 7097 //! <b>OutputMCUStructure</b> is set to YUV420.</li> 7098 //! <li>If <b>InputSurfaceFormatYUV</b> is set to UYVY or YUY2, 7099 //! <b>OutputMCUStructure</b> is set to YUV422H_2Y.</li> 7100 //! <li>If <b>InputSurfaceFormatYUV</b> is set to Y8, 7101 //! <b>OutputMCuStructure</b> is set to YUV400.</li> 7102 //! <li>If <b>InputSurfaceFormatYUV</b> is set to RGB (or GBR, BGR, 7103 //! YUV), <b>OutputMCuStructure</b> is set to RGB.</li> 7104 //! <li>If <b>InputSurfaceFormatYUV</b> is set to RGB, the order of 7105 //! encoded blocks in MCU will be same as the order of input image 7106 //! components. 7107 //! If the order of input image components is RGB (or GBR, BGR, YUV), 7108 //! then the order of blocks will be RGB (or GBR, BGR, YUV 7109 //! respectively).</li> 7110 //! </ul> 7111 //! <p></p> 7112 enum OUTPUT_MCU_STRUCTURE 7113 { 7114 OUTPUT_MCU_STRUCTURE_YUV_400 = 0, //!< Grayscale Image 7115 OUTPUT_MCU_STRUCTURE_YUV_420 = 1, //!< Both horizontally and vertically chroma 2:1 subsampled 7116 OUTPUT_MCU_STRUCTURE_YUV_422H2Y = 2, //!< Horizontally chroma 2:1 subsampled - horizontal 2 Y-blocks, 1 U and 1 V block 7117 OUTPUT_MCU_STRUCTURE_RGB = 3, //!< RGB or YUV444: No subsample 7118 OUTPUT_MCU_STRUCTURE_UNNAMED_4 = 4, //!< No additional details 7119 OUTPUT_MCU_STRUCTURE_UNNAMED5 = 5, //!< No additional details 7120 OUTPUT_MCU_STRUCTURE_UNNAMED6 = 6, //!< No additional details 7121 OUTPUT_MCU_STRUCTURE_UNNAMED7 = 7, //!< No additional details 7122 }; 7123 7124 enum INPUT_FORMAT_YUV 7125 { 7126 INPUT_FORMAT_YUV_UNNAMED0 = 0, //!< YUV400 (grayscale image) 7127 INPUT_FORMAT_YUV_UNNAMED1 = 1, //!< YUV420 7128 INPUT_FORMAT_YUV_UNNAMED2 = 2, //!< YUV422H_2Y (Horizontally chroma 2:1 subsampled) - horizontal 2 Y-block, 1U and 1V 7129 INPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUV444 7130 INPUT_FORMAT_YUV_UNNAMED_4 = 4, //!< YUV411 7131 INPUT_FORMAT_YUV_UNNAMED5 = 5, //!< YUV422V_2Y (Vertically chroma 2:1 subsampled) - vertical 2 Y-blocks, 1U and 1V 7132 INPUT_FORMAT_YUV_UNNAMED6 = 6, //!< YUV422H_4Y - 2x2 Y-blocks, vertical 2U and 2V 7133 INPUT_FORMAT_YUV_UNNAMED7 = 7, //!< YUV422V_4Y - 2x2 Y-blocks, horizontal 2U and 2V 7134 }; 7135 7136 //! \brief ROTATION 7137 //! \details 7138 //! Rotation can be set to 01b, 10b, or 11b when OutputFormatYUV is set to 7139 //! 0000b. For other OutputFormatYUV, Rotation is not allowed. 7140 enum ROTATION 7141 { 7142 ROTATION_UNNAMED0 = 0, //!< no rotation 7143 ROTATION_UNNAMED1 = 1, //!< rotate clockwise 90 degree 7144 ROTATION_UNNAMED2 = 2, //!< rotate counter-clockwise 90 degree (same as rotating 270 degree clockwise) 7145 ROTATION_UNNAMED3 = 3, //!< rotate 180 degree (NOT the same as flipped on the x-axis) 7146 }; 7147 7148 //! \brief OUTPUT_FORMAT_YUV 7149 //! \details 7150 //! This field specifies the surface format to write the decoded JPEG 7151 //! image.Note that any non-interleaved JPEG input should be set to "0000". 7152 //! For the interleaved input Scan data, it can be set either "0000" or the 7153 //! corresponding format. 7154 enum OUTPUT_FORMAT_YUV 7155 { 7156 OUTPUT_FORMAT_YUV_UNNAMED0 = 0, //!< 3 separate plane for Y, U, and V respectively 7157 OUTPUT_FORMAT_YUV_UNNAMED1 = 1, //!< NV12 for chroma 4:2:0 7158 OUTPUT_FORMAT_YUV_UNNAMED2 = 2, //!< UYVY for chroma 4:2:2 7159 OUTPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUY2 for chroma 4:2:2 7160 }; 7161 7162 //! \brief INPUT_SURFACE_FORMAT_YUV 7163 //! \details 7164 //! This field specifies the surface format to read a YUV image data 7165 enum INPUT_SURFACE_FORMAT_YUV 7166 { 7167 INPUT_SURFACE_FORMAT_YUV_UNNAMED0 = 0, //!< Reserved 7168 INPUT_SURFACE_FORMAT_YUV_NV12 = 1, //!< NV12 for chroma 4:2:0 7169 INPUT_SURFACE_FORMAT_YUV_UYVY = 2, //!< UYVY for chroma 4:2:2 7170 INPUT_SURFACE_FORMAT_YUV_YUY2 = 3, //!< YUY2 for chroma 4:2:2 7171 INPUT_SURFACE_FORMAT_YUV_Y8 = 4, //!< Y8 for chroma400 Y-only image 7172 INPUT_SURFACE_FORMAT_YUV_RGB = 5, //!< RGB or YUV for chroma 4:4:4 7173 }; 7174 7175 //! \brief AVERAGE_DOWN_SAMPLING 7176 //! \details 7177 //! This flag is used to select a down-sampling method when 7178 //! <b>VertDownSamplingEnb</b> or <b>HoriDownSamplingEnb</b> is set to 1. 7179 enum AVERAGE_DOWN_SAMPLING 7180 { 7181 AVERAGE_DOWN_SAMPLING_UNNAMED0 = 0, //!< Drop every other line (or column) pixels 7182 AVERAGE_DOWN_SAMPLING_UNNAMED1 = 1, //!< Average neighboring two pixels 7183 }; 7184 7185 //! \brief VERTICAL_DOWN_SAMPLING_ENABLE 7186 //! \details 7187 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 7188 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 7189 //! enable this flag, the input should be interleaved Scan, 7190 //! <b>InputFormatYUV</b> should be set to YUV422H_2Y or YUV422H_4Y, and 7191 //! <b>OutputFormatYUV</b> should be set to NV12. 7192 enum VERTICAL_DOWN_SAMPLING_ENABLE 7193 { 7194 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 7195 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical down-sampling 7196 }; 7197 7198 //! \brief HORIZONTAL_DOWN_SAMPLING_ENABLE 7199 //! \details 7200 //! Only applied to chroma blocks. This flag is used for 2:1 horizontal 7201 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 7202 //! enable this flag, the input should be interleaved Scan, 7203 //! <b>InputFormatYUV</b> should be set to YUV422V_2Y or YUV422V_4Y, and 7204 //! <b>OutputFormatYUV</b> should be set to NV12. 7205 enum HORIZONTAL_DOWN_SAMPLING_ENABLE 7206 { 7207 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 7208 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 horizonatl down-sampling 7209 }; 7210 7211 //! \brief VERTICAL_UP_SAMPLING_ENABLE 7212 //! \details 7213 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 7214 //! up-sampling for chroma 420 and outputting chroma422 YUY2 or UYVY format. 7215 //! To enable this flag, the input should be interleaved Scan, 7216 //! <b>InputFormatYUV</b> should be set to YUV420, and 7217 //! <b>OutputFormatYUV</b> should be set to YUY2 or UYVY. 7218 enum VERTICAL_UP_SAMPLING_ENABLE 7219 { 7220 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no up-sampling 7221 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical up-sampling 7222 }; 7223 7224 //! \brief ROUNDINGQUANT 7225 //! \details 7226 //! Rounding value applied to quantization output 7227 enum ROUNDINGQUANT 7228 { 7229 ROUNDINGQUANT_UNNAMED0 = 0, //!< 1/2 7230 ROUNDINGQUANT_UNNAMED1 = 1, //!< (1/2 - 1/128) 7231 ROUNDINGQUANT_UNNAMED2 = 2, //!< (1/2 + 1/128) 7232 ROUNDINGQUANT_UNNAMED3 = 3, //!< (1/2 - 1/64) 7233 ROUNDINGQUANT_UNNAMED_4 = 4, //!< (1/2 + 1/64) 7234 ROUNDINGQUANT_UNNAMED5 = 5, //!< (1/2 - 1/32) 7235 ROUNDINGQUANT_UNNAMED6 = 6, //!< (1/2 - 1/16) 7236 ROUNDINGQUANT_UNNAMED7 = 7, //!< (1/2 - 1/8) 7237 }; 7238 7239 //! \brief OUTPUT_PIXEL_NORMALIZE 7240 //! \details 7241 //! JPEG decoded output pixels for Y and U/V in order to adjust display YUV 7242 //! range. 7243 enum OUTPUT_PIXEL_NORMALIZE 7244 { 7245 OUTPUT_PIXEL_NORMALIZE_UNNAMED0 = 0, //!< No Normalization 7246 OUTPUT_PIXEL_NORMALIZE_UNNAMED1 = 1, //!< Normalize output pixels from [0,255] to [16,235] 7247 }; 7248 7249 //! \name Initializations 7250 7251 //! \brief Explicit member initialization function 7252 MFX_JPEG_PIC_STATE_CMD(); 7253 7254 static const size_t dwSize = 3; 7255 static const size_t byteSize = 12; 7256 }; 7257 7258 //! 7259 //! \brief MFC_JPEG_HUFF_TABLE_STATE 7260 //! \details 7261 //! This Huffman table commands contains both DC and AC tables for either 7262 //! luma or chroma. Once a Huffman table has been defined for a particular 7263 //! destination, it replaces the previous tables stored in that destination 7264 //! and shall be used in the remaining Scans of the current image. Two 7265 //! Huffman tables for luma and chroma will be sent to H/W, and chroma table 7266 //! is used for both U and V. 7267 //! 7268 struct MFC_JPEG_HUFF_TABLE_STATE_CMD 7269 { 7270 union 7271 { 7272 //!< DWORD 0 7273 struct 7274 { 7275 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7276 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7277 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7278 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7279 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7280 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7281 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7282 }; 7283 uint32_t Value; 7284 } DW0; 7285 union 7286 { 7287 //!< DWORD 1 7288 struct 7289 { 7290 uint32_t HuffTableId : __CODEGEN_BITFIELD( 0, 0) ; //!< HUFF_TABLE_ID 7291 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 7292 }; 7293 uint32_t Value; 7294 } DW1; 7295 7296 uint32_t DcTable[12]; //!< DC_TABLE 7297 7298 7299 uint32_t AcTable[162]; //!< AC_TABLE 7300 7301 7302 //! \name Local enumerations 7303 7304 enum SUBOPCODE_B 7305 { 7306 SUBOPCODE_B_MEDIA = 3, //!< No additional details 7307 }; 7308 7309 enum SUBOPCODE_A 7310 { 7311 SUBOPCODE_A_COMMON = 2, //!< No additional details 7312 }; 7313 7314 enum MEDIA_COMMAND_OPCODE 7315 { 7316 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 7317 }; 7318 7319 enum PIPELINE 7320 { 7321 PIPELINE_MFCJPEGHUFFTABLESTATE = 2, //!< No additional details 7322 }; 7323 7324 enum COMMAND_TYPE 7325 { 7326 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7327 }; 7328 7329 //! \brief HUFF_TABLE_ID 7330 //! \details 7331 //! Huffman table destination identifier will specify one of two 7332 //! destinations at the encoder into which the Huffman table must be stored. 7333 enum HUFF_TABLE_ID 7334 { 7335 HUFF_TABLE_ID_UNNAMED0 = 0, //!< Huffman table 0 7336 HUFF_TABLE_ID_UNNAMED1 = 1, //!< Huffman table 1 7337 }; 7338 7339 //! \name Initializations 7340 7341 //! \brief Explicit member initialization function 7342 MFC_JPEG_HUFF_TABLE_STATE_CMD(); 7343 7344 static const size_t dwSize = 176; 7345 static const size_t byteSize = 704; 7346 }; 7347 7348 //! 7349 //! \brief MFD_JPEG_BSD_OBJECT 7350 //! \details 7351 //! 7352 //! 7353 struct MFD_JPEG_BSD_OBJECT_CMD 7354 { 7355 union 7356 { 7357 //!< DWORD 0 7358 struct 7359 { 7360 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7361 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7362 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7363 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7364 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7365 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7366 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7367 }; 7368 uint32_t Value; 7369 } DW0; 7370 union 7371 { 7372 //!< DWORD 1 7373 struct 7374 { 7375 uint32_t IndirectDataLength ; //!< Indirect Data Length 7376 }; 7377 uint32_t Value; 7378 } DW1; 7379 union 7380 { 7381 //!< DWORD 2 7382 struct 7383 { 7384 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 7385 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 7386 }; 7387 uint32_t Value; 7388 } DW2; 7389 union 7390 { 7391 //!< DWORD 3 7392 struct 7393 { 7394 uint32_t ScanVerticalPosition : __CODEGEN_BITFIELD( 0, 12) ; //!< Scan Vertical Position 7395 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 7396 uint32_t ScanHorizontalPosition : __CODEGEN_BITFIELD(16, 28) ; //!< Scan Horizontal Position 7397 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 7398 }; 7399 uint32_t Value; 7400 } DW3; 7401 union 7402 { 7403 //!< DWORD 4 7404 struct 7405 { 7406 uint32_t McuCount : __CODEGEN_BITFIELD( 0, 25) ; //!< MCU Count 7407 uint32_t Reserved154 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 7408 uint32_t ScanComponents : __CODEGEN_BITFIELD(27, 29) ; //!< Scan Components 7409 uint32_t Interleaved : __CODEGEN_BITFIELD(30, 30) ; //!< INTERLEAVED 7410 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 7411 }; 7412 uint32_t Value; 7413 } DW4; 7414 union 7415 { 7416 //!< DWORD 5 7417 struct 7418 { 7419 uint32_t Restartinterval16Bit : __CODEGEN_BITFIELD( 0, 15) ; //!< RestartInterval(16 bit) 7420 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 7421 }; 7422 uint32_t Value; 7423 } DW5; 7424 7425 //! \name Local enumerations 7426 7427 enum SUBOPCODE_B 7428 { 7429 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 7430 }; 7431 7432 enum SUBOPCODE_A 7433 { 7434 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 7435 }; 7436 7437 enum MEDIA_COMMAND_OPCODE 7438 { 7439 MEDIA_COMMAND_OPCODE_JPEGDEC = 7, //!< No additional details 7440 }; 7441 7442 enum PIPELINE 7443 { 7444 PIPELINE_MFDJPEGBSDOBJECT = 2, //!< No additional details 7445 }; 7446 7447 enum COMMAND_TYPE 7448 { 7449 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7450 }; 7451 7452 enum INTERLEAVED 7453 { 7454 INTERLEAVED_NON_INTERLEAVED = 0, //!< one component in the Scan 7455 INTERLEAVED_INTERLEAVED = 1, //!< multiple components in the Scan 7456 }; 7457 7458 //! \name Initializations 7459 7460 //! \brief Explicit member initialization function 7461 MFD_JPEG_BSD_OBJECT_CMD(); 7462 7463 static const size_t dwSize = 6; 7464 static const size_t byteSize = 24; 7465 }; 7466 7467 //! 7468 //! \brief MFC_JPEG_SCAN_OBJECT 7469 //! \details 7470 //! Encoder Only 7471 //! 7472 struct MFC_JPEG_SCAN_OBJECT_CMD 7473 { 7474 union 7475 { 7476 //!< DWORD 0 7477 struct 7478 { 7479 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7480 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7481 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7482 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7483 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7484 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7485 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7486 }; 7487 uint32_t Value; 7488 } DW0; 7489 union 7490 { 7491 //!< DWORD 1 7492 struct 7493 { 7494 uint32_t McuCount : __CODEGEN_BITFIELD( 0, 25) ; //!< MCU Count 7495 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 7496 }; 7497 uint32_t Value; 7498 } DW1; 7499 union 7500 { 7501 //!< DWORD 2 7502 struct 7503 { 7504 uint32_t RestartInterval : __CODEGEN_BITFIELD( 0, 15) ; //!< Restart Interval 7505 uint32_t IsLastScan : __CODEGEN_BITFIELD(16, 16) ; //!< IS_LAST_SCAN 7506 uint32_t HeadPresentFlag : __CODEGEN_BITFIELD(17, 17) ; //!< HEAD_PRESENT_FLAG 7507 uint32_t HuffmanDcTable : __CODEGEN_BITFIELD(18, 20) ; //!< HUFFMAN_DC_TABLE 7508 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 7509 uint32_t HuffmanAcTable : __CODEGEN_BITFIELD(22, 24) ; //!< HUFFMAN_AC_TABLE 7510 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 7511 }; 7512 uint32_t Value; 7513 } DW2; 7514 7515 //! \name Local enumerations 7516 7517 enum SUBOPCODE_B 7518 { 7519 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 7520 }; 7521 7522 enum SUBOPCODE_A 7523 { 7524 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 7525 }; 7526 7527 enum MEDIA_COMMAND_OPCODE 7528 { 7529 MEDIA_COMMAND_OPCODE_JPEGENC = 7, //!< No additional details 7530 }; 7531 7532 enum PIPELINE 7533 { 7534 PIPELINE_MFCJPEGSCANOBJECT = 2, //!< No additional details 7535 }; 7536 7537 enum COMMAND_TYPE 7538 { 7539 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7540 }; 7541 7542 //! \brief IS_LAST_SCAN 7543 //! \details 7544 //! If this flag is set, then HW will insert EOI (0xFFD9) to the end of Scan 7545 //! encoded bitstream. 7546 enum IS_LAST_SCAN 7547 { 7548 IS_LAST_SCAN_UNNAMED0 = 0, //!< Not the last Scan. 7549 IS_LAST_SCAN_UNNAMED1 = 1, //!< Indicates that the current Scan is the last one. 7550 }; 7551 7552 //! \brief HEAD_PRESENT_FLAG 7553 //! \details 7554 //! If this flag is set to 0, then no MFC_JPEG_PAK_INSERT_OBJECT commands 7555 //! will be sent. 7556 //! If this flag is set to 1, then one or more 7557 //! MFC_JPEG_PAK_INSERT_OBJECT commands will be sent after 7558 //! MFC_JPEG_SCAN_OBJECT command. 7559 enum HEAD_PRESENT_FLAG 7560 { 7561 HEAD_PRESENT_FLAG_UNNAMED0 = 0, //!< No insertion into the output bitstream buffer before Scan encoded bitstream 7562 HEAD_PRESENT_FLAG_UNNAMED1 = 1, //!< Headers, tables, App data insertion into the output bitstream buffer. HW will insert the insertion data before the Scan encoded bitstream. 7563 }; 7564 7565 //! \brief HUFFMAN_DC_TABLE 7566 //! \details 7567 //! DC Huffman table destination selector specifies one of two possible DC 7568 //! table destinations for each Y, U, V, or R, G, B. 7569 //! The DC Huffman tables shall have been loaded in destination 0 and 1 7570 //! by the time of issuing MFC_JPEG_HUFF_TABLE_STATE Command. 7571 enum HUFFMAN_DC_TABLE 7572 { 7573 HUFFMAN_DC_TABLE_BIT20V0 = 0, //!< The third image component must use the DC table 0. 7574 HUFFMAN_DC_TABLE_BIT19U0 = 0, //!< The second image component must use the DC table 0. 7575 HUFFMAN_DC_TABLE_BIT18Y0 = 0, //!< The first image component must use the DC table 0. 7576 HUFFMAN_DC_TABLE_BIT18Y1 = 1, //!< The first image component must use the DC table 1. 7577 HUFFMAN_DC_TABLE_BIT19U1 = 2, //!< The second image component must use the DC table 1. 7578 HUFFMAN_DC_TABLE_BIT20V1 = 4, //!< The third image component must use the DC table 1. 7579 }; 7580 7581 //! \brief HUFFMAN_AC_TABLE 7582 //! \details 7583 //! AC Huffman table destination selector specifies one of two possible AC 7584 //! table destinations for each Y, U, V, or R, G, B. 7585 //! The AC Huffman tables must have been loaded in destination 0 and 1 7586 //! by the time of issuing MFC_JPEG_HUFF_TABLE_STATE Command. 7587 enum HUFFMAN_AC_TABLE 7588 { 7589 HUFFMAN_AC_TABLE_BIT2_4V0 = 0, //!< The third image component must use the AC table 0. 7590 HUFFMAN_AC_TABLE_BIT23U0 = 0, //!< The second image component must use the AC table 0. 7591 HUFFMAN_AC_TABLE_BIT22Y0 = 0, //!< The first image component must use the AC table 0. 7592 HUFFMAN_AC_TABLE_BIT22Y1 = 1, //!< The first image component must use the AC table 1. 7593 HUFFMAN_AC_TABLE_BIT23U1 = 2, //!< The second image component must use the AC table 1. 7594 HUFFMAN_AC_TABLE_BIT2_4V1 = 4, //!< The third image component must use the AC table 1. 7595 }; 7596 7597 //! \name Initializations 7598 7599 //! \brief Explicit member initialization function 7600 MFC_JPEG_SCAN_OBJECT_CMD(); 7601 7602 static const size_t dwSize = 3; 7603 static const size_t byteSize = 12; 7604 }; 7605 7606 //! 7607 //! \brief MFX_VP8_Encoder_CFG 7608 //! \details 7609 //! This must be the very first command to issue after the surface state, 7610 //! the pipe select and base address setting commands and must be issued 7611 //! before MFX_VP8_PIC_STATE. 7612 //! 7613 struct MFX_VP8_Encoder_CFG_CMD 7614 { 7615 union 7616 { 7617 //!< DWORD 0 7618 struct 7619 { 7620 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7621 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7622 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 7623 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 7624 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7625 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7626 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7627 }; 7628 uint32_t Value; 7629 } DW0; 7630 union 7631 { 7632 //!< DWORD 1 7633 struct 7634 { 7635 uint32_t PerformanceCounterEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Performance Counter Enable 7636 uint32_t FinalBitstreamOutputDisable : __CODEGEN_BITFIELD( 1, 1) ; //!< Final Bitstream Output Disable 7637 uint32_t TokenStatisticsOutputEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Output Enable 7638 uint32_t BitstreamStatisticsOutputEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< Bitstream Statistics Output Enable 7639 uint32_t UpdateSegmentFeatureDataFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< Update Segment Feature Data Flag 7640 uint32_t SkipFinalBitstreamWhenOverUnderFlow : __CODEGEN_BITFIELD( 5, 5) ; //!< Skip Final Bitstream when Over / Under flow 7641 uint32_t RateControlInitialPass : __CODEGEN_BITFIELD( 6, 6) ; //!< RATE_CONTROL_INITIAL_PASS 7642 uint32_t PerSegmentDeltaQindexLoopfilterDisable : __CODEGEN_BITFIELD( 7, 7) ; //!< Per Segment Delta Qindex / LoopFilter Disable 7643 uint32_t FinerBrcEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Finer BRC Enable 7644 uint32_t CompressedBitstreamOutputDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Compressed Bitstream Output Disable 7645 uint32_t VbspunitpowerclockGatingDisable : __CODEGEN_BITFIELD(10, 10) ; //!< VBSPunitPowerClock Gating Disable 7646 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 7647 }; 7648 uint32_t Value; 7649 } DW1; 7650 union 7651 { 7652 //!< DWORD 2 7653 struct 7654 { 7655 uint32_t MaxFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD( 0, 0) ; //!< MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7656 uint32_t MinFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD( 1, 1) ; //!< MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7657 uint32_t MaxInterMbBitCountCheckEnableMask : __CODEGEN_BITFIELD( 2, 2) ; //!< Max Inter MB Bit Count Check Enable Mask 7658 uint32_t MaxIntraMbBitCountCheckEnableMask : __CODEGEN_BITFIELD( 3, 3) ; //!< Max Intra MB Bit Count Check Enable Mask 7659 uint32_t IntermediateBitBufferOverrunEnableMask : __CODEGEN_BITFIELD( 4, 4) ; //!< Intermediate Bit Buffer Overrun Enable Mask 7660 uint32_t FinalBistreamBufferOverrunEnableMask : __CODEGEN_BITFIELD( 5, 5) ; //!< Final Bistream Buffer Overrun Enable Mask 7661 uint32_t QindexClampHighMaskForUnderflow : __CODEGEN_BITFIELD( 6, 6) ; //!< Qindex_Clamp_High_mask for underflow 7662 uint32_t QindexClampHighMaskForOverflow : __CODEGEN_BITFIELD( 7, 7) ; //!< Qindex_Clamp_High_mask for overflow 7663 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 7664 }; 7665 uint32_t Value; 7666 } DW2; 7667 union 7668 { 7669 //!< DWORD 3 7670 struct 7671 { 7672 uint32_t MaxInterMbBitCount : __CODEGEN_BITFIELD( 0, 11) ; //!< Max Inter MB bit count 7673 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7674 uint32_t MaxIntraMbBitCountLimit : __CODEGEN_BITFIELD(16, 27) ; //!< Max Intra MB Bit Count Limit 7675 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 7676 }; 7677 uint32_t Value; 7678 } DW3; 7679 union 7680 { 7681 //!< DWORD 4 7682 struct 7683 { 7684 uint32_t FrameBitRateMax : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Bit Rate Max 7685 uint32_t FrameBitRateMaxUnit : __CODEGEN_BITFIELD(14, 14) ; //!< FRAME_BIT_RATE_MAX_UNIT 7686 uint32_t FrameBitrateMaxUnitMode : __CODEGEN_BITFIELD(15, 15) ; //!< FRAME_BITRATE_MAX_UNIT_MODE 7687 uint32_t FrameBitRateMin : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Bit Rate Min 7688 uint32_t FrameBitRateMinUnit : __CODEGEN_BITFIELD(30, 30) ; //!< FRAME_BIT_RATE_MIN_UNIT 7689 uint32_t FrameBitrateMinUnitMode : __CODEGEN_BITFIELD(31, 31) ; //!< FRAME_BITRATE_MIN_UNIT_MODE 7690 }; 7691 uint32_t Value; 7692 } DW4; 7693 union 7694 { 7695 //!< DWORD 5 7696 struct 7697 { 7698 uint32_t FrameDeltaQindexMax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta QIndex Max [0] 7699 uint32_t FrameDeltaQindexMax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta QIndex Max[1] 7700 uint32_t FrameDeltaqIndexMax2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame DeltaQ Index Max[2] 7701 uint32_t FrameDeltaQindexMax3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta QIndex Max[3] 7702 }; 7703 uint32_t Value; 7704 } DW5; 7705 union 7706 { 7707 //!< DWORD 6 7708 struct 7709 { 7710 uint32_t FrameDeltaQindexMin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta QIndex Min[0] 7711 uint32_t FrameDeltaQindexMin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta QIndex Min[1] 7712 uint32_t FrameDeltaQindexMin2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta QIndex Min[2] 7713 uint32_t FrameDeltaQindexMin3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta QIndex Min[3] 7714 }; 7715 uint32_t Value; 7716 } DW6; 7717 union 7718 { 7719 //!< DWORD 7 7720 struct 7721 { 7722 uint32_t PerSegmentFrameDeltaQindexMax1 ; //!< Per Segment Frame Delta QIndex Max[1] 7723 }; 7724 uint32_t Value; 7725 } DW7; 7726 union 7727 { 7728 //!< DWORD 8 7729 struct 7730 { 7731 uint32_t PerSegmentFrameDeltaQindexMin1 ; //!< Per Segment Frame Delta QIndex Min[1] 7732 }; 7733 uint32_t Value; 7734 } DW8; 7735 union 7736 { 7737 //!< DWORD 9 7738 struct 7739 { 7740 uint32_t PerSegmentFrameDeltaQindexMax2 ; //!< Per Segment Frame Delta QIndex Max[2] 7741 }; 7742 uint32_t Value; 7743 } DW9; 7744 union 7745 { 7746 //!< DWORD 10 7747 struct 7748 { 7749 uint32_t PerSegmentFrameDeltaQindexMin2 ; //!< Per Segment Frame Delta QIndex Min[2] 7750 }; 7751 uint32_t Value; 7752 } DW10; 7753 union 7754 { 7755 //!< DWORD 11 7756 struct 7757 { 7758 uint32_t PerSegmentFrameDeltaQindexMax3 ; //!< Per Segment Frame Delta QIndex Max[3] 7759 }; 7760 uint32_t Value; 7761 } DW11; 7762 union 7763 { 7764 //!< DWORD 12 7765 struct 7766 { 7767 uint32_t PerSegmentFrameDeltaQindexMin3 ; //!< Per Segment Frame Delta QIndex Min[3] 7768 }; 7769 uint32_t Value; 7770 } DW12; 7771 union 7772 { 7773 //!< DWORD 13 7774 struct 7775 { 7776 uint32_t FrameDeltaLoopFilterMax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta Loop Filter Max[0] 7777 uint32_t FramEdeltaLoopFilterMax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Fram eDelta Loop Filter Max[1] 7778 uint32_t FrameDeltaLoopFilterMax2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta Loop Filter Max[2] 7779 uint32_t FrameDeltaLoopFilterMax3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta Loop Filter Max[3] 7780 }; 7781 uint32_t Value; 7782 } DW13; 7783 union 7784 { 7785 //!< DWORD 14 7786 struct 7787 { 7788 uint32_t FrameDeltaLoopFilterMin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta Loop Filter Min[0] 7789 uint32_t FrameDeltaLoopFilterMin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta Loop Filter Min[1] 7790 uint32_t FrameDeltaLoopFilterMin2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta Loop Filter Min[2] 7791 uint32_t FrameDeltaLoopFilterMin3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta Loop Filter Min[3] 7792 }; 7793 uint32_t Value; 7794 } DW14; 7795 union 7796 { 7797 //!< DWORD 15 7798 struct 7799 { 7800 uint32_t PerSegmentFrameDeltaLoopfilterMax1 ; //!< Per Segment Frame Delta LoopFilter Max[1] 7801 }; 7802 uint32_t Value; 7803 } DW15; 7804 union 7805 { 7806 //!< DWORD 16 7807 struct 7808 { 7809 uint32_t PerSegmentFrameDeltaLoopfilterMin1 ; //!< Per Segment Frame Delta LoopFilter Min[1] 7810 }; 7811 uint32_t Value; 7812 } DW16; 7813 union 7814 { 7815 //!< DWORD 17 7816 struct 7817 { 7818 uint32_t PerSegmentFrameDeltaLoopfilterMax2 ; //!< Per Segment Frame Delta LoopFilter Max[2] 7819 }; 7820 uint32_t Value; 7821 } DW17; 7822 union 7823 { 7824 //!< DWORD 18 7825 struct 7826 { 7827 uint32_t PerSegmentFrameDeltaLoopfilterMin2 ; //!< Per Segment Frame Delta LoopFilter Min[2] 7828 }; 7829 uint32_t Value; 7830 } DW18; 7831 union 7832 { 7833 //!< DWORD 19 7834 struct 7835 { 7836 uint32_t PerSegmentFrameDeltaLoopfilterMax3 ; //!< Per Segment Frame Delta LoopFilter Max[3] 7837 }; 7838 uint32_t Value; 7839 } DW19; 7840 union 7841 { 7842 //!< DWORD 20 7843 struct 7844 { 7845 uint32_t PerSegmentFrameDeltaLoopfilterMin3 ; //!< Per Segment Frame Delta LoopFilter Min[3] 7846 }; 7847 uint32_t Value; 7848 } DW20; 7849 union 7850 { 7851 //!< DWORD 21 7852 struct 7853 { 7854 uint32_t FrameBitRateMaxDelta : __CODEGEN_BITFIELD( 0, 14) ; //!< Frame Bit Rate Max Delta 7855 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 7856 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(16, 30) ; //!< FrameBitRateMinDelta 7857 uint32_t Reserved703 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 7858 }; 7859 uint32_t Value; 7860 } DW21; 7861 union 7862 { 7863 //!< DWORD 22 7864 struct 7865 { 7866 uint32_t MinFrameWsize : __CODEGEN_BITFIELD( 0, 15) ; //!< Min Frame WSize 7867 uint32_t MinFrameWsizeUnit : __CODEGEN_BITFIELD(16, 17) ; //!< MIN_FRAME_WSIZE_UNIT 7868 uint32_t Reserved722 : __CODEGEN_BITFIELD(18, 19) ; //!< Reserved 7869 uint32_t BitstreamFormatVersion : __CODEGEN_BITFIELD(20, 22) ; //!< Bitstream Format Version 7870 uint32_t ShowFrame : __CODEGEN_BITFIELD(23, 23) ; //!< Show Frame 7871 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 7872 }; 7873 uint32_t Value; 7874 } DW22; 7875 union 7876 { 7877 //!< DWORD 23 7878 struct 7879 { 7880 uint32_t HorizontalSizeCode : __CODEGEN_BITFIELD( 0, 15) ; //!< Horizontal_Size_Code 7881 uint32_t VerticalSizeCode : __CODEGEN_BITFIELD(16, 31) ; //!< Vertical_Size_Code 7882 }; 7883 uint32_t Value; 7884 } DW23; 7885 union 7886 { 7887 //!< DWORD 24 7888 struct 7889 { 7890 uint32_t FrameHeaderBitCount ; //!< Frame Header Bit Count 7891 }; 7892 uint32_t Value; 7893 } DW24; 7894 union 7895 { 7896 //!< DWORD 25 7897 struct 7898 { 7899 uint32_t FrameHeaderBinBufferQindexUpdatePointer ; //!< Frame Header Bin Buffer Qindex Update Pointer 7900 }; 7901 uint32_t Value; 7902 } DW25; 7903 union 7904 { 7905 //!< DWORD 26 7906 struct 7907 { 7908 uint32_t FrameHeaderBinBufferLoopfilterUpdatePointer ; //!< Frame Header Bin Buffer LoopFilter Update Pointer 7909 }; 7910 uint32_t Value; 7911 } DW26; 7912 union 7913 { 7914 //!< DWORD 27 7915 struct 7916 { 7917 uint32_t FrameHeaderBinBufferTokenUpdatePointer ; //!< Frame Header Bin Buffer Token Update Pointer 7918 }; 7919 uint32_t Value; 7920 } DW27; 7921 union 7922 { 7923 //!< DWORD 28 7924 struct 7925 { 7926 uint32_t FrameHeaderBinBufferMvupdatePointer ; //!< Frame Header Bin Buffer MVUpdate Pointer 7927 }; 7928 uint32_t Value; 7929 } DW28; 7930 union 7931 { 7932 //!< DWORD 29 7933 struct 7934 { 7935 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 7936 uint32_t Cv1 : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 7937 uint32_t Cv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 7938 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 7939 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 7940 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 7941 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 7942 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31) ; //!< ClampValues - CV7 7943 }; 7944 uint32_t Value; 7945 } DW29; 7946 7947 //! \name Local enumerations 7948 7949 enum SUB_OPCODE_B 7950 { 7951 SUB_OPCODE_B_MFXVP8ENCODERCFG = 1, //!< No additional details 7952 }; 7953 7954 enum SUB_OPCODE_A 7955 { 7956 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 7957 }; 7958 7959 enum MEDIA_COMMAND_OPCODE 7960 { 7961 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 7962 }; 7963 7964 enum PIPELINE 7965 { 7966 PIPELINE_VIDEOCODEC = 2, //!< No additional details 7967 }; 7968 7969 enum COMMAND_TYPE 7970 { 7971 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7972 }; 7973 7974 enum RATE_CONTROL_INITIAL_PASS 7975 { 7976 RATE_CONTROL_INITIAL_PASS_SUBSEQUENCEPASSES = 0, //!< No additional details 7977 RATE_CONTROL_INITIAL_PASS_INITIALPASS = 1, //!< No additional details 7978 }; 7979 7980 //! \brief MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7981 //! \details 7982 //! Enable Max. Frame Rate Control. 7983 //! This is a mask bit controlling if the condition of frame level bit 7984 //! count is greater than or equal to FrameBitRateMax. 7985 enum MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7986 { 7987 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS control register. 7988 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) >= (Frame Bit Rate Maximum Limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS control register. 7989 }; 7990 7991 //! \brief MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7992 //! \details 7993 //! Enable Min. Frame Rate Control. 7994 //! This is a mask bit controlling if the condition of frame level bit 7995 //! count is less than or equal to FrameBitRateMin. 7996 enum MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7997 { 7998 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS Control Register. 7999 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) =< (Frame Bit Rate Minimum limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS Control Register. 8000 }; 8001 8002 //! \brief FRAME_BIT_RATE_MAX_UNIT 8003 //! \details 8004 //! <i>This field is Frame Bitrate Maximum Mode</i> 8005 enum FRAME_BIT_RATE_MAX_UNIT 8006 { 8007 FRAME_BIT_RATE_MAX_UNIT_32_B = 0, //!< No additional details 8008 FRAME_BIT_RATE_MAX_UNIT_4_KB = 1, //!< No additional details 8009 }; 8010 8011 //! \brief FRAME_BITRATE_MAX_UNIT_MODE 8012 //! \details 8013 //! This field is the Frame Bitrate Maximum Limit Units. 8014 enum FRAME_BITRATE_MAX_UNIT_MODE 8015 { 8016 FRAME_BITRATE_MAX_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Max Unit is in old mode (128b/16Kb) 8017 FRAME_BITRATE_MAX_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Max Unit is in new mode (32byte/4Kb) 8018 }; 8019 8020 //! \brief FRAME_BIT_RATE_MIN_UNIT 8021 //! \details 8022 //! <i>This field is Frame Bitrate Minimum Mode.</i> 8023 enum FRAME_BIT_RATE_MIN_UNIT 8024 { 8025 FRAME_BIT_RATE_MIN_UNIT_32_B = 0, //!< No additional details 8026 FRAME_BIT_RATE_MIN_UNIT_4_KB = 1, //!< No additional details 8027 }; 8028 8029 //! \brief FRAME_BITRATE_MIN_UNIT_MODE 8030 //! \details 8031 //! This field is the Frame Bitrate Minimum Limit Units. 8032 enum FRAME_BITRATE_MIN_UNIT_MODE 8033 { 8034 FRAME_BITRATE_MIN_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Min Unit is in old mode (128b/16Kb) 8035 FRAME_BITRATE_MIN_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Min Unit is in new mode (32byte/4Kb) 8036 }; 8037 8038 enum MIN_FRAME_WSIZE_UNIT 8039 { 8040 MIN_FRAME_WSIZE_UNIT_COMPATIBILITYMODE = 0, //!< MinFrameWSizeUnit is in old mode (128b/16Kb) 8041 MIN_FRAME_WSIZE_UNIT_NEWMODE = 1, //!< MinFrameWSizeUnit is in new mode (32byte/4Kb) 8042 }; 8043 8044 //! \name Initializations 8045 8046 //! \brief Explicit member initialization function 8047 MFX_VP8_Encoder_CFG_CMD(); 8048 8049 static const size_t dwSize = 30; 8050 static const size_t byteSize = 120; 8051 }; 8052 8053 //! 8054 //! \brief MFX_VP8_BSP_BUF_BASE_ADDR_STATE 8055 //! \details 8056 //! 8057 //! 8058 struct MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD 8059 { 8060 union 8061 { 8062 //!< DWORD 0 8063 struct 8064 { 8065 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 8066 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 8067 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 8068 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 8069 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 8070 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 8071 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 8072 }; 8073 uint32_t Value; 8074 } DW0; 8075 union 8076 { 8077 //!< DWORD 1 8078 struct 8079 { 8080 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8081 uint32_t FrameHeaderBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Frame Header Base Addr 8082 }; 8083 uint32_t Value; 8084 } DW1; 8085 union 8086 { 8087 //!< DWORD 2 8088 struct 8089 { 8090 uint32_t FrameHeaderBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Frame Header Base Addr - Upper Range 8091 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8092 }; 8093 uint32_t Value; 8094 } DW2; 8095 union 8096 { 8097 //!< DWORD 3 8098 struct 8099 { 8100 uint32_t FrameHeaderBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8101 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8102 uint32_t FrameHeaderBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8103 uint32_t ForFrameheaderbaseaddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8104 uint32_t FrameHeaderBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8105 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8106 }; 8107 uint32_t Value; 8108 } DW3; 8109 union 8110 { 8111 //!< DWORD 4 8112 struct 8113 { 8114 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8115 uint32_t IntermediateBufferBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Intermediate Buffer Base Addr 8116 }; 8117 uint32_t Value; 8118 } DW4; 8119 union 8120 { 8121 //!< DWORD 5 8122 struct 8123 { 8124 uint32_t IntermediateBufferBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Intermediate Buffer Base Addr - Upper Range 8125 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8126 }; 8127 uint32_t Value; 8128 } DW5; 8129 union 8130 { 8131 //!< DWORD 6 8132 struct 8133 { 8134 uint32_t IntermediateBufferBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8135 uint32_t Reserved194 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8136 uint32_t IntermediateBufferBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8137 uint32_t IntermediateBufferBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8138 uint32_t IntermediateBufferBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8139 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8140 }; 8141 uint32_t Value; 8142 } DW6; 8143 union 8144 { 8145 //!< DWORD 7 8146 struct 8147 { 8148 uint32_t IntermediateBufferPartition1Offset ; //!< Intermediate Buffer Partition-1 Offset 8149 }; 8150 uint32_t Value; 8151 } DW7; 8152 union 8153 { 8154 //!< DWORD 8 8155 struct 8156 { 8157 uint32_t IntermediateBufferPartition2Offset ; //!< Intermediate Buffer Partition-2 Offset 8158 }; 8159 uint32_t Value; 8160 } DW8; 8161 union 8162 { 8163 //!< DWORD 9 8164 struct 8165 { 8166 uint32_t IntermediateBufferPartition3Offset ; //!< Intermediate Buffer Partition-3 Offset 8167 }; 8168 uint32_t Value; 8169 } DW9; 8170 union 8171 { 8172 //!< DWORD 10 8173 struct 8174 { 8175 uint32_t IntermediateBufferPartition4Offset ; //!< Intermediate Buffer Partition-4 Offset 8176 }; 8177 uint32_t Value; 8178 } DW10; 8179 union 8180 { 8181 //!< DWORD 11 8182 struct 8183 { 8184 uint32_t IntermediateBufferPartition5Offset ; //!< Intermediate Buffer Partition-5 Offset 8185 }; 8186 uint32_t Value; 8187 } DW11; 8188 union 8189 { 8190 //!< DWORD 12 8191 struct 8192 { 8193 uint32_t IntermediateBufferPartition6Offset ; //!< Intermediate Buffer Partition-6 Offset 8194 }; 8195 uint32_t Value; 8196 } DW12; 8197 union 8198 { 8199 //!< DWORD 13 8200 struct 8201 { 8202 uint32_t IntermediateBufferPartition7Offset ; //!< Intermediate Buffer Partition-7 Offset 8203 }; 8204 uint32_t Value; 8205 } DW13; 8206 union 8207 { 8208 //!< DWORD 14 8209 struct 8210 { 8211 uint32_t IntermediateBufferPartition8Offset ; //!< Intermediate Buffer Partition-8 Offset 8212 }; 8213 uint32_t Value; 8214 } DW14; 8215 union 8216 { 8217 //!< DWORD 15 8218 struct 8219 { 8220 uint32_t IntermediateBufferMaxSize ; //!< Intermediate Buffer Max Size 8221 }; 8222 uint32_t Value; 8223 } DW15; 8224 union 8225 { 8226 //!< DWORD 16 8227 struct 8228 { 8229 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8230 uint32_t FinalFrameBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Final Frame Base Addr 8231 }; 8232 uint32_t Value; 8233 } DW16; 8234 union 8235 { 8236 //!< DWORD 17 8237 struct 8238 { 8239 uint32_t FinalFrameBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Final Frame Base Addr - Upper Range 8240 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8241 }; 8242 uint32_t Value; 8243 } DW17; 8244 union 8245 { 8246 //!< DWORD 18 8247 struct 8248 { 8249 uint32_t FinalFrameBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8250 uint32_t Reserved578 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8251 uint32_t FinalFrameBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8252 uint32_t FinalFrameBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8253 uint32_t FinalFrameBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< FINAL_FRAME_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8254 uint32_t Reserved585 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8255 }; 8256 uint32_t Value; 8257 } DW18; 8258 union 8259 { 8260 //!< DWORD 19 8261 struct 8262 { 8263 uint32_t Finalframebyteoffset : __CODEGEN_BITFIELD( 0, 5) ; //!< FinalFrameByteOffset 8264 uint32_t Reserved614 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 8265 }; 8266 uint32_t Value; 8267 } DW19; 8268 union 8269 { 8270 //!< DWORD 20 8271 struct 8272 { 8273 uint32_t StreamoutBaseAddrCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8274 uint32_t StreamoutBaseAddrGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Streamout Base Addr - Graphics Data Type (GFDT) 8275 uint32_t Reserved643 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8276 uint32_t StreamoutBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8277 uint32_t StreamoutBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Streamout Base Addr 8278 }; 8279 uint32_t Value; 8280 } DW20; 8281 union 8282 { 8283 //!< DWORD 21 8284 struct 8285 { 8286 uint32_t StreamoutBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Streamout Base Addr - Upper Range 8287 uint32_t Reserved688 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8288 }; 8289 uint32_t Value; 8290 } DW21; 8291 union 8292 { 8293 //!< DWORD 22 8294 struct 8295 { 8296 uint32_t StreamoutBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8297 uint32_t Reserved706 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8298 uint32_t StreamoutBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8299 uint32_t StreamoutBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8300 uint32_t StreamoutBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8301 uint32_t Reserved713 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8302 }; 8303 uint32_t Value; 8304 } DW22; 8305 union 8306 { 8307 //!< DWORD 23 8308 struct 8309 { 8310 uint32_t CoeffProbsStreaminSurfaceCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8311 uint32_t CoeffProbsStreaminSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Coeff Probs StreamIn Surface - Graphics Data Type (GFDT) 8312 uint32_t Reserved739 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8313 uint32_t CoeffProbsStreaminSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8314 uint32_t CoeffProbsStreaminSurface : __CODEGEN_BITFIELD( 6, 31) ; //!< Coeff Probs StreamIn Surface 8315 }; 8316 uint32_t Value; 8317 } DW23; 8318 union 8319 { 8320 //!< DWORD 24 8321 struct 8322 { 8323 uint32_t CoeffProbsStreaminSurfaceUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Coeff Probs StreamIn Surface - Upper Range 8324 uint32_t Reserved784 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8325 }; 8326 uint32_t Value; 8327 } DW24; 8328 union 8329 { 8330 //!< DWORD 25 8331 struct 8332 { 8333 uint32_t CoeffProbsStreaminSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8334 uint32_t Reserved802 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8335 uint32_t CoeffProbsStreaminSurfaceTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8336 uint32_t CoeffProbsStreaminSurfaceLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8337 uint32_t CoeffProbsStreaminSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL 8338 uint32_t Reserved809 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8339 }; 8340 uint32_t Value; 8341 } DW25; 8342 union 8343 { 8344 //!< DWORD 26 8345 struct 8346 { 8347 uint32_t TokenStatisticsSurfaceCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8348 uint32_t TokenStatisticsSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Surface - Graphics Data Type (GFDT) 8349 uint32_t Reserved835 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8350 uint32_t FrameHeaderBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8351 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 6, 31) ; //!< Token Statistics Surface 8352 }; 8353 uint32_t Value; 8354 } DW26; 8355 union 8356 { 8357 //!< DWORD 27 8358 struct 8359 { 8360 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 0, 15) ; //!< Token Statistics Surface 8361 uint32_t Reserved880 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8362 }; 8363 uint32_t Value; 8364 } DW27; 8365 union 8366 { 8367 //!< DWORD 28 8368 struct 8369 { 8370 uint32_t TokenStatisticsSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8371 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Surface 8372 uint32_t TokenStatisticsSurfaceTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8373 uint32_t MemoryTypeLlcEllcCacheabilityControlLellcccForCoeffprobsStreaminSurface : __CODEGEN_BITFIELD( 5, 6) ; //!< MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8374 uint32_t TokenStatisticsSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8375 uint32_t Reserved905 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8376 }; 8377 uint32_t Value; 8378 } DW28; 8379 union 8380 { 8381 //!< DWORD 29..30 8382 struct 8383 { 8384 uint64_t MpcRowstoreSurfaceCacheabilityControl : __CODEGEN_BITFIELD(0, 1); //!< MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8385 uint64_t MpcRowstoreSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD(2, 2); //!< MPC RowStore Surface Graphics Data Type (GFDT) 8386 uint64_t Reserved931 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 8387 uint64_t MpcRowstoreBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD(4, 5); //!< MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8388 uint64_t MpcRowstoreSurfaceAddressLow : __CODEGEN_BITFIELD(6, 63); //!< MPC RowStore Surface Address Low 8389 }; 8390 uint32_t Value[2]; 8391 } DW29_30; 8392 union 8393 { 8394 //!< DWORD 31 8395 struct 8396 { 8397 uint32_t MpcRowstoreSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8398 uint32_t MpcRowstoreSurface : __CODEGEN_BITFIELD( 2, 2) ; //!< MPC RowStore Surface 8399 uint32_t MpcRowstoreTargetCache : __CODEGEN_BITFIELD( 3, 4) ; //!< MPC_ROWSTORE__TARGET_CACHE 8400 uint32_t MpcRowstoreMemoryTypeLlcEllcCacheabilityControl : __CODEGEN_BITFIELD( 5, 6) ; //!< MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8401 uint32_t MpcRowstoreArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8402 uint32_t Reserved1001 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8403 }; 8404 uint32_t Value; 8405 } DW31; 8406 8407 //! \name Local enumerations 8408 8409 enum SUB_OPCODE_B 8410 { 8411 SUB_OPCODE_B_MFXVP8BSPBUFBASEADDRSTATE = 3, //!< No additional details 8412 }; 8413 8414 enum SUB_OPCODE_A 8415 { 8416 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 8417 }; 8418 8419 enum MEDIA_COMMAND_OPCODE 8420 { 8421 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 8422 }; 8423 8424 enum PIPELINE 8425 { 8426 PIPELINE_VIDEOCODEC = 2, //!< No additional details 8427 }; 8428 8429 enum COMMAND_TYPE 8430 { 8431 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 8432 }; 8433 8434 //! \brief FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8435 //! \details 8436 //! This field allows the selection of AGE parameter for a given surface in 8437 //! LLC or eLLC. . 8438 //! If a particular allocation is done at youngest age ("3") it tends 8439 //! to stay longer in the cache as compared to older age allocations ("2", 8440 //! "1", or "0"). 8441 //! This option is given to driver to be able to decide which surfaces 8442 //! are more likely to generate HITs, hence need to be replaced least often 8443 //! in caches. 8444 enum FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8445 { 8446 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8447 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8448 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8449 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8450 }; 8451 8452 //! \brief FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8453 //! \details 8454 //! This field allows the choice of LLC vs eLLC for caching 8455 enum FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8456 { 8457 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8458 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8459 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8460 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8461 }; 8462 8463 //! \brief FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8464 //! \details 8465 //! This is the field used in GT interface block to determine what type of 8466 //! access need to be generated to uncore. 8467 //! For the cases where the LeLLCCC is set, cacheable transaction are 8468 //! generated to enable LLC usage for particular stream. 8469 enum FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8470 { 8471 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8472 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8473 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8474 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8475 }; 8476 8477 //! \brief FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8478 //! \details 8479 //! This field controls the priority of arbitration used in the GAC/GAM 8480 //! pipeline for this surface. 8481 enum FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8482 { 8483 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8484 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8485 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8486 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8487 }; 8488 8489 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8490 //! \details 8491 //! This field allows the selection of AGE parameter for a given surface in 8492 //! LLC or eLLC. . 8493 //! If a particular allocation is done at youngest age ("3") it tends 8494 //! to stay longer in the cache as compared to older age allocations ("2", 8495 //! "1", or "0"). 8496 //! This option is given to driver to be able to decide which surfaces 8497 //! are more likely to generate HITs, hence need to be replaced least often 8498 //! in caches. 8499 enum INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8500 { 8501 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8502 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8503 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8504 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8505 }; 8506 8507 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8508 //! \details 8509 //! This field allows the choice of LLC vs. eLLC for caching 8510 enum INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8511 { 8512 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8513 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8514 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8515 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8516 }; 8517 8518 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8519 //! \details 8520 //! This is the field used in GT interface block to determine what type of 8521 //! access need to be generated to uncore. 8522 //! For the cases where the LeLLCCC is set, cacheable transaction are 8523 //! generated to enable LLC usage for particular stream. 8524 enum INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8525 { 8526 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8527 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8528 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8529 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8530 }; 8531 8532 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8533 //! \details 8534 //! This field controls the priority of arbitration used in the GAC/GAM 8535 //! pipeline for this surface. 8536 enum INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8537 { 8538 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8539 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8540 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8541 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8542 }; 8543 8544 //! \brief FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8545 //! \details 8546 //! This field allows the selection of AGE parameter for a given surface in 8547 //! LLC or eLLC. . 8548 //! If a particular allocation is done at youngest age ("3") it tends 8549 //! to stay longer in the cache as compared to older age allocations ("2", 8550 //! "1", or "0"). 8551 //! This option is given to driver to be able to decide which surfaces 8552 //! are more likely to generate HITs, hence need to be replaced least often 8553 //! in caches. 8554 enum FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8555 { 8556 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8557 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8558 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8559 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8560 }; 8561 8562 //! \brief FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8563 //! \details 8564 //! This field allows the choice of LLC vs eLLC for caching 8565 enum FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8566 { 8567 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8568 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8569 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8570 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8571 }; 8572 8573 //! \brief FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8574 //! \details 8575 //! This is the field used in GT interface block to determine what type of 8576 //! access need to be generated to uncore. 8577 //! For the cases where the LeLLCCC is set, cacheable transaction are 8578 //! generated to enable LLC usage for particular stream. 8579 enum FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8580 { 8581 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8582 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8583 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8584 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8585 }; 8586 8587 enum FINAL_FRAME_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8588 { 8589 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8590 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8591 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8592 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8593 }; 8594 8595 //! \brief STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8596 //! \details 8597 //! This field controls cacheability in the mid-level cache (MLC) and 8598 //! last-level cache (LLC) 8599 enum STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8600 { 8601 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8602 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8603 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8604 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8605 }; 8606 8607 //! \brief STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8608 //! \details 8609 //! This field controls the priority of arbitration used in the GAC/GAM 8610 //! pipeline for this surface. 8611 enum STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8612 { 8613 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8614 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8615 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8616 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8617 }; 8618 8619 //! \brief STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8620 //! \details 8621 //! This field allows the selection of AGE parameter for a given surface in 8622 //! LLC or eLLC. . 8623 //! If a particular allocation is done at youngest age ("3") it tends 8624 //! to stay longer in the cache as compared to older age allocations ("2", 8625 //! "1", or "0"). 8626 //! This option is given to driver to be able to decide which surfaces 8627 //! are more likely to generate HITs, hence need to be replaced least often 8628 //! in caches. 8629 enum STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8630 { 8631 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8632 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8633 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8634 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8635 }; 8636 8637 //! \brief STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8638 //! \details 8639 //! This field allows the choice of LLC vs eLLC for caching 8640 enum STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8641 { 8642 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8643 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8644 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8645 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8646 }; 8647 8648 //! \brief STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8649 //! \details 8650 //! This is the field used in GT interface block to determine what type of 8651 //! access need to be generated to uncore. 8652 //! For the cases where the LeLLCCC is set, cacheable transaction are 8653 //! generated to enable LLC usage for particular stream. 8654 enum STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8655 { 8656 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8657 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8658 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8659 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8660 }; 8661 8662 //! \brief COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8663 //! \details 8664 //! This field controls cacheability in the mid-level cache (MLC) and 8665 //! last-level cache (LLC) 8666 enum COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8667 { 8668 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8669 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8670 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8671 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8672 }; 8673 8674 //! \brief COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8675 //! \details 8676 //! This field controls the priority of arbitration used in the GAC/GAM 8677 //! pipeline for this surface. 8678 enum COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8679 { 8680 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8681 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8682 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8683 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8684 }; 8685 8686 //! \brief COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8687 //! \details 8688 //! This field allows the selection of AGE parameter for a given surface in 8689 //! LLC or eLLC. . 8690 //! If a particular allocation is done at youngest age ("3") it tends 8691 //! to stay longer in the cache as compared to older age allocations ("2", 8692 //! "1", or "0"). 8693 //! This option is given to driver to be able to decide which surfaces 8694 //! are more likely to generate HITs, hence need to be replaced least often 8695 //! in caches. 8696 enum COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8697 { 8698 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8699 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8700 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8701 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8702 }; 8703 8704 //! \brief COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8705 //! \details 8706 //! This field allows the choice of LLC vs eLLC for caching 8707 enum COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8708 { 8709 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8710 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8711 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8712 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8713 }; 8714 8715 //! \brief COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8716 //! \details 8717 //! This is the field used in GT interface block to determine what type of 8718 //! access need to be generated to uncore. 8719 //! For the cases where the LeLLCCC is set, cacheable transaction are 8720 //! generated to enable LLC usage for particular stream. 8721 enum COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8722 { 8723 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8724 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8725 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8726 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8727 }; 8728 8729 //! \brief TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8730 //! \details 8731 //! This field controls cacheability in the mid-level cache (MLC) and 8732 //! last-level cache (LLC). 8733 enum TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8734 { 8735 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8736 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8737 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8738 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8739 }; 8740 8741 //! \brief TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8742 //! \details 8743 //! This field allows the selection of AGE parameter for a given surface in 8744 //! LLC or eLLC. . If a particular allocation is done at youngest age ("3") 8745 //! it tends to stay longer in the cache as compared to older age 8746 //! allocations ("2", "1", or "0"). 8747 //! This option is given to driver to be able to decide which surfaces 8748 //! are more likely to generate HITs, hence need to be replaced least often 8749 //! in caches. 8750 enum TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8751 { 8752 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 0, //!< No additional details 8753 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 1, //!< No additional details 8754 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 2, //!< No additional details 8755 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 3, //!< No additional details 8756 }; 8757 8758 //! \brief TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8759 //! \details 8760 //! This field allows the choice of LLC vs eLLC for caching. 8761 enum TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8762 { 8763 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGTBDW = 0, //!< No additional details 8764 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8765 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8766 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8767 }; 8768 8769 //! \brief MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8770 //! \details 8771 //! This is the field used in GT interface block to determine what type of 8772 //! access need to be generated to uncore. 8773 //! For the cases where the LeLLCCC is set, cacheable transaction are 8774 //! generated to enable LLC usage for particular stream. 8775 enum MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8776 { 8777 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_USECACHEABILITYCONTROLSFROMPAGETABLEUCWITHFENCEIFCOHERENTCYCLE = 0, //!< No additional details 8778 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_UC = 1, //!< Uncacheable - non-cacheable 8779 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_WT = 2, //!< Writethrough 8780 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_WB = 3, //!< Writeback 8781 }; 8782 8783 //! \brief TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8784 //! \details 8785 //! This field controls the priority of arbitration used in the GAC/GAM 8786 //! pipeline for this surface. 8787 enum TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8788 { 8789 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8790 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8791 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8792 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8793 }; 8794 8795 //! \brief MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8796 //! \details 8797 //! <b>This field controls cacheability in the mid-level cache (MLC) and 8798 //! last-level cache (LLC).</b> 8799 enum MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8800 { 8801 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8802 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8803 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8804 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8805 }; 8806 8807 //! \brief MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8808 //! \details 8809 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8810 //! pipeline for this surface.</b> 8811 enum MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8812 { 8813 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8814 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8815 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8816 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8817 }; 8818 8819 //! \brief MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8820 //! \details 8821 //! <b>This field allows the selection of AGE parameter for a given surface 8822 //! in LLC or eLLC. . If a particular allocation is done at youngest age 8823 //! ("3") it tends to stay longer in the cache as compared to older age 8824 //! allocations ("2", "1", or "0"). 8825 //! This option is given to driver to be able to decide which surfaces 8826 //! are more likely to generate HITs, hence need to be replaced least often 8827 //! in caches.</b> 8828 enum MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8829 { 8830 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 0, //!< No additional details 8831 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 1, //!< No additional details 8832 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 2, //!< No additional details 8833 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 3, //!< No additional details 8834 }; 8835 8836 //! \brief MPC_ROWSTORE__TARGET_CACHE 8837 //! \details 8838 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8839 //! pipeline for this surface.</b> 8840 enum MPC_ROWSTORE__TARGET_CACHE 8841 { 8842 MPC_ROWSTORE_TARGET_CACHE_ELLCONLY = 0, //!< No additional details 8843 MPC_ROWSTORE_TARGET_CACHE_LLCONLY = 1, //!< No additional details 8844 MPC_ROWSTORE_TARGET_CACHE_LLCELLCALLOWED = 2, //!< No additional details 8845 MPC_ROWSTORE_TARGET_CACHE_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8846 }; 8847 8848 //! \brief MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8849 //! \details 8850 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8851 //! pipeline for this surface.</b> 8852 enum MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8853 { 8854 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_USECACHEABILITYCONTROLSFROMPAGETABLEUCWITHFENCEIFCOHERENTCYCLE = 0, //!< No additional details 8855 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_UC = 1, //!< Uncacheable - non-cacheable 8856 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_WT = 2, //!< Writethrough 8857 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_WB = 3, //!< Writeback 8858 }; 8859 8860 //! \brief MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8861 //! \details 8862 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8863 //! pipeline for this surface.</b> 8864 enum MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8865 { 8866 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8867 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8868 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8869 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8870 }; 8871 8872 //! \name Initializations 8873 8874 //! \brief Explicit member initialization function 8875 MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD(); 8876 8877 static const size_t dwSize = 32; 8878 static const size_t byteSize = 128; 8879 }; 8880 8881 //! 8882 //! \brief MFD_VP8_BSD_OBJECT 8883 //! \details 8884 //! The MFD_VP8_BSD_OBJECT command is the only primitive command for the VP8 8885 //! Decoding Pipeline. The Partitions of the bitstream is loaded as indirect 8886 //! data object. Before issuing a MFD_VP8_BSD_OBJECT command, all VP8 frame 8887 //! level states of the MFD Engine need to be valid. Therefore the commands 8888 //! used to set these states need to have been issued prior to the issue of 8889 //! a MFD_VP8_BSD_OBJECT command. Context switch interrupt is not supported 8890 //! by this command. 8891 //! 8892 struct MFD_VP8_BSD_OBJECT_CMD 8893 { 8894 union 8895 { 8896 //!< DWORD 0 8897 struct 8898 { 8899 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 8900 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 8901 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 8902 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 8903 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 8904 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 8905 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 8906 }; 8907 uint32_t Value; 8908 } DW0; 8909 union 8910 { 8911 //!< DWORD 1 8912 struct 8913 { 8914 uint32_t Partition0FirstmbbitoffsetFromFrameHeader : __CODEGEN_BITFIELD( 0, 2) ; //!< Partition0 FirstMBBitOffset from Frame Header 8915 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8916 uint32_t CodedNumOfCoeffTokenPartitions : __CODEGEN_BITFIELD( 4, 5) ; //!< Coded Num of Coeff Token Partitions 8917 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 8918 uint32_t Partition0CpbacEntropyRange : __CODEGEN_BITFIELD( 8, 15) ; //!< Partition0 CPBAC Entropy Range 8919 uint32_t Partition0CpbacEntropyCount : __CODEGEN_BITFIELD(16, 20) ; //!< Partition0 CPBAC Entropy Count 8920 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 8921 }; 8922 uint32_t Value; 8923 } DW1; 8924 union 8925 { 8926 //!< DWORD 2 8927 struct 8928 { 8929 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 23) ; //!< Reserved 8930 uint32_t Partition0CpbacEntropyValue : __CODEGEN_BITFIELD(24, 31) ; //!< Partition0 CPBAC Entropy Value 8931 }; 8932 uint32_t Value; 8933 } DW2; 8934 union 8935 { 8936 //!< DWORD 3 8937 struct 8938 { 8939 uint32_t IndirectPartition0DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition0 Data Length 8940 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8941 }; 8942 uint32_t Value; 8943 } DW3; 8944 union 8945 { 8946 //!< DWORD 4 8947 struct 8948 { 8949 uint32_t IndirectPartition0DataStartOffset ; //!< Indirect Partition0 Data Start Offset 8950 }; 8951 uint32_t Value; 8952 } DW4; 8953 union 8954 { 8955 //!< DWORD 5 8956 struct 8957 { 8958 uint32_t IndirectPartition1DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition1 Data Length 8959 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8960 }; 8961 uint32_t Value; 8962 } DW5; 8963 union 8964 { 8965 //!< DWORD 6 8966 struct 8967 { 8968 uint32_t IndirectPartition1DataStartOffset ; //!< Indirect Partition1 Data Start Offset 8969 }; 8970 uint32_t Value; 8971 } DW6; 8972 union 8973 { 8974 //!< DWORD 7 8975 struct 8976 { 8977 uint32_t IndirectPartition2DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition2 Data Length 8978 uint32_t Reserved248 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8979 }; 8980 uint32_t Value; 8981 } DW7; 8982 union 8983 { 8984 //!< DWORD 8 8985 struct 8986 { 8987 uint32_t IndirectPartition2DataStartOffset ; //!< Indirect Partition2 Data Start Offset 8988 }; 8989 uint32_t Value; 8990 } DW8; 8991 union 8992 { 8993 //!< DWORD 9 8994 struct 8995 { 8996 uint32_t IndirectPartition3DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition3 Data Length 8997 uint32_t Reserved312 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8998 }; 8999 uint32_t Value; 9000 } DW9; 9001 union 9002 { 9003 //!< DWORD 10 9004 struct 9005 { 9006 uint32_t IndirectPartition3DataStartOffset ; //!< Indirect Partition3 Data Start Offset 9007 }; 9008 uint32_t Value; 9009 } DW10; 9010 union 9011 { 9012 //!< DWORD 11 9013 struct 9014 { 9015 uint32_t IndirectPartition4DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition4 Data Length 9016 uint32_t Reserved376 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9017 }; 9018 uint32_t Value; 9019 } DW11; 9020 union 9021 { 9022 //!< DWORD 12 9023 struct 9024 { 9025 uint32_t IndirectPartition4DataStartOffset ; //!< Indirect Partition4 Data Start Offset 9026 }; 9027 uint32_t Value; 9028 } DW12; 9029 union 9030 { 9031 //!< DWORD 13 9032 struct 9033 { 9034 uint32_t IndirectPartition5DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition5 Data Length 9035 uint32_t Reserved440 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9036 }; 9037 uint32_t Value; 9038 } DW13; 9039 union 9040 { 9041 //!< DWORD 14 9042 struct 9043 { 9044 uint32_t IndirectPartition5DataStartOffset ; //!< Indirect Partition5 Data Start Offset 9045 }; 9046 uint32_t Value; 9047 } DW14; 9048 union 9049 { 9050 //!< DWORD 15 9051 struct 9052 { 9053 uint32_t IndirectPartition6DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition6 Data Length 9054 uint32_t Reserved504 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9055 }; 9056 uint32_t Value; 9057 } DW15; 9058 union 9059 { 9060 //!< DWORD 16 9061 struct 9062 { 9063 uint32_t IndirectPartition6DataStartOffset ; //!< Indirect Partition6 Data Start Offset 9064 }; 9065 uint32_t Value; 9066 } DW16; 9067 union 9068 { 9069 //!< DWORD 17 9070 struct 9071 { 9072 uint32_t IndirectPartition7DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition7 Data Length 9073 uint32_t Reserved568 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9074 }; 9075 uint32_t Value; 9076 } DW17; 9077 union 9078 { 9079 //!< DWORD 18 9080 struct 9081 { 9082 uint32_t IndirectPartition7DataStartOffset ; //!< Indirect Partition7 Data Start Offset 9083 }; 9084 uint32_t Value; 9085 } DW18; 9086 union 9087 { 9088 //!< DWORD 19 9089 struct 9090 { 9091 uint32_t IndirectPartition8DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition8 Data Length 9092 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9093 }; 9094 uint32_t Value; 9095 } DW19; 9096 union 9097 { 9098 //!< DWORD 20 9099 struct 9100 { 9101 uint32_t IndirectPartition8DataStartOffset ; //!< Indirect Partition8 Data Start Offset 9102 }; 9103 uint32_t Value; 9104 } DW20; 9105 union 9106 { 9107 //!< DWORD 21 9108 struct 9109 { 9110 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 9111 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD( 8, 8) ; //!< MB_HEADER_ERROR_HANDLING 9112 uint32_t Reserved681 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 9113 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10) ; //!< ENTROPY_ERROR_HANDLING 9114 uint32_t Reserved683 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 9115 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 9116 uint32_t Reserved685 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 9117 uint32_t BsdprematurecompleteErrorHandling : __CODEGEN_BITFIELD(14, 14) ; //!< BSDPREMATURECOMPLETE_ERROR_HANDLING 9118 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9119 uint32_t ConcealPicIdConcealmentPictureId : __CODEGEN_BITFIELD(16, 17) ; //!< Conceal_Pic_Id (Concealment Picture ID) 9120 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 9121 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31) ; //!< CONCEALMENT_METHOD 9122 }; 9123 uint32_t Value; 9124 } DW21; 9125 9126 //! \name Local enumerations 9127 9128 enum SUBOPCODEB 9129 { 9130 SUBOPCODEB_UNNAMED8 = 8, //!< No additional details 9131 }; 9132 9133 enum SUBOPCODEA 9134 { 9135 SUBOPCODEA_UNNAMED1 = 1, //!< No additional details 9136 }; 9137 9138 enum MEDIA_COMMAND_OPCODE 9139 { 9140 MEDIA_COMMAND_OPCODE_VP8DEC = 4, //!< No additional details 9141 }; 9142 9143 enum PIPELINE 9144 { 9145 PIPELINE_MFDVP8BSDOBJECT = 2, //!< No additional details 9146 }; 9147 9148 enum COMMAND_TYPE 9149 { 9150 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9151 }; 9152 9153 enum MB_HEADER_ERROR_HANDLING 9154 { 9155 MB_HEADER_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9156 MB_HEADER_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9157 }; 9158 9159 enum ENTROPY_ERROR_HANDLING 9160 { 9161 ENTROPY_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9162 ENTROPY_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9163 }; 9164 9165 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 9166 { 9167 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9168 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9169 }; 9170 9171 //! \brief BSDPREMATURECOMPLETE_ERROR_HANDLING 9172 //! \details 9173 //! It occurs in situation where the decode is completed but there are still 9174 //! data in the bitstream. 9175 enum BSDPREMATURECOMPLETE_ERROR_HANDLING 9176 { 9177 BSDPREMATURECOMPLETE_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9178 BSDPREMATURECOMPLETE_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9179 }; 9180 9181 //! \brief CONCEALMENT_METHOD 9182 //! \details 9183 //! This field specifies the method used for concealment when error is 9184 //! detected. 9185 enum CONCEALMENT_METHOD 9186 { 9187 CONCEALMENT_METHOD_INTRA16X16PREDICTION = 0, //!< A copy from the current picture is performed using Intra 16x16 Prediction method. 9188 CONCEALMENT_METHOD_INTERPCOPY = 1, //!< A copy from collocated macroblock location is performed from the concealment reference indicated by the ConCeal_Pic_Id field. 9189 }; 9190 9191 //! \name Initializations 9192 9193 //! \brief Explicit member initialization function 9194 MFD_VP8_BSD_OBJECT_CMD(); 9195 9196 static const size_t dwSize = 22; 9197 static const size_t byteSize = 88; 9198 }; 9199 9200 //! 9201 //! \brief MFX_VP8_PIC_STATE 9202 //! \details 9203 //! This must be the very first command to issue after the surface state, 9204 //! the pipe select and base address setting commands and must be issued 9205 //! before MFX_VP8_IMG_STATE. 9206 //! 9207 struct MFX_VP8_PIC_STATE_CMD 9208 { 9209 union 9210 { 9211 //!< DWORD 0 9212 struct 9213 { 9214 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 9215 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 9216 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 9217 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 9218 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 9219 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 9220 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 9221 }; 9222 uint32_t Value; 9223 } DW0; 9224 union 9225 { 9226 //!< DWORD 1 9227 struct 9228 { 9229 uint32_t FrameWidthMinus1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Width Minus 1 9230 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 9231 uint32_t FrameHeightMinus1 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Height Minus 1 9232 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9233 }; 9234 uint32_t Value; 9235 } DW1; 9236 union 9237 { 9238 //!< DWORD 2 9239 struct 9240 { 9241 uint32_t McFilterSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< MC_FILTER_SELECT, Decoder / Encoder 9242 uint32_t ChromaFullPixelMcFilterMode : __CODEGEN_BITFIELD( 1, 1) ; //!< CHROMA_FULL_PIXEL_MC_FILTER_MODE, Decoder / Encoder 9243 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved, Decoder / Encoder 9244 uint32_t Dblkfiltertype : __CODEGEN_BITFIELD( 4, 4) ; //!< DBLKFILTERTYPE, Decoder / Encoder 9245 uint32_t Skeyframeflag : __CODEGEN_BITFIELD( 5, 5) ; //!< SKEYFRAMEFLAG, Decoder / Encoder 9246 uint32_t SegmentationIdStreamoutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< SEGMENTATION_ID_STREAMOUT_ENABLE, Decoder Only 9247 uint32_t SegmentationIdStreaminEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< SEGMENTATION_ID_STREAMIN_ENABLE, Decoder Only 9248 uint32_t SegmentEnableFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< SEGMENT_ENABLE_FLAG, Decoder / Encoder 9249 uint32_t UpdateMbsegmentMapFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< UPDATE_MBSEGMENT_MAP_FLAG, Decoder / Encoder 9250 uint32_t MbNocoeffSkipflag : __CODEGEN_BITFIELD(10, 10) ; //!< MB_NOCOEFF_SKIPFLAG, Decoder / Encoder 9251 uint32_t ModeReferenceLoopFilterDeltaEnabled : __CODEGEN_BITFIELD(11, 11) ; //!< MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED, Decoder / Encoder 9252 uint32_t GoldenRefPictureMvSignbiasFlag : __CODEGEN_BITFIELD(12, 12) ; //!< Golden Ref Picture MV SignBias Flag, Decoder / Encoder 9253 uint32_t AlternateRefPicMvSignbiasFlag : __CODEGEN_BITFIELD(13, 13) ; //!< Alternate Ref Pic MV SignBias Flag, Decoder / Encoder 9254 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved, Decoder / Encoder 9255 uint32_t DeblockSharpnessLevel : __CODEGEN_BITFIELD(16, 18) ; //!< Deblock Sharpness Level, Decoder / Encoder 9256 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved, Decoder / Encoder 9257 uint32_t Log2NumOfPartition : __CODEGEN_BITFIELD(24, 25) ; //!< LOG2_NUM_OF_PARTITION, Decoder / Encoder 9258 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 9259 }; 9260 uint32_t Value; 9261 } DW2; 9262 union 9263 { 9264 //!< DWORD 3 9265 struct 9266 { 9267 uint32_t DblkfilterlevelForSegment0 : __CODEGEN_BITFIELD( 0, 5) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT0 9268 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 9269 uint32_t DblkfilterlevelForSegment1 : __CODEGEN_BITFIELD( 8, 13) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT1 9270 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 9271 uint32_t DblkfilterlevelForSegment2 : __CODEGEN_BITFIELD(16, 21) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT2 9272 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 9273 uint32_t DblkfilterlevelForSegment3 : __CODEGEN_BITFIELD(24, 29) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT3 9274 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 9275 }; 9276 uint32_t Value; 9277 } DW3; 9278 union 9279 { 9280 //!< DWORD 4 9281 struct 9282 { 9283 uint32_t QuantizerValue0Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType0=Y1DC], Decoder Only 9284 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9285 uint32_t QuantizerValue0Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType1=Y1AC], Decoder Only 9286 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9287 } dec; 9288 struct 9289 { 9290 uint32_t Seg0Qindex : __CODEGEN_BITFIELD( 0, 6) ; //!< Seg 0 Qindex, Encoder Only 9291 uint32_t Reserved135 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved, Encoder Only 9292 uint32_t Seg1Qindex : __CODEGEN_BITFIELD( 8, 14) ; //!< Seg 1 Qindex, Encoder Only 9293 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved, Encoder Only 9294 uint32_t Seg2Qindex : __CODEGEN_BITFIELD(16, 22) ; //!< Seg 2 Qindex, Encoder Only 9295 uint32_t Reserved151 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved, Encoder Only 9296 uint32_t Seg3Qindex : __CODEGEN_BITFIELD(24, 30) ; //!< Seg 3 Qindex, Encoder Only 9297 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9298 } enc; 9299 uint32_t Value; 9300 } DW4; 9301 union 9302 { 9303 //!< DWORD 5 9304 struct 9305 { 9306 uint32_t QuantizerValue0Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType2=UVDC], Decoder Only 9307 uint32_t Reserved169 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9308 uint32_t QuantizerValue0Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType3=UVAC], Decoder Only 9309 uint32_t Reserved185 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9310 } dec; 9311 struct 9312 { 9313 uint32_t Y2DcQindexDelta : __CODEGEN_BITFIELD( 0, 3) ; //!< Y2dc Qindex Delta, Encoder Only 9314 uint32_t Y2AcQindexDeltaSign : __CODEGEN_BITFIELD( 4, 4) ; //!< Y2ac Qindex Delta Sign , Encoder Only 9315 uint32_t Reserved165 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved, Encoder Only 9316 uint32_t Y2AcQindexDelta : __CODEGEN_BITFIELD( 8, 11) ; //!< Y2ac Qindex Delta , Encoder Only 9317 uint32_t Y2AcQindexSign : __CODEGEN_BITFIELD(12, 12) ; //!< Y2ac Qindex Sign, Encoder Only 9318 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, Encoder Only 9319 uint32_t UvdcQindexDelta : __CODEGEN_BITFIELD(16, 19) ; //!< UVdc Qindex Delta, Encoder Only 9320 uint32_t UvdcQindexDeltaSign : __CODEGEN_BITFIELD(20, 20) ; //!< UVdc Qindex Delta Sign, Encoder Only 9321 uint32_t Reserved181 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved, Encoder Only 9322 uint32_t UvacQindexdelta : __CODEGEN_BITFIELD(24, 27) ; //!< UVac QindexDelta, Encoder Only 9323 uint32_t UvacQindexDeltaSign : __CODEGEN_BITFIELD(28, 28) ; //!< UVac Qindex Delta Sign, Encoder Only 9324 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 9325 } enc; 9326 uint32_t Value; 9327 } DW5; 9328 union 9329 { 9330 //!< DWORD 6 9331 struct 9332 { 9333 uint32_t QuantizerValue0Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType4=Y2DC], Decoder Only 9334 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9335 uint32_t QuantizerValue0Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType5=Y2AC], Decoder Only 9336 uint32_t Reserved217 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9337 } dec; 9338 struct 9339 { 9340 uint32_t Y1DcQindexDelta : __CODEGEN_BITFIELD( 0, 3) ; //!< Y1dc Qindex Delta, Encoder Only 9341 uint32_t Y1DcQindexDeltaSign : __CODEGEN_BITFIELD( 4, 4) ; //!< Y1dc Qindex Delta Sign , Encoder Only 9342 uint32_t Reserved197 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 9343 } enc; 9344 uint32_t Value; 9345 } DW6; 9346 union 9347 { 9348 //!< DWORD 7 9349 struct 9350 { 9351 uint32_t QuantizerValue1Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType0=Y1DC], Decoder Only 9352 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9353 uint32_t QuantizerValue1Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType1=Y1AC], Decoder Only 9354 uint32_t Reserved249 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9355 } dec; 9356 struct 9357 { 9358 uint32_t ClampQindexLow : __CODEGEN_BITFIELD( 0, 6) ; //!< Clamp Qindex Low, Encoder Only 9359 uint32_t Reserved231 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved, Encoder Only 9360 uint32_t ClampQindexHigh : __CODEGEN_BITFIELD( 8, 14) ; //!< Clamp Qindex high, Encoder Only 9361 uint32_t Reserved239 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9362 } enc; 9363 uint32_t Value; 9364 } DW7; 9365 union 9366 { 9367 //!< DWORD 8 9368 struct 9369 { 9370 uint32_t QuantizerValue1Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType2=UVDC], Decoder Only 9371 uint32_t Reserved265 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9372 uint32_t QuantizerValue1Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType3=UVAC], Decoder Only 9373 uint32_t Reserved281 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9374 }; 9375 uint32_t Value; 9376 } DW8; 9377 union 9378 { 9379 //!< DWORD 9 9380 struct 9381 { 9382 uint32_t QuantizerValue1Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType4=Y2DC], Decoder Only 9383 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9384 uint32_t QuantizerValue1Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType5=Y2AC], Decoder Only 9385 uint32_t Reserved313 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9386 }; 9387 uint32_t Value; 9388 } DW9; 9389 union 9390 { 9391 //!< DWORD 10 9392 struct 9393 { 9394 uint32_t QuantizerValue2Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType0=Y1DC], Decoder Only 9395 uint32_t Reserved329 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9396 uint32_t QuantizerValue2Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType1=Y1AC], Decoder Only 9397 uint32_t Reserved345 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9398 }; 9399 uint32_t Value; 9400 } DW10; 9401 union 9402 { 9403 //!< DWORD 11 9404 struct 9405 { 9406 uint32_t QuantizerValue2Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType2=UVDC], Decoder Only 9407 uint32_t Reserved361 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9408 uint32_t QuantizerValue2Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType3=UVAC], Decoder Only 9409 uint32_t Reserved377 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9410 }; 9411 uint32_t Value; 9412 } DW11; 9413 union 9414 { 9415 //!< DWORD 12 9416 struct 9417 { 9418 uint32_t QuantizerValue2Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType4=Y2DC], Decoder Only 9419 uint32_t Reserved393 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9420 uint32_t QuantizerValue2Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType5=Y2AC], Decoder Only 9421 uint32_t Reserved409 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9422 }; 9423 uint32_t Value; 9424 } DW12; 9425 union 9426 { 9427 //!< DWORD 13 9428 struct 9429 { 9430 uint32_t QuantizerValue3Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType0=Y1DC], Decoder Only 9431 uint32_t Reserved425 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9432 uint32_t QuantizerValue3Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType1=Y1AC], Decoder Only 9433 uint32_t Reserved441 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9434 }; 9435 uint32_t Value; 9436 } DW13; 9437 union 9438 { 9439 //!< DWORD 14 9440 struct 9441 { 9442 uint32_t QuantizerValue3Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType2=UVDC], Decoder Only 9443 uint32_t Reserved457 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9444 uint32_t QuantizerValue3Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType3=UVAC], Decoder Only 9445 uint32_t Reserved473 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9446 }; 9447 uint32_t Value; 9448 } DW14; 9449 union 9450 { 9451 //!< DWORD 15 9452 struct 9453 { 9454 uint32_t QuantizerValue3Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType4=Y2DC], Decoder Only 9455 uint32_t Reserved489 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9456 uint32_t QuantizerValue3Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType5=Y2AC], Decoder Only 9457 uint32_t Reserved505 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9458 }; 9459 uint32_t Value; 9460 } DW15; 9461 union 9462 { 9463 //!< DWORD 16 9464 struct 9465 { 9466 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 9467 uint32_t CoeffprobabilityStreaminBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< CoeffProbability StreamIn Base Address, Decoder Only 9468 }; 9469 uint32_t Value; 9470 } DW16; 9471 union 9472 { 9473 //!< DWORD 17 9474 struct 9475 { 9476 uint32_t CoeffprobabilityStreaminAddress : __CODEGEN_BITFIELD( 0, 15) ; //!< CoeffProbability StreamIn Address, Decoder Only 9477 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9478 }; 9479 uint32_t Value; 9480 } DW17; 9481 union 9482 { 9483 //!< DWORD 18 9484 struct 9485 { 9486 uint32_t Reserved576 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 9487 uint32_t CoeffprobabilityStreaminArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL, Decoder Only 9488 uint32_t CoeffprobabilityStreaminMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< CoeffProbability StreamIn - Memory Compression Enable, Decoder Only 9489 uint32_t CoeffprobabilityStreaminMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE, Decoder Only 9490 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved, Decoder Only 9491 uint32_t CoeffprobabilityStreaminTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE, Decoder Only 9492 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9493 }; 9494 uint32_t Value; 9495 } DW18; 9496 union 9497 { 9498 //!< DWORD 19 9499 struct 9500 { 9501 uint32_t Mbsegmentidtreeprobs0 : __CODEGEN_BITFIELD( 0, 7) ; //!< MBSegmentIDTreeProbs[0] 9502 uint32_t Mbsegmentidtreeprobs1 : __CODEGEN_BITFIELD( 8, 15) ; //!< MBSegmentIDTreeProbs[1] 9503 uint32_t Mbsegmentidtreeprobs2 : __CODEGEN_BITFIELD(16, 23) ; //!< MBSegmentIDTreeProbs[2] 9504 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9505 }; 9506 uint32_t Value; 9507 } DW19; 9508 union 9509 { 9510 //!< DWORD 20 9511 struct 9512 { 9513 uint32_t Interpredfromgrefrefprob : __CODEGEN_BITFIELD( 0, 7) ; //!< InterPredFromGRefRefProb 9514 uint32_t Interpredfromlastrefprob : __CODEGEN_BITFIELD( 8, 15) ; //!< InterPredFromLastRefProb 9515 uint32_t Intrambprob : __CODEGEN_BITFIELD(16, 23) ; //!< IntraMBProb 9516 uint32_t Mbnocoeffskipfalseprob : __CODEGEN_BITFIELD(24, 31) ; //!< MBNoCoeffSkipFalseProb 9517 }; 9518 uint32_t Value; 9519 } DW20; 9520 union 9521 { 9522 //!< DWORD 21 9523 struct 9524 { 9525 uint32_t Ymodeprob0 : __CODEGEN_BITFIELD( 0, 7) ; //!< YModeProb[0] 9526 uint32_t Ymodeprob1 : __CODEGEN_BITFIELD( 8, 15) ; //!< YModeProb[1] 9527 uint32_t Ymodeprob2 : __CODEGEN_BITFIELD(16, 23) ; //!< YModeProb[2] 9528 uint32_t Ymodeprob3 : __CODEGEN_BITFIELD(24, 31) ; //!< YModeProb[3] 9529 }; 9530 uint32_t Value; 9531 } DW21; 9532 union 9533 { 9534 //!< DWORD 22 9535 struct 9536 { 9537 uint32_t Uvmodeprob0 : __CODEGEN_BITFIELD( 0, 7) ; //!< UVModeProb[0] 9538 uint32_t Uvmodeprob1 : __CODEGEN_BITFIELD( 8, 15) ; //!< UVModeProb[1] 9539 uint32_t Uvmodeprob2 : __CODEGEN_BITFIELD(16, 23) ; //!< UVModeProb[2] 9540 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9541 }; 9542 uint32_t Value; 9543 } DW22; 9544 union 9545 { 9546 //!< DWORD 23 9547 struct 9548 { 9549 uint32_t Mvupdateprobs00 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][0] 9550 uint32_t Mvupdateprobs01 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][1] 9551 uint32_t Mvupdateprobs02 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][2] 9552 uint32_t Mvupdateprobs03 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][3] 9553 }; 9554 uint32_t Value; 9555 } DW23; 9556 union 9557 { 9558 //!< DWORD 24 9559 struct 9560 { 9561 uint32_t Mvupdateprobs04 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][4] 9562 uint32_t Mvupdateprobs05 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][5] 9563 uint32_t Mvupdateprobs06 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][6] 9564 uint32_t Mvupdateprobs07 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][7] 9565 }; 9566 uint32_t Value; 9567 } DW24; 9568 union 9569 { 9570 //!< DWORD 25 9571 struct 9572 { 9573 uint32_t Mvupdateprobs08 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][8] 9574 uint32_t Mvupdateprobs09 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][9] 9575 uint32_t Mvupdateprobs010 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][10] 9576 uint32_t Mvupdateprobs011 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][11] 9577 }; 9578 uint32_t Value; 9579 } DW25; 9580 union 9581 { 9582 //!< DWORD 26 9583 struct 9584 { 9585 uint32_t Mvupdateprobs012 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][12] 9586 uint32_t Mvupdateprobs013 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][13] 9587 uint32_t Mvupdateprobs014 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][14] 9588 uint32_t Mvupdateprobs015 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][15] 9589 }; 9590 uint32_t Value; 9591 } DW26; 9592 union 9593 { 9594 //!< DWORD 27 9595 struct 9596 { 9597 uint32_t Mvupdateprobs016 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][16] 9598 uint32_t Mvupdateprobs017 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][17] 9599 uint32_t Mvupdateprobs018 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][18] 9600 uint32_t Reserved888 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9601 }; 9602 uint32_t Value; 9603 } DW27; 9604 union 9605 { 9606 //!< DWORD 28 9607 struct 9608 { 9609 uint32_t Mvupdateprobs10 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][0] 9610 uint32_t Mvupdateprobs11 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][1] 9611 uint32_t Mvupdateprobs12 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][2] 9612 uint32_t Mvupdateprobs13 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][3] 9613 }; 9614 uint32_t Value; 9615 } DW28; 9616 union 9617 { 9618 //!< DWORD 29 9619 struct 9620 { 9621 uint32_t Mvupdateprobs14 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][4] 9622 uint32_t Mvupdateprobs15 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][5] 9623 uint32_t Mvupdateprobs16 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][6] 9624 uint32_t Mvupdateprobs17 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][7] 9625 }; 9626 uint32_t Value; 9627 } DW29; 9628 union 9629 { 9630 //!< DWORD 30 9631 struct 9632 { 9633 uint32_t Mvupdateprobs18 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][8] 9634 uint32_t Mvupdateprobs19 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][9] 9635 uint32_t Mvupdateprobs110 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][10] 9636 uint32_t Mvupdateprobs111 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][11] 9637 }; 9638 uint32_t Value; 9639 } DW30; 9640 union 9641 { 9642 //!< DWORD 31 9643 struct 9644 { 9645 uint32_t Mvupdateprobs112 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][12] 9646 uint32_t Mvupdateprobs113 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][13] 9647 uint32_t Mvupdateprobs114 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][14] 9648 uint32_t Mvupdateprobs115 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][15] 9649 }; 9650 uint32_t Value; 9651 } DW31; 9652 union 9653 { 9654 //!< DWORD 32 9655 struct 9656 { 9657 uint32_t Mvupdateprobs116 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][16] 9658 uint32_t Mvupdateprobs117 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][17] 9659 uint32_t Mvupdateprobs118 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][18] 9660 uint32_t Reserved1048 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9661 }; 9662 uint32_t Value; 9663 } DW32; 9664 union 9665 { 9666 //!< DWORD 33 9667 struct 9668 { 9669 uint32_t Reflfdelta0ForIntraFrame : __CODEGEN_BITFIELD( 0, 6) ; //!< RefLFDelta0 (for INTRA FRAME) 9670 uint32_t Reserved1063 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 9671 uint32_t Reflfdelta1ForLastFrame : __CODEGEN_BITFIELD( 8, 14) ; //!< RefLFDelta1 (for LAST FRAME) 9672 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9673 uint32_t Reflfdelta2ForGoldenFrame : __CODEGEN_BITFIELD(16, 22) ; //!< RefLFDelta2 (for GOLDEN FRAME) 9674 uint32_t Reserved1079 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 9675 uint32_t Reflfdelta3ForAltrefFrame : __CODEGEN_BITFIELD(24, 30) ; //!< RefLFDelta3 (for ALTREF FRAME) 9676 uint32_t Reserved1087 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9677 }; 9678 uint32_t Value; 9679 } DW33; 9680 union 9681 { 9682 //!< DWORD 34 9683 struct 9684 { 9685 uint32_t Modelfdelta0ForBPredMode : __CODEGEN_BITFIELD( 0, 6) ; //!< ModeLFDelta0 (for B_PRED mode) 9686 uint32_t Reserved1095 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 9687 uint32_t Modelfdelta1ForZeromvMode : __CODEGEN_BITFIELD( 8, 14) ; //!< ModeLFDelta1(for ZEROMV mode) 9688 uint32_t Reserved1103 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9689 uint32_t Modelfdelta2ForNearestNearAndNewMode : __CODEGEN_BITFIELD(16, 22) ; //!< ModeLFDelta2 (for Nearest, Near and New mode) 9690 uint32_t Reserved1111 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 9691 uint32_t Modelfdelta3ForSplitmvMode : __CODEGEN_BITFIELD(24, 30) ; //!< ModeLFDelta3 (for SPLITMV mode) 9692 uint32_t Reserved1119 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9693 }; 9694 uint32_t Value; 9695 } DW34; 9696 union 9697 { 9698 //!< DWORD 35 9699 struct 9700 { 9701 uint32_t SegmentationIdStreamBaseAddress ; //!< Segmentation ID Stream Base Address 9702 }; 9703 uint32_t Value; 9704 } DW35; 9705 union 9706 { 9707 //!< DWORD 36 9708 struct 9709 { 9710 uint32_t SegmentationIdStreamBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Segmentation ID Stream Base Address [47:32] 9711 uint32_t Reserved1168 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9712 }; 9713 uint32_t Value; 9714 } DW36; 9715 union 9716 { 9717 //!< DWORD 37 9718 struct 9719 { 9720 uint32_t Reserved1184 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 9721 uint32_t CoeffprobabilityStreaminAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< CoeffProbability StreamIn Address - Index to Memory Object Control State (MOCS) Tables 9722 uint32_t SegmentationIdStreamArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9723 uint32_t SegmentationIdStreamMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Segmentation ID Stream - Memory Compression Enable 9724 uint32_t SegmentationIdStreamMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9725 uint32_t Reserved1195 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 9726 uint32_t SegmentationIdStreamTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9727 uint32_t Reserved1199 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9728 }; 9729 uint32_t Value; 9730 } DW37; 9731 9732 //! \name Local enumerations 9733 9734 enum SUB_OPCODE_B 9735 { 9736 SUB_OPCODE_B_MFXVP8PICSTATE = 0, //!< No additional details 9737 }; 9738 9739 enum SUB_OPCODE_A 9740 { 9741 SUB_OPCODE_A_VP8COMMON = 0, //!< No additional details 9742 }; 9743 9744 enum MEDIA_COMMAND_OPCODE 9745 { 9746 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 9747 }; 9748 9749 enum PIPELINE 9750 { 9751 PIPELINE_VIDEOCODEC = 2, //!< No additional details 9752 }; 9753 9754 enum COMMAND_TYPE 9755 { 9756 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9757 }; 9758 9759 //! \brief MC_FILTER_SELECT 9760 //! \details 9761 //! To specify VP8 Profile of operation. 9762 enum MC_FILTER_SELECT 9763 { 9764 MC_FILTER_SELECT_UNNAMED0 = 0, //!< 6-tap filter (regular filter mode) 9765 MC_FILTER_SELECT_UNNAMED1 = 1, //!< 2-tap bilinear filter (simple profile/version mode) 9766 }; 9767 9768 //! \brief CHROMA_FULL_PIXEL_MC_FILTER_MODE 9769 //! \details 9770 //! To specify VP8 Profile of operation. 9771 enum CHROMA_FULL_PIXEL_MC_FILTER_MODE 9772 { 9773 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED0 = 0, //!< Chroma MC filter operates in sub-pixel mode 9774 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED1 = 1, //!< Chroma MC filter only operates in full pixel position, i.e. no sub-pixel interpolation. 9775 }; 9776 9777 //! \brief DBLKFILTERTYPE 9778 //! \details 9779 //! To specify VP8 Profile of operation. 9780 enum DBLKFILTERTYPE 9781 { 9782 DBLKFILTERTYPE_UNNAMED0 = 0, //!< Use a full feature normal deblocking filter 9783 DBLKFILTERTYPE_UNNAMED1 = 1, //!< Use a simple filter for deblocking 9784 }; 9785 9786 enum SKEYFRAMEFLAG 9787 { 9788 SKEYFRAMEFLAG_NON_KEYFRAMEP_FRAME = 0, //!< No additional details 9789 SKEYFRAMEFLAG_KEYFRAMEI_FRAME = 1, //!< No additional details 9790 }; 9791 9792 //! \brief SEGMENTATION_ID_STREAMOUT_ENABLE 9793 //! \details 9794 //! When 0, no output needed. 9795 enum SEGMENTATION_ID_STREAMOUT_ENABLE 9796 { 9797 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTDISABLED = 0, //!< No additional details 9798 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTENABLED = 1, //!< No additional details 9799 }; 9800 9801 //! \brief SEGMENTATION_ID_STREAMIN_ENABLE 9802 //! \details 9803 //! When 0, no input needed. 9804 enum SEGMENTATION_ID_STREAMIN_ENABLE 9805 { 9806 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINDISABLED = 0, //!< No additional details 9807 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINENABLED = 1, //!< No additional details 9808 }; 9809 9810 enum SEGMENT_ENABLE_FLAG 9811 { 9812 SEGMENT_ENABLE_FLAG_UNNAMED0 = 0, //!< Disable Segmentation processing in the current frame 9813 SEGMENT_ENABLE_FLAG_UNNAMED1 = 1, //!< Enable Segmentation processing in the current frame 9814 }; 9815 9816 enum UPDATE_MBSEGMENT_MAP_FLAG 9817 { 9818 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED0 = 0, //!< Disable segmentation update 9819 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED1 = 1, //!< Enable segmentation update, and to enable reading segment_id for each MB. 9820 }; 9821 9822 //! \brief MB_NOCOEFF_SKIPFLAG 9823 //! \details 9824 //! Frame level control if Skip MB (with no non-zero coefficient) is allowed 9825 //! or not. 9826 enum MB_NOCOEFF_SKIPFLAG 9827 { 9828 MB_NOCOEFF_SKIPFLAG_UNNAMED0 = 0, //!< All MBs will have its MB level signaling mb_skip_coeff forced to 0. That is, no skip of coefficient record in the bitstream (even their values are all 0s) 9829 MB_NOCOEFF_SKIPFLAG_UNNAMED1 = 1, //!< Skip MB is enabled in the per MB record. 9830 }; 9831 9832 enum MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED 9833 { 9834 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED0 = 0, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is disabled. 9835 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED1 = 1, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is enabled. 9836 }; 9837 9838 enum LOG2_NUM_OF_PARTITION 9839 { 9840 LOG2_NUM_OF_PARTITION_1TOKENPARTITION = 0, //!< No additional details 9841 LOG2_NUM_OF_PARTITION_2TOKENPARTITION = 1, //!< No additional details 9842 LOG2_NUM_OF_PARTITION_4TOKENPARTITION = 2, //!< No additional details 9843 LOG2_NUM_OF_PARTITION_8TOKENPARTITION = 3, //!< No additional details 9844 }; 9845 9846 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT0 9847 //! \details 9848 //! There are max 4 segments per frame, each segment can have its own 9849 //! deblocking filter level. When segmentation is disabled, only segment 0 9850 //! parameter is used for the entire frame. 9851 enum DBLKFILTERLEVEL_FOR_SEGMENT0 9852 { 9853 DBLKFILTERLEVEL_FOR_SEGMENT0_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9854 }; 9855 9856 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT1 9857 //! \details 9858 //! There are max 4 segments per frame, each segment can have its own 9859 //! deblocking filter level. When segmentation is disabled, only segment 0 9860 //! parameter is used for the entire frame. 9861 enum DBLKFILTERLEVEL_FOR_SEGMENT1 9862 { 9863 DBLKFILTERLEVEL_FOR_SEGMENT1_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9864 }; 9865 9866 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT2 9867 //! \details 9868 //! There are max 4 segments per frame, each segment can have its own 9869 //! deblocking filter level. When segmentation is disabled, only segment 0 9870 //! parameter is used for the entire frame. 9871 enum DBLKFILTERLEVEL_FOR_SEGMENT2 9872 { 9873 DBLKFILTERLEVEL_FOR_SEGMENT2_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9874 }; 9875 9876 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT3 9877 //! \details 9878 //! There are max 4 segments per frame, each segment can have its own 9879 //! deblocking filter level. When segmentation is disabled, only segment 0 9880 //! parameter is used for the entire frame. 9881 enum DBLKFILTERLEVEL_FOR_SEGMENT3 9882 { 9883 DBLKFILTERLEVEL_FOR_SEGMENT3_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9884 }; 9885 9886 //! \brief COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL 9887 //! \details 9888 //! This field controls the priority of arbitration used in the GAC/GAM 9889 //! pipeline for this surface. 9890 enum COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL 9891 { 9892 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9893 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9894 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9895 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9896 }; 9897 9898 //! \brief COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE 9899 //! \details 9900 //! Distinguishes Vertical from Horizontal compression. Please refer to 9901 //! vol1a 9902 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 9903 //! section for more details. 9904 enum COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE 9905 { 9906 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 9907 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 9908 }; 9909 9910 //! \brief COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE 9911 //! \details 9912 //! <b>For Media Surfaces:</b> 9913 //! This field specifies the tiled resource mode. 9914 enum COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE 9915 { 9916 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 9917 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 9918 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 9919 }; 9920 9921 //! \brief SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9922 //! \details 9923 //! This field controls the priority of arbitration used in the GAC/GAM 9924 //! pipeline for this surface. 9925 enum SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9926 { 9927 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9928 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9929 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9930 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9931 }; 9932 9933 //! \brief SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9934 //! \details 9935 //! Distinguishes Vertical from Horizontal compression. Please refer to 9936 //! vol1a 9937 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 9938 //! section for more details. 9939 enum SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9940 { 9941 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 9942 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 9943 }; 9944 9945 //! \brief SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9946 //! \details 9947 //! <b>For Media Surfaces:</b> 9948 //! This field specifies the tiled resource mode. 9949 enum SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9950 { 9951 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 9952 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 9953 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 9954 }; 9955 9956 //! \name Initializations 9957 9958 //! \brief Explicit member initialization function 9959 MFX_VP8_PIC_STATE_CMD(); 9960 9961 static const size_t dwSize = 38; 9962 static const size_t byteSize = 152; 9963 }; 9964 9965 //! 9966 //! \brief MFX_JPEG_HUFF_TABLE_STATE 9967 //! \details 9968 //! This Huffman table commands contains both DC and AC tables for either 9969 //! luma or chroma. Once a Huffman table has been defined for a particular 9970 //! destination, it replaces the previous tables stored in that destination 9971 //! and shall be used in the remaining Scans of the current image. A Huffman 9972 //! table will be sent to H/W only when it is loaded from bitstream. 9973 //! 9974 struct MFX_JPEG_HUFF_TABLE_STATE_CMD 9975 { 9976 union 9977 { 9978 //!< DWORD 0 9979 struct 9980 { 9981 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 9982 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 9983 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 9984 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 9985 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 9986 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 9987 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 9988 }; 9989 uint32_t Value; 9990 } DW0; 9991 union 9992 { 9993 //!< DWORD 1 9994 struct 9995 { 9996 uint32_t Hufftableid1Bit : __CODEGEN_BITFIELD( 0, 0) ; //!< HUFFTABLEID_1_BIT 9997 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 9998 }; 9999 uint32_t Value; 10000 } DW1; 10001 10002 uint32_t DcBits128BitArray[3]; //!< DC_BITS (12 8-bit array) 10003 10004 10005 uint32_t DcHuffval128BitArray[3]; //!< DC_HUFFVAL (12 8-bit array) 10006 10007 10008 uint32_t AcBits168BitArray[4]; //!< AC_BITS (16 8-bit array) 10009 10010 10011 uint32_t AcHuffval1608BitArray[40]; //!< AC_HUFFVAL (160 8-bit array) 10012 10013 union 10014 { 10015 //!< DWORD 52 10016 struct 10017 { 10018 uint32_t AcHuffval28BitArray : __CODEGEN_BITFIELD( 0, 15) ; //!< AC_HUFFVAL(2-8 bit array) 10019 uint32_t Reserved1680 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10020 }; 10021 uint32_t Value; 10022 } DW52; 10023 10024 //! \name Local enumerations 10025 10026 enum SUBOPCODE_B 10027 { 10028 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 10029 }; 10030 10031 enum SUBOPCODE_A 10032 { 10033 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 10034 }; 10035 10036 enum MEDIA_COMMAND_OPCODE 10037 { 10038 MEDIA_COMMAND_OPCODE_JPEGCOMMON = 7, //!< No additional details 10039 }; 10040 10041 enum PIPELINE 10042 { 10043 PIPELINE_MFXMULTIDW = 2, //!< No additional details 10044 }; 10045 10046 enum COMMAND_TYPE 10047 { 10048 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 10049 }; 10050 10051 //! \brief HUFFTABLEID_1_BIT 10052 //! \details 10053 //! Identifies the huffman table. 10054 enum HUFFTABLEID_1_BIT 10055 { 10056 HUFFTABLEID_1_BIT_Y = 0, //!< Huffman table for Y 10057 }; 10058 10059 //! \name Initializations 10060 10061 //! \brief Explicit member initialization function 10062 MFX_JPEG_HUFF_TABLE_STATE_CMD(); 10063 10064 static const size_t dwSize = 53; 10065 static const size_t byteSize = 212; 10066 }; 10067 10068 //! 10069 //! \brief GRAPHICSADDRESS63_6 10070 //! \details 10071 //! This structure is intended to define the upper bits of the 10072 //! GraphicsAddress, when bits 5:0 are already defined in the referring 10073 //! register. So bit 0 of this structure should correspond to bit 6 of the 10074 //! full GraphicsAddress. 10075 //! 10076 struct GRAPHICSADDRESS63_6_CMD 10077 { 10078 union 10079 { 10080 //!< DWORD 0..1 10081 struct 10082 { 10083 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10084 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD( 6, 47) ; //!< GraphicsAddress47-6 10085 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 10086 }; 10087 uint32_t Value[2]; 10088 } DW0_1; 10089 10090 //! \name Local enumerations 10091 10092 //! \name Initializations 10093 10094 //! \brief Explicit member initialization function 10095 GRAPHICSADDRESS63_6_CMD(); 10096 10097 static const size_t dwSize = 2; 10098 static const size_t byteSize = 8; 10099 }; 10100 10101 //! 10102 //! \brief MFX_PIPE_BUF_ADDR_STATE 10103 //! \details 10104 //! This state command provides the memory base addresses for all row 10105 //! stores, StreamOut buffer and reconstructed picture output buffers 10106 //! required by the MFD or MFC Engine (that are in addition to the row 10107 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 10108 //! reference picture buffers). 10109 //! This is a picture level state command and is common among all codec 10110 //! standards and for both encoder and decoder operating modes. However, 10111 //! some fields may only applicable to a specific codec standard. All Pixel 10112 //! Surfaces (original, reference frame and reconstructed frame) in the 10113 //! Encoder are programmed with the same surface state (NV12 and TileY 10114 //! format), except each has its own frame buffer base address. In the tile 10115 //! format, there is no need to provide buffer offset for each slice; since 10116 //! from each MB address, the hardware can calculated the corresponding 10117 //! memory location within the frame buffer directly. 10118 //! 10119 struct MFX_PIPE_BUF_ADDR_STATE_CMD 10120 { 10121 union 10122 { 10123 //!< DWORD 0 10124 struct 10125 { 10126 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 10127 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 10128 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 10129 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 10130 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMON_OPCODE 10131 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 10132 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 10133 }; 10134 uint32_t Value; 10135 } DW0; 10136 union 10137 { 10138 //!< DWORD 1 10139 struct 10140 { 10141 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10142 uint32_t PreDeblockingDestinationAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Pre Deblocking Destination Address 10143 }; 10144 uint32_t Value; 10145 } DW1; 10146 union 10147 { 10148 //!< DWORD 2 10149 struct 10150 { 10151 uint32_t PreDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Pre Deblocking Destination Address High 10152 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10153 }; 10154 uint32_t Value; 10155 } DW2; 10156 union 10157 { 10158 //!< DWORD 3 10159 struct 10160 { 10161 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10162 uint32_t PreDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10163 uint32_t PreDeblockingMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10164 uint32_t PreDeblockingMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< Pre Deblocking - Memory Compression Type 10165 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10166 uint32_t PreDeblockingTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< PRE_DEBLOCKING__TILED_RESOURCE_MODE 10167 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10168 }; 10169 uint32_t Value; 10170 } DW3; 10171 union 10172 { 10173 //!< DWORD 4 10174 struct 10175 { 10176 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10177 uint32_t PostDeblockingDestinationAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Post Deblocking Destination Address 10178 }; 10179 uint32_t Value; 10180 } DW4; 10181 union 10182 { 10183 //!< DWORD 5 10184 struct 10185 { 10186 uint32_t PostDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Post Deblocking Destination Address High 10187 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10188 }; 10189 uint32_t Value; 10190 } DW5; 10191 union 10192 { 10193 //!< DWORD 6 10194 struct 10195 { 10196 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10197 uint32_t PostDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10198 uint32_t PostDeblockingMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10199 uint32_t PostDeblockingMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< POST_DEBLOCKING__MEMORY_COMPRESSION_TYPE 10200 uint32_t Reserved203 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10201 uint32_t PostDeblockingTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< POST_DEBLOCKING__TILED_RESOURCE_MODE 10202 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10203 }; 10204 uint32_t Value; 10205 } DW6; 10206 union 10207 { 10208 //!< DWORD 7 10209 struct 10210 { 10211 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10212 uint32_t OriginalUncompressedPictureSourceAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Original Uncompressed Picture Source Address 10213 }; 10214 uint32_t Value; 10215 } DW7; 10216 union 10217 { 10218 //!< DWORD 8 10219 struct 10220 { 10221 uint32_t OriginalUncompressedPictureSourceAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Original Uncompressed Picture Source Address High 10222 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10223 }; 10224 uint32_t Value; 10225 } DW8; 10226 union 10227 { 10228 //!< DWORD 9 10229 struct 10230 { 10231 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10232 uint32_t OriginalUncompressedPictureSourceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10233 uint32_t OriginalUncompressedPictureMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10234 uint32_t OriginalUncompressedPictureMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_TYPE 10235 uint32_t Reserved299 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10236 uint32_t OriginalUncompressedPictureTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10237 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10238 }; 10239 uint32_t Value; 10240 } DW9; 10241 union 10242 { 10243 //!< DWORD 10 10244 struct 10245 { 10246 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10247 uint32_t StreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< StreamOut Data Destination Base Address 10248 }; 10249 uint32_t Value; 10250 } DW10; 10251 union 10252 { 10253 //!< DWORD 11 10254 struct 10255 { 10256 uint32_t StreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< StreamOut Data Destination Base Address High 10257 uint32_t Reserved368 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10258 }; 10259 uint32_t Value; 10260 } DW11; 10261 union 10262 { 10263 //!< DWORD 12 10264 struct 10265 { 10266 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10267 uint32_t StreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10268 uint32_t StreamoutDataDestinationMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10269 uint32_t Reserved394 : __CODEGEN_BITFIELD(10, 10) ; //!< STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_TYPE 10270 uint32_t Reserved395 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10271 uint32_t StreamoutDataDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10272 uint32_t Reserved399 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10273 }; 10274 uint32_t Value; 10275 } DW12; 10276 union 10277 { 10278 //!< DWORD 13 10279 struct 10280 { 10281 uint32_t Reserved416 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10282 uint32_t IntraRowStoreScratchBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Intra Row Store Scratch Buffer Base Address 10283 }; 10284 uint32_t Value; 10285 } DW13; 10286 union 10287 { 10288 //!< DWORD 14 10289 struct 10290 { 10291 uint32_t IntraRowStoreScratchBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra Row Store Scratch Buffer Base Address High 10292 uint32_t Reserved464 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10293 }; 10294 uint32_t Value; 10295 } DW14; 10296 union 10297 { 10298 //!< DWORD 15 10299 struct 10300 { 10301 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10302 uint32_t IntraRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10303 uint32_t IntraRowStoreScratchBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10304 uint32_t Reserved490 : __CODEGEN_BITFIELD(10, 10) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_TYPE 10305 uint32_t Reserved491 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 10306 uint32_t IntraRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10307 uint32_t IntraRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10308 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10309 }; 10310 uint32_t Value; 10311 } DW15; 10312 union 10313 { 10314 //!< DWORD 16 10315 struct 10316 { 10317 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10318 uint32_t DeblockingFilterRowStoreScratchBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Deblocking Filter Row Store Scratch Base Address 10319 }; 10320 uint32_t Value; 10321 } DW16; 10322 union 10323 { 10324 //!< DWORD 17 10325 struct 10326 { 10327 uint32_t DeblockingFilterRowStoreScratchBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Deblocking Filter Row Store Scratch Base Address High 10328 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10329 }; 10330 uint32_t Value; 10331 } DW17; 10332 union 10333 { 10334 //!< DWORD 18 10335 struct 10336 { 10337 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10338 uint32_t DeblockingFilterRowStoreScratchArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10339 uint32_t DeblockingFilterRowStoreScratchMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10340 uint32_t Reserved586 : __CODEGEN_BITFIELD(10, 10) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_TYPE 10341 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 10342 uint32_t DeblockingFilterRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10343 uint32_t DeblockingFilterRowStoreTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10344 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10345 }; 10346 uint32_t Value; 10347 } DW18; 10348 10349 mhw_vdbox_mfx_g12_X::GRAPHICSADDRESS63_6_CMD Refpicbaseaddr[16]; //!< RefPicBaseAddr 10350 10351 union 10352 { 10353 //!< DWORD 51 10354 struct 10355 { 10356 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10357 uint32_t ReferencePictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10358 uint32_t Reserved1641 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 10359 uint32_t ReferencePictureTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< REFERENCE_PICTURE__TILED_RESOURCE_MODE 10360 uint32_t Reserved1647 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10361 }; 10362 uint32_t Value; 10363 } DW51; 10364 union 10365 { 10366 //!< DWORD 52 10367 struct 10368 { 10369 uint32_t Reserved1664 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10370 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address 10371 }; 10372 uint32_t Value; 10373 } DW52; 10374 union 10375 { 10376 //!< DWORD 53 10377 struct 10378 { 10379 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address High 10380 uint32_t Reserved1712 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10381 }; 10382 uint32_t Value; 10383 } DW53; 10384 union 10385 { 10386 //!< DWORD 54 10387 struct 10388 { 10389 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10390 uint32_t MacroblockStatusBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10391 uint32_t MacroblockStatusBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10392 uint32_t Reserved1738 : __CODEGEN_BITFIELD(10, 10) ; //!< MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10393 uint32_t Reserved1739 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10394 uint32_t MacroblockStatusBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10395 uint32_t Reserved1743 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10396 }; 10397 uint32_t Value; 10398 } DW54; 10399 union 10400 { 10401 //!< DWORD 55 10402 struct 10403 { 10404 uint32_t Reserved1760 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10405 uint32_t MacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Macroblock ILDB StreamOut Buffer Base Address 10406 }; 10407 uint32_t Value; 10408 } DW55; 10409 union 10410 { 10411 //!< DWORD 56 10412 struct 10413 { 10414 uint32_t MacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock ILDB StreamOut Buffer Base Address High 10415 uint32_t Reserved1808 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10416 }; 10417 uint32_t Value; 10418 } DW56; 10419 union 10420 { 10421 //!< DWORD 57 10422 struct 10423 { 10424 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10425 uint32_t MacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10426 uint32_t MacroblockIldbStreamoutBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10427 uint32_t Reserved1834 : __CODEGEN_BITFIELD(10, 10) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10428 uint32_t Reserved1835 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10429 uint32_t MacroblockIldbStreamoutTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10430 uint32_t Reserved1839 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10431 }; 10432 uint32_t Value; 10433 } DW57; 10434 union 10435 { 10436 //!< DWORD 58 10437 struct 10438 { 10439 uint32_t Reserved1856 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10440 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Second Macroblock ILDB StreamOut Buffer Base Address 10441 }; 10442 uint32_t Value; 10443 } DW58; 10444 union 10445 { 10446 //!< DWORD 59 10447 struct 10448 { 10449 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Second Macroblock ILDB StreamOut Buffer Base Address High 10450 uint32_t Reserved1904 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10451 }; 10452 uint32_t Value; 10453 } DW59; 10454 union 10455 { 10456 //!< DWORD 60 10457 struct 10458 { 10459 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10460 uint32_t SecondMacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Second Macroblock ILDB StreamOut Buffer - Arbitration Priority Control 10461 uint32_t SecondMacroblockIldbStreamoutBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10462 uint32_t Reserved1930 : __CODEGEN_BITFIELD(10, 10) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10463 uint32_t Reserved1931 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10464 uint32_t SecondMacroblockIldbStreamoutBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 10465 uint32_t Reserved1935 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10466 }; 10467 uint32_t Value; 10468 } DW60; 10469 union 10470 { 10471 //!< DWORD 61 10472 struct 10473 { 10474 uint32_t ReferencePicture0MemoryCompressionEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< REFERENCE_PICTURE_0__MEMORY_COMPRESSION_ENABLE 10475 uint32_t ReferencePicture0MemoryCompressionType : __CODEGEN_BITFIELD( 1, 1) ; //!< REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 10476 uint32_t ReferencePicture1MemoryCompressionEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< REFERENCE_PICTURE_1__MEMORY_COMPRESSION_ENABLE 10477 uint32_t ReferencePicture1MemoryCompressionType : __CODEGEN_BITFIELD( 3, 3) ; //!< REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 10478 uint32_t ReferencePicture2MemoryCompressionEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< REFERENCE_PICTURE_2__MEMORY_COMPRESSION_ENABLE 10479 uint32_t ReferencePicture2MemoryCompressionType : __CODEGEN_BITFIELD( 5, 5) ; //!< REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 10480 uint32_t ReferencePicture3MemoryCompressionEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< REFERENCE_PICTURE_3__MEMORY_COMPRESSION_ENABLE 10481 uint32_t ReferencePicture3MemoryCompressionType : __CODEGEN_BITFIELD( 7, 7) ; //!< REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 10482 uint32_t ReferencePicture4MemoryCompressionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< REFERENCE_PICTURE_4__MEMORY_COMPRESSION_ENABLE 10483 uint32_t ReferencePicture4MemoryCompressionType : __CODEGEN_BITFIELD( 9, 9) ; //!< REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 10484 uint32_t ReferencePicture5MemoryCompressionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< REFERENCE_PICTURE_5__MEMORY_COMPRESSION_ENABLE 10485 uint32_t ReferencePicture5MemoryCompressionType : __CODEGEN_BITFIELD(11, 11) ; //!< REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 10486 uint32_t ReferencePicture6MemoryCompressionEnable : __CODEGEN_BITFIELD(12, 12) ; //!< REFERENCE_PICTURE_6__MEMORY_COMPRESSION_ENABLE 10487 uint32_t ReferencePicture6MemoryCompressionType : __CODEGEN_BITFIELD(13, 13) ; //!< REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 10488 uint32_t ReferencePicture7MemoryCompressionEnable : __CODEGEN_BITFIELD(14, 14) ; //!< REFERENCE_PICTURE_7__MEMORY_COMPRESSION_ENABLE 10489 uint32_t ReferencePicture7MemoryCompressionType : __CODEGEN_BITFIELD(15, 15) ; //!< REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 10490 uint32_t ReferencePicture8MemoryCompressionEnable : __CODEGEN_BITFIELD(16, 16) ; //!< REFERENCE_PICTURE_8__MEMORY_COMPRESSION_ENABLE 10491 uint32_t ReferencePicture8MemoryCompressionType : __CODEGEN_BITFIELD(17, 17) ; //!< REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 10492 uint32_t ReferencePicture9MemoryCompressionEnable : __CODEGEN_BITFIELD(18, 18) ; //!< REFERENCE_PICTURE_9__MEMORY_COMPRESSION_ENABLE 10493 uint32_t ReferencePicture9MemoryCompressionType : __CODEGEN_BITFIELD(19, 19) ; //!< REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 10494 uint32_t ReferencePicture10MemoryCompressionEnable : __CODEGEN_BITFIELD(20, 20) ; //!< REFERENCE_PICTURE_10__MEMORY_COMPRESSION_ENABLE 10495 uint32_t ReferencePicture10MemoryCompressionType : __CODEGEN_BITFIELD(21, 21) ; //!< REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 10496 uint32_t ReferencePicture11MemoryCompressionEnable : __CODEGEN_BITFIELD(22, 22) ; //!< REFERENCE_PICTURE_11__MEMORY_COMPRESSION_ENABLE 10497 uint32_t ReferencePicture11MemoryCompressionType : __CODEGEN_BITFIELD(23, 23) ; //!< REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 10498 uint32_t ReferencePicture12MemoryCompressionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< REFERENCE_PICTURE_12__MEMORY_COMPRESSION_ENABLE 10499 uint32_t ReferencePicture12MemoryCompressionType : __CODEGEN_BITFIELD(25, 25) ; //!< REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 10500 uint32_t ReferencePicture13MemoryCompressionEnable : __CODEGEN_BITFIELD(26, 26) ; //!< REFERENCE_PICTURE_13__MEMORY_COMPRESSION_ENABLE 10501 uint32_t ReferencePicture13MemoryCompressionType : __CODEGEN_BITFIELD(27, 27) ; //!< REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 10502 uint32_t ReferencePicture14MemoryCompressionEnable : __CODEGEN_BITFIELD(28, 28) ; //!< REFERENCE_PICTURE_14__MEMORY_COMPRESSION_ENABLE 10503 uint32_t ReferencePicture14MemoryCompressionType : __CODEGEN_BITFIELD(29, 29) ; //!< REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 10504 uint32_t ReferencePicture15MemoryCompressionEnable : __CODEGEN_BITFIELD(30, 30) ; //!< REFERENCE_PICTURE_15__MEMORY_COMPRESSION_ENABLE 10505 uint32_t ReferencePicture15MemoryCompressionType : __CODEGEN_BITFIELD(31, 31) ; //!< REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 10506 }; 10507 uint32_t Value; 10508 } DW61; 10509 union 10510 { 10511 //!< DWORD 62 10512 struct 10513 { 10514 uint32_t Reserved1984 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10515 uint32_t ScaledReferenceSurfaceBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Scaled Reference Surface Base Address 10516 }; 10517 uint32_t Value; 10518 } DW62; 10519 union 10520 { 10521 //!< DWORD 63 10522 struct 10523 { 10524 uint32_t ScaledReferenceSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Scaled Reference Surface Base Address High 10525 uint32_t Reserved2032 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10526 }; 10527 uint32_t Value; 10528 } DW63; 10529 union 10530 { 10531 //!< DWORD 64 10532 struct 10533 { 10534 uint32_t Reserved2048 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 10535 uint32_t ScaledReferenceSurfaceIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Scaled Reference Surface - Index to Memory Object Control State (MOCS) Tables 10536 uint32_t ScaleReferenceSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 10537 uint32_t ScaledReferenceSurfaceMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Scaled Reference Surface - Memory Compression Enable 10538 uint32_t ScaledReferenceSurfaceMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 10539 uint32_t Reserved2059 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10540 uint32_t ScaledReferenceSurfaceTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 10541 uint32_t Reserved2063 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10542 }; 10543 uint32_t Value; 10544 } DW64; 10545 union 10546 { 10547 //!< DWORD 65 10548 struct 10549 { 10550 uint32_t Reserved2080 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10551 uint32_t SlicesizeStreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< SliceSize StreamOut Data Destination Base Address 10552 }; 10553 uint32_t Value; 10554 } DW65; 10555 union 10556 { 10557 //!< DWORD 66 10558 struct 10559 { 10560 uint32_t SlicesizeStreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SliceSize StreamOut Data Destination Base Address High 10561 uint32_t Reserved2128 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10562 }; 10563 uint32_t Value; 10564 } DW66; 10565 union 10566 { 10567 //!< DWORD 67 10568 struct 10569 { 10570 uint32_t Reserved2144 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 10571 uint32_t SlicesizeStreamoutDataDestinationIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SliceSize StreamOut Data Destination - Index to Memory Object Control State (MOCS) Tables 10572 uint32_t SlicesizeStreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SLICESIZE_STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10573 uint32_t SlicesizeStreamoutDataDestinationMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SliceSize StreamOut Data Destination - Memory Compression Enable 10574 uint32_t Reserved2154 : __CODEGEN_BITFIELD(10, 10) ; //!< SLICESIZE_STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10575 uint32_t Reserved2155 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10576 uint32_t SlicesizeStreamoutDataDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SLICESIZE_STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10577 uint32_t Reserved2159 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10578 }; 10579 uint32_t Value; 10580 } DW67; 10581 10582 //! \name Local enumerations 10583 10584 enum SUBOPCODE_B 10585 { 10586 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 10587 }; 10588 10589 enum SUBOPCODE_A 10590 { 10591 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 10592 }; 10593 10594 enum COMMON_OPCODE 10595 { 10596 COMMON_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 10597 }; 10598 10599 enum PIPELINE 10600 { 10601 PIPELINE_MFXPIPEBUFADDRSTATE = 2, //!< No additional details 10602 }; 10603 10604 enum COMMAND_TYPE 10605 { 10606 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 10607 }; 10608 10609 //! \brief PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10610 //! \details 10611 //! This field controls the priority of arbitration used in the GAC/GAM 10612 //! pipeline for this surface. 10613 enum PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10614 { 10615 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10616 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10617 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10618 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10619 }; 10620 10621 //! \brief PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10622 //! \details 10623 //! Memory compression will be attempted for this surface. 10624 enum PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10625 { 10626 PRE_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10627 PRE_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10628 }; 10629 10630 //! \brief PRE_DEBLOCKING__TILED_RESOURCE_MODE 10631 //! \details 10632 //! <b>For Media Surfaces:</b> 10633 //! This field specifies the tiled resource mode. 10634 enum PRE_DEBLOCKING__TILED_RESOURCE_MODE 10635 { 10636 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10637 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10638 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10639 }; 10640 10641 //! \brief POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10642 //! \details 10643 //! This field controls the priority of arbitration used in the GAC/GAM 10644 //! pipeline for this surface. 10645 enum POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10646 { 10647 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10648 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10649 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10650 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10651 }; 10652 10653 //! \brief POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10654 //! \details 10655 //! Memory compression will be attempted for this surface. 10656 enum POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10657 { 10658 POST_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10659 POST_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10660 }; 10661 10662 //! \brief POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10663 //! \details 10664 //! Distinguishes Vertical from Horizontal compression. Please refer to 10665 //! vol1a <b>Memory Data Formats chapter -section</b> Media Memory 10666 //! Compression <b>for more details.</b> 10667 enum POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10668 { 10669 POST_DEBLOCKING_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10670 }; 10671 10672 //! \brief POST_DEBLOCKING__TILED_RESOURCE_MODE 10673 //! \details 10674 //! <b>For Media Surfaces:</b> 10675 //! This field specifies the tiled resource mode. 10676 enum POST_DEBLOCKING__TILED_RESOURCE_MODE 10677 { 10678 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10679 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10680 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10681 }; 10682 10683 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10684 //! \details 10685 //! This field controls the priority of arbitration used in the GAC/GAM 10686 //! pipeline for this surface. 10687 enum ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10688 { 10689 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10690 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10691 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10692 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10693 }; 10694 10695 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10696 //! \details 10697 //! Note: This is a READ Surface. The setting of this bit should match the 10698 //! settings on how this is written out before. 10699 enum ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10700 { 10701 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10702 }; 10703 10704 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10705 //! \details 10706 //! Distinguishes Vertical from Horizontal compression. Please refer to 10707 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10708 //! more details. Note: This bit is not used unless Memory Compression 10709 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10710 //! bit should match the settings on how this is written out before 10711 enum ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10712 { 10713 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10714 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10715 }; 10716 10717 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10718 //! \details 10719 //! <b>For Media Surfaces:</b> 10720 //! This field specifies the tiled resource mode. 10721 enum ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10722 { 10723 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10724 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10725 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10726 }; 10727 10728 //! \brief STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10729 //! \details 10730 //! This field controls the priority of arbitration used in the GAC/GAM 10731 //! pipeline for this surface. 10732 enum STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10733 { 10734 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10735 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10736 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10737 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10738 }; 10739 10740 //! \brief STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10741 //! \details 10742 //! Note: This is a READ Surface. The setting of this bit should match the 10743 //! settings on how this is written out before. 10744 enum STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10745 { 10746 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10747 }; 10748 10749 //! \brief STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10750 //! \details 10751 //! Distinguishes Vertical from Horizontal compression. Please refer to 10752 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10753 //! more details. Note: This bit is not used unless Memory Compression 10754 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10755 //! bit should match the settings on how this is written out before 10756 enum STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10757 { 10758 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10759 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10760 }; 10761 10762 //! \brief STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10763 //! \details 10764 //! <b>For Media Surfaces:</b> 10765 //! This field specifies the tiled resource mode. 10766 enum STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10767 { 10768 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10769 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10770 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10771 }; 10772 10773 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10774 //! \details 10775 //! This field controls the priority of arbitration used in the GAC/GAM 10776 //! pipeline for this surface. 10777 enum INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10778 { 10779 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10780 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10781 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10782 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10783 }; 10784 10785 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10786 //! \details 10787 //! This surface is linear surface. This bit must be set to "0" since only 10788 //! TileY/TileYf/TileYs surface is allowed to be compressed 10789 enum INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10790 { 10791 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10792 }; 10793 10794 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10795 //! \details 10796 //! Distinguishes Vertical from Horizontal compression. Please refer to 10797 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10798 //! more details. Note: This bit is not used unless Memory Compression 10799 //! Enable is set to "1" 10800 enum INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10801 { 10802 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10803 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10804 }; 10805 10806 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10807 //! \details 10808 //! This field controls if Intra Row Store is going to store inside Media 10809 //! Cache or to LLC. 10810 enum INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10811 { 10812 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 10813 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 10814 }; 10815 10816 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10817 //! \details 10818 //! <b>For Media Surfaces:</b> 10819 //! This field specifies the tiled resource mode. 10820 enum INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10821 { 10822 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10823 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10824 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10825 }; 10826 10827 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10828 //! \details 10829 //! This field controls the priority of arbitration used in the GAC/GAM 10830 //! pipeline for this surface. 10831 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10832 { 10833 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10834 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10835 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10836 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10837 }; 10838 10839 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10840 //! \details 10841 //! This surface is linear surface. This bit must be set to "0" since only 10842 //! TileY/TileYf/TileYs surface is allowed to be compressed 10843 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10844 { 10845 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10846 }; 10847 10848 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10849 //! \details 10850 //! Distinguishes Vertical from Horizontal compression. Please refer to 10851 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10852 //! more details. Note: This bit is not used unless Memory Compression 10853 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10854 //! bit should match the settings on how this is written out before. 10855 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10856 { 10857 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10858 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10859 }; 10860 10861 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10862 //! \details 10863 //! This field controls if Intra Row Store is going to store inside Media 10864 //! Internal Storage or to LLC. 10865 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10866 { 10867 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 10868 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Media Internal Storage 10869 }; 10870 10871 //! \brief DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10872 //! \details 10873 //! <b>For Media Surfaces:</b> 10874 //! This field specifies the tiled resource mode. 10875 enum DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10876 { 10877 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10878 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10879 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10880 }; 10881 10882 //! \brief REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10883 //! \details 10884 //! This field controls the priority of arbitration used in the GAC/GAM 10885 //! pipeline for this surface. 10886 enum REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10887 { 10888 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10889 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10890 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10891 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10892 }; 10893 10894 //! \brief REFERENCE_PICTURE__TILED_RESOURCE_MODE 10895 //! \details 10896 //! <b>For Media Surfaces:</b> 10897 //! This field specifies the tiled resource mode. 10898 enum REFERENCE_PICTURE__TILED_RESOURCE_MODE 10899 { 10900 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10901 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10902 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10903 }; 10904 10905 //! \brief MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10906 //! \details 10907 //! This field controls the priority of arbitration used in the GAC/GAM 10908 //! pipeline for this surface. 10909 enum MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10910 { 10911 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10912 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10913 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10914 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10915 }; 10916 10917 //! \brief MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10918 //! \details 10919 //! This surface is linear surface. This bit must be set to "0" since only 10920 //! TileY/TileYf/TileYs surface is allowed to be compressed 10921 enum MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10922 { 10923 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10924 }; 10925 10926 //! \brief MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10927 //! \details 10928 //! Distinguishes Vertical from Horizontal compression. Please refer to 10929 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10930 //! more details. Note: This bit is not used unless Memory Compression 10931 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10932 //! bit should match the settings on how this is written out before. 10933 enum MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10934 { 10935 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10936 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10937 }; 10938 10939 //! \brief MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10940 //! \details 10941 //! <b>For Media Surfaces:</b> 10942 //! This field specifies the tiled resource mode. 10943 enum MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10944 { 10945 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10946 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10947 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10948 }; 10949 10950 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10951 //! \details 10952 //! This field controls the priority of arbitration used in the GAC/GAM 10953 //! pipeline for this surface. 10954 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10955 { 10956 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10957 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10958 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10959 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10960 }; 10961 10962 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10963 //! \details 10964 //! This surface is linear surface. This bit must be set to "0" since only 10965 //! TileY/TileYf/TileYs surface is allowed to be compressed 10966 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10967 { 10968 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10969 }; 10970 10971 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10972 //! \details 10973 //! Distinguishes Vertical from Horizontal compression. Please refer to 10974 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10975 //! more details. Note: This bit is not used unless Memory Compression 10976 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10977 //! bit should match the settings on how this is written out before. 10978 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10979 { 10980 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10981 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10982 }; 10983 10984 //! \brief MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10985 //! \details 10986 //! <b>For Media Surfaces:</b> 10987 //! This field specifies the tiled resource mode. 10988 enum MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10989 { 10990 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10991 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10992 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10993 }; 10994 10995 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10996 //! \details 10997 //! This surface is linear surface. This bit must be set to "0" since only 10998 //! TileY/TileYf/TileYs surface is allowed to be compressed 10999 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 11000 { 11001 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11002 }; 11003 11004 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 11005 //! \details 11006 //! Distinguishes Vertical from Horizontal compression. Please refer to 11007 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11008 //! more details. Note: This bit is not used unless Memory Compression 11009 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11010 //! bit should match the settings on how this is written out before. 11011 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 11012 { 11013 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11014 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11015 }; 11016 11017 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 11018 //! \details 11019 //! <b>For Media Surfaces:</b> 11020 //! This field specifies the tiled resource mode. 11021 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 11022 { 11023 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11024 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11025 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11026 }; 11027 11028 enum REFERENCE_PICTURE_0__MEMORY_COMPRESSION_ENABLE 11029 { 11030 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11031 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11032 }; 11033 11034 //! \brief REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 11035 //! \details 11036 //! Distinguishes Vertical from Horizontal compression. Please refer to 11037 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11038 //! more details. Note: This bit is not used unless Memory Compression 11039 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11040 //! bit should match the settings on how this is written out before. 11041 enum REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 11042 { 11043 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11044 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11045 }; 11046 11047 enum REFERENCE_PICTURE_1__MEMORY_COMPRESSION_ENABLE 11048 { 11049 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11050 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11051 }; 11052 11053 //! \brief REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 11054 //! \details 11055 //! Distinguishes Vertical from Horizontal compression. Please refer to 11056 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11057 //! more details. Note: This bit is not used unless Memory Compression 11058 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11059 //! bit should match the settings on how this is written out before. 11060 enum REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 11061 { 11062 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11063 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11064 }; 11065 11066 enum REFERENCE_PICTURE_2__MEMORY_COMPRESSION_ENABLE 11067 { 11068 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11069 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11070 }; 11071 11072 //! \brief REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 11073 //! \details 11074 //! Distinguishes Vertical from Horizontal compression. Please refer to 11075 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11076 //! more details. Note: This bit is not used unless Memory Compression 11077 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11078 //! bit should match the settings on how this is written out before. 11079 enum REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 11080 { 11081 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11082 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11083 }; 11084 11085 enum REFERENCE_PICTURE_3__MEMORY_COMPRESSION_ENABLE 11086 { 11087 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11088 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11089 }; 11090 11091 //! \brief REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 11092 //! \details 11093 //! Distinguishes Vertical from Horizontal compression. Please refer to 11094 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11095 //! more details. Note: This bit is not used unless Memory Compression 11096 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11097 //! bit should match the settings on how this is written out before. 11098 enum REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 11099 { 11100 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11101 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11102 }; 11103 11104 enum REFERENCE_PICTURE_4__MEMORY_COMPRESSION_ENABLE 11105 { 11106 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11107 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11108 }; 11109 11110 //! \brief REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 11111 //! \details 11112 //! Distinguishes Vertical from Horizontal compression. Please refer to 11113 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11114 //! more details. Note: This bit is not used unless Memory Compression 11115 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11116 //! bit should match the settings on how this is written out before. 11117 enum REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 11118 { 11119 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11120 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11121 }; 11122 11123 enum REFERENCE_PICTURE_5__MEMORY_COMPRESSION_ENABLE 11124 { 11125 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11126 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11127 }; 11128 11129 //! \brief REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 11130 //! \details 11131 //! Distinguishes Vertical from Horizontal compression. Please refer to 11132 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11133 //! more details. Note: This bit is not used unless Memory Compression 11134 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11135 //! bit should match the settings on how this is written out before. 11136 enum REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 11137 { 11138 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11139 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11140 }; 11141 11142 enum REFERENCE_PICTURE_6__MEMORY_COMPRESSION_ENABLE 11143 { 11144 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11145 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11146 }; 11147 11148 //! \brief REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 11149 //! \details 11150 //! Distinguishes Vertical from Horizontal compression. Please refer to 11151 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11152 //! more details. Note: This bit is not used unless Memory Compression 11153 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11154 //! bit should match the settings on how this is written out before. 11155 enum REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 11156 { 11157 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11158 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11159 }; 11160 11161 enum REFERENCE_PICTURE_7__MEMORY_COMPRESSION_ENABLE 11162 { 11163 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11164 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11165 }; 11166 11167 //! \brief REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 11168 //! \details 11169 //! Distinguishes Vertical from Horizontal compression. Please refer to 11170 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11171 //! more details. Note: This bit is not used unless Memory Compression 11172 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11173 //! bit should match the settings on how this is written out before. 11174 enum REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 11175 { 11176 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11177 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11178 }; 11179 11180 enum REFERENCE_PICTURE_8__MEMORY_COMPRESSION_ENABLE 11181 { 11182 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11183 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11184 }; 11185 11186 //! \brief REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 11187 //! \details 11188 //! Distinguishes Vertical from Horizontal compression. Please refer to 11189 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11190 //! more details. Note: This bit is not used unless Memory Compression 11191 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11192 //! bit should match the settings on how this is written out before. 11193 enum REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 11194 { 11195 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11196 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11197 }; 11198 11199 enum REFERENCE_PICTURE_9__MEMORY_COMPRESSION_ENABLE 11200 { 11201 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11202 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11203 }; 11204 11205 //! \brief REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 11206 //! \details 11207 //! Distinguishes Vertical from Horizontal compression. Please refer to 11208 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11209 //! more details. Note: This bit is not used unless Memory Compression 11210 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11211 //! bit should match the settings on how this is written out before. 11212 enum REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 11213 { 11214 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11215 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11216 }; 11217 11218 enum REFERENCE_PICTURE_10__MEMORY_COMPRESSION_ENABLE 11219 { 11220 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11221 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11222 }; 11223 11224 //! \brief REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 11225 //! \details 11226 //! Distinguishes Vertical from Horizontal compression. Please refer to 11227 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11228 //! more details. Note: This bit is not used unless Memory Compression 11229 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11230 //! bit should match the settings on how this is written out before. 11231 enum REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 11232 { 11233 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11234 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11235 }; 11236 11237 enum REFERENCE_PICTURE_11__MEMORY_COMPRESSION_ENABLE 11238 { 11239 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11240 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11241 }; 11242 11243 //! \brief REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 11244 //! \details 11245 //! Distinguishes Vertical from Horizontal compression. Please refer to 11246 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11247 //! more details. 11248 //! Note: This bit is not used unless Memory Compression Enable is set 11249 //! to "1" 11250 //! Note: This is a READ Surface. The setting of this bit should 11251 //! match the settings on how this is written out before. 11252 enum REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 11253 { 11254 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11255 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11256 }; 11257 11258 enum REFERENCE_PICTURE_12__MEMORY_COMPRESSION_ENABLE 11259 { 11260 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11261 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11262 }; 11263 11264 //! \brief REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 11265 //! \details 11266 //! Distinguishes Vertical from Horizontal compression. Please refer to 11267 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11268 //! more details. Note: This bit is not used unless Memory Compression 11269 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11270 //! bit should match the settings on how this is written out before. 11271 enum REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 11272 { 11273 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11274 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11275 }; 11276 11277 enum REFERENCE_PICTURE_13__MEMORY_COMPRESSION_ENABLE 11278 { 11279 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11280 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11281 }; 11282 11283 //! \brief REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 11284 //! \details 11285 //! Distinguishes Vertical from Horizontal compression. Please refer to 11286 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11287 //! more details. Note: This bit is not used unless Memory Compression 11288 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11289 //! bit should match the settings on how this is written out before. 11290 enum REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 11291 { 11292 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11293 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11294 }; 11295 11296 enum REFERENCE_PICTURE_14__MEMORY_COMPRESSION_ENABLE 11297 { 11298 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11299 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11300 }; 11301 11302 //! \brief REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 11303 //! \details 11304 //! Distinguishes Vertical from Horizontal compression. Please refer to 11305 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11306 //! more details. Note: This bit is not used unless Memory Compression 11307 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11308 //! bit should match the settings on how this is written out before. 11309 enum REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 11310 { 11311 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11312 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11313 }; 11314 11315 enum REFERENCE_PICTURE_15__MEMORY_COMPRESSION_ENABLE 11316 { 11317 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11318 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11319 }; 11320 11321 //! \brief REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 11322 //! \details 11323 //! Distinguishes Vertical from Horizontal compression. Please refer to 11324 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11325 //! more details. Note: This bit is not used unless Memory Compression 11326 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11327 //! bit should match the settings on how this is written out before. 11328 enum REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 11329 { 11330 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11331 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11332 }; 11333 11334 //! \brief SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 11335 //! \details 11336 //! This field controls the priority of arbitration used in the GAC/GAM 11337 //! pipeline for this surface. 11338 enum SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 11339 { 11340 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11341 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11342 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11343 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11344 }; 11345 11346 //! \brief SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 11347 //! \details 11348 //! Distinguishes Vertical from Horizontal compression. Please refer to 11349 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11350 //! more details. 11351 enum SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 11352 { 11353 SCALED_REFERENCE_SURFACE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11354 SCALED_REFERENCE_SURFACE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11355 }; 11356 11357 //! \brief SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 11358 //! \details 11359 //! For Media Surfaces: 11360 //! This field specifies the tiled resource mode 11361 enum SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 11362 { 11363 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11364 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< No tiled resource 11365 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< No tiled resource 11366 }; 11367 11368 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 11369 //! \details 11370 //! This field controls the priority of arbitration used in the GAC/GAM 11371 //! pipeline for this surface. 11372 enum SLICESIZE_STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 11373 { 11374 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11375 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11376 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11377 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11378 }; 11379 11380 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 11381 //! \details 11382 //! Distinguishes Vertical from Horizontal compression. Please refer to 11383 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11384 //! more details. 11385 enum SLICESIZE_STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 11386 { 11387 SLICESIZE_STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11388 SLICESIZE_STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11389 }; 11390 11391 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 11392 //! \details 11393 //! For Media Surfaces: This Surface is never tiled. 11394 enum SLICESIZE_STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 11395 { 11396 SLICESIZE_STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11397 SLICESIZE_STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< No tiled resource 11398 SLICESIZE_STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< No tiled resource 11399 }; 11400 11401 //! \name Initializations 11402 11403 //! \brief Explicit member initialization function 11404 MFX_PIPE_BUF_ADDR_STATE_CMD(); 11405 11406 static const size_t dwSize = 68; 11407 static const size_t byteSize = 272; 11408 }; 11409 11410 //! 11411 //! \brief MFX_AVC_DIRECTMODE_STATE 11412 //! \details 11413 //! This is a picture level command and is issued once per picture. All DMV 11414 //! buffers are treated as standard media surfaces, in which the lower 6 11415 //! bits are used for conveying surface states.Current Pic POC number is 11416 //! assumed to be available in POCList[32 and 33] of the 11417 //! MFX_AVC_DIRECTMODE_STATE Command.This command is only valid in the AVC 11418 //! decoding in VLD and IT modes, and AVC encoder mode. The same command 11419 //! supports both Long and Short AVC Interface. The DMV buffers are 11420 //! not required to be programmed for encoder mode. 11421 //! 11422 struct MFX_AVC_DIRECTMODE_STATE_CMD 11423 { 11424 union 11425 { 11426 //!< DWORD 0 11427 struct 11428 { 11429 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 11430 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 11431 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 11432 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 11433 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 11434 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 11435 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 11436 }; 11437 uint32_t Value; 11438 } DW0; 11439 11440 mhw_vdbox_mfx_g12_X::GRAPHICSADDRESS63_6_CMD DirectMvBufferBaseAddress[16]; //!< Direct MV Buffer Base Address 11441 11442 union 11443 { 11444 //!< DWORD 33 11445 struct 11446 { 11447 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 11448 uint32_t DirectMvBufferBaseAddressForReferenceFrameArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11449 uint32_t DirectMvBufferBaseAddressForReferenceFrameMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11450 uint32_t DirectMvBufferBaseAddressForReferenceFrameMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11451 uint32_t Reserved1067 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 11452 uint32_t DirectMvBufferBaseAddressForReferenceFrameTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11453 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 11454 }; 11455 uint32_t Value; 11456 } DW33; 11457 11458 mhw_vdbox_mfx_g12_X::GRAPHICSADDRESS63_6_CMD DirectMvBufferBaseAddressForWrite[1]; //!< Direct MV Buffer Base Address for Write 11459 11460 union 11461 { 11462 //!< DWORD 36 11463 struct 11464 { 11465 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 11466 uint32_t DirectMvBufferBaseAddressForWriteArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11467 uint32_t DirectMvBufferBaseAddressForWriteMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11468 uint32_t DirectMvBufferBaseAddressForWriteMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11469 uint32_t Reserved1163 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 11470 uint32_t DirectMvBufferBaseAddressForWriteTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11471 uint32_t Reserved1167 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 11472 }; 11473 uint32_t Value; 11474 } DW36; 11475 11476 uint32_t PocList[34]; //!< POC List 11477 11478 11479 //! \name Local enumerations 11480 11481 enum SUBOPCODEB 11482 { 11483 SUBOPCODEB_UNNAMED2 = 2, //!< No additional details 11484 }; 11485 11486 enum SUBOPCODEA 11487 { 11488 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 11489 }; 11490 11491 enum MEDIA_COMMAND_OPCODE 11492 { 11493 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 11494 }; 11495 11496 enum PIPELINE 11497 { 11498 PIPELINE_MFXSINGLEDW = 2, //!< No additional details 11499 }; 11500 11501 enum COMMAND_TYPE 11502 { 11503 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 11504 }; 11505 11506 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11507 //! \details 11508 //! This field controls the priority of arbitration used in the GAC/GAM 11509 //! pipeline for this surface. 11510 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11511 { 11512 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11513 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11514 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11515 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11516 }; 11517 11518 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11519 //! \details 11520 //! This surface is linear surface. This bit must be set to "0" since only 11521 //! TileY/TileYf/TileYs surface is allowed to be compressed 11522 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11523 { 11524 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11525 }; 11526 11527 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11528 //! \details 11529 //! Distinguishes Vertical from Horizontal compression. Please refer to 11530 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11531 //! more details. 11532 //! Note: This bit is not used unless Memory Compression Enable is set 11533 //! to "1" 11534 //! Note: This is a READ Surface. The setting of this bit should 11535 //! match the settings on how this is written out before. 11536 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11537 { 11538 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11539 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11540 }; 11541 11542 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11543 //! \details 11544 //! <b>For Media Surfaces:</b> 11545 //! This field specifies the tiled resource mode. 11546 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11547 { 11548 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11549 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11550 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11551 }; 11552 11553 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11554 //! \details 11555 //! This field controls the priority of arbitration used in the GAC/GAM 11556 //! pipeline for this surface. 11557 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11558 { 11559 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11560 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11561 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11562 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11563 }; 11564 11565 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11566 //! \details 11567 //! This surface is linear surface. This bit must be set to "0" since only 11568 //! TileY/TileYf/TileYs surface is allowed to be compressed 11569 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11570 { 11571 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11572 }; 11573 11574 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11575 //! \details 11576 //! Distinguishes Vertical from Horizontal compression. Please refer to 11577 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11578 //! more details. 11579 //! Note: This bit is not used unless Memory Compression Enable is set 11580 //! to "1" 11581 //! Note: This is a READ Surface. The setting of this bit should 11582 //! match the settings on how this is written out before. 11583 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11584 { 11585 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11586 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11587 }; 11588 11589 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11590 //! \details 11591 //! <b>For Media Surfaces:</b> 11592 //! This field specifies the tiled resource mode. 11593 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11594 { 11595 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11596 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11597 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11598 }; 11599 11600 //! \name Initializations 11601 11602 //! \brief Explicit member initialization function 11603 MFX_AVC_DIRECTMODE_STATE_CMD(); 11604 11605 static const size_t dwSize = 71; 11606 static const size_t byteSize = 284; 11607 }; 11608 11609 }; 11610 11611 #pragma pack() 11612 11613 #endif // __MHW_VDBOX_MFX_HWCMD_G12_X_H__