1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_mfx_hwcmd_g11_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g11_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_VDBOX_MFX_HWCMD_G11_X_H__ 29 #define __MHW_VDBOX_MFX_HWCMD_G11_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_vdbox_mfx_g11_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH( x ) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MFX_QM_STATE 50 //! \details 51 //! This is a common state command for AVC encoder modes. For encoder, it 52 //! represents both the forward QM matrices as well as the decoding QM 53 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 54 //! application are being sent to the hardware. The driver is responsible 55 //! for determining the final set of scaling lists to be used for decoding 56 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 57 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 58 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 59 //! order. But the Forward Q scaling lists are sent in column-wise raster 60 //! order (column-by-column) to simplify the H/W. Driver will perform all 61 //! the scan order conversion for both ForwardQ and IQ. 62 //! 63 struct MFX_QM_STATE_CMD 64 { 65 union 66 { 67 //!< DWORD 0 68 struct 69 { 70 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 71 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 72 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 73 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 74 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 75 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 76 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 77 }; 78 uint32_t Value; 79 } DW0; 80 union 81 { 82 //!< DWORD 1 83 struct 84 { 85 uint32_t Avc : __CODEGEN_BITFIELD( 0, 1) ; //!< AVC, AVC- Decoder Only 86 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, AVC- Decoder Only 87 } Obj0; 88 struct 89 { 90 uint32_t Mpeg2 : __CODEGEN_BITFIELD( 0, 1) ; //!< MPEG2, MPEG2- Decoder Only 91 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, MPEG2- Decoder Only 92 } Obj1; 93 struct 94 { 95 uint32_t Jpeg : __CODEGEN_BITFIELD( 0, 1) ; //!< JPEG, JPEG- Encoder Only 96 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 97 }Obj2; 98 uint32_t Value; 99 } DW1; 100 101 uint32_t ForwardQuantizerMatrix[16]; //!< Forward Quantizer Matrix 102 103 104 //! \name Local enumerations 105 106 enum SUBOPCODE_B 107 { 108 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 109 }; 110 111 enum SUBOPCODE_A 112 { 113 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 114 }; 115 116 enum MEDIA_COMMAND_OPCODE 117 { 118 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 119 }; 120 121 enum PIPELINE 122 { 123 PIPELINE_MFXMULTIDW = 2, //!< No additional details 124 }; 125 126 enum COMMAND_TYPE 127 { 128 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 129 }; 130 131 //! \brief AVC 132 //! \details 133 //! <b>For AVC QM Type</b>: This field specifies which Quantizer Matrix is 134 //! loaded. 135 enum AVC 136 { 137 AVC_AVC_4X_4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 138 AVC_AVC_4X_4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 139 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 140 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 141 }; 142 143 //! \brief MPEG2 144 //! \details 145 //! <b>For MPEG2 QM Type</b>: This field specifies which Quantizer Matrix is 146 //! loaded. 147 enum MPEG2 148 { 149 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 150 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 151 }; 152 153 //! \brief JPEG 154 //! \details 155 //! <b> For JPEG QM Type</b>:This field specifies which Quantizer Matrix is 156 //! loaded. 157 enum JPEG 158 { 159 JPEG_JPEGLUMAYQUANTIZERMATRIXORR = 0, //!< No additional details 160 JPEG_JPEGCHROMACBQUANTIZERMATRIXORG = 1, //!< No additional details 161 JPEG_JPEGCHROMACRQUANTIZERMATRIXORB = 2, //!< No additional details 162 }; 163 164 //! \name Initializations 165 166 //! \brief Explicit member initialization function 167 MFX_QM_STATE_CMD(); 168 169 static const size_t dwSize = 18; 170 static const size_t byteSize = 72; 171 }; 172 173 //! 174 //! \brief MFX_FQM_STATE 175 //! \details 176 //! This is a common state command for AVC encoder modes. For encoder, it 177 //! represents both the forward QM matrices as well as the decoding QM 178 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 179 //! application are being sent to the hardware. The driver is responsible 180 //! for determining the final set of scaling lists to be used for decoding 181 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 182 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 183 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 184 //! order. But the Forward Q scaling lists are sent in column-wise raster 185 //! order (column-by-column) to simplify the H/W. Driver will perform all 186 //! the scan order conversion for both ForwardQ and IQ. 187 //! 188 struct MFX_FQM_STATE_CMD 189 { 190 union 191 { 192 //!< DWORD 0 193 struct 194 { 195 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 196 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 197 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 198 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 199 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 200 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 201 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 202 }; 203 uint32_t Value; 204 } DW0; 205 union 206 { 207 //!< DWORD 1 208 struct 209 { 210 uint32_t Avc : __CODEGEN_BITFIELD( 0, 1) ; //!< AVC, AVC- Decoder Only 211 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, AVC- Decoder Only 212 } Obj0; 213 struct 214 { 215 uint32_t Mpeg2 : __CODEGEN_BITFIELD( 0, 1) ; //!< MPEG2, MPEG2- Decoder Only 216 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, MPEG2- Decoder Only 217 } Obj1; 218 struct 219 { 220 uint32_t Jpeg : __CODEGEN_BITFIELD( 0, 1) ; //!< JPEG, JPEG- Encoder Only 221 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 222 }Obj2; 223 uint32_t Value; 224 } DW1; 225 226 uint32_t ForwardQuantizerMatrix[32]; //!< Forward Quantizer Matrix 227 228 229 //! \name Local enumerations 230 231 enum SUBOPCODE_B 232 { 233 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 234 }; 235 236 enum SUBOPCODE_A 237 { 238 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 239 }; 240 241 enum MEDIA_COMMAND_OPCODE 242 { 243 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 244 }; 245 246 enum PIPELINE 247 { 248 PIPELINE_MFXMULTIDW = 2, //!< No additional details 249 }; 250 251 enum COMMAND_TYPE 252 { 253 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 254 }; 255 256 //! \brief AVC 257 //! \details 258 //! <b>For AVC QM Type</b>: This field specifies which Quantizer Matrix is 259 //! loaded. 260 enum AVC 261 { 262 AVC_AVC_4X_4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 263 AVC_AVC_4X_4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 264 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 265 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 266 }; 267 268 //! \brief MPEG2 269 //! \details 270 //! <b>For MPEG2 QM Type</b>: This field specifies which Quantizer Matrix is 271 //! loaded. 272 enum MPEG2 273 { 274 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 275 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 276 }; 277 278 //! \brief JPEG 279 //! \details 280 //! <b> For JPEG QM Type</b>:This field specifies which Quantizer Matrix is 281 //! loaded. 282 enum JPEG 283 { 284 JPEG_JPEGLUMAYQUANTIZERMATRIXORR = 0, //!< No additional details 285 JPEG_JPEGCHROMACBQUANTIZERMATRIXORG = 1, //!< No additional details 286 JPEG_JPEGCHROMACRQUANTIZERMATRIXORB = 2, //!< No additional details 287 }; 288 289 //! \name Initializations 290 291 //! \brief Explicit member initialization function 292 MFX_FQM_STATE_CMD(); 293 294 static const size_t dwSize = 34; 295 static const size_t byteSize = 136; 296 }; 297 298 //! 299 //! \brief MFX_PIPE_MODE_SELECT 300 //! \details 301 //! Specifies which codec and hardware module is being used to encode/decode 302 //! the video data, on a per-frame basis. The MFX_PIPE_MODE_SELECT command 303 //! specifies which codec and hardware module is being used to encode/decode 304 //! the video data, on a per-frame basis. It also configures the hardware 305 //! pipeline according to the active encoder/decoder operating mode for 306 //! encoding/decoding the current picture. Commands issued specifically for 307 //! AVC and MPEG2 are ignored when VC1 is the active codec. 308 //! 309 struct MFX_PIPE_MODE_SELECT_CMD 310 { 311 union 312 { 313 //!< DWORD 0 314 struct 315 { 316 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 317 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 318 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 319 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPA 320 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26) ; //!< OPCODE 321 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 322 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 323 }; 324 uint32_t Value; 325 } DW0; 326 union 327 { 328 //!< DWORD 1 329 struct 330 { 331 uint32_t StandardSelect : __CODEGEN_BITFIELD( 0, 3) ; //!< STANDARD_SELECT 332 uint32_t CodecSelect : __CODEGEN_BITFIELD( 4, 4) ; //!< CODEC_SELECT 333 uint32_t StitchMode : __CODEGEN_BITFIELD( 5, 5) ; //!< STITCH_MODE 334 uint32_t FrameStatisticsStreamoutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< FRAME_STATISTICS_STREAMOUT_ENABLE 335 uint32_t ScaledSurfaceEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< SCALED_SURFACE_ENABLE 336 uint32_t PreDeblockingOutputEnablePredeblockoutenable : __CODEGEN_BITFIELD( 8, 8) ; //!< PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 337 uint32_t PostDeblockingOutputEnablePostdeblockoutenable : __CODEGEN_BITFIELD( 9, 9) ; //!< POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 338 uint32_t StreamOutEnable : __CODEGEN_BITFIELD(10, 10) ; //!< STREAM_OUT_ENABLE 339 uint32_t PicErrorStatusReportEnable : __CODEGEN_BITFIELD(11, 11) ; //!< PIC_ERRORSTATUS_REPORT_ENABLE 340 uint32_t DeblockerStreamOutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< DEBLOCKER_STREAM_OUT_ENABLE 341 uint32_t VdencMode : __CODEGEN_BITFIELD(13, 13) ; //!< VDENC_MODE 342 uint32_t StandaloneVdencModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< STANDALONE_VDENC_MODE_ENABLE 343 uint32_t DecoderModeSelect : __CODEGEN_BITFIELD(15, 16) ; //!< DECODER_MODE_SELECT 344 uint32_t DecoderShortFormatMode : __CODEGEN_BITFIELD(17, 17) ; //!< DECODER_SHORT_FORMAT_MODE 345 uint32_t ExtendedStreamOutEnable : __CODEGEN_BITFIELD(18, 18) ; //!< Extended stream out enable 346 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 347 }; 348 uint32_t Value; 349 } DW1; 350 union 351 { 352 //!< DWORD 2 353 struct 354 { 355 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 356 uint32_t VdsIldbCalculation : __CODEGEN_BITFIELD( 3, 3) ; //!< VDS_ILDB_CALCULATION 357 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 5) ; //!< Reserved 358 uint32_t ClockGateEnableAtSliceLevel : __CODEGEN_BITFIELD( 6, 6) ; //!< CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 359 uint32_t Reserved71 : __CODEGEN_BITFIELD( 7, 9) ; //!< Reserved 360 uint32_t MpcPref08X8DisableFlagDefault0 : __CODEGEN_BITFIELD(10, 10) ; //!< MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 361 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13) ; //!< Reserved 362 uint32_t Vlf720IOddHeightInVc1Mode : __CODEGEN_BITFIELD(14, 14) ; //!< VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 363 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 364 uint32_t VmbSvcTlbDummyFetchDisableForPerformance : __CODEGEN_BITFIELD(27, 27) ; //!< VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 365 uint32_t VmbSvcMvReplicationFor8X8EnableErrorHandling : __CODEGEN_BITFIELD(28, 28) ; //!< VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 366 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 367 }; 368 uint32_t Value; 369 } DW2; 370 union 371 { 372 //!< DWORD 3 373 struct 374 { 375 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 376 }; 377 uint32_t Value; 378 } DW3; 379 union 380 { 381 //!< DWORD 4 382 struct 383 { 384 uint32_t Reserved128 ; //!< Reserved 385 }; 386 uint32_t Value; 387 } DW4; 388 389 //! \name Local enumerations 390 391 enum SUBOPB 392 { 393 SUBOPB_MFXPIPEMODESELECT = 0, //!< No additional details 394 }; 395 396 enum SUBOPA 397 { 398 SUBOPA_UNNAMED0 = 0, //!< No additional details 399 }; 400 401 enum OPCODE 402 { 403 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 404 }; 405 406 enum PIPELINE 407 { 408 PIPELINE_MFXCOMMON = 2, //!< No additional details 409 }; 410 411 enum COMMAND_TYPE 412 { 413 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 414 }; 415 416 enum STANDARD_SELECT 417 { 418 STANDARD_SELECT_MPEG2 = 0, //!< No additional details 419 STANDARD_SELECT_VC1 = 1, //!< No additional details 420 STANDARD_SELECT_AVC = 2, //!< Covers both AVC and MVC 421 STANDARD_SELECT_JPEG = 3, //!< No additional details 422 STANDARD_SELECT_SVC = 4, //!< No additional details 423 STANDARD_SELECT_VP8 = 5, //!< Decoder starting from BDW, Encoder starting from SKL 424 STANDARD_SELECT_UVLD = 15, //!< SW decoder w/ embedded micro-controller and co-processor 425 }; 426 427 enum CODEC_SELECT 428 { 429 CODEC_SELECT_DECODE = 0, //!< No additional details 430 CODEC_SELECT_ENCODE = 1, //!< Valid only if StandardSel is AVC, MPEG2 and SVC) 431 }; 432 433 enum STITCH_MODE 434 { 435 STITCH_MODE_NOTINSTITCHMODE = 0, //!< No additional details 436 STITCH_MODE_INTHESPECIALSTITCHMODE = 1, //!< This mode can be used for any Codec as long as bitfield conditions are met. 437 }; 438 439 //! \brief FRAME_STATISTICS_STREAMOUT_ENABLE 440 //! \details 441 //! This field controls the frame level statistics streamout from the PAK. 442 //! <p><b>Note</b>: This field needs to be always "Enabled" in VD_Enc 443 //! mode. In case of non-VDEnc mode, 444 //! this can be used to control the frame statistics output from the 445 //! PAK.</p> 446 enum FRAME_STATISTICS_STREAMOUT_ENABLE 447 { 448 FRAME_STATISTICS_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 449 FRAME_STATISTICS_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 450 }; 451 452 //! \brief SCALED_SURFACE_ENABLE 453 //! \details 454 //! This field indicates if the scaled surface is enabled. This field 455 //! enables the 4x HME downscalar of the reconstructed image. Only 456 //! supported for AVC and VP8 formats. 457 enum SCALED_SURFACE_ENABLE 458 { 459 SCALED_SURFACE_ENABLE_DISABLE = 0, //!< No additional details 460 SCALED_SURFACE_ENABLE_ENABLE = 1, //!< No additional details 461 }; 462 463 //! \brief PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 464 //! \details 465 //! This field controls the output write for the reconstructed pixels BEFORE 466 //! the deblocking filter. 467 enum PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 468 { 469 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 470 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 471 }; 472 473 //! \brief POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 474 //! \details 475 //! This field controls the output write for the reconstructed pixels AFTER 476 //! the deblocking filter.In MPEG2 decoding mode, if this is enabled, VC1 477 //! deblocking filter is used. 478 enum POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 479 { 480 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 481 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 482 }; 483 484 //! \brief STREAM_OUT_ENABLE 485 //! \details 486 //! This field controls whether the macroblock parameter stream-out is 487 //! enabled during VLD decoding for transcoding purpose. 488 enum STREAM_OUT_ENABLE 489 { 490 STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 491 STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 492 }; 493 494 //! \brief PIC_ERRORSTATUS_REPORT_ENABLE 495 //! \details 496 //! <p>This field control whether the error/status reporting is enable or 497 //! not.0: Disable1: EnableIn decoder modes: Error reporting is written out 498 //! once per frame. The Error Report frame ID listed in DW3 along with the 499 //! VLD/IT error status bits are packed into one cache and written to the 500 //! "Decoded Picture Error/Status Buffer address" listed in the 501 //! MFX_PIPE_BUF_ADDR_STATE Command. Note: driver shall program different 502 //! error buffer addresses between pictrues; otherwise, hardware might 503 //! overwrite previous written data if driver does not read it fast 504 //! enough.In encoder modes: Not used</p> 505 //! <p>Please refer to "Media VDBOX -> Video Codec -> Other Codec 506 //! Functions -> MFX Error Handling -> Decoder" session for the output 507 //! format.</p> 508 enum PIC_ERRORSTATUS_REPORT_ENABLE 509 { 510 PIC_ERRORSTATUS_REPORT_ENABLE_DISABLE = 0, //!< No additional details 511 PIC_ERRORSTATUS_REPORT_ENABLE_ENABLE = 1, //!< No additional details 512 }; 513 514 //! \brief DEBLOCKER_STREAM_OUT_ENABLE 515 //! \details 516 //! This field indicates if Deblocker information is going to be streamout 517 //! during VLD decoding. 518 //! For AVC, it is needed to enable the deblocker streamout as the AVC 519 //! Disable_DLKFilterIdc is a slice level parameters. Driver needs to 520 //! determine ahead of time if at least one slice of the current frame/ has 521 //! deblocker ON. 522 //! For SVC, there are two deblocking control streamout buffers 523 //! (specified in MFX_BUF_ADDR State Command). This field is still 524 //! associated with the slice level SVC Disable.DLK_Filter_Idc. 525 enum DEBLOCKER_STREAM_OUT_ENABLE 526 { 527 DEBLOCKER_STREAM_OUT_ENABLE_DISABLE = 0, //!< Disable streamout of deblocking control information for standalone deblocker operation.It needs other fields to determine one or two SVC deblocking surface streamout (Post Deblocking Output Enable, Pre Deblocking Output Enable, interlayer idc and regular deblock idc). 528 DEBLOCKER_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 529 }; 530 531 //! \brief VDENC_MODE 532 //! \details 533 //! This field indicates if PAK is working in legacy MBEnc mode or the VDEnc 534 //! mode. 535 enum VDENC_MODE 536 { 537 VDENC_MODE_MBENCMODE = 0, //!< PAK is working in legacy mode 538 VDENC_MODE_VDENCMODE = 1, //!< PAK is working in VDEnc mode 539 }; 540 541 //! \brief STANDALONE_VDENC_MODE_ENABLE 542 //! \details 543 //! This field indicates to PAK if this is standalone VDEnc mode. This is 544 //! primarily a validation mode. 545 enum STANDALONE_VDENC_MODE_ENABLE 546 { 547 STANDALONE_VDENC_MODE_ENABLE_VDENCPAK = 0, //!< No additional details 548 STANDALONE_VDENC_MODE_ENABLE_PAKONLY = 1, //!< No additional details 549 }; 550 551 //! \brief DECODER_MODE_SELECT 552 //! \details 553 //! Each coding standard supports two entry points: VLD entry point and IT 554 //! (IDCT) entry point. This field selects which one is in use.This field is 555 //! only valid if Codec Select is 0 (decoder). 556 enum DECODER_MODE_SELECT 557 { 558 DECODER_MODE_SELECT_VLDMODE = 0, //!< All codec minimum must support this mode Configure the MFD Engine for VLD ModeNote: All codec minimum must support this mode 559 DECODER_MODE_SELECT_ITMODE = 1, //!< Configure the MFD Engine for IT ModeNote: Only VC1 and MPEG2 support this mode 560 DECODER_MODE_SELECT_DEBLOCKERMODE = 2, //!< Configure the MFD Engine for Standalone Deblocker Mode. Require streamout AVC edge control information from preceeding decoding pass.Note: [HSW, EXCLUDE(HSW:GT3:A, HSW:GT3:B, HSW:GT2:B)] Only AVC, MPEG2 and SVC are supported. 561 DECODER_MODE_SELECT_INTERLAYERMODE = 3, //!< Configure the MFX Engine for standalone SVC interlayer upsampling for motion info, residual and reconstructed pixel. Require information being streamout from the preceding encoding and decoding pass of a reference layer.> 562 }; 563 564 //! \brief DECODER_SHORT_FORMAT_MODE 565 //! \details 566 //! For IT mode, this bit must be 0. 567 enum DECODER_SHORT_FORMAT_MODE 568 { 569 DECODER_SHORT_FORMAT_MODE_SHORTFORMATDRIVERINTERFACE = 0, //!< AVC/VC1/MVC/SVC/VP8 Short Format Mode is in useNote: There is no Short Format for SVC and VP8 yet, so this field must be set to 1 for SVC and VP8. 570 DECODER_SHORT_FORMAT_MODE_LONGFORMATDRIVERINTERFACE = 1, //!< AVC/VC1/MVC/SVC/VP8 Long Format Mode is in use. 571 }; 572 573 //! \brief VDS_ILDB_CALCULATION 574 //! \details 575 //! This bit forces all MB into INTRA MBs before doing ILDB control 576 //! generation in VDS. 577 enum VDS_ILDB_CALCULATION 578 { 579 VDS_ILDB_CALCULATION_DISABLE = 0, //!< Use original definition for ILDB calculation. 580 VDS_ILDB_CALCULATION_ENABLE = 1, //!< Force neighbor Intra MB = 1 on ILDB BS calculation. 581 }; 582 583 //! \brief CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 584 //! \details 585 //! BitFieldDesc: 586 enum CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 587 { 588 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_DISABLE = 0, //!< Disable Slice-level Clock gating, Unit-level Clock gating will apply 589 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_ENABLE = 1, //!< Enable Slice-level Clock gating, overrides any Unit level Clock gating 590 }; 591 592 enum MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 593 { 594 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_DISABLE = 0, //!< No additional details 595 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_ENABLE = 1, //!< No additional details 596 }; 597 598 //! \brief VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 599 //! \details 600 //! This bit indicates VLF write out VC1 picture with odd height (in MBs). 601 enum VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 602 { 603 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_DISABLE = 0, //!< No additional details 604 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ENABLE = 1, //!< 720i Enable 605 }; 606 607 //! \brief VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 608 //! \details 609 //! This bit disables TLB dummy fetch in SVC mode in VMB. 610 enum VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 611 { 612 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_ENABLE = 0, //!< Enable VMB TLB Dummy Fetch for Performance 613 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_DISABLE = 1, //!< Disable VMB TLB Dummy Fetch 614 }; 615 616 //! \brief VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 617 //! \details 618 //! This bit enables Motion Vector replication on 8x8 level during SVC mode 619 //! for error handling. 620 enum VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 621 { 622 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_DISABLE = 0, //!< Disable MV 8x8 replication in SVC mode 623 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_ENABLE = 1, //!< Enable MV 8x8 Replication in SVC Mode 624 }; 625 626 //! \brief PIC_STATUSERROR_REPORT_ID 627 //! \details 628 //! In decoder modes: Error reporting is written out once per frame. This 629 //! field along with the VLD error status bits are packed into one cache and 630 //! written to the memory location specified by "Decoded Picture 631 //! Error/Status Buffer address" listed in the MFX_PIPE_BUF_ADDR_STATE 632 //! Command. 633 enum PIC_STATUSERROR_REPORT_ID 634 { 635 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 636 }; 637 638 //! \name Initializations 639 640 //! \brief Explicit member initialization function 641 MFX_PIPE_MODE_SELECT_CMD(); 642 643 static const size_t dwSize = 5; 644 static const size_t byteSize = 20; 645 }; 646 647 //! 648 //! \brief MFX_SURFACE_STATE 649 //! \details 650 //! This command is common for all encoding/decoding modes, to specify the 651 //! uncompressed YUV picture (i.e. destination surface) or intermediate 652 //! streamout in/out surface (e.g. coefficient/residual) (field, frame or 653 //! interleaved frame) format for reading and writing: Uncompressed, 654 //! original input picture to be encoded 655 //! Reconstructed non-filtered/filtered display picturec(becoming reference 656 //! pictures as well for subsequent temporal inter-prediction) 657 //! Residual in SVC 658 //! Reconstructed Intra pixel in SVC 659 //! CoeffPred in SVC 660 //! Since there is only one media surface state being active during the 661 //! entire encoding/decoding process, all the uncompressed/reconstructed 662 //! pictures are defined to have the same surface state. For each media 663 //! object call (decoding or encoding), multiple SVC surfaces can be active 664 //! concurrently, to distinguish among them, a surfaceID is added to 665 //! specify for each type of surface. The primary difference among picture 666 //! surface states is their individual programmed base addresses, which are 667 //! provided by other state commands and not included in this command. MFX 668 //! engine is making the association of surface states and corresponding 669 //! buffer base addresses. MFX engine currently supports only one media 670 //! surface type for video and that is the NV12 (Planar YUV420 with 671 //! interleaved U (Cb) and V (Cr). For optimizing memory efficiency based on 672 //! access patterns, only TileY is supported. For JPEG decoder, only IMC1 673 //! and IMC3 are supported. Pitch can be wider than the Picture Width in 674 //! pixels and garbage will be there at the end of each line. The following 675 //! describes all the different formats that are supported and not supported 676 //! in Gen7 MFX : NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V 677 //! offset is set to 0 (the only format supported for video codec); vertical 678 //! UV offset is MB aligned; UV xoffsets = 0. JPEG does not support NV12 679 //! format because non-interleave JPEG has performance issue with partial 680 //! write (in interleaved UV format) 681 //! IMC 1 & 3 - Full Pitch, U and V are separate plane; (JPEG only; U 682 //! plane + garbage first in full pitch followed by V plane + garbage in 683 //! full pitch). U and V vertical offsets are block aligned; U and V xoffset 684 //! = 0; there is no gap between Y, U and V planes. IMC1 and IMC3 are 685 //! different by a swap of U and V. This is the only format supported in 686 //! JPEG for all video subsampling types (4:4:4, 4:2:2 and 4:2:0) 687 //! We are not supporting IMC 2 & 4 - Full Pitch, U and V are separate 688 //! plane (JPEG only; U plane first in full pitch followed by V plane in 689 //! full pitch - U and V plane are side-by-side). U and V vertical offsets 690 //! are 16-pixel aligned; V xoffset is half-pitch aligned; U xoffset is 0; 691 //! there is no gap between Y, U and V planes. IMC2 and IMC4 are different 692 //! by a swap of U and V. 693 //! We are not supporting YV12 - half pitch for each U and V plane, and 694 //! separate planes for Y, U and V (U plane first in half pitch followed by 695 //! V plane in half pitch). For YV12, U and V vertical offsets are block 696 //! aligned; U and V xoffset = 0; there is no gap between Y, U and V planes 697 //! Note that the following data structures are not specified through the 698 //! media surface state 1D buffers for row-store and other miscellaneous 699 //! information. 700 //! 2D buffers for per-MB data-structures (e.g. DMV biffer, MB info record, 701 //! ILDB Control and Tcoeff/Stocoeff). 702 //! This surface state here is identical to the Surface State for 703 //! deinterlace and sample_8x8 messages described in the Shared Function 704 //! Volume and Sampler Chapter. For non pixel data, such as row stores, 705 //! indirect data (Compressed Slice Data, AVC MV record, Coeff record and 706 //! AVC ILDB record) and streamin/out and output compressed bitstream, a 707 //! linear buffer is employed. For row stores, the H/W is designed to 708 //! guarantee legal memory accesses (read and write). For the remaining 709 //! cases, indirect object base address, indirect object address upper 710 //! bound, object data start address (offset) and object data length are 711 //! used to fully specified their corresponding buffer. This mechanism is 712 //! chosen over the pixel surface type because of their variable record 713 //! sizes. All row store surfaces are linear surface. Their addresses are 714 //! programmed in Pipe_Buf_Base_State or Bsp_Buf_Base_Addr_State 715 //! 716 //! VC1 I picture scaling: Even though VC1 allows I reconstructed picture 717 //! scaling (via RESPIC), as such scaling is only allowed at I picture. All 718 //! subsequent P (and B) pictures must have the same picture dimensions with 719 //! the preceding I picture. Therefore, all reference pictures for P or B 720 //! picture can share the same surface state with the current P and B 721 //! picture. Note : H/W is not processing RESPIC. Application is no longer 722 //! expecting intel decoder pipelineand kernel to perform this function, it 723 //! is going to be done in the video post-processing scaler or display 724 //! controller scale as a separate step and controller. 725 //! 726 //! All video codec surfaces must be NV12 Compliant, except JPEG. U/V 727 //! vertical must be MB aligned for all video codec (further contrained for 728 //! field picture), but JPEG can be block aligned. All video codec and JPEG 729 //! uses Tiled - Y format only, for uncompressed pixel surfaces. 730 //! 731 //! Even for JPEG planar 420 surface, application may provide only 1 732 //! buffers, but there is still only one single surface state for all of 733 //! them. If IMC equal to 1, 2, 3 or 4, U and V have the pitch same as Y. 734 //! And U and V will have different offset, each offset is block aligned. 735 //! 736 struct MFX_SURFACE_STATE_CMD 737 { 738 union 739 { 740 //!< DWORD 0 741 struct 742 { 743 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 744 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 745 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 746 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPA 747 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26) ; //!< OPCODE 748 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 749 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 750 }; 751 uint32_t Value; 752 } DW0; 753 union 754 { 755 //!< DWORD 1 756 struct 757 { 758 uint32_t SurfaceId : __CODEGEN_BITFIELD( 0, 3) ; //!< SURFACE_ID 759 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 760 }; 761 uint32_t Value; 762 } DW1; 763 union 764 { 765 //!< DWORD 2 766 struct 767 { 768 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< Cr(V)/Cb(U) Pixel Offset V Direction 769 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 770 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 771 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 772 }; 773 uint32_t Value; 774 } DW2; 775 union 776 { 777 //!< DWORD 3 778 struct 779 { 780 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 781 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 782 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 783 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 784 uint32_t Reserved116 : __CODEGEN_BITFIELD( 20,26) ; //!< Reserved 785 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(27, 27) ; //!< INTERLEAVE_CHROMA_ 786 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_FORMAT 787 }; 788 uint32_t Value; 789 } DW3; 790 union 791 { 792 //!< DWORD 4 793 struct 794 { 795 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) 796 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 797 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for U(Cb) 798 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 799 }; 800 uint32_t Value; 801 } DW4; 802 union 803 { 804 //!< DWORD 5 805 struct 806 { 807 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 15) ; //!< Y Offset for V(Cr) 808 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V(Cr) 809 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 810 }; 811 uint32_t Value; 812 } DW5; 813 814 //! \name Local enumerations 815 816 enum SUBOPB 817 { 818 SUBOPB_UNNAMED1 = 1, //!< No additional details 819 }; 820 821 enum SUBOPA 822 { 823 SUBOPA_UNNAMED0 = 0, //!< No additional details 824 }; 825 826 enum OPCODE 827 { 828 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 829 }; 830 831 enum PIPELINE 832 { 833 PIPELINE_MFXCOMMON = 2, //!< No additional details 834 }; 835 836 enum COMMAND_TYPE 837 { 838 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 839 }; 840 841 enum SURFACE_ID 842 { 843 SURFACE_ID_DECODEDPICTUREANDREFERENCEPICTURES_SVCUPSAMPLINGSTREAMOUTRECONSTRUCTEDPIXELSCOEFFPREDUPPERLAYERSIZE = 0, //!< 8-bit uncompressed data 844 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMOUTSURFACEUPPERLAYERSIZE = 1, //!< 16-bit uncompressed data 845 SURFACE_ID_SVCRECONSTRUCTEDPIXELANDCOEFFPREDUPSAMPLINGSTREAMINSURFACELOWERLAYERSIZE = 2, //!< 8-bit uncompressed data. 846 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMINSURFACELOWERLAYERSIZE = 3, //!< 16-bit uncompressed data 847 SURFACE_ID_SOURCEINPUTPICTUREENCODER = 4, //!< 8-bit uncompressed data 848 SURFACE_ID_RECONSTRUCTEDSCALEDREFERENCEPICTURE = 5, //!< 8-bit data 849 }; 850 851 //! \brief TILE_WALK 852 //! \details 853 //! (This field must be set to 1: TILEWALK_YMAJOR)This field specifies the 854 //! type of memory tiling (XMajor or YMajor) employed to tile this surface. 855 //! See Memory Interface Functions for details on memory tiling and 856 //! restrictions.This field is ignored when the surface is linear.This field 857 //! is ignored by MFX. Internally H/W is always treated this set to 1 for 858 //! all video codec and for JPEG. 859 enum TILE_WALK 860 { 861 TILE_WALK_XMAJOR = 0, //!< TILEWALK_XMAJOR 862 TILE_WALK_YMAJOR = 1, //!< TILEWALK_YMAJOR 863 }; 864 865 //! \brief TILED_SURFACE 866 //! \details 867 //! (This field must be set to TRUE: Tiled)This field specifies whether the 868 //! surface is tiled.This field is ignored by MFX 869 enum TILED_SURFACE 870 { 871 TILED_SURFACE_FALSE = 0, //!< Linear 872 TILED_SURFACE_TRUE = 1, //!< Tiled 873 }; 874 875 //! \brief INTERLEAVE_CHROMA_ 876 //! \details 877 //! This field indicates that the chroma fields are interleaved in a single 878 //! plane rather than stored as two separate planes. This field is only used 879 //! for PLANAR surface formats.For AVC/VC1/MPEG VLD and IT modes : set to 880 //! Enable to support interleave U/V only.For JPEG : set to Disable for all 881 //! formats (including 4:2:0) - because JPEG does not support NV12. (This 882 //! field is needed only if JPEG will support NV12; otherwise is ignored.) 883 enum INTERLEAVE_CHROMA_ 884 { 885 INTERLEAVE_CHROMA_DISABLE = 0, //!< No additional details 886 INTERLEAVE_CHROMA_ENABLE = 1, //!< No additional details 887 }; 888 889 //! \brief SURFACE_FORMAT 890 //! \details 891 //! Specifies the format of the surface. All of the Y and G channels will 892 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1.Usage: 893 //! For 420 planar YUV surface, use 4; for monochrome surfaces, use 12. For 894 //! monochrome surfaces, hardware ignores control fields for Chroma 895 //! planes.This field must be set to 4 - PLANAR_420_8, or 12 - Y8_UNORMNot 896 //! used for MFX, and is ignored. But for JPEG decoding, this field should 897 //! be programmed to the same format as JPEG_PIC_STATE. For video codec, it 898 //! should set to 4 always. 899 enum SURFACE_FORMAT 900 { 901 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 902 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 903 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 904 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 905 SURFACE_FORMAT_PLANAR_4208 = 4, //!< (NV12, IMC1,2,3,4, YV12) 906 SURFACE_FORMAT_PLANAR_4118 = 5, //!< Deinterlace Only 907 SURFACE_FORMAT_PLANAR_4228 = 6, //!< Deinterlace Only 908 SURFACE_FORMAT_STMMDNSTATISTICS = 7, //!< Deinterlace Only 909 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 Only 910 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 Only 911 SURFACE_FORMAT_R8B8UNORMCRCB = 10, //!< Sample_8x8 Only 912 SURFACE_FORMAT_R8UNORMCRCB = 11, //!< Sample_8x8 Only 913 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 Only 914 }; 915 916 //! \name Initializations 917 918 //! \brief Explicit member initialization function 919 MFX_SURFACE_STATE_CMD(); 920 921 static const size_t dwSize = 6; 922 static const size_t byteSize = 24; 923 }; 924 925 //! 926 //! \brief MFX_IND_OBJ_BASE_ADDR_STATE 927 //! \details 928 //! This state command provides the memory base addresses for all row 929 //! stores, StreamOut buffer and reconstructed picture output buffers 930 //! required by the MFD or MFC Engine (that are in addition to the row 931 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 932 //! reference picture buffers). This is a picture level state command and is 933 //! common among all codec standards and for both encoder and decoder 934 //! operating modes. However, some fields may only applicable to a specific 935 //! codec standard. All Pixel Surfaces (original, reference frame and 936 //! reconstructed frame) in the Encoder are programmed with the same surface 937 //! state (NV12 and TileY format), except each has its own frame buffer base 938 //! address. In the tile format, there is no need to provide buffer offset 939 //! for each slice; since from each MB address, the hardware can calculated 940 //! the corresponding memory location within the frame buffer directly. 941 //! 942 //! The MFX_IND_OBJ_BASE_ADDR command sets the memory base address pointers 943 //! for the corresponding Indirect Object Data Start Addresses (Offsets) 944 //! specified in each OBJECT commands. The characteristic of these indirect 945 //! object data is their variable size (per MB or per Slice). Hence, each 946 //! OBJECT command must specify the indirect object data offset from the 947 //! base address to start fetching or writing object data. 948 //! 949 //! While the use of base address is unconditional, the indirection can be 950 //! effectively disabled by setting the base address to zero. For decoder, 951 //! there are: 1 read-only per-slice indirect object in the BSD_OBJECT 952 //! Command, and 953 //! 2 read-only per-MB indirect objects in the IT_OBJECT Command. 954 //! For decoder: the Video Command Streamer (VCS) will perform the memory 955 //! access bound check automatically using the corresponding MFC Indirect 956 //! Object Access Upper Bound specification. If any access is at or beyond 957 //! the upper bound, zero value is returned. The request to memory is still 958 //! being sent, but the corresponding codec's BSD unit will detect this 959 //! condition and perform the zeroing return. If the Upper Bound is turned 960 //! off, the beyond bound request will return whatever on the bus (invalid 961 //! data). For encoder, there are: 1 read-only per-MB indirect object in 962 //! the PAK_OBJECT Command, and 963 //! 1 write-only per-slice indirect object in the PAK Slice_State Command 964 //! For encoder: whenever an out of bound address accessing request is 965 //! generated, VMX will detect such requests and snap the address to the 966 //! corresponding [indirect object base address + indirect data start 967 //! address]. VMX will return all 0s as the data to the requestor. 968 //! NotationDefinitionPhysicalAddress[n:m] Corresponding bits of a physical 969 //! graphics memory byte address (not mapped by a GTT) GraphicsAddress[n:m] 970 //! Corresponding bits of an absolute, virtual graphics memory byte address 971 //! (mapped by a GTT). 972 //! 973 struct MFX_IND_OBJ_BASE_ADDR_STATE_CMD 974 { 975 union 976 { 977 //!< DWORD 0 978 struct 979 { 980 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 981 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 982 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 983 uint32_t SubOpcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODEA 984 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMON_OPCODE 985 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 986 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 987 }; 988 uint32_t Value; 989 } DW0; 990 union 991 { 992 //!< DWORD 1 993 struct 994 { 995 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 996 uint32_t MfxIndirectBitstreamObjectBaseAddressDecoderAndStitchModes : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect Bitstream Object - Base Address (Decoder and Stitch Modes) 997 }; 998 uint32_t Value; 999 } DW1; 1000 union 1001 { 1002 //!< DWORD 2 1003 struct 1004 { 1005 uint32_t MfxIndirectBitstreamObjectDestinationAddressDecoderAndStitchModes4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect Bitstream Object - Destination Address (Decoder and Stitch Modes)[47:32] 1006 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1007 }; 1008 uint32_t Value; 1009 } DW2; 1010 union 1011 { 1012 //!< DWORD 3 1013 struct 1014 { 1015 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1016 uint32_t MfxIndirectBitstreamObjectbaseArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1017 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1018 uint32_t MfxIndirectBitstreamObjectTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1019 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1020 }; 1021 uint32_t Value; 1022 } DW3; 1023 union 1024 { 1025 //!< DWORD 4 1026 struct 1027 { 1028 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1029 uint32_t MfxIndirectBitstreamObjectAccessUpperBoundDecoderAndStitchModes : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect Bitstream Object - Access Upper Bound (Decoder and Stitch Modes) 1030 }; 1031 uint32_t Value; 1032 } DW4; 1033 union 1034 { 1035 //!< DWORD 5 1036 struct 1037 { 1038 uint32_t MfxIndirectBitstreamObjectUpperboundDecoderAndStitchModes4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect Bitstream Object UpperBound (Decoder and Stitch Modes)[47:32] 1039 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1040 }; 1041 uint32_t Value; 1042 } DW5; 1043 union 1044 { 1045 //!< DWORD 6 1046 struct 1047 { 1048 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1049 uint32_t MfxIndirectMvObjectBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect MV Object - Base Address 1050 }; 1051 uint32_t Value; 1052 } DW6; 1053 union 1054 { 1055 //!< DWORD 7 1056 struct 1057 { 1058 uint32_t MfxIndirectMvObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect MV Object Base Address [47:32] 1059 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1060 }; 1061 uint32_t Value; 1062 } DW7; 1063 union 1064 { 1065 //!< DWORD 8 1066 struct 1067 { 1068 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1069 uint32_t MfxIndirectMvObjectArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1070 uint32_t Reserved265 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1071 uint32_t MfxIndirectMvObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1072 uint32_t Reserved271 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1073 }; 1074 uint32_t Value; 1075 } DW8; 1076 union 1077 { 1078 //!< DWORD 9 1079 struct 1080 { 1081 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1082 uint32_t MfxIndirectMvObjectAccessUpperBound : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect MV Object Access Upper Bound 1083 }; 1084 uint32_t Value; 1085 } DW9; 1086 union 1087 { 1088 //!< DWORD 10 1089 struct 1090 { 1091 uint32_t MfxIndirectMvObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect MV Object UpperBound [47:32] 1092 uint32_t Reserved336 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1093 }; 1094 uint32_t Value; 1095 } DW10; 1096 union 1097 { 1098 //!< DWORD 11 1099 struct 1100 { 1101 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1102 uint32_t MfdIndirectItCoeffObjectBaseAddressDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-COEFF Object - Base Address (Decoder Only) 1103 }; 1104 uint32_t Value; 1105 } DW11; 1106 union 1107 { 1108 //!< DWORD 12 1109 struct 1110 { 1111 uint32_t MfdIndirectItCoeffObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-COEFF Object Base Address [47:32] 1112 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1113 }; 1114 uint32_t Value; 1115 } DW12; 1116 union 1117 { 1118 //!< DWORD 13 1119 struct 1120 { 1121 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1122 uint32_t MfdIndirectItCoeffObjectDesitnationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1123 uint32_t Reserved425 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1124 uint32_t MfdIndirectItCoeffTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1125 uint32_t Reserved431 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1126 }; 1127 uint32_t Value; 1128 } DW13; 1129 union 1130 { 1131 //!< DWORD 14 1132 struct 1133 { 1134 uint32_t Reserved448 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1135 uint32_t MfdIndirectItCoeffObjectAccessUpperBoundDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-COEFF Object - Access Upper Bound (Decoder Only) 1136 }; 1137 uint32_t Value; 1138 } DW14; 1139 union 1140 { 1141 //!< DWORD 15 1142 struct 1143 { 1144 uint32_t MfdIndirectItCoeffObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-COEFF Object UpperBound [47:32] 1145 uint32_t Reserved496 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1146 }; 1147 uint32_t Value; 1148 } DW15; 1149 union 1150 { 1151 //!< DWORD 16 1152 struct 1153 { 1154 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1155 uint32_t MfdIndirectItDblkObjectBaseAddressDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-DBLK Object - Base Address (Decoder Only) 1156 }; 1157 uint32_t Value; 1158 } DW16; 1159 union 1160 { 1161 //!< DWORD 17 1162 struct 1163 { 1164 uint32_t MfdIndirectItDblkObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-DBLK Object Base Address [47:32] 1165 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1166 }; 1167 uint32_t Value; 1168 } DW17; 1169 union 1170 { 1171 //!< DWORD 18 1172 struct 1173 { 1174 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1175 uint32_t MfdIndirectItDblkObjectArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1176 uint32_t Reserved585 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1177 uint32_t MfdIndirectItDblkObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1178 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1179 }; 1180 uint32_t Value; 1181 } DW18; 1182 union 1183 { 1184 //!< DWORD 19 1185 struct 1186 { 1187 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1188 uint32_t MfdIndirectItDblkObjectAccessUpperBoundDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-DBLK Object - Access Upper Bound (Decoder Only) 1189 }; 1190 uint32_t Value; 1191 } DW19; 1192 union 1193 { 1194 //!< DWORD 20 1195 struct 1196 { 1197 uint32_t MfdIndirectItDblkObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-DBLK Object UpperBound [47:32] 1198 uint32_t Reserved656 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1199 }; 1200 uint32_t Value; 1201 } DW20; 1202 union 1203 { 1204 //!< DWORD 21 1205 struct 1206 { 1207 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1208 uint32_t MfcIndirectPakBseObjectBaseAddressEncoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFC Indirect PAK-BSE Object - Base Address (Encoder Only) 1209 }; 1210 uint32_t Value; 1211 } DW21; 1212 union 1213 { 1214 //!< DWORD 22 1215 struct 1216 { 1217 uint32_t MfcIndirectPakBseObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFC Indirect PAK-BSE Object Base Address [47:32] 1218 uint32_t Reserved720 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1219 }; 1220 uint32_t Value; 1221 } DW22; 1222 union 1223 { 1224 //!< DWORD 23 1225 struct 1226 { 1227 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1228 uint32_t MfcIndirectPakBseObjectDesitnationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1229 uint32_t Reserved745 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1230 uint32_t MfcIndirectPakBseObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1231 uint32_t Reserved751 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1232 }; 1233 uint32_t Value; 1234 } DW23; 1235 union 1236 { 1237 //!< DWORD 24 1238 struct 1239 { 1240 uint32_t Reserved768 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1241 uint32_t MfcIndirectPakBseObjectAccessUpperBoundEecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFC Indirect PAK-BSE Object - Access Upper Bound (Eecoder Only) 1242 }; 1243 uint32_t Value; 1244 } DW24; 1245 union 1246 { 1247 //!< DWORD 25 1248 struct 1249 { 1250 uint32_t MfcIndirectPakBseObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFC Indirect PAK-BSE Object UpperBound [47:32] 1251 uint32_t Reserved816 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1252 }; 1253 uint32_t Value; 1254 } DW25; 1255 1256 //! \name Local enumerations 1257 1258 enum SUBOPCODEB 1259 { 1260 SUBOPCODEB_MFXINDOBJBASEADDRSTATE = 3, //!< No additional details 1261 }; 1262 1263 enum SUB_OPCODEA 1264 { 1265 SUB_OPCODEA_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1266 }; 1267 1268 enum COMMON_OPCODE 1269 { 1270 COMMON_OPCODE_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1271 }; 1272 1273 enum PIPELINE 1274 { 1275 PIPELINE_MFXINDOBJBASEADDRSTATE = 2, //!< No additional details 1276 }; 1277 1278 enum COMMAND_TYPE 1279 { 1280 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1281 }; 1282 1283 //! \brief MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1284 //! \details 1285 //! This field controls the priority of arbitration used in the GAC/GAM 1286 //! pipeline for this surface. 1287 enum MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1288 { 1289 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1290 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1291 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1292 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1293 }; 1294 1295 //! \brief MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1296 //! \details 1297 //! <b>For Media Surfaces:</b> 1298 //! This field specifies the tiled resource mode. 1299 enum MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1300 { 1301 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1302 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1303 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1304 }; 1305 1306 //! \brief MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1307 //! \details 1308 //! This field controls the priority of arbitration used in the GAC/GAM 1309 //! pipeline for this surface. 1310 enum MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1311 { 1312 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1313 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1314 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1315 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1316 }; 1317 1318 //! \brief MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1319 //! \details 1320 //! <b>For Media Surfaces:</b> 1321 //! This field specifies the tiled resource mode. 1322 enum MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1323 { 1324 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1325 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1326 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1327 }; 1328 1329 //! \brief MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1330 //! \details 1331 //! This field controls the priority of arbitration used in the GAC/GAM 1332 //! pipeline for this surface. 1333 enum MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1334 { 1335 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1336 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1337 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1338 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1339 }; 1340 1341 //! \brief MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1342 //! \details 1343 //! <b>For Media Surfaces:</b> 1344 //! This field specifies the tiled resource mode. 1345 enum MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1346 { 1347 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1348 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1349 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1350 }; 1351 1352 //! \brief MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1353 //! \details 1354 //! This field controls the priority of arbitration used in the GAC/GAM 1355 //! pipeline for this surface. 1356 enum MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1357 { 1358 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1359 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1360 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1361 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1362 }; 1363 1364 //! \brief MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1365 //! \details 1366 //! <b>For Media Surfaces:</b> 1367 //! This field specifies the tiled resource mode. 1368 enum MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1369 { 1370 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1371 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1372 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1373 }; 1374 1375 //! \brief MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1376 //! \details 1377 //! This field controls the priority of arbitration used in the GAC/GAM 1378 //! pipeline for this surface. 1379 enum MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1380 { 1381 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1382 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1383 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1384 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1385 }; 1386 1387 //! \brief MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1388 //! \details 1389 //! <b>For Media Surfaces:</b> 1390 //! This field specifies the tiled resource mode. 1391 enum MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1392 { 1393 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1394 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1395 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1396 }; 1397 1398 //! \name Initializations 1399 1400 //! \brief Explicit member initialization function 1401 MFX_IND_OBJ_BASE_ADDR_STATE_CMD(); 1402 1403 static const size_t dwSize = 26; 1404 static const size_t byteSize = 104; 1405 }; 1406 1407 //! 1408 //! \brief MFX_BSP_BUF_BASE_ADDR_STATE 1409 //! \details 1410 //! This frame-level state command is used to specify all the buffer base 1411 //! addresses needed for the operation of the AVC Bit Stream Processing 1412 //! Units (for decoder, it is BSD Unit; for encoder, it is BSE Unit) For 1413 //! both encoder and decoder, currently it is assumed that all codec 1414 //! standards can share the same BSP_BUF_BASE_STATE. The simplicity of this 1415 //! command is the result of moving all the direct MV related processing 1416 //! into the ENC Subsystem. Since all implicit weight calculations and 1417 //! directMV calculations are done in ENC and all picture buffer management 1418 //! are done in the Host, there is no need to provide POC (POC List - 1419 //! FieldOrderCntList, CurrPic POC - CurrFieldOrderCnt) information to PAK. 1420 //! For decoder, all the direct mode information are sent in a separate 1421 //! slice-level command (AVC_DIRECTMODE_STATE command). In addition, in 1422 //! Encoder, the row stores for CABAC encoding and MB Parameters 1423 //! Construction (MPC) are combined into one single row store. The row 1424 //! stores specified in this command do not combine with those specified in 1425 //! the MFC_PIPE_BUF_ADDR_STATE command for hardware simplification reason. 1426 //! 1427 struct MFX_BSP_BUF_BASE_ADDR_STATE_CMD 1428 { 1429 union 1430 { 1431 //!< DWORD 0 1432 struct 1433 { 1434 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1435 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1436 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1437 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1438 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1439 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1440 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1441 }; 1442 uint32_t Value; 1443 } DW0; 1444 union 1445 { 1446 //!< DWORD 1 1447 struct 1448 { 1449 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1450 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite : __CODEGEN_BITFIELD( 6, 31) ; //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write 1451 }; 1452 uint32_t Value; 1453 } DW1; 1454 union 1455 { 1456 //!< DWORD 2 1457 struct 1458 { 1459 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write [47:32] 1460 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1461 }; 1462 uint32_t Value; 1463 } DW2; 1464 union 1465 { 1466 //!< DWORD 3 1467 struct 1468 { 1469 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1470 uint32_t BsdMpcRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1471 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 11) ; //!< Reserved 1472 uint32_t BsdMpcRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1473 uint32_t BsdMpcRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1474 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1475 }; 1476 uint32_t Value; 1477 } DW3; 1478 union 1479 { 1480 //!< DWORD 4 1481 struct 1482 { 1483 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1484 uint32_t MprRowStoreScratchBufferBaseAddressReadWriteDecoderOnly : __CODEGEN_BITFIELD( 6, 31) ; //!< MPR Row Store Scratch Buffer Base Address - Read/Write (Decoder Only) 1485 }; 1486 uint32_t Value; 1487 } DW4; 1488 union 1489 { 1490 //!< DWORD 5 1491 struct 1492 { 1493 uint32_t MprRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MPR Row Store Scratch Buffer Base Address - Read/Write [47:32] 1494 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1495 }; 1496 uint32_t Value; 1497 } DW5; 1498 union 1499 { 1500 //!< DWORD 6 1501 struct 1502 { 1503 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1504 uint32_t MprRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1505 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 11) ; //!< Reserved 1506 uint32_t MprRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1507 uint32_t MprRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1508 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1509 }; 1510 uint32_t Value; 1511 } DW6; 1512 union 1513 { 1514 //!< DWORD 7 1515 struct 1516 { 1517 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1518 uint32_t BitplaneReadBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitplane Read Buffer Base Address 1519 }; 1520 uint32_t Value; 1521 } DW7; 1522 union 1523 { 1524 //!< DWORD 8 1525 struct 1526 { 1527 uint32_t BitplaneReadBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Bitplane Read Buffer Base Address - Read/Write [47:32] 1528 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1529 }; 1530 uint32_t Value; 1531 } DW8; 1532 union 1533 { 1534 //!< DWORD 9 1535 struct 1536 { 1537 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1538 uint32_t BitplaneReadBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1539 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1540 uint32_t BitplaneReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1541 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1542 }; 1543 uint32_t Value; 1544 } DW9; 1545 1546 //! \name Local enumerations 1547 1548 enum SUBOPCODE_B 1549 { 1550 SUBOPCODE_B_UNNAMED_4 = 4, //!< No additional details 1551 }; 1552 1553 enum SUBOPCODE_A 1554 { 1555 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 1556 }; 1557 1558 enum MEDIA_COMMAND_OPCODE 1559 { 1560 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 1561 }; 1562 1563 enum PIPELINE 1564 { 1565 PIPELINE_PIPELINE = 2, //!< No additional details 1566 }; 1567 1568 enum COMMAND_TYPE 1569 { 1570 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1571 }; 1572 1573 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1574 //! \details 1575 //! This field controls the priority of arbitration used in the GAC/GAM 1576 //! pipeline for this surface. 1577 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1578 { 1579 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1580 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1581 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1582 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1583 }; 1584 1585 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1586 //! \details 1587 //! This field controls if Intra Row Store is going to store inside Media 1588 //! Internal Storage or to LLC. 1589 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1590 { 1591 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1592 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1593 }; 1594 1595 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1596 //! \details 1597 //! <b>For Media Surfaces:</b> 1598 //! This field specifies the tiled resource mode. 1599 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1600 { 1601 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1602 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1603 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1604 }; 1605 1606 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1607 //! \details 1608 //! This field controls the priority of arbitration used in the GAC/GAM 1609 //! pipeline for this surface. 1610 enum MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1611 { 1612 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1613 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1614 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1615 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1616 }; 1617 1618 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1619 //! \details 1620 //! This field controls if Intra Row Store is going to store inside Media 1621 //! Internal Storage or to LLC. 1622 enum MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1623 { 1624 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1625 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1626 }; 1627 1628 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1629 //! \details 1630 //! <b>For Media Surfaces:</b> 1631 //! This field specifies the tiled resource mode. 1632 enum MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1633 { 1634 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1635 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1636 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1637 }; 1638 1639 //! \brief BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1640 //! \details 1641 //! This field controls the priority of arbitration used in the GAC/GAM 1642 //! pipeline for this surface. 1643 enum BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1644 { 1645 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1646 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1647 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1648 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1649 }; 1650 1651 //! \brief BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1652 //! \details 1653 //! <b>For Media Surfaces:</b> 1654 //! This field specifies the tiled resource mode. 1655 enum BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1656 { 1657 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1658 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1659 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1660 }; 1661 1662 //! \name Initializations 1663 1664 //! \brief Explicit member initialization function 1665 MFX_BSP_BUF_BASE_ADDR_STATE_CMD(); 1666 1667 static const size_t dwSize = 10; 1668 static const size_t byteSize = 40; 1669 }; 1670 1671 //! 1672 //! \brief MFD_AVC_PICID_STATE 1673 //! \details 1674 //! This is a frame level state command used for both AVC Long and Short 1675 //! Format in VLD mode.PictureID[16] contains the pictureID of each 1676 //! reference picture (16 maximum) so hardware can uniquely identify the 1677 //! reference picture across frames (this will be used for DMV 1678 //! operation).This command will be needed for both short and long format. 1679 //! 1680 struct MFD_AVC_PICID_STATE_CMD 1681 { 1682 union 1683 { 1684 //!< DWORD 0 1685 struct 1686 { 1687 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1688 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1689 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1690 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1691 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1692 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1693 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1694 }; 1695 uint32_t Value; 1696 } DW0; 1697 union 1698 { 1699 //!< DWORD 1 1700 struct 1701 { 1702 uint32_t PictureidRemappingDisable : __CODEGEN_BITFIELD( 0, 0) ; //!< PICTUREID_REMAPPING_DISABLE 1703 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 1704 }; 1705 uint32_t Value; 1706 } DW1; 1707 1708 uint32_t Pictureidlist1616Bits[8]; //!< PictureIDList[16][16 bits] 1709 1710 1711 //! \name Local enumerations 1712 1713 enum SUBOPCODE_B 1714 { 1715 SUBOPCODE_B_MEDIA = 5, //!< No additional details 1716 }; 1717 1718 enum SUBOPCODE_A 1719 { 1720 SUBOPCODE_A_DEC = 1, //!< No additional details 1721 }; 1722 1723 enum MEDIA_COMMAND_OPCODE 1724 { 1725 MEDIA_COMMAND_OPCODE_MFDAVCDPBSTATE = 1, //!< No additional details 1726 }; 1727 1728 enum PIPELINE 1729 { 1730 PIPELINE_MFXMULTIDW = 2, //!< No additional details 1731 }; 1732 1733 enum COMMAND_TYPE 1734 { 1735 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1736 }; 1737 1738 //! \brief PICTUREID_REMAPPING_DISABLE 1739 //! \details 1740 //! If Picture ID Remapping Disable is "1", PictureIDList will not be used. 1741 enum PICTUREID_REMAPPING_DISABLE 1742 { 1743 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE16BITSPICTUREIDTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURE = 0, //!< Desc 1744 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE_4BITSFRAMESTOREIDINDEXTOREFFRAMELISTTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURETHISCAUSESDMVLOGICTOFUNCTIONTHESAMEINPROJECTIVBANDBEFORE = 1, //!< Desc 1745 }; 1746 1747 //! \name Initializations 1748 1749 //! \brief Explicit member initialization function 1750 MFD_AVC_PICID_STATE_CMD(); 1751 1752 static const size_t dwSize = 10; 1753 static const size_t byteSize = 40; 1754 }; 1755 1756 //! 1757 //! \brief MFX_AVC_IMG_STATE 1758 //! \details 1759 //! This must be the very first command to issue after the surface state, 1760 //! the pipe select and base address setting commands. This command supports 1761 //! both Long and Short VLD and IT AVC Decoding Interface. 1762 //! 1763 struct MFX_AVC_IMG_STATE_CMD 1764 { 1765 union 1766 { 1767 //!< DWORD 0 1768 struct 1769 { 1770 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1771 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1772 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1773 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1774 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1775 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1776 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1777 }; 1778 uint32_t Value; 1779 } DW0; 1780 union 1781 { 1782 //!< DWORD 1 1783 struct 1784 { 1785 uint32_t FrameSize : __CODEGEN_BITFIELD( 0, 15) ; //!< Frame Size 1786 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1787 }; 1788 uint32_t Value; 1789 } DW1; 1790 union 1791 { 1792 //!< DWORD 2 1793 struct 1794 { 1795 uint32_t FrameWidth : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Width 1796 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1797 uint32_t FrameHeight : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Height 1798 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1799 }; 1800 uint32_t Value; 1801 } DW2; 1802 union 1803 { 1804 //!< DWORD 3 1805 struct 1806 { 1807 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1808 uint32_t ImgstructImageStructureImgStructure10 : __CODEGEN_BITFIELD( 8, 9) ; //!< IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 1809 uint32_t WeightedBipredIdc : __CODEGEN_BITFIELD(10, 11) ; //!< WEIGHTED_BIPRED_IDC 1810 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(12, 12) ; //!< WEIGHTED_PRED_FLAG 1811 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD(13, 13) ; //!< RHODOMAIN_RATE_CONTROL_ENABLE 1812 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1813 uint32_t FirstChromaQpOffset : __CODEGEN_BITFIELD(16, 20) ; //!< First Chroma QP Offset 1814 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 1815 uint32_t SecondChromaQpOffset : __CODEGEN_BITFIELD(24, 28) ; //!< Second Chroma QP Offset 1816 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1817 }; 1818 uint32_t Value; 1819 } DW3; 1820 union 1821 { 1822 //!< DWORD 4 1823 struct 1824 { 1825 uint32_t Fieldpicflag : __CODEGEN_BITFIELD( 0, 0) ; //!< FIELDPICFLAG 1826 uint32_t Mbaffflameflag : __CODEGEN_BITFIELD( 1, 1) ; //!< MBAFFFLAMEFLAG 1827 uint32_t Framembonlyflag : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMEMBONLYFLAG 1828 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD( 3, 3) ; //!< TRANSFORM8X8FLAG 1829 uint32_t Direct8X8Infflag : __CODEGEN_BITFIELD( 4, 4) ; //!< DIRECT8X8INFFLAG 1830 uint32_t Constrainedipredflag : __CODEGEN_BITFIELD( 5, 5) ; //!< CONSTRAINEDIPREDFLAG 1831 uint32_t Imgdisposableflag : __CODEGEN_BITFIELD( 6, 6) ; //!< IMGDISPOSABLEFLAG 1832 uint32_t Entropycodingflag : __CODEGEN_BITFIELD( 7, 7) ; //!< ENTROPYCODINGFLAG 1833 uint32_t Mbmvformatflag : __CODEGEN_BITFIELD( 8, 8) ; //!< MBMVFORMATFLAG 1834 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1835 uint32_t Chromaformatidc : __CODEGEN_BITFIELD(10, 11) ; //!< CHROMAFORMATIDC 1836 uint32_t Mvunpackedflag : __CODEGEN_BITFIELD(12, 12) ; //!< MVUNPACKEDFLAG 1837 uint32_t Reserved141 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 1838 uint32_t Loadslicepointerflag : __CODEGEN_BITFIELD(14, 14) ; //!< LOADSLICEPOINTERFLAG 1839 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15) ; //!< MBSTATENABLED 1840 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31) ; //!< MINFRAMEWSIZE 1841 }; 1842 uint32_t Value; 1843 } DW4; 1844 union 1845 { 1846 //!< DWORD 5 1847 struct 1848 { 1849 uint32_t IntrambmaxbitflagIntrambmaxsizereportmask : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 1850 uint32_t IntermbmaxbitflagIntermbmaxsizereportmask : __CODEGEN_BITFIELD( 1, 1) ; //!< INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 1851 uint32_t FrameszoverflagFramebitratemaxreportmask : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 1852 uint32_t FrameszunderflagFramebitrateminreportmask : __CODEGEN_BITFIELD( 3, 3) ; //!< FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 1853 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 6) ; //!< Reserved 1854 uint32_t IntraIntermbipcmflagForceipcmcontrolmask : __CODEGEN_BITFIELD( 7, 7) ; //!< INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 1855 uint32_t Reserved168 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 1856 uint32_t MbratectrlflagMbLevelRateControlEnablingFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 1857 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11) ; //!< MINFRAMEWSIZEUNITS 1858 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1859 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 1860 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 26) ; //!< Reserved 1861 uint32_t TrellisQuantizationChromaDisableTqchromadisable : __CODEGEN_BITFIELD(27, 27) ; //!< TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 1862 uint32_t TrellisQuantizationRoundingTqr : __CODEGEN_BITFIELD(28, 30) ; //!< TRELLIS_QUANTIZATION_ROUNDING_TQR 1863 uint32_t TrellisQuantizationEnabledTqenb : __CODEGEN_BITFIELD(31, 31) ; //!< TRELLIS_QUANTIZATION_ENABLED_TQENB 1864 }; 1865 uint32_t Value; 1866 } DW5; 1867 union 1868 { 1869 //!< DWORD 6 1870 struct 1871 { 1872 uint32_t Intrambmaxsz : __CODEGEN_BITFIELD( 0, 11) ; //!< IntraMbMaxSz 1873 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1874 uint32_t Intermbmaxsz : __CODEGEN_BITFIELD(16, 27) ; //!< InterMbMaxSz 1875 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1876 }; 1877 uint32_t Value; 1878 } DW6; 1879 union 1880 { 1881 //!< DWORD 7 1882 struct 1883 { 1884 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSL_TOP_MB_TRANS8X8FLAG 1885 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 15) ; //!< Reserved 1886 uint32_t BspEncoderEcoEnable : __CODEGEN_BITFIELD(16, 16) ; //!< BSP_ENCODER_ECO_ENABLE 1887 uint32_t Reserved241 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1888 }; 1889 uint32_t Value; 1890 } DW7; 1891 union 1892 { 1893 //!< DWORD 8 1894 struct 1895 { 1896 uint32_t Slicedeltaqppmax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQpPMax[0] 1897 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQpMax[1] 1898 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQpMax[2] 1899 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQpMax[3] 1900 }; 1901 uint32_t Value; 1902 } DW8; 1903 union 1904 { 1905 //!< DWORD 9 1906 struct 1907 { 1908 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQpMin[0] 1909 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQpMin[1] 1910 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQpMin[2] 1911 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQpMin[3] 1912 }; 1913 uint32_t Value; 1914 } DW9; 1915 union 1916 { 1917 //!< DWORD 10 1918 struct 1919 { 1920 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1921 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14) ; //!< FRAMEBITRATEMINUNITMODE 1922 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15) ; //!< FRAMEBITRATEMINUNIT 1923 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29) ; //!< FrameBitRateMax 1924 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30) ; //!< FRAMEBITRATEMAXUNITMODE 1925 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT_ 1926 }; 1927 uint32_t Value; 1928 } DW10; 1929 union 1930 { 1931 //!< DWORD 11 1932 struct 1933 { 1934 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FrameBitRateMinDelta 1935 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1936 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1937 uint32_t SliceStatsStreamoutEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Slice Stats Streamout Enable 1938 }; 1939 uint32_t Value; 1940 } DW11; 1941 union 1942 { 1943 //!< DWORD 12 1944 struct 1945 { 1946 uint32_t Reserved384 ; //!< Reserved 1947 }; 1948 uint32_t Value; 1949 } DW12; 1950 union 1951 { 1952 //!< DWORD 13 1953 struct 1954 { 1955 uint32_t InitialQpValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Initial QP Value 1956 uint32_t NumberOfActiveReferencePicturesFromL0 : __CODEGEN_BITFIELD( 8, 13) ; //!< Number of Active Reference Pictures from L0 1957 uint32_t Reserved430 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1958 uint32_t NumberOfActiveReferencePicturesFromL1 : __CODEGEN_BITFIELD(16, 21) ; //!< Number of Active Reference Pictures from L1 1959 uint32_t Reserved438 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 1960 uint32_t NumberOfReferenceFrames : __CODEGEN_BITFIELD(24, 28) ; //!< Number of Reference Frames 1961 uint32_t CurrentPictureHasPerformedMmco5 : __CODEGEN_BITFIELD(29, 29) ; //!< Current Picture Has Performed MMCO5 1962 uint32_t Reserved446 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1963 }; 1964 uint32_t Value; 1965 } DW13; 1966 union 1967 { 1968 //!< DWORD 14 1969 struct 1970 { 1971 uint32_t PicOrderPresentFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< Pic_order_present_flag 1972 uint32_t DeltaPicOrderAlwaysZeroFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< Delta_pic_order_always_zero_flag 1973 uint32_t PicOrderCntType : __CODEGEN_BITFIELD( 2, 3) ; //!< Pic_order_cnt_type 1974 uint32_t Reserved452 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 1975 uint32_t SliceGroupMapType : __CODEGEN_BITFIELD( 8, 10) ; //!< slice_group_map_type 1976 uint32_t RedundantPicCntPresentFlag : __CODEGEN_BITFIELD(11, 11) ; //!< redundant_pic_cnt_present_flag 1977 uint32_t NumSliceGroupsMinus1 : __CODEGEN_BITFIELD(12, 14) ; //!< num_slice_groups_minus1 1978 uint32_t DeblockingFilterControlPresentFlag : __CODEGEN_BITFIELD(15, 15) ; //!< deblocking_filter_control_present_flag 1979 uint32_t Log2MaxFrameNumMinus4 : __CODEGEN_BITFIELD(16, 23) ; //!< Log2_max_frame_num_minus4 1980 uint32_t Log2MaxPicOrderCntLsbMinus4 : __CODEGEN_BITFIELD(24, 31) ; //!< Log2_max_pic_order_cnt_lsb_minus4 1981 }; 1982 uint32_t Value; 1983 } DW14; 1984 union 1985 { 1986 //!< DWORD 15 1987 struct 1988 { 1989 uint32_t SliceGroupChangeRate : __CODEGEN_BITFIELD( 0, 15) ; //!< Slice Group Change Rate 1990 uint32_t CurrPicFrameNum : __CODEGEN_BITFIELD(16, 31) ; //!< Curr Pic Frame Num 1991 }; 1992 uint32_t Value; 1993 } DW15; 1994 union 1995 { 1996 //!< DWORD 16 1997 struct 1998 { 1999 uint32_t CurrentFrameViewId : __CODEGEN_BITFIELD( 0, 9) ; //!< Current Frame View ID 2000 uint32_t Reserved522 : __CODEGEN_BITFIELD(10, 11) ; //!< Reserved 2001 uint32_t MaxViewIdxl0 : __CODEGEN_BITFIELD(12, 15) ; //!< Max View IDXL0 2002 uint32_t Reserved528 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 2003 uint32_t MaxViewIdxl1 : __CODEGEN_BITFIELD(18, 21) ; //!< Max View IDXL1 2004 uint32_t Reserved534 : __CODEGEN_BITFIELD(22, 30) ; //!< Reserved 2005 uint32_t InterViewOrderDisable : __CODEGEN_BITFIELD(31, 31) ; //!< INTER_VIEW_ORDER_DISABLE 2006 }; 2007 uint32_t Value; 2008 } DW16; 2009 union 2010 { 2011 //!< DWORD 17 2012 struct 2013 { 2014 uint32_t FractionalQpInput : __CODEGEN_BITFIELD( 0, 2) ; //!< Fractional QP input 2015 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD( 3, 5) ; //!< Fractional QP offset 2016 uint32_t Reserved550 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 2017 uint32_t ExtendedRhodomainStatisticsEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Extended RhoDomain Statistics Enable 2018 uint32_t Reserved553 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2019 uint32_t RhodomainAveragemacroblockqp : __CODEGEN_BITFIELD(16, 21) ; //!< RhoDomain AverageMacroblockQP 2020 uint32_t Reserved566 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 2021 }; 2022 uint32_t Value; 2023 } DW17; 2024 union 2025 { 2026 //!< DWORD 18 2027 struct 2028 { 2029 uint32_t Reserved576 ; //!< Reserved 2030 }; 2031 uint32_t Value; 2032 } DW18; 2033 union 2034 { 2035 //!< DWORD 19 2036 struct 2037 { 2038 uint32_t ThresholdSizeInBytes ; //!< Threshold Size in Bytes 2039 }; 2040 uint32_t Value; 2041 } DW19; 2042 union 2043 { 2044 //!< DWORD 20 2045 struct 2046 { 2047 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 2048 }; 2049 uint32_t Value; 2050 } DW20; 2051 2052 //! \name Local enumerations 2053 2054 enum SUBOPCODE_B 2055 { 2056 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 2057 }; 2058 2059 enum SUBOPCODE_A 2060 { 2061 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2062 }; 2063 2064 enum MEDIA_COMMAND_OPCODE 2065 { 2066 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2067 }; 2068 2069 enum PIPELINE 2070 { 2071 PIPELINE_MFXAVCIMGSTATE = 2, //!< No additional details 2072 }; 2073 2074 enum COMMAND_TYPE 2075 { 2076 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2077 }; 2078 2079 //! \brief IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 2080 //! \details 2081 //! The current encoding picture structure can only takes on 3 possible 2082 //! values 2083 enum IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 2084 { 2085 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_FRAMEPICTURE = 0, //!< No additional details 2086 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_TOPFIELDPICTURE = 1, //!< No additional details 2087 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_INVALID_NOTALLOWED = 2, //!< No additional details 2088 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_BOTTOMFIELDPICTURE = 3, //!< No additional details 2089 }; 2090 2091 //! \brief WEIGHTED_BIPRED_IDC 2092 //! \details 2093 //! (This field is defined differently from DevSNB; DevIVB follows strictly 2094 //! AVC interface.) 2095 enum WEIGHTED_BIPRED_IDC 2096 { 2097 WEIGHTED_BIPRED_IDC_DEFAULT = 0, //!< Specifies that the default weighted prediction is used for B slices 2098 WEIGHTED_BIPRED_IDC_EXPLICIT = 1, //!< Specifies that explicit weighted prediction is used for B slices 2099 WEIGHTED_BIPRED_IDC_IMPLICIT = 2, //!< Specifies that implicit weighted prediction is used for B slices. 2100 }; 2101 2102 //! \brief WEIGHTED_PRED_FLAG 2103 //! \details 2104 //! (This field is defined differently from Gen6, Gen7 follows strictly 2105 //! AVC interface.) 2106 enum WEIGHTED_PRED_FLAG 2107 { 2108 WEIGHTED_PRED_FLAG_DISABLE = 0, //!< specifies that weighted prediction is not used for P and SP slices 2109 WEIGHTED_PRED_FLAG_ENABLE = 1, //!< specifies that weighted prediction is used for P and SP slices 2110 }; 2111 2112 //! \brief RHODOMAIN_RATE_CONTROL_ENABLE 2113 //! \details 2114 //! This field indicates if RhoDomain related parameters are present in the 2115 //! MFX_AVC_IMAGE_STATE. (AverageMacroblockQP). It enables the Rho Domain 2116 //! statistics collection. 2117 enum RHODOMAIN_RATE_CONTROL_ENABLE 2118 { 2119 RHODOMAIN_RATE_CONTROL_ENABLE_DISABLE = 0, //!< RhoDomain rate control parameters are not present in MFX_AVC_IMAGE_STATE 2120 RHODOMAIN_RATE_CONTROL_ENABLE_ENABLE = 1, //!< RhoDomain rate control parameters are present in MFX_AVC_IMAGE_STATE. 2121 }; 2122 2123 //! \brief FIELDPICFLAG 2124 //! \details 2125 //! Field picture flag, field_pic_flag, specifies the current slice is a 2126 //! coded field or not.It is set to the same value as the syntax element in 2127 //! the Slice Header. It must be consistent with the img_structure[1:0] and 2128 //! the frame_mbs_only_flag settings.Although field_pic_flag is a Slice 2129 //! Header parameter, its value is expected to be the same for all the 2130 //! slices of a picture. 2131 enum FIELDPICFLAG 2132 { 2133 FIELDPICFLAG_FRAME = 0, //!< a slice of a coded frame 2134 FIELDPICFLAG_FIELD = 1, //!< a slice of a coded field 2135 }; 2136 2137 //! \brief MBAFFFLAMEFLAG 2138 //! \details 2139 //! MBAFF mode is active, mbaff_frame_flag.It is derived from MbaffFrameFlag 2140 //! = (mb_adaptive_frame_field_flag && ! field_pic_flag ). 2141 //! mb_adaptive_frame_field_flag is a syntax element in the current active 2142 //! SPS and field_pic_flag is a syntax element in the current Slice Header. 2143 //! They both are present only if frame_mbs_only_flag is 0. Although 2144 //! mbaff_frame_flag is a Slice Header parameter, its value is expected to 2145 //! be the same for all the slices of a picture.It must be consistent with 2146 //! the mb_adaptive_frame_field_flag, the field_pic_flag and the 2147 //! frame_mbs_only_flag settings.This bit is valid only when the 2148 //! img_structure[1:0] indicates the current picture is a frame. 2149 enum MBAFFFLAMEFLAG 2150 { 2151 MBAFFFLAMEFLAG_FALSE = 0, //!< not in MBAFF mode 2152 MBAFFFLAMEFLAG_TRUE = 1, //!< in MBAFF mode 2153 }; 2154 2155 //! \brief FRAMEMBONLYFLAG 2156 //! \details 2157 //! Frame MB only flag, frame_mbs_only_flagIt is set to the value of the 2158 //! syntax element in the current active SPS. 2159 enum FRAMEMBONLYFLAG 2160 { 2161 FRAMEMBONLYFLAG_FALSE = 0, //!< not true ; effectively enables the possibility of MBAFF mode. 2162 FRAMEMBONLYFLAG_TRUE = 1, //!< true, only frame MBs can occur in this sequence, hence disallows the MBAFF mode and field picture. 2163 }; 2164 2165 //! \brief TRANSFORM8X8FLAG 2166 //! \details 2167 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flagSpecifies 8x8 IDCT 2168 //! transform may be used in this pictureIt is set to the value of the 2169 //! syntax element in the current active PPS. 2170 enum TRANSFORM8X8FLAG 2171 { 2172 TRANSFORM8X8FLAG_4X_4 = 0, //!< no 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present 2173 TRANSFORM8X8FLAG_8X8 = 1, //!< 8x8 Transform is allowed 2174 }; 2175 2176 //! \brief DIRECT8X8INFFLAG 2177 //! \details 2178 //! Direct 8x8 Inference Flag, direct_8x8_inference_flagIt is set to the 2179 //! value of the syntax element in the current active SPS.It specifies the 2180 //! derivation process for luma motion vectors in the Direct MV coding modes 2181 //! (B_Skip, B_Direct_16x16 and B_Direct_8x8). When frame_mbs_only_flag is 2182 //! equal to 0, direct_8x8_inference_flag shall be equal to 1.It must be 2183 //! consistent with the frame_mbs_only_flag and transform_8x8_mode_flag 2184 //! settings. 2185 enum DIRECT8X8INFFLAG 2186 { 2187 DIRECT8X8INFFLAG_SUBBLOCK = 0, //!< allows subpartitioning to go below 8x8 block size (i.e. 4x4, 8x4 or 4x8) 2188 DIRECT8X8INFFLAG_BLOCK = 1, //!< allows processing only at 8x8 block size. MB Info is stored for 8x8 block size. 2189 }; 2190 2191 //! \brief CONSTRAINEDIPREDFLAG 2192 //! \details 2193 //! Constrained Intra Prediction Flag, constrained_ipred_flagIt is set to 2194 //! the value of the syntax element in the current active PPS. 2195 enum CONSTRAINEDIPREDFLAG 2196 { 2197 CONSTRAINEDIPREDFLAG_INTRAANDINTER = 0, //!< allows both intra and inter neighboring MB to be used in the intra-prediction encoding of the current MB. 2198 CONSTRAINEDIPREDFLAG_INTRAONLY = 1, //!< allows only to use neighboring Intra MBs in the intra-prediction encoding of the current MB. If the neighbor is an inter MB, it is considered as not available. 2199 }; 2200 2201 //! \brief IMGDISPOSABLEFLAG 2202 //! \details 2203 //! Current Img Disposable Flag or Non-Reference Picture Flag 2204 enum IMGDISPOSABLEFLAG 2205 { 2206 IMGDISPOSABLEFLAG_REFERENCE = 0, //!< the current decoding picture may be used as a reference picture for others 2207 IMGDISPOSABLEFLAG_DISPOSABLE = 1, //!< the current decoding picture is not used as a reference picture (e.g. a B-picture cannot be a reference picture for any subsequent decoding) 2208 }; 2209 2210 //! \brief ENTROPYCODINGFLAG 2211 //! \details 2212 //! Entropy Coding Flag, entropy_coding_flag 2213 enum ENTROPYCODINGFLAG 2214 { 2215 ENTROPYCODINGFLAG_CAVLCBIT_SERIALENCODINGMODE = 0, //!< Desc 2216 ENTROPYCODINGFLAG_CABACBIT_SERIALENCODINGMODE = 1, //!< Desc 2217 }; 2218 2219 //! \brief MBMVFORMATFLAG 2220 //! \details 2221 //! Use MB level MvFormat flag (Encoder Only)(This bit must be set to zero 2222 //! in IVB:GT2:A0) 2223 enum MBMVFORMATFLAG 2224 { 2225 MBMVFORMATFLAG_IGNORE = 0, //!< HW PAK ignore MvFormat in the MB data. When bit 12 == 0, all MBs use packed MV formatWhen bit 12 == 1, each MB data must use unpacked MV format, 8MV when there is no minor MV involved, and 32MV if there are some minor motion vector. 2226 MBMVFORMATFLAG_FOLLOW = 1, //!< HW PAK will follow MvFormat value set within each MB data. 2227 }; 2228 2229 //! \brief CHROMAFORMATIDC 2230 //! \details 2231 //! Chroma Format IDC, ChromaFormatIdc[1:0]It specifies the sampling of 2232 //! chroma component (Cb, Cr) in the current picture as follows : 2233 enum CHROMAFORMATIDC 2234 { 2235 CHROMAFORMATIDC_MONOCHROMEPICTURE = 0, //!< Desc 2236 CHROMAFORMATIDC_420PICTURE = 1, //!< Desc 2237 CHROMAFORMATIDC_422PICTURENOTSUPPORTED = 2, //!< No additional details 2238 CHROMAFORMATIDC_4_4_4PICTURENOTSUPPORTED = 3, //!< No additional details 2239 }; 2240 2241 //! \brief MVUNPACKEDFLAG 2242 //! \details 2243 //! MVUnPackedEnable (Encoder Only)This field is reserved in Decode mode. 2244 enum MVUNPACKEDFLAG 2245 { 2246 MVUNPACKEDFLAG_PACKED = 0, //!< use packed MV format 2247 MVUNPACKEDFLAG_UNPACKED = 1, //!< use unpacked 8MV/32MV format only 2248 }; 2249 2250 //! \brief LOADSLICEPOINTERFLAG 2251 //! \details 2252 //! LoadBitStreamPointerPerSlice (Encoder-only)To support multiple slice 2253 //! picture and additional header/data insertion before and after an encoded 2254 //! slice.When this field is set to 0, bitstream pointer is only loaded once 2255 //! for the first slice of a frame. For subsequent slices in the frame, 2256 //! bitstream data are stitched together to form a single output data 2257 //! stream.When this field is set to 1, bitstream pointer is loaded for each 2258 //! slice of a frame. Basically bitstream data for different slices of a 2259 //! frame will be written to different memory locations. 2260 enum LOADSLICEPOINTERFLAG 2261 { 2262 LOADSLICEPOINTERFLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame 2263 LOADSLICEPOINTERFLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 2264 }; 2265 2266 //! \brief MBSTATENABLED 2267 //! \details 2268 //! <p>Enable reading in MB status buffer (a.k.a. encoding stream-out 2269 //! buffer) Note: For multi-pass encoder, all passes except the first one 2270 //! need to set this value to 1. By setting the first pass to 0, it does 2271 //! save some memory bandwidth.</p> 2272 //! <p><span style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 2273 //! line-height: normal;">In VDenc mode this must be set to zero as no MB 2274 //! level rate control is used. </span></p> 2275 enum MBSTATENABLED 2276 { 2277 MBSTATENABLED_DISABLE = 0, //!< Disable Reading of Macroblock Status Buffer 2278 MBSTATENABLED_ENABLE = 1, //!< Enable Reading of Macroblock Status Buffer 2279 }; 2280 2281 //! \brief MINFRAMEWSIZE 2282 //! \details 2283 //! <p><b>Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)</b> 2284 //! Mininum Frame Size is specified to compensate for intel Rate 2285 //! Control Currently zero fill (no need to perform emulation byte 2286 //! insertion) is done 2287 //! only to the end of the CABAC_ZERO_WORD insertion (if any) at the 2288 //! last slice of a 2289 //! picture. Intel encoder parameter. The caller 2290 //! should always make 2291 //! sure that the value, represented by Mininum Frame Size, is always 2292 //! less than maximum 2293 //! frame size <b>FrameBitRateMax (DWORD 10 bits</b> 29:16).This field 2294 //! is reserved in 2295 //! Decode mode.</p> 2296 //! <p>The programmable range 0…2^18-1</p> 2297 //! <p>When MinFrameWSizeUnits is 00.</p> 2298 //! <p>Programmable range is 0…2^20-1 when MinFrameWSizeUnits is 2299 //! 01.</p> 2300 //! <p>Programmable range is 0…2^26-1 when MinFrameWSizeUnits is 2301 //! 10.</p> 2302 //! <p>Programmable range is 0…2^32-1 when MinFrameWSizeUnits is 2303 //! 11.</p> 2304 enum MINFRAMEWSIZE 2305 { 2306 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 2307 }; 2308 2309 //! \brief INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 2310 //! \details 2311 //! This is a mask bit controlling if the condition of any intra MB in the 2312 //! frame exceeds IntraMBMaxSize. 2313 enum INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 2314 { 2315 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2316 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_ENABLE = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 2317 }; 2318 2319 //! \brief INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 2320 //! \details 2321 //! This is a mask bit controlling if the condition of any inter MB in the 2322 //! frame exceeds InterMBMaxSize. 2323 enum INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 2324 { 2325 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2326 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_ENABLE = 1, //!< Set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 2327 }; 2328 2329 //! \brief FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 2330 //! \details 2331 //! This is a mask bit controlling if the condition of frame level bit count 2332 //! exceeds FrameBitRateMax. 2333 enum FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 2334 { 2335 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2336 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 2337 }; 2338 2339 //! \brief FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 2340 //! \details 2341 //! This is a mask bit controlling if the condition of frame level bit count 2342 //! is less than FrameBitRateMin 2343 enum FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 2344 { 2345 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2346 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 2347 }; 2348 2349 //! \brief INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 2350 //! \details 2351 //! This field is to Force <b>IPCM</b> for Intra or Inter Macroblock size 2352 //! conformance mask. 2353 enum INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 2354 { 2355 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_DISABLE = 0, //!< Do not change intra or Inter macroblocks even 2356 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_ENABLE = 1, //!< Change intra or Inter macroblocks MB_type to IPCM 2357 }; 2358 2359 //! \brief MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2360 //! \details 2361 //! <p>MB Rate Control conformance mask</p> 2362 //! <p>In VDenc mode, this field must be zero as frame level rate control is 2363 //! used.</p> 2364 enum MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2365 { 2366 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_DISABLE = 0, //!< Apply accumulative delta QP for consecutive passes on top of the macroblock QP values in inline data 2367 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_ENABLE = 1, //!< Apply RC QP delta to suggested QP values in Macroblock Status Buffer except the first pass. 2368 }; 2369 2370 //! \brief MINFRAMEWSIZEUNITS 2371 //! \details 2372 //! This field is the Minimum Frame Size Units 2373 enum MINFRAMEWSIZEUNITS 2374 { 2375 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 2376 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 2377 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 2378 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 2379 }; 2380 2381 //! \brief NONFIRSTPASSFLAG 2382 //! \details 2383 //! This signals the current pass is not the first pass. It will imply 2384 //! designate HW behavior: e.g 2385 enum NONFIRSTPASSFLAG 2386 { 2387 NONFIRSTPASSFLAG_DISABLE = 0, //!< Always use the MbQpY from initial PAK inline object for all passes of PAK 2388 NONFIRSTPASSFLAG_ENABLE = 1, //!< Use MbQpY from stream-out buffer if MbRateCtrlFlag is set to 1 2389 }; 2390 2391 //! \brief TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2392 //! \details 2393 //! This signal is used to disable chroma TQ. To enable TQ for both luma and 2394 //! chroma, TQEnb=1, TQChromaDisable=0. To enable TQ only for luma, TQEnb=1, 2395 //! TQChromaDisable=1. 2396 enum TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2397 { 2398 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_UNNAMED0 = 0, //!< Enable Trellis Quantization chroma 2399 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_DEFAULT = 1, //!< Disable Trellis Quantization chroma 2400 }; 2401 2402 //! \brief TRELLIS_QUANTIZATION_ROUNDING_TQR 2403 //! \details 2404 //! This rounding scheme is only applied to the quantized coefficients 2405 //! ranging from 0 to 1 when TQEnb is set to 1 in AVC CABAC mode. One of the 2406 //! following values is added to quantized coefficients before truncating 2407 //! fractional part. 2408 enum TRELLIS_QUANTIZATION_ROUNDING_TQR 2409 { 2410 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED0 = 0, //!< Add 1/8 2411 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED1 = 1, //!< Add 2/8 2412 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED2 = 2, //!< Add 3/8 2413 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED3 = 3, //!< Add 4/8 (rounding 0.5) 2414 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED_4 = 4, //!< Add 5/8 2415 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED5 = 5, //!< Add 6/8 2416 TRELLIS_QUANTIZATION_ROUNDING_TQR_DEFAULT = 6, //!< Add 7/8 (Default rounding 0.875) 2417 }; 2418 2419 //! \brief TRELLIS_QUANTIZATION_ENABLED_TQENB 2420 //! \details 2421 //! The TQ improves output video quality of AVC CABAC encoder by selecting 2422 //! quantized values for each non-zero coefficient so as to minimize the 2423 //! total R-D cost.This flag is only valid AVC CABAC mode. Otherwise, this 2424 //! flag should be disabled. 2425 enum TRELLIS_QUANTIZATION_ENABLED_TQENB 2426 { 2427 TRELLIS_QUANTIZATION_ENABLED_TQENB_DISABLE = 0, //!< Use Normal 2428 TRELLIS_QUANTIZATION_ENABLED_TQENB_ENABLE = 1, //!< Use Trellis quantization 2429 }; 2430 2431 enum VSL_TOP_MB_TRANS8X8FLAG 2432 { 2433 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 2434 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 2435 }; 2436 2437 //! \brief BSP_ENCODER_ECO_ENABLE 2438 //! \details 2439 //! <p>Enable AVC Encoder BSP Bit Outstanding ECO</p> 2440 //! <p>This bit must be same as bit9 of Dword2 of MFX_PIPE_MODE_SELECT</p> 2441 enum BSP_ENCODER_ECO_ENABLE 2442 { 2443 BSP_ENCODER_ECO_ENABLE_DISABLE = 0, //!< No additional details 2444 BSP_ENCODER_ECO_ENABLE_ENABLE = 1, //!< No additional details 2445 }; 2446 2447 //! \brief FRAMEBITRATEMINUNITMODE 2448 //! \details 2449 //! This field is the Frame Bitrate Minimum Limit Units. 2450 enum FRAMEBITRATEMINUNITMODE 2451 { 2452 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2453 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2454 }; 2455 2456 //! \brief FRAMEBITRATEMINUNIT 2457 //! \details 2458 //! This field is the Frame Bitrate Minimum Limit Units. 2459 enum FRAMEBITRATEMINUNIT 2460 { 2461 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 2462 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2463 }; 2464 2465 //! \brief FRAMEBITRATEMAXUNITMODE 2466 //! \details 2467 //! This field is the Frame Bitrate Maximum Limit Units. 2468 enum FRAMEBITRATEMAXUNITMODE 2469 { 2470 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2471 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2472 }; 2473 2474 //! \brief FRAMEBITRATEMAXUNIT_ 2475 //! \details 2476 //! This field is the Frame Bitrate Maximum Limit Units. 2477 enum FRAMEBITRATEMAXUNIT_ 2478 { 2479 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 2480 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2481 }; 2482 2483 //! \brief FRAMEBITRATEMAXDELTA 2484 //! \details 2485 //! This field is used to select the slice delta QP when FrameBitRateMax Is 2486 //! exceeded. It shares the same FrameBitrateMaxUnit. When 2487 //! FrameBitrateMaxUnitMode is 0(compatibility mode) bits 16:27 should be 2488 //! used, bits 28, 29 and 30 should be 0. 2489 enum FRAMEBITRATEMAXDELTA 2490 { 2491 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 2492 }; 2493 2494 enum VAD_ERROR_LOGIC 2495 { 2496 VAD_ERROR_LOGIC_ENABLE = 0, //!< Error reporting ON in case of premature Slice done 2497 VAD_ERROR_LOGIC_DISABLE = 1, //!< CABAC Engine will auto decode the bitstream in case of premature slice done. 2498 }; 2499 2500 //! \brief INTER_VIEW_ORDER_DISABLE 2501 //! \details 2502 //! It indicates how to append inter-view picture into initial sorted 2503 //! reference list. (due to ambiguity in the MVC Spec) 2504 enum INTER_VIEW_ORDER_DISABLE 2505 { 2506 INTER_VIEW_ORDER_DISABLE_DEFAULT = 0, //!< View Order Ascending 2507 INTER_VIEW_ORDER_DISABLE_DISABLE = 1, //!< View ID Ascending 2508 }; 2509 2510 //! \name Initializations 2511 2512 //! \brief Explicit member initialization function 2513 MFX_AVC_IMG_STATE_CMD(); 2514 2515 static const size_t dwSize = 21; 2516 static const size_t byteSize = 84; 2517 }; 2518 2519 //! 2520 //! \brief MFX_AVC_REF_IDX_STATE 2521 //! \details 2522 //! This is a slice level command and can be issued multiple times within a 2523 //! picture that is comprised of multiple slices. The same command is used 2524 //! for AVC encoder (PAK mode) and decoder (VLD mode); it is not need in 2525 //! decoder IT mode. The inline data of this command is interpreted 2526 //! differently for encoder as for decoder. For decoder, it is interpreted 2527 //! as RefIdx List L0/L1 as in AVC spec., and it matches with the AVC 2528 //! API data structure for decoder in VLD mode : RefPicList[2][32] (L0:L1, 2529 //! 0:31 RefPic). But for encoder, it is interpreted as a Reference Index 2530 //! Mapping Table for L0 and L1 reference pictures. For packing the bits at 2531 //! the output of PAK, the syntax elements must follow the definition of 2532 //! RefIdxL0/L1 list according to the AVC spec. However, the decoder 2533 //! pipeline was designed to use a variation of that standard definition, as 2534 //! such a conversion (mapping) is needed to support the hardware design. 2535 //! The Reference lists are needed in processing both P and B slice in AVC 2536 //! codec. For P-MB, only L0 list is used; for B-MB both L0 and L1 lists are 2537 //! needed. For a B-MB that is coded in L1-only Prediction, only L1 list is 2538 //! used. 2539 //! 2540 //! Specifies that an application will create the RefPicList L0 and L1 2541 //! and pass onto the driver. The content of each entry of RefPicList 2542 //! L0/L1[ ] is a 7-bit picture index. This picture index is the same as 2543 //! that of RefFrameList[ ] content. This picture index, however, is not 2544 //! defined the same as the frame store ID (0 to 16, 5-bits) we have 2545 //! implemented in H/W. Hence, driver is required to manage a table to 2546 //! convert between picture index and intel frame store ID. As such, 2547 //! the final RefPicList L0/L1[ ] that the driver passes onto the H/W is not 2548 //! the same as that defined. 2549 //! 2550 struct MFX_AVC_REF_IDX_STATE_CMD 2551 { 2552 union 2553 { 2554 //!< DWORD 0 2555 struct 2556 { 2557 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2558 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2559 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2560 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 2561 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 2562 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2563 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2564 }; 2565 uint32_t Value; 2566 } DW0; 2567 union 2568 { 2569 //!< DWORD 1 2570 struct 2571 { 2572 uint32_t RefpiclistSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLIST_SELECT 2573 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2574 }; 2575 uint32_t Value; 2576 } DW1; 2577 2578 uint32_t ReferenceListEntry[8]; //!< Reference List Entry 2579 2580 2581 //! \name Local enumerations 2582 2583 enum SUBOPCODEB 2584 { 2585 SUBOPCODEB_MFXAVCREFIDXSTATE = 4, //!< No additional details 2586 }; 2587 2588 enum SUBOPCODEA 2589 { 2590 SUBOPCODEA_MFXAVCREFIDXSTATE = 0, //!< No additional details 2591 }; 2592 2593 enum COMMAND_OPCODE 2594 { 2595 COMMAND_OPCODE_AVC = 1, //!< No additional details 2596 }; 2597 2598 enum PIPELINE 2599 { 2600 PIPELINE_MFXAVCREFIDXSTATE = 2, //!< No additional details 2601 }; 2602 2603 enum COMMAND_TYPE 2604 { 2605 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2606 }; 2607 2608 //! \brief REFPICLIST_SELECT 2609 //! \details 2610 //! <p>Num_ref_idx_l1_active is resulted from the specifications in both PPS 2611 //! and Slice Header for the current slice. However, since the full 2612 //! reference list L0 and/or L1 are always sent, only present flags are 2613 //! specified instead.</p> 2614 //! <p>This parameter is specified for Intel interface only.</p> 2615 enum REFPICLIST_SELECT 2616 { 2617 REFPICLIST_SELECT_REFPICLIST0 = 0, //!< The list that followed represents RefList L0 (Decoder VLD mode) or Ref Idx Mapping Table L0 (Encoder PAK mode) 2618 REFPICLIST_SELECT_REFPICLIST1 = 1, //!< The list that followed represents RefList L1 (Decoder VLD mode) or Ref Idx Mapping Table L1 (Encoder PAK mode) 2619 }; 2620 2621 //! \name Initializations 2622 2623 //! \brief Explicit member initialization function 2624 MFX_AVC_REF_IDX_STATE_CMD(); 2625 2626 static const size_t dwSize = 10; 2627 static const size_t byteSize = 40; 2628 }; 2629 2630 //! 2631 //! \brief MFX_AVC_WEIGHTOFFSET_STATE 2632 //! \details 2633 //! This is a slice level command and can be issued multiple times within a 2634 //! picture that is comprised of multiple slices. The same command is used 2635 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). However, 2636 //! since for AVC decoder VLD and IT modes, and AVC encoder mode, the 2637 //! implicit weights are computed in hardware, this command is not issued. 2638 //! For encoder, regardless of the type of weight calculation is active for 2639 //! the current slice (default, implicit or explicit), they are all sent to 2640 //! the PAK as if they were all in explicit mode. However, for implicit 2641 //! weight and offset, each entry contains only a 16-bit weight and no 2642 //! offset (offset = 0 always in implicit mode and can be hard-coded inside 2643 //! the hardware).The weights (and offsets) are needed in processing both P 2644 //! and B slice in AVC codec. For P-MB, at most only L0 list is used; for 2645 //! B-MB both L0 and L1 lists may be needed. For a B-MB that is coded in 2646 //! L1-only Prediction, only L1 list is sent.The content of this command 2647 //! matches with the AVC API data structure for explicit prediction 2648 //! mode only : Weights[2][32][3][2] (L0:L1, 0:31 RefPic, Y:Cb:Cr, W:0) 2649 //! 2650 struct MFX_AVC_WEIGHTOFFSET_STATE_CMD 2651 { 2652 union 2653 { 2654 //!< DWORD 0 2655 struct 2656 { 2657 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2658 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2659 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 2660 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 2661 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 2662 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2663 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2664 }; 2665 uint32_t Value; 2666 } DW0; 2667 union 2668 { 2669 //!< DWORD 1 2670 struct 2671 { 2672 uint32_t WeightAndOffsetSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< WEIGHT_AND_OFFSET_SELECT 2673 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2674 }; 2675 uint32_t Value; 2676 } DW1; 2677 2678 uint32_t Weightoffset[96]; //!< WeightOffset 2679 2680 2681 //! \name Local enumerations 2682 2683 enum SUBOPCODE_B 2684 { 2685 SUBOPCODE_B_UNNAMED5 = 5, //!< No additional details 2686 }; 2687 2688 enum SUBOPCODE_A 2689 { 2690 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2691 }; 2692 2693 enum MEDIA_COMMAND_OPCODE 2694 { 2695 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2696 }; 2697 2698 enum PIPELINE 2699 { 2700 PIPELINE_MFXAVCWEIGHTOFFSETSTATE = 2, //!< No additional details 2701 }; 2702 2703 enum COMMAND_TYPE 2704 { 2705 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2706 }; 2707 2708 //! \brief WEIGHT_AND_OFFSET_SELECT 2709 //! \details 2710 //! It must be set in consistent with the WeightedPredFlag and 2711 //! WeightedBiPredIdc in the Img_State command. 2712 //! This parameter is specified for Intel interface only 2713 //! For implicit even though only one entry may be used, still loading 2714 //! the whole 32-entry table. 2715 enum WEIGHT_AND_OFFSET_SELECT 2716 { 2717 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL0TABLE = 0, //!< The list that followed is associated with the weight and offset for RefPicList L0 2718 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL1TABLE = 1, //!< The list that followed is associated with the weight and offset for RefPicList L1 2719 }; 2720 2721 //! \name Initializations 2722 2723 //! \brief Explicit member initialization function 2724 MFX_AVC_WEIGHTOFFSET_STATE_CMD(); 2725 2726 static const size_t dwSize = 98; 2727 static const size_t byteSize = 392; 2728 }; 2729 2730 //! 2731 //! \brief MFX_AVC_SLICE_STATE 2732 //! \details 2733 //! This is a slice level command and can be issued multiple times within a 2734 //! picture that is comprised of multiple slices. The same command is used 2735 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). 2736 //! 2737 //! In VDEnc mode, this command is programmed for every super-slice. However 2738 //! not all parameters are allowed to change across super-slices. 2739 //! 2740 //! MFX_AVC_SLICE_STATE command is not issued for AVC Short Format 2741 //! Bitstream decode, instead MFD_AVC_SLICEADDR command is executed to 2742 //! retrieve the next slice MB Start Address X and Y by H/W itself. 2743 //! 2744 struct MFX_AVC_SLICE_STATE_CMD 2745 { 2746 union 2747 { 2748 //!< DWORD 0 2749 struct 2750 { 2751 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2752 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2753 uint32_t CommandSubopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< COMMAND_SUBOPCODEB 2754 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 2755 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 2756 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2757 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2758 }; 2759 uint32_t Value; 2760 } DW0; 2761 union 2762 { 2763 //!< DWORD 1 2764 struct 2765 { 2766 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 3) ; //!< SLICE_TYPE 2767 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 2768 }; 2769 uint32_t Value; 2770 } DW1; 2771 union 2772 { 2773 //!< DWORD 2 2774 struct 2775 { 2776 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD( 0, 2) ; //!< Log 2 Weight Denom Luma 2777 uint32_t Reserved67 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2778 uint32_t Log2WeightDenomChroma : __CODEGEN_BITFIELD( 8, 10) ; //!< Log 2 Weight Denom Chroma 2779 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 2780 uint32_t NumberOfReferencePicturesInInterPredictionList0 : __CODEGEN_BITFIELD(16, 21) ; //!< Number of Reference Pictures in Inter-prediction List 0 2781 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2782 uint32_t NumberOfReferencePicturesInInterPredictionList1 : __CODEGEN_BITFIELD(24, 29) ; //!< Number of Reference Pictures in Inter-prediction List 1 2783 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2784 }; 2785 uint32_t Value; 2786 } DW2; 2787 union 2788 { 2789 //!< DWORD 3 2790 struct 2791 { 2792 uint32_t SliceAlphaC0OffsetDiv2 : __CODEGEN_BITFIELD( 0, 3) ; //!< Slice Alpha C0 Offset Div2 2793 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 2794 uint32_t SliceBetaOffsetDiv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< Slice Beta Offset Div2 2795 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2796 uint32_t SliceQuantizationParameter : __CODEGEN_BITFIELD(16, 21) ; //!< Slice Quantization Parameter 2797 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2798 uint32_t CabacInitIdc10 : __CODEGEN_BITFIELD(24, 25) ; //!< Cabac Init Idc[1:0] 2799 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 2800 uint32_t DisableDeblockingFilterIndicator : __CODEGEN_BITFIELD(27, 28) ; //!< DISABLE_DEBLOCKING_FILTER_INDICATOR 2801 uint32_t DirectPredictionType : __CODEGEN_BITFIELD(29, 29) ; //!< DIRECT_PREDICTION_TYPE 2802 uint32_t WeightedPredictionIndicator : __CODEGEN_BITFIELD(30, 31) ; //!< Weighted Prediction Indicator 2803 }; 2804 uint32_t Value; 2805 } DW3; 2806 union 2807 { 2808 //!< DWORD 4 2809 struct 2810 { 2811 uint32_t SliceStartMbNum : __CODEGEN_BITFIELD( 0, 14) ; //!< Slice Start Mb Num 2812 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2813 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Horizontal Position 2814 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(24, 31) ; //!< Slice Vertical Position 2815 }; 2816 uint32_t Value; 2817 } DW4; 2818 union 2819 { 2820 //!< DWORD 5 2821 struct 2822 { 2823 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< Next Slice Horizontal Position 2824 uint32_t Reserved168 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2825 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(16, 24) ; //!< Next Slice Vertical Position 2826 uint32_t Reserved184 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 2827 }; 2828 uint32_t Value; 2829 } DW5; 2830 union 2831 { 2832 //!< DWORD 6 2833 struct 2834 { 2835 uint32_t StreamId10 : __CODEGEN_BITFIELD( 0, 1) ; //!< Stream ID [1:0] 2836 uint32_t Reserved194 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 2837 uint32_t SliceId30 : __CODEGEN_BITFIELD( 4, 7) ; //!< Slice ID [3:0] 2838 uint32_t Reserved200 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 2839 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD(12, 12) ; //!< CABACZEROWORDINSERTIONENABLE 2840 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD(13, 13) ; //!< EMULATIONBYTESLICEINSERTENABLE 2841 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 2842 uint32_t TailInsertionPresentInBitstream : __CODEGEN_BITFIELD(15, 15) ; //!< TAIL_INSERTION_PRESENT_IN_BITSTREAM 2843 uint32_t SlicedataInsertionPresentInBitstream : __CODEGEN_BITFIELD(16, 16) ; //!< SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2844 uint32_t HeaderInsertionPresentInBitstream : __CODEGEN_BITFIELD(17, 17) ; //!< HEADER_INSERTION_PRESENT_IN_BITSTREAM 2845 uint32_t Reserved210 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 2846 uint32_t IsLastSlice : __CODEGEN_BITFIELD(19, 19) ; //!< IS_LAST_SLICE 2847 uint32_t MbTypeSkipConversionDisable : __CODEGEN_BITFIELD(20, 20) ; //!< MB_TYPE_SKIP_CONVERSION_DISABLE 2848 uint32_t MbTypeDirectConversionDisable : __CODEGEN_BITFIELD(21, 21) ; //!< MB_TYPE_DIRECT_CONVERSION_DISABLE 2849 uint32_t RcPanicType : __CODEGEN_BITFIELD(22, 22) ; //!< RC_PANIC_TYPE 2850 uint32_t RcPanicEnable : __CODEGEN_BITFIELD(23, 23) ; //!< RC_PANIC_ENABLE 2851 uint32_t RcStableTolerance : __CODEGEN_BITFIELD(24, 27) ; //!< RC Stable Tolerance 2852 uint32_t RcTriggleMode : __CODEGEN_BITFIELD(28, 29) ; //!< RC_TRIGGLE_MODE 2853 uint32_t Resetratecontrolcounter : __CODEGEN_BITFIELD(30, 30) ; //!< RESETRATECONTROLCOUNTER 2854 uint32_t RateControlCounterEnable : __CODEGEN_BITFIELD(31, 31) ; //!< RATE_CONTROL_COUNTER_ENABLE 2855 }; 2856 uint32_t Value; 2857 } DW6; 2858 union 2859 { 2860 //!< DWORD 7 2861 struct 2862 { 2863 uint32_t IndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect PAK-BSE Data Start Address (Write) 2864 uint32_t Reserved253 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2865 }; 2866 uint32_t Value; 2867 } DW7; 2868 union 2869 { 2870 //!< DWORD 8 2871 struct 2872 { 2873 uint32_t GrowParamGrowInit : __CODEGEN_BITFIELD( 0, 3) ; //!< Grow Param - Grow Init 2874 uint32_t GrowParamGrowResistance : __CODEGEN_BITFIELD( 4, 7) ; //!< Grow Param - Grow Resistance 2875 uint32_t ShrinkParamShrinkInit : __CODEGEN_BITFIELD( 8, 11) ; //!< Shrink Param - Shrink Init 2876 uint32_t ShrinkParamShrinkResistance : __CODEGEN_BITFIELD(12, 15) ; //!< Shrink Param - Shrink Resistance 2877 uint32_t MagnitudeOfQpMaxPositiveModifier : __CODEGEN_BITFIELD(16, 23) ; //!< Magnitude of QP Max Positive Modifier 2878 uint32_t MagnitudeOfQpMaxNegativeModifier : __CODEGEN_BITFIELD(24, 31) ; //!< Magnitude of QP Max Negative Modifier 2879 }; 2880 uint32_t Value; 2881 } DW8; 2882 union 2883 { 2884 //!< DWORD 9 2885 struct 2886 { 2887 uint32_t Correct1 : __CODEGEN_BITFIELD( 0, 3) ; //!< Correct 1 2888 uint32_t Correct2 : __CODEGEN_BITFIELD( 4, 7) ; //!< Correct 2 2889 uint32_t Correct3 : __CODEGEN_BITFIELD( 8, 11) ; //!< Correct 3 2890 uint32_t Correct4 : __CODEGEN_BITFIELD(12, 15) ; //!< Correct 4 2891 uint32_t Correct5 : __CODEGEN_BITFIELD(16, 19) ; //!< Correct 5 2892 uint32_t Correct6 : __CODEGEN_BITFIELD(20, 23) ; //!< Correct 6 2893 uint32_t Roundintra : __CODEGEN_BITFIELD(24, 26) ; //!< ROUNDINTRA 2894 uint32_t Roundintraenable : __CODEGEN_BITFIELD(27, 27) ; //!< RoundIntraEnable 2895 uint32_t Roundinter : __CODEGEN_BITFIELD(28, 30) ; //!< ROUNDINTER 2896 uint32_t Roundinterenable : __CODEGEN_BITFIELD(31, 31) ; //!< RoundInterEnable 2897 }; 2898 uint32_t Value; 2899 } DW9; 2900 union 2901 { 2902 //!< DWORD 10 2903 struct 2904 { 2905 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 2906 uint32_t Cv1 : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 2907 uint32_t Cv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 2908 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 2909 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 2910 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 2911 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 2912 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31) ; //!< ClampValues - CV7 2913 }; 2914 uint32_t Value; 2915 } DW10; 2916 2917 //! \name Local enumerations 2918 2919 enum COMMAND_SUBOPCODEB 2920 { 2921 COMMAND_SUBOPCODEB_MFXAVCSLICESTATE = 3, //!< No additional details 2922 }; 2923 2924 enum SUBOPCODEA 2925 { 2926 SUBOPCODEA_MFXAVCSLICESTATE = 0, //!< No additional details 2927 }; 2928 2929 enum COMMAND_OPCODE 2930 { 2931 COMMAND_OPCODE_AVC = 1, //!< No additional details 2932 }; 2933 2934 enum PIPELINE 2935 { 2936 PIPELINE_MFXAVCSLICESTATE = 2, //!< No additional details 2937 }; 2938 2939 enum COMMAND_TYPE 2940 { 2941 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2942 }; 2943 2944 //! \brief SLICE_TYPE 2945 //! \details 2946 //! It is set to the value of the syntax element read from the Slice Header. 2947 enum SLICE_TYPE 2948 { 2949 SLICE_TYPE_PSLICE = 0, //!< No additional details 2950 SLICE_TYPE_BSLICE = 1, //!< No additional details 2951 SLICE_TYPE_ISLICE = 2, //!< No additional details 2952 }; 2953 2954 enum DISABLE_DEBLOCKING_FILTER_INDICATOR 2955 { 2956 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED0 = 0, //!< FilterInternalEdgesFlag is set equal to 1 2957 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED1 = 1, //!< Disable all deblocking operation, no deblocking parameter syntax element is read; filterInternalEdgesFlag is set equal to 0 2958 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED2 = 2, //!< Macroblocks in different slices are considered not available; filterInternalEdgesFlag is set equal to 1 2959 }; 2960 2961 //! \brief DIRECT_PREDICTION_TYPE 2962 //! \details 2963 //! Type of direct prediction used for B Slices. This field is valid only 2964 //! for Slice_Type = B Slice; otherwise, it must be set to 0. 2965 enum DIRECT_PREDICTION_TYPE 2966 { 2967 DIRECT_PREDICTION_TYPE_TEMPORAL = 0, //!< No additional details 2968 DIRECT_PREDICTION_TYPE_SPATIAL = 1, //!< No additional details 2969 }; 2970 2971 //! \brief CABACZEROWORDINSERTIONENABLE 2972 //! \details 2973 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2974 //! requirement. 2975 enum CABACZEROWORDINSERTIONENABLE 2976 { 2977 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion 2978 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP(effectively can be used as an indicator for last slice of a picture, if the assumption is only the last slice of a picture needs to insert CABAC_ZERO_WORDs. 2979 }; 2980 2981 //! \brief EMULATIONBYTESLICEINSERTENABLE 2982 //! \details 2983 //! To have PAK outputting SODB or EBSP to the output bitstream buffer 2984 enum EMULATIONBYTESLICEINSERTENABLE 2985 { 2986 EMULATIONBYTESLICEINSERTENABLE_UNNAMED0 = 0, //!< outputting RBSP 2987 EMULATIONBYTESLICEINSERTENABLE_UNNAMED1 = 1, //!< outputting EBSP 2988 }; 2989 2990 //! \brief TAIL_INSERTION_PRESENT_IN_BITSTREAM 2991 //! \details 2992 //! <p>This bit should only be set for the last super slice.</p> 2993 //! <p><span style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 2994 //! line-height: normal;">SKL Restriction: In VDENC mode, SW should insert 2995 //! 1000 </span><b style="color: rgb(0, 0, 0); font-family: Arial, 2996 //! sans-serif; line-height: normal;">VD_PIPELINE_FLUSH commands with 2997 //! VDENC_pipeline_Done set to 1 before inserting tail command. This is for 2998 //! delaying the tail insertion in HW. The HW recommendation is to insert 2999 //! tail only at the end of sequence to avoid performance loss since this 3000 //! restriction potentially cause performance degradation.</b></p> 3001 enum TAIL_INSERTION_PRESENT_IN_BITSTREAM 3002 { 3003 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits 3004 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 3005 }; 3006 3007 //! \brief SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 3008 //! \details 3009 //! <p>This bit should be set for all super-slices.</p> 3010 enum SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 3011 { 3012 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No Slice Data insertion into the output bitstream buffer 3013 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Slice Data insertion into the output bitstream buffer is present. 3014 }; 3015 3016 //! \brief HEADER_INSERTION_PRESENT_IN_BITSTREAM 3017 //! \details 3018 //! Note: In VDEnc mode, the slice header PAK object maximum size is 25 DWs. 3019 enum HEADER_INSERTION_PRESENT_IN_BITSTREAM 3020 { 3021 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, in front of the current slice encoded bits. 3022 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 3023 }; 3024 3025 //! \brief IS_LAST_SLICE 3026 //! \details 3027 //! It is used by the zero filling in the Minimum Frame Size test. 3028 enum IS_LAST_SLICE 3029 { 3030 IS_LAST_SLICE_UNNAMED0 = 0, //!< Current slice is NOT the last slice of a picture 3031 IS_LAST_SLICE_UNNAMED1 = 1, //!< Current slice is the last slice of a picture 3032 }; 3033 3034 //! \brief MB_TYPE_SKIP_CONVERSION_DISABLE 3035 //! \details 3036 //! For all Macroblock type conversions in different slices, refer to 3037 //! Section "Macroblock Type Conversion Rules" in the same volume. 3038 enum MB_TYPE_SKIP_CONVERSION_DISABLE 3039 { 3040 MB_TYPE_SKIP_CONVERSION_DISABLE_ENABLESKIPTYPECONVERSION = 0, //!< No additional details 3041 MB_TYPE_SKIP_CONVERSION_DISABLE_DISABLESKIPTYPECONVERSION = 1, //!< No additional details 3042 }; 3043 3044 //! \brief MB_TYPE_DIRECT_CONVERSION_DISABLE 3045 //! \details 3046 //! For all Macroblock type conversions in different slices, refer to 3047 //! Section "Macroblock Type Conversion Rules" in the same volume. 3048 enum MB_TYPE_DIRECT_CONVERSION_DISABLE 3049 { 3050 MB_TYPE_DIRECT_CONVERSION_DISABLE_ENABLEDIRECTMODECONVERSION = 0, //!< No additional details 3051 MB_TYPE_DIRECT_CONVERSION_DISABLE_DISABLEDIRECTMODECONVERSION = 1, //!< No additional details 3052 }; 3053 3054 //! \brief RC_PANIC_TYPE 3055 //! \details 3056 //! This field selects between two RC Panic methods 3057 enum RC_PANIC_TYPE 3058 { 3059 RC_PANIC_TYPE_QPPANIC = 0, //!< No additional details 3060 RC_PANIC_TYPE_CBPPANIC = 1, //!< No additional details 3061 }; 3062 3063 //! \brief RC_PANIC_ENABLE 3064 //! \details 3065 //! If this field is set to 1, RC enters panic mode when sum_act > 3066 //! sum_max. RC Panic Type field controls what type of panic behavior is 3067 //! invoked. 3068 enum RC_PANIC_ENABLE 3069 { 3070 RC_PANIC_ENABLE_DISABLE = 0, //!< No additional details 3071 RC_PANIC_ENABLE_ENABLE = 1, //!< No additional details 3072 }; 3073 3074 enum RC_TRIGGLE_MODE 3075 { 3076 RC_TRIGGLE_MODE_ALWAYSRATECONTROL = 0, //!< Whereas RC becomes active if sum_act > sum_target or sum_act < sum_target 3077 RC_TRIGGLE_MODE_GENTLERATECONTROL = 1, //!< whereas RC becomes active if sum_act > upper_midpt or sum_act < lower_midpt 3078 RC_TRIGGLE_MODE_LOOSERATECONTROL = 2, //!< whereas RC becomes active if sum_act > sum_max or sum_act < sum_min 3079 }; 3080 3081 //! \brief RESETRATECONTROLCOUNTER 3082 //! \details 3083 //! To reset the bit allocation accumulation counter to 0 to restart the 3084 //! rate control. 3085 enum RESETRATECONTROLCOUNTER 3086 { 3087 RESETRATECONTROLCOUNTER_NOTRESET = 0, //!< No additional details 3088 RESETRATECONTROLCOUNTER_RESET = 1, //!< No additional details 3089 }; 3090 3091 //! \brief RATE_CONTROL_COUNTER_ENABLE 3092 //! \details 3093 //! To enable the accumulation of bit allocation for rate control 3094 //! This field enables hardware Rate Control logic. The rest of the RC 3095 //! control fields are only valid when this field is set to 1. Otherwise, 3096 //! hardware ignores these fields. 3097 enum RATE_CONTROL_COUNTER_ENABLE 3098 { 3099 RATE_CONTROL_COUNTER_ENABLE_DISABLE = 0, //!< No additional details 3100 RATE_CONTROL_COUNTER_ENABLE_ENABLE = 1, //!< No additional details 3101 }; 3102 3103 //! \brief ROUNDINTRA 3104 //! \details 3105 //! Rounding precision for Intra quantized coefficients 3106 enum ROUNDINTRA 3107 { 3108 ROUNDINTRA_116 = 0, //!< No additional details 3109 ROUNDINTRA_216 = 1, //!< No additional details 3110 ROUNDINTRA_316 = 2, //!< No additional details 3111 ROUNDINTRA_416 = 3, //!< No additional details 3112 ROUNDINTRA_516 = 4, //!< No additional details 3113 ROUNDINTRA_616 = 5, //!< No additional details 3114 ROUNDINTRA_716 = 6, //!< No additional details 3115 ROUNDINTRA_816 = 7, //!< No additional details 3116 }; 3117 3118 //! \brief ROUNDINTER 3119 //! \details 3120 //! Rounding precision for Inter quantized coefficients 3121 enum ROUNDINTER 3122 { 3123 ROUNDINTER_116 = 0, //!< No additional details 3124 ROUNDINTER_216 = 1, //!< No additional details 3125 ROUNDINTER_316 = 2, //!< No additional details 3126 ROUNDINTER_416 = 3, //!< No additional details 3127 ROUNDINTER_516 = 4, //!< No additional details 3128 ROUNDINTER_616 = 5, //!< No additional details 3129 ROUNDINTER_716 = 6, //!< No additional details 3130 ROUNDINTER_816 = 7, //!< No additional details 3131 }; 3132 3133 //! \name Initializations 3134 3135 //! \brief Explicit member initialization function 3136 MFX_AVC_SLICE_STATE_CMD(); 3137 3138 static const size_t dwSize = 11; 3139 static const size_t byteSize = 44; 3140 }; 3141 3142 //! 3143 //! \brief MFD_AVC_DPB_STATE 3144 //! \details 3145 //! This is a frame level state command used only in AVC Short Slice 3146 //! Bitstream Format VLD mode. RefFrameList[16] of interface is 3147 //! replaced with intel Reference Picture Addresses[16] of 3148 //! MFX_PIPE_BUF_ADDR_STATE command. The LongTerm Picture flag indicator of 3149 //! all reference pictures are collected into LongTermPic_Flag[16]. 3150 //! FieldOrderCntList[16][2] and CurrFieldOrderCnt[2] of interface are 3151 //! replaced with intel POCList[34] of MFX_AVC_DIRECTMODE_STATE command. 3152 //! 3153 struct MFD_AVC_DPB_STATE_CMD 3154 { 3155 union 3156 { 3157 //!< DWORD 0 3158 struct 3159 { 3160 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3161 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3162 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3163 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3164 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3165 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3166 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3167 }; 3168 uint32_t Value; 3169 } DW0; 3170 union 3171 { 3172 //!< DWORD 1 3173 struct 3174 { 3175 uint32_t NonExistingframeFlag161Bit : __CODEGEN_BITFIELD( 0, 15) ; //!< NON_EXISTINGFRAME_FLAG161_BIT 3176 uint32_t LongtermframeFlag161Bit : __CODEGEN_BITFIELD(16, 31) ; //!< LONGTERMFRAME_FLAG161_BIT 3177 }; 3178 uint32_t Value; 3179 } DW1; 3180 union 3181 { 3182 //!< DWORD 2 3183 struct 3184 { 3185 uint32_t UsedforreferenceFlag162Bits ; //!< USEDFORREFERENCE_FLAG162_BITS 3186 }; 3187 uint32_t Value; 3188 } DW2; 3189 3190 uint32_t Ltstframenumlist1616Bits[8]; //!< LTSTFRAMENUMLIST1616_BITS 3191 3192 3193 uint32_t Viewidlist1616Bits[8]; //!< ViewIDList[16][16 bits] 3194 3195 3196 uint32_t Vieworderlistl0168Bits[4]; //!< ViewOrderListL0[16][8 bits] 3197 3198 3199 uint32_t Vieworderlistl1168Bits[4]; //!< ViewOrderListL1[16][8 bits] 3200 3201 3202 //! \name Local enumerations 3203 3204 enum SUBOPCODE_B 3205 { 3206 SUBOPCODE_B_UNNAMED6 = 6, //!< No additional details 3207 }; 3208 3209 enum SUBOPCODE_A 3210 { 3211 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3212 }; 3213 3214 enum MEDIA_COMMAND_OPCODE 3215 { 3216 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3217 }; 3218 3219 enum PIPELINE 3220 { 3221 PIPELINE_MFXMULTIDW = 2, //!< No additional details 3222 }; 3223 3224 enum COMMAND_TYPE 3225 { 3226 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3227 }; 3228 3229 //! \brief NON_EXISTINGFRAME_FLAG161_BIT 3230 //! \details 3231 //! One-to-one correspondence with the entries of the Intel 3232 //! RefFrameList[16]. 1 bit per reference frame. 3233 enum NON_EXISTINGFRAME_FLAG161_BIT 3234 { 3235 NON_EXISTINGFRAME_FLAG161_BIT_VALID = 0, //!< the reference picture in that entry of RefFrameList[] is a valid reference 3236 NON_EXISTINGFRAME_FLAG161_BIT_INVALID = 1, //!< the reference picture in that entry of RefFrameList[] does not exist anymore. 3237 }; 3238 3239 //! \brief LONGTERMFRAME_FLAG161_BIT 3240 //! \details 3241 //! One-to-one correspondence with the entries of the Intel 3242 //! RefFrameList[16]. 1 bit per reference frame. 3243 enum LONGTERMFRAME_FLAG161_BIT 3244 { 3245 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISASHORTTERMREFERENCEPICTURE = 0, //!< No additional details 3246 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISALONGTERMREFERENCEPICTURE = 1, //!< No additional details 3247 }; 3248 3249 //! \brief USEDFORREFERENCE_FLAG162_BITS 3250 //! \details 3251 //! One-to-one correspondence with the entries of the Intel 3252 //! RefFrameList[16]. 2 bits per reference frame. 3253 enum USEDFORREFERENCE_FLAG162_BITS 3254 { 3255 USEDFORREFERENCE_FLAG162_BITS_NOTREFERENCE = 0, //!< indicates a frame is "not used for reference". 3256 USEDFORREFERENCE_FLAG162_BITS_TOPFIELD = 1, //!< bit[0] indicates that the top field of a frame is marked as "used for reference". 3257 USEDFORREFERENCE_FLAG162_BITS_BOTTOMFIELD = 2, //!< bit[1] indicates that the bottom field of a frame is marked as "used for reference". 3258 USEDFORREFERENCE_FLAG162_BITS_FRAME = 3, //!< bit[1:0] indicates that a frame (or field pair) is marked as "used for reference". 3259 }; 3260 3261 //! \brief LTSTFRAMENUMLIST1616_BITS 3262 //! \details 3263 //! One-to-one correspondence with the entries of the Intel 3264 //! RefFrameList[16]. 16 bits per reference frame.Depending on the 3265 //! corresponding LongTermFrame_Flag[], the content of this field is 3266 //! interpreted differently. 3267 enum LTSTFRAMENUMLIST1616_BITS 3268 { 3269 LTSTFRAMENUMLIST1616_BITS_SHORTTERMFRAMEFLAGI = 0, //!< LTSTFrameNumList[i]represent Short Term Picture FrameNum. 3270 LTSTFRAMENUMLIST1616_BITS_LONGTERMFRAMEFLAGI = 1, //!< LTSTFrameNumList[i] represent LongTermFrameIdx. 3271 }; 3272 3273 //! \name Initializations 3274 3275 //! \brief Explicit member initialization function 3276 MFD_AVC_DPB_STATE_CMD(); 3277 3278 static const size_t dwSize = 27; 3279 static const size_t byteSize = 108; 3280 }; 3281 3282 //! 3283 //! \brief MFD_AVC_SLICEADDR 3284 //! \details 3285 //! This is a Slice level command used only for AVC Short Slice 3286 //! Bitstream Format VLD mode.When decoding a slice, H/W needs to know the 3287 //! last MB of the slice has reached in order to start decoding the next 3288 //! slice. It also needs to know if a slice is terminated but the last MB 3289 //! has not reached, error conealment should be invoked to generate those 3290 //! missing MBs. For AVC Short Format, the only way to know the last 3291 //! MB position of the current slice, H/W needs to snoop into the next 3292 //! slice's start MB address (a linear address encoded in the Slice Header). 3293 //! Since each BSD Object command can have only one indirect bitstream 3294 //! buffer address, this command is added to help H/W to snoop into the next 3295 //! slice's slice header and retrieve its Start MB Address. This command 3296 //! will take the next slice's bitstream buffer address as input (exactly 3297 //! the same way as a BSD Object command), and parse only the 3298 //! first_mb_in_slice syntax element. The result will stored inside the H/W, 3299 //! and will be used to decode the current slice specified in the BSD Object 3300 //! command.Only the very first few bytes (max 5 bytes for a max 4K picture) 3301 //! of the Slice Header will be decoded, the rest of the bitstream are don't 3302 //! care. This is because the first_mb_in_slice is encoded in Exponential 3303 //! Golomb, and will take 33 bits to represent the max 256 x 256 = 64K-1 3304 //! value. The indirect data of MFD_AVC_SLICEADDR is a valid BSD object and 3305 //! is decoded as in BSD OBJECT command.The next Slice Start MB Address is 3306 //! also exposed to the MMIO interface.The Slice Start MB Address 3307 //! (first_mb_in_slice) is a linear MB address count; but it is translated 3308 //! into the corresponding 2D MB X and Y raster position, and are stored 3309 //! internally as NextSliceMbY and NextSliceMbX. 3310 //! 3311 struct MFD_AVC_SLICEADDR_CMD 3312 { 3313 union 3314 { 3315 //!< DWORD 0 3316 struct 3317 { 3318 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3319 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3320 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3321 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3322 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3323 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3324 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3325 }; 3326 uint32_t Value; 3327 } DW0; 3328 union 3329 { 3330 //!< DWORD 1 3331 struct 3332 { 3333 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3334 }; 3335 uint32_t Value; 3336 } DW1; 3337 union 3338 { 3339 //!< DWORD 2 3340 struct 3341 { 3342 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect BSD Data Start Address 3343 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3344 }; 3345 uint32_t Value; 3346 } DW2; 3347 union 3348 { 3349 //!< DWORD 3 3350 struct 3351 { 3352 uint32_t DriverProvidedNalTypeValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Driver Provided NAL Type Value 3353 uint32_t AvcNalTypeFirstByteOverrideBit : __CODEGEN_BITFIELD( 8, 8) ; //!< AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3354 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 3355 }; 3356 uint32_t Value; 3357 } DW3; 3358 3359 //! \name Local enumerations 3360 3361 enum SUBOPCODE_B 3362 { 3363 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 3364 }; 3365 3366 enum SUBOPCODE_A 3367 { 3368 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3369 }; 3370 3371 enum MEDIA_COMMAND_OPCODE 3372 { 3373 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3374 }; 3375 3376 enum PIPELINE 3377 { 3378 PIPELINE_MFDAVCSLICEADDR = 2, //!< No additional details 3379 }; 3380 3381 enum COMMAND_TYPE 3382 { 3383 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3384 }; 3385 3386 //! \brief AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3387 //! \details 3388 //! <p>This bit indicates hardware should use the NAL Type (provided below) 3389 //! programmed by driver instead of using the one from bitstream. The NAL 3390 //! byte from bitstream will not be correct.</p> 3391 enum AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3392 { 3393 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEBITSTREAMDECODEDNALTYPE = 0, //!< NAL Type should come from first byte of decoded bitstream. 3394 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEDRIVERPROGRAMMEDNALTYPE = 1, //!< NAL Type should come from "Driver Provided NAL Type Values" programmed by driver. 3395 }; 3396 3397 //! \name Initializations 3398 3399 //! \brief Explicit member initialization function 3400 MFD_AVC_SLICEADDR_CMD(); 3401 3402 static const size_t dwSize = 4; 3403 static const size_t byteSize = 16; 3404 }; 3405 3406 //! 3407 //! \brief MFD_AVC_BSD_OBJECT 3408 //! \details 3409 //! The MFD_AVC_BSD_OBJECT command is the only primitive command for the AVC 3410 //! Decoding Pipeline. The same command is used for both CABAC and CAVLD 3411 //! modes. The Slice Data portion of the bitstream is loaded as indirect 3412 //! data object.Before issuing a MFD_AVC_BSD_OBJECT command, all AVC states 3413 //! of the MFD Engine need to be valid. Therefore the commands used to set 3414 //! these states need to have been issued prior to the issue of a 3415 //! MFD_AVC_BSD_OBJECT command. 3416 //! 3417 //! Context switch interrupt is not supported by this command. 3418 //! 3419 struct MFD_AVC_BSD_OBJECT_CMD 3420 { 3421 union 3422 { 3423 //!< DWORD 0 3424 struct 3425 { 3426 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3427 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3428 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3429 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3430 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3431 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3432 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3433 }; 3434 uint32_t Value; 3435 } DW0; 3436 union 3437 { 3438 //!< DWORD 1 3439 struct 3440 { 3441 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3442 }; 3443 uint32_t Value; 3444 } DW1; 3445 union 3446 { 3447 //!< DWORD 2 3448 struct 3449 { 3450 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect BSD Data Start Address 3451 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3452 }; 3453 uint32_t Value; 3454 } DW2; 3455 union 3456 { 3457 //!< DWORD 3 3458 struct 3459 { 3460 uint32_t MbErrorConcealmentPSliceWeightPredictionDisableFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3461 uint32_t MbErrorConcealmentPSliceMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3462 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 3463 uint32_t MbErrorConcealmentBSpatialWeightPredictionDisableFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3464 uint32_t MbErrorConcealmentBSpatialMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3465 uint32_t Reserved101 : __CODEGEN_BITFIELD( 5, 5) ; //!< Reserved 3466 uint32_t MbErrorConcealmentBSpatialPredictionMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3467 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD( 8, 8) ; //!< MB_HEADER_ERROR_HANDLING_ 3468 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 3469 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10) ; //!< ENTROPY_ERROR_HANDLING 3470 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 3471 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3472 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 3473 uint32_t BsdPrematureCompleteErrorHandling : __CODEGEN_BITFIELD(14, 14) ; //!< BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3474 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3475 uint32_t ConcealmentPictureId : __CODEGEN_BITFIELD(16, 21) ; //!< Concealment Picture ID 3476 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3477 uint32_t MbErrorConcealmentBTemporalWeightPredictionDisableFlag : __CODEGEN_BITFIELD(24, 24) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3478 uint32_t MbErrorConcealmentBTemporalMotionVectorsOverrideEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3479 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 3480 uint32_t MbErrorConcealmentBTemporalPredictionMode : __CODEGEN_BITFIELD(27, 28) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3481 uint32_t IntraPredmode4X48X8LumaErrorControlBit : __CODEGEN_BITFIELD(29, 29) ; //!< INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3482 uint32_t InitCurrentMbNumber : __CODEGEN_BITFIELD(30, 30) ; //!< Init Current MB Number 3483 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31) ; //!< CONCEALMENT_METHOD 3484 }; 3485 uint32_t Value; 3486 } DW3; 3487 union 3488 { 3489 //!< DWORD 4 3490 struct 3491 { 3492 uint32_t FirstMacroblockMbBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< First Macroblock (MB)Bit Offset 3493 uint32_t LastsliceFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< LASTSLICE_FLAG 3494 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD( 4, 4) ; //!< EMULATION_PREVENTION_BYTE_PRESENT 3495 uint32_t Reserved133 : __CODEGEN_BITFIELD( 5, 6) ; //!< Reserved 3496 uint32_t FixPrevMbSkipped : __CODEGEN_BITFIELD( 7, 7) ; //!< Fix Prev Mb Skipped 3497 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3498 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31) ; //!< First MB Byte Offset of Slice Data or Slice Header 3499 }; 3500 uint32_t Value; 3501 } DW4; 3502 union 3503 { 3504 //!< DWORD 5 3505 struct 3506 { 3507 uint32_t IntraPredictionErrorControlBitAppliedToIntra16X16Intra8X8Intra4X4LumaAndChroma : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3508 uint32_t Intra8X84X4PredictionErrorConcealmentControlBit : __CODEGEN_BITFIELD( 1, 1) ; //!< INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3509 uint32_t Reserved162 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 3510 uint32_t BSliceTemporalInterConcealmentMode : __CODEGEN_BITFIELD( 4, 6) ; //!< B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3511 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3512 uint32_t BSliceSpatialInterConcealmentMode : __CODEGEN_BITFIELD( 8, 10) ; //!< B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3513 uint32_t Reserved171 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 3514 uint32_t BSliceInterDirectTypeConcealmentMode : __CODEGEN_BITFIELD(12, 13) ; //!< B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3515 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 3516 uint32_t BSliceConcealmentMode : __CODEGEN_BITFIELD(15, 15) ; //!< B_SLICE_CONCEALMENT_MODE 3517 uint32_t PSliceInterConcealmentMode : __CODEGEN_BITFIELD(16, 18) ; //!< P_SLICE_INTER_CONCEALMENT_MODE 3518 uint32_t Reserved179 : __CODEGEN_BITFIELD(19, 22) ; //!< Reserved 3519 uint32_t PSliceConcealmentMode : __CODEGEN_BITFIELD(23, 23) ; //!< P_SLICE_CONCEALMENT_MODE 3520 uint32_t ConcealmentReferencePictureFieldBit : __CODEGEN_BITFIELD(24, 29) ; //!< Concealment Reference Picture + Field Bit 3521 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 3522 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31) ; //!< I_SLICE_CONCEALMENT_MODE 3523 }; 3524 uint32_t Value; 3525 } DW5; 3526 union 3527 { 3528 //!< DWORD 6 3529 struct 3530 { 3531 uint32_t DriverProvidedNalTypeValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Driver Provided Nal Type Value 3532 uint32_t AvcNalTypeFirstByteOverrideBit : __CODEGEN_BITFIELD( 8, 8) ; //!< AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3533 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 3534 }; 3535 uint32_t Value; 3536 } DW6; 3537 3538 //! \name Local enumerations 3539 3540 enum SUBOPCODE_B 3541 { 3542 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3543 }; 3544 3545 enum SUBOPCODE_A 3546 { 3547 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3548 }; 3549 3550 enum MEDIA_COMMAND_OPCODE 3551 { 3552 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3553 }; 3554 3555 enum PIPELINE 3556 { 3557 PIPELINE_MFDAVCBSDOBJECT = 2, //!< No additional details 3558 }; 3559 3560 enum COMMAND_TYPE 3561 { 3562 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3563 }; 3564 3565 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3566 //! \details 3567 //! During MB Error Concealment on P slice, weight prediction is disabled to 3568 //! improve image quality. 3569 //! This bit can be set to preserve the original weight prediction. 3570 //! This bit does not affect normal decoded MB. 3571 enum MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3572 { 3573 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3574 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3575 }; 3576 3577 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3578 //! \details 3579 //! During MB Error Concealment on P slice, motion vectors are forced to 0 3580 //! to improve image quality. 3581 //! This bit can be set to use the predicted motion vectors instead. 3582 //! This bit does not affect normal decoded MB. 3583 enum MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3584 { 3585 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3586 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3587 }; 3588 3589 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3590 //! \details 3591 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3592 //! weight prediction is disabled to improve image quality. 3593 //! This bit can be set to preserve the original weight prediction. 3594 //! This bit does not affect normal decoded MB. 3595 enum MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3596 { 3597 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3598 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3599 }; 3600 3601 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3602 //! \details 3603 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3604 //! motion vectors are forced to 0 to improve image quality. 3605 //! This bit can be set to use the predicted motion vectors instead. 3606 //! This bit does not affect normal decoded MB. 3607 enum MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3608 { 3609 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3610 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3611 }; 3612 3613 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3614 //! \details 3615 //! These two bits control how the reference L0/L1 are overridden in B 3616 //! spatial slice. 3617 enum MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3618 { 3619 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3620 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3621 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3622 }; 3623 3624 //! \brief MB_HEADER_ERROR_HANDLING_ 3625 //! \details 3626 //! Software must follow the action for each Value as follow: 3627 enum MB_HEADER_ERROR_HANDLING_ 3628 { 3629 MB_HEADER_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error concealment. 3630 MB_HEADER_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3631 }; 3632 3633 //! \brief ENTROPY_ERROR_HANDLING 3634 //! \details 3635 //! Software must follow the action for each Value as follow: 3636 enum ENTROPY_ERROR_HANDLING 3637 { 3638 ENTROPY_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error handling. 3639 ENTROPY_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3640 }; 3641 3642 //! \brief MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3643 //! \details 3644 //! Software must follow the action for each Value as follow: 3645 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3646 { 3647 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3648 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3649 }; 3650 3651 //! \brief BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3652 //! \details 3653 //! BSD Premature Complete Error occurs in situation where the Slice decode 3654 //! is completed but there are still data in the bitstream. 3655 enum BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3656 { 3657 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3658 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3659 }; 3660 3661 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3662 //! \details 3663 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3664 //! weight prediction is disabled to improve image quality. 3665 //! This bit can be set to preserve the original weight prediction. 3666 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3667 { 3668 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment 3669 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment 3670 }; 3671 3672 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3673 //! \details 3674 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3675 //! motion vectors are forced to 0 to improve image quality. 3676 //! This bit can be set to preserve the original weight prediction. 3677 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3678 { 3679 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED0 = 0, //!< Predicted Motion Vectors are used during MB Concealment 3680 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED1 = 1, //!< Motion Vectors are Overridden to 0 during MB Concealment 3681 }; 3682 3683 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3684 //! \details 3685 //! These two bits control how the reference L0/L1 are overridden in B 3686 //! temporal slice. 3687 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3688 { 3689 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3690 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3691 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3692 }; 3693 3694 //! \brief INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3695 //! \details 3696 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3697 //! decoded value is incorrect according to MB position 3698 enum INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3699 { 3700 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will detect and fix IntraPredMode (4x4/8x8 Luma) Errors. 3701 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will NOT detect IntraPredMode (4x4/8x8 Luma) Errors. The wrong IntraPredMode value will be retaind. 3702 }; 3703 3704 //! \brief CONCEALMENT_METHOD 3705 //! \details 3706 //! This field specifies the method used for concealment when error is 3707 //! detected. If set, a copy from collocated macroblock location is 3708 //! performed from the concealment reference indicated by the ConCeal_Pic_Id 3709 //! field. If it is not set, a copy from the current picture is performed 3710 //! using Intra 16x16 Prediction method. 3711 enum CONCEALMENT_METHOD 3712 { 3713 CONCEALMENT_METHOD_UNNAMED0 = 0, //!< Intra 16x16 Prediction 3714 CONCEALMENT_METHOD_UNNAMED1 = 1, //!< Inter P Copy 3715 }; 3716 3717 //! \brief LASTSLICE_FLAG 3718 //! \details 3719 //! It is needed for both error concealment at the end of a picture (so, no 3720 //! more phantom slice as in DevSNB). It is also needed to know to set the 3721 //! last MB in a picture correctly. 3722 enum LASTSLICE_FLAG 3723 { 3724 LASTSLICE_FLAG_UNNAMED0 = 0, //!< If the current Slice to be decoded is any slice other than the very last slice of the current picture 3725 LASTSLICE_FLAG_UNNAMED1 = 1, //!< If the current Slice to be decoded is the very last slice of the current picture. 3726 }; 3727 3728 enum EMULATION_PREVENTION_BYTE_PRESENT 3729 { 3730 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 3731 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 3732 }; 3733 3734 //! \brief INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3735 //! \details 3736 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3737 //! decoded value is incorrect according to MB position. 3738 enum INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3739 { 3740 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED0 = 0, //!< AVC decoder will detect and fix Intra Prediction Mode Errors. 3741 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED1 = 1, //!< AVC decoder will retain the Intra Prediction value decoded from bitstream. 3742 }; 3743 3744 //! \brief INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3745 //! \details 3746 //! This field controls if AVC goes into MB concealment mode (next MB) when 3747 //! an error is detected on Intra8x8/4x4 Prediction Mode (these 2 modes have 3748 //! fixed coding so it may not affect the bitstream. 3749 enum INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3750 { 3751 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will NOT go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3752 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3753 }; 3754 3755 //! \brief B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3756 //! \details 3757 //! This field controls how AVC decoder select reference picture for 3758 //! Temporal Inter Concealment in B Slice 3759 enum B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3760 { 3761 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1) 3762 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3763 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using B-Skip Algorithm) 3764 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< " Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3765 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< First Long Term Picture in Reference List L0/L1(If no long term picture available, use Temporal Closest Picture) 3766 }; 3767 3768 //! \brief B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3769 //! \details 3770 //! This field controls how AVC decoder select reference picture for Spatial 3771 //! Inter Concealment in B Slice. 3772 enum B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3773 { 3774 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1). 3775 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3776 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3777 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< " First Long Term Picture in Reference List L0/L1 (If no long term picture available, use Temporal Closest Picture) 3778 }; 3779 3780 //! \brief B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3781 //! \details 3782 //! AVC decoder can use Spatial or Temporal Direct for B Skip/Direct. 3783 //! This field determine can override the mode on how AVC decoder 3784 //! handles MB concealment in B slice. 3785 enum B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3786 { 3787 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Use Default Direct Type (slice programmed direct type) 3788 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Forced to Spatial Direct Only 3789 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Forced to Temporal Direct Only 3790 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Spatial Direct without Temporal Componenet (MovingBlock information) 3791 }; 3792 3793 //! \brief B_SLICE_CONCEALMENT_MODE 3794 //! \details 3795 //! This field controls how AVC decoder handle MB concealment in B Slice 3796 enum B_SLICE_CONCEALMENT_MODE 3797 { 3798 B_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3799 B_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3800 }; 3801 3802 //! \brief P_SLICE_INTER_CONCEALMENT_MODE 3803 //! \details 3804 //! This field controls how AVC decoder select reference picture for 3805 //! Concealment in P Slice. 3806 enum P_SLICE_INTER_CONCEALMENT_MODE 3807 { 3808 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0 (Use top entry of Reference List L0) 3809 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3810 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using P-Skip Algorithm) 3811 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC] 3812 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< First Long Term Picture in Reference List L0 (If no long term picture available, use Temporal Closest Picture) 3813 }; 3814 3815 //! \brief P_SLICE_CONCEALMENT_MODE 3816 //! \details 3817 //! This field controls how AVC decoder handle MB concealment in P Slice 3818 enum P_SLICE_CONCEALMENT_MODE 3819 { 3820 P_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3821 P_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3822 }; 3823 3824 //! \brief I_SLICE_CONCEALMENT_MODE 3825 //! \details 3826 //! This field controls how AVC decoder handle MB concealment in I Slice 3827 enum I_SLICE_CONCEALMENT_MODE 3828 { 3829 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< No additional details 3830 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< No additional details 3831 }; 3832 3833 //! \brief AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3834 //! \details 3835 //! <p>This bit indicates hardware should use the NAL Type (provided below) 3836 //! programmed by driver instead of using the one from bitstream. The NAL 3837 //! byte from bitstream will not be correct.</p> 3838 enum AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3839 { 3840 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEBITSTREAMDECODEDNALTYPE = 0, //!< NAL Type should come from the first byte of Decoded Bitstream 3841 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEDRIVERPROGRAMMEDNALTYPE = 1, //!< NAL Type should come from "Driver Provided Nal Type" programmed by driver. 3842 }; 3843 3844 //! \name Initializations 3845 3846 //! \brief Explicit member initialization function 3847 MFD_AVC_BSD_OBJECT_CMD(); 3848 3849 static const size_t dwSize = 7; 3850 static const size_t byteSize = 28; 3851 }; 3852 3853 //! 3854 //! \brief MFX_PAK_INSERT_OBJECT 3855 //! \details 3856 //! The MFX_PAK_INSERT_OBJECT command is the first primitive command for the 3857 //! AVC, MPEG2, JPEG, SVC and VP8 Encoding Pipeline. 3858 //! 3859 //! This command is issued to setup the control and parameters of inserting 3860 //! a chunk of compressed/encoded bits into the current bitstream output 3861 //! buffer starting at the specified bit locationto perform the actual 3862 //! insertion by transferring the command inline data to the output buffer 3863 //! max, 32 bits at a time. It is a variable length command as the data to 3864 //! be inserted are presented as inline data of this command. It is a 3865 //! multiple of 32-bit (1 DW), as the data bus to the bitstream buffer is 3866 //! 32-bit wide. Multiple insertion commands can be issued back to back in a 3867 //! series. It is host software's responsibility to make sure their 3868 //! corresponding data will properly stitch together to form a valid H.264 3869 //! bitstream. Internally, MFX hardware will keep track of the very last two 3870 //! bytes' (the very last byte can be a partial byte) values of the previous 3871 //! insertion. It is required that the next Insertion Object Command or the 3872 //! next PAK Object Command to perform the start code emulation sequence 3873 //! check and prevention 0x03 byte insertion with this end condition of the 3874 //! previous insertion. Hardware will keep track of an output bitstream 3875 //! buffer current byte position and the associated next bit insertion 3876 //! position index. Data to be inserted can be a valid H.264 NAL units or a 3877 //! partial NAL unit. Certain NAL unit has a minimum byte size requirement. 3878 //! As such the hardware will optionally (enabled by STATE Command) 3879 //! determines the number of CABAC_ZERO_WORD to be inserted to the end of 3880 //! the current NAL, based on the minimum byte size of a NAL and the actual 3881 //! bin count of the encoded Slice. Since prior to the CABAC_ZERO_WORD 3882 //! insertion, the RBSP or EBSP is already byte-aligned, so each 3883 //! CABAC_ZERO_WORD insertion is actually a 3-byte sequence 0x00 00 03. The 3884 //! inline data may have already been processed for start code emulation 3885 //! byte insertion, except the possibility of the last 2 bytes plus the very 3886 //! last partial byte (if any). Hence, when hardware performing the 3887 //! concatenation of multiple consecutive insertion commands, or 3888 //! concatenation of an insertion command and a PAK object command, it must 3889 //! check and perform the necessary start code emulation byte insert at the 3890 //! junction.The inline data is required to be byte aligned on the left 3891 //! (first transmitted bit order) and may or may not be byte aligned on the 3892 //! right (last transmitted bits). The command will specify the bit offset 3893 //! of the last valid DW.Each insertion state command defines a chunk of 3894 //! bits (compressed data) to be inserted at a specific location of the 3895 //! output compressed bitstream in the output buffer.Depend on CABAC or 3896 //! CAVLC encoding mode (from Slice State), PAK Object Command is always 3897 //! ended in byte aligned output bitstream except for CABAC header insertion 3898 //! which is bit aligned. In the aligned cases, PAK will perform 0 filling 3899 //! in CAVLC mode, and 1 filling in CABAC mode. Insertion data can 3900 //! include:any encoded syntax elements bit data before the encoded Slice 3901 //! Data (PAK Object Command) of the current SliceSPS NALPPS NALSEI NALOther 3902 //! Non-Slice NALLeading_Zero_8_bits (as many bytes as there is)Start Code 3903 //! PrefixNAL Header ByteSlice HeaderAny encoded syntax elements bit data 3904 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3905 //! and prior to the next encoded Slice Data of the next Slice or prior to 3906 //! the end of the bistream, whichever comes firstCabac_Zero_Word or 3907 //! Trailing_Zero_8bits (as many bytes as there is). Anything listed above 3908 //! before a Slice DataContext switch interrupt is not supported by this 3909 //! command. 3910 //! 3911 struct MFX_PAK_INSERT_OBJECT_CMD 3912 { 3913 union 3914 { 3915 //!< DWORD 0 3916 struct 3917 { 3918 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3919 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3920 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3921 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3922 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3923 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3924 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3925 }; 3926 uint32_t Value; 3927 } DW0; 3928 union 3929 { 3930 //!< DWORD 1 3931 struct 3932 { 3933 uint32_t BitstreamstartresetResetbitstreamstartingpos : __CODEGEN_BITFIELD( 0, 0) ; //!< BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3934 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3935 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3936 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3937 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 3938 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3939 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< SLICE_HEADER_INDICATOR 3940 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3941 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3942 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 3943 }; 3944 uint32_t Value; 3945 } DW1; 3946 3947 //! \name Local enumerations 3948 3949 enum SUBOPCODE_B 3950 { 3951 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3952 }; 3953 3954 enum SUBOPCODE_A 3955 { 3956 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 3957 }; 3958 3959 enum MEDIA_COMMAND_OPCODE 3960 { 3961 MEDIA_COMMAND_OPCODE_MFXCOMMON = 0, //!< No additional details 3962 }; 3963 3964 enum PIPELINE 3965 { 3966 PIPELINE_MFXPAKINSERTOBJECT = 2, //!< No additional details 3967 }; 3968 3969 enum COMMAND_TYPE 3970 { 3971 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3972 }; 3973 3974 //! \brief BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3975 //! \details 3976 //! Must be set to 1 for JPEG encoder 3977 enum BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3978 { 3979 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_INSERT = 0, //!< Insert the current command inline data starting at the current bitstream buffer insertion position 3980 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_RESET = 1, //!< Reset the bitstream buffer insertion position to the bitstream buffer starting position. 3981 }; 3982 3983 //! \brief EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3984 //! \details 3985 //! Must be set to 0 for JPEG encoder 3986 enum EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3987 { 3988 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_NONE = 0, //!< No emulation 3989 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_EMULATE = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between insertion commands, or an insertion command followed by a PAK Object command. 3990 }; 3991 3992 //! \brief SLICE_HEADER_INDICATOR 3993 //! \details 3994 //! This bit indicates if the insert object is a slice header. In the VDEnc 3995 //! mode, PAK only gets this command at the beginning of the frame for slice 3996 //! position X=0, Y=0. It internally generates the header that needs to be 3997 //! inserted per slice. For VDEnc mode, this bit should always be set. 3998 enum SLICE_HEADER_INDICATOR 3999 { 4000 SLICE_HEADER_INDICATOR_LEGACY = 0, //!< Legacy Insertion Object command. The PAK Insertion Object command is not stored in HW. 4001 SLICE_HEADER_INDICATOR_SLICEHEADER = 1, //!< Insertion Object is a Slice Header. The command is stored internally by HW and is used for inserting slice headers. 4002 }; 4003 4004 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 4005 //! \details 4006 //! In case this flag is on, bits are NOT accumulated during current access 4007 //! unit coding neither for Cabac Zero Word insertion bits counting or for 4008 //! output in MMIO register MFC_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER. 4009 //! When using HeaderLenghtExcludeFrmSize for header insertion, the 4010 //! software needs to make sure that data comes already with inserted start 4011 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 4012 //! DWORD1 of MFX_PAK_INSERT_OBJECT). 4013 enum HEADERLENGTHEXCLUDEFRMSIZE_ 4014 { 4015 HEADERLENGTHEXCLUDEFRMSIZE_ACCUMULATE = 0, //!< All bits accumulated 4016 HEADERLENGTHEXCLUDEFRMSIZE_NOACCUMULATION = 1, //!< Bits during current call are not accumulated 4017 }; 4018 4019 //! \name Initializations 4020 4021 //! \brief Explicit member initialization function 4022 MFX_PAK_INSERT_OBJECT_CMD(); 4023 4024 static const size_t dwSize = 2; 4025 static const size_t byteSize = 8; 4026 }; 4027 4028 //! 4029 //! \brief MFX_MPEG2_PIC_STATE 4030 //! \details 4031 //! This must be the very first command to issue after the surface state, 4032 //! the pipe select and base address setting commands. For MPEG-2 the 4033 //! encoder is called per slice-group, however the picture state is called 4034 //! per picture.Notice that a slice-group is a group of consecutive slices 4035 //! that no non-trivial slice headers are inserted in between. 4036 //! 4037 struct MFX_MPEG2_PIC_STATE_CMD 4038 { 4039 union 4040 { 4041 //!< DWORD 0 4042 struct 4043 { 4044 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4045 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4046 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 4047 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 4048 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 4049 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4050 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4051 }; 4052 uint32_t Value; 4053 } DW0; 4054 union 4055 { 4056 //!< DWORD 1 4057 struct 4058 { 4059 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4060 uint32_t ScanOrder : __CODEGEN_BITFIELD( 6, 6) ; //!< SCAN_ORDER 4061 uint32_t IntraVlcFormat : __CODEGEN_BITFIELD( 7, 7) ; //!< Intra VLC Format 4062 uint32_t QuantizerScaleType : __CODEGEN_BITFIELD( 8, 8) ; //!< QUANTIZER_SCALE_TYPE 4063 uint32_t ConcealmentMotionVectorFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< Concealment Motion Vector Flag 4064 uint32_t FramePredictionFrameDct : __CODEGEN_BITFIELD(10, 10) ; //!< Frame Prediction Frame DCT 4065 uint32_t TffTopFieldFirst : __CODEGEN_BITFIELD(11, 11) ; //!< TFF (Top Field First) 4066 uint32_t PictureStructure : __CODEGEN_BITFIELD(12, 13) ; //!< Picture Structure 4067 uint32_t IntraDcPrecision : __CODEGEN_BITFIELD(14, 15) ; //!< Intra DC Precision 4068 uint32_t FCode00 : __CODEGEN_BITFIELD(16, 19) ; //!< f_code[0][0] 4069 uint32_t FCode01 : __CODEGEN_BITFIELD(20, 23) ; //!< f_code[0][1] 4070 uint32_t FCode10 : __CODEGEN_BITFIELD(24, 27) ; //!< f_code[1][0]. 4071 uint32_t FCode11 : __CODEGEN_BITFIELD(28, 31) ; //!< f_code[1][1]. 4072 }; 4073 uint32_t Value; 4074 } DW1; 4075 union 4076 { 4077 //!< DWORD 2 4078 struct 4079 { 4080 uint32_t DisableMismatch : __CODEGEN_BITFIELD( 0, 0) ; //!< Disable Mismatch 4081 uint32_t Mismatchcontroldisabled : __CODEGEN_BITFIELD( 1, 1) ; //!< MISMATCHCONTROLDISABLED 4082 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 8) ; //!< Reserved 4083 uint32_t PictureCodingType : __CODEGEN_BITFIELD( 9, 10) ; //!< PICTURE_CODING_TYPE 4084 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13) ; //!< Reserved 4085 uint32_t LoadslicepointerflagLoadbitstreampointerperslice : __CODEGEN_BITFIELD(14, 14) ; //!< LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4086 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 23) ; //!< Reserved 4087 uint32_t PBSlicePredictedMotionVectorOverrideFinalMvValueOverride : __CODEGEN_BITFIELD(24, 24) ; //!< PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4088 uint32_t PBSlicePredictedBidirMotionTypeOverrideBiDirectionMvTypeOverride : __CODEGEN_BITFIELD(25, 26) ; //!< PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4089 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 27) ; //!< Reserved 4090 uint32_t PBSliceConcealmentMode : __CODEGEN_BITFIELD(28, 29) ; //!< PB_SLICE_CONCEALMENT_MODE_ 4091 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 4092 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31) ; //!< I_SLICE_CONCEALMENT_MODE_ 4093 }; 4094 uint32_t Value; 4095 } DW2; 4096 union 4097 { 4098 //!< DWORD 3 4099 struct 4100 { 4101 uint32_t Framewidthinmbsminus170PictureWidthInMacroblocks : __CODEGEN_BITFIELD( 0, 7) ; //!< FrameWidthInMBsMinus1[7:0] (Picture Width in Macroblocks) 4102 uint32_t Reserved104 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 4103 uint32_t Frameheightinmbsminus170PictureHeightInMacroblocks : __CODEGEN_BITFIELD(16, 23) ; //!< FrameHeightInMBsMinus1[7:0] (Picture Height in Macroblocks) 4104 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 30) ; //!< Reserved 4105 uint32_t SliceConcealmentDisableBit : __CODEGEN_BITFIELD(31, 31) ; //!< SLICE_CONCEALMENT_DISABLE_BIT 4106 }; 4107 uint32_t Value; 4108 } DW3; 4109 union 4110 { 4111 //!< DWORD 4 4112 struct 4113 { 4114 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 4115 uint32_t Roundintradc : __CODEGEN_BITFIELD( 1, 2) ; //!< RoundIntraDC 4116 uint32_t Reserved131 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 4117 uint32_t Roundinterdc : __CODEGEN_BITFIELD( 4, 6) ; //!< RoundInterDC 4118 uint32_t Reserved135 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 4119 uint32_t Roundintraac : __CODEGEN_BITFIELD( 8, 10) ; //!< RoundIntraAC 4120 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 4121 uint32_t Roundinterac : __CODEGEN_BITFIELD(12, 14) ; //!< RoundInterAC, 4122 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15) ; //!< MBSTATENABLED 4123 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31) ; //!< MINFRAMEWSIZE 4124 }; 4125 uint32_t Value; 4126 } DW4; 4127 union 4128 { 4129 //!< DWORD 5 4130 struct 4131 { 4132 uint32_t Intrambmaxsizereportmask : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAMBMAXSIZEREPORTMASK 4133 uint32_t Intermbmaxsizereportmask : __CODEGEN_BITFIELD( 1, 1) ; //!< INTERMBMAXSIZEREPORTMASK 4134 uint32_t Framebitratemaxreportmask : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMEBITRATEMAXREPORTMASK_ 4135 uint32_t Framebitrateminreportmask : __CODEGEN_BITFIELD( 3, 3) ; //!< FRAMEBITRATEMINREPORTMASK 4136 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 8) ; //!< Reserved 4137 uint32_t Mbratecontrolmask : __CODEGEN_BITFIELD( 9, 9) ; //!< MBRATECONTROLMASK 4138 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11) ; //!< MINFRAMEWSIZEUNITS 4139 uint32_t Intermbforcecbpzerocontrolmask : __CODEGEN_BITFIELD(12, 12) ; //!< INTERMBFORCECBPZEROCONTROLMASK 4140 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 4141 uint32_t Framesizecontrolmask : __CODEGEN_BITFIELD(16, 16) ; //!< FRAMESIZECONTROLMASK 4142 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 4143 }; 4144 uint32_t Value; 4145 } DW5; 4146 union 4147 { 4148 //!< DWORD 6 4149 struct 4150 { 4151 uint32_t Intrambmaxsize : __CODEGEN_BITFIELD( 0, 11) ; //!< INTRAMBMAXSIZE 4152 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4153 uint32_t Intermbmaxsize : __CODEGEN_BITFIELD(16, 27) ; //!< INTERMBMAXSIZE 4154 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 4155 }; 4156 uint32_t Value; 4157 } DW6; 4158 union 4159 { 4160 //!< DWORD 7 4161 struct 4162 { 4163 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSL_TOP_MB_TRANS8X8FLAG 4164 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 4165 }; 4166 uint32_t Value; 4167 } DW7; 4168 union 4169 { 4170 //!< DWORD 8 4171 struct 4172 { 4173 uint32_t Slicedeltaqpmax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQPMax[0] 4174 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQPMax[1] 4175 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQPMax[2] 4176 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31) ; //!< SLICEDELTAQPMAX3 4177 }; 4178 uint32_t Value; 4179 } DW8; 4180 union 4181 { 4182 //!< DWORD 9 4183 struct 4184 { 4185 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQPMin[0] 4186 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQPMin[1] 4187 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQPMin[2] 4188 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQPMin[3] 4189 }; 4190 uint32_t Value; 4191 } DW9; 4192 union 4193 { 4194 //!< DWORD 10 4195 struct 4196 { 4197 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 4198 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14) ; //!< FRAMEBITRATEMINUNITMODE 4199 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15) ; //!< FRAMEBITRATEMINUNIT 4200 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29) ; //!< FrameBitRateMax 4201 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30) ; //!< FRAMEBITRATEMAXUNITMODE 4202 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT_ 4203 }; 4204 uint32_t Value; 4205 } DW10; 4206 union 4207 { 4208 //!< DWORD 11 4209 struct 4210 { 4211 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FrameBitRateMinDelta 4212 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 4213 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 4214 uint32_t Reserved383 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 4215 }; 4216 uint32_t Value; 4217 } DW11; 4218 union 4219 { 4220 //!< DWORD 12 4221 struct 4222 { 4223 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4224 }; 4225 uint32_t Value; 4226 } DW12; 4227 4228 //! \name Local enumerations 4229 4230 enum SUBOPCODE_B 4231 { 4232 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 4233 }; 4234 4235 enum SUBOPCODE_A 4236 { 4237 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 4238 }; 4239 4240 enum MEDIA_COMMAND_OPCODE 4241 { 4242 MEDIA_COMMAND_OPCODE_MPEG2COMMON = 3, //!< No additional details 4243 }; 4244 4245 enum PIPELINE 4246 { 4247 PIPELINE_MFXMPEG2PICSTATE = 2, //!< No additional details 4248 }; 4249 4250 enum COMMAND_TYPE 4251 { 4252 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4253 }; 4254 4255 //! \brief SCAN_ORDER 4256 //! \details 4257 //! This field specifies the Inverse Scan method for the DCT-domain 4258 //! coefficients in the blocks of the current picture. 4259 enum SCAN_ORDER 4260 { 4261 SCAN_ORDER_UNNAMED0 = 0, //!< MPEG_ZIGZAG_SCAN 4262 SCAN_ORDER_UNNAMED1 = 1, //!< MPEG_ALTERNATE_VERTICAL_SCAN 4263 }; 4264 4265 //! \brief QUANTIZER_SCALE_TYPE 4266 //! \details 4267 //! This field specifies the quantizer scaling type. 4268 enum QUANTIZER_SCALE_TYPE 4269 { 4270 QUANTIZER_SCALE_TYPE_UNNAMED0 = 0, //!< MPEG_QSCALE_LINEAR 4271 QUANTIZER_SCALE_TYPE_UNNAMED1 = 1, //!< D MPEG_QSCALE_NONLINEAR esc 4272 }; 4273 4274 //! \brief MISMATCHCONTROLDISABLED 4275 //! \details 4276 //! These 2 bits flag disables mismatch control of the inverse 4277 //! transformation for some specific cases during reference reconstruction. 4278 enum MISMATCHCONTROLDISABLED 4279 { 4280 MISMATCHCONTROLDISABLED_UNNAMED0 = 0, //!< Mismatch control applies to all MBs 4281 MISMATCHCONTROLDISABLED_UNNAMED1 = 1, //!< Disable mismatch control to all intra MBs whose all AC-coefficients are zero. 4282 MISMATCHCONTROLDISABLED_UNNAMED2 = 2, //!< Disable mismatch control to all MBs whose all AC-coefficients are zero. 4283 MISMATCHCONTROLDISABLED_UNNAMED3 = 3, //!< Disable mismatch control to all MBs. 4284 }; 4285 4286 //! \brief PICTURE_CODING_TYPE 4287 //! \details 4288 //! This field identifies whether the picture is an intra-coded picture (I), 4289 //! predictive-coded picture (P) or bi-directionally predictive-coded 4290 //! picture (B). See ISO/IEC 13818-2 6.3.9 for details. 4291 enum PICTURE_CODING_TYPE 4292 { 4293 PICTURE_CODING_TYPE_MPEGIPICTURE = 1, //!< No additional details 4294 PICTURE_CODING_TYPE_10MPEGPPICTURE = 2, //!< No additional details 4295 PICTURE_CODING_TYPE_MPEGBPICTURE = 3, //!< No additional details 4296 }; 4297 4298 //! \brief LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4299 //! \details 4300 //! To support multiple slice picture and additional header/data insertion 4301 //! before and after an encoded slice.When this field is set to 0, bitstream 4302 //! pointer is only loaded once for the first slice of a frame. For 4303 //! subsequent slices in the frame, bitstream data are stitched together to 4304 //! form a single output data stream.When this field is set to 1, bitstream 4305 //! pointer is loaded for each slice of a frame. Basically bitstream data 4306 //! for different slices of a frame will be written to different memory 4307 //! locations. 4308 enum LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4309 { 4310 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED0 = 0, //!< Load BitStream Pointer only once for the first slice of a frame 4311 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED1 = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 4312 }; 4313 4314 //! \brief PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4315 //! \details 4316 //! This field is only applicable if the Concealment Motion Vectors are 4317 //! non-zero. 4318 //! It is only possible if "P/B Slice Concealment Mode" is set to "00" 4319 //! or "01" and left MB has non-zero motion vectors). 4320 enum PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4321 { 4322 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_PREDICTED = 0, //!< Motion Vectors use predicted values 4323 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_ZERO = 1, //!< Motion Vectors force to 0 4324 }; 4325 4326 //! \brief PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4327 //! \details 4328 //! This field is only applicable if the Concealment Motion Type is 4329 //! predicted to be Bi-directional. 4330 //! (It is only possible if "P/B Slice Concealment Mode" is set to "00" 4331 //! or "01" and left MB is a bi-directional MB). 4332 enum PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4333 { 4334 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BID = 0, //!< Keep Bi-direction Prediction 4335 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_FWD = 2, //!< Only use Forward Prediction (Backward MV is forced to invalid 4336 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BWD = 3, //!< Only use Backward Prediction (Forward MV is forced to invalid) 4337 }; 4338 4339 //! \brief PB_SLICE_CONCEALMENT_MODE_ 4340 //! \details 4341 //! This field controls how MPEG decoder handles MB concealment in P/B 4342 //! Slice. 4343 enum PB_SLICE_CONCEALMENT_MODE_ 4344 { 4345 PB_SLICE_CONCEALMENT_MODE_INTER = 0, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use forward reference (same polarity for field pic) with MV final values set to 0. 4346 PB_SLICE_CONCEALMENT_MODE_LEFT = 1, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data) 4347 PB_SLICE_CONCEALMENT_MODE_ZERO = 2, //!< Always use forward reference (same polarity for field pic) with MV final values set to 0 (Macroblock is concealed as INTER coded) 4348 PB_SLICE_CONCEALMENT_MODE_INTRA = 3, //!< Use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data 4349 }; 4350 4351 //! \brief I_SLICE_CONCEALMENT_MODE_ 4352 //! \details 4353 //! This field controls how MPEG decoder handles MB concealment in I Slice 4354 enum I_SLICE_CONCEALMENT_MODE_ 4355 { 4356 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< Using Coefficient values to handle MB concealment 4357 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< Using Motion Vectors to handle MB concealment 4358 }; 4359 4360 //! \brief SLICE_CONCEALMENT_DISABLE_BIT 4361 //! \details 4362 //! If VINunit detects the next slice starting position is either 4363 //! out-of-bound or smaller than or equal to the current slice starting 4364 //! position, VIN will set the current slice to be 1 MB and force VMDunit to 4365 //! do slice concealment on the next slice. 4366 //! This bit will disable this feature and the MB data from the next 4367 //! slice will be decoded from bitstream. 4368 enum SLICE_CONCEALMENT_DISABLE_BIT 4369 { 4370 SLICE_CONCEALMENT_DISABLE_BIT_ENABLE = 0, //!< VIN will force next slice to be concealment if detects slice boundary error 4371 SLICE_CONCEALMENT_DISABLE_BIT_DISABLE = 1, //!< VIN will not force next slice to be in concealment 4372 }; 4373 4374 //! \brief MINFRAMEWSIZE 4375 //! \details 4376 //! - Minimum Frame Size [15:0] (16-bit) (Encoder Only)Mininum Frame Size is 4377 //! specified to compensate for intel Rate ControlCurrently zero fill (no 4378 //! need to perform emulation byte insertion) is done only to the end of the 4379 //! CABAC_ZERO_WORD insertion (if any) at the last slice of a picture. Intel 4380 //! encoder parameter. The caller should always make sure 4381 //! that the value, represented by Mininum Frame Size, is always less than 4382 //! maximum frame size FrameBitRateMax (DWORD 10 bits 29:16). This field is 4383 //! reserved in Decode mode. 4384 enum MINFRAMEWSIZE 4385 { 4386 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 4387 }; 4388 4389 //! \brief INTRAMBMAXSIZEREPORTMASK 4390 //! \details 4391 //! This is a mask bit controlling if the condition of any intra MB in the 4392 //! frame exceeds IntraMBMaxSize. 4393 enum INTRAMBMAXSIZEREPORTMASK 4394 { 4395 INTRAMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4396 INTRAMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 4397 }; 4398 4399 //! \brief INTERMBMAXSIZEREPORTMASK 4400 //! \details 4401 //! This is a mask bit controlling if the condition of any inter MB in the 4402 //! frame exceeds InterMBMaxSize. 4403 enum INTERMBMAXSIZEREPORTMASK 4404 { 4405 INTERMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4406 INTERMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 4407 }; 4408 4409 //! \brief FRAMEBITRATEMAXREPORTMASK_ 4410 //! \details 4411 //! This is a mask bit controlling if the condition of frame level bit count 4412 //! exceeds FrameBitRateMax. 4413 enum FRAMEBITRATEMAXREPORTMASK_ 4414 { 4415 FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4416 FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 4417 }; 4418 4419 //! \brief FRAMEBITRATEMINREPORTMASK 4420 //! \details 4421 //! This is a mask bit controlling if the condition of frame level bit count 4422 //! is less than FrameBitRateMin. 4423 enum FRAMEBITRATEMINREPORTMASK 4424 { 4425 FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4426 FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 4427 }; 4428 4429 //! \brief MBRATECONTROLMASK 4430 //! \details 4431 //! MB Rate Control conformance maskThis field is ignored when 4432 //! MacroblockStatEnable is disabled or MB level Rate control flag for the 4433 //! current MB is disable in Macroblock Status Buffer. 4434 enum MBRATECONTROLMASK 4435 { 4436 MBRATECONTROLMASK_UNNAMED0 = 0, //!< Do not change QP values of inter macroblock with suggested QP values in Macroblock Status Buffer 4437 MBRATECONTROLMASK_UNNAMED1 = 1, //!< Apply RC QP delta for all macroblock 4438 }; 4439 4440 //! \brief MINFRAMEWSIZEUNITS 4441 //! \details 4442 //! This field is the Minimum Frame Size Units 4443 enum MINFRAMEWSIZEUNITS 4444 { 4445 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 4446 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 4447 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 4448 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 4449 }; 4450 4451 //! \brief INTERMBFORCECBPZEROCONTROLMASK 4452 //! \details 4453 //! Inter MB Force CBP ZERO mask. 4454 enum INTERMBFORCECBPZEROCONTROLMASK 4455 { 4456 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED0 = 0, //!< No effect 4457 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED1 = 1, //!< Zero out all A/C coefficients for the inter MB violating Inter Confirmance 4458 }; 4459 4460 //! \brief FRAMESIZECONTROLMASK 4461 //! \details 4462 //! Frame size conformance maskThis field is used when MacroblockStatEnable 4463 //! is set to 1. 4464 enum FRAMESIZECONTROLMASK 4465 { 4466 FRAMESIZECONTROLMASK_UNNAMED0 = 0, //!< Do not change Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control 4467 FRAMESIZECONTROLMASK_UNNAMED1 = 1, //!< Replace Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control values in MFC_IMAGE_STATUS control register. 4468 }; 4469 4470 //! \brief INTRAMBMAXSIZE 4471 //! \details 4472 //! This field, Intra MB Conformance Max size limit,indicates the allowed 4473 //! max bit count size for Intra MB 4474 enum INTRAMBMAXSIZE 4475 { 4476 INTRAMBMAXSIZE_UNNAMED_4095 = 4095, //!< No additional details 4477 }; 4478 4479 //! \brief INTERMBMAXSIZE 4480 //! \details 4481 //! This field, Inter MB Conformance Max size limit,indicates the allowed 4482 //! max bit count size for Inter MB 4483 enum INTERMBMAXSIZE 4484 { 4485 INTERMBMAXSIZE_UNNAMED_4095 = 4095, //!< No additional details 4486 }; 4487 4488 enum VSL_TOP_MB_TRANS8X8FLAG 4489 { 4490 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 4491 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 4492 }; 4493 4494 //! \brief SLICEDELTAQPMAX3 4495 //! \details 4496 //! This field is the Slice level delta QP for total 4497 //! bit-count above FrameBitRateMax - first 1/8 regionThis field is 4498 //! used to 4499 //! calculate the suggested slice QP into the MFC_IMAGE_STATUS control 4500 //! register when 4501 //! total bit count for the entire frame exceeds FrameBitRateMax but is 4502 //! within 1/8 4503 //! of FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range 4504 //! of 4505 //! (FrameBitRateMax, (FrameBitRateMax+ 4506 //! FrameBitRateMaxDelta>>3). 4507 enum SLICEDELTAQPMAX3 4508 { 4509 SLICEDELTAQPMAX3_DISABLE = 0, //!< No additional details 4510 SLICEDELTAQPMAX3_ENABLE = 1, //!< No additional details 4511 }; 4512 4513 //! \brief FRAMEBITRATEMINUNITMODE 4514 //! \details 4515 //! This field is the Frame Bitrate Minimum Limit 4516 //! Units.ValueNameDescriptionProject 4517 enum FRAMEBITRATEMINUNITMODE 4518 { 4519 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4520 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4521 }; 4522 4523 //! \brief FRAMEBITRATEMINUNIT 4524 //! \details 4525 //! This field is the Frame Bitrate Minimum Limit Units. 4526 enum FRAMEBITRATEMINUNIT 4527 { 4528 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 4529 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4530 }; 4531 4532 //! \brief FRAMEBITRATEMAXUNITMODE 4533 //! \details 4534 //! BitFiel This field is the Frame Bitrate Maximum Limit Units.dDesc 4535 enum FRAMEBITRATEMAXUNITMODE 4536 { 4537 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4538 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4539 }; 4540 4541 //! \brief FRAMEBITRATEMAXUNIT_ 4542 //! \details 4543 //! This field is the Frame Bitrate Maximum Limit Units. 4544 enum FRAMEBITRATEMAXUNIT_ 4545 { 4546 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 4547 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4548 }; 4549 4550 //! \brief FRAMEBITRATEMAXDELTA 4551 //! \details 4552 //! This field is used to select the slice delta QP when FrameBitRateMax Is 4553 //! exceeded. It shares the same FrameBitrateMaxUnit. 4554 //! The programmable range is either 0- 512KB or 4MBB in 4555 //! FrameBitrateMaxUnit of 128 Bytes or 16KB respectively. 4556 enum FRAMEBITRATEMAXDELTA 4557 { 4558 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 4559 }; 4560 4561 //! \name Initializations 4562 4563 //! \brief Explicit member initialization function 4564 MFX_MPEG2_PIC_STATE_CMD(); 4565 4566 static const size_t dwSize = 13; 4567 static const size_t byteSize = 52; 4568 }; 4569 4570 //! 4571 //! \brief MFD_MPEG2_BSD_OBJECT 4572 //! \details 4573 //! Different from AVC and VC1, MFD_MPEG2_BSD_OBJECT command is pipelinable. 4574 //! This is for performance purpose as in MPEG2 a slice is defined as a 4575 //! group of MBs of any size that must be within a macroblock row.Slice 4576 //! header parameters are passed in as inline data and the bitstream data 4577 //! for the slice is passed in as indirect data. Of the inline data, 4578 //! slice_horizontal_position and slice_vertical_position determines the 4579 //! location within the destination picture of the first macroblock in the 4580 //! slice. The content in this command is identical to that in the 4581 //! MEDIA_OBJECT command in VLD mode described in the Media Chapter. 4582 //! 4583 struct MFD_MPEG2_BSD_OBJECT_CMD 4584 { 4585 union 4586 { 4587 //!< DWORD 0 4588 struct 4589 { 4590 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4591 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4592 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 4593 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 4594 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 4595 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4596 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4597 }; 4598 uint32_t Value; 4599 } DW0; 4600 union 4601 { 4602 //!< DWORD 1 4603 struct 4604 { 4605 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 4606 }; 4607 uint32_t Value; 4608 } DW1; 4609 union 4610 { 4611 //!< DWORD 2 4612 struct 4613 { 4614 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 4615 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4616 }; 4617 uint32_t Value; 4618 } DW2; 4619 union 4620 { 4621 //!< DWORD 3 4622 struct 4623 { 4624 uint32_t FirstMacroblockBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< First Macroblock Bit Offset 4625 uint32_t IsLastMb : __CODEGEN_BITFIELD( 3, 3) ; //!< IS_LAST_MB 4626 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 4627 uint32_t LastPicSlice : __CODEGEN_BITFIELD( 5, 5) ; //!< LAST_PIC_SLICE 4628 uint32_t SliceConcealmentTypeBit : __CODEGEN_BITFIELD( 6, 6) ; //!< SLICE_CONCEALMENT_TYPE_BIT 4629 uint32_t SliceConcealmentOverrideBit : __CODEGEN_BITFIELD( 7, 7) ; //!< SLICE_CONCEALMENT_OVERRIDE_BIT 4630 uint32_t MacroblockCount : __CODEGEN_BITFIELD( 8, 15) ; //!< Macroblock Count 4631 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Vertical Position 4632 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(24, 31) ; //!< Slice Horizontal Position 4633 }; 4634 uint32_t Value; 4635 } DW3; 4636 union 4637 { 4638 //!< DWORD 4 4639 struct 4640 { 4641 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD( 0, 7) ; //!< Next Slice Horizontal Position 4642 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD( 8, 16) ; //!< Next Slice Vertical Position 4643 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 23) ; //!< Reserved 4644 uint32_t QuantizerScaleCode : __CODEGEN_BITFIELD(24, 28) ; //!< Quantizer Scale Code 4645 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4646 }; 4647 uint32_t Value; 4648 } DW4; 4649 4650 //! \name Local enumerations 4651 4652 enum SUBOPCODE_B 4653 { 4654 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 4655 }; 4656 4657 enum SUBOPCODE_A 4658 { 4659 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 4660 }; 4661 4662 enum MEDIA_COMMAND_OPCODE 4663 { 4664 MEDIA_COMMAND_OPCODE_MPEG2DEC = 3, //!< No additional details 4665 }; 4666 4667 enum PIPELINE 4668 { 4669 PIPELINE_MFDMPEG2BSDOBJECT = 2, //!< No additional details 4670 }; 4671 4672 enum COMMAND_TYPE 4673 { 4674 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4675 }; 4676 4677 enum IS_LAST_MB 4678 { 4679 IS_LAST_MB_UNNAMED0 = 0, //!< The current MB is not the last MB in the current Slice 4680 IS_LAST_MB_UNNAMED1 = 1, //!< The current MB is the last MB in the current Slice 4681 }; 4682 4683 //! \brief LAST_PIC_SLICE 4684 //! \details 4685 //! This bit is added to support error concealment at the end of a picture. 4686 enum LAST_PIC_SLICE 4687 { 4688 LAST_PIC_SLICE_UNNAMED0 = 0, //!< The current Slice is not the last Slice of current picture 4689 LAST_PIC_SLICE_UNNAMED1 = 1, //!< The current Slice is the last Slice of the entire picture 4690 }; 4691 4692 //! \brief SLICE_CONCEALMENT_TYPE_BIT 4693 //! \details 4694 //! This bit can be forced by driver ("Slice Concealment Override Bit") or 4695 //! set by VINunit depending on slice boundary errors. 4696 enum SLICE_CONCEALMENT_TYPE_BIT 4697 { 4698 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED0 = 0, //!< VMD will decode MBs from the bitstream until the bitstream is run-out. Then VMD will conceal the remaining MBs. 4699 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED1 = 1, //!< VMD will conceal all MBs of the slice regardless of bitstream. (If driver does not force the value of this bit, VIN will set this bit depending on slice boundary error. If the next slice position of the current slice is out-of-bound or the same or earlier than the current slice start position, VIN will set this bit for the next slice) 4700 }; 4701 4702 //! \brief SLICE_CONCEALMENT_OVERRIDE_BIT 4703 //! \details 4704 //! This bit forces hardware to handle the current slice in Conceal or 4705 //! Deocde Mode. If this bit is set to one, VIN will force the current 4706 //! slice to do concealment or to decode from bitstream regardless if the 4707 //! slice boundary has errors or not. 4708 enum SLICE_CONCEALMENT_OVERRIDE_BIT 4709 { 4710 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED0 = 0, //!< Driver must program "Slice Concealment Type" to '0'. VIN will set "Slice Concealment Type" depending if the slice boundary has error or not 4711 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED1 = 1, //!< VIN will use driver-provided "Slice Concealment Type" regardless of valid slice boundary 4712 }; 4713 4714 //! \name Initializations 4715 4716 //! \brief Explicit member initialization function 4717 MFD_MPEG2_BSD_OBJECT_CMD(); 4718 4719 static const size_t dwSize = 5; 4720 static const size_t byteSize = 20; 4721 }; 4722 4723 //! 4724 //! \brief MFD_IT_OBJECT_MPEG2_INLINE_DATA 4725 //! \details 4726 //! The content in this command is similar to that in the MEDIA_OBJECT 4727 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4728 //! command corresponds to the processing of one macroblock. Macroblock 4729 //! parameters are passed in as inline data and the non-zero DCT coefficient 4730 //! data for the macroblock is passed in as indirect data. Inline data 4731 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4732 //! 4733 struct MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD 4734 { 4735 union 4736 { 4737 //!< DWORD 0 4738 struct 4739 { 4740 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 2); //!< Reserved 4741 uint32_t Lastmbinrow : __CODEGEN_BITFIELD(3, 3); //!< LastMBInRow 4742 uint32_t Reserved4 : __CODEGEN_BITFIELD(4, 5); //!< Reserved 4743 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD(6, 11); //!< Coded Block Pattern 4744 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 4745 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16); //!< MACROBLOCK_INTRA_TYPE 4746 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17); //!< MACROBLOCK_MOTION_FORWARD 4747 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18); //!< MACROBLOCK_MOTION_BACKWARD 4748 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 20); //!< Reserved 4749 uint32_t DctType : __CODEGEN_BITFIELD(21, 21); //!< DCT_TYPE 4750 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 23); //!< Reserved 4751 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25); //!< Motion Type 4752 uint32_t Reserved26 : __CODEGEN_BITFIELD(26, 27); //!< Reserved 4753 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31); //!< MOTION_VERTICAL_FIELD_SELECT 4754 }; 4755 uint32_t Value; 4756 } DW0; 4757 union 4758 { 4759 //!< DWORD 1 4760 struct 4761 { 4762 uint32_t Horzorigin : __CODEGEN_BITFIELD(0, 7); //!< HorzOrigin 4763 uint32_t Vertorigin : __CODEGEN_BITFIELD(8, 15); //!< VertOrigin 4764 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 4765 }; 4766 uint32_t Value; 4767 } DW1; 4768 union 4769 { 4770 //!< DWORD 2 4771 struct 4772 { 4773 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Forward, Horizontal Component 4774 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Forward, Vertical Component 4775 }; 4776 uint32_t Value; 4777 } DW2; 4778 union 4779 { 4780 //!< DWORD 3 4781 struct 4782 { 4783 uint32_t MotionVectorsField0BackwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Backward, Horizontal Component 4784 uint32_t MotionVectorsField0BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Backward, Vertical Component 4785 }; 4786 uint32_t Value; 4787 } DW3; 4788 union 4789 { 4790 //!< DWORD 4 4791 struct 4792 { 4793 uint32_t MotionVectorsField1ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 1, Forward, Horizontal Component 4794 uint32_t MotionVectorsField1ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 1, Forward, Vertical Component 4795 }; 4796 uint32_t Value; 4797 } DW4; 4798 union 4799 { 4800 //!< DWORD 5 4801 struct 4802 { 4803 uint32_t MotionVectorsField1BackwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 1, Backward, Horizontal Component 4804 uint32_t MotionVectorsField1BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 1, Backward, Vertical Component 4805 }; 4806 uint32_t Value; 4807 } DW5; 4808 4809 //! \name Local enumerations 4810 4811 //! \brief MACROBLOCK_INTRA_TYPE 4812 //! \details 4813 //! This field specifies if the current macroblock is intra-coded. When set, 4814 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 4815 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 4816 enum MACROBLOCK_INTRA_TYPE 4817 { 4818 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 4819 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 4820 }; 4821 4822 //! \brief MACROBLOCK_MOTION_FORWARD 4823 //! \details 4824 //! This field specifies if the forward motion vector is active. See ISO/IEC 4825 //! 13818-2 Tables B-2 through B-4. 4826 enum MACROBLOCK_MOTION_FORWARD 4827 { 4828 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 4829 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTORS = 1, //!< No additional details 4830 }; 4831 4832 //! \brief MACROBLOCK_MOTION_BACKWARD 4833 //! \details 4834 //! This field specifies if the backward motion vector is active. See 4835 //! ISO/IEC 13818-2 Tables B-2 through B-4. 4836 enum MACROBLOCK_MOTION_BACKWARD 4837 { 4838 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 4839 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTORS = 1, //!< No additional details 4840 }; 4841 4842 //! \brief DCT_TYPE 4843 //! \details 4844 //! This field specifies the DCT type of the current macroblock. The kernel 4845 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 4846 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 4847 //! (no coded blocks present). 4848 enum DCT_TYPE 4849 { 4850 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 4851 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 4852 }; 4853 4854 //! \brief MOTION_VERTICAL_FIELD_SELECT 4855 //! \details 4856 //! A bit-wise representation of a long [2][2] array as defined in 4857 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also #167;7.6.4). 4858 //! <table> 4859 //! <thead> 4860 //! 4861 //! <tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 4862 //! Index</td></tr> 4863 //! </thead> 4864 //! <tbody> 4865 //! <tr><td>28</td><td>0</td><td>0</td><td>0</td></tr> 4866 //! <tr><td>29</td><td>0</td><td>1</td><td>1</td></tr> 4867 //! <tr><td>30</td><td>1</td><td>0</td><td>2</td></tr> 4868 //! <tr><td>31</td><td>1</td><td>1</td><td>3</td></tr> 4869 //! </tbody> 4870 //! </table> 4871 enum MOTION_VERTICAL_FIELD_SELECT 4872 { 4873 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field. 4874 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 4875 }; 4876 4877 //! \name Initializations 4878 4879 //! \brief Explicit member initialization function 4880 MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD(); 4881 4882 static const size_t dwSize = 6; 4883 static const size_t byteSize = 24; 4884 }; 4885 4886 //! 4887 //! \brief MFD_IT_OBJECT_VC1_INLINE_DATA 4888 //! \details 4889 //! The content in this command is similar to that in the MEDIA_OBJECT 4890 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4891 //! command corresponds to the processing of one macroblock. Macroblock 4892 //! parameters are passed in as inline data and the non-zero DCT coefficient 4893 //! data for the macroblock is passed in as indirect data. Inline data 4894 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4895 //! 4896 struct MFD_IT_OBJECT_VC1_INLINE_DATA_CMD 4897 { 4898 union 4899 { 4900 //!< DWORD 0 4901 struct 4902 { 4903 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 2); //!< Reserved 4904 uint32_t Lastmbinrow : __CODEGEN_BITFIELD(3, 3); //!< LastMBInRow 4905 uint32_t LastRowFlag : __CODEGEN_BITFIELD(4, 4); //!< Last Row Flag 4906 uint32_t ChromaIntraFlag : __CODEGEN_BITFIELD(5, 5); //!< Chroma Intra Flag 4907 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD(6, 11); //!< Coded Block Pattern 4908 uint32_t LumaIntra8X8Flag : __CODEGEN_BITFIELD(12, 15); //!< Luma Intra 8x8 Flag 4909 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16); //!< MACROBLOCK_INTRA_TYPE 4910 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17); //!< MACROBLOCK_MOTION_FORWARD 4911 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18); //!< MACROBLOCK_MOTION_BACKWARD 4912 uint32_t Motion4Mv : __CODEGEN_BITFIELD(19, 19); //!< MOTION4MV 4913 uint32_t Overlaptransform : __CODEGEN_BITFIELD(20, 20); //!< OVERLAPTRANSFORM 4914 uint32_t DctType : __CODEGEN_BITFIELD(21, 21); //!< DCT_TYPE 4915 uint32_t Mvswitch : __CODEGEN_BITFIELD(22, 22); 4916 uint32_t Reserved23 : __CODEGEN_BITFIELD(23, 23); //!< Reserved 4917 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25); //!< Motion Type 4918 uint32_t Mvfieldselectchroma : __CODEGEN_BITFIELD(26, 26); //!< MvFieldSelectChroma 4919 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 27); //!< Reserved 4920 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31); //!< MOTION_VERTICAL_FIELD_SELECT 4921 }; 4922 uint32_t Value; 4923 } DW0; 4924 union 4925 { 4926 //!< DWORD 1 4927 struct 4928 { 4929 uint32_t Horzorigin : __CODEGEN_BITFIELD(0, 7); //!< HorzOrigin 4930 uint32_t Vertorigin : __CODEGEN_BITFIELD(8, 15); //!< VertOrigin 4931 uint32_t Osedgemaskluma : __CODEGEN_BITFIELD(16, 23); //!< OSEdgeMaskLuma 4932 uint32_t Osedgemaskchroma : __CODEGEN_BITFIELD(24, 25); //!< OSEdgeMaskChroma 4933 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31); //!< Reserved 4934 }; 4935 uint32_t Value; 4936 } DW1; 4937 union 4938 { 4939 //!< DWORD 2 4940 struct 4941 { 4942 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD(0, 15); //!< Motion Vectors - Field 0, Forward, Horizontal Component 4943 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31); //!< Motion Vectors - Field 0, Forward, Vertical Component 4944 }; 4945 uint32_t Value; 4946 } DW2; 4947 union 4948 { 4949 //!< DWORD 3 4950 struct 4951 { 4952 uint32_t Motionvector1; //!< MotionVector1 4953 }; 4954 uint32_t Value; 4955 } DW3; 4956 union 4957 { 4958 //!< DWORD 4 4959 struct 4960 { 4961 uint32_t Motionvector2; //!< MotionVector2 4962 }; 4963 uint32_t Value; 4964 } DW4; 4965 union 4966 { 4967 //!< DWORD 5 4968 struct 4969 { 4970 uint32_t Motionvector3; //!< MotionVector3 4971 }; 4972 uint32_t Value; 4973 } DW5; 4974 union 4975 { 4976 //!< DWORD 6 4977 struct 4978 { 4979 uint32_t Motionvectorchroma; //!< MotionVectorChroma 4980 }; 4981 uint32_t Value; 4982 } DW6; 4983 union 4984 { 4985 //!< DWORD 7 4986 struct 4987 { 4988 uint32_t SubblockCodeForY0 : __CODEGEN_BITFIELD(0, 7); //!< Subblock Code for Y0 4989 uint32_t SubblockCodeForY1 : __CODEGEN_BITFIELD(8, 15); //!< Subblock Code for Y1 4990 uint32_t SubblockCodeForY2 : __CODEGEN_BITFIELD(16, 23); //!< Subblock Code for Y2 4991 uint32_t SubblockCodeForY3 : __CODEGEN_BITFIELD(24, 31); //!< Subblock Code for Y3 4992 }; 4993 uint32_t Value; 4994 } DW7; 4995 union 4996 { 4997 //!< DWORD 8 4998 struct 4999 { 5000 uint32_t SubblockCodeForCb : __CODEGEN_BITFIELD(0, 7); //!< Subblock Code for Cb 5001 uint32_t SubblockCodeForCr : __CODEGEN_BITFIELD(8, 15); //!< Subblock Code for Cr 5002 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 5003 }; 5004 uint32_t Value; 5005 } DW8; 5006 union 5007 { 5008 //!< DWORD 9 5009 struct 5010 { 5011 uint32_t IldbControlDataForBlockY0 : __CODEGEN_BITFIELD(0, 7); //!< ILDB control data for block Y0 5012 uint32_t IldbControlDataForBlockY1 : __CODEGEN_BITFIELD(8, 15); //!< ILDB control data for block Y1 5013 uint32_t IldbControlDataForBlockY2 : __CODEGEN_BITFIELD(16, 23); //!< ILDB control data for block Y2 5014 uint32_t IldbControlDataForBlockY3 : __CODEGEN_BITFIELD(24, 31); //!< ILDB control data for block Y3 5015 }; 5016 uint32_t Value; 5017 } DW9; 5018 union 5019 { 5020 //!< DWORD 10 5021 struct 5022 { 5023 uint32_t IldbControlDataForCbBlock : __CODEGEN_BITFIELD(0, 7); //!< ILDB control data for Cb block 5024 uint32_t IldbControlDataForCrBlock : __CODEGEN_BITFIELD(8, 15); //!< ILDB control data for Cr block 5025 uint32_t Reserved336 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 5026 }; 5027 uint32_t Value; 5028 } DW10; 5029 5030 //! \name Local enumerations 5031 5032 //! \brief MACROBLOCK_INTRA_TYPE 5033 //! \details 5034 //! This field specifies if the current macroblock is intra-coded. When set, 5035 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 5036 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 5037 enum MACROBLOCK_INTRA_TYPE 5038 { 5039 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 5040 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 5041 }; 5042 5043 //! \brief MACROBLOCK_MOTION_FORWARD 5044 //! \details 5045 //! This field specifies if the forward motion vector is active. See ISO/IEC 5046 //! 13818-2 Tables B-2 through B-4. 5047 enum MACROBLOCK_MOTION_FORWARD 5048 { 5049 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 5050 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTORS = 1, //!< No additional details 5051 }; 5052 5053 //! \brief MACROBLOCK_MOTION_BACKWARD 5054 //! \details 5055 //! This field specifies if the backward motion vector is active. See 5056 //! ISO/IEC 13818-2 Tables B-2 through B-4. 5057 enum MACROBLOCK_MOTION_BACKWARD 5058 { 5059 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 5060 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTORS = 1, //!< No additional details 5061 }; 5062 5063 enum MOTION4MV 5064 { 5065 MOTION4MV_1MV_MODE = 0, //!< No additional details 5066 MOTION4MV_4MV_MODE = 1, //!< No additional details 5067 }; 5068 5069 //! \brief OVERLAPTRANSFORM 5070 //! \details 5071 //! Was Overlap Transform - H261 Loop Filter 5072 enum OVERLAPTRANSFORM 5073 { 5074 OVERLAPTRANSFORM_NOOVERLAPSMOOTHINGFILTER = 0, //!< This field indicates whether overlap smoothing filter should be performed on I-block boundaries. 5075 OVERLAPTRANSFORM_OVERLAPSMOOTHINGFILTERPERFORMED = 1, //!< Macroblock is field DCT coded 5076 }; 5077 5078 //! \brief DCT_TYPE 5079 //! \details 5080 //! This field specifies the DCT type of the current macroblock. The kernel 5081 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 5082 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 5083 //! (no coded blocks present). 5084 enum DCT_TYPE 5085 { 5086 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 5087 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 5088 }; 5089 5090 //! \brief MOTION_VERTICAL_FIELD_SELECT 5091 //! \details 5092 //! A bit-wise representation of a long [2][2] array as defined in 5093 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also #167;7.6.4). 5094 //! <table> 5095 //! <thead> 5096 //! 5097 //! <tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 5098 //! Index</td></tr> 5099 //! </thead> 5100 //! <tbody> 5101 //! <tr><td>28</td><td>0</td><td>0</td><td>0</td></tr> 5102 //! <tr><td>29</td><td>0</td><td>1</td><td>1</td></tr> 5103 //! <tr><td>30</td><td>1</td><td>0</td><td>2</td></tr> 5104 //! <tr><td>31</td><td>1</td><td>1</td><td>3</td></tr> 5105 //! </tbody> 5106 //! </table> 5107 enum MOTION_VERTICAL_FIELD_SELECT 5108 { 5109 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field. 5110 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 5111 }; 5112 5113 //! \name Initializations 5114 5115 //! \brief Explicit member initialization function 5116 MFD_IT_OBJECT_VC1_INLINE_DATA_CMD(); 5117 5118 static const size_t dwSize = 11; 5119 static const size_t byteSize = 44; 5120 }; 5121 5122 //! 5123 //! \brief MFD_IT_OBJECT 5124 //! \details 5125 //! All weight mode (default and implicit) are mapped to explicit mode. But 5126 //! the weights come in either as explicit or implicit. 5127 //! 5128 struct MFD_IT_OBJECT_CMD 5129 { 5130 union 5131 { 5132 //!< DWORD 0 5133 struct 5134 { 5135 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5136 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5137 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5138 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5139 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5140 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5141 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5142 }; 5143 uint32_t Value; 5144 } DW0; 5145 union 5146 { 5147 //!< DWORD 1 5148 struct 5149 { 5150 uint32_t IndirectItMvDataLength : __CODEGEN_BITFIELD( 0, 9) ; //!< Indirect IT-MV Data Length 5151 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 5152 }; 5153 uint32_t Value; 5154 } DW1; 5155 union 5156 { 5157 //!< DWORD 2 5158 struct 5159 { 5160 uint32_t IndirectItMvDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-MV Data Start Address Offset 5161 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5162 }; 5163 uint32_t Value; 5164 } DW2; 5165 union 5166 { 5167 //!< DWORD 3 5168 struct 5169 { 5170 uint32_t IndirectItCoeffDataLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Indirect IT-COEFF Data Length 5171 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 5172 }; 5173 uint32_t Value; 5174 } DW3; 5175 union 5176 { 5177 //!< DWORD 4 5178 struct 5179 { 5180 uint32_t IndirectItCoeffDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-COEFF Data Start Address Offset 5181 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5182 }; 5183 uint32_t Value; 5184 } DW4; 5185 union 5186 { 5187 //!< DWORD 5 5188 struct 5189 { 5190 uint32_t IndirectItDblkControlDataLength : __CODEGEN_BITFIELD( 0, 5) ; //!< Indirect IT-DBLK Control Data Length 5191 uint32_t Reserved166 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 5192 }; 5193 uint32_t Value; 5194 } DW5; 5195 union 5196 { 5197 //!< DWORD 6 5198 struct 5199 { 5200 uint32_t IndirectItDblkControlDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-DBLK Control Data Start Address Offset 5201 uint32_t Reserved221 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5202 }; 5203 uint32_t Value; 5204 } DW6; 5205 5206 //! \name Local enumerations 5207 5208 enum SUBOPCODE_B 5209 { 5210 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 5211 }; 5212 5213 enum SUBOPCODE_A 5214 { 5215 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5216 }; 5217 5218 enum MEDIA_COMMAND_OPCODE 5219 { 5220 MEDIA_COMMAND_OPCODE_MFXCOMMONDEC = 0, //!< No additional details 5221 }; 5222 5223 enum PIPELINE 5224 { 5225 PIPELINE_MFDITOBJECT = 2, //!< No additional details 5226 }; 5227 5228 enum COMMAND_TYPE 5229 { 5230 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5231 }; 5232 5233 //! \name Initializations 5234 5235 //! \brief Explicit member initialization function 5236 MFD_IT_OBJECT_CMD(); 5237 5238 static const size_t dwSize = 7; 5239 static const size_t byteSize = 28; 5240 }; 5241 5242 //! 5243 //! \brief MFC_MPEG2_SLICEGROUP_STATE 5244 //! \details 5245 //! This is a slice group level command and can be issued multiple times 5246 //! within a picture that is comprised of multiple slice groups. The same 5247 //! command is used for AVC encoder (PAK mode) and decoder (VLD and IT 5248 //! modes). 5249 //! 5250 struct MFC_MPEG2_SLICEGROUP_STATE_CMD 5251 { 5252 union 5253 { 5254 //!< DWORD 0 5255 struct 5256 { 5257 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5258 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5259 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5260 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5261 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5262 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5263 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5264 }; 5265 uint32_t Value; 5266 } DW0; 5267 union 5268 { 5269 //!< DWORD 1 5270 struct 5271 { 5272 uint32_t Streamid10EncoderOnly : __CODEGEN_BITFIELD( 0, 1) ; //!< StreamID[1:0] (Encoder-only) 5273 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 5274 uint32_t Sliceid30EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< SliceID[3:0] (Encoder-only) 5275 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 5276 uint32_t Intrasliceflag : __CODEGEN_BITFIELD(12, 12) ; //!< IntraSliceFlag 5277 uint32_t Intraslice : __CODEGEN_BITFIELD(13, 13) ; //!< IntraSlice 5278 uint32_t Firstslicehdrdisabled : __CODEGEN_BITFIELD(14, 14) ; //!< FirstSliceHdrDisabled 5279 uint32_t TailpresentflagTailInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(15, 15) ; //!< TAILPRESENTFLAG__TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5280 uint32_t SlicedataPresentflagSlicedataInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(16, 16) ; //!< SLICEDATA_PRESENTFLAG__SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5281 uint32_t HeaderpresentflagHeaderInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(17, 17) ; //!< HEADERPRESENTFLAG__HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5282 uint32_t BitstreamoutputflagCompressedBitstreamOutputDisableFlagEncoderOnly : __CODEGEN_BITFIELD(18, 18) ; //!< BITSTREAMOUTPUTFLAG__COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5283 uint32_t Islastslicegrp : __CODEGEN_BITFIELD(19, 19) ; //!< IsLastSliceGrp 5284 uint32_t SkipconvdisabledMbTypeSkipConversionDisableEncoderOnly : __CODEGEN_BITFIELD(20, 20) ; //!< SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5285 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 5286 uint32_t RatectrlpanictypeRcPanicTypeEncoderOnly : __CODEGEN_BITFIELD(22, 22) ; //!< RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5287 uint32_t RatectrlpanicflagRcPanicEnableEncoderOnly : __CODEGEN_BITFIELD(23, 23) ; //!< RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5288 uint32_t MbratectrlparamRcStableToleranceEncoderOnly : __CODEGEN_BITFIELD(24, 27) ; //!< MbRateCtrlParam- RC Stable Tolerance (Encoder-only) 5289 uint32_t MbratectrlmodeRcTriggleModeEncoderOnly : __CODEGEN_BITFIELD(28, 29) ; //!< MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5290 uint32_t MbratectrlresetResetratecontrolcounterEncoderOnly : __CODEGEN_BITFIELD(30, 30) ; //!< MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5291 uint32_t MbratectrlflagRatecontrolcounterenableEncoderOnly : __CODEGEN_BITFIELD(31, 31) ; //!< MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5292 }; 5293 uint32_t Value; 5294 } DW1; 5295 union 5296 { 5297 //!< DWORD 2 5298 struct 5299 { 5300 uint32_t FirstmbxcntAlsoCurrstarthorzpos : __CODEGEN_BITFIELD( 0, 7) ; //!< FirstMbXcnt - also CurrStartHorzPos 5301 uint32_t FirstmbycntAlsoCurrstartvertpos : __CODEGEN_BITFIELD( 8, 15) ; //!< FirstMbYcnt - also CurrStartVertPos 5302 uint32_t NextsgmbxcntAlsoNextstarthorzpos : __CODEGEN_BITFIELD(16, 23) ; //!< NextSgMbXcnt - also NextStartHorzPos 5303 uint32_t NextsgmbycntAlsoNextstartvertpos : __CODEGEN_BITFIELD(24, 31) ; //!< NextSgMbYcnt - also NextStartVertPos 5304 }; 5305 uint32_t Value; 5306 } DW2; 5307 union 5308 { 5309 //!< DWORD 3 5310 struct 5311 { 5312 uint32_t Slicegroupqp : __CODEGEN_BITFIELD( 0, 5) ; //!< SliceGroupQp 5313 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5314 uint32_t Slicegroupskip : __CODEGEN_BITFIELD( 8, 8) ; //!< SliceGroupSkip 5315 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 5316 }; 5317 uint32_t Value; 5318 } DW3; 5319 union 5320 { 5321 //!< DWORD 4 5322 struct 5323 { 5324 uint32_t BitstreamoffsetIndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD( 0, 28) ; //!< BitstreamOffset - Indirect PAK-BSE Data Start Address (Write) 5325 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5326 }; 5327 uint32_t Value; 5328 } DW4; 5329 union 5330 { 5331 //!< DWORD 5 5332 struct 5333 { 5334 uint32_t GrowparamGrowInitEncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< GrowParam - Grow Init (Encoder-only) 5335 uint32_t GrowparamGrowResistanceEncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< GrowParam - Grow Resistance (Encoder-only) 5336 uint32_t ShrinkaramShrinkInitEncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< Shrinkaram - Shrink Init (Encoder-only) 5337 uint32_t ShrinkparamShrinkResistanceEncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< ShrinkParam - Shrink Resistance (Encoder-only) 5338 uint32_t MaxqpposmodifierMagnitudeOfQpMaxPositiveModifierEncoderOnly : __CODEGEN_BITFIELD(16, 23) ; //!< MaxQpPosModifier - Magnitude of QP Max Positive Modifier (Encoder-only) 5339 uint32_t MaxqpnegmodifierMagnitudeOfQpMaxNegativeModifierEncoderOnly : __CODEGEN_BITFIELD(24, 31) ; //!< MaxQpNegModifier - Magnitude of QP Max Negative Modifier (Encoder-only) 5340 }; 5341 uint32_t Value; 5342 } DW5; 5343 union 5344 { 5345 //!< DWORD 6 5346 struct 5347 { 5348 uint32_t CorrectpointsCorrect1EncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< CorrectPoints - Correct 1 (Encoder-only) 5349 uint32_t CorrectpointsCorrect2EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< CorrectPoints - Correct 2 (Encoder-only) 5350 uint32_t CorrectpointsCorrect3EncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< CorrectPoints - Correct 3 (Encoder-only) 5351 uint32_t CorrectpointsCorrect4EncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< CorrectPoints - Correct 4 (Encoder-only) 5352 uint32_t CorrectpointsCorrect5EncoderOnly : __CODEGEN_BITFIELD(16, 19) ; //!< CorrectPoints - Correct 5 (Encoder-only) 5353 uint32_t CorrectpointsCorrect6EncoderOnly : __CODEGEN_BITFIELD(20, 23) ; //!< CorrectPoints - Correct 6 (Encoder-only) 5354 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 5355 }; 5356 uint32_t Value; 5357 } DW6; 5358 union 5359 { 5360 //!< DWORD 7 5361 struct 5362 { 5363 uint32_t Cv0ClampValue0EncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 (Encoder-only) 5364 uint32_t Cv1ClampValue1EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 - Clamp Value 1 (Encoder-only) 5365 uint32_t Cv2ClampValue2EncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 - Clamp Value 2 (Encoder-only) 5366 uint32_t Cv3ClampValue3EncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 - Clamp Value 3 (Encoder-only) 5367 uint32_t Cv4ClampValue4EncoderOnly : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 - Clamp Value 4 (Encoder-only) 5368 uint32_t Cv5ClampValue5EncoderOnly : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 - Clamp Value 5 (Encoder-only) 5369 uint32_t Cv6ClampValue6EncoderOnly : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 - Clamp Value 6 (Encoder-only) 5370 uint32_t Cv7ClampValue7EncoderOnly : __CODEGEN_BITFIELD(28, 31) ; //!< CV7 - Clamp Value 7 (Encoder-only) 5371 }; 5372 uint32_t Value; 5373 } DW7; 5374 5375 //! \name Local enumerations 5376 5377 enum SUBOPCODE_B 5378 { 5379 SUBOPCODE_B_MEDIA = 3, //!< No additional details 5380 }; 5381 5382 enum SUBOPCODE_A 5383 { 5384 SUBOPCODE_A_MEDIA = 2, //!< No additional details 5385 }; 5386 5387 enum MEDIA_COMMAND_OPCODE 5388 { 5389 MEDIA_COMMAND_OPCODE_MPEG2 = 3, //!< No additional details 5390 }; 5391 5392 enum PIPELINE 5393 { 5394 PIPELINE_MFXMPEG2SLICEGROUPSTATE = 2, //!< No additional details 5395 }; 5396 5397 enum COMMAND_TYPE 5398 { 5399 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5400 }; 5401 5402 enum TAILPRESENTFLAG__TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5403 { 5404 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED0 = 0, //!< no tail insertion into the output bitstream buffer, after the current slice encoded bits 5405 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED1 = 1, //!< tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 5406 }; 5407 5408 enum SLICEDATA_PRESENTFLAG__SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5409 { 5410 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no Slice Data insertion into the output bitstream buffer 5411 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< Slice Data insertion into the output bitstream buffer is present. 5412 }; 5413 5414 enum HEADERPRESENTFLAG__HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5415 { 5416 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no header insertion into the output bitstream buffer, in front of the current slice encoded bits 5417 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 5418 }; 5419 5420 enum BITSTREAMOUTPUTFLAG__COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5421 { 5422 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_ENABLE = 0, //!< enable the writing of the output compressed bitstream 5423 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_DISABLE = 1, //!< disable the writing of the output compressed bitstream 5424 }; 5425 5426 //! \brief SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5427 //! \details 5428 //! This field is only valid for a P or B slice. It must be zero for other 5429 //! slice types. Rules are provided in Section 2.3.3.1.6 5430 enum SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5431 { 5432 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_ENABLE = 0, //!< Enable skip type conversion 5433 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_DISABLE = 1, //!< Disable skip type conversion 5434 }; 5435 5436 //! \brief RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5437 //! \details 5438 //! This field selects between two RC Panic methods. If it is set to 0, in 5439 //! panic mode, the macroblock QP is maxed out, setting to requested QP + 5440 //! QP_max_pos_mod. If it is set to 1, for an intra macroblock, AC CBPs are 5441 //! set to zero (note that DC CBPs are not modified). For inter macroblocks, 5442 //! AC and DC CBPs are forced to zero. 5443 enum RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5444 { 5445 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED0 = 0, //!< QP Panic 5446 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED1 = 1, //!< CBP Panic 5447 }; 5448 5449 //! \brief RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5450 //! \details 5451 //! If this field is set to 1, RC enters panic mode 5452 //! when sum_act > sum_max. RC Panic Type field controls what type 5453 //! of panic 5454 //! behavior is invoked. 5455 enum RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5456 { 5457 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5458 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5459 }; 5460 5461 enum MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5462 { 5463 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED0 = 0, //!< Always Rate Control, whereas RC becomes activeif sum_act > sum_target or sum_act < sum_target 5464 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED1 = 1, //!< Gentle Rate Control, whereas RC becomes activeif sum_act > upper_midpt or sum_act < lower_midpt 5465 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED2 = 2, //!< Loose Rate Control, whereas RC becomes activeif sum_act > sum_max or sum_act < sum_min 5466 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED3 = 3, //!< Reserved 5467 }; 5468 5469 //! \brief MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5470 //! \details 5471 //! To reset the bit allocation accumulation counter to 0 to restart the 5472 //! rate control. 5473 enum MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5474 { 5475 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_DISABLE = 0, //!< Not reset 5476 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_ENABLE = 1, //!< reset 5477 }; 5478 5479 //! \brief MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5480 //! \details 5481 //! To enable the accumulation of bit allocation for rate controlThis field 5482 //! enables hardware Rate Control logic. The rest of the RC control fields 5483 //! are only valid when this field is set to 1. Otherwise, hardware ignores 5484 //! these fields.Note: To reset MB level rate control (QRC), we need to set 5485 //! both bits MbRateCtrlFlag and MbRateCtrlReset to 1 in the new slice 5486 enum MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5487 { 5488 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5489 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5490 }; 5491 5492 //! \name Initializations 5493 5494 //! \brief Explicit member initialization function 5495 MFC_MPEG2_SLICEGROUP_STATE_CMD(); 5496 5497 static const size_t dwSize = 8; 5498 static const size_t byteSize = 32; 5499 }; 5500 5501 //! 5502 //! \brief MFX_VC1_PRED_PIPE_STATE 5503 //! \details 5504 //! This command is used to set the operating states of the MFD Engine 5505 //! beyond the BSD unit. It is used with both VC1 Long and Short 5506 //! format.Driver is responsible to take the intensity compensation enable 5507 //! signal, the LumScale and the LumShift provided from VC1 5508 //! interface, and maintain a history of these values for reference 5509 //! pictures. Together with these three parameters specified for the current 5510 //! picture being decoded, driver will derive and supply the above sets of 5511 //! LumScaleX, LumShiftX and intensity compensation enable (single or 5512 //! double, forward or backward) signals. H/W is responsible to take these 5513 //! state values, and use them to build the lookup table (including the 5514 //! derivation of iScale and iShift) for remapping the reference frame 5515 //! pixels, as well as perfoming the actual pixel remapping 5516 //! calculations/process. 5517 //! 5518 struct MFX_VC1_PRED_PIPE_STATE_CMD 5519 { 5520 union 5521 { 5522 //!< DWORD 0 5523 struct 5524 { 5525 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5526 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5527 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5528 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5529 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5530 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5531 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5532 }; 5533 uint32_t Value; 5534 } DW0; 5535 union 5536 { 5537 //!< DWORD 1 5538 struct 5539 { 5540 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 5541 uint32_t ReferenceFrameBoundaryReplicationMode : __CODEGEN_BITFIELD( 4, 7) ; //!< Reference Frame Boundary Replication Mode 5542 uint32_t VinIntensitycompSingleBwden : __CODEGEN_BITFIELD( 8, 9) ; //!< vin_intensitycomp_Single_BWDen 5543 uint32_t VinIntensitycompSingleFwden : __CODEGEN_BITFIELD(10, 11) ; //!< vin_intensitycomp_Single_FWDen 5544 uint32_t VinIntensitycompDoubleBwden : __CODEGEN_BITFIELD(12, 13) ; //!< vin_intensitycomp_Double_BWDen 5545 uint32_t VinIntensitycompDoubleFwden : __CODEGEN_BITFIELD(14, 15) ; //!< vin_intensitycomp_Double_FWDen 5546 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 5547 }; 5548 uint32_t Value; 5549 } DW1; 5550 union 5551 { 5552 //!< DWORD 2 5553 struct 5554 { 5555 uint32_t Lumscale1SingleFwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - Single - FWD 5556 uint32_t Reserved70 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5557 uint32_t Lumscale2SingleFwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - single - FWD 5558 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5559 uint32_t Lumshift1SingleFwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - single - FWD 5560 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5561 uint32_t Lumshift2SingleFwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- single - FWD 5562 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5563 }; 5564 uint32_t Value; 5565 } DW2; 5566 union 5567 { 5568 //!< DWORD 3 5569 struct 5570 { 5571 uint32_t Lumscale1DoubleFwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - double - FWD 5572 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5573 uint32_t Lumscale2DoubleFwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - double - FWD 5574 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5575 uint32_t Lumshift1DoubleFwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - double -FWD 5576 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5577 uint32_t Lumshift2DoubleFwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- double - FWD 5578 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5579 }; 5580 uint32_t Value; 5581 } DW3; 5582 union 5583 { 5584 //!< DWORD 4 5585 struct 5586 { 5587 uint32_t Lumscale1SingleBwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - Single - BWD 5588 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5589 uint32_t Lumscale2SingleBwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - single - BWD 5590 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5591 uint32_t Lumshift1SingleBwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - single - BWD 5592 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5593 uint32_t Lumshift2SingleBwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- single - BWD 5594 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5595 }; 5596 uint32_t Value; 5597 } DW4; 5598 union 5599 { 5600 //!< DWORD 5 5601 struct 5602 { 5603 uint32_t Lumscale1DoubleBwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - double - BWD 5604 uint32_t Reserved166 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5605 uint32_t Lumscale2DoubleBwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - double - BWD 5606 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5607 uint32_t Lumshift1DoubleBwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - double -BWD 5608 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5609 uint32_t Lumshift2DoubleBwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- double - BWD 5610 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5611 }; 5612 uint32_t Value; 5613 } DW5; 5614 5615 //! \name Local enumerations 5616 5617 enum SUBOPCODE_B 5618 { 5619 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5620 }; 5621 5622 enum SUBOPCODE_A 5623 { 5624 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 5625 }; 5626 5627 enum MEDIA_COMMAND_OPCODE 5628 { 5629 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 5630 }; 5631 5632 enum PIPELINE 5633 { 5634 PIPELINE_MFXVC1PREDPIPESTATE = 2, //!< No additional details 5635 }; 5636 5637 enum COMMAND_TYPE 5638 { 5639 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5640 }; 5641 5642 //! \name Initializations 5643 5644 //! \brief Explicit member initialization function 5645 MFX_VC1_PRED_PIPE_STATE_CMD(); 5646 5647 static const size_t dwSize = 6; 5648 static const size_t byteSize = 24; 5649 }; 5650 5651 //! 5652 //! \brief MFD_VC1_LONG_PIC_STATE 5653 //! \details 5654 //! MFX_VC1_LONG PIC_STATE command encapsulates the decoding parameters that 5655 //! are read or derived from bitstream syntax elements above (inclusive) 5656 //! picture header layer. These parameters are static for a picture and when 5657 //! slice structure is present, these parameters are not changed from slice 5658 //! to slice of the same picture. Hence, this command is only issued at the 5659 //! beginning of processing a new picture and prior to the VC1_*_OBJECT 5660 //! command. The values set for these state variables are retained 5661 //! internally across slices.Only the parameters needed by hardware (BSD 5662 //! unit) to decode bit sequence for the macroblocks in a picture layer or a 5663 //! slice layer are presented in this command. Other parameters such as the 5664 //! ones used for inverse transform or motion compensation are provided in 5665 //! MFX_VC1_PRED_PIPE_STATE command.This Long interface format is intel 5666 //! proprietary interface. Driver will need to perform addition operations 5667 //! to generate all the fields in this command. 5668 //! 5669 struct MFD_VC1_LONG_PIC_STATE_CMD 5670 { 5671 union 5672 { 5673 //!< DWORD 0 5674 struct 5675 { 5676 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5677 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5678 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5679 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5680 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5681 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5682 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5683 }; 5684 uint32_t Value; 5685 } DW0; 5686 union 5687 { 5688 //!< DWORD 1 5689 struct 5690 { 5691 uint32_t Picturewidthinmbsminus1PictureWidthMinus1InMacroblocks : __CODEGEN_BITFIELD( 0, 7) ; //!< PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS 5692 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 5693 uint32_t Pictureheightinmbsminus1PictureHeightMinus1InMacroblocks : __CODEGEN_BITFIELD(16, 23) ; //!< PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_ 5694 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 5695 }; 5696 uint32_t Value; 5697 } DW1; 5698 union 5699 { 5700 //!< DWORD 2 5701 struct 5702 { 5703 uint32_t Vc1Profile : __CODEGEN_BITFIELD( 0, 0) ; //!< VC1_PROFILE 5704 uint32_t Reserved65 : __CODEGEN_BITFIELD( 1, 2) ; //!< Reserved 5705 uint32_t Secondfield : __CODEGEN_BITFIELD( 3, 3) ; //!< Secondfield 5706 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< OVERLAP_SMOOTHING_ENABLE_FLAG 5707 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< LOOPFILTER_ENABLE_FLAG 5708 uint32_t RangereductionEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RANGEREDUCTION_ENABLE 5709 uint32_t Rangereductionscale : __CODEGEN_BITFIELD( 7, 7) ; //!< RANGEREDUCTIONSCALE 5710 uint32_t MotionVectorMode : __CODEGEN_BITFIELD( 8, 11) ; //!< MOTION_VECTOR_MODE 5711 uint32_t Syncmarker : __CODEGEN_BITFIELD(12, 12) ; //!< SYNCMARKER 5712 uint32_t InterpolationRounderContro : __CODEGEN_BITFIELD(13, 13) ; //!< Interpolation Rounder Contro 5713 uint32_t Implicitquantizer : __CODEGEN_BITFIELD(14, 14) ; //!< ImplicitQuantizer 5714 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15) ; //!< DmvSurfaceValid 5715 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 5716 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31) ; //!< Bitplane Buffer Pitch Minus 1 5717 }; 5718 uint32_t Value; 5719 } DW2; 5720 union 5721 { 5722 //!< DWORD 3 5723 struct 5724 { 5725 uint32_t Bscalefactor : __CODEGEN_BITFIELD( 0, 7) ; //!< BScaleFactor 5726 uint32_t PquantPictureQuantizationValue : __CODEGEN_BITFIELD( 8, 12) ; //!< PQuant (Picture Quantization Value) 5727 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 5728 uint32_t AltpquantAlternativePictureQuantizationValue : __CODEGEN_BITFIELD(16, 20) ; //!< AltPQuant (Alternative Picture Quantization Value) 5729 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 5730 uint32_t FcmFrameCodingMode : __CODEGEN_BITFIELD(24, 25) ; //!< FCM_FRAME_CODING_MODE 5731 uint32_t PictypePictureType : __CODEGEN_BITFIELD(26, 28) ; //!< PicType (Picture Type) 5732 uint32_t Condover : __CODEGEN_BITFIELD(29, 30) ; //!< CONDOVER 5733 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 5734 }; 5735 uint32_t Value; 5736 } DW3; 5737 union 5738 { 5739 //!< DWORD 4 5740 struct 5741 { 5742 uint32_t Pquantuniform : __CODEGEN_BITFIELD( 0, 0) ; //!< PQUANTUNIFORM 5743 uint32_t Halfqp : __CODEGEN_BITFIELD( 1, 1) ; //!< HalfQP 5744 uint32_t AltpquantconfigAlternativePictureQuantizationConfiguration : __CODEGEN_BITFIELD( 2, 3) ; //!< ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5745 uint32_t AltpquantedgemaskAlternativePictureQuantizationEdgeMask : __CODEGEN_BITFIELD( 4, 7) ; //!< AltPQuantEdgeMask (Alternative Picture Quantization Edge Mask) 5746 uint32_t ExtendedmvrangeExtendedMotionVectorRangeFlag : __CODEGEN_BITFIELD( 8, 9) ; //!< EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5747 uint32_t ExtendeddmvrangeExtendedDifferentialMotionVectorRangeFlag : __CODEGEN_BITFIELD(10, 11) ; //!< EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5748 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5749 uint32_t FwdrefdistReferenceDistance : __CODEGEN_BITFIELD(16, 19) ; //!< FwdRefDist (Reference Distance) 5750 uint32_t BwdrefdistReferenceDistance : __CODEGEN_BITFIELD(20, 23) ; //!< BwdRefDist (Reference Distance) 5751 uint32_t NumrefNumberOfReferences : __CODEGEN_BITFIELD(24, 24) ; //!< NUMREF_NUMBER_OF_REFERENCES 5752 uint32_t ReffieldpicpolarityReferenceFieldPicturePolarity : __CODEGEN_BITFIELD(25, 25) ; //!< REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5753 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD(26, 26) ; //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5754 uint32_t FourmvswitchFourMotionVectorSwitch : __CODEGEN_BITFIELD(27, 27) ; //!< FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5755 uint32_t UnifiedmvmodeUnifiedMotionVectorMode : __CODEGEN_BITFIELD(28, 29) ; //!< UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5756 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5757 }; 5758 uint32_t Value; 5759 } DW4; 5760 union 5761 { 5762 //!< DWORD 5 5763 struct 5764 { 5765 uint32_t CbptabCodedBlockPatternTable : __CODEGEN_BITFIELD( 0, 2) ; //!< CbpTab (Coded Block Pattern Table) 5766 uint32_t TransdctabIntraTransformDcTable : __CODEGEN_BITFIELD( 3, 3) ; //!< TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5767 uint32_t TransacuvPictureLevelTransformChromaAcCodingSetIndexTransactable : __CODEGEN_BITFIELD( 4, 5) ; //!< TransAcUV (Picture-level Transform Chroma AC Coding Set Index, TRANSACTABLE) 5768 uint32_t TransacyPictureLevelTransformLumaAcCodingSetIndexTransactable2 : __CODEGEN_BITFIELD( 6, 7) ; //!< TransAcY (Picture-level Transform Luma AC Coding Set Index, TRANSACTABLE2 5769 uint32_t MbmodetabMacroblockModeTable : __CODEGEN_BITFIELD( 8, 10) ; //!< MbModeTab (Macroblock Mode Table) 5770 uint32_t TranstypembflagMacroblockTransformTypeFlag : __CODEGEN_BITFIELD(11, 11) ; //!< TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5771 uint32_t TranstypePictureLevelTransformType : __CODEGEN_BITFIELD(12, 13) ; //!< TransType (Picture-level Transform Type) 5772 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5773 uint32_t Twomvbptab2MvBlockPatternTable : __CODEGEN_BITFIELD(16, 17) ; //!< TwoMvBpTab (2MV Block Pattern Table) 5774 uint32_t Fourmvbptab4MvBlockPatternTable : __CODEGEN_BITFIELD(18, 19) ; //!< FourMvBpTab (4-MV Block Pattern Table) 5775 uint32_t MvtabMotionVectorTable : __CODEGEN_BITFIELD(20, 22) ; //!< MvTab (Motion Vector Table) 5776 uint32_t Reserved183 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 5777 uint32_t Fieldtxraw : __CODEGEN_BITFIELD(24, 24) ; //!< FIELDTXRAW 5778 uint32_t Acpredraw : __CODEGEN_BITFIELD(25, 25) ; //!< ACPREDRAW 5779 uint32_t Overflagsraw : __CODEGEN_BITFIELD(26, 26) ; //!< OVERFLAGSRAW 5780 uint32_t Directmbraw : __CODEGEN_BITFIELD(27, 27) ; //!< DIRECTMBRAW 5781 uint32_t Skipmbraw : __CODEGEN_BITFIELD(28, 28) ; //!< SKIPMBRAW 5782 uint32_t Mvtypembraw : __CODEGEN_BITFIELD(29, 29) ; //!< MVTYPEMBRAW 5783 uint32_t Forwardmbraw : __CODEGEN_BITFIELD(30, 30) ; //!< FORWARDMBRAW 5784 uint32_t BitplanepresentflagBitplaneBufferPresentFlag : __CODEGEN_BITFIELD(31, 31) ; //!< BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5785 }; 5786 uint32_t Value; 5787 } DW5; 5788 5789 //! \name Local enumerations 5790 5791 enum SUBOPCODE_B 5792 { 5793 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5794 }; 5795 5796 enum SUBOPCODE_A 5797 { 5798 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5799 }; 5800 5801 enum MEDIA_COMMAND_OPCODE 5802 { 5803 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 5804 }; 5805 5806 enum PIPELINE 5807 { 5808 PIPELINE_MFDVC1LONGPICSTATE = 2, //!< No additional details 5809 }; 5810 5811 enum COMMAND_TYPE 5812 { 5813 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5814 }; 5815 5816 //! \brief PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS 5817 //! \details 5818 //! This field indicates the width of the picture in unit of macroblocks. 5819 //! For example, for a 1920x1080 frame picture, PictureWidthInMBs equals 120 5820 //! (1920 divided by 16).This field is used in VLD and IT modes 5821 enum PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS 5822 { 5823 PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS_VALUE255 = 255, //!< No additional details 5824 }; 5825 5826 //! \brief PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_ 5827 //! \details 5828 //! This field indicates the height of the picture in unit of macroblocks. 5829 //! For example, for a 1920x1080 frame picture, PictureHeightInMBs equals 68 5830 //! (1080 divided by 16, and rounded up, i.e. effectively specified as 1088 5831 //! instead).This field is used in VLD and IT modes. 5832 enum PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_ 5833 { 5834 PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_VALUE255 = 255, //!< No additional details 5835 }; 5836 5837 //! \brief VC1_PROFILE 5838 //! \details 5839 //! specifies the bitstream profile.This field is used in both VLD and IT 5840 //! modes. 5841 enum VC1_PROFILE 5842 { 5843 VC1_PROFILE_DISABLE = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 5844 VC1_PROFILE_ENABLE = 1, //!< current picture is in Advanced Profile 5845 }; 5846 5847 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 5848 //! \details 5849 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 5850 //! if Overlap smoothing is ON at the picture levelThis field is used in 5851 //! both VLD and IT modes. 5852 enum OVERLAP_SMOOTHING_ENABLE_FLAG 5853 { 5854 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 5855 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 5856 }; 5857 5858 //! \brief LOOPFILTER_ENABLE_FLAG 5859 //! \details 5860 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 5861 //! indicates if In-loop Deblocking is ON according to picture level 5862 //! bitstream syntax control. This bit affects BSD unit and also the loop 5863 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 5864 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 5865 //! in-loop deblocking operation follows the VC1 standard - deblocking 5866 //! doesn't cross slice boundary.When this bit is set to 0, but 5867 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 5868 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 5869 //! this case, deblocking operation does cross slice boundary.This field is 5870 //! used in VLD mode only, not in IT mode. 5871 enum LOOPFILTER_ENABLE_FLAG 5872 { 5873 LOOPFILTER_ENABLE_FLAG_DISABLE = 0, //!< Disables loop filter 5874 LOOPFILTER_ENABLE_FLAG_ENABLE = 1, //!< Enables loop filter 5875 }; 5876 5877 //! \brief RANGEREDUCTION_ENABLE 5878 //! \details 5879 //! This field specifies whether on-the-fly pixel value range reduction 5880 //! should be performed for the preceding (or forward) reference picture. 5881 //! Along with RangeReductionScale to specify whether scale up or down 5882 //! should be performed. It is not the same value as RANGEREDFRM Syntax 5883 //! Element (PictureParameters bPicDeblocked bit 5) in the Picture 5884 //! Header. 5885 enum RANGEREDUCTION_ENABLE 5886 { 5887 RANGEREDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 5888 RANGEREDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 5889 }; 5890 5891 //! \brief RANGEREDUCTIONSCALE 5892 //! \details 5893 //! This field specifies whether the reference picture pixel values should 5894 //! be scaled up or scaled down on-the-fly, if RangeReduction is Enabled. 5895 enum RANGEREDUCTIONSCALE 5896 { 5897 RANGEREDUCTIONSCALE_UNNAMED0 = 0, //!< Scale down reference picture by factor of 2 5898 RANGEREDUCTIONSCALE_UNNAMED1 = 1, //!< Scale up reference picture by factor of 2 5899 }; 5900 5901 //! \brief MOTION_VECTOR_MODE 5902 //! \details 5903 //! This field indicates one of the following motion compensation 5904 //! interpolation modes for P and B pictures. The MC interpolation modes 5905 //! apply to prediction values of luminance blocks and are always in 5906 //! quarter-sample. For chrominance blocks, it always performs bilinear 5907 //! interpolation with either half-pel or quarter-pel precision.Before the 5908 //! polarity of Chroma Half-pel or Q-pel is reversed from Spec, now I 5909 //! have fixed it to match with VC1 Spec. 5910 enum MOTION_VECTOR_MODE 5911 { 5912 MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Chroma Quarter -pel + Luma bicubic. (can only be 1MV) 5913 MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< Chroma Half-pel + Luma bicubic. (can be 1MV or 4MV) 5914 MOTION_VECTOR_MODE_UNNAMED8 = 8, //!< Chroma Quarter -pel + Luma bilinear. (can only be 1MV) 5915 MOTION_VECTOR_MODE_UNNAMED9 = 9, //!< Chroma Half-pel + Luma bilinear 5916 }; 5917 5918 //! \brief SYNCMARKER 5919 //! \details 5920 //! Indicates whether sync markers are enabled/disabled. If enable, sync 5921 //! markers "may be" present in the current video sequence being decoded. It 5922 //! is a sequence level syntax element and is valid only for Simple and Main 5923 //! Profiles. 5924 enum SYNCMARKER 5925 { 5926 SYNCMARKER_NOTPRESENT = 0, //!< Sync Marker is not present in the bitstream 5927 SYNCMARKER_MAYBEPRESENT = 1, //!< Sync Marker maybe present in the bitstream 5928 }; 5929 5930 //! \brief FCM_FRAME_CODING_MODE 5931 //! \details 5932 //! This is the same as the variable FCM defined in VC1.This field must be 5933 //! set to 0 for Simple and Main ProfilesThis field is unique to intel VC1 5934 //! VLD Long format, and is used in IT mode as well. For VC1 IT mode, 5935 //! driver needs to convert the interface to intel HW VLD Long Format 5936 //! interface. 5937 enum FCM_FRAME_CODING_MODE 5938 { 5939 FCM_FRAME_CODING_MODE_DISABLE = 0, //!< Progressive Frame Picture 5940 FCM_FRAME_CODING_MODE_ENABLE = 1, //!< Interlaced Frame Picture 5941 FCM_FRAME_CODING_MODE_UNNAMED2 = 2, //!< Field Picture with Top Field First 5942 FCM_FRAME_CODING_MODE_UNNAMED3 = 3, //!< Field Picture with Bottom Field First 5943 }; 5944 5945 //! \brief CONDOVER 5946 //! \details 5947 //! This field is the decoded syntax element CONDOVER in a bitstream of 5948 //! advanced profile. It controls the overlap smoothing filter operation for 5949 //! an I frame or an BI frame when the picture level qualization step size 5950 //! PQUANT is 8 or lower.This field is used in intel VC1 VLD mode only, not 5951 //! in VC1 and IT modes. 5952 enum CONDOVER 5953 { 5954 CONDOVER_UNNAMED0 = 0, //!< No overlap smoothing 5955 CONDOVER_UNNAMED1 = 1, //!< Reserved 5956 CONDOVER_UNNAMED2 = 2, //!< Always perform overlap smoothing filter 5957 CONDOVER_UNNAMED3 = 3, //!< Overlap smoothing on a per macroblock basis based on OVERFLAGS 5958 }; 5959 5960 //! \brief PQUANTUNIFORM 5961 //! \details 5962 //! Indicating if uniform quantization applies to the 5963 //! picture. It is used for inverse quantization of the AC 5964 //! coefficients.QUANTIZER 5965 //! 001123PQUANTIZER - 5966 //! -01--PQINDEX>=9<=8----PQuantUniform010201ImplicitQuantizer = 5967 //! 0, and 5968 //! PQuantUniform = 0 is used to represent 2 cases : 1) QUANTIZER=01 5969 //! and 5970 //! PQUANTIZER=0; and 2) QUANTIZER = 10b.ImplicitQuantizer = 0, and 5971 //! PQuantUniform = 5972 //! 1 is used to represent 2 cases : 1) QUANTIZER=01 and PQUANTIZER=1; 5973 //! and 2) 5974 //! QUANTIZER = 11bThis field is unique to intel VC1 VLD Long format 5975 //! mode, and is 5976 //! not used in IT and VC1 modes. 5977 enum PQUANTUNIFORM 5978 { 5979 PQUANTUNIFORM_UNNAMED0 = 0, //!< Non-uniform 5980 PQUANTUNIFORM_UNNAMED1 = 1, //!< Uniform 5981 }; 5982 5983 //! \brief ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5984 //! \details 5985 //! This field specifies the way AltPQuant is used in the picture. It 5986 //! determines how to compute the macroblock quantizer step size, MQUANT. It 5987 //! is derived based on the following variables DQUANT, DQUANTFRM, 5988 //! DQPROFILE, DQSBEDGE, DQDBEDGE, and DQBILEVEL defined in the VC1 5989 //! standard, as shown in Error! Reference source not found..This field is 5990 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 5991 //! VC1 modes. 5992 enum ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5993 { 5994 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED0 = 0, //!< AltPQuant not used 5995 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED1 = 1, //!< AltPQuant is used and applied to edge macroblocks only 5996 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED2 = 2, //!< MQUANT is encoded in macroblock layer 5997 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED3 = 3, //!< AltPQuant and PQuant are selected on macroblock basis 5998 }; 5999 6000 //! \brief EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 6001 //! \details 6002 //! This field specifies the motion vector range in quarter-pel or half-pel 6003 //! modes. It is equivalent to the variable MVRANGE in the VC1 standard. 6004 //! This field is unique to intel VC1 VLD Long format mode, and is not used 6005 //! in IT and VC1 modes 6006 enum EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 6007 { 6008 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< [-256, 255] x [-128, 127] 6009 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< 512, 511] x [-256, 255] 6010 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< [-2048, 2047] x [-1024, 1023] 6011 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< [-4096, 4095] x [-2048, 2047] 6012 }; 6013 6014 //! \brief EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 6015 //! \details 6016 //! This field specifies the differential motion vector range in interlaced 6017 //! pictures. It is equivalent to the variable DMVRANGE in the VC1 standard. 6018 //! This field is unique to intel VC1 VLD Long format mode, and is not used 6019 //! in IT and VC1 modes. 6020 enum EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 6021 { 6022 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< No extended range 6023 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< Extended horizontally 6024 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< Extended vertically 6025 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< Extended in both directions 6026 }; 6027 6028 //! \brief NUMREF_NUMBER_OF_REFERENCES 6029 //! \details 6030 //! This field indicates how many reference fields are referenced by the 6031 //! current (field) picture. It is identical to the variable NUMREF in the 6032 //! VC1 standard. This field is only valid for field P picture (FCM = 10 | 6033 //! 11).This field is unique to intel VC1 VLD Long format mode, and is not 6034 //! used in IT and VC1 modes. 6035 enum NUMREF_NUMBER_OF_REFERENCES 6036 { 6037 NUMREF_NUMBER_OF_REFERENCES_UNNAMED0 = 0, //!< One field referenced 6038 NUMREF_NUMBER_OF_REFERENCES_UNNAMED1 = 1, //!< Two fields referenced 6039 }; 6040 6041 //! \brief REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 6042 //! \details 6043 //! This field specifies the polarity of the one reference field picture 6044 //! used for a field P picture. It is derived from the variable REFFIELD 6045 //! defined in VC1 standard and is only valid when one field is referenced 6046 //! (NUMREF = 0) for a field P picture.When NUMREF = 0 and REFFIELD = 0, 6047 //! this field is the polarity of the reference I/P field that is temporally 6048 //! closest; When NUMREF = 0 and REFFIELD = 1, this field is the polarity of 6049 //! the reference I/P field that is the second most temporally closest. The 6050 //! distance is measured based on display order but ignoring the repeated 6051 //! field if present (due to RFF = 1).This field is unique to intel VC1 VLD 6052 //! Long format mode, and is not used in IT and VC1 modes. 6053 enum REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 6054 { 6055 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED0 = 0, //!< Top (even) field 6056 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED1 = 1, //!< Bottom (odd) field 6057 }; 6058 6059 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6060 //! \details 6061 //! This field specifies whether the motion vectors for 6062 //! UV is rounded to half or full pel position. It is identical to the 6063 //! variable 6064 //! FASTUVMC in VC1 standard.This field is used in both VLD and IT 6065 //! modes.It is 6066 //! derived from FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in 6067 //! both VLD and 6068 //! IT modes, and should have the same value as Motion Vector Mode 6069 //! LSBit. 6070 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6071 { 6072 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 6073 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 6074 }; 6075 6076 //! \brief FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 6077 //! \details 6078 //! This field indicates if 4-MV is present for an interlaced frame P 6079 //! picture. It is identical to the variable 4MVSWITCH (4 Motion Vector 6080 //! Switch) in VC1 standard.This field is used in intel VC1 VLD Long Format 6081 //! mode only, it is not used in VC1 VLD and IT modes. 6082 enum FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 6083 { 6084 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_DISABLE = 0, //!< only 1-MV 6085 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_ENABLE = 1, //!< 1, 2, or 4 motion vector 6086 }; 6087 6088 //! \brief UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 6089 //! \details 6090 //! This field is a combination of the variables MVMODE and MVMODE2 in the 6091 //! VC1 standard, for parsing Luma MVD from the bitstream. This field is 6092 //! used to signal 1MV vs 4MVallowed (Mixed Mode). This field is also used 6093 //! to signal Q-pel or Half-pel MVD read from the bitstream. The bicubic or 6094 //! bilinear Luma MC interpolation mode is duplicate information from Motion 6095 //! Vector Mode field, and is ignored here.This field is used in intel VC1 6096 //! VLD Long Format mode only, it is not used in VC1 VLD and IT modes. 6097 enum UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 6098 { 6099 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Mixed MV, Q-pel bicubic 6100 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< 1-MV, Q-pel bicubic 6101 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED2 = 2, //!< 1-MV half-pel bicubic 6102 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED3 = 3, //!< 1-MV half-pel bilinear 6103 }; 6104 6105 //! \brief TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 6106 //! \details 6107 //! This field specifies whether the low motion tables or the high motion 6108 //! tables are used to decode the Transform DC coefficients in intra-coded 6109 //! blocks. This field is identical to the variable TRANSDCTAB in the VC1 6110 //! standard, section 8.1.1.2.This field is valid for all picture types.This 6111 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6112 //! and VC1 modes. 6113 enum TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 6114 { 6115 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED0 = 0, //!< The high motion tables 6116 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED1 = 1, //!< The low motion tables 6117 }; 6118 6119 //! \brief TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 6120 //! \details 6121 //! This field indicates whether Transform Type is fixed at picture level or 6122 //! variable at macroblock level. It is identical to the variable TTMBF in 6123 //! the VC1 standard, section 7.1.1.40.This field is set to 1 when 6124 //! VSTRANSFORM is 0 in the entry point layer.This field is unique to intel 6125 //! VC1 VLD Long format mode, and is not used in IT and VC1 modes. 6126 enum TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 6127 { 6128 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED0 = 0, //!< variable transform type in macroblock layer 6129 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED1 = 1, //!< use picture level transform type TransType 6130 }; 6131 6132 //! \brief FIELDTXRAW 6133 //! \details 6134 //! This field indicates whether the FIELDTX field is coded in raw or 6135 //! non-raw mode.This field is only valid when PictureType is I or BI.This 6136 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6137 //! and VC1 modes. 6138 enum FIELDTXRAW 6139 { 6140 FIELDTXRAW_DISABLE = 0, //!< Non-Raw Mode 6141 FIELDTXRAW_ENABLE = 1, //!< Raw Mode 6142 }; 6143 6144 //! \brief ACPREDRAW 6145 //! \details 6146 //! This field indicates whether the ACPRED field is coded in raw or non-raw 6147 //! mode.This field is only valid when PictureType is I or BI.This field is 6148 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 6149 //! VC1 modes. 6150 enum ACPREDRAW 6151 { 6152 ACPREDRAW_DISABLE = 0, //!< Non-Raw Mode 6153 ACPREDRAW_ENABLE = 1, //!< Raw Mode 6154 }; 6155 6156 //! \brief OVERFLAGSRAW 6157 //! \details 6158 //! This field indicates whether the OVERFLAGS field is coded in raw or 6159 //! non-raw mode.This field is only valid when PictureType is I or BI.This 6160 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6161 //! and VC1 modes. 6162 enum OVERFLAGSRAW 6163 { 6164 OVERFLAGSRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6165 OVERFLAGSRAW_UNNAMED1 = 1, //!< Raw Mode 6166 }; 6167 6168 //! \brief DIRECTMBRAW 6169 //! \details 6170 //! This field indicates whether the DIRECTMB field is coded in raw or 6171 //! non-raw mode.This field is only valid when PictureType is P or B.This 6172 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6173 //! and VC1 modes. 6174 enum DIRECTMBRAW 6175 { 6176 DIRECTMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6177 DIRECTMBRAW_UNNAMED1 = 1, //!< Raw Mode 6178 }; 6179 6180 //! \brief SKIPMBRAW 6181 //! \details 6182 //! This field indicates whether the SKIPMB field is coded in raw or non-raw 6183 //! mode.This field is only valid when PictureType is P or B.0 = non-raw 6184 //! mode1 = raw modeThis field is unique to intel VC1 VLD Long format mode, 6185 //! and is not used in IT and VC1 modes. 6186 enum SKIPMBRAW 6187 { 6188 SKIPMBRAW_DISABLE = 0, //!< Non-Raw Mode 6189 SKIPMBRAW_ENABLE = 1, //!< Raw Mode 6190 }; 6191 6192 //! \brief MVTYPEMBRAW 6193 //! \details 6194 //! This field indicates whether the MVTYPREMB field is coded in raw or 6195 //! non-raw mode.This field is only valid when PictureType is P.This field 6196 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 6197 //! VC1 modes. 6198 enum MVTYPEMBRAW 6199 { 6200 MVTYPEMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6201 MVTYPEMBRAW_UNNAMED1 = 1, //!< Raw Mode 6202 }; 6203 6204 //! \brief FORWARDMBRAW 6205 //! \details 6206 //! This field indicates whether the FORWARDMB field is coded in raw or 6207 //! non-raw mode.This field is only valid when PictureType is B.This field 6208 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 6209 //! VC1 modes. 6210 enum FORWARDMBRAW 6211 { 6212 FORWARDMBRAW_UNNAMED0 = 0, //!< non-raw mode 6213 FORWARDMBRAW_UNNAMED1 = 1, //!< raw mode 6214 }; 6215 6216 //! \brief BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 6217 //! \details 6218 //! This field indicates whether the bitplane buffer is present for the 6219 //! picture. If set, at least one of the fields listed in bits 22:16 is 6220 //! coded in non-raw mode, and Bitplane Buffer Base Address field in the 6221 //! VC1_BSD_BUF_BASE_STATE command points to the bitplane buffer. Otherwise, 6222 //! all the fields that are applicable for the current picture in bits 22:16 6223 //! must be coded in raw mode.This field is unique to intel VC1 VLD Long 6224 //! format mode, and is not used in IT and VC1 modes. 6225 enum BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 6226 { 6227 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED0 = 0, //!< bitplane buffer is not present 6228 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED1 = 1, //!< bitplane buffer is present 6229 }; 6230 6231 //! \name Initializations 6232 6233 //! \brief Explicit member initialization function 6234 MFD_VC1_LONG_PIC_STATE_CMD(); 6235 6236 static const size_t dwSize = 6; 6237 static const size_t byteSize = 24; 6238 }; 6239 6240 //! 6241 //! \brief MFD_VC1_SHORT_PIC_STATE 6242 //! \details 6243 //! 6244 //! 6245 struct MFD_VC1_SHORT_PIC_STATE_CMD 6246 { 6247 union 6248 { 6249 //!< DWORD 0 6250 struct 6251 { 6252 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6253 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6254 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6255 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6256 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6257 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6258 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6259 }; 6260 uint32_t Value; 6261 } DW0; 6262 union 6263 { 6264 //!< DWORD 1 6265 struct 6266 { 6267 uint32_t PictureWidth : __CODEGEN_BITFIELD( 0, 7) ; //!< Picture Width 6268 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 6269 uint32_t PictureHeight : __CODEGEN_BITFIELD(16, 23) ; //!< Picture Height 6270 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6271 }; 6272 uint32_t Value; 6273 } DW1; 6274 union 6275 { 6276 //!< DWORD 2 6277 struct 6278 { 6279 uint32_t PictureStructure : __CODEGEN_BITFIELD( 0, 1) ; //!< PICTURE_STRUCTURE 6280 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 6281 uint32_t Secondfield : __CODEGEN_BITFIELD( 3, 3) ; //!< SecondField 6282 uint32_t IntraPictureFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< INTRA_PICTURE_FLAG 6283 uint32_t BackwardPredictionPresentFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< Backward Prediction Present Flag 6284 uint32_t Reserved70 : __CODEGEN_BITFIELD( 6, 10) ; //!< Reserved 6285 uint32_t Vc1Profile : __CODEGEN_BITFIELD(11, 11) ; //!< VC1_PROFILE 6286 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 14) ; //!< Reserved 6287 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15) ; //!< DmvSurfaceValid 6288 uint32_t MotionVectorMode : __CODEGEN_BITFIELD(16, 19) ; //!< Motion Vector Mode 6289 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 6290 uint32_t InterpolationRounderControl : __CODEGEN_BITFIELD(23, 23) ; //!< Interpolation Rounder Control 6291 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31) ; //!< Bitplane Buffer Pitch Minus 1 6292 }; 6293 uint32_t Value; 6294 } DW2; 6295 union 6296 { 6297 //!< DWORD 3 6298 struct 6299 { 6300 uint32_t VstransformFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSTRANSFORM_FLAG 6301 uint32_t Dquant : __CODEGEN_BITFIELD( 1, 2) ; //!< DQUANT 6302 uint32_t ExtendedMvPresentFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< EXTENDED_MV_PRESENT_FLAG 6303 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6304 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< LOOPFILTER_ENABLE_FLAG 6305 uint32_t RefdistFlag : __CODEGEN_BITFIELD( 6, 6) ; //!< REFDIST_FLAG 6306 uint32_t PanscanPresentFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< PANSCAN_PRESENT_FLAG 6307 uint32_t Maxbframes : __CODEGEN_BITFIELD( 8, 10) ; //!< MAXBFRAMES 6308 uint32_t RangeredPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(11, 11) ; //!< RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6309 uint32_t SyncmarkerPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(12, 12) ; //!< SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6310 uint32_t MultiresPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(13, 13) ; //!< MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6311 uint32_t Quantizer : __CODEGEN_BITFIELD(14, 15) ; //!< QUANTIZER 6312 uint32_t PPicRefDistance : __CODEGEN_BITFIELD(16, 20) ; //!< P_PIC_REF_DISTANCE 6313 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 6314 uint32_t ProgressivePicType : __CODEGEN_BITFIELD(22, 23) ; //!< PROGRESSIVE_PIC_TYPE 6315 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 27) ; //!< Reserved 6316 uint32_t RangeReductionEnable : __CODEGEN_BITFIELD(28, 28) ; //!< RANGE_REDUCTION_ENABLE 6317 uint32_t RangeReductionScale : __CODEGEN_BITFIELD(29, 29) ; //!< RANGE_REDUCTION_SCALE 6318 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD(30, 30) ; //!< OVERLAP_SMOOTHING_ENABLE_FLAG 6319 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 6320 }; 6321 uint32_t Value; 6322 } DW3; 6323 union 6324 { 6325 //!< DWORD 4 6326 struct 6327 { 6328 uint32_t ExtendedDmvPresentFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< EXTENDED_DMV_PRESENT_FLAG 6329 uint32_t Psf : __CODEGEN_BITFIELD( 1, 1) ; //!< PSF 6330 uint32_t RefpicFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< REFPIC_FLAG 6331 uint32_t Finterflag : __CODEGEN_BITFIELD( 3, 3) ; //!< FINTERFLAG 6332 uint32_t Tfcntrflag : __CODEGEN_BITFIELD( 4, 4) ; //!< TFCNTRFLAG 6333 uint32_t Interlace : __CODEGEN_BITFIELD( 5, 5) ; //!< INTERLACE 6334 uint32_t Pulldown : __CODEGEN_BITFIELD( 6, 6) ; //!< PULLDOWN 6335 uint32_t PostprocFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< POSTPROC Flag 6336 uint32_t _4MvAllowedFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< _4MV Allowed Flag 6337 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 23) ; //!< Reserved 6338 uint32_t BfractionEnumeration : __CODEGEN_BITFIELD(24, 28) ; //!< BFraction Enumeration 6339 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 6340 }; 6341 uint32_t Value; 6342 } DW4; 6343 6344 //! \name Local enumerations 6345 6346 enum SUBOPCODE_B 6347 { 6348 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 6349 }; 6350 6351 enum SUBOPCODE_A 6352 { 6353 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6354 }; 6355 6356 enum MEDIA_COMMAND_OPCODE 6357 { 6358 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6359 }; 6360 6361 enum PIPELINE 6362 { 6363 PIPELINE_MFDVC1SHORTPICSTATE = 2, //!< No additional details 6364 }; 6365 6366 enum COMMAND_TYPE 6367 { 6368 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6369 }; 6370 6371 //! \brief PICTURE_STRUCTURE 6372 //! \details 6373 //! This field is used in both VC1 VLD mode and IT mode. It is the 6374 //! same parameter as bPicStructure in VC1 spec. 6375 //! The Picture Structure and Progressive Pic Type are used to derive 6376 //! the picture structure as specified in FCM, in VC1 VLD and IT mode. 6377 enum PICTURE_STRUCTURE 6378 { 6379 PICTURE_STRUCTURE_UNNAMED0 = 0, //!< illegal 6380 PICTURE_STRUCTURE_UNNAMED1 = 1, //!< top field (bit 0) 6381 PICTURE_STRUCTURE_UNNAMED2 = 2, //!< bottom field (bit 1) 6382 PICTURE_STRUCTURE_UNNAMED3 = 3, //!< frame (both fields are present) 6383 }; 6384 6385 //! \brief INTRA_PICTURE_FLAG 6386 //! \details 6387 //! This field is used in both VC1 VLD mode and IT mode. It is the 6388 //! same parameter as bPicIntra in VC1 spec. 6389 //! The Intra Picture Flag, Backward Prediction Present Flag and 6390 //! RefPicFlag are used to derive the picture type, as specified in PTYPE 6391 //! for a frame, and in FPTYPE for a field, in VC1 VLD and IT mode. 6392 enum INTRA_PICTURE_FLAG 6393 { 6394 INTRA_PICTURE_FLAG_UNNAMED0 = 0, //!< entire picture can have a mixture of intra and inter MB type or just inter MB type. 6395 INTRA_PICTURE_FLAG_UNNAMED1 = 1, //!< entire picture is coded in intra MB type 6396 }; 6397 6398 //! \brief VC1_PROFILE 6399 //! \details 6400 //! specifies the bitstream profile. 6401 //! Note: This is required because 128 is added for intra blocks post 6402 //! inverse transform in advanced profile and also to find out if Motion 6403 //! vectors are adjusted or not. 6404 //! This field is used in both VLD and IT modes. 6405 enum VC1_PROFILE 6406 { 6407 VC1_PROFILE_UNNAMED0 = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 6408 VC1_PROFILE_UNNAMED1 = 1, //!< current picture is in Advanced Profile 6409 }; 6410 6411 enum VSTRANSFORM_FLAG 6412 { 6413 VSTRANSFORM_FLAG_DISABLE = 0, //!< variable-sized transform coding is not enabled 6414 VSTRANSFORM_FLAG_ENABLE = 1, //!< variable-sized transform coding is enabled 6415 }; 6416 6417 //! \brief DQUANT 6418 //! \details 6419 //! Use for Picture Header Parsing of VOPDUANT elements 6420 enum DQUANT 6421 { 6422 DQUANT_UNNAMED0 = 0, //!< no VOPDQUANT elements; Quantizer cannot vary in frame, same quantization step size PQUANT is used for all MBs in the frame 6423 DQUANT_UNNAMED1 = 1, //!< refer to VC1 Spec. for all the MB position dependent quantizer selection 6424 DQUANT_UNNAMED2 = 2, //!< The macroblocks located on the picture edge boundary shall be quantized with ALTPQUANT while the rest of the macroblocks shall be quantized with PQUANT. 6425 }; 6426 6427 //! \brief EXTENDED_MV_PRESENT_FLAG 6428 //! \details 6429 //! BitFieldDesc 6430 enum EXTENDED_MV_PRESENT_FLAG 6431 { 6432 EXTENDED_MV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_MV is not present in the picture header 6433 EXTENDED_MV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_MV is present in the picture header 6434 }; 6435 6436 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6437 //! \details 6438 //! This field specifies whether the motion vectors for 6439 //! UV is rounded to half or full pel position. It is identical to the 6440 //! variable 6441 //! FASTUVMC in VC1 standard.This field is used in both VLD and IT 6442 //! modes.It is 6443 //! derived from FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in 6444 //! both VLD and 6445 //! IT modes, and should have the same value as Motion Vector Mode 6446 //! LSBit. 6447 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6448 { 6449 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 6450 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 6451 }; 6452 6453 //! \brief LOOPFILTER_ENABLE_FLAG 6454 //! \details 6455 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 6456 //! indicates if In-loop Deblocking is ON according to picture level 6457 //! bitstream syntax control. This bit affects BSD unit and also the loop 6458 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 6459 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 6460 //! in-loop deblocking operation follows the VC1 standard - deblocking 6461 //! doesn't cross slice boundary.When this bit is set to 0, but 6462 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 6463 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 6464 //! this case, deblocking operation does cross slice boundary.This field is 6465 //! used in VLD mode only, not in IT mode. 6466 enum LOOPFILTER_ENABLE_FLAG 6467 { 6468 LOOPFILTER_ENABLE_FLAG_UNNAMED0 = 0, //!< In-Loop-Deblocking-Filter is disabled 6469 LOOPFILTER_ENABLE_FLAG_UNNAMED1 = 1, //!< In-Loop-Deblocking-Filter is enabled 6470 }; 6471 6472 enum PANSCAN_PRESENT_FLAG 6473 { 6474 PANSCAN_PRESENT_FLAG_UNNAMED0 = 0, //!< Pan Scan Parameters are not present in the picture header 6475 PANSCAN_PRESENT_FLAG_UNNAMED1 = 1, //!< Pan Scan Parameters are present in the picture header 6476 }; 6477 6478 //! \brief RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6479 //! \details 6480 //! It is needed for Picture Header Parsing.Driver is responsible to keep 6481 //! RangeReductionScale, RangeReduction Enable and RANGERED Present Flag of 6482 //! current picture coherent. 6483 enum RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6484 { 6485 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Range Reduction Parameter (RANGEREDFRM) is not present in the picture header 6486 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Range Reduction Parameter (RANGEREDFRM) is present in the picture header. 6487 }; 6488 6489 enum SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6490 { 6491 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Bitstream for Simple and Main Profile has no sync marker 6492 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Bitstream for Simple and Main Profile may have sync marker(s) 6493 }; 6494 6495 enum MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6496 { 6497 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< RESPIC Parameter is present in the picture header 6498 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< RESPIC Parameter is present in the picture header 6499 }; 6500 6501 enum QUANTIZER 6502 { 6503 QUANTIZER_UNNAMED0 = 0, //!< implicit quantizer at frame leve 6504 QUANTIZER_UNNAMED1 = 1, //!< explicit quantizer at frame level, and use PQUANTIZER SE to specify uniform or non-uniform 6505 QUANTIZER_UNNAMED2 = 2, //!< explicit quantizer, and non-uniform quantizer for all frames 6506 QUANTIZER_UNNAMED3 = 3, //!< explicit quantizer, and uniform quantizer for all frames 6507 }; 6508 6509 //! \brief P_PIC_REF_DISTANCE 6510 //! \details 6511 //! This element defines the number of frames between the current frame and 6512 //! the reference frame. It is the same as the REFDIST SE in VC1 interlaced 6513 //! field picture header. It is present if the entry-level flag REFDIST_FLAG 6514 //! == 1, and if the picture type is not one of the following types: B/B, 6515 //! B/BI, BI/B, BI/BI. If the entry level flag REFDIST_FLAG == 0, REFDIST 6516 //! shall be set to the default value of 0.This field is used in VC1 6517 //! VLD mode only, not used in IT and intel VC1 VLD Long Format modes. 6518 enum P_PIC_REF_DISTANCE 6519 { 6520 P_PIC_REF_DISTANCE_UNNAMED0 = 0, //!< No additional details 6521 }; 6522 6523 //! \brief PROGRESSIVE_PIC_TYPE 6524 //! \details 6525 //! This field is used in both VC1 VLD mode and IT mode. It is the 6526 //! same parameter as bPicExtrapolation in VC1 spec.The Picture 6527 //! Structure and Progressive Pic Type are used to derive the picture 6528 //! structure as specified in FCM, in VC1 VLD and IT mode. 6529 enum PROGRESSIVE_PIC_TYPE 6530 { 6531 PROGRESSIVE_PIC_TYPE_UNNAMED0 = 0, //!< progressive only picture 6532 PROGRESSIVE_PIC_TYPE_UNNAMED1 = 1, //!< progressive only picture 6533 PROGRESSIVE_PIC_TYPE_UNNAMED2 = 2, //!< interlace picture (frame-interlace or field-interlace) 6534 PROGRESSIVE_PIC_TYPE_UNNAMED3 = 3, //!< illegal 6535 }; 6536 6537 //! \brief RANGE_REDUCTION_ENABLE 6538 //! \details 6539 //! This field specifies whether on-the-fly pixel value 6540 //! range reduction should be performed for the preceding (or forward) 6541 //! reference 6542 //! picture. Along with RangeReductionScale to specify whether scale up 6543 //! or down 6544 //! should be performed. It is not the same value as RANGEREDFRM Syntax 6545 //! Element 6546 //! (PictureParameters bPicDeblocked bit 5) in the Picture 6547 //! Header.This field is 6548 //! for Main Profile only. Simple Profile is always disable, and not 6549 //! applicable to 6550 //! Advanced Profile. This field is used in both VLD and IT modes.This 6551 //! is derived by 6552 //! driver from the history of RANGERED and RANGEREDFRM syntax elements 6553 //! (i.e. of 6554 //! forward/preceding reference picture) and those of the current 6555 //! picture.RANGERED 6556 //! is the same as (bPicOverflowBlocks >> 3) & 1. RANGEREDFRM 6557 //! is the same 6558 //! as (bPicDeblocked >> 5) & 1.For the current picture is a 6559 //! B picture, 6560 //! this field represents the state of the forward/preceding reference 6561 //! picture 6562 //! onlyDriver is responsible to keep RangeReductionScale, 6563 //! RangeReduction Enable and 6564 //! RANGERED Present Flag of current picture coherent. 6565 enum RANGE_REDUCTION_ENABLE 6566 { 6567 RANGE_REDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 6568 RANGE_REDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 6569 }; 6570 6571 //! \brief RANGE_REDUCTION_SCALE 6572 //! \details 6573 //! This field specifies whether the reference picture 6574 //! pixel values should be scaled up or scaled down on-the-fly, if 6575 //! RangeReduction is 6576 //! Enabled.NOTE: This bit is derived by driver for Main Profile only. 6577 //! Ignored in 6578 //! Simple and Advanced Profiles. This field is used in both VLD and IT 6579 //! modes.This 6580 //! is derived by driver from the history of RANGERED and RANGEREDFRM 6581 //! syntax 6582 //! elements (i.e. of forward/preceding reference picture) and those of 6583 //! the current 6584 //! picture. RANGERED is the same as (bPicOverflowBlocks >> 3) 6585 //! & 1. 6586 //! RANGEREDFRM is the same as (bPicDeblocked >> 5) & 1. For 6587 //! the current 6588 //! picture is a B picture, this field represents the state of the 6589 //! forward/preceding 6590 //! reference picture onlyDriver is responsible to keep 6591 //! RangeReductionScale, 6592 //! RangeReduction Enable and RANGERED Present Flag of current picture 6593 //! coherent. 6594 enum RANGE_REDUCTION_SCALE 6595 { 6596 RANGE_REDUCTION_SCALE_DISABLE = 0, //!< Scale down reference picture by factor of 2 6597 RANGE_REDUCTION_SCALE_ENABLE = 1, //!< Scale up reference picture by factor of 2 6598 }; 6599 6600 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 6601 //! \details 6602 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 6603 //! if Overlap smoothing is ON at the picture levelThis field is used in 6604 //! both VLD and IT modes 6605 enum OVERLAP_SMOOTHING_ENABLE_FLAG 6606 { 6607 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 6608 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 6609 }; 6610 6611 enum EXTENDED_DMV_PRESENT_FLAG 6612 { 6613 EXTENDED_DMV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_DMV is not present in the picture header 6614 EXTENDED_DMV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_DMV is present in the picture header 6615 }; 6616 6617 //! \brief REFPIC_FLAG 6618 //! \details 6619 //! For a BI picture, REFPIC flag must set to 0For I and P picture, REFPIC 6620 //! flag must set to 0.For a B picture, REFPIC flag must set to 0, except 6621 //! for a B-field in interlaced field mode which can be 0 or 1 (e.g. the top 6622 //! B field can be used as a reference for decoding its corresponding bottom 6623 //! B-field in a field pair).In VLD mode, this flag cannot be used as an 6624 //! optimization signaling for an I or P picture that is not used as a 6625 //! reference picture.This field is used in both VC1 VLD mode and IT 6626 //! mode. It is the same parameter as bPicDeblockConfined[bit2] in VC1 6627 //! spec.The Intra Picture Flag, Backward Prediction Present Flag and 6628 //! RefPicFlag are used to derive the picture type, as specified in PTYPE 6629 //! for a frame, and in FPTYPE for a field, in VC1 VLD and IT mode. 6630 enum REFPIC_FLAG 6631 { 6632 REFPIC_FLAG_UNNAMED0 = 0, //!< the current picture after decoded, will never used as a reference picture 6633 REFPIC_FLAG_UNNAMED1 = 1, //!< the current picture after decoded, will be used as a reference picture later 6634 }; 6635 6636 //! \name Initializations 6637 6638 //! \brief Explicit member initialization function 6639 MFD_VC1_SHORT_PIC_STATE_CMD(); 6640 6641 static const size_t dwSize = 5; 6642 static const size_t byteSize = 20; 6643 }; 6644 6645 //! 6646 //! \brief MFX_VC1_DIRECTMODE_STATE 6647 //! \details 6648 //! This is a picture level command and should be issued only once, even for 6649 //! a multi-slices picture. There is only one DMV buffer for read (when 6650 //! processing a B-picture) and one for write (when processing a P-Picture). 6651 //! Each DMV record is 64 bits per MB, to store the top and bottom field 6652 //! Motion Vector (32-bit MVx,y each). 6653 //! 6654 struct MFX_VC1_DIRECTMODE_STATE_CMD 6655 { 6656 union 6657 { 6658 //!< DWORD 0 6659 struct 6660 { 6661 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6662 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6663 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6664 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6665 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6666 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6667 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6668 }; 6669 uint32_t Value; 6670 } DW0; 6671 union 6672 { 6673 //!< DWORD 1 6674 struct 6675 { 6676 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 6677 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPicture : __CODEGEN_BITFIELD( 6, 31) ; //!< Direct MV Write Buffer Base Address for the Current Picture 6678 }; 6679 uint32_t Value; 6680 } DW1; 6681 union 6682 { 6683 //!< DWORD 2 6684 struct 6685 { 6686 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPicture4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Direct MV Write Buffer Base Address for the Current Picture [47:32] 6687 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 6688 }; 6689 uint32_t Value; 6690 } DW2; 6691 union 6692 { 6693 //!< DWORD 3 6694 struct 6695 { 6696 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 6697 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6698 uint32_t DirectMvWriteBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Direct MV Write Buffer - Memory Compression Enable 6699 uint32_t DirectMvWriteBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6700 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 6701 uint32_t DirectMvWriteBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6702 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 6703 }; 6704 uint32_t Value; 6705 } DW3; 6706 union 6707 { 6708 //!< DWORD 4 6709 struct 6710 { 6711 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 6712 uint32_t DirectMvReadBufferBaseAddressForTheReferencePicture : __CODEGEN_BITFIELD( 6, 31) ; //!< Direct MV Read Buffer Base Address for the Reference Picture 6713 }; 6714 uint32_t Value; 6715 } DW4; 6716 union 6717 { 6718 //!< DWORD 5 6719 struct 6720 { 6721 uint32_t DirectMvReadBufferBaseAddressForTheCurrentPicture4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Direct MV Read Buffer Base Address for the Current Picture [47:32] 6722 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 6723 }; 6724 uint32_t Value; 6725 } DW5; 6726 union 6727 { 6728 //!< DWORD 6 6729 struct 6730 { 6731 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 6732 uint32_t DirectMvReadBufferBaseAddressForTheCurrentPictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6733 uint32_t DirectMvReadBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Direct MV Read Buffer - Memory Compression Enable 6734 uint32_t DirectMvReadBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6735 uint32_t Reserved203 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 6736 uint32_t DirectMvReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6737 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 6738 }; 6739 uint32_t Value; 6740 } DW6; 6741 6742 //! \name Local enumerations 6743 6744 enum SUBOPCODE_B 6745 { 6746 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 6747 }; 6748 6749 enum SUBOPCODE_A 6750 { 6751 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 6752 }; 6753 6754 enum MEDIA_COMMAND_OPCODE 6755 { 6756 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 6757 }; 6758 6759 enum PIPELINE 6760 { 6761 PIPELINE_MFXVC1DIRECTMODESTATE = 2, //!< No additional details 6762 }; 6763 6764 enum COMMAND_TYPE 6765 { 6766 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6767 }; 6768 6769 //! \brief DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6770 //! \details 6771 //! This field controls the priority of arbitration used in the GAC/GAM 6772 //! pipeline for this surface. 6773 enum DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6774 { 6775 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 6776 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 6777 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 6778 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 6779 }; 6780 6781 //! \brief DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6782 //! \details 6783 //! Distinguishes Vertical from Horizontal compression. Please refer to 6784 //! vol1a 6785 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 6786 //! section for more details. 6787 enum DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6788 { 6789 DIRECT_MV_WRITE_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 6790 DIRECT_MV_WRITE_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 6791 }; 6792 6793 //! \brief DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6794 //! \details 6795 //! <b>For Media Surfaces:</b> 6796 //! This field specifies the tiled resource mode. 6797 enum DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6798 { 6799 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 6800 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 6801 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 6802 }; 6803 6804 //! \brief DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6805 //! \details 6806 //! This field controls the priority of arbitration used in the GAC/GAM 6807 //! pipeline for this surface. 6808 enum DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6809 { 6810 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 6811 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 6812 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 6813 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 6814 }; 6815 6816 //! \brief DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6817 //! \details 6818 //! Distinguishes Vertical from Horizontal compression. Please refer to 6819 //! vol1a 6820 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 6821 //! section for more details. 6822 enum DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6823 { 6824 DIRECT_MV_READ_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 6825 DIRECT_MV_READ_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 6826 }; 6827 6828 //! \brief DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6829 //! \details 6830 //! <b>For Media Surfaces:</b> 6831 //! This field specifies the tiled resource mode. 6832 enum DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6833 { 6834 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 6835 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 6836 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 6837 }; 6838 6839 //! \name Initializations 6840 6841 //! \brief Explicit member initialization function 6842 MFX_VC1_DIRECTMODE_STATE_CMD(); 6843 6844 static const size_t dwSize = 7; 6845 static const size_t byteSize = 28; 6846 }; 6847 6848 //! 6849 //! \brief MFD_VC1_BSD_OBJECT 6850 //! \details 6851 //! The MFD_VC1_BSD_OBJECT command is the only primitive command for the VC1 6852 //! Decoding Pipeline. The macroblock data portion of the bitstream is 6853 //! loaded as indirect data object.Before issuing a MFD_VC1_BSD_OBJECT 6854 //! command, all VC1 states of the MFD Engine need to be valid. Therefore 6855 //! the commands used to set these states need to have been issued prior to 6856 //! the issue of a MFD_VC1_BSD_OBJECT command.VC1 deblock filter kernel 6857 //! cross the slice boundary if in the last MB row of a slice, so need to 6858 //! know the last MB row of a slice to disable the edge mask. There is why 6859 //! VC1 BSD hardware need to know the end of MB address for the current 6860 //! slice. As such no more phantom slice is needed for VC1, as long as the 6861 //! driver will program both start MB address in the current slice and the 6862 //! start MB address of the next slice. As a result, we can also support 6863 //! multiple picture state commands in between slices. 6864 //! 6865 struct MFD_VC1_BSD_OBJECT_CMD 6866 { 6867 union 6868 { 6869 //!< DWORD 0 6870 struct 6871 { 6872 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6873 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6874 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6875 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6876 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6877 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6878 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6879 }; 6880 uint32_t Value; 6881 } DW0; 6882 union 6883 { 6884 //!< DWORD 1 6885 struct 6886 { 6887 uint32_t IndirectBsdDataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect BSD Data Length 6888 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6889 }; 6890 uint32_t Value; 6891 } DW1; 6892 union 6893 { 6894 //!< DWORD 2 6895 struct 6896 { 6897 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 6898 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 6899 }; 6900 uint32_t Value; 6901 } DW2; 6902 union 6903 { 6904 //!< DWORD 3 6905 struct 6906 { 6907 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< Next Slice Vertical Position 6908 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 6909 uint32_t SliceStartVerticalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Start Vertical Position 6910 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6911 }; 6912 uint32_t Value; 6913 } DW3; 6914 union 6915 { 6916 //!< DWORD 4 6917 struct 6918 { 6919 uint32_t FirstmbbitoffsetFirstMacroblockBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< FirstMbBitOffset (First Macroblock Bit Offset ) 6920 uint32_t Reserved131 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 6921 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD( 4, 4) ; //!< EMULATION_PREVENTION_BYTE_PRESENT 6922 uint32_t Reserved133 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 6923 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31) ; //!< First_MB_Byte_Offset of Slice Data or Slice Header 6924 }; 6925 uint32_t Value; 6926 } DW4; 6927 6928 //! \name Local enumerations 6929 6930 enum SUBOPCODE_B 6931 { 6932 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 6933 }; 6934 6935 enum SUBOPCODE_A 6936 { 6937 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6938 }; 6939 6940 enum MEDIA_COMMAND_OPCODE 6941 { 6942 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6943 }; 6944 6945 enum PIPELINE 6946 { 6947 PIPELINE_MFXMULTIDW = 2, //!< No additional details 6948 }; 6949 6950 enum COMMAND_TYPE 6951 { 6952 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6953 }; 6954 6955 enum EMULATION_PREVENTION_BYTE_PRESENT 6956 { 6957 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 6958 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 6959 }; 6960 6961 //! \name Initializations 6962 6963 //! \brief Explicit member initialization function 6964 MFD_VC1_BSD_OBJECT_CMD(); 6965 6966 static const size_t dwSize = 5; 6967 static const size_t byteSize = 20; 6968 }; 6969 6970 //! 6971 //! \brief MFX_JPEG_PIC_STATE 6972 //! \details 6973 //! 6974 //! 6975 struct MFX_JPEG_PIC_STATE_CMD 6976 { 6977 union 6978 { 6979 //!< DWORD 0 6980 struct 6981 { 6982 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6983 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6984 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6985 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6986 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6987 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6988 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6989 }; 6990 uint32_t Value; 6991 } DW0; 6992 union 6993 { 6994 //!< DWORD 1 6995 struct 6996 { 6997 uint32_t OutputMcuStructure : __CODEGEN_BITFIELD( 0, 2) ; //!< OUTPUT_MCU_STRUCTURE, Encoder Only 6998 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved, Encoder Only 6999 uint32_t InputSurfaceFormatYuv : __CODEGEN_BITFIELD( 8, 11) ; //!< INPUT_SURFACE_FORMAT_YUV, Encoder Only 7000 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 20) ; //!< Reserved, Encoder Only 7001 uint32_t PixelsInVerticalLastMcu : __CODEGEN_BITFIELD(21, 25) ; //!< Pixels In Vertical Last MCU, Encoder Only 7002 uint32_t PixelsInHorizontalLastMcu : __CODEGEN_BITFIELD(26, 30) ; //!< Pixels In Horizontal Last MCU, Encoder Only 7003 uint32_t Reserved63 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, Encoder Only 7004 } Obj0; 7005 struct 7006 { 7007 uint32_t InputFormatYuv : __CODEGEN_BITFIELD( 0, 2) ; //!< INPUT_FORMAT_YUV, Decoder Only 7008 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved, Decoder Only 7009 uint32_t Rotation : __CODEGEN_BITFIELD( 4, 5) ; //!< ROTATION, Decoder Only 7010 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved, Decoder Only 7011 uint32_t OutputFormatYuv : __CODEGEN_BITFIELD( 8, 11) ; //!< OUTPUT_FORMAT_YUV, Decoder Only 7012 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved, Decoder Only 7013 uint32_t AverageDownSampling : __CODEGEN_BITFIELD(16, 16) ; //!< AVERAGE_DOWN_SAMPLING, Decoder Only 7014 uint32_t VerticalDownSamplingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< VERTICAL_DOWN_SAMPLING_ENABLE, Decoder Only 7015 uint32_t HorizontalDownSamplingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< HORIZONTAL_DOWN_SAMPLING_ENABLE, Decoder Only 7016 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved, Decoder Only 7017 uint32_t VerticalUpSamplingEnable : __CODEGEN_BITFIELD(20, 20) ; //!< VERTICAL_UP_SAMPLING_ENABLE, Decoder Only 7018 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved, Decoder Only 7019 } Obj1; 7020 uint32_t Value; 7021 } DW1; 7022 union 7023 { 7024 //!< DWORD 2 7025 struct 7026 { 7027 uint32_t FrameWidthInBlocksMinus1 : __CODEGEN_BITFIELD( 0, 12) ; //!< Frame Width In Blocks Minus 1, Decoder Only 7028 uint32_t Reserved77 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, Decoder Only 7029 uint32_t FrameHeightInBlocksMinus1 : __CODEGEN_BITFIELD(16, 28) ; //!< Frame Height In Blocks Minus 1, Decoder Only 7030 uint32_t OutputPixelNormalize : __CODEGEN_BITFIELD(29, 29) ; //!< OUTPUT_PIXEL_NORMALIZE, Decoder Only 7031 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved, Decoder Only 7032 } Obj0; 7033 struct 7034 { 7035 uint32_t FrameWidthInBlksMinus1 : __CODEGEN_BITFIELD( 0, 12) ; //!< Frame Width In Blks Minus 1, Encoder Only 7036 uint32_t Roundingquant : __CODEGEN_BITFIELD(13, 15) ; //!< ROUNDINGQUANT, Encoder Only 7037 uint32_t FrameHeightInBlksMinus1 : __CODEGEN_BITFIELD(16, 28) ; //!< Frame Height In Blks Minus 1, Encoder Only 7038 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved, Encoder Only 7039 } Obj1; 7040 uint32_t Value; 7041 } DW2; 7042 7043 //! \name Local enumerations 7044 7045 enum SUBOPCODE_B 7046 { 7047 SUBOPCODE_B_MEDIA = 0, //!< No additional details 7048 }; 7049 7050 enum SUBOPCODE_A 7051 { 7052 SUBOPCODE_A_COMMON = 0, //!< No additional details 7053 }; 7054 7055 enum MEDIA_COMMAND_OPCODE 7056 { 7057 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 7058 }; 7059 7060 enum PIPELINE 7061 { 7062 PIPELINE_MFXMULTIDW = 2, //!< No additional details 7063 }; 7064 7065 enum COMMAND_TYPE 7066 { 7067 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7068 }; 7069 7070 //! \brief OUTPUT_MCU_STRUCTURE 7071 //! \details 7072 //! <p></p> 7073 //! Output MCU Structure(<b>OutputMcuStructure</b>) should be set 7074 //! accordingly for each Input Surface Format 7075 //! YUV(<b>InputSurfaceFormatYUV</b>): 7076 //! <ul> 7077 //! <li>If <b>InputSurfaceFormatYUV</b> is set to NV12, 7078 //! <b>OutputMCUStructure</b> is set to YUV420.</li> 7079 //! <li>If <b>InputSurfaceFormatYUV</b> is set to UYVY or YUY2, 7080 //! <b>OutputMCUStructure</b> is set to YUV422H_2Y.</li> 7081 //! <li>If <b>InputSurfaceFormatYUV</b> is set to Y8, 7082 //! <b>OutputMCuStructure</b> is set to YUV400.</li> 7083 //! <li>If <b>InputSurfaceFormatYUV</b> is set to RGB (or GBR, BGR, 7084 //! YUV), <b>OutputMCuStructure</b> is set to RGB.</li> 7085 //! <li>If <b>InputSurfaceFormatYUV</b> is set to RGB, the order of 7086 //! encoded blocks in MCU will be same as the order of input image 7087 //! components. 7088 //! If the order of input image components is RGB (or GBR, BGR, YUV), 7089 //! then the order of blocks will be RGB (or GBR, BGR, YUV 7090 //! respectively).</li> 7091 //! </ul> 7092 //! <p></p> 7093 enum OUTPUT_MCU_STRUCTURE 7094 { 7095 OUTPUT_MCU_STRUCTURE_YUV_400 = 0, //!< Grayscale Image 7096 OUTPUT_MCU_STRUCTURE_YUV_420 = 1, //!< Both horizontally and vertically chroma 2:1 subsampled 7097 OUTPUT_MCU_STRUCTURE_YUV_422H2Y = 2, //!< Horizontally chroma 2:1 subsampled - horizontal 2 Y-blocks, 1 U and 1 V block 7098 OUTPUT_MCU_STRUCTURE_RGB = 3, //!< RGB or YUV444: No subsample 7099 OUTPUT_MCU_STRUCTURE_UNNAMED_4 = 4, //!< No additional details 7100 OUTPUT_MCU_STRUCTURE_UNNAMED5 = 5, //!< No additional details 7101 OUTPUT_MCU_STRUCTURE_UNNAMED6 = 6, //!< No additional details 7102 OUTPUT_MCU_STRUCTURE_UNNAMED7 = 7, //!< No additional details 7103 }; 7104 7105 enum INPUT_FORMAT_YUV 7106 { 7107 INPUT_FORMAT_YUV_UNNAMED0 = 0, //!< YUV400 (grayscale image) 7108 INPUT_FORMAT_YUV_UNNAMED1 = 1, //!< YUV420 7109 INPUT_FORMAT_YUV_UNNAMED2 = 2, //!< YUV422H_2Y (Horizontally chroma 2:1 subsampled) - horizontal 2 Y-block, 1U and 1V 7110 INPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUV444 7111 INPUT_FORMAT_YUV_UNNAMED_4 = 4, //!< YUV411 7112 INPUT_FORMAT_YUV_UNNAMED5 = 5, //!< YUV422V_2Y (Vertically chroma 2:1 subsampled) - vertical 2 Y-blocks, 1U and 1V 7113 INPUT_FORMAT_YUV_UNNAMED6 = 6, //!< YUV422H_4Y - 2x2 Y-blocks, vertical 2U and 2V 7114 INPUT_FORMAT_YUV_UNNAMED7 = 7, //!< YUV422V_4Y - 2x2 Y-blocks, horizontal 2U and 2V 7115 }; 7116 7117 //! \brief ROTATION 7118 //! \details 7119 //! Rotation can be set to 01b, 10b, or 11b when OutputFormatYUV is set to 7120 //! 0000b. For other OutputFormatYUV, Rotation is not allowed. 7121 enum ROTATION 7122 { 7123 ROTATION_UNNAMED0 = 0, //!< no rotation 7124 ROTATION_UNNAMED1 = 1, //!< rotate clockwise 90 degree 7125 ROTATION_UNNAMED2 = 2, //!< rotate counter-clockwise 90 degree (same as rotating 270 degree clockwise) 7126 ROTATION_UNNAMED3 = 3, //!< rotate 180 degree (NOT the same as flipped on the x-axis) 7127 }; 7128 7129 //! \brief OUTPUT_FORMAT_YUV 7130 //! \details 7131 //! This field specifies the surface format to write the decoded JPEG 7132 //! image.Note that any non-interleaved JPEG input should be set to "0000". 7133 //! For the interleaved input Scan data, it can be set either "0000" or the 7134 //! corresponding format. 7135 enum OUTPUT_FORMAT_YUV 7136 { 7137 OUTPUT_FORMAT_YUV_UNNAMED0 = 0, //!< 3 separate plane for Y, U, and V respectively 7138 OUTPUT_FORMAT_YUV_UNNAMED1 = 1, //!< NV12 for chroma 4:2:0 7139 OUTPUT_FORMAT_YUV_UNNAMED2 = 2, //!< UYVY for chroma 4:2:2 7140 OUTPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUY2 for chroma 4:2:2 7141 }; 7142 7143 //! \brief INPUT_SURFACE_FORMAT_YUV 7144 //! \details 7145 //! This field specifies the surface format to read a YUV image data 7146 enum INPUT_SURFACE_FORMAT_YUV 7147 { 7148 INPUT_SURFACE_FORMAT_YUV_UNNAMED0 = 0, //!< Reserved 7149 INPUT_SURFACE_FORMAT_YUV_NV12 = 1, //!< NV12 for chroma 4:2:0 7150 INPUT_SURFACE_FORMAT_YUV_UYVY = 2, //!< UYVY for chroma 4:2:2 7151 INPUT_SURFACE_FORMAT_YUV_YUY2 = 3, //!< YUY2 for chroma 4:2:2 7152 INPUT_SURFACE_FORMAT_YUV_Y8 = 4, //!< Y8 for chroma400 Y-only image 7153 INPUT_SURFACE_FORMAT_YUV_RGB = 5, //!< RGB or YUV for chroma 4:4:4 7154 }; 7155 7156 //! \brief AVERAGE_DOWN_SAMPLING 7157 //! \details 7158 //! This flag is used to select a down-sampling method when 7159 //! <b>VertDownSamplingEnb</b> or <b>HoriDownSamplingEnb</b> is set to 1. 7160 enum AVERAGE_DOWN_SAMPLING 7161 { 7162 AVERAGE_DOWN_SAMPLING_UNNAMED0 = 0, //!< Drop every other line (or column) pixels 7163 AVERAGE_DOWN_SAMPLING_UNNAMED1 = 1, //!< Average neighboring two pixels 7164 }; 7165 7166 //! \brief VERTICAL_DOWN_SAMPLING_ENABLE 7167 //! \details 7168 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 7169 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 7170 //! enable this flag, the input should be interleaved Scan, 7171 //! <b>InputFormatYUV</b> should be set to YUV422H_2Y or YUV422H_4Y, and 7172 //! <b>OutputFormatYUV</b> should be set to NV12. 7173 enum VERTICAL_DOWN_SAMPLING_ENABLE 7174 { 7175 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 7176 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical down-sampling 7177 }; 7178 7179 //! \brief HORIZONTAL_DOWN_SAMPLING_ENABLE 7180 //! \details 7181 //! Only applied to chroma blocks. This flag is used for 2:1 horizontal 7182 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 7183 //! enable this flag, the input should be interleaved Scan, 7184 //! <b>InputFormatYUV</b> should be set to YUV422V_2Y or YUV422V_4Y, and 7185 //! <b>OutputFormatYUV</b> should be set to NV12. 7186 enum HORIZONTAL_DOWN_SAMPLING_ENABLE 7187 { 7188 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 7189 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 horizonatl down-sampling 7190 }; 7191 7192 //! \brief VERTICAL_UP_SAMPLING_ENABLE 7193 //! \details 7194 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 7195 //! up-sampling for chroma 420 and outputting chroma422 YUY2 or UYVY format. 7196 //! To enable this flag, the input should be interleaved Scan, 7197 //! <b>InputFormatYUV</b> should be set to YUV420, and 7198 //! <b>OutputFormatYUV</b> should be set to YUY2 or UYVY. 7199 enum VERTICAL_UP_SAMPLING_ENABLE 7200 { 7201 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no up-sampling 7202 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical up-sampling 7203 }; 7204 7205 //! \brief ROUNDINGQUANT 7206 //! \details 7207 //! Rounding value applied to quantization output 7208 enum ROUNDINGQUANT 7209 { 7210 ROUNDINGQUANT_UNNAMED0 = 0, //!< 1/2 7211 ROUNDINGQUANT_UNNAMED1 = 1, //!< (1/2 - 1/128) 7212 ROUNDINGQUANT_UNNAMED2 = 2, //!< (1/2 + 1/128) 7213 ROUNDINGQUANT_UNNAMED3 = 3, //!< (1/2 - 1/64) 7214 ROUNDINGQUANT_UNNAMED_4 = 4, //!< (1/2 + 1/64) 7215 ROUNDINGQUANT_UNNAMED5 = 5, //!< (1/2 - 1/32) 7216 ROUNDINGQUANT_UNNAMED6 = 6, //!< (1/2 - 1/16) 7217 ROUNDINGQUANT_UNNAMED7 = 7, //!< (1/2 - 1/8) 7218 }; 7219 7220 //! \brief OUTPUT_PIXEL_NORMALIZE 7221 //! \details 7222 //! JPEG decoded output pixels for Y and U/V in order to adjust display YUV 7223 //! range. 7224 enum OUTPUT_PIXEL_NORMALIZE 7225 { 7226 OUTPUT_PIXEL_NORMALIZE_UNNAMED0 = 0, //!< No Normalization 7227 OUTPUT_PIXEL_NORMALIZE_UNNAMED1 = 1, //!< Normalize output pixels from [0,255] to [16,235] 7228 }; 7229 7230 //! \name Initializations 7231 7232 //! \brief Explicit member initialization function 7233 MFX_JPEG_PIC_STATE_CMD(); 7234 7235 static const size_t dwSize = 3; 7236 static const size_t byteSize = 12; 7237 }; 7238 7239 //! 7240 //! \brief MFC_JPEG_HUFF_TABLE_STATE 7241 //! \details 7242 //! This Huffman table commands contains both DC and AC tables for either 7243 //! luma or chroma. Once a Huffman table has been defined for a particular 7244 //! destination, it replaces the previous tables stored in that destination 7245 //! and shall be used in the remaining Scans of the current image. Two 7246 //! Huffman tables for luma and chroma will be sent to H/W, and chroma table 7247 //! is used for both U and V. 7248 //! 7249 struct MFC_JPEG_HUFF_TABLE_STATE_CMD 7250 { 7251 union 7252 { 7253 //!< DWORD 0 7254 struct 7255 { 7256 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7257 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7258 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7259 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7260 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7261 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7262 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7263 }; 7264 uint32_t Value; 7265 } DW0; 7266 union 7267 { 7268 //!< DWORD 1 7269 struct 7270 { 7271 uint32_t HuffTableId : __CODEGEN_BITFIELD( 0, 0) ; //!< HUFF_TABLE_ID 7272 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 7273 }; 7274 uint32_t Value; 7275 } DW1; 7276 7277 uint32_t DcTable[12]; //!< DC_TABLE 7278 7279 7280 uint32_t AcTable[162]; //!< AC_TABLE 7281 7282 7283 //! \name Local enumerations 7284 7285 enum SUBOPCODE_B 7286 { 7287 SUBOPCODE_B_MEDIA = 3, //!< No additional details 7288 }; 7289 7290 enum SUBOPCODE_A 7291 { 7292 SUBOPCODE_A_COMMON = 2, //!< No additional details 7293 }; 7294 7295 enum MEDIA_COMMAND_OPCODE 7296 { 7297 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 7298 }; 7299 7300 enum PIPELINE 7301 { 7302 PIPELINE_MFCJPEGHUFFTABLESTATE = 2, //!< No additional details 7303 }; 7304 7305 enum COMMAND_TYPE 7306 { 7307 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7308 }; 7309 7310 //! \brief HUFF_TABLE_ID 7311 //! \details 7312 //! Huffman table destination identifier will specify one of two 7313 //! destinations at the encoder into which the Huffman table must be stored. 7314 enum HUFF_TABLE_ID 7315 { 7316 HUFF_TABLE_ID_UNNAMED0 = 0, //!< Huffman table 0 7317 HUFF_TABLE_ID_UNNAMED1 = 1, //!< Huffman table 1 7318 }; 7319 7320 //! \name Initializations 7321 7322 //! \brief Explicit member initialization function 7323 MFC_JPEG_HUFF_TABLE_STATE_CMD(); 7324 7325 static const size_t dwSize = 176; 7326 static const size_t byteSize = 704; 7327 }; 7328 7329 //! 7330 //! \brief MFD_JPEG_BSD_OBJECT 7331 //! \details 7332 //! 7333 //! 7334 struct MFD_JPEG_BSD_OBJECT_CMD 7335 { 7336 union 7337 { 7338 //!< DWORD 0 7339 struct 7340 { 7341 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7342 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7343 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7344 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7345 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7346 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7347 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7348 }; 7349 uint32_t Value; 7350 } DW0; 7351 union 7352 { 7353 //!< DWORD 1 7354 struct 7355 { 7356 uint32_t IndirectDataLength ; //!< Indirect Data Length 7357 }; 7358 uint32_t Value; 7359 } DW1; 7360 union 7361 { 7362 //!< DWORD 2 7363 struct 7364 { 7365 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 7366 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 7367 }; 7368 uint32_t Value; 7369 } DW2; 7370 union 7371 { 7372 //!< DWORD 3 7373 struct 7374 { 7375 uint32_t ScanVerticalPosition : __CODEGEN_BITFIELD( 0, 12) ; //!< Scan Vertical Position 7376 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 7377 uint32_t ScanHorizontalPosition : __CODEGEN_BITFIELD(16, 28) ; //!< Scan Horizontal Position 7378 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 7379 }; 7380 uint32_t Value; 7381 } DW3; 7382 union 7383 { 7384 //!< DWORD 4 7385 struct 7386 { 7387 uint32_t McuCount : __CODEGEN_BITFIELD( 0, 25) ; //!< MCU Count 7388 uint32_t Reserved154 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 7389 uint32_t ScanComponents : __CODEGEN_BITFIELD(27, 29) ; //!< Scan Components 7390 uint32_t Interleaved : __CODEGEN_BITFIELD(30, 30) ; //!< INTERLEAVED 7391 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 7392 }; 7393 uint32_t Value; 7394 } DW4; 7395 union 7396 { 7397 //!< DWORD 5 7398 struct 7399 { 7400 uint32_t Restartinterval16Bit : __CODEGEN_BITFIELD( 0, 15) ; //!< RestartInterval(16 bit) 7401 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 7402 }; 7403 uint32_t Value; 7404 } DW5; 7405 7406 //! \name Local enumerations 7407 7408 enum SUBOPCODE_B 7409 { 7410 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 7411 }; 7412 7413 enum SUBOPCODE_A 7414 { 7415 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 7416 }; 7417 7418 enum MEDIA_COMMAND_OPCODE 7419 { 7420 MEDIA_COMMAND_OPCODE_JPEGDEC = 7, //!< No additional details 7421 }; 7422 7423 enum PIPELINE 7424 { 7425 PIPELINE_MFDJPEGBSDOBJECT = 2, //!< No additional details 7426 }; 7427 7428 enum COMMAND_TYPE 7429 { 7430 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7431 }; 7432 7433 enum INTERLEAVED 7434 { 7435 INTERLEAVED_NON_INTERLEAVED = 0, //!< one component in the Scan 7436 INTERLEAVED_INTERLEAVED = 1, //!< multiple components in the Scan 7437 }; 7438 7439 //! \name Initializations 7440 7441 //! \brief Explicit member initialization function 7442 MFD_JPEG_BSD_OBJECT_CMD(); 7443 7444 static const size_t dwSize = 6; 7445 static const size_t byteSize = 24; 7446 }; 7447 7448 //! 7449 //! \brief MFC_JPEG_SCAN_OBJECT 7450 //! \details 7451 //! Encoder Only 7452 //! 7453 struct MFC_JPEG_SCAN_OBJECT_CMD 7454 { 7455 union 7456 { 7457 //!< DWORD 0 7458 struct 7459 { 7460 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7461 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7462 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7463 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7464 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7465 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7466 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7467 }; 7468 uint32_t Value; 7469 } DW0; 7470 union 7471 { 7472 //!< DWORD 1 7473 struct 7474 { 7475 uint32_t McuCount : __CODEGEN_BITFIELD( 0, 25) ; //!< MCU Count 7476 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 7477 }; 7478 uint32_t Value; 7479 } DW1; 7480 union 7481 { 7482 //!< DWORD 2 7483 struct 7484 { 7485 uint32_t RestartInterval : __CODEGEN_BITFIELD( 0, 15) ; //!< Restart Interval 7486 uint32_t IsLastScan : __CODEGEN_BITFIELD(16, 16) ; //!< IS_LAST_SCAN 7487 uint32_t HeadPresentFlag : __CODEGEN_BITFIELD(17, 17) ; //!< HEAD_PRESENT_FLAG 7488 uint32_t HuffmanDcTable : __CODEGEN_BITFIELD(18, 20) ; //!< HUFFMAN_DC_TABLE 7489 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 7490 uint32_t HuffmanAcTable : __CODEGEN_BITFIELD(22, 24) ; //!< HUFFMAN_AC_TABLE 7491 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 7492 }; 7493 uint32_t Value; 7494 } DW2; 7495 7496 //! \name Local enumerations 7497 7498 enum SUBOPCODE_B 7499 { 7500 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 7501 }; 7502 7503 enum SUBOPCODE_A 7504 { 7505 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 7506 }; 7507 7508 enum MEDIA_COMMAND_OPCODE 7509 { 7510 MEDIA_COMMAND_OPCODE_JPEGENC = 7, //!< No additional details 7511 }; 7512 7513 enum PIPELINE 7514 { 7515 PIPELINE_MFCJPEGSCANOBJECT = 2, //!< No additional details 7516 }; 7517 7518 enum COMMAND_TYPE 7519 { 7520 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7521 }; 7522 7523 //! \brief IS_LAST_SCAN 7524 //! \details 7525 //! If this flag is set, then HW will insert EOI (0xFFD9) to the end of Scan 7526 //! encoded bitstream. 7527 enum IS_LAST_SCAN 7528 { 7529 IS_LAST_SCAN_UNNAMED0 = 0, //!< Not the last Scan. 7530 IS_LAST_SCAN_UNNAMED1 = 1, //!< Indicates that the current Scan is the last one. 7531 }; 7532 7533 //! \brief HEAD_PRESENT_FLAG 7534 //! \details 7535 //! If this flag is set to 0, then no MFC_JPEG_PAK_INSERT_OBJECT commands 7536 //! will be sent. 7537 //! If this flag is set to 1, then one or more 7538 //! MFC_JPEG_PAK_INSERT_OBJECT commands will be sent after 7539 //! MFC_JPEG_SCAN_OBJECT command. 7540 enum HEAD_PRESENT_FLAG 7541 { 7542 HEAD_PRESENT_FLAG_UNNAMED0 = 0, //!< No insertion into the output bitstream buffer before Scan encoded bitstream 7543 HEAD_PRESENT_FLAG_UNNAMED1 = 1, //!< Headers, tables, App data insertion into the output bitstream buffer. HW will insert the insertion data before the Scan encoded bitstream. 7544 }; 7545 7546 //! \brief HUFFMAN_DC_TABLE 7547 //! \details 7548 //! DC Huffman table destination selector specifies one of two possible DC 7549 //! table destinations for each Y, U, V, or R, G, B. 7550 //! The DC Huffman tables shall have been loaded in destination 0 and 1 7551 //! by the time of issuing MFC_JPEG_HUFF_TABLE_STATE Command. 7552 enum HUFFMAN_DC_TABLE 7553 { 7554 HUFFMAN_DC_TABLE_BIT20V0 = 0, //!< The third image component must use the DC table 0. 7555 HUFFMAN_DC_TABLE_BIT19U0 = 0, //!< The second image component must use the DC table 0. 7556 HUFFMAN_DC_TABLE_BIT18Y0 = 0, //!< The first image component must use the DC table 0. 7557 HUFFMAN_DC_TABLE_BIT18Y1 = 1, //!< The first image component must use the DC table 1. 7558 HUFFMAN_DC_TABLE_BIT19U1 = 2, //!< The second image component must use the DC table 1. 7559 HUFFMAN_DC_TABLE_BIT20V1 = 4, //!< The third image component must use the DC table 1. 7560 }; 7561 7562 //! \brief HUFFMAN_AC_TABLE 7563 //! \details 7564 //! AC Huffman table destination selector specifies one of two possible AC 7565 //! table destinations for each Y, U, V, or R, G, B. 7566 //! The AC Huffman tables must have been loaded in destination 0 and 1 7567 //! by the time of issuing MFC_JPEG_HUFF_TABLE_STATE Command. 7568 enum HUFFMAN_AC_TABLE 7569 { 7570 HUFFMAN_AC_TABLE_BIT2_4V0 = 0, //!< The third image component must use the AC table 0. 7571 HUFFMAN_AC_TABLE_BIT23U0 = 0, //!< The second image component must use the AC table 0. 7572 HUFFMAN_AC_TABLE_BIT22Y0 = 0, //!< The first image component must use the AC table 0. 7573 HUFFMAN_AC_TABLE_BIT22Y1 = 1, //!< The first image component must use the AC table 1. 7574 HUFFMAN_AC_TABLE_BIT23U1 = 2, //!< The second image component must use the AC table 1. 7575 HUFFMAN_AC_TABLE_BIT2_4V1 = 4, //!< The third image component must use the AC table 1. 7576 }; 7577 7578 //! \name Initializations 7579 7580 //! \brief Explicit member initialization function 7581 MFC_JPEG_SCAN_OBJECT_CMD(); 7582 7583 static const size_t dwSize = 3; 7584 static const size_t byteSize = 12; 7585 }; 7586 7587 //! 7588 //! \brief MFX_VP8_Encoder_CFG 7589 //! \details 7590 //! This must be the very first command to issue after the surface state, 7591 //! the pipe select and base address setting commands and must be issued 7592 //! before MFX_VP8_PIC_STATE. 7593 //! 7594 struct MFX_VP8_Encoder_CFG_CMD 7595 { 7596 union 7597 { 7598 //!< DWORD 0 7599 struct 7600 { 7601 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7602 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7603 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 7604 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 7605 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7606 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7607 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7608 }; 7609 uint32_t Value; 7610 } DW0; 7611 union 7612 { 7613 //!< DWORD 1 7614 struct 7615 { 7616 uint32_t PerformanceCounterEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Performance Counter Enable 7617 uint32_t FinalBitstreamOutputDisable : __CODEGEN_BITFIELD( 1, 1) ; //!< Final Bitstream Output Disable 7618 uint32_t TokenStatisticsOutputEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Output Enable 7619 uint32_t BitstreamStatisticsOutputEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< Bitstream Statistics Output Enable 7620 uint32_t UpdateSegmentFeatureDataFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< Update Segment Feature Data Flag 7621 uint32_t SkipFinalBitstreamWhenOverUnderFlow : __CODEGEN_BITFIELD( 5, 5) ; //!< Skip Final Bitstream when Over / Under flow 7622 uint32_t RateControlInitialPass : __CODEGEN_BITFIELD( 6, 6) ; //!< RATE_CONTROL_INITIAL_PASS 7623 uint32_t PerSegmentDeltaQindexLoopfilterDisable : __CODEGEN_BITFIELD( 7, 7) ; //!< Per Segment Delta Qindex / LoopFilter Disable 7624 uint32_t FinerBrcEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Finer BRC Enable 7625 uint32_t CompressedBitstreamOutputDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Compressed Bitstream Output Disable 7626 uint32_t VbspunitpowerclockGatingDisable : __CODEGEN_BITFIELD(10, 10) ; //!< VBSPunitPowerClock Gating Disable 7627 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 7628 }; 7629 uint32_t Value; 7630 } DW1; 7631 union 7632 { 7633 //!< DWORD 2 7634 struct 7635 { 7636 uint32_t MaxFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD( 0, 0) ; //!< MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7637 uint32_t MinFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD( 1, 1) ; //!< MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7638 uint32_t MaxInterMbBitCountCheckEnableMask : __CODEGEN_BITFIELD( 2, 2) ; //!< Max Inter MB Bit Count Check Enable Mask 7639 uint32_t MaxIntraMbBitCountCheckEnableMask : __CODEGEN_BITFIELD( 3, 3) ; //!< Max Intra MB Bit Count Check Enable Mask 7640 uint32_t IntermediateBitBufferOverrunEnableMask : __CODEGEN_BITFIELD( 4, 4) ; //!< Intermediate Bit Buffer Overrun Enable Mask 7641 uint32_t FinalBistreamBufferOverrunEnableMask : __CODEGEN_BITFIELD( 5, 5) ; //!< Final Bistream Buffer Overrun Enable Mask 7642 uint32_t QindexClampHighMaskForUnderflow : __CODEGEN_BITFIELD( 6, 6) ; //!< Qindex_Clamp_High_mask for underflow 7643 uint32_t QindexClampHighMaskForOverflow : __CODEGEN_BITFIELD( 7, 7) ; //!< Qindex_Clamp_High_mask for overflow 7644 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 7645 }; 7646 uint32_t Value; 7647 } DW2; 7648 union 7649 { 7650 //!< DWORD 3 7651 struct 7652 { 7653 uint32_t MaxInterMbBitCount : __CODEGEN_BITFIELD( 0, 11) ; //!< Max Inter MB bit count 7654 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7655 uint32_t MaxIntraMbBitCountLimit : __CODEGEN_BITFIELD(16, 27) ; //!< Max Intra MB Bit Count Limit 7656 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 7657 }; 7658 uint32_t Value; 7659 } DW3; 7660 union 7661 { 7662 //!< DWORD 4 7663 struct 7664 { 7665 uint32_t FrameBitRateMax : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Bit Rate Max 7666 uint32_t FrameBitRateMaxUnit : __CODEGEN_BITFIELD(14, 14) ; //!< FRAME_BIT_RATE_MAX_UNIT 7667 uint32_t FrameBitrateMaxUnitMode : __CODEGEN_BITFIELD(15, 15) ; //!< FRAME_BITRATE_MAX_UNIT_MODE 7668 uint32_t FrameBitRateMin : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Bit Rate Min 7669 uint32_t FrameBitRateMinUnit : __CODEGEN_BITFIELD(30, 30) ; //!< FRAME_BIT_RATE_MIN_UNIT 7670 uint32_t FrameBitrateMinUnitMode : __CODEGEN_BITFIELD(31, 31) ; //!< FRAME_BITRATE_MIN_UNIT_MODE 7671 }; 7672 uint32_t Value; 7673 } DW4; 7674 union 7675 { 7676 //!< DWORD 5 7677 struct 7678 { 7679 uint32_t FrameDeltaQindexMax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta QIndex Max [0] 7680 uint32_t FrameDeltaQindexMax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta QIndex Max[1] 7681 uint32_t FrameDeltaqIndexMax2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame DeltaQ Index Max[2] 7682 uint32_t FrameDeltaQindexMax3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta QIndex Max[3] 7683 }; 7684 uint32_t Value; 7685 } DW5; 7686 union 7687 { 7688 //!< DWORD 6 7689 struct 7690 { 7691 uint32_t FrameDeltaQindexMin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta QIndex Min[0] 7692 uint32_t FrameDeltaQindexMin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta QIndex Min[1] 7693 uint32_t FrameDeltaQindexMin2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta QIndex Min[2] 7694 uint32_t FrameDeltaQindexMin3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta QIndex Min[3] 7695 }; 7696 uint32_t Value; 7697 } DW6; 7698 union 7699 { 7700 //!< DWORD 7 7701 struct 7702 { 7703 uint32_t PerSegmentFrameDeltaQindexMax1 ; //!< Per Segment Frame Delta QIndex Max[1] 7704 }; 7705 uint32_t Value; 7706 } DW7; 7707 union 7708 { 7709 //!< DWORD 8 7710 struct 7711 { 7712 uint32_t PerSegmentFrameDeltaQindexMin1 ; //!< Per Segment Frame Delta QIndex Min[1] 7713 }; 7714 uint32_t Value; 7715 } DW8; 7716 union 7717 { 7718 //!< DWORD 9 7719 struct 7720 { 7721 uint32_t PerSegmentFrameDeltaQindexMax2 ; //!< Per Segment Frame Delta QIndex Max[2] 7722 }; 7723 uint32_t Value; 7724 } DW9; 7725 union 7726 { 7727 //!< DWORD 10 7728 struct 7729 { 7730 uint32_t PerSegmentFrameDeltaQindexMin2 ; //!< Per Segment Frame Delta QIndex Min[2] 7731 }; 7732 uint32_t Value; 7733 } DW10; 7734 union 7735 { 7736 //!< DWORD 11 7737 struct 7738 { 7739 uint32_t PerSegmentFrameDeltaQindexMax3 ; //!< Per Segment Frame Delta QIndex Max[3] 7740 }; 7741 uint32_t Value; 7742 } DW11; 7743 union 7744 { 7745 //!< DWORD 12 7746 struct 7747 { 7748 uint32_t PerSegmentFrameDeltaQindexMin3 ; //!< Per Segment Frame Delta QIndex Min[3] 7749 }; 7750 uint32_t Value; 7751 } DW12; 7752 union 7753 { 7754 //!< DWORD 13 7755 struct 7756 { 7757 uint32_t FrameDeltaLoopFilterMax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta Loop Filter Max[0] 7758 uint32_t FramEdeltaLoopFilterMax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Fram eDelta Loop Filter Max[1] 7759 uint32_t FrameDeltaLoopFilterMax2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta Loop Filter Max[2] 7760 uint32_t FrameDeltaLoopFilterMax3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta Loop Filter Max[3] 7761 }; 7762 uint32_t Value; 7763 } DW13; 7764 union 7765 { 7766 //!< DWORD 14 7767 struct 7768 { 7769 uint32_t FrameDeltaLoopFilterMin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta Loop Filter Min[0] 7770 uint32_t FrameDeltaLoopFilterMin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta Loop Filter Min[1] 7771 uint32_t FrameDeltaLoopFilterMin2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta Loop Filter Min[2] 7772 uint32_t FrameDeltaLoopFilterMin3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta Loop Filter Min[3] 7773 }; 7774 uint32_t Value; 7775 } DW14; 7776 union 7777 { 7778 //!< DWORD 15 7779 struct 7780 { 7781 uint32_t PerSegmentFrameDeltaLoopfilterMax1 ; //!< Per Segment Frame Delta LoopFilter Max[1] 7782 }; 7783 uint32_t Value; 7784 } DW15; 7785 union 7786 { 7787 //!< DWORD 16 7788 struct 7789 { 7790 uint32_t PerSegmentFrameDeltaLoopfilterMin1 ; //!< Per Segment Frame Delta LoopFilter Min[1] 7791 }; 7792 uint32_t Value; 7793 } DW16; 7794 union 7795 { 7796 //!< DWORD 17 7797 struct 7798 { 7799 uint32_t PerSegmentFrameDeltaLoopfilterMax2 ; //!< Per Segment Frame Delta LoopFilter Max[2] 7800 }; 7801 uint32_t Value; 7802 } DW17; 7803 union 7804 { 7805 //!< DWORD 18 7806 struct 7807 { 7808 uint32_t PerSegmentFrameDeltaLoopfilterMin2 ; //!< Per Segment Frame Delta LoopFilter Min[2] 7809 }; 7810 uint32_t Value; 7811 } DW18; 7812 union 7813 { 7814 //!< DWORD 19 7815 struct 7816 { 7817 uint32_t PerSegmentFrameDeltaLoopfilterMax3 ; //!< Per Segment Frame Delta LoopFilter Max[3] 7818 }; 7819 uint32_t Value; 7820 } DW19; 7821 union 7822 { 7823 //!< DWORD 20 7824 struct 7825 { 7826 uint32_t PerSegmentFrameDeltaLoopfilterMin3 ; //!< Per Segment Frame Delta LoopFilter Min[3] 7827 }; 7828 uint32_t Value; 7829 } DW20; 7830 union 7831 { 7832 //!< DWORD 21 7833 struct 7834 { 7835 uint32_t FrameBitRateMaxDelta : __CODEGEN_BITFIELD( 0, 14) ; //!< Frame Bit Rate Max Delta 7836 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 7837 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(16, 30) ; //!< FrameBitRateMinDelta 7838 uint32_t Reserved703 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 7839 }; 7840 uint32_t Value; 7841 } DW21; 7842 union 7843 { 7844 //!< DWORD 22 7845 struct 7846 { 7847 uint32_t MinFrameWsize : __CODEGEN_BITFIELD( 0, 15) ; //!< Min Frame WSize 7848 uint32_t MinFrameWsizeUnit : __CODEGEN_BITFIELD(16, 17) ; //!< MIN_FRAME_WSIZE_UNIT 7849 uint32_t Reserved722 : __CODEGEN_BITFIELD(18, 19) ; //!< Reserved 7850 uint32_t BitstreamFormatVersion : __CODEGEN_BITFIELD(20, 22) ; //!< Bitstream Format Version 7851 uint32_t ShowFrame : __CODEGEN_BITFIELD(23, 23) ; //!< Show Frame 7852 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 7853 }; 7854 uint32_t Value; 7855 } DW22; 7856 union 7857 { 7858 //!< DWORD 23 7859 struct 7860 { 7861 uint32_t HorizontalSizeCode : __CODEGEN_BITFIELD( 0, 15) ; //!< Horizontal_Size_Code 7862 uint32_t VerticalSizeCode : __CODEGEN_BITFIELD(16, 31) ; //!< Vertical_Size_Code 7863 }; 7864 uint32_t Value; 7865 } DW23; 7866 union 7867 { 7868 //!< DWORD 24 7869 struct 7870 { 7871 uint32_t FrameHeaderBitCount ; //!< Frame Header Bit Count 7872 }; 7873 uint32_t Value; 7874 } DW24; 7875 union 7876 { 7877 //!< DWORD 25 7878 struct 7879 { 7880 uint32_t FrameHeaderBinBufferQindexUpdatePointer ; //!< Frame Header Bin Buffer Qindex Update Pointer 7881 }; 7882 uint32_t Value; 7883 } DW25; 7884 union 7885 { 7886 //!< DWORD 26 7887 struct 7888 { 7889 uint32_t FrameHeaderBinBufferLoopfilterUpdatePointer ; //!< Frame Header Bin Buffer LoopFilter Update Pointer 7890 }; 7891 uint32_t Value; 7892 } DW26; 7893 union 7894 { 7895 //!< DWORD 27 7896 struct 7897 { 7898 uint32_t FrameHeaderBinBufferTokenUpdatePointer ; //!< Frame Header Bin Buffer Token Update Pointer 7899 }; 7900 uint32_t Value; 7901 } DW27; 7902 union 7903 { 7904 //!< DWORD 28 7905 struct 7906 { 7907 uint32_t FrameHeaderBinBufferMvupdatePointer ; //!< Frame Header Bin Buffer MVUpdate Pointer 7908 }; 7909 uint32_t Value; 7910 } DW28; 7911 union 7912 { 7913 //!< DWORD 29 7914 struct 7915 { 7916 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 7917 uint32_t Cv1 : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 7918 uint32_t Cv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 7919 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 7920 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 7921 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 7922 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 7923 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31) ; //!< ClampValues - CV7 7924 }; 7925 uint32_t Value; 7926 } DW29; 7927 7928 //! \name Local enumerations 7929 7930 enum SUB_OPCODE_B 7931 { 7932 SUB_OPCODE_B_MFXVP8ENCODERCFG = 1, //!< No additional details 7933 }; 7934 7935 enum SUB_OPCODE_A 7936 { 7937 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 7938 }; 7939 7940 enum MEDIA_COMMAND_OPCODE 7941 { 7942 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 7943 }; 7944 7945 enum PIPELINE 7946 { 7947 PIPELINE_VIDEOCODEC = 2, //!< No additional details 7948 }; 7949 7950 enum COMMAND_TYPE 7951 { 7952 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7953 }; 7954 7955 enum RATE_CONTROL_INITIAL_PASS 7956 { 7957 RATE_CONTROL_INITIAL_PASS_SUBSEQUENCEPASSES = 0, //!< No additional details 7958 RATE_CONTROL_INITIAL_PASS_INITIALPASS = 1, //!< No additional details 7959 }; 7960 7961 //! \brief MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7962 //! \details 7963 //! Enable Max. Frame Rate Control. 7964 //! This is a mask bit controlling if the condition of frame level bit 7965 //! count is greater than or equal to FrameBitRateMax. 7966 enum MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7967 { 7968 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS control register. 7969 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) >= (Frame Bit Rate Maximum Limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS control register. 7970 }; 7971 7972 //! \brief MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7973 //! \details 7974 //! Enable Min. Frame Rate Control. 7975 //! This is a mask bit controlling if the condition of frame level bit 7976 //! count is less than or equal to FrameBitRateMin. 7977 enum MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7978 { 7979 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS Control Register. 7980 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) =< (Frame Bit Rate Minimum limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS Control Register. 7981 }; 7982 7983 //! \brief FRAME_BIT_RATE_MAX_UNIT 7984 //! \details 7985 //! <i>This field is Frame Bitrate Maximum Mode</i> 7986 enum FRAME_BIT_RATE_MAX_UNIT 7987 { 7988 FRAME_BIT_RATE_MAX_UNIT_32_B = 0, //!< No additional details 7989 FRAME_BIT_RATE_MAX_UNIT_4_KB = 1, //!< No additional details 7990 }; 7991 7992 //! \brief FRAME_BITRATE_MAX_UNIT_MODE 7993 //! \details 7994 //! This field is the Frame Bitrate Maximum Limit Units. 7995 enum FRAME_BITRATE_MAX_UNIT_MODE 7996 { 7997 FRAME_BITRATE_MAX_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Max Unit is in old mode (128b/16Kb) 7998 FRAME_BITRATE_MAX_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Max Unit is in new mode (32byte/4Kb) 7999 }; 8000 8001 //! \brief FRAME_BIT_RATE_MIN_UNIT 8002 //! \details 8003 //! <i>This field is Frame Bitrate Minimum Mode.</i> 8004 enum FRAME_BIT_RATE_MIN_UNIT 8005 { 8006 FRAME_BIT_RATE_MIN_UNIT_32_B = 0, //!< No additional details 8007 FRAME_BIT_RATE_MIN_UNIT_4_KB = 1, //!< No additional details 8008 }; 8009 8010 //! \brief FRAME_BITRATE_MIN_UNIT_MODE 8011 //! \details 8012 //! This field is the Frame Bitrate Minimum Limit Units. 8013 enum FRAME_BITRATE_MIN_UNIT_MODE 8014 { 8015 FRAME_BITRATE_MIN_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Min Unit is in old mode (128b/16Kb) 8016 FRAME_BITRATE_MIN_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Min Unit is in new mode (32byte/4Kb) 8017 }; 8018 8019 enum MIN_FRAME_WSIZE_UNIT 8020 { 8021 MIN_FRAME_WSIZE_UNIT_COMPATIBILITYMODE = 0, //!< MinFrameWSizeUnit is in old mode (128b/16Kb) 8022 MIN_FRAME_WSIZE_UNIT_NEWMODE = 1, //!< MinFrameWSizeUnit is in new mode (32byte/4Kb) 8023 }; 8024 8025 //! \name Initializations 8026 8027 //! \brief Explicit member initialization function 8028 MFX_VP8_Encoder_CFG_CMD(); 8029 8030 static const size_t dwSize = 30; 8031 static const size_t byteSize = 120; 8032 }; 8033 8034 //! 8035 //! \brief MFX_VP8_BSP_BUF_BASE_ADDR_STATE 8036 //! \details 8037 //! 8038 //! 8039 struct MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD 8040 { 8041 union 8042 { 8043 //!< DWORD 0 8044 struct 8045 { 8046 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 8047 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 8048 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 8049 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 8050 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 8051 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 8052 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 8053 }; 8054 uint32_t Value; 8055 } DW0; 8056 union 8057 { 8058 //!< DWORD 1 8059 struct 8060 { 8061 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8062 uint32_t FrameHeaderBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Frame Header Base Addr 8063 }; 8064 uint32_t Value; 8065 } DW1; 8066 union 8067 { 8068 //!< DWORD 2 8069 struct 8070 { 8071 uint32_t FrameHeaderBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Frame Header Base Addr - Upper Range 8072 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8073 }; 8074 uint32_t Value; 8075 } DW2; 8076 union 8077 { 8078 //!< DWORD 3 8079 struct 8080 { 8081 uint32_t FrameHeaderBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8082 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8083 uint32_t FrameHeaderBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8084 uint32_t ForFrameheaderbaseaddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8085 uint32_t FrameHeaderBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8086 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8087 }; 8088 uint32_t Value; 8089 } DW3; 8090 union 8091 { 8092 //!< DWORD 4 8093 struct 8094 { 8095 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8096 uint32_t IntermediateBufferBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Intermediate Buffer Base Addr 8097 }; 8098 uint32_t Value; 8099 } DW4; 8100 union 8101 { 8102 //!< DWORD 5 8103 struct 8104 { 8105 uint32_t IntermediateBufferBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Intermediate Buffer Base Addr - Upper Range 8106 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8107 }; 8108 uint32_t Value; 8109 } DW5; 8110 union 8111 { 8112 //!< DWORD 6 8113 struct 8114 { 8115 uint32_t IntermediateBufferBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8116 uint32_t Reserved194 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8117 uint32_t IntermediateBufferBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8118 uint32_t IntermediateBufferBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8119 uint32_t IntermediateBufferBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8120 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8121 }; 8122 uint32_t Value; 8123 } DW6; 8124 union 8125 { 8126 //!< DWORD 7 8127 struct 8128 { 8129 uint32_t IntermediateBufferPartition1Offset ; //!< Intermediate Buffer Partition-1 Offset 8130 }; 8131 uint32_t Value; 8132 } DW7; 8133 union 8134 { 8135 //!< DWORD 8 8136 struct 8137 { 8138 uint32_t IntermediateBufferPartition2Offset ; //!< Intermediate Buffer Partition-2 Offset 8139 }; 8140 uint32_t Value; 8141 } DW8; 8142 union 8143 { 8144 //!< DWORD 9 8145 struct 8146 { 8147 uint32_t IntermediateBufferPartition3Offset ; //!< Intermediate Buffer Partition-3 Offset 8148 }; 8149 uint32_t Value; 8150 } DW9; 8151 union 8152 { 8153 //!< DWORD 10 8154 struct 8155 { 8156 uint32_t IntermediateBufferPartition4Offset ; //!< Intermediate Buffer Partition-4 Offset 8157 }; 8158 uint32_t Value; 8159 } DW10; 8160 union 8161 { 8162 //!< DWORD 11 8163 struct 8164 { 8165 uint32_t IntermediateBufferPartition5Offset ; //!< Intermediate Buffer Partition-5 Offset 8166 }; 8167 uint32_t Value; 8168 } DW11; 8169 union 8170 { 8171 //!< DWORD 12 8172 struct 8173 { 8174 uint32_t IntermediateBufferPartition6Offset ; //!< Intermediate Buffer Partition-6 Offset 8175 }; 8176 uint32_t Value; 8177 } DW12; 8178 union 8179 { 8180 //!< DWORD 13 8181 struct 8182 { 8183 uint32_t IntermediateBufferPartition7Offset ; //!< Intermediate Buffer Partition-7 Offset 8184 }; 8185 uint32_t Value; 8186 } DW13; 8187 union 8188 { 8189 //!< DWORD 14 8190 struct 8191 { 8192 uint32_t IntermediateBufferPartition8Offset ; //!< Intermediate Buffer Partition-8 Offset 8193 }; 8194 uint32_t Value; 8195 } DW14; 8196 union 8197 { 8198 //!< DWORD 15 8199 struct 8200 { 8201 uint32_t IntermediateBufferMaxSize ; //!< Intermediate Buffer Max Size 8202 }; 8203 uint32_t Value; 8204 } DW15; 8205 union 8206 { 8207 //!< DWORD 16 8208 struct 8209 { 8210 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8211 uint32_t FinalFrameBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Final Frame Base Addr 8212 }; 8213 uint32_t Value; 8214 } DW16; 8215 union 8216 { 8217 //!< DWORD 17 8218 struct 8219 { 8220 uint32_t FinalFrameBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Final Frame Base Addr - Upper Range 8221 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8222 }; 8223 uint32_t Value; 8224 } DW17; 8225 union 8226 { 8227 //!< DWORD 18 8228 struct 8229 { 8230 uint32_t FinalFrameBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8231 uint32_t Reserved578 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8232 uint32_t FinalFrameBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8233 uint32_t FinalFrameBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8234 uint32_t FinalFrameBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< FINAL_FRAME_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8235 uint32_t Reserved585 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8236 }; 8237 uint32_t Value; 8238 } DW18; 8239 union 8240 { 8241 //!< DWORD 19 8242 struct 8243 { 8244 uint32_t Finalframebyteoffset : __CODEGEN_BITFIELD( 0, 5) ; //!< FinalFrameByteOffset 8245 uint32_t Reserved614 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 8246 }; 8247 uint32_t Value; 8248 } DW19; 8249 union 8250 { 8251 //!< DWORD 20 8252 struct 8253 { 8254 uint32_t StreamoutBaseAddrCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8255 uint32_t StreamoutBaseAddrGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Streamout Base Addr - Graphics Data Type (GFDT) 8256 uint32_t Reserved643 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8257 uint32_t StreamoutBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8258 uint32_t StreamoutBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Streamout Base Addr 8259 }; 8260 uint32_t Value; 8261 } DW20; 8262 union 8263 { 8264 //!< DWORD 21 8265 struct 8266 { 8267 uint32_t StreamoutBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Streamout Base Addr - Upper Range 8268 uint32_t Reserved688 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8269 }; 8270 uint32_t Value; 8271 } DW21; 8272 union 8273 { 8274 //!< DWORD 22 8275 struct 8276 { 8277 uint32_t StreamoutBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8278 uint32_t Reserved706 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8279 uint32_t StreamoutBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8280 uint32_t StreamoutBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8281 uint32_t StreamoutBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8282 uint32_t Reserved713 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8283 }; 8284 uint32_t Value; 8285 } DW22; 8286 union 8287 { 8288 //!< DWORD 23 8289 struct 8290 { 8291 uint32_t CoeffProbsStreaminSurfaceCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8292 uint32_t CoeffProbsStreaminSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Coeff Probs StreamIn Surface - Graphics Data Type (GFDT) 8293 uint32_t Reserved739 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8294 uint32_t CoeffProbsStreaminSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8295 uint32_t CoeffProbsStreaminSurface : __CODEGEN_BITFIELD( 6, 31) ; //!< Coeff Probs StreamIn Surface 8296 }; 8297 uint32_t Value; 8298 } DW23; 8299 union 8300 { 8301 //!< DWORD 24 8302 struct 8303 { 8304 uint32_t CoeffProbsStreaminSurfaceUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Coeff Probs StreamIn Surface - Upper Range 8305 uint32_t Reserved784 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8306 }; 8307 uint32_t Value; 8308 } DW24; 8309 union 8310 { 8311 //!< DWORD 25 8312 struct 8313 { 8314 uint32_t CoeffProbsStreaminSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8315 uint32_t Reserved802 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8316 uint32_t CoeffProbsStreaminSurfaceTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8317 uint32_t CoeffProbsStreaminSurfaceLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8318 uint32_t CoeffProbsStreaminSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL 8319 uint32_t Reserved809 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8320 }; 8321 uint32_t Value; 8322 } DW25; 8323 union 8324 { 8325 //!< DWORD 26 8326 struct 8327 { 8328 uint32_t TokenStatisticsSurfaceCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8329 uint32_t TokenStatisticsSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Surface - Graphics Data Type (GFDT) 8330 uint32_t Reserved835 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8331 uint32_t FrameHeaderBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8332 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 6, 31) ; //!< Token Statistics Surface 8333 }; 8334 uint32_t Value; 8335 } DW26; 8336 union 8337 { 8338 //!< DWORD 27 8339 struct 8340 { 8341 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 0, 15) ; //!< Token Statistics Surface 8342 uint32_t Reserved880 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8343 }; 8344 uint32_t Value; 8345 } DW27; 8346 union 8347 { 8348 //!< DWORD 28 8349 struct 8350 { 8351 uint32_t TokenStatisticsSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8352 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Surface 8353 uint32_t TokenStatisticsSurfaceTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8354 uint32_t MemoryTypeLlcEllcCacheabilityControlLellcccForCoeffprobsStreaminSurface : __CODEGEN_BITFIELD( 5, 6) ; //!< MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8355 uint32_t TokenStatisticsSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8356 uint32_t Reserved905 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8357 }; 8358 uint32_t Value; 8359 } DW28; 8360 union 8361 { 8362 //!< DWORD 29..30 8363 struct 8364 { 8365 uint64_t MpcRowstoreSurfaceCacheabilityControl : __CODEGEN_BITFIELD(0, 1); //!< MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8366 uint64_t MpcRowstoreSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD(2, 2); //!< MPC RowStore Surface Graphics Data Type (GFDT) 8367 uint64_t Reserved931 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 8368 uint64_t MpcRowstoreBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD(4, 5); //!< MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8369 uint64_t MpcRowstoreSurfaceAddressLow : __CODEGEN_BITFIELD(6, 63); //!< MPC RowStore Surface Address Low 8370 }; 8371 uint32_t Value[2]; 8372 } DW29_30; 8373 union 8374 { 8375 //!< DWORD 31 8376 struct 8377 { 8378 uint32_t MpcRowstoreSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8379 uint32_t MpcRowstoreSurface : __CODEGEN_BITFIELD( 2, 2) ; //!< MPC RowStore Surface 8380 uint32_t MpcRowstoreTargetCache : __CODEGEN_BITFIELD( 3, 4) ; //!< MPC_ROWSTORE__TARGET_CACHE 8381 uint32_t MpcRowstoreMemoryTypeLlcEllcCacheabilityControl : __CODEGEN_BITFIELD( 5, 6) ; //!< MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8382 uint32_t MpcRowstoreArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8383 uint32_t Reserved1001 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8384 }; 8385 uint32_t Value; 8386 } DW31; 8387 8388 //! \name Local enumerations 8389 8390 enum SUB_OPCODE_B 8391 { 8392 SUB_OPCODE_B_MFXVP8BSPBUFBASEADDRSTATE = 3, //!< No additional details 8393 }; 8394 8395 enum SUB_OPCODE_A 8396 { 8397 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 8398 }; 8399 8400 enum MEDIA_COMMAND_OPCODE 8401 { 8402 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 8403 }; 8404 8405 enum PIPELINE 8406 { 8407 PIPELINE_VIDEOCODEC = 2, //!< No additional details 8408 }; 8409 8410 enum COMMAND_TYPE 8411 { 8412 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 8413 }; 8414 8415 //! \brief FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8416 //! \details 8417 //! This field allows the selection of AGE parameter for a given surface in 8418 //! LLC or eLLC. . 8419 //! If a particular allocation is done at youngest age ("3") it tends 8420 //! to stay longer in the cache as compared to older age allocations ("2", 8421 //! "1", or "0"). 8422 //! This option is given to driver to be able to decide which surfaces 8423 //! are more likely to generate HITs, hence need to be replaced least often 8424 //! in caches. 8425 enum FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8426 { 8427 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8428 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8429 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8430 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8431 }; 8432 8433 //! \brief FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8434 //! \details 8435 //! This field allows the choice of LLC vs eLLC for caching 8436 enum FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8437 { 8438 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8439 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8440 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8441 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8442 }; 8443 8444 //! \brief FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8445 //! \details 8446 //! This is the field used in GT interface block to determine what type of 8447 //! access need to be generated to uncore. 8448 //! For the cases where the LeLLCCC is set, cacheable transaction are 8449 //! generated to enable LLC usage for particular stream. 8450 enum FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8451 { 8452 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8453 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8454 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8455 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8456 }; 8457 8458 //! \brief FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8459 //! \details 8460 //! This field controls the priority of arbitration used in the GAC/GAM 8461 //! pipeline for this surface. 8462 enum FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8463 { 8464 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8465 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8466 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8467 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8468 }; 8469 8470 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8471 //! \details 8472 //! This field allows the selection of AGE parameter for a given surface in 8473 //! LLC or eLLC. . 8474 //! If a particular allocation is done at youngest age ("3") it tends 8475 //! to stay longer in the cache as compared to older age allocations ("2", 8476 //! "1", or "0"). 8477 //! This option is given to driver to be able to decide which surfaces 8478 //! are more likely to generate HITs, hence need to be replaced least often 8479 //! in caches. 8480 enum INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8481 { 8482 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8483 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8484 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8485 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8486 }; 8487 8488 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8489 //! \details 8490 //! This field allows the choice of LLC vs. eLLC for caching 8491 enum INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8492 { 8493 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8494 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8495 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8496 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8497 }; 8498 8499 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8500 //! \details 8501 //! This is the field used in GT interface block to determine what type of 8502 //! access need to be generated to uncore. 8503 //! For the cases where the LeLLCCC is set, cacheable transaction are 8504 //! generated to enable LLC usage for particular stream. 8505 enum INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8506 { 8507 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8508 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8509 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8510 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8511 }; 8512 8513 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8514 //! \details 8515 //! This field controls the priority of arbitration used in the GAC/GAM 8516 //! pipeline for this surface. 8517 enum INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8518 { 8519 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8520 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8521 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8522 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8523 }; 8524 8525 //! \brief FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8526 //! \details 8527 //! This field allows the selection of AGE parameter for a given surface in 8528 //! LLC or eLLC. . 8529 //! If a particular allocation is done at youngest age ("3") it tends 8530 //! to stay longer in the cache as compared to older age allocations ("2", 8531 //! "1", or "0"). 8532 //! This option is given to driver to be able to decide which surfaces 8533 //! are more likely to generate HITs, hence need to be replaced least often 8534 //! in caches. 8535 enum FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8536 { 8537 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8538 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8539 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8540 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8541 }; 8542 8543 //! \brief FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8544 //! \details 8545 //! This field allows the choice of LLC vs eLLC for caching 8546 enum FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8547 { 8548 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8549 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8550 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8551 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8552 }; 8553 8554 //! \brief FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8555 //! \details 8556 //! This is the field used in GT interface block to determine what type of 8557 //! access need to be generated to uncore. 8558 //! For the cases where the LeLLCCC is set, cacheable transaction are 8559 //! generated to enable LLC usage for particular stream. 8560 enum FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8561 { 8562 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8563 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8564 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8565 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8566 }; 8567 8568 enum FINAL_FRAME_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8569 { 8570 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8571 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8572 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8573 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8574 }; 8575 8576 //! \brief STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8577 //! \details 8578 //! This field controls cacheability in the mid-level cache (MLC) and 8579 //! last-level cache (LLC) 8580 enum STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8581 { 8582 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8583 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8584 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8585 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8586 }; 8587 8588 //! \brief STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8589 //! \details 8590 //! This field controls the priority of arbitration used in the GAC/GAM 8591 //! pipeline for this surface. 8592 enum STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8593 { 8594 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8595 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8596 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8597 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8598 }; 8599 8600 //! \brief STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8601 //! \details 8602 //! This field allows the selection of AGE parameter for a given surface in 8603 //! LLC or eLLC. . 8604 //! If a particular allocation is done at youngest age ("3") it tends 8605 //! to stay longer in the cache as compared to older age allocations ("2", 8606 //! "1", or "0"). 8607 //! This option is given to driver to be able to decide which surfaces 8608 //! are more likely to generate HITs, hence need to be replaced least often 8609 //! in caches. 8610 enum STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8611 { 8612 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8613 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8614 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8615 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8616 }; 8617 8618 //! \brief STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8619 //! \details 8620 //! This field allows the choice of LLC vs eLLC for caching 8621 enum STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8622 { 8623 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8624 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8625 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8626 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8627 }; 8628 8629 //! \brief STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8630 //! \details 8631 //! This is the field used in GT interface block to determine what type of 8632 //! access need to be generated to uncore. 8633 //! For the cases where the LeLLCCC is set, cacheable transaction are 8634 //! generated to enable LLC usage for particular stream. 8635 enum STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8636 { 8637 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8638 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8639 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8640 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8641 }; 8642 8643 //! \brief COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8644 //! \details 8645 //! This field controls cacheability in the mid-level cache (MLC) and 8646 //! last-level cache (LLC) 8647 enum COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8648 { 8649 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8650 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8651 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8652 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8653 }; 8654 8655 //! \brief COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8656 //! \details 8657 //! This field controls the priority of arbitration used in the GAC/GAM 8658 //! pipeline for this surface. 8659 enum COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8660 { 8661 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8662 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8663 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8664 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8665 }; 8666 8667 //! \brief COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8668 //! \details 8669 //! This field allows the selection of AGE parameter for a given surface in 8670 //! LLC or eLLC. . 8671 //! If a particular allocation is done at youngest age ("3") it tends 8672 //! to stay longer in the cache as compared to older age allocations ("2", 8673 //! "1", or "0"). 8674 //! This option is given to driver to be able to decide which surfaces 8675 //! are more likely to generate HITs, hence need to be replaced least often 8676 //! in caches. 8677 enum COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8678 { 8679 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8680 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8681 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8682 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8683 }; 8684 8685 //! \brief COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8686 //! \details 8687 //! This field allows the choice of LLC vs eLLC for caching 8688 enum COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8689 { 8690 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8691 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8692 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8693 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8694 }; 8695 8696 //! \brief COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8697 //! \details 8698 //! This is the field used in GT interface block to determine what type of 8699 //! access need to be generated to uncore. 8700 //! For the cases where the LeLLCCC is set, cacheable transaction are 8701 //! generated to enable LLC usage for particular stream. 8702 enum COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8703 { 8704 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8705 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8706 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8707 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8708 }; 8709 8710 //! \brief TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8711 //! \details 8712 //! This field controls cacheability in the mid-level cache (MLC) and 8713 //! last-level cache (LLC). 8714 enum TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8715 { 8716 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8717 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8718 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8719 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8720 }; 8721 8722 //! \brief TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8723 //! \details 8724 //! This field allows the selection of AGE parameter for a given surface in 8725 //! LLC or eLLC. . If a particular allocation is done at youngest age ("3") 8726 //! it tends to stay longer in the cache as compared to older age 8727 //! allocations ("2", "1", or "0"). 8728 //! This option is given to driver to be able to decide which surfaces 8729 //! are more likely to generate HITs, hence need to be replaced least often 8730 //! in caches. 8731 enum TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8732 { 8733 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 0, //!< No additional details 8734 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 1, //!< No additional details 8735 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 2, //!< No additional details 8736 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 3, //!< No additional details 8737 }; 8738 8739 //! \brief TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8740 //! \details 8741 //! This field allows the choice of LLC vs eLLC for caching. 8742 enum TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8743 { 8744 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGTBDW = 0, //!< No additional details 8745 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8746 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8747 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8748 }; 8749 8750 //! \brief MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8751 //! \details 8752 //! This is the field used in GT interface block to determine what type of 8753 //! access need to be generated to uncore. 8754 //! For the cases where the LeLLCCC is set, cacheable transaction are 8755 //! generated to enable LLC usage for particular stream. 8756 enum MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8757 { 8758 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_USECACHEABILITYCONTROLSFROMPAGETABLEUCWITHFENCEIFCOHERENTCYCLE = 0, //!< No additional details 8759 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_UC = 1, //!< Uncacheable - non-cacheable 8760 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_WT = 2, //!< Writethrough 8761 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_WB = 3, //!< Writeback 8762 }; 8763 8764 //! \brief TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8765 //! \details 8766 //! This field controls the priority of arbitration used in the GAC/GAM 8767 //! pipeline for this surface. 8768 enum TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8769 { 8770 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8771 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8772 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8773 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8774 }; 8775 8776 //! \brief MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8777 //! \details 8778 //! <b>This field controls cacheability in the mid-level cache (MLC) and 8779 //! last-level cache (LLC).</b> 8780 enum MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8781 { 8782 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8783 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8784 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8785 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8786 }; 8787 8788 //! \brief MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8789 //! \details 8790 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8791 //! pipeline for this surface.</b> 8792 enum MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8793 { 8794 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8795 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8796 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8797 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8798 }; 8799 8800 //! \brief MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8801 //! \details 8802 //! <b>This field allows the selection of AGE parameter for a given surface 8803 //! in LLC or eLLC. . If a particular allocation is done at youngest age 8804 //! ("3") it tends to stay longer in the cache as compared to older age 8805 //! allocations ("2", "1", or "0"). 8806 //! This option is given to driver to be able to decide which surfaces 8807 //! are more likely to generate HITs, hence need to be replaced least often 8808 //! in caches.</b> 8809 enum MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8810 { 8811 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 0, //!< No additional details 8812 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 1, //!< No additional details 8813 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 2, //!< No additional details 8814 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 3, //!< No additional details 8815 }; 8816 8817 //! \brief MPC_ROWSTORE__TARGET_CACHE 8818 //! \details 8819 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8820 //! pipeline for this surface.</b> 8821 enum MPC_ROWSTORE__TARGET_CACHE 8822 { 8823 MPC_ROWSTORE_TARGET_CACHE_ELLCONLY = 0, //!< No additional details 8824 MPC_ROWSTORE_TARGET_CACHE_LLCONLY = 1, //!< No additional details 8825 MPC_ROWSTORE_TARGET_CACHE_LLCELLCALLOWED = 2, //!< No additional details 8826 MPC_ROWSTORE_TARGET_CACHE_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8827 }; 8828 8829 //! \brief MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8830 //! \details 8831 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8832 //! pipeline for this surface.</b> 8833 enum MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8834 { 8835 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_USECACHEABILITYCONTROLSFROMPAGETABLEUCWITHFENCEIFCOHERENTCYCLE = 0, //!< No additional details 8836 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_UC = 1, //!< Uncacheable - non-cacheable 8837 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_WT = 2, //!< Writethrough 8838 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_WB = 3, //!< Writeback 8839 }; 8840 8841 //! \brief MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8842 //! \details 8843 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8844 //! pipeline for this surface.</b> 8845 enum MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8846 { 8847 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8848 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8849 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8850 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8851 }; 8852 8853 //! \name Initializations 8854 8855 //! \brief Explicit member initialization function 8856 MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD(); 8857 8858 static const size_t dwSize = 32; 8859 static const size_t byteSize = 128; 8860 }; 8861 8862 //! 8863 //! \brief MFD_VP8_BSD_OBJECT 8864 //! \details 8865 //! The MFD_VP8_BSD_OBJECT command is the only primitive command for the VP8 8866 //! Decoding Pipeline. The Partitions of the bitstream is loaded as indirect 8867 //! data object. Before issuing a MFD_VP8_BSD_OBJECT command, all VP8 frame 8868 //! level states of the MFD Engine need to be valid. Therefore the commands 8869 //! used to set these states need to have been issued prior to the issue of 8870 //! a MFD_VP8_BSD_OBJECT command. Context switch interrupt is not supported 8871 //! by this command. 8872 //! 8873 struct MFD_VP8_BSD_OBJECT_CMD 8874 { 8875 union 8876 { 8877 //!< DWORD 0 8878 struct 8879 { 8880 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 8881 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 8882 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 8883 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 8884 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 8885 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 8886 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 8887 }; 8888 uint32_t Value; 8889 } DW0; 8890 union 8891 { 8892 //!< DWORD 1 8893 struct 8894 { 8895 uint32_t Partition0FirstmbbitoffsetFromFrameHeader : __CODEGEN_BITFIELD( 0, 2) ; //!< Partition0 FirstMBBitOffset from Frame Header 8896 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8897 uint32_t CodedNumOfCoeffTokenPartitions : __CODEGEN_BITFIELD( 4, 5) ; //!< Coded Num of Coeff Token Partitions 8898 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 8899 uint32_t Partition0CpbacEntropyRange : __CODEGEN_BITFIELD( 8, 15) ; //!< Partition0 CPBAC Entropy Range 8900 uint32_t Partition0CpbacEntropyCount : __CODEGEN_BITFIELD(16, 20) ; //!< Partition0 CPBAC Entropy Count 8901 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 8902 }; 8903 uint32_t Value; 8904 } DW1; 8905 union 8906 { 8907 //!< DWORD 2 8908 struct 8909 { 8910 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 23) ; //!< Reserved 8911 uint32_t Partition0CpbacEntropyValue : __CODEGEN_BITFIELD(24, 31) ; //!< Partition0 CPBAC Entropy Value 8912 }; 8913 uint32_t Value; 8914 } DW2; 8915 union 8916 { 8917 //!< DWORD 3 8918 struct 8919 { 8920 uint32_t IndirectPartition0DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition0 Data Length 8921 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8922 }; 8923 uint32_t Value; 8924 } DW3; 8925 union 8926 { 8927 //!< DWORD 4 8928 struct 8929 { 8930 uint32_t IndirectPartition0DataStartOffset ; //!< Indirect Partition0 Data Start Offset 8931 }; 8932 uint32_t Value; 8933 } DW4; 8934 union 8935 { 8936 //!< DWORD 5 8937 struct 8938 { 8939 uint32_t IndirectPartition1DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition1 Data Length 8940 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8941 }; 8942 uint32_t Value; 8943 } DW5; 8944 union 8945 { 8946 //!< DWORD 6 8947 struct 8948 { 8949 uint32_t IndirectPartition1DataStartOffset ; //!< Indirect Partition1 Data Start Offset 8950 }; 8951 uint32_t Value; 8952 } DW6; 8953 union 8954 { 8955 //!< DWORD 7 8956 struct 8957 { 8958 uint32_t IndirectPartition2DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition2 Data Length 8959 uint32_t Reserved248 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8960 }; 8961 uint32_t Value; 8962 } DW7; 8963 union 8964 { 8965 //!< DWORD 8 8966 struct 8967 { 8968 uint32_t IndirectPartition2DataStartOffset ; //!< Indirect Partition2 Data Start Offset 8969 }; 8970 uint32_t Value; 8971 } DW8; 8972 union 8973 { 8974 //!< DWORD 9 8975 struct 8976 { 8977 uint32_t IndirectPartition3DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition3 Data Length 8978 uint32_t Reserved312 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8979 }; 8980 uint32_t Value; 8981 } DW9; 8982 union 8983 { 8984 //!< DWORD 10 8985 struct 8986 { 8987 uint32_t IndirectPartition3DataStartOffset ; //!< Indirect Partition3 Data Start Offset 8988 }; 8989 uint32_t Value; 8990 } DW10; 8991 union 8992 { 8993 //!< DWORD 11 8994 struct 8995 { 8996 uint32_t IndirectPartition4DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition4 Data Length 8997 uint32_t Reserved376 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8998 }; 8999 uint32_t Value; 9000 } DW11; 9001 union 9002 { 9003 //!< DWORD 12 9004 struct 9005 { 9006 uint32_t IndirectPartition4DataStartOffset ; //!< Indirect Partition4 Data Start Offset 9007 }; 9008 uint32_t Value; 9009 } DW12; 9010 union 9011 { 9012 //!< DWORD 13 9013 struct 9014 { 9015 uint32_t IndirectPartition5DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition5 Data Length 9016 uint32_t Reserved440 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9017 }; 9018 uint32_t Value; 9019 } DW13; 9020 union 9021 { 9022 //!< DWORD 14 9023 struct 9024 { 9025 uint32_t IndirectPartition5DataStartOffset ; //!< Indirect Partition5 Data Start Offset 9026 }; 9027 uint32_t Value; 9028 } DW14; 9029 union 9030 { 9031 //!< DWORD 15 9032 struct 9033 { 9034 uint32_t IndirectPartition6DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition6 Data Length 9035 uint32_t Reserved504 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9036 }; 9037 uint32_t Value; 9038 } DW15; 9039 union 9040 { 9041 //!< DWORD 16 9042 struct 9043 { 9044 uint32_t IndirectPartition6DataStartOffset ; //!< Indirect Partition6 Data Start Offset 9045 }; 9046 uint32_t Value; 9047 } DW16; 9048 union 9049 { 9050 //!< DWORD 17 9051 struct 9052 { 9053 uint32_t IndirectPartition7DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition7 Data Length 9054 uint32_t Reserved568 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9055 }; 9056 uint32_t Value; 9057 } DW17; 9058 union 9059 { 9060 //!< DWORD 18 9061 struct 9062 { 9063 uint32_t IndirectPartition7DataStartOffset ; //!< Indirect Partition7 Data Start Offset 9064 }; 9065 uint32_t Value; 9066 } DW18; 9067 union 9068 { 9069 //!< DWORD 19 9070 struct 9071 { 9072 uint32_t IndirectPartition8DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition8 Data Length 9073 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9074 }; 9075 uint32_t Value; 9076 } DW19; 9077 union 9078 { 9079 //!< DWORD 20 9080 struct 9081 { 9082 uint32_t IndirectPartition8DataStartOffset ; //!< Indirect Partition8 Data Start Offset 9083 }; 9084 uint32_t Value; 9085 } DW20; 9086 union 9087 { 9088 //!< DWORD 21 9089 struct 9090 { 9091 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 9092 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD( 8, 8) ; //!< MB_HEADER_ERROR_HANDLING 9093 uint32_t Reserved681 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 9094 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10) ; //!< ENTROPY_ERROR_HANDLING 9095 uint32_t Reserved683 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 9096 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 9097 uint32_t Reserved685 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 9098 uint32_t BsdprematurecompleteErrorHandling : __CODEGEN_BITFIELD(14, 14) ; //!< BSDPREMATURECOMPLETE_ERROR_HANDLING 9099 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9100 uint32_t ConcealPicIdConcealmentPictureId : __CODEGEN_BITFIELD(16, 17) ; //!< Conceal_Pic_Id (Concealment Picture ID) 9101 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 9102 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31) ; //!< CONCEALMENT_METHOD 9103 }; 9104 uint32_t Value; 9105 } DW21; 9106 9107 //! \name Local enumerations 9108 9109 enum SUBOPCODEB 9110 { 9111 SUBOPCODEB_UNNAMED8 = 8, //!< No additional details 9112 }; 9113 9114 enum SUBOPCODEA 9115 { 9116 SUBOPCODEA_UNNAMED1 = 1, //!< No additional details 9117 }; 9118 9119 enum MEDIA_COMMAND_OPCODE 9120 { 9121 MEDIA_COMMAND_OPCODE_VP8DEC = 4, //!< No additional details 9122 }; 9123 9124 enum PIPELINE 9125 { 9126 PIPELINE_MFDVP8BSDOBJECT = 2, //!< No additional details 9127 }; 9128 9129 enum COMMAND_TYPE 9130 { 9131 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9132 }; 9133 9134 enum MB_HEADER_ERROR_HANDLING 9135 { 9136 MB_HEADER_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9137 MB_HEADER_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9138 }; 9139 9140 enum ENTROPY_ERROR_HANDLING 9141 { 9142 ENTROPY_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9143 ENTROPY_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9144 }; 9145 9146 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 9147 { 9148 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9149 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9150 }; 9151 9152 //! \brief BSDPREMATURECOMPLETE_ERROR_HANDLING 9153 //! \details 9154 //! It occurs in situation where the decode is completed but there are still 9155 //! data in the bitstream. 9156 enum BSDPREMATURECOMPLETE_ERROR_HANDLING 9157 { 9158 BSDPREMATURECOMPLETE_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9159 BSDPREMATURECOMPLETE_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9160 }; 9161 9162 //! \brief CONCEALMENT_METHOD 9163 //! \details 9164 //! This field specifies the method used for concealment when error is 9165 //! detected. 9166 enum CONCEALMENT_METHOD 9167 { 9168 CONCEALMENT_METHOD_INTRA16X16PREDICTION = 0, //!< A copy from the current picture is performed using Intra 16x16 Prediction method. 9169 CONCEALMENT_METHOD_INTERPCOPY = 1, //!< A copy from collocated macroblock location is performed from the concealment reference indicated by the ConCeal_Pic_Id field. 9170 }; 9171 9172 //! \name Initializations 9173 9174 //! \brief Explicit member initialization function 9175 MFD_VP8_BSD_OBJECT_CMD(); 9176 9177 static const size_t dwSize = 22; 9178 static const size_t byteSize = 88; 9179 }; 9180 9181 //! 9182 //! \brief MFX_VP8_PIC_STATE 9183 //! \details 9184 //! This must be the very first command to issue after the surface state, 9185 //! the pipe select and base address setting commands and must be issued 9186 //! before MFX_VP8_IMG_STATE. 9187 //! 9188 struct MFX_VP8_PIC_STATE_CMD 9189 { 9190 union 9191 { 9192 //!< DWORD 0 9193 struct 9194 { 9195 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 9196 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 9197 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 9198 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 9199 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 9200 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 9201 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 9202 }; 9203 uint32_t Value; 9204 } DW0; 9205 union 9206 { 9207 //!< DWORD 1 9208 struct 9209 { 9210 uint32_t FrameWidthMinus1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Width Minus 1 9211 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 9212 uint32_t FrameHeightMinus1 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Height Minus 1 9213 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9214 }; 9215 uint32_t Value; 9216 } DW1; 9217 union 9218 { 9219 //!< DWORD 2 9220 struct 9221 { 9222 uint32_t McFilterSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< MC_FILTER_SELECT, Decoder / Encoder 9223 uint32_t ChromaFullPixelMcFilterMode : __CODEGEN_BITFIELD( 1, 1) ; //!< CHROMA_FULL_PIXEL_MC_FILTER_MODE, Decoder / Encoder 9224 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved, Decoder / Encoder 9225 uint32_t Dblkfiltertype : __CODEGEN_BITFIELD( 4, 4) ; //!< DBLKFILTERTYPE, Decoder / Encoder 9226 uint32_t Skeyframeflag : __CODEGEN_BITFIELD( 5, 5) ; //!< SKEYFRAMEFLAG, Decoder / Encoder 9227 uint32_t SegmentationIdStreamoutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< SEGMENTATION_ID_STREAMOUT_ENABLE, Decoder Only 9228 uint32_t SegmentationIdStreaminEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< SEGMENTATION_ID_STREAMIN_ENABLE, Decoder Only 9229 uint32_t SegmentEnableFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< SEGMENT_ENABLE_FLAG, Decoder / Encoder 9230 uint32_t UpdateMbsegmentMapFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< UPDATE_MBSEGMENT_MAP_FLAG, Decoder / Encoder 9231 uint32_t MbNocoeffSkipflag : __CODEGEN_BITFIELD(10, 10) ; //!< MB_NOCOEFF_SKIPFLAG, Decoder / Encoder 9232 uint32_t ModeReferenceLoopFilterDeltaEnabled : __CODEGEN_BITFIELD(11, 11) ; //!< MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED, Decoder / Encoder 9233 uint32_t GoldenRefPictureMvSignbiasFlag : __CODEGEN_BITFIELD(12, 12) ; //!< Golden Ref Picture MV SignBias Flag, Decoder / Encoder 9234 uint32_t AlternateRefPicMvSignbiasFlag : __CODEGEN_BITFIELD(13, 13) ; //!< Alternate Ref Pic MV SignBias Flag, Decoder / Encoder 9235 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved, Decoder / Encoder 9236 uint32_t DeblockSharpnessLevel : __CODEGEN_BITFIELD(16, 18) ; //!< Deblock Sharpness Level, Decoder / Encoder 9237 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved, Decoder / Encoder 9238 uint32_t Log2NumOfPartition : __CODEGEN_BITFIELD(24, 25) ; //!< LOG2_NUM_OF_PARTITION, Decoder / Encoder 9239 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 9240 }; 9241 uint32_t Value; 9242 } DW2; 9243 union 9244 { 9245 //!< DWORD 3 9246 struct 9247 { 9248 uint32_t DblkfilterlevelForSegment0 : __CODEGEN_BITFIELD( 0, 5) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT0 9249 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 9250 uint32_t DblkfilterlevelForSegment1 : __CODEGEN_BITFIELD( 8, 13) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT1 9251 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 9252 uint32_t DblkfilterlevelForSegment2 : __CODEGEN_BITFIELD(16, 21) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT2 9253 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 9254 uint32_t DblkfilterlevelForSegment3 : __CODEGEN_BITFIELD(24, 29) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT3 9255 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 9256 }; 9257 uint32_t Value; 9258 } DW3; 9259 union 9260 { 9261 //!< DWORD 4 9262 struct 9263 { 9264 uint32_t QuantizerValue0Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType0=Y1DC], Decoder Only 9265 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9266 uint32_t QuantizerValue0Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType1=Y1AC], Decoder Only 9267 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9268 } dec; 9269 struct 9270 { 9271 uint32_t Seg0Qindex : __CODEGEN_BITFIELD( 0, 6) ; //!< Seg 0 Qindex, Encoder Only 9272 uint32_t Reserved135 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved, Encoder Only 9273 uint32_t Seg1Qindex : __CODEGEN_BITFIELD( 8, 14) ; //!< Seg 1 Qindex, Encoder Only 9274 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved, Encoder Only 9275 uint32_t Seg2Qindex : __CODEGEN_BITFIELD(16, 22) ; //!< Seg 2 Qindex, Encoder Only 9276 uint32_t Reserved151 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved, Encoder Only 9277 uint32_t Seg3Qindex : __CODEGEN_BITFIELD(24, 30) ; //!< Seg 3 Qindex, Encoder Only 9278 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9279 } enc; 9280 uint32_t Value; 9281 } DW4; 9282 union 9283 { 9284 //!< DWORD 5 9285 struct 9286 { 9287 uint32_t QuantizerValue0Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType2=UVDC], Decoder Only 9288 uint32_t Reserved169 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9289 uint32_t QuantizerValue0Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType3=UVAC], Decoder Only 9290 uint32_t Reserved185 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9291 } dec; 9292 struct 9293 { 9294 uint32_t Y2DcQindexDelta : __CODEGEN_BITFIELD( 0, 3) ; //!< Y2dc Qindex Delta, Encoder Only 9295 uint32_t Y2AcQindexDeltaSign : __CODEGEN_BITFIELD( 4, 4) ; //!< Y2ac Qindex Delta Sign , Encoder Only 9296 uint32_t Reserved165 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved, Encoder Only 9297 uint32_t Y2AcQindexDelta : __CODEGEN_BITFIELD( 8, 11) ; //!< Y2ac Qindex Delta , Encoder Only 9298 uint32_t Y2AcQindexSign : __CODEGEN_BITFIELD(12, 12) ; //!< Y2ac Qindex Sign, Encoder Only 9299 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, Encoder Only 9300 uint32_t UvdcQindexDelta : __CODEGEN_BITFIELD(16, 19) ; //!< UVdc Qindex Delta, Encoder Only 9301 uint32_t UvdcQindexDeltaSign : __CODEGEN_BITFIELD(20, 20) ; //!< UVdc Qindex Delta Sign, Encoder Only 9302 uint32_t Reserved181 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved, Encoder Only 9303 uint32_t UvacQindexdelta : __CODEGEN_BITFIELD(24, 27) ; //!< UVac QindexDelta, Encoder Only 9304 uint32_t UvacQindexDeltaSign : __CODEGEN_BITFIELD(28, 28) ; //!< UVac Qindex Delta Sign, Encoder Only 9305 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 9306 } enc; 9307 uint32_t Value; 9308 } DW5; 9309 union 9310 { 9311 //!< DWORD 6 9312 struct 9313 { 9314 uint32_t QuantizerValue0Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType4=Y2DC], Decoder Only 9315 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9316 uint32_t QuantizerValue0Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType5=Y2AC], Decoder Only 9317 uint32_t Reserved217 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9318 } dec; 9319 struct 9320 { 9321 uint32_t Y1DcQindexDelta : __CODEGEN_BITFIELD( 0, 3) ; //!< Y1dc Qindex Delta, Encoder Only 9322 uint32_t Y1DcQindexDeltaSign : __CODEGEN_BITFIELD( 4, 4) ; //!< Y1dc Qindex Delta Sign , Encoder Only 9323 uint32_t Reserved197 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 9324 } enc; 9325 uint32_t Value; 9326 } DW6; 9327 union 9328 { 9329 //!< DWORD 7 9330 struct 9331 { 9332 uint32_t QuantizerValue1Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType0=Y1DC], Decoder Only 9333 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9334 uint32_t QuantizerValue1Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType1=Y1AC], Decoder Only 9335 uint32_t Reserved249 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9336 } dec; 9337 struct 9338 { 9339 uint32_t ClampQindexLow : __CODEGEN_BITFIELD( 0, 6) ; //!< Clamp Qindex Low, Encoder Only 9340 uint32_t Reserved231 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved, Encoder Only 9341 uint32_t ClampQindexHigh : __CODEGEN_BITFIELD( 8, 14) ; //!< Clamp Qindex high, Encoder Only 9342 uint32_t Reserved239 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9343 } enc; 9344 uint32_t Value; 9345 } DW7; 9346 union 9347 { 9348 //!< DWORD 8 9349 struct 9350 { 9351 uint32_t QuantizerValue1Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType2=UVDC], Decoder Only 9352 uint32_t Reserved265 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9353 uint32_t QuantizerValue1Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType3=UVAC], Decoder Only 9354 uint32_t Reserved281 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9355 }; 9356 uint32_t Value; 9357 } DW8; 9358 union 9359 { 9360 //!< DWORD 9 9361 struct 9362 { 9363 uint32_t QuantizerValue1Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType4=Y2DC], Decoder Only 9364 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9365 uint32_t QuantizerValue1Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType5=Y2AC], Decoder Only 9366 uint32_t Reserved313 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9367 }; 9368 uint32_t Value; 9369 } DW9; 9370 union 9371 { 9372 //!< DWORD 10 9373 struct 9374 { 9375 uint32_t QuantizerValue2Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType0=Y1DC], Decoder Only 9376 uint32_t Reserved329 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9377 uint32_t QuantizerValue2Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType1=Y1AC], Decoder Only 9378 uint32_t Reserved345 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9379 }; 9380 uint32_t Value; 9381 } DW10; 9382 union 9383 { 9384 //!< DWORD 11 9385 struct 9386 { 9387 uint32_t QuantizerValue2Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType2=UVDC], Decoder Only 9388 uint32_t Reserved361 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9389 uint32_t QuantizerValue2Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType3=UVAC], Decoder Only 9390 uint32_t Reserved377 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9391 }; 9392 uint32_t Value; 9393 } DW11; 9394 union 9395 { 9396 //!< DWORD 12 9397 struct 9398 { 9399 uint32_t QuantizerValue2Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType4=Y2DC], Decoder Only 9400 uint32_t Reserved393 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9401 uint32_t QuantizerValue2Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType5=Y2AC], Decoder Only 9402 uint32_t Reserved409 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9403 }; 9404 uint32_t Value; 9405 } DW12; 9406 union 9407 { 9408 //!< DWORD 13 9409 struct 9410 { 9411 uint32_t QuantizerValue3Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType0=Y1DC], Decoder Only 9412 uint32_t Reserved425 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9413 uint32_t QuantizerValue3Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType1=Y1AC], Decoder Only 9414 uint32_t Reserved441 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9415 }; 9416 uint32_t Value; 9417 } DW13; 9418 union 9419 { 9420 //!< DWORD 14 9421 struct 9422 { 9423 uint32_t QuantizerValue3Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType2=UVDC], Decoder Only 9424 uint32_t Reserved457 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9425 uint32_t QuantizerValue3Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType3=UVAC], Decoder Only 9426 uint32_t Reserved473 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9427 }; 9428 uint32_t Value; 9429 } DW14; 9430 union 9431 { 9432 //!< DWORD 15 9433 struct 9434 { 9435 uint32_t QuantizerValue3Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType4=Y2DC], Decoder Only 9436 uint32_t Reserved489 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9437 uint32_t QuantizerValue3Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType5=Y2AC], Decoder Only 9438 uint32_t Reserved505 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9439 }; 9440 uint32_t Value; 9441 } DW15; 9442 union 9443 { 9444 //!< DWORD 16 9445 struct 9446 { 9447 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 9448 uint32_t CoeffprobabilityStreaminBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< CoeffProbability StreamIn Base Address, Decoder Only 9449 }; 9450 uint32_t Value; 9451 } DW16; 9452 union 9453 { 9454 //!< DWORD 17 9455 struct 9456 { 9457 uint32_t CoeffprobabilityStreaminAddress : __CODEGEN_BITFIELD( 0, 15) ; //!< CoeffProbability StreamIn Address, Decoder Only 9458 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9459 }; 9460 uint32_t Value; 9461 } DW17; 9462 union 9463 { 9464 //!< DWORD 18 9465 struct 9466 { 9467 uint32_t Reserved576 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 9468 uint32_t CoeffprobabilityStreaminArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL, Decoder Only 9469 uint32_t CoeffprobabilityStreaminMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< CoeffProbability StreamIn - Memory Compression Enable, Decoder Only 9470 uint32_t CoeffprobabilityStreaminMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE, Decoder Only 9471 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved, Decoder Only 9472 uint32_t CoeffprobabilityStreaminTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE, Decoder Only 9473 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9474 }; 9475 uint32_t Value; 9476 } DW18; 9477 union 9478 { 9479 //!< DWORD 19 9480 struct 9481 { 9482 uint32_t Mbsegmentidtreeprobs0 : __CODEGEN_BITFIELD( 0, 7) ; //!< MBSegmentIDTreeProbs[0] 9483 uint32_t Mbsegmentidtreeprobs1 : __CODEGEN_BITFIELD( 8, 15) ; //!< MBSegmentIDTreeProbs[1] 9484 uint32_t Mbsegmentidtreeprobs2 : __CODEGEN_BITFIELD(16, 23) ; //!< MBSegmentIDTreeProbs[2] 9485 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9486 }; 9487 uint32_t Value; 9488 } DW19; 9489 union 9490 { 9491 //!< DWORD 20 9492 struct 9493 { 9494 uint32_t Interpredfromgrefrefprob : __CODEGEN_BITFIELD( 0, 7) ; //!< InterPredFromGRefRefProb 9495 uint32_t Interpredfromlastrefprob : __CODEGEN_BITFIELD( 8, 15) ; //!< InterPredFromLastRefProb 9496 uint32_t Intrambprob : __CODEGEN_BITFIELD(16, 23) ; //!< IntraMBProb 9497 uint32_t Mbnocoeffskipfalseprob : __CODEGEN_BITFIELD(24, 31) ; //!< MBNoCoeffSkipFalseProb 9498 }; 9499 uint32_t Value; 9500 } DW20; 9501 union 9502 { 9503 //!< DWORD 21 9504 struct 9505 { 9506 uint32_t Ymodeprob0 : __CODEGEN_BITFIELD( 0, 7) ; //!< YModeProb[0] 9507 uint32_t Ymodeprob1 : __CODEGEN_BITFIELD( 8, 15) ; //!< YModeProb[1] 9508 uint32_t Ymodeprob2 : __CODEGEN_BITFIELD(16, 23) ; //!< YModeProb[2] 9509 uint32_t Ymodeprob3 : __CODEGEN_BITFIELD(24, 31) ; //!< YModeProb[3] 9510 }; 9511 uint32_t Value; 9512 } DW21; 9513 union 9514 { 9515 //!< DWORD 22 9516 struct 9517 { 9518 uint32_t Uvmodeprob0 : __CODEGEN_BITFIELD( 0, 7) ; //!< UVModeProb[0] 9519 uint32_t Uvmodeprob1 : __CODEGEN_BITFIELD( 8, 15) ; //!< UVModeProb[1] 9520 uint32_t Uvmodeprob2 : __CODEGEN_BITFIELD(16, 23) ; //!< UVModeProb[2] 9521 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9522 }; 9523 uint32_t Value; 9524 } DW22; 9525 union 9526 { 9527 //!< DWORD 23 9528 struct 9529 { 9530 uint32_t Mvupdateprobs00 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][0] 9531 uint32_t Mvupdateprobs01 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][1] 9532 uint32_t Mvupdateprobs02 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][2] 9533 uint32_t Mvupdateprobs03 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][3] 9534 }; 9535 uint32_t Value; 9536 } DW23; 9537 union 9538 { 9539 //!< DWORD 24 9540 struct 9541 { 9542 uint32_t Mvupdateprobs04 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][4] 9543 uint32_t Mvupdateprobs05 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][5] 9544 uint32_t Mvupdateprobs06 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][6] 9545 uint32_t Mvupdateprobs07 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][7] 9546 }; 9547 uint32_t Value; 9548 } DW24; 9549 union 9550 { 9551 //!< DWORD 25 9552 struct 9553 { 9554 uint32_t Mvupdateprobs08 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][8] 9555 uint32_t Mvupdateprobs09 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][9] 9556 uint32_t Mvupdateprobs010 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][10] 9557 uint32_t Mvupdateprobs011 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][11] 9558 }; 9559 uint32_t Value; 9560 } DW25; 9561 union 9562 { 9563 //!< DWORD 26 9564 struct 9565 { 9566 uint32_t Mvupdateprobs012 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][12] 9567 uint32_t Mvupdateprobs013 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][13] 9568 uint32_t Mvupdateprobs014 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][14] 9569 uint32_t Mvupdateprobs015 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][15] 9570 }; 9571 uint32_t Value; 9572 } DW26; 9573 union 9574 { 9575 //!< DWORD 27 9576 struct 9577 { 9578 uint32_t Mvupdateprobs016 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][16] 9579 uint32_t Mvupdateprobs017 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][17] 9580 uint32_t Mvupdateprobs018 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][18] 9581 uint32_t Reserved888 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9582 }; 9583 uint32_t Value; 9584 } DW27; 9585 union 9586 { 9587 //!< DWORD 28 9588 struct 9589 { 9590 uint32_t Mvupdateprobs10 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][0] 9591 uint32_t Mvupdateprobs11 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][1] 9592 uint32_t Mvupdateprobs12 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][2] 9593 uint32_t Mvupdateprobs13 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][3] 9594 }; 9595 uint32_t Value; 9596 } DW28; 9597 union 9598 { 9599 //!< DWORD 29 9600 struct 9601 { 9602 uint32_t Mvupdateprobs14 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][4] 9603 uint32_t Mvupdateprobs15 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][5] 9604 uint32_t Mvupdateprobs16 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][6] 9605 uint32_t Mvupdateprobs17 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][7] 9606 }; 9607 uint32_t Value; 9608 } DW29; 9609 union 9610 { 9611 //!< DWORD 30 9612 struct 9613 { 9614 uint32_t Mvupdateprobs18 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][8] 9615 uint32_t Mvupdateprobs19 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][9] 9616 uint32_t Mvupdateprobs110 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][10] 9617 uint32_t Mvupdateprobs111 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][11] 9618 }; 9619 uint32_t Value; 9620 } DW30; 9621 union 9622 { 9623 //!< DWORD 31 9624 struct 9625 { 9626 uint32_t Mvupdateprobs112 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][12] 9627 uint32_t Mvupdateprobs113 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][13] 9628 uint32_t Mvupdateprobs114 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][14] 9629 uint32_t Mvupdateprobs115 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][15] 9630 }; 9631 uint32_t Value; 9632 } DW31; 9633 union 9634 { 9635 //!< DWORD 32 9636 struct 9637 { 9638 uint32_t Mvupdateprobs116 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][16] 9639 uint32_t Mvupdateprobs117 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][17] 9640 uint32_t Mvupdateprobs118 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][18] 9641 uint32_t Reserved1048 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9642 }; 9643 uint32_t Value; 9644 } DW32; 9645 union 9646 { 9647 //!< DWORD 33 9648 struct 9649 { 9650 uint32_t Reflfdelta0ForIntraFrame : __CODEGEN_BITFIELD( 0, 6) ; //!< RefLFDelta0 (for INTRA FRAME) 9651 uint32_t Reserved1063 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 9652 uint32_t Reflfdelta1ForLastFrame : __CODEGEN_BITFIELD( 8, 14) ; //!< RefLFDelta1 (for LAST FRAME) 9653 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9654 uint32_t Reflfdelta2ForGoldenFrame : __CODEGEN_BITFIELD(16, 22) ; //!< RefLFDelta2 (for GOLDEN FRAME) 9655 uint32_t Reserved1079 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 9656 uint32_t Reflfdelta3ForAltrefFrame : __CODEGEN_BITFIELD(24, 30) ; //!< RefLFDelta3 (for ALTREF FRAME) 9657 uint32_t Reserved1087 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9658 }; 9659 uint32_t Value; 9660 } DW33; 9661 union 9662 { 9663 //!< DWORD 34 9664 struct 9665 { 9666 uint32_t Modelfdelta0ForBPredMode : __CODEGEN_BITFIELD( 0, 6) ; //!< ModeLFDelta0 (for B_PRED mode) 9667 uint32_t Reserved1095 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 9668 uint32_t Modelfdelta1ForZeromvMode : __CODEGEN_BITFIELD( 8, 14) ; //!< ModeLFDelta1(for ZEROMV mode) 9669 uint32_t Reserved1103 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9670 uint32_t Modelfdelta2ForNearestNearAndNewMode : __CODEGEN_BITFIELD(16, 22) ; //!< ModeLFDelta2 (for Nearest, Near and New mode) 9671 uint32_t Reserved1111 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 9672 uint32_t Modelfdelta3ForSplitmvMode : __CODEGEN_BITFIELD(24, 30) ; //!< ModeLFDelta3 (for SPLITMV mode) 9673 uint32_t Reserved1119 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9674 }; 9675 uint32_t Value; 9676 } DW34; 9677 union 9678 { 9679 //!< DWORD 35 9680 struct 9681 { 9682 uint32_t SegmentationIdStreamBaseAddress ; //!< Segmentation ID Stream Base Address 9683 }; 9684 uint32_t Value; 9685 } DW35; 9686 union 9687 { 9688 //!< DWORD 36 9689 struct 9690 { 9691 uint32_t SegmentationIdStreamBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Segmentation ID Stream Base Address [47:32] 9692 uint32_t Reserved1168 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9693 }; 9694 uint32_t Value; 9695 } DW36; 9696 union 9697 { 9698 //!< DWORD 37 9699 struct 9700 { 9701 uint32_t Reserved1184 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 9702 uint32_t CoeffprobabilityStreaminAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< CoeffProbability StreamIn Address - Index to Memory Object Control State (MOCS) Tables 9703 uint32_t SegmentationIdStreamArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9704 uint32_t SegmentationIdStreamMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Segmentation ID Stream - Memory Compression Enable 9705 uint32_t SegmentationIdStreamMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9706 uint32_t Reserved1195 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 9707 uint32_t SegmentationIdStreamTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9708 uint32_t Reserved1199 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9709 }; 9710 uint32_t Value; 9711 } DW37; 9712 9713 //! \name Local enumerations 9714 9715 enum SUB_OPCODE_B 9716 { 9717 SUB_OPCODE_B_MFXVP8PICSTATE = 0, //!< No additional details 9718 }; 9719 9720 enum SUB_OPCODE_A 9721 { 9722 SUB_OPCODE_A_VP8COMMON = 0, //!< No additional details 9723 }; 9724 9725 enum MEDIA_COMMAND_OPCODE 9726 { 9727 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 9728 }; 9729 9730 enum PIPELINE 9731 { 9732 PIPELINE_VIDEOCODEC = 2, //!< No additional details 9733 }; 9734 9735 enum COMMAND_TYPE 9736 { 9737 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9738 }; 9739 9740 //! \brief MC_FILTER_SELECT 9741 //! \details 9742 //! To specify VP8 Profile of operation. 9743 enum MC_FILTER_SELECT 9744 { 9745 MC_FILTER_SELECT_UNNAMED0 = 0, //!< 6-tap filter (regular filter mode) 9746 MC_FILTER_SELECT_UNNAMED1 = 1, //!< 2-tap bilinear filter (simple profile/version mode) 9747 }; 9748 9749 //! \brief CHROMA_FULL_PIXEL_MC_FILTER_MODE 9750 //! \details 9751 //! To specify VP8 Profile of operation. 9752 enum CHROMA_FULL_PIXEL_MC_FILTER_MODE 9753 { 9754 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED0 = 0, //!< Chroma MC filter operates in sub-pixel mode 9755 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED1 = 1, //!< Chroma MC filter only operates in full pixel position, i.e. no sub-pixel interpolation. 9756 }; 9757 9758 //! \brief DBLKFILTERTYPE 9759 //! \details 9760 //! To specify VP8 Profile of operation. 9761 enum DBLKFILTERTYPE 9762 { 9763 DBLKFILTERTYPE_UNNAMED0 = 0, //!< Use a full feature normal deblocking filter 9764 DBLKFILTERTYPE_UNNAMED1 = 1, //!< Use a simple filter for deblocking 9765 }; 9766 9767 enum SKEYFRAMEFLAG 9768 { 9769 SKEYFRAMEFLAG_NON_KEYFRAMEP_FRAME = 0, //!< No additional details 9770 SKEYFRAMEFLAG_KEYFRAMEI_FRAME = 1, //!< No additional details 9771 }; 9772 9773 //! \brief SEGMENTATION_ID_STREAMOUT_ENABLE 9774 //! \details 9775 //! When 0, no output needed. 9776 enum SEGMENTATION_ID_STREAMOUT_ENABLE 9777 { 9778 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTDISABLED = 0, //!< No additional details 9779 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTENABLED = 1, //!< No additional details 9780 }; 9781 9782 //! \brief SEGMENTATION_ID_STREAMIN_ENABLE 9783 //! \details 9784 //! When 0, no input needed. 9785 enum SEGMENTATION_ID_STREAMIN_ENABLE 9786 { 9787 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINDISABLED = 0, //!< No additional details 9788 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINENABLED = 1, //!< No additional details 9789 }; 9790 9791 enum SEGMENT_ENABLE_FLAG 9792 { 9793 SEGMENT_ENABLE_FLAG_UNNAMED0 = 0, //!< Disable Segmentation processing in the current frame 9794 SEGMENT_ENABLE_FLAG_UNNAMED1 = 1, //!< Enable Segmentation processing in the current frame 9795 }; 9796 9797 enum UPDATE_MBSEGMENT_MAP_FLAG 9798 { 9799 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED0 = 0, //!< Disable segmentation update 9800 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED1 = 1, //!< Enable segmentation update, and to enable reading segment_id for each MB. 9801 }; 9802 9803 //! \brief MB_NOCOEFF_SKIPFLAG 9804 //! \details 9805 //! Frame level control if Skip MB (with no non-zero coefficient) is allowed 9806 //! or not. 9807 enum MB_NOCOEFF_SKIPFLAG 9808 { 9809 MB_NOCOEFF_SKIPFLAG_UNNAMED0 = 0, //!< All MBs will have its MB level signaling mb_skip_coeff forced to 0. That is, no skip of coefficient record in the bitstream (even their values are all 0s) 9810 MB_NOCOEFF_SKIPFLAG_UNNAMED1 = 1, //!< Skip MB is enabled in the per MB record. 9811 }; 9812 9813 enum MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED 9814 { 9815 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED0 = 0, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is disabled. 9816 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED1 = 1, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is enabled. 9817 }; 9818 9819 enum LOG2_NUM_OF_PARTITION 9820 { 9821 LOG2_NUM_OF_PARTITION_1TOKENPARTITION = 0, //!< No additional details 9822 LOG2_NUM_OF_PARTITION_2TOKENPARTITION = 1, //!< No additional details 9823 LOG2_NUM_OF_PARTITION_4TOKENPARTITION = 2, //!< No additional details 9824 LOG2_NUM_OF_PARTITION_8TOKENPARTITION = 3, //!< No additional details 9825 }; 9826 9827 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT0 9828 //! \details 9829 //! There are max 4 segments per frame, each segment can have its own 9830 //! deblocking filter level. When segmentation is disabled, only segment 0 9831 //! parameter is used for the entire frame. 9832 enum DBLKFILTERLEVEL_FOR_SEGMENT0 9833 { 9834 DBLKFILTERLEVEL_FOR_SEGMENT0_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9835 }; 9836 9837 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT1 9838 //! \details 9839 //! There are max 4 segments per frame, each segment can have its own 9840 //! deblocking filter level. When segmentation is disabled, only segment 0 9841 //! parameter is used for the entire frame. 9842 enum DBLKFILTERLEVEL_FOR_SEGMENT1 9843 { 9844 DBLKFILTERLEVEL_FOR_SEGMENT1_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9845 }; 9846 9847 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT2 9848 //! \details 9849 //! There are max 4 segments per frame, each segment can have its own 9850 //! deblocking filter level. When segmentation is disabled, only segment 0 9851 //! parameter is used for the entire frame. 9852 enum DBLKFILTERLEVEL_FOR_SEGMENT2 9853 { 9854 DBLKFILTERLEVEL_FOR_SEGMENT2_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9855 }; 9856 9857 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT3 9858 //! \details 9859 //! There are max 4 segments per frame, each segment can have its own 9860 //! deblocking filter level. When segmentation is disabled, only segment 0 9861 //! parameter is used for the entire frame. 9862 enum DBLKFILTERLEVEL_FOR_SEGMENT3 9863 { 9864 DBLKFILTERLEVEL_FOR_SEGMENT3_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9865 }; 9866 9867 //! \brief COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL 9868 //! \details 9869 //! This field controls the priority of arbitration used in the GAC/GAM 9870 //! pipeline for this surface. 9871 enum COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL 9872 { 9873 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9874 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9875 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9876 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9877 }; 9878 9879 //! \brief COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE 9880 //! \details 9881 //! Distinguishes Vertical from Horizontal compression. Please refer to 9882 //! vol1a 9883 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 9884 //! section for more details. 9885 enum COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE 9886 { 9887 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 9888 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 9889 }; 9890 9891 //! \brief COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE 9892 //! \details 9893 //! <b>For Media Surfaces:</b> 9894 //! This field specifies the tiled resource mode. 9895 enum COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE 9896 { 9897 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 9898 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 9899 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 9900 }; 9901 9902 //! \brief SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9903 //! \details 9904 //! This field controls the priority of arbitration used in the GAC/GAM 9905 //! pipeline for this surface. 9906 enum SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9907 { 9908 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9909 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9910 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9911 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9912 }; 9913 9914 //! \brief SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9915 //! \details 9916 //! Distinguishes Vertical from Horizontal compression. Please refer to 9917 //! vol1a 9918 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 9919 //! section for more details. 9920 enum SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9921 { 9922 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 9923 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 9924 }; 9925 9926 //! \brief SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9927 //! \details 9928 //! <b>For Media Surfaces:</b> 9929 //! This field specifies the tiled resource mode. 9930 enum SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9931 { 9932 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 9933 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 9934 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 9935 }; 9936 9937 //! \name Initializations 9938 9939 //! \brief Explicit member initialization function 9940 MFX_VP8_PIC_STATE_CMD(); 9941 9942 static const size_t dwSize = 38; 9943 static const size_t byteSize = 152; 9944 }; 9945 9946 //! 9947 //! \brief MFX_JPEG_HUFF_TABLE_STATE 9948 //! \details 9949 //! This Huffman table commands contains both DC and AC tables for either 9950 //! luma or chroma. Once a Huffman table has been defined for a particular 9951 //! destination, it replaces the previous tables stored in that destination 9952 //! and shall be used in the remaining Scans of the current image. A Huffman 9953 //! table will be sent to H/W only when it is loaded from bitstream. 9954 //! 9955 struct MFX_JPEG_HUFF_TABLE_STATE_CMD 9956 { 9957 union 9958 { 9959 //!< DWORD 0 9960 struct 9961 { 9962 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 9963 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 9964 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 9965 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 9966 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 9967 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 9968 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 9969 }; 9970 uint32_t Value; 9971 } DW0; 9972 union 9973 { 9974 //!< DWORD 1 9975 struct 9976 { 9977 uint32_t Hufftableid1Bit : __CODEGEN_BITFIELD( 0, 0) ; //!< HUFFTABLEID_1_BIT 9978 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 9979 }; 9980 uint32_t Value; 9981 } DW1; 9982 9983 uint32_t DcBits128BitArray[3]; //!< DC_BITS (12 8-bit array) 9984 9985 9986 uint32_t DcHuffval128BitArray[3]; //!< DC_HUFFVAL (12 8-bit array) 9987 9988 9989 uint32_t AcBits168BitArray[4]; //!< AC_BITS (16 8-bit array) 9990 9991 9992 uint32_t AcHuffval1608BitArray[40]; //!< AC_HUFFVAL (160 8-bit array) 9993 9994 union 9995 { 9996 //!< DWORD 52 9997 struct 9998 { 9999 uint32_t AcHuffval28BitArray : __CODEGEN_BITFIELD( 0, 15) ; //!< AC_HUFFVAL(2-8 bit array) 10000 uint32_t Reserved1680 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10001 }; 10002 uint32_t Value; 10003 } DW52; 10004 10005 //! \name Local enumerations 10006 10007 enum SUBOPCODE_B 10008 { 10009 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 10010 }; 10011 10012 enum SUBOPCODE_A 10013 { 10014 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 10015 }; 10016 10017 enum MEDIA_COMMAND_OPCODE 10018 { 10019 MEDIA_COMMAND_OPCODE_JPEGCOMMON = 7, //!< No additional details 10020 }; 10021 10022 enum PIPELINE 10023 { 10024 PIPELINE_MFXMULTIDW = 2, //!< No additional details 10025 }; 10026 10027 enum COMMAND_TYPE 10028 { 10029 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 10030 }; 10031 10032 //! \brief HUFFTABLEID_1_BIT 10033 //! \details 10034 //! Identifies the huffman table. 10035 enum HUFFTABLEID_1_BIT 10036 { 10037 HUFFTABLEID_1_BIT_Y = 0, //!< Huffman table for Y 10038 }; 10039 10040 //! \name Initializations 10041 10042 //! \brief Explicit member initialization function 10043 MFX_JPEG_HUFF_TABLE_STATE_CMD(); 10044 10045 static const size_t dwSize = 53; 10046 static const size_t byteSize = 212; 10047 }; 10048 10049 //! 10050 //! \brief GRAPHICSADDRESS63_6 10051 //! \details 10052 //! This structure is intended to define the upper bits of the 10053 //! GraphicsAddress, when bits 5:0 are already defined in the referring 10054 //! register. So bit 0 of this structure should correspond to bit 6 of the 10055 //! full GraphicsAddress. 10056 //! 10057 struct GRAPHICSADDRESS63_6_CMD 10058 { 10059 union 10060 { 10061 //!< DWORD 0..1 10062 struct 10063 { 10064 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10065 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD( 6, 47) ; //!< GraphicsAddress47-6 10066 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 10067 }; 10068 uint32_t Value[2]; 10069 } DW0_1; 10070 10071 //! \name Local enumerations 10072 10073 //! \name Initializations 10074 10075 //! \brief Explicit member initialization function 10076 GRAPHICSADDRESS63_6_CMD(); 10077 10078 static const size_t dwSize = 2; 10079 static const size_t byteSize = 8; 10080 }; 10081 10082 //! 10083 //! \brief MFX_PIPE_BUF_ADDR_STATE 10084 //! \details 10085 //! This state command provides the memory base addresses for all row 10086 //! stores, StreamOut buffer and reconstructed picture output buffers 10087 //! required by the MFD or MFC Engine (that are in addition to the row 10088 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 10089 //! reference picture buffers). 10090 //! This is a picture level state command and is common among all codec 10091 //! standards and for both encoder and decoder operating modes. However, 10092 //! some fields may only applicable to a specific codec standard. All Pixel 10093 //! Surfaces (original, reference frame and reconstructed frame) in the 10094 //! Encoder are programmed with the same surface state (NV12 and TileY 10095 //! format), except each has its own frame buffer base address. In the tile 10096 //! format, there is no need to provide buffer offset for each slice; since 10097 //! from each MB address, the hardware can calculated the corresponding 10098 //! memory location within the frame buffer directly. 10099 //! 10100 struct MFX_PIPE_BUF_ADDR_STATE_CMD 10101 { 10102 union 10103 { 10104 //!< DWORD 0 10105 struct 10106 { 10107 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 10108 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 10109 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 10110 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 10111 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMON_OPCODE 10112 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 10113 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 10114 }; 10115 uint32_t Value; 10116 } DW0; 10117 union 10118 { 10119 //!< DWORD 1 10120 struct 10121 { 10122 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10123 uint32_t PreDeblockingDestinationAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Pre Deblocking Destination Address 10124 }; 10125 uint32_t Value; 10126 } DW1; 10127 union 10128 { 10129 //!< DWORD 2 10130 struct 10131 { 10132 uint32_t PreDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Pre Deblocking Destination Address High 10133 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10134 }; 10135 uint32_t Value; 10136 } DW2; 10137 union 10138 { 10139 //!< DWORD 3 10140 struct 10141 { 10142 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10143 uint32_t PreDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10144 uint32_t PreDeblockingMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10145 uint32_t PreDeblockingMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< Pre Deblocking - Memory Compression Mode 10146 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10147 uint32_t PreDeblockingTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< PRE_DEBLOCKING__TILED_RESOURCE_MODE 10148 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10149 }; 10150 uint32_t Value; 10151 } DW3; 10152 union 10153 { 10154 //!< DWORD 4 10155 struct 10156 { 10157 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10158 uint32_t PostDeblockingDestinationAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Post Deblocking Destination Address 10159 }; 10160 uint32_t Value; 10161 } DW4; 10162 union 10163 { 10164 //!< DWORD 5 10165 struct 10166 { 10167 uint32_t PostDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Post Deblocking Destination Address High 10168 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10169 }; 10170 uint32_t Value; 10171 } DW5; 10172 union 10173 { 10174 //!< DWORD 6 10175 struct 10176 { 10177 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10178 uint32_t PostDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10179 uint32_t PostDeblockingMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10180 uint32_t PostDeblockingMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10181 uint32_t Reserved203 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10182 uint32_t PostDeblockingTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< POST_DEBLOCKING__TILED_RESOURCE_MODE 10183 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10184 }; 10185 uint32_t Value; 10186 } DW6; 10187 union 10188 { 10189 //!< DWORD 7 10190 struct 10191 { 10192 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10193 uint32_t OriginalUncompressedPictureSourceAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Original Uncompressed Picture Source Address 10194 }; 10195 uint32_t Value; 10196 } DW7; 10197 union 10198 { 10199 //!< DWORD 8 10200 struct 10201 { 10202 uint32_t OriginalUncompressedPictureSourceAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Original Uncompressed Picture Source Address High 10203 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10204 }; 10205 uint32_t Value; 10206 } DW8; 10207 union 10208 { 10209 //!< DWORD 9 10210 struct 10211 { 10212 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10213 uint32_t OriginalUncompressedPictureSourceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10214 uint32_t OriginalUncompressedPictureMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10215 uint32_t OriginalUncompressedPictureMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10216 uint32_t Reserved299 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10217 uint32_t OriginalUncompressedPictureTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10218 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10219 }; 10220 uint32_t Value; 10221 } DW9; 10222 union 10223 { 10224 //!< DWORD 10 10225 struct 10226 { 10227 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10228 uint32_t StreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< StreamOut Data Destination Base Address 10229 }; 10230 uint32_t Value; 10231 } DW10; 10232 union 10233 { 10234 //!< DWORD 11 10235 struct 10236 { 10237 uint32_t StreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< StreamOut Data Destination Base Address High 10238 uint32_t Reserved368 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10239 }; 10240 uint32_t Value; 10241 } DW11; 10242 union 10243 { 10244 //!< DWORD 12 10245 struct 10246 { 10247 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10248 uint32_t StreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10249 uint32_t StreamoutDataDestinationMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10250 uint32_t StreamoutDataDestinationMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10251 uint32_t Reserved395 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10252 uint32_t StreamoutDataDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10253 uint32_t Reserved399 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10254 }; 10255 uint32_t Value; 10256 } DW12; 10257 union 10258 { 10259 //!< DWORD 13 10260 struct 10261 { 10262 uint32_t Reserved416 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10263 uint32_t IntraRowStoreScratchBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Intra Row Store Scratch Buffer Base Address 10264 }; 10265 uint32_t Value; 10266 } DW13; 10267 union 10268 { 10269 //!< DWORD 14 10270 struct 10271 { 10272 uint32_t IntraRowStoreScratchBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra Row Store Scratch Buffer Base Address High 10273 uint32_t Reserved464 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10274 }; 10275 uint32_t Value; 10276 } DW14; 10277 union 10278 { 10279 //!< DWORD 15 10280 struct 10281 { 10282 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10283 uint32_t IntraRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10284 uint32_t IntraRowStoreScratchBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10285 uint32_t IntraRowStoreScratchBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10286 uint32_t Reserved491 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 10287 uint32_t IntraRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10288 uint32_t IntraRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10289 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10290 }; 10291 uint32_t Value; 10292 } DW15; 10293 union 10294 { 10295 //!< DWORD 16 10296 struct 10297 { 10298 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10299 uint32_t DeblockingFilterRowStoreScratchBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Deblocking Filter Row Store Scratch Base Address 10300 }; 10301 uint32_t Value; 10302 } DW16; 10303 union 10304 { 10305 //!< DWORD 17 10306 struct 10307 { 10308 uint32_t DeblockingFilterRowStoreScratchBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Deblocking Filter Row Store Scratch Base Address High 10309 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10310 }; 10311 uint32_t Value; 10312 } DW17; 10313 union 10314 { 10315 //!< DWORD 18 10316 struct 10317 { 10318 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10319 uint32_t DeblockingFilterRowStoreScratchArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10320 uint32_t DeblockingFilterRowStoreScratchMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10321 uint32_t DeblockingFilterRowStoreScratchMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10322 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 10323 uint32_t DeblockingFilterRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10324 uint32_t DeblockingFilterRowStoreTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10325 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10326 }; 10327 uint32_t Value; 10328 } DW18; 10329 10330 mhw_vdbox_mfx_g11_X::GRAPHICSADDRESS63_6_CMD Refpicbaseaddr[16]; //!< RefPicBaseAddr 10331 10332 union 10333 { 10334 //!< DWORD 51 10335 struct 10336 { 10337 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10338 uint32_t ReferencePictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10339 uint32_t Reserved1641 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 10340 uint32_t ReferencePictureTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< REFERENCE_PICTURE__TILED_RESOURCE_MODE 10341 uint32_t Reserved1647 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10342 }; 10343 uint32_t Value; 10344 } DW51; 10345 union 10346 { 10347 //!< DWORD 52 10348 struct 10349 { 10350 uint32_t Reserved1664 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10351 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address 10352 }; 10353 uint32_t Value; 10354 } DW52; 10355 union 10356 { 10357 //!< DWORD 53 10358 struct 10359 { 10360 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address High 10361 uint32_t Reserved1712 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10362 }; 10363 uint32_t Value; 10364 } DW53; 10365 union 10366 { 10367 //!< DWORD 54 10368 struct 10369 { 10370 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10371 uint32_t MacroblockStatusBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10372 uint32_t MacroblockStatusBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10373 uint32_t MacroblockStatusBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10374 uint32_t Reserved1739 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10375 uint32_t MacroblockStatusBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10376 uint32_t Reserved1743 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10377 }; 10378 uint32_t Value; 10379 } DW54; 10380 union 10381 { 10382 //!< DWORD 55 10383 struct 10384 { 10385 uint32_t Reserved1760 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10386 uint32_t MacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Macroblock ILDB StreamOut Buffer Base Address 10387 }; 10388 uint32_t Value; 10389 } DW55; 10390 union 10391 { 10392 //!< DWORD 56 10393 struct 10394 { 10395 uint32_t MacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock ILDB StreamOut Buffer Base Address High 10396 uint32_t Reserved1808 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10397 }; 10398 uint32_t Value; 10399 } DW56; 10400 union 10401 { 10402 //!< DWORD 57 10403 struct 10404 { 10405 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10406 uint32_t MacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10407 uint32_t MacroblockIldbStreamoutBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10408 uint32_t MacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10409 uint32_t Reserved1835 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10410 uint32_t MacroblockIldbStreamoutTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10411 uint32_t Reserved1839 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10412 }; 10413 uint32_t Value; 10414 } DW57; 10415 union 10416 { 10417 //!< DWORD 58 10418 struct 10419 { 10420 uint32_t Reserved1856 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10421 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Second Macroblock ILDB StreamOut Buffer Base Address 10422 }; 10423 uint32_t Value; 10424 } DW58; 10425 union 10426 { 10427 //!< DWORD 59 10428 struct 10429 { 10430 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Second Macroblock ILDB StreamOut Buffer Base Address High 10431 uint32_t Reserved1904 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10432 }; 10433 uint32_t Value; 10434 } DW59; 10435 union 10436 { 10437 //!< DWORD 60 10438 struct 10439 { 10440 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10441 uint32_t SecondMacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Second Macroblock ILDB StreamOut Buffer - Arbitration Priority Control 10442 uint32_t SecondMacroblockIldbStreamoutBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10443 uint32_t SecondMacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10444 uint32_t Reserved1931 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10445 uint32_t SecondMacroblockIldbStreamoutBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 10446 uint32_t Reserved1935 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10447 }; 10448 uint32_t Value; 10449 } DW60; 10450 union 10451 { 10452 //!< DWORD 61 10453 struct 10454 { 10455 uint32_t ReferencePicture0MemoryCompressionEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< REFERENCE_PICTURE_0__MEMORY_COMPRESSION_ENABLE 10456 uint32_t ReferencePicture0MemoryCompressionMode : __CODEGEN_BITFIELD( 1, 1) ; //!< REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 10457 uint32_t ReferencePicture1MemoryCompressionEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< REFERENCE_PICTURE_1__MEMORY_COMPRESSION_ENABLE 10458 uint32_t ReferencePicture1MemoryCompressionMode : __CODEGEN_BITFIELD( 3, 3) ; //!< REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 10459 uint32_t ReferencePicture2MemoryCompressionEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< REFERENCE_PICTURE_2__MEMORY_COMPRESSION_ENABLE 10460 uint32_t ReferencePicture2MemoryCompressionMode : __CODEGEN_BITFIELD( 5, 5) ; //!< REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 10461 uint32_t ReferencePicture3MemoryCompressionEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< REFERENCE_PICTURE_3__MEMORY_COMPRESSION_ENABLE 10462 uint32_t ReferencePicture3MemoryCompressionMode : __CODEGEN_BITFIELD( 7, 7) ; //!< REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 10463 uint32_t ReferencePicture4MemoryCompressionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< REFERENCE_PICTURE_4__MEMORY_COMPRESSION_ENABLE 10464 uint32_t ReferencePicture4MemoryCompressionMode : __CODEGEN_BITFIELD( 9, 9) ; //!< REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 10465 uint32_t ReferencePicture5MemoryCompressionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< REFERENCE_PICTURE_5__MEMORY_COMPRESSION_ENABLE 10466 uint32_t ReferencePicture5MemoryCompressionMode : __CODEGEN_BITFIELD(11, 11) ; //!< REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 10467 uint32_t ReferencePicture6MemoryCompressionEnable : __CODEGEN_BITFIELD(12, 12) ; //!< REFERENCE_PICTURE_6__MEMORY_COMPRESSION_ENABLE 10468 uint32_t ReferencePicture6MemoryCompressionMode : __CODEGEN_BITFIELD(13, 13) ; //!< REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 10469 uint32_t ReferencePicture7MemoryCompressionEnable : __CODEGEN_BITFIELD(14, 14) ; //!< REFERENCE_PICTURE_7__MEMORY_COMPRESSION_ENABLE 10470 uint32_t ReferencePicture7MemoryCompressionMode : __CODEGEN_BITFIELD(15, 15) ; //!< REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 10471 uint32_t ReferencePicture8MemoryCompressionEnable : __CODEGEN_BITFIELD(16, 16) ; //!< REFERENCE_PICTURE_8__MEMORY_COMPRESSION_ENABLE 10472 uint32_t ReferencePicture8MemoryCompressionMode : __CODEGEN_BITFIELD(17, 17) ; //!< REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 10473 uint32_t ReferencePicture9MemoryCompressionEnable : __CODEGEN_BITFIELD(18, 18) ; //!< REFERENCE_PICTURE_9__MEMORY_COMPRESSION_ENABLE 10474 uint32_t ReferencePicture9MemoryCompressionMode : __CODEGEN_BITFIELD(19, 19) ; //!< REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 10475 uint32_t ReferencePicture10MemoryCompressionEnable : __CODEGEN_BITFIELD(20, 20) ; //!< REFERENCE_PICTURE_10__MEMORY_COMPRESSION_ENABLE 10476 uint32_t ReferencePicture10MemoryCompressionMode : __CODEGEN_BITFIELD(21, 21) ; //!< REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 10477 uint32_t ReferencePicture11MemoryCompressionEnable : __CODEGEN_BITFIELD(22, 22) ; //!< REFERENCE_PICTURE_11__MEMORY_COMPRESSION_ENABLE 10478 uint32_t ReferencePicture11MemoryCompressionMode : __CODEGEN_BITFIELD(23, 23) ; //!< REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 10479 uint32_t ReferencePicture12MemoryCompressionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< REFERENCE_PICTURE_12__MEMORY_COMPRESSION_ENABLE 10480 uint32_t ReferencePicture12MemoryCompressionMode : __CODEGEN_BITFIELD(25, 25) ; //!< REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 10481 uint32_t ReferencePicture13MemoryCompressionEnable : __CODEGEN_BITFIELD(26, 26) ; //!< REFERENCE_PICTURE_13__MEMORY_COMPRESSION_ENABLE 10482 uint32_t ReferencePicture13MemoryCompressionMode : __CODEGEN_BITFIELD(27, 27) ; //!< REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 10483 uint32_t ReferencePicture14MemoryCompressionEnable : __CODEGEN_BITFIELD(28, 28) ; //!< REFERENCE_PICTURE_14__MEMORY_COMPRESSION_ENABLE 10484 uint32_t ReferencePicture14MemoryCompressionMode : __CODEGEN_BITFIELD(29, 29) ; //!< REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 10485 uint32_t ReferencePicture15MemoryCompressionEnable : __CODEGEN_BITFIELD(30, 30) ; //!< REFERENCE_PICTURE_15__MEMORY_COMPRESSION_ENABLE 10486 uint32_t ReferencePicture15MemoryCompressionMode : __CODEGEN_BITFIELD(31, 31) ; //!< REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 10487 }; 10488 uint32_t Value; 10489 } DW61; 10490 union 10491 { 10492 //!< DWORD 62 10493 struct 10494 { 10495 uint32_t Reserved1984 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10496 uint32_t ScaledReferenceSurfaceBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Scaled Reference Surface Base Address 10497 }; 10498 uint32_t Value; 10499 } DW62; 10500 union 10501 { 10502 //!< DWORD 63 10503 struct 10504 { 10505 uint32_t ScaledReferenceSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Scaled Reference Surface Base Address High 10506 uint32_t Reserved2032 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10507 }; 10508 uint32_t Value; 10509 } DW63; 10510 union 10511 { 10512 //!< DWORD 64 10513 struct 10514 { 10515 uint32_t Reserved2048 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 10516 uint32_t ScaledReferenceSurfaceIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Scaled Reference Surface - Index to Memory Object Control State (MOCS) Tables 10517 uint32_t ScaleReferenceSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 10518 uint32_t ScaledReferenceSurfaceMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Scaled Reference Surface - Memory Compression Enable 10519 uint32_t ScaledReferenceSurfaceMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 10520 uint32_t Reserved2059 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10521 uint32_t ScaledReferenceSurfaceTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 10522 uint32_t Reserved2063 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10523 }; 10524 uint32_t Value; 10525 } DW64; 10526 union 10527 { 10528 //!< DWORD 65 10529 struct 10530 { 10531 uint32_t Reserved2080 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10532 uint32_t SlicesizeStreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< SliceSize StreamOut Data Destination Base Address 10533 }; 10534 uint32_t Value; 10535 } DW65; 10536 union 10537 { 10538 //!< DWORD 66 10539 struct 10540 { 10541 uint32_t SlicesizeStreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SliceSize StreamOut Data Destination Base Address High 10542 uint32_t Reserved2128 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10543 }; 10544 uint32_t Value; 10545 } DW66; 10546 union 10547 { 10548 //!< DWORD 67 10549 struct 10550 { 10551 uint32_t Reserved2144 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 10552 uint32_t SlicesizeStreamoutDataDestinationIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SliceSize StreamOut Data Destination - Index to Memory Object Control State (MOCS) Tables 10553 uint32_t SlicesizeStreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SLICESIZE_STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10554 uint32_t SlicesizeStreamoutDataDestinationMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SliceSize StreamOut Data Destination - Memory Compression Enable 10555 uint32_t SlicesizeStreamoutDataDestinationMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SLICESIZE_STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10556 uint32_t Reserved2155 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10557 uint32_t SlicesizeStreamoutDataDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SLICESIZE_STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10558 uint32_t Reserved2159 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10559 }; 10560 uint32_t Value; 10561 } DW67; 10562 10563 //! \name Local enumerations 10564 10565 enum SUBOPCODE_B 10566 { 10567 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 10568 }; 10569 10570 enum SUBOPCODE_A 10571 { 10572 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 10573 }; 10574 10575 enum COMMON_OPCODE 10576 { 10577 COMMON_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 10578 }; 10579 10580 enum PIPELINE 10581 { 10582 PIPELINE_MFXPIPEBUFADDRSTATE = 2, //!< No additional details 10583 }; 10584 10585 enum COMMAND_TYPE 10586 { 10587 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 10588 }; 10589 10590 //! \brief PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10591 //! \details 10592 //! This field controls the priority of arbitration used in the GAC/GAM 10593 //! pipeline for this surface. 10594 enum PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10595 { 10596 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10597 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10598 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10599 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10600 }; 10601 10602 //! \brief PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10603 //! \details 10604 //! Memory compression will be attempted for this surface. 10605 enum PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10606 { 10607 PRE_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10608 PRE_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10609 }; 10610 10611 //! \brief PRE_DEBLOCKING__TILED_RESOURCE_MODE 10612 //! \details 10613 //! <b>For Media Surfaces:</b> 10614 //! This field specifies the tiled resource mode. 10615 enum PRE_DEBLOCKING__TILED_RESOURCE_MODE 10616 { 10617 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10618 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10619 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10620 }; 10621 10622 //! \brief POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10623 //! \details 10624 //! This field controls the priority of arbitration used in the GAC/GAM 10625 //! pipeline for this surface. 10626 enum POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10627 { 10628 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10629 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10630 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10631 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10632 }; 10633 10634 //! \brief POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10635 //! \details 10636 //! Memory compression will be attempted for this surface. 10637 enum POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10638 { 10639 POST_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10640 POST_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10641 }; 10642 10643 //! \brief POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10644 //! \details 10645 //! Distinguishes Vertical from Horizontal compression. Please refer to 10646 //! vol1a <b>Memory Data Formats chapter -section</b> Media Memory 10647 //! Compression <b>for more details.</b> 10648 enum POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10649 { 10650 POST_DEBLOCKING_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10651 }; 10652 10653 //! \brief POST_DEBLOCKING__TILED_RESOURCE_MODE 10654 //! \details 10655 //! <b>For Media Surfaces:</b> 10656 //! This field specifies the tiled resource mode. 10657 enum POST_DEBLOCKING__TILED_RESOURCE_MODE 10658 { 10659 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10660 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10661 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10662 }; 10663 10664 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10665 //! \details 10666 //! This field controls the priority of arbitration used in the GAC/GAM 10667 //! pipeline for this surface. 10668 enum ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10669 { 10670 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10671 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10672 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10673 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10674 }; 10675 10676 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10677 //! \details 10678 //! Note: This is a READ Surface. The setting of this bit should match the 10679 //! settings on how this is written out before. 10680 enum ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10681 { 10682 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10683 }; 10684 10685 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10686 //! \details 10687 //! Distinguishes Vertical from Horizontal compression. Please refer to 10688 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10689 //! more details. Note: This bit is not used unless Memory Compression 10690 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10691 //! bit should match the settings on how this is written out before 10692 enum ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10693 { 10694 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10695 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10696 }; 10697 10698 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10699 //! \details 10700 //! <b>For Media Surfaces:</b> 10701 //! This field specifies the tiled resource mode. 10702 enum ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10703 { 10704 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10705 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10706 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10707 }; 10708 10709 //! \brief STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10710 //! \details 10711 //! This field controls the priority of arbitration used in the GAC/GAM 10712 //! pipeline for this surface. 10713 enum STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10714 { 10715 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10716 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10717 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10718 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10719 }; 10720 10721 //! \brief STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10722 //! \details 10723 //! Note: This is a READ Surface. The setting of this bit should match the 10724 //! settings on how this is written out before. 10725 enum STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10726 { 10727 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10728 }; 10729 10730 //! \brief STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10731 //! \details 10732 //! Distinguishes Vertical from Horizontal compression. Please refer to 10733 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10734 //! more details. Note: This bit is not used unless Memory Compression 10735 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10736 //! bit should match the settings on how this is written out before 10737 enum STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10738 { 10739 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10740 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10741 }; 10742 10743 //! \brief STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10744 //! \details 10745 //! <b>For Media Surfaces:</b> 10746 //! This field specifies the tiled resource mode. 10747 enum STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10748 { 10749 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10750 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10751 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10752 }; 10753 10754 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10755 //! \details 10756 //! This field controls the priority of arbitration used in the GAC/GAM 10757 //! pipeline for this surface. 10758 enum INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10759 { 10760 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10761 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10762 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10763 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10764 }; 10765 10766 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10767 //! \details 10768 //! This surface is linear surface. This bit must be set to "0" since only 10769 //! TileY/TileYf/TileYs surface is allowed to be compressed 10770 enum INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10771 { 10772 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10773 }; 10774 10775 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10776 //! \details 10777 //! Distinguishes Vertical from Horizontal compression. Please refer to 10778 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10779 //! more details. Note: This bit is not used unless Memory Compression 10780 //! Enable is set to "1" 10781 enum INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10782 { 10783 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10784 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10785 }; 10786 10787 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10788 //! \details 10789 //! This field controls if Intra Row Store is going to store inside Media 10790 //! Cache or to LLC. 10791 enum INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10792 { 10793 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 10794 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 10795 }; 10796 10797 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10798 //! \details 10799 //! <b>For Media Surfaces:</b> 10800 //! This field specifies the tiled resource mode. 10801 enum INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10802 { 10803 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10804 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10805 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10806 }; 10807 10808 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10809 //! \details 10810 //! This field controls the priority of arbitration used in the GAC/GAM 10811 //! pipeline for this surface. 10812 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10813 { 10814 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10815 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10816 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10817 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10818 }; 10819 10820 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10821 //! \details 10822 //! This surface is linear surface. This bit must be set to "0" since only 10823 //! TileY/TileYf/TileYs surface is allowed to be compressed 10824 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10825 { 10826 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10827 }; 10828 10829 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10830 //! \details 10831 //! Distinguishes Vertical from Horizontal compression. Please refer to 10832 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10833 //! more details. Note: This bit is not used unless Memory Compression 10834 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10835 //! bit should match the settings on how this is written out before. 10836 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10837 { 10838 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10839 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10840 }; 10841 10842 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10843 //! \details 10844 //! This field controls if Intra Row Store is going to store inside Media 10845 //! Internal Storage or to LLC. 10846 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10847 { 10848 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 10849 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Media Internal Storage 10850 }; 10851 10852 //! \brief DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10853 //! \details 10854 //! <b>For Media Surfaces:</b> 10855 //! This field specifies the tiled resource mode. 10856 enum DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10857 { 10858 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10859 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10860 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10861 }; 10862 10863 //! \brief REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10864 //! \details 10865 //! This field controls the priority of arbitration used in the GAC/GAM 10866 //! pipeline for this surface. 10867 enum REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10868 { 10869 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10870 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10871 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10872 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10873 }; 10874 10875 //! \brief REFERENCE_PICTURE__TILED_RESOURCE_MODE 10876 //! \details 10877 //! <b>For Media Surfaces:</b> 10878 //! This field specifies the tiled resource mode. 10879 enum REFERENCE_PICTURE__TILED_RESOURCE_MODE 10880 { 10881 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10882 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10883 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10884 }; 10885 10886 //! \brief MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10887 //! \details 10888 //! This field controls the priority of arbitration used in the GAC/GAM 10889 //! pipeline for this surface. 10890 enum MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10891 { 10892 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10893 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10894 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10895 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10896 }; 10897 10898 //! \brief MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10899 //! \details 10900 //! This surface is linear surface. This bit must be set to "0" since only 10901 //! TileY/TileYf/TileYs surface is allowed to be compressed 10902 enum MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10903 { 10904 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10905 }; 10906 10907 //! \brief MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10908 //! \details 10909 //! Distinguishes Vertical from Horizontal compression. Please refer to 10910 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10911 //! more details. Note: This bit is not used unless Memory Compression 10912 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10913 //! bit should match the settings on how this is written out before. 10914 enum MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10915 { 10916 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10917 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10918 }; 10919 10920 //! \brief MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10921 //! \details 10922 //! <b>For Media Surfaces:</b> 10923 //! This field specifies the tiled resource mode. 10924 enum MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10925 { 10926 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10927 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10928 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10929 }; 10930 10931 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10932 //! \details 10933 //! This field controls the priority of arbitration used in the GAC/GAM 10934 //! pipeline for this surface. 10935 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10936 { 10937 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10938 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10939 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10940 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10941 }; 10942 10943 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10944 //! \details 10945 //! This surface is linear surface. This bit must be set to "0" since only 10946 //! TileY/TileYf/TileYs surface is allowed to be compressed 10947 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10948 { 10949 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10950 }; 10951 10952 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10953 //! \details 10954 //! Distinguishes Vertical from Horizontal compression. Please refer to 10955 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10956 //! more details. Note: This bit is not used unless Memory Compression 10957 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10958 //! bit should match the settings on how this is written out before. 10959 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10960 { 10961 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10962 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10963 }; 10964 10965 //! \brief MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10966 //! \details 10967 //! <b>For Media Surfaces:</b> 10968 //! This field specifies the tiled resource mode. 10969 enum MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10970 { 10971 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10972 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10973 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10974 }; 10975 10976 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10977 //! \details 10978 //! This surface is linear surface. This bit must be set to "0" since only 10979 //! TileY/TileYf/TileYs surface is allowed to be compressed 10980 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10981 { 10982 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10983 }; 10984 10985 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10986 //! \details 10987 //! Distinguishes Vertical from Horizontal compression. Please refer to 10988 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10989 //! more details. Note: This bit is not used unless Memory Compression 10990 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10991 //! bit should match the settings on how this is written out before. 10992 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10993 { 10994 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10995 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10996 }; 10997 10998 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 10999 //! \details 11000 //! <b>For Media Surfaces:</b> 11001 //! This field specifies the tiled resource mode. 11002 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 11003 { 11004 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11005 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11006 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11007 }; 11008 11009 enum REFERENCE_PICTURE_0__MEMORY_COMPRESSION_ENABLE 11010 { 11011 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11012 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11013 }; 11014 11015 //! \brief REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 11016 //! \details 11017 //! Distinguishes Vertical from Horizontal compression. Please refer to 11018 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11019 //! more details. Note: This bit is not used unless Memory Compression 11020 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11021 //! bit should match the settings on how this is written out before. 11022 enum REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 11023 { 11024 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11025 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11026 }; 11027 11028 enum REFERENCE_PICTURE_1__MEMORY_COMPRESSION_ENABLE 11029 { 11030 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11031 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11032 }; 11033 11034 //! \brief REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 11035 //! \details 11036 //! Distinguishes Vertical from Horizontal compression. Please refer to 11037 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11038 //! more details. Note: This bit is not used unless Memory Compression 11039 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11040 //! bit should match the settings on how this is written out before. 11041 enum REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 11042 { 11043 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11044 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11045 }; 11046 11047 enum REFERENCE_PICTURE_2__MEMORY_COMPRESSION_ENABLE 11048 { 11049 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11050 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11051 }; 11052 11053 //! \brief REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 11054 //! \details 11055 //! Distinguishes Vertical from Horizontal compression. Please refer to 11056 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11057 //! more details. Note: This bit is not used unless Memory Compression 11058 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11059 //! bit should match the settings on how this is written out before. 11060 enum REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 11061 { 11062 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11063 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11064 }; 11065 11066 enum REFERENCE_PICTURE_3__MEMORY_COMPRESSION_ENABLE 11067 { 11068 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11069 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11070 }; 11071 11072 //! \brief REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 11073 //! \details 11074 //! Distinguishes Vertical from Horizontal compression. Please refer to 11075 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11076 //! more details. Note: This bit is not used unless Memory Compression 11077 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11078 //! bit should match the settings on how this is written out before. 11079 enum REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 11080 { 11081 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11082 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11083 }; 11084 11085 enum REFERENCE_PICTURE_4__MEMORY_COMPRESSION_ENABLE 11086 { 11087 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11088 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11089 }; 11090 11091 //! \brief REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 11092 //! \details 11093 //! Distinguishes Vertical from Horizontal compression. Please refer to 11094 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11095 //! more details. Note: This bit is not used unless Memory Compression 11096 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11097 //! bit should match the settings on how this is written out before. 11098 enum REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 11099 { 11100 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11101 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11102 }; 11103 11104 enum REFERENCE_PICTURE_5__MEMORY_COMPRESSION_ENABLE 11105 { 11106 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11107 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11108 }; 11109 11110 //! \brief REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 11111 //! \details 11112 //! Distinguishes Vertical from Horizontal compression. Please refer to 11113 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11114 //! more details. Note: This bit is not used unless Memory Compression 11115 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11116 //! bit should match the settings on how this is written out before. 11117 enum REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 11118 { 11119 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11120 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11121 }; 11122 11123 enum REFERENCE_PICTURE_6__MEMORY_COMPRESSION_ENABLE 11124 { 11125 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11126 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11127 }; 11128 11129 //! \brief REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 11130 //! \details 11131 //! Distinguishes Vertical from Horizontal compression. Please refer to 11132 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11133 //! more details. Note: This bit is not used unless Memory Compression 11134 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11135 //! bit should match the settings on how this is written out before. 11136 enum REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 11137 { 11138 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11139 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11140 }; 11141 11142 enum REFERENCE_PICTURE_7__MEMORY_COMPRESSION_ENABLE 11143 { 11144 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11145 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11146 }; 11147 11148 //! \brief REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 11149 //! \details 11150 //! Distinguishes Vertical from Horizontal compression. Please refer to 11151 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11152 //! more details. Note: This bit is not used unless Memory Compression 11153 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11154 //! bit should match the settings on how this is written out before. 11155 enum REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 11156 { 11157 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11158 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11159 }; 11160 11161 enum REFERENCE_PICTURE_8__MEMORY_COMPRESSION_ENABLE 11162 { 11163 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11164 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11165 }; 11166 11167 //! \brief REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 11168 //! \details 11169 //! Distinguishes Vertical from Horizontal compression. Please refer to 11170 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11171 //! more details. Note: This bit is not used unless Memory Compression 11172 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11173 //! bit should match the settings on how this is written out before. 11174 enum REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 11175 { 11176 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11177 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11178 }; 11179 11180 enum REFERENCE_PICTURE_9__MEMORY_COMPRESSION_ENABLE 11181 { 11182 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11183 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11184 }; 11185 11186 //! \brief REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 11187 //! \details 11188 //! Distinguishes Vertical from Horizontal compression. Please refer to 11189 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11190 //! more details. Note: This bit is not used unless Memory Compression 11191 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11192 //! bit should match the settings on how this is written out before. 11193 enum REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 11194 { 11195 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11196 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11197 }; 11198 11199 enum REFERENCE_PICTURE_10__MEMORY_COMPRESSION_ENABLE 11200 { 11201 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11202 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11203 }; 11204 11205 //! \brief REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 11206 //! \details 11207 //! Distinguishes Vertical from Horizontal compression. Please refer to 11208 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11209 //! more details. Note: This bit is not used unless Memory Compression 11210 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11211 //! bit should match the settings on how this is written out before. 11212 enum REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 11213 { 11214 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11215 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11216 }; 11217 11218 enum REFERENCE_PICTURE_11__MEMORY_COMPRESSION_ENABLE 11219 { 11220 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11221 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11222 }; 11223 11224 //! \brief REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 11225 //! \details 11226 //! Distinguishes Vertical from Horizontal compression. Please refer to 11227 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11228 //! more details. 11229 //! Note: This bit is not used unless Memory Compression Enable is set 11230 //! to "1" 11231 //! Note: This is a READ Surface. The setting of this bit should 11232 //! match the settings on how this is written out before. 11233 enum REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 11234 { 11235 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11236 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11237 }; 11238 11239 enum REFERENCE_PICTURE_12__MEMORY_COMPRESSION_ENABLE 11240 { 11241 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11242 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11243 }; 11244 11245 //! \brief REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 11246 //! \details 11247 //! Distinguishes Vertical from Horizontal compression. Please refer to 11248 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11249 //! more details. Note: This bit is not used unless Memory Compression 11250 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11251 //! bit should match the settings on how this is written out before. 11252 enum REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 11253 { 11254 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11255 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11256 }; 11257 11258 enum REFERENCE_PICTURE_13__MEMORY_COMPRESSION_ENABLE 11259 { 11260 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11261 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11262 }; 11263 11264 //! \brief REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 11265 //! \details 11266 //! Distinguishes Vertical from Horizontal compression. Please refer to 11267 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11268 //! more details. Note: This bit is not used unless Memory Compression 11269 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11270 //! bit should match the settings on how this is written out before. 11271 enum REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 11272 { 11273 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11274 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11275 }; 11276 11277 enum REFERENCE_PICTURE_14__MEMORY_COMPRESSION_ENABLE 11278 { 11279 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11280 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11281 }; 11282 11283 //! \brief REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 11284 //! \details 11285 //! Distinguishes Vertical from Horizontal compression. Please refer to 11286 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11287 //! more details. Note: This bit is not used unless Memory Compression 11288 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11289 //! bit should match the settings on how this is written out before. 11290 enum REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 11291 { 11292 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11293 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11294 }; 11295 11296 enum REFERENCE_PICTURE_15__MEMORY_COMPRESSION_ENABLE 11297 { 11298 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11299 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11300 }; 11301 11302 //! \brief REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 11303 //! \details 11304 //! Distinguishes Vertical from Horizontal compression. Please refer to 11305 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11306 //! more details. Note: This bit is not used unless Memory Compression 11307 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11308 //! bit should match the settings on how this is written out before. 11309 enum REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 11310 { 11311 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11312 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11313 }; 11314 11315 //! \brief SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 11316 //! \details 11317 //! This field controls the priority of arbitration used in the GAC/GAM 11318 //! pipeline for this surface. 11319 enum SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 11320 { 11321 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11322 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11323 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11324 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11325 }; 11326 11327 //! \brief SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 11328 //! \details 11329 //! Distinguishes Vertical from Horizontal compression. Please refer to 11330 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11331 //! more details. 11332 enum SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 11333 { 11334 SCALED_REFERENCE_SURFACE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11335 SCALED_REFERENCE_SURFACE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11336 }; 11337 11338 //! \brief SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 11339 //! \details 11340 //! For Media Surfaces: 11341 //! This field specifies the tiled resource mode 11342 enum SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 11343 { 11344 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11345 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< No tiled resource 11346 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< No tiled resource 11347 }; 11348 11349 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 11350 //! \details 11351 //! This field controls the priority of arbitration used in the GAC/GAM 11352 //! pipeline for this surface. 11353 enum SLICESIZE_STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 11354 { 11355 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11356 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11357 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11358 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11359 }; 11360 11361 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 11362 //! \details 11363 //! Distinguishes Vertical from Horizontal compression. Please refer to 11364 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11365 //! more details. 11366 enum SLICESIZE_STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 11367 { 11368 SLICESIZE_STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11369 SLICESIZE_STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11370 }; 11371 11372 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 11373 //! \details 11374 //! For Media Surfaces: This Surface is never tiled. 11375 enum SLICESIZE_STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 11376 { 11377 SLICESIZE_STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11378 SLICESIZE_STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< No tiled resource 11379 SLICESIZE_STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< No tiled resource 11380 }; 11381 11382 //! \name Initializations 11383 11384 //! \brief Explicit member initialization function 11385 MFX_PIPE_BUF_ADDR_STATE_CMD(); 11386 11387 static const size_t dwSize = 68; 11388 static const size_t byteSize = 272; 11389 }; 11390 11391 //! 11392 //! \brief MFX_AVC_DIRECTMODE_STATE 11393 //! \details 11394 //! This is a picture level command and is issued once per picture. All DMV 11395 //! buffers are treated as standard media surfaces, in which the lower 6 11396 //! bits are used for conveying surface states.Current Pic POC number is 11397 //! assumed to be available in POCList[32 and 33] of the 11398 //! MFX_AVC_DIRECTMODE_STATE Command.This command is only valid in the AVC 11399 //! decoding in VLD and IT modes, and AVC encoder mode. The same command 11400 //! supports both Long and Short AVC Interface. The DMV buffers are 11401 //! not required to be programmed for encoder mode. 11402 //! 11403 struct MFX_AVC_DIRECTMODE_STATE_CMD 11404 { 11405 union 11406 { 11407 //!< DWORD 0 11408 struct 11409 { 11410 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 11411 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 11412 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 11413 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 11414 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 11415 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 11416 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 11417 }; 11418 uint32_t Value; 11419 } DW0; 11420 11421 mhw_vdbox_mfx_g11_X::GRAPHICSADDRESS63_6_CMD DirectMvBufferBaseAddress[16]; //!< Direct MV Buffer Base Address 11422 11423 union 11424 { 11425 //!< DWORD 33 11426 struct 11427 { 11428 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 11429 uint32_t DirectMvBufferBaseAddressForReferenceFrameArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11430 uint32_t DirectMvBufferBaseAddressForReferenceFrameMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11431 uint32_t DirectMvBufferBaseAddressForReferenceFrameMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11432 uint32_t Reserved1067 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 11433 uint32_t DirectMvBufferBaseAddressForReferenceFrameTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11434 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 11435 }; 11436 uint32_t Value; 11437 } DW33; 11438 11439 mhw_vdbox_mfx_g11_X::GRAPHICSADDRESS63_6_CMD DirectMvBufferBaseAddressForWrite[1]; //!< Direct MV Buffer Base Address for Write 11440 11441 union 11442 { 11443 //!< DWORD 36 11444 struct 11445 { 11446 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 11447 uint32_t DirectMvBufferBaseAddressForWriteArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11448 uint32_t DirectMvBufferBaseAddressForWriteMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11449 uint32_t DirectMvBufferBaseAddressForWriteMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11450 uint32_t Reserved1163 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 11451 uint32_t DirectMvBufferBaseAddressForWriteTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11452 uint32_t Reserved1167 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 11453 }; 11454 uint32_t Value; 11455 } DW36; 11456 11457 uint32_t PocList[34]; //!< POC List 11458 11459 11460 //! \name Local enumerations 11461 11462 enum SUBOPCODEB 11463 { 11464 SUBOPCODEB_UNNAMED2 = 2, //!< No additional details 11465 }; 11466 11467 enum SUBOPCODEA 11468 { 11469 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 11470 }; 11471 11472 enum MEDIA_COMMAND_OPCODE 11473 { 11474 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 11475 }; 11476 11477 enum PIPELINE 11478 { 11479 PIPELINE_MFXSINGLEDW = 2, //!< No additional details 11480 }; 11481 11482 enum COMMAND_TYPE 11483 { 11484 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 11485 }; 11486 11487 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11488 //! \details 11489 //! This field controls the priority of arbitration used in the GAC/GAM 11490 //! pipeline for this surface. 11491 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11492 { 11493 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11494 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11495 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11496 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11497 }; 11498 11499 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11500 //! \details 11501 //! This surface is linear surface. This bit must be set to "0" since only 11502 //! TileY/TileYf/TileYs surface is allowed to be compressed 11503 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11504 { 11505 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11506 }; 11507 11508 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11509 //! \details 11510 //! Distinguishes Vertical from Horizontal compression. Please refer to 11511 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11512 //! more details. 11513 //! Note: This bit is not used unless Memory Compression Enable is set 11514 //! to "1" 11515 //! Note: This is a READ Surface. The setting of this bit should 11516 //! match the settings on how this is written out before. 11517 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11518 { 11519 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11520 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11521 }; 11522 11523 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11524 //! \details 11525 //! <b>For Media Surfaces:</b> 11526 //! This field specifies the tiled resource mode. 11527 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11528 { 11529 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11530 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11531 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11532 }; 11533 11534 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11535 //! \details 11536 //! This field controls the priority of arbitration used in the GAC/GAM 11537 //! pipeline for this surface. 11538 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11539 { 11540 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11541 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11542 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11543 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11544 }; 11545 11546 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11547 //! \details 11548 //! This surface is linear surface. This bit must be set to "0" since only 11549 //! TileY/TileYf/TileYs surface is allowed to be compressed 11550 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11551 { 11552 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11553 }; 11554 11555 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11556 //! \details 11557 //! Distinguishes Vertical from Horizontal compression. Please refer to 11558 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11559 //! more details. 11560 //! Note: This bit is not used unless Memory Compression Enable is set 11561 //! to "1" 11562 //! Note: This is a READ Surface. The setting of this bit should 11563 //! match the settings on how this is written out before. 11564 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11565 { 11566 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11567 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11568 }; 11569 11570 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11571 //! \details 11572 //! <b>For Media Surfaces:</b> 11573 //! This field specifies the tiled resource mode. 11574 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11575 { 11576 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11577 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11578 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11579 }; 11580 11581 //! \name Initializations 11582 11583 //! \brief Explicit member initialization function 11584 MFX_AVC_DIRECTMODE_STATE_CMD(); 11585 11586 static const size_t dwSize = 71; 11587 static const size_t byteSize = 284; 11588 }; 11589 11590 }; 11591 11592 #pragma pack() 11593 11594 #endif // __MHW_VDBOX_MFX_HWCMD_G11_X_H__ 11595