1 /* 2 * Copyright (c) 2017-2022, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_mfx_g11_X.h 24 //! \brief Defines functions for constructing Vdbox MFX commands on Gen11-based platforms 25 //! 26 27 #ifndef __MHW_VDBOX_MFX_G11_X_H__ 28 #define __MHW_VDBOX_MFX_G11_X_H__ 29 30 #include "mhw_vdbox_mfx_generic.h" 31 #include "mhw_vdbox_mfx_hwcmd_g11_X.h" 32 #include "mhw_mi_hwcmd_g11_X.h" 33 34 35 //! MHW Vdbox Mfx interface for Gen11 36 /*! 37 This class defines the Mfx command construction functions for Gen11 platform 38 */ 39 class MhwVdboxMfxInterfaceG11 : public MhwVdboxMfxInterfaceGeneric<mhw_vdbox_mfx_g11_X, mhw_mi_g11_X> 40 { 41 protected: 42 static const uint32_t m_avcInterMbMaxSize = 4095; //! AVC inter macroblock max size 43 static const uint32_t m_avcIntraMbMaxSize = 2700; //! AVC intra macroblock max size 44 45 bool m_scalabilitySupported = false; //!< Indicate if scalability supported 46 47 #define PATCH_LIST_COMMAND(x) (x##_NUMBER_OF_ADDRESSES) 48 49 enum CommandsNumberOfAddresses 50 { 51 // MFX Engine Commands 52 MI_BATCH_BUFFER_START_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 53 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 54 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 55 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 56 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 57 MFX_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 58 MFX_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 59 MFX_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 27, // 50 DW for 25 address fields, added 2 for DownScaledReconPicAddr 60 MFX_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 5, // 10 DW for 5 address fields 61 MFX_WAIT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 62 MFX_BSP_BUF_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 3, // 2 DW for 3 address fields 63 MFD_AVC_PICID_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 64 MFX_AVC_DIRECTMODE_STATE_CMD_NUMBER_OF_ADDRESSES = 17, // 50 DW for 17 address fields 65 MFX_AVC_IMG_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 66 MFX_QM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 67 MFX_FQM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 68 MFD_VC1_LONG_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 69 MFX_VC1_PRED_PIPE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 70 MFX_VC1_DIRECTMODE_STATE_CMD_NUMBER_OF_ADDRESSES = 2, // 2 DW for 2 address fields 71 MFX_MPEG2_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 72 MFX_DBK_OBJECT_CMD_NUMBER_OF_ADDRESSES = 4, // 2 DW for 4 address fields 73 MFX_VP8_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 2, // 2 DW for 2 address fields 74 MFX_AVC_SLICE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 75 MFD_AVC_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 76 MFD_AVC_DPB_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 77 MFD_AVC_SLICEADDR_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 78 MFX_AVC_REF_IDX_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 79 MFX_AVC_WEIGHTOFFSET_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 80 MFC_AVC_PAK_INSERT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 81 MFD_VC1_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 82 MFD_VC1_IT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 83 MFD_MPEG2_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 84 MFD_MPEG2_IT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 85 MFD_VP8_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 86 }; 87 88 public: 89 //! 90 //! \brief Constructor 91 //! MhwVdboxMfxInterfaceG11(PMOS_INTERFACE osInterface,MhwMiInterface * miInterface,MhwCpInterface * cpInterface,bool decodeInUse)92 MhwVdboxMfxInterfaceG11( 93 PMOS_INTERFACE osInterface, 94 MhwMiInterface *miInterface, 95 MhwCpInterface *cpInterface, 96 bool decodeInUse) 97 : MhwVdboxMfxInterfaceGeneric(osInterface, miInterface, cpInterface, decodeInUse) 98 { 99 MHW_FUNCTION_ENTER; 100 101 MHW_ASSERT(m_osInterface); 102 m_osInterface = osInterface; 103 104 if (m_numVdbox > 1 105 && m_osInterface != nullptr 106 && m_osInterface->bHcpDecScalabilityMode) 107 { 108 m_scalabilitySupported = true; 109 } 110 111 m_rhoDomainStatsEnabled = true; 112 113 InitRowstoreUserFeatureSettings(); 114 InitMmioRegisters(); 115 } 116 117 //! 118 //! \brief Destructor 119 //! ~MhwVdboxMfxInterfaceG11()120 virtual ~MhwVdboxMfxInterfaceG11() { MHW_FUNCTION_ENTER; } 121 122 //! 123 //! \brief Judge if scalability is supported 124 //! 125 //! \return bool 126 //! true if supported, else false 127 //! IsScalabilitySupported()128 inline bool IsScalabilitySupported() 129 { 130 return m_scalabilitySupported; 131 } 132 133 //! 134 //! \brief Disable scalability support 135 //! 136 //! \return void 137 //! DisableScalabilitySupport()138 inline void DisableScalabilitySupport() 139 { 140 m_scalabilitySupported = false; 141 } 142 143 protected: 144 145 void InitMmioRegisters(); 146 147 void InitRowstoreUserFeatureSettings(); 148 149 MOS_STATUS GetRowstoreCachingAddrs( 150 PMHW_VDBOX_ROWSTORE_PARAMS rowstoreParams); 151 152 #if (_DEBUG || _RELEASE_INTERNAL) 153 MOS_STATUS CheckScalabilityOverrideValidity(); 154 #endif 155 156 MOS_STATUS FindGpuNodeToUse( 157 PMHW_VDBOX_GPUNODE_LIMIT gpuNodeLimit); 158 159 MOS_STATUS GetMfxStateCommandsDataSize( 160 uint32_t mode, 161 uint32_t *commandsSize, 162 uint32_t *patchListSize, 163 bool isShortFormat); 164 165 MOS_STATUS GetMfxPrimitiveCommandsDataSize( 166 uint32_t mode, 167 uint32_t *commandsSize, 168 uint32_t *patchListSize, 169 bool isModeSpecific); 170 171 MOS_STATUS AddMfxPipeModeSelectCmd( 172 PMOS_COMMAND_BUFFER cmdBuffer, 173 PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS params); 174 175 MOS_STATUS AddMfxSurfaceCmd( 176 PMOS_COMMAND_BUFFER cmdBuffer, 177 PMHW_VDBOX_SURFACE_PARAMS params); 178 179 MOS_STATUS AddMfxPipeBufAddrCmd( 180 PMOS_COMMAND_BUFFER cmdBuffer, 181 PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS params); 182 183 MOS_STATUS AddMfxIndObjBaseAddrCmd( 184 PMOS_COMMAND_BUFFER cmdBuffer, 185 PMHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS params); 186 187 MOS_STATUS AddMfxBspBufBaseAddrCmd( 188 PMOS_COMMAND_BUFFER cmdBuffer, 189 PMHW_VDBOX_BSP_BUF_BASE_ADDR_PARAMS params); 190 191 MOS_STATUS AddMfxDecodeAvcImgCmd( 192 PMOS_COMMAND_BUFFER cmdBuffer, 193 PMHW_BATCH_BUFFER batchBuffer, 194 PMHW_VDBOX_AVC_IMG_PARAMS params); 195 196 MOS_STATUS AddMfxEncodeAvcImgCmd( 197 PMOS_COMMAND_BUFFER cmdBuffer, 198 PMHW_BATCH_BUFFER batchBuffer, 199 PMHW_VDBOX_AVC_IMG_PARAMS params); 200 201 MOS_STATUS AddMfxAvcDirectmodeCmd( 202 PMOS_COMMAND_BUFFER cmdBuffer, 203 PMHW_VDBOX_AVC_DIRECTMODE_PARAMS params); 204 205 MOS_STATUS AddMfdAvcSliceAddrCmd( 206 PMOS_COMMAND_BUFFER cmdBuffer, 207 PMHW_VDBOX_AVC_SLICE_STATE avcSliceState); 208 209 MOS_STATUS AddMfdAvcBsdObjectCmd( 210 PMOS_COMMAND_BUFFER cmdBuffer, 211 PMHW_VDBOX_AVC_SLICE_STATE avcSliceState); 212 213 MOS_STATUS AddMfxPakInsertObject( 214 PMOS_COMMAND_BUFFER cmdBuffer, 215 PMHW_BATCH_BUFFER batchBuffer, 216 PMHW_VDBOX_PAK_INSERT_PARAMS params); 217 218 MOS_STATUS AddMfxJpegPicCmd( 219 PMOS_COMMAND_BUFFER cmdBuffer, 220 PMHW_VDBOX_JPEG_PIC_STATE params); 221 222 MOS_STATUS AddMfxJpegEncodePicStateCmd( 223 PMOS_COMMAND_BUFFER cmdBuffer, 224 MhwVdboxJpegEncodePicState *params); 225 226 MOS_STATUS AddMfxJpegFqmCmd( 227 PMOS_COMMAND_BUFFER cmdBuffer, 228 PMHW_VDBOX_QM_PARAMS params, 229 uint32_t numQuantTables); 230 231 MOS_STATUS AddMfcJpegHuffTableStateCmd( 232 PMOS_COMMAND_BUFFER cmdBuffer, 233 PMHW_VDBOX_ENCODE_HUFF_TABLE_PARAMS params); 234 235 MOS_STATUS AddMfcJpegScanObjCmd( 236 PMOS_COMMAND_BUFFER cmdBuffer, 237 MhwVdboxJpegScanParams *params); 238 239 MOS_STATUS AddMfxDecodeVp8PicCmd( 240 PMOS_COMMAND_BUFFER cmdBuffer, 241 PMHW_VDBOX_VP8_PIC_STATE params); 242 243 MOS_STATUS AddMfxEncodeVp8PicCmd( 244 PMOS_COMMAND_BUFFER cmdBuffer, 245 PMHW_VDBOX_VP8_PIC_STATE params); 246 247 MOS_STATUS InitMfxVp8EncoderCfgCmd( 248 PMOS_RESOURCE cfgCmdBuffer, 249 PMHW_VDBOX_VP8_ENCODER_CFG_PARAMS params); 250 251 MOS_STATUS AddMfxVp8BspBufBaseAddrCmd( 252 PMOS_COMMAND_BUFFER cmdBuffer, 253 PMHW_VDBOX_VP8_BSP_BUF_BASE_ADDR_PARAMS params); 254 }; 255 256 #endif 257