1 /* 2 * Copyright (c) 2021, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_huc_itf.h 24 //! \brief MHW VDBOX HUC interface common base 25 //! \details 26 //! 27 28 #ifndef __MHW_VDBOX_HUC_ITF_H__ 29 #define __MHW_VDBOX_HUC_ITF_H__ 30 31 #include "mhw_itf.h" 32 #include "mhw_vdbox.h" 33 #include "mhw_vdbox_huc_cmdpar.h" 34 35 #define _HUC_CMD_DEF(DEF) \ 36 DEF(HUC_PIPE_MODE_SELECT); \ 37 DEF(HUC_IMEM_STATE); \ 38 DEF(HUC_DMEM_STATE); \ 39 DEF(HUC_VIRTUAL_ADDR_STATE); \ 40 DEF(HUC_START); \ 41 DEF(HUC_IND_OBJ_BASE_ADDR_STATE); \ 42 DEF(HUC_STREAM_OBJECT) 43 44 namespace mhw 45 { 46 namespace vdbox 47 { 48 namespace huc 49 { 50 struct HucMmioRegisters 51 { 52 uint32_t hucStatusRegOffset = 0; 53 uint32_t hucUKernelHdrInfoRegOffset = 0; 54 uint32_t hucStatus2RegOffset = 0; 55 uint32_t hucLoadInfoOffset = 0; 56 }; 57 58 class Itf 59 { 60 public: 61 //! 62 //! \enum CommandsNumberOfAddresses 63 //! \brief Commands number of addresses 64 //! 65 enum CommandsNumberOfAddresses 66 { 67 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 68 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 69 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 70 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, // 2 DW for 1 address field 71 MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 2, // 4 DW for 2 address fields 72 73 VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for 0 address fields 74 75 HUC_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 76 HUC_IMEM_STATE_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 77 HUC_DMEM_STATE_CMD_NUMBER_OF_ADDRESSES = 2, // 3 DW for 2 address fields 78 HUC_VIRTUAL_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 16, // 32 DW for 16 address fields 79 HUC_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 4, // 8 DW for 4 address fields 80 HUC_STREAM_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 81 HUC_START_CMD_NUMBER_OF_ADDRESSES = 0, // 0 DW for address fields 82 }; 83 84 class ParSetting 85 { 86 public: 87 virtual ~ParSetting() = default; 88 89 _HUC_CMD_DEF(_MHW_SETPAR_DEF); 90 }; 91 92 virtual ~Itf() = default; 93 94 virtual MOS_STATUS SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS settings[MOS_CODEC_RESOURCE_USAGE_END_CODEC]) = 0; 95 virtual HucMmioRegisters* GetMmioRegisters(MHW_VDBOX_NODE_IND index) = 0; 96 virtual uint32_t GetHucStatusHevcS2lFailureMask() = 0; 97 virtual uint32_t GetHucStatus2ImemLoadedMask() = 0; 98 virtual uint32_t GetHucErrorFlagsMask() = 0; 99 virtual uint32_t GetHucProductFamily() = 0; 100 virtual uint32_t GetHucStatusReEncodeMask() = 0; 101 102 _HUC_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_ITF); 103 MEDIA_CLASS_DEFINE_END(mhw__vdbox__huc__Itf) 104 }; 105 } // namespace huc 106 } // namespace vdbox 107 } // namespace mhw 108 109 #endif // __MHW_VDBOX_HUC_ITF_H__ 110