1 /*===================== begin_copyright_notice ================================== 2 3 # Copyright (c) 2024, Intel Corporation 4 5 # Permission is hereby granted, free of charge, to any person obtaining a 6 # copy of this software and associated documentation files (the "Software"), 7 # to deal in the Software without restriction, including without limitation 8 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 # and/or sell copies of the Software, and to permit persons to whom the 10 # Software is furnished to do so, subject to the following conditions: 11 12 # The above copyright notice and this permission notice shall be included 13 # in all copies or substantial portions of the Software. 14 15 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 # OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_huc_hwcmd_xe2_hpm.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details 28 //! 29 //! 30 31 // DO NOT EDIT 32 33 #ifndef __MHW_VDBOX_HUC_HWCMD_XE2_HPM_H__ 34 #define __MHW_VDBOX_HUC_HWCMD_XE2_HPM_H__ 35 36 #pragma once 37 #pragma pack(1) 38 39 #include "mhw_hwcmd.h" 40 #include <cstdint> 41 #include <cstddef> 42 #include "media_class_trace.h" 43 44 namespace mhw 45 { 46 namespace vdbox 47 { 48 namespace huc 49 { 50 namespace xe_lpm_plus_base 51 { 52 namespace v1 53 { 54 class Cmd 55 { 56 public: GetOpLength(uint32_t uiLength)57 static uint32_t GetOpLength(uint32_t uiLength) 58 { 59 return __CODEGEN_OP_LENGTH(uiLength); 60 } 61 62 //! 63 //! \brief MEMORYADDRESSATTRIBUTES 64 //! \details 65 //! This field controls the priority of arbitration used in the GAC/GAM 66 //! pipeline for this surface. It defines the attributes for VDBOX addresses 67 //! on BDW+. 68 //! 69 struct MEMORYADDRESSATTRIBUTES_CMD 70 { 71 union 72 { 73 struct 74 { 75 uint32_t Reserved0 : __CODEGEN_BITFIELD(0, 0); //!< Reserved 76 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD(1, 6); //!< Base Address - Index to Memory Object Control State (MOCS) Tables 77 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< Base Address - Arbitration Priority Control 78 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< Base Address - Memory Compression Enable 79 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10); //!< COMPRESSION_TYPE 80 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 81 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 82 uint32_t BaseAddressTiledResourceMode : __CODEGEN_BITFIELD(13, 14); //!< BASE_ADDRESS_TILED_RESOURCE_MODE 83 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 84 }; 85 uint32_t Value; 86 } DW0; 87 88 //! \name Local enumerations 89 90 //! \brief COMPRESSION_TYPE 91 //! \details 92 //! Indicates if buffer is render/media compressed. 93 enum COMPRESSION_TYPE 94 { 95 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE = 0, //!< No additional details 96 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLE = 1, //!< No additional details 97 }; 98 99 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 100 //! \details 101 //! This field controls if the Row Store is going to store inside Media 102 //! Cache (rowstore cache) or to LLC. 103 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 104 { 105 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 106 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 107 }; 108 109 //! \brief BASE_ADDRESS_TILED_RESOURCE_MODE 110 //! \details 111 //! For Media Surfaces: This field specifies the tiled resource mode. 112 enum BASE_ADDRESS_TILED_RESOURCE_MODE 113 { 114 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< TileY resources 115 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 116 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 117 }; 118 119 //! \name Initializations 120 121 //! \brief Explicit member initialization function 122 MEMORYADDRESSATTRIBUTES_CMD(); 123 124 static const size_t dwSize = 1; 125 static const size_t byteSize = 4; 126 }; 127 128 //! 129 //! \brief SPLITBASEADDRESS64BYTEALIGNED 130 //! \details 131 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 132 //! address. 133 //! 134 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 135 { 136 union 137 { 138 struct 139 { 140 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 141 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD(6, 47); //!< GraphicsAddress47-6 142 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63); //!< Reserved 143 }; 144 uint32_t Value[2]; 145 } DW0_1; 146 147 //! \name Local enumerations 148 149 //! \name Initializations 150 151 //! \brief Explicit member initialization function 152 SPLITBASEADDRESS64BYTEALIGNED_CMD(); 153 154 static const size_t dwSize = 2; 155 static const size_t byteSize = 8; 156 }; 157 158 //! 159 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 160 //! \details 161 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 162 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 163 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 164 //! 165 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 166 { 167 union 168 { 169 struct 170 { 171 uint64_t Reserved0 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 172 uint64_t Graphicsaddress4712 : __CODEGEN_BITFIELD(12, 47); //!< GraphicsAddress47-12 173 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63); //!< Reserved 174 }; 175 uint32_t Value[2]; 176 } DW0_1; 177 178 //! \name Local enumerations 179 180 //! \name Initializations 181 182 //! \brief Explicit member initialization function 183 SPLITBASEADDRESS4KBYTEALIGNED_CMD(); 184 185 static const size_t dwSize = 2; 186 static const size_t byteSize = 8; 187 }; 188 189 //! 190 //! \brief HUC_PIPE_MODE_SELECT 191 //! \details 192 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 193 //! Commands. Each HUC command has assigned a media instruction command as 194 //! defined in DWord 0, BitField 22:16. 195 //! 196 //! The HUC_PIPE_MODE_SELECT command is responsible for general pipeline 197 //! level configuration that would normally be set once for a single stream 198 //! decode and would not be modified on a frame workload basis. 199 //! 200 struct HUC_PIPE_MODE_SELECT_CMD 201 { 202 union 203 { 204 struct 205 { 206 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 207 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 208 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 209 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 210 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 211 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 212 }; 213 uint32_t Value; 214 } DW0; 215 union 216 { 217 struct 218 { 219 uint32_t Reserved32 : __CODEGEN_BITFIELD(0, 3); //!< Reserved 220 uint32_t IndirectStreamOutEnable : __CODEGEN_BITFIELD(4, 4); //!< INDIRECT_STREAM_OUT_ENABLE 221 uint32_t Reserved37 : __CODEGEN_BITFIELD(5, 31); //!< Reserved 222 }; 223 uint32_t Value; 224 } DW1; 225 union 226 { 227 struct 228 { 229 uint32_t MediaSoftResetCounterPer1000Clocks; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 230 }; 231 uint32_t Value; 232 } DW2; 233 234 //! \name Local enumerations 235 236 enum MEDIA_INSTRUCTION_COMMAND 237 { 238 MEDIA_INSTRUCTION_COMMAND_HUCPIPEMODESELECT = 0, //!< No additional details 239 }; 240 241 //! \brief MEDIA_INSTRUCTION_OPCODE 242 //! \details 243 //! Codec/Engine Name = HUP = Bh 244 enum MEDIA_INSTRUCTION_OPCODE 245 { 246 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 247 }; 248 249 enum PIPELINE_TYPE 250 { 251 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 252 }; 253 254 enum COMMAND_TYPE 255 { 256 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 257 }; 258 259 //! \brief INDIRECT_STREAM_OUT_ENABLE 260 //! \details 261 //! Enables the bitstream to be written out to memory immediately following 262 //! the output of the bit stream. The memory buffer is addressed through 263 //! the HuC Indirect Stream Out ObjectBase Address. 264 enum INDIRECT_STREAM_OUT_ENABLE 265 { 266 INDIRECT_STREAM_OUT_ENABLE_DISABLEINDIRECTSTREAMOUT = 0, //!< No additional details 267 INDIRECT_STREAM_OUT_ENABLE_ENABLEINDIRECTSTREAMOUT = 1, //!< No additional details 268 }; 269 270 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 271 //! \details 272 //! In decoder modes, this counter value specifies the number of clocks (per 273 //! 1000) of GAC inactivity 274 //! before a media soft-reset is applied to the HCP and HuC. If counter 275 //! value is set to 0, the media 276 //! soft-reset feature is disabled and no reset will occur. 277 //! In encoder modes, this counter must be set to 0 to disable media 278 //! soft reset. This feature is not 279 //! supported for the encoder. 280 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 281 { 282 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 283 }; 284 285 //! \name Initializations 286 287 //! \brief Explicit member initialization function 288 HUC_PIPE_MODE_SELECT_CMD(); 289 290 static const size_t dwSize = 3; 291 static const size_t byteSize = 12; 292 }; 293 294 //! 295 //! \brief HUC_IMEM_STATE 296 //! \details 297 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 298 //! Commands. Each HUC command has assigned a media instruction command as 299 //! defined in DWord 0, BitField 22:16. 300 //! 301 //! The HUC_IMEM_STATE command is used to fetch the HUC firmware from the 302 //! WOPCM region and load it into the HUC 96KB L2 storage RAM. The 303 //! HUC_IMEM_STATE specifies the firmware's offset in WOPCM which is a cache 304 //! line aligned 32-bit offset address. The firmware, code and data segment 305 //! size should always be less than 96KB. If its greater than 96KB then the 306 //! firmware should be broken into smaller functions so that there is no 307 //! firmware straddling case. 308 //! When the HUC_IMEM_STATE command is received, the hardware confirms that 309 //! the code has been successfully authenticated by checking the VCR 310 //! provided authentication successful signal. If this signal is asserted, 311 //! the firmware is loaded by the HUC DMA into the 96KB L2 storage RAM. Once 312 //! the firmware is loaded, the VALID IMEM LOADED bit in the HUC_STATUS2 313 //! register is asserted high in the. If the authentication signal is not 314 //! asserted, the DMA aborts the HUC_IMEM_STATE command, the firmware is not 315 //! loaded, and the VALID IMEM LOADED bit remains low. 316 //! 317 struct HUC_IMEM_STATE_CMD 318 { 319 union 320 { 321 struct 322 { 323 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 324 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 325 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 326 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 327 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 328 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 329 }; 330 uint32_t Value; 331 } DW0; 332 union 333 { 334 struct 335 { 336 uint32_t Reserved32; //!< Reserved 337 }; 338 uint32_t Value; 339 } DW1; 340 union 341 { 342 struct 343 { 344 uint32_t Reserved64; //!< Reserved 345 }; 346 uint32_t Value; 347 } DW2; 348 union 349 { 350 struct 351 { 352 uint32_t Reserved96; //!< Reserved 353 }; 354 uint32_t Value; 355 } DW3; 356 union 357 { 358 struct 359 { 360 uint32_t HucFirmwareDescriptor : __CODEGEN_BITFIELD(0, 7); //!< HUC_FIRMWARE_DESCRIPTOR 361 uint32_t Reserved136 : __CODEGEN_BITFIELD(8, 31); //!< Reserved 362 }; 363 uint32_t Value; 364 } DW4; 365 366 //! \name Local enumerations 367 368 enum MEDIA_INSTRUCTION_COMMAND 369 { 370 MEDIA_INSTRUCTION_COMMAND_HUCIMEMSTATE = 1, //!< No additional details 371 }; 372 373 //! \brief MEDIA_INSTRUCTION_OPCODE 374 //! \details 375 //! Codec/Engine Name = HUC = Bh 376 enum MEDIA_INSTRUCTION_OPCODE 377 { 378 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 379 }; 380 381 enum PIPELINE_TYPE 382 { 383 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 384 }; 385 386 enum COMMAND_TYPE 387 { 388 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 389 }; 390 391 //! \brief HUC_FIRMWARE_DESCRIPTOR 392 //! \details 393 //! This field specifies 1 of 255 firmware descriptors which describe 394 //! which firmware is be loaded in the L2 storage RAM. If the firmware 395 //! descriptor is set to zero, the HUC will not load the firmware. 396 enum HUC_FIRMWARE_DESCRIPTOR 397 { 398 HUC_FIRMWARE_DESCRIPTOR_UNNAMED0 = 0, //!< Illegal 399 }; 400 401 //! \name Initializations 402 403 //! \brief Explicit member initialization function 404 HUC_IMEM_STATE_CMD(); 405 406 static const size_t dwSize = 5; 407 static const size_t byteSize = 20; 408 }; 409 410 //! 411 //! \brief HUC_DMEM_STATE 412 //! \details 413 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 414 //! Commands. Each HUC command has assigned a media instruction command as 415 //! defined in DWord 0, BitField 22:16. 416 //! 417 //! The HUC_DMEM_STATE command is used to fetch the HUC data from the 418 //! graphics memory and load it into the HUC 96KB L2 storage RAM. The 419 //! HUC_DMEM_STATE specifies the data source base address in graphics 420 //! memory. 421 //! 422 //! When the HUC_DMEM_STATE command is received, the data is loaded by the 423 //! HUC DMA into the 96KB L2 storage RAM at the location provided in the 424 //! HUC_DMEM_STATE command. This command also specifies the length of the 425 //! data, which is specified in bytes but must be in increments of 64 byte 426 //! cache lines. 427 //! 428 struct HUC_DMEM_STATE_CMD 429 { 430 union 431 { 432 struct 433 { 434 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 435 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 436 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 437 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 438 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 439 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 440 }; 441 uint32_t Value; 442 } DW0; 443 SPLITBASEADDRESS64BYTEALIGNED_CMD HucDataSourceBaseAddress; //!< DW1..2, HUC Data Source - Base Address 444 MEMORYADDRESSATTRIBUTES_CMD HucDataSourceAttributes; //!< DW3, HUC Data Source - Attributes 445 union 446 { 447 struct 448 { 449 uint32_t Reserved128 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 450 uint32_t HucDataDestinationBaseAddress : __CODEGEN_BITFIELD(6, 16); //!< HUC Data Destination Base Address 451 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 452 }; 453 uint32_t Value; 454 } DW4; 455 union 456 { 457 struct 458 { 459 uint32_t Reserved160 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 460 uint32_t HucDataLength : __CODEGEN_BITFIELD(6, 16); //!< HUC Data Length 461 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31); //!< Reserved 462 }; 463 uint32_t Value; 464 } DW5; 465 466 //! \name Local enumerations 467 468 enum MEDIA_INSTRUCTION_COMMAND 469 { 470 MEDIA_INSTRUCTION_COMMAND_HUCDMEMSTATE = 2, //!< No additional details 471 }; 472 473 //! \brief MEDIA_INSTRUCTION_OPCODE 474 //! \details 475 //! Codec/Engine Name = HUC = Bh 476 enum MEDIA_INSTRUCTION_OPCODE 477 { 478 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 479 }; 480 481 enum PIPELINE_TYPE 482 { 483 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 484 }; 485 486 enum COMMAND_TYPE 487 { 488 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 489 }; 490 491 //! \name Initializations 492 493 //! \brief Explicit member initialization function 494 HUC_DMEM_STATE_CMD(); 495 496 static const size_t dwSize = 6; 497 static const size_t byteSize = 24; 498 }; 499 500 //! 501 //! \brief HUC_CFG_STATE 502 //! \details 503 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 504 //! Commands. Each HUC command has assigned a media instruction command as 505 //! defined in DWord 0, BitField 22:16. 506 //! 507 //! The HUC_CFG_STATE command is used to force the P24C (MinuteIA) into a 508 //! reset condition as well as forcing it out of a reset condition. This 509 //! command is not normally required since the hardware will handle placing 510 //! the P24C into a reset condition and releasing it from reset, but there 511 //! may be conditions that require a forced reset. 512 //! 513 struct HUC_CFG_STATE_CMD 514 { 515 union 516 { 517 struct 518 { 519 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 520 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 521 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 522 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 523 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 524 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 525 }; 526 uint32_t Value; 527 } DW0; 528 union 529 { 530 struct 531 { 532 uint32_t P24CMinuteia : __CODEGEN_BITFIELD(0, 0); //!< P24C_MINUTEIA 533 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 534 }; 535 uint32_t Value; 536 } DW1; 537 538 //! \name Local enumerations 539 540 enum MEDIA_INSTRUCTION_COMMAND 541 { 542 MEDIA_INSTRUCTION_COMMAND_HUCCFGSTATE = 3, //!< No additional details 543 }; 544 545 //! \brief MEDIA_INSTRUCTION_OPCODE 546 //! \details 547 //! Codec/Engine Name = HUC = Bh 548 enum MEDIA_INSTRUCTION_OPCODE 549 { 550 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 551 }; 552 553 enum PIPELINE_TYPE 554 { 555 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 556 }; 557 558 enum COMMAND_TYPE 559 { 560 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 561 }; 562 563 enum P24C_MINUTEIA 564 { 565 P24C_MINUTEIA_NORMALOPERATION = 0, //!< No reset. 566 P24C_MINUTEIA_FORCERESET = 1, //!< No additional details 567 }; 568 569 //! \name Initializations 570 571 //! \brief Explicit member initialization function 572 HUC_CFG_STATE_CMD(); 573 574 static const size_t dwSize = 2; 575 static const size_t byteSize = 8; 576 }; 577 578 //! 579 //! \brief HUC_VIRTUAL_ADDR_REGION 580 //! \details 581 //! 582 //! 583 struct HUC_VIRTUAL_ADDR_REGION_CMD 584 { 585 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucSurfaceBaseAddressVirtualaddrregion015; //!< DW0..2, HUC Surface Base Address (VirtualAddrRegion[0-15]) 586 MEMORYADDRESSATTRIBUTES_CMD HucSurfaceVirtualaddrregion015; //!< DW0..2, HUC Surface (VirtualAddrRegion[0-15]) 587 588 //! \name Local enumerations 589 590 //! \name Initializations 591 592 //! \brief Explicit member initialization function 593 HUC_VIRTUAL_ADDR_REGION_CMD(); 594 595 static const size_t dwSize = 3; 596 static const size_t byteSize = 12; 597 }; 598 599 //! 600 //! \brief HUC_VIRTUAL_ADDR_STATE 601 //! \details 602 //! HUC is selected with the Media Instruction Opcode "Bh" for all HUC 603 //! Commands. Each HUC command has assigned a media instruction command as 604 //! defined in DWord 0, BitField 22:16. 605 //! 606 //! The HUC_VIRTUAL_ADDR_STATE command is used to define the 48-bit HUC 607 //! Surface Base Address and HUC Surface for each region. 608 //! 609 struct HUC_VIRTUAL_ADDR_STATE_CMD 610 { 611 union 612 { 613 struct 614 { 615 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 616 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 617 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 618 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 619 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 620 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 621 }; 622 uint32_t Value; 623 } DW0; 624 HUC_VIRTUAL_ADDR_REGION_CMD HucVirtualAddressRegion[16]; //!< DW1..48, Huc Virtual Address Region 625 626 //! \name Local enumerations 627 628 enum MEDIA_INSTRUCTION_COMMAND 629 { 630 MEDIA_INSTRUCTION_COMMAND_HUCVIRTUALADDRSTATE = 4, //!< No additional details 631 }; 632 633 //! \brief MEDIA_INSTRUCTION_OPCODE 634 //! \details 635 //! Codec/Engine Name = HUC = Bh 636 enum MEDIA_INSTRUCTION_OPCODE 637 { 638 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 639 }; 640 641 enum PIPELINE_TYPE 642 { 643 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 644 }; 645 646 enum COMMAND_TYPE 647 { 648 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 649 }; 650 651 //! \name Initializations 652 653 //! \brief Explicit member initialization function 654 HUC_VIRTUAL_ADDR_STATE_CMD(); 655 656 static const size_t dwSize = 49; 657 static const size_t byteSize = 196; 658 }; 659 660 //! 661 //! \brief HUC_IND_OBJ_BASE_ADDR_STATE 662 //! \details 663 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 664 //! Commands. Each HUC command has assigned a media instruction command as 665 //! defined in DWord 0, BitField 22:16. 666 //! 667 //! The HUC_IND_OBJ_BASE_ADDR_STATE command is used to define the indirect 668 //! object base address of the stream in graphics memory. This is a frame 669 //! level command. 670 //! 671 struct HUC_IND_OBJ_BASE_ADDR_STATE_CMD 672 { 673 union 674 { 675 struct 676 { 677 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 678 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 679 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 680 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 681 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 682 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 683 }; 684 uint32_t Value; 685 } DW0; 686 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamInObjectbaseAddress; //!< DW1..2, HUC Indirect Stream In ObjectBase Address 687 MEMORYADDRESSATTRIBUTES_CMD HucIndirectStreamInObjectbaseAttributes; //!< DW3, HUC Indirect Stream In ObjectBase Attributes 688 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamInObjectaccessUpperBound; //!< DW4..5, HUC Indirect Stream In ObjectAccess Upper Bound 689 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamOutObjectbaseAddress; //!< DW6..7, HUC Indirect Stream Out ObjectBase Address 690 MEMORYADDRESSATTRIBUTES_CMD HucIndirectStreamOutObjectbaseAttributes; //!< DW8, HUC Indirect Stream Out ObjectBase Attributes 691 SPLITBASEADDRESS4KBYTEALIGNED_CMD HucIndirectStreamOutObjectaccessUpperBound; //!< DW9..10, HUC Indirect Stream Out ObjectAccess Upper Bound 692 693 //! \name Local enumerations 694 695 enum MEDIA_INSTRUCTION_COMMAND 696 { 697 MEDIA_INSTRUCTION_COMMAND_HUCINDOBJBASEADDRSTATE = 5, //!< No additional details 698 }; 699 700 //! \brief MEDIA_INSTRUCTION_OPCODE 701 //! \details 702 //! Codec/Engine Name = HUC = Bh 703 enum MEDIA_INSTRUCTION_OPCODE 704 { 705 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 706 }; 707 708 enum PIPELINE_TYPE 709 { 710 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 711 }; 712 713 enum COMMAND_TYPE 714 { 715 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 716 }; 717 718 //! \name Initializations 719 720 //! \brief Explicit member initialization function 721 HUC_IND_OBJ_BASE_ADDR_STATE_CMD(); 722 723 static const size_t dwSize = 11; 724 static const size_t byteSize = 44; 725 }; 726 727 //! 728 //! \brief HUC_STREAM_OBJECT 729 //! \details 730 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 731 //! Commands. Each HUC command has assigned a media instruction command as 732 //! defined in DWord 0, BitField 22:16. 733 //! 734 //! The HUC_STREAM_OBJECT command is used to define the bit stream address 735 //! offset to the Stream Indirect Object base Address and the length of the 736 //! bit stream. The bitstream buffer the HUC operates upon is specified 737 //! through indirect addressing. 738 //! 739 struct HUC_STREAM_OBJECT_CMD 740 { 741 union 742 { 743 struct 744 { 745 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 746 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 747 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 748 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 749 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 750 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 751 }; 752 uint32_t Value; 753 } DW0; 754 union 755 { 756 struct 757 { 758 uint32_t IndirectStreamInDataLength; //!< Indirect Stream In Data Length 759 }; 760 uint32_t Value; 761 } DW1; 762 union 763 { 764 struct 765 { 766 uint32_t IndirectStreamInStartAddress : __CODEGEN_BITFIELD(0, 28); //!< Indirect Stream In Start Address 767 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 30); //!< Reserved 768 uint32_t HucProcessing : __CODEGEN_BITFIELD(31, 31); //!< HUC_PROCESSING 769 }; 770 uint32_t Value; 771 } DW2; 772 union 773 { 774 struct 775 { 776 uint32_t IndirectStreamOutStartAddress : __CODEGEN_BITFIELD(0, 28); //!< Indirect Stream Out Start Address 777 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31); //!< Reserved 778 }; 779 uint32_t Value; 780 } DW3; 781 union 782 { 783 struct 784 { 785 uint32_t StartCodeByte0 : __CODEGEN_BITFIELD(0, 7); //!< Start Code Byte [0] 786 uint32_t StartCodeByte1 : __CODEGEN_BITFIELD(8, 15); //!< Start Code Byte [1] 787 uint32_t StartCodeByte2 : __CODEGEN_BITFIELD(16, 23); //!< Start Code Byte [2] 788 uint32_t StartCodeSearchEngine : __CODEGEN_BITFIELD(24, 24); //!< START_CODE_SEARCH_ENGINE 789 uint32_t EmulationPreventionByteRemoval : __CODEGEN_BITFIELD(25, 25); //!< EMULATION_PREVENTION_BYTE_REMOVAL 790 uint32_t StreamOut : __CODEGEN_BITFIELD(26, 26); //!< STREAM_OUT 791 uint32_t Drmlengthmode : __CODEGEN_BITFIELD(27, 28); //!< DRMLENGTHMODE 792 uint32_t HucBitstreamEnable : __CODEGEN_BITFIELD(29, 29); //!< HUC_BITSTREAM_ENABLE 793 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31); //!< Reserved 794 }; 795 uint32_t Value; 796 } DW4; 797 798 //! \name Local enumerations 799 800 enum MEDIA_INSTRUCTION_COMMAND 801 { 802 MEDIA_INSTRUCTION_COMMAND_HUCSTREAMOBJECT = 32, //!< No additional details 803 }; 804 805 //! \brief MEDIA_INSTRUCTION_OPCODE 806 //! \details 807 //! Codec/Engine Name = HUC = Bh 808 enum MEDIA_INSTRUCTION_OPCODE 809 { 810 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 811 }; 812 813 enum PIPELINE_TYPE 814 { 815 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 816 }; 817 818 enum COMMAND_TYPE 819 { 820 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 821 }; 822 823 //! \brief HUC_PROCESSING 824 //! \details 825 //! Disables the HEVC Decoder CABAC engine to prevent it from starting 826 //! while the HuC is processing. Must be set to "1" for HUC processing so 827 //! that the stream is directed to the HuC and not the CABAC engine. 828 enum HUC_PROCESSING 829 { 830 HUC_PROCESSING_DISABLE = 1, //!< No additional details 831 }; 832 833 enum START_CODE_SEARCH_ENGINE 834 { 835 START_CODE_SEARCH_ENGINE_DISABLE = 0, //!< Bypass Start Code Search Engine 836 START_CODE_SEARCH_ENGINE_ENABLE = 1, //!< Enables the start code search engine to stop on every third byte start code defined by Start Code Byte [2:0] defined in this DWord. 837 }; 838 839 enum EMULATION_PREVENTION_BYTE_REMOVAL 840 { 841 EMULATION_PREVENTION_BYTE_REMOVAL_DISABLE = 0, //!< Bypass Emulation Prevention Byte Removal. 842 EMULATION_PREVENTION_BYTE_REMOVAL_ENABLE = 1, //!< Emulation prevention bytes will be removed after the start code search engine. 843 }; 844 845 //! \brief STREAM_OUT 846 //! \details 847 //! Enables the stream output. 848 enum STREAM_OUT 849 { 850 STREAM_OUT_DISABLE = 0, //!< Disable the stream output. 851 STREAM_OUT_ENABLE = 1, //!< Enable the stream output. 852 }; 853 854 enum DRMLENGTHMODE 855 { 856 DRMLENGTHMODE_STARTCODEMODE = 0, //!< Stops on a start code 857 DRMLENGTHMODE_LENGTHMODE = 1, //!< Stops after a number of bytes are reached in the length counter 858 }; 859 860 //! \brief HUC_BITSTREAM_ENABLE 861 //! \details 862 //! style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 863 //! line-height: normal;">Enables the bitstream to be sent to the HuC 864 enum HUC_BITSTREAM_ENABLE 865 { 866 HUC_BITSTREAM_ENABLE_DISABLE = 0, //!< No additional details 867 HUC_BITSTREAM_ENABLE_ENABLE = 1, //!< No additional details 868 }; 869 870 //! \name Initializations 871 872 //! \brief Explicit member initialization function 873 HUC_STREAM_OBJECT_CMD(); 874 875 static const size_t dwSize = 5; 876 static const size_t byteSize = 20; 877 }; 878 879 //! 880 //! \brief HUC_START 881 //! \details 882 //! The HUC is selected with the Media Instruction Opcode "Bh" for all HUC 883 //! Commands. Each HUC command has assigned a media instruction command as 884 //! defined in DWord 0, BitField 22:16. 885 //! 886 struct HUC_START_CMD 887 { 888 union 889 { 890 struct 891 { 892 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 11); //!< DWORD_LENGTH 893 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15); //!< Reserved 894 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22); //!< MEDIA_INSTRUCTION_COMMAND 895 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26); //!< MEDIA_INSTRUCTION_OPCODE 896 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28); //!< PIPELINE_TYPE 897 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 898 }; 899 uint32_t Value; 900 } DW0; 901 union 902 { 903 struct 904 { 905 uint32_t Laststreamobject : __CODEGEN_BITFIELD(0, 0); //!< LASTSTREAMOBJECT 906 uint32_t Reserved33 : __CODEGEN_BITFIELD(1, 31); //!< Reserved 907 }; 908 uint32_t Value; 909 } DW1; 910 911 //! \name Local enumerations 912 913 enum MEDIA_INSTRUCTION_COMMAND 914 { 915 MEDIA_INSTRUCTION_COMMAND_HUCSTART = 33, //!< No additional details 916 }; 917 918 //! \brief MEDIA_INSTRUCTION_OPCODE 919 //! \details 920 //! Codec/Engine Name = HUC = Bh 921 enum MEDIA_INSTRUCTION_OPCODE 922 { 923 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 11, //!< No additional details 924 }; 925 926 enum PIPELINE_TYPE 927 { 928 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 929 }; 930 931 enum COMMAND_TYPE 932 { 933 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 934 }; 935 936 enum LASTSTREAMOBJECT 937 { 938 LASTSTREAMOBJECT_NOTLASTSTREAMOBJECT = 0, //!< Not the last stream object in the workload. 939 LASTSTREAMOBJECT_LASTSTREAMOBJECT = 1, //!< Last stream object in the workload. 940 }; 941 942 //! \name Initializations 943 944 //! \brief Explicit member initialization function 945 HUC_START_CMD(); 946 947 static const size_t dwSize = 2; 948 static const size_t byteSize = 8; 949 }; 950 951 MEDIA_CLASS_DEFINE_END(mhw__vdbox__huc__xe_lpm_plus_base__v1__Cmd) 952 }; 953 } // namespace v1 954 } // namespace xe_lpm_plus_base 955 } // namespace huc 956 } // namespace vdbox 957 } // namespace mhw 958 959 #pragma pack() 960 961 #endif // __MHW_VDBOX_HUC_HWCMD_XE2_HPM_H__ 962