1 /*===================== begin_copyright_notice ================================== 2 3 # Copyright (c) 2024, Intel Corporation 4 # 5 # Permission is hereby granted, free of charge, to any person obtaining a 6 # copy of this software and associated documentation files (the "Software"), 7 # to deal in the Software without restriction, including without limitation 8 # the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 # and/or sell copies of the Software, and to permit persons to whom the 10 # Software is furnished to do so, subject to the following conditions: 11 # 12 # The above copyright notice and this permission notice shall be included 13 # in all copies or substantial portions of the Software. 14 # 15 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 # OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_hcp_hwcmd_xe2_hpm.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of xe2_hpm as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 31 // DO NOT EDIT 32 33 #ifndef __MHW_VDBOX_HCP_HWCMD_XE2_HPM_H__ 34 #define __MHW_VDBOX_HCP_HWCMD_XE2_HPM_H__ 35 36 #include "mhw_hwcmd.h" 37 38 #pragma once 39 #pragma pack(1) 40 41 #include <cstdint> 42 #include <cstddef> 43 44 namespace mhw 45 { 46 namespace vdbox 47 { 48 namespace hcp 49 { 50 namespace xe_lpm_plus_base 51 { 52 namespace v1 53 { 54 class Cmd 55 { 56 public: 57 GetOpLength(uint32_t uiLength)58 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 59 60 //! 61 //! \brief MEMORYADDRESSATTRIBUTES 62 //! \details 63 //! This field controls the priority of arbitration used in the GAC/GAM 64 //! pipeline for this surface. It defines the attributes for VDBOX addresses 65 //! on BDW+. 66 //! 67 struct MEMORYADDRESSATTRIBUTES_CMD 68 { 69 union 70 { 71 struct 72 { 73 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 74 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Base Address - Index to Memory Object Control State (MOCS) Tables 75 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Base Address - Arbitration Priority Control 76 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Base Address - Memory Compression Enable 77 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< COMPRESSION_TYPE 78 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 79 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 80 uint32_t TileMode : __CODEGEN_BITFIELD(13, 14) ; //!< TILE_MODE 81 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 82 }; 83 uint32_t Value; 84 } DW0; 85 86 //! \name Local enumerations 87 88 //! \brief COMPRESSION_TYPE 89 //! \details 90 //! Indicates if buffer is render/media compressed. 91 enum COMPRESSION_TYPE 92 { 93 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE = 0, //!< No additional details 94 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLE = 1, //!< No additional details 95 }; 96 97 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 98 //! \details 99 //! This field controls if the Row Store is going to store inside Media 100 //! Cache (rowstore cache) or to LLC. 101 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 102 { 103 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 104 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 105 }; 106 107 //! \brief BASE_ADDRESS_TILED_RESOURCE_MODE 108 //! \details 109 //! <b>For Media Surfaces:</b> This field specifies the tiled resource mode. 110 enum BASE_ADDRESS_TILED_RESOURCE_MODE 111 { 112 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< TileY resources 113 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 114 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 115 }; 116 117 //! \name Initializations 118 119 //! \brief Explicit member initialization function MEMORYADDRESSATTRIBUTES_CMDMEMORYADDRESSATTRIBUTES_CMD120 MEMORYADDRESSATTRIBUTES_CMD() 121 { 122 DW0.Value = 0x00000000; 123 //DW0.CompressionType = COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE; 124 //DW0.BaseAddressRowStoreScratchBufferCacheSelect = BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0; 125 //DW0.BaseAddressTiledResourceMode = BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE; 126 } 127 128 static const size_t dwSize = 1; 129 static const size_t byteSize = 4; 130 }; 131 132 //! 133 //! \brief SPLITBASEADDRESS64BYTEALIGNED 134 //! \details 135 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 136 //! address. 137 //! 138 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 139 { 140 union 141 { 142 struct 143 { 144 uint64_t Reserved64 : __CODEGEN_BITFIELD(0, 5); //!< Reserved 145 uint64_t BaseAddress : __CODEGEN_BITFIELD(6, 47); //!< Base Address 146 uint64_t Reserved121 : __CODEGEN_BITFIELD(48, 63); //!< Reserved 147 }; 148 uint32_t Value[2]; 149 } DW0_1; 150 151 //! \name Local enumerations 152 153 //! \name Initializations 154 155 //! \brief Explicit member initialization function SPLITBASEADDRESS64BYTEALIGNED_CMDSPLITBASEADDRESS64BYTEALIGNED_CMD156 SPLITBASEADDRESS64BYTEALIGNED_CMD() 157 { 158 DW0_1.Value[0] = DW0_1.Value[1] = 0x00000000; 159 } 160 161 static const size_t dwSize = 2; 162 static const size_t byteSize = 8; 163 }; 164 165 //! 166 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 167 //! \details 168 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 169 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 170 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 171 //! 172 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 173 { 174 union 175 { 176 struct 177 { 178 uint64_t Reserved64 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 179 uint64_t BaseAddress : __CODEGEN_BITFIELD(12, 47); //!< Base Address 180 uint64_t Reserved121 : __CODEGEN_BITFIELD(48, 63); //!< Reserved 181 }; 182 uint32_t Value[2]; 183 } DW0_1; 184 185 //! \name Local enumerations 186 187 //! \name Initializations 188 189 //! \brief Explicit member initialization function SPLITBASEADDRESS4KBYTEALIGNED_CMDSPLITBASEADDRESS4KBYTEALIGNED_CMD190 SPLITBASEADDRESS4KBYTEALIGNED_CMD() 191 { 192 DW0_1.Value[0] = DW0_1.Value[1] = 0x00000000; 193 } 194 195 static const size_t dwSize = 2; 196 static const size_t byteSize = 8; 197 }; 198 199 //! 200 //! \brief HCP_PIPE_MODE_SELECT 201 //! \details 202 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 203 //! Commands. Each HCP command has assigned a media instruction command as 204 //! defined in DWord 0, BitField 22:16. 205 //! 206 //! The workload for the HCP is based upon a single frame decode. There are 207 //! no states saved between frame decodes in the HCP. Once the bit stream 208 //! DMA is configured with the HCP_BSD_OBJECT command, and the bit stream is 209 //! presented to the HCP, the frame decode will begin. The 210 //! HCP_PIPE_MODE_SELECT command is responsible for general pipeline level 211 //! configuration that would normally be set once for a single stream encode 212 //! or decode and would not be modified on a frame workload basis. This is a 213 //! picture level state command and is shared by both encoding and decoding 214 //! processes. 215 //! 216 struct HCP_PIPE_MODE_SELECT_CMD 217 { 218 union 219 { 220 struct 221 { 222 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 223 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 224 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 225 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 226 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 227 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 228 }; 229 uint32_t Value; 230 } DW0; 231 union 232 { 233 struct 234 { 235 uint32_t CodecSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< CODEC_SELECT 236 uint32_t DeblockerStreamoutEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< DEBLOCKER_STREAMOUT_ENABLE 237 uint32_t PakPipelineStreamoutEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< PAK_PIPELINE_STREAMOUT_ENABLE 238 uint32_t PicStatusErrorReportEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< PIC_STATUSERROR_REPORT_ENABLE 239 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 240 uint32_t CodecStandardSelect : __CODEGEN_BITFIELD( 5, 7) ; //!< CODEC_STANDARD_SELECT 241 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 242 uint32_t AdvancedRateControlEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Advanced Rate Control Enable 243 uint32_t VdencMode : __CODEGEN_BITFIELD(10, 10) ; //!< VDEnc_Mode 244 uint32_t RdoqEnabledFlag : __CODEGEN_BITFIELD(11, 11) ; //!< RDOQ_ENABLED_FLAG 245 uint32_t PakFrameLevelStreamoutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< PAK Frame Level StreamOut enable 246 uint32_t MultiEngineMode : __CODEGEN_BITFIELD(13, 14) ; //!< MULTI_ENGINE_MODE 247 uint32_t PipeWorkingMode : __CODEGEN_BITFIELD(15, 16) ; //!< PIPE_WORKING_MODE 248 uint32_t TileBasedEngine : __CODEGEN_BITFIELD(17, 17) ; //!< Tile Based Engine 249 uint32_t PrefetchDisable : __CODEGEN_BITFIELD(18, 18) ; //!< Prefetch Disable 250 uint32_t Vp9DynamicScalingEnable : __CODEGEN_BITFIELD(19, 19) ; //!< VP9 Dynamic scaling enable 251 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 252 uint32_t MotionCompMemoryTrackerCounterEnable : __CODEGEN_BITFIELD(23, 23) ; //!< Motion Comp Memory Tracker Counter Enable 253 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 254 }; 255 uint32_t Value; 256 } DW1; 257 union 258 { 259 struct 260 { 261 uint32_t MediaSoftResetCounterPer1000Clocks ; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 262 }; 263 uint32_t Value; 264 } DW2; 265 union 266 { 267 struct 268 { 269 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 270 }; 271 uint32_t Value; 272 } DW3; 273 union 274 { 275 struct 276 { 277 uint32_t Reserved128 ; //!< Reserved 278 }; 279 uint32_t Value; 280 } DW4; 281 union 282 { 283 struct 284 { 285 uint32_t Reserved160 ; //!< Reserved 286 }; 287 uint32_t Value; 288 } DW5; 289 union 290 { 291 struct 292 { 293 uint32_t PhaseIndicator : __CODEGEN_BITFIELD( 0, 1) ; //!< PHASE_INDICATOR 294 uint32_t HevcSeparateTileProgramming : __CODEGEN_BITFIELD( 2, 2) ; //!< HEVC Separate Tile Programming 295 uint32_t FrameReconstructionDisable : __CODEGEN_BITFIELD( 3, 3) ; //!< Frame reconstruction disable 296 uint32_t Reserved196 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 297 }; 298 uint32_t Value; 299 } DW6; 300 301 //! \name Local enumerations 302 303 enum MEDIA_INSTRUCTION_COMMAND 304 { 305 MEDIA_INSTRUCTION_COMMAND_HCPPIPEMODESELECT = 0, //!< No additional details 306 }; 307 308 //! \brief MEDIA_INSTRUCTION_OPCODE 309 //! \details 310 //! Codec/Engine Name = HCP = 7h 311 enum MEDIA_INSTRUCTION_OPCODE 312 { 313 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 314 }; 315 316 enum PIPELINE_TYPE 317 { 318 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 319 }; 320 321 enum COMMAND_TYPE 322 { 323 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 324 }; 325 326 enum CODEC_SELECT 327 { 328 CODEC_SELECT_DECODE = 0, //!< No additional details 329 CODEC_SELECT_ENCODE = 1, //!< No additional details 330 }; 331 332 //! \brief DEBLOCKER_STREAMOUT_ENABLE 333 //! \details 334 //! Deblocker Streamout Enable not currently supported for Encode or Decode 335 enum DEBLOCKER_STREAMOUT_ENABLE 336 { 337 DEBLOCKER_STREAMOUT_ENABLE_DISABLE = 0, //!< Disable deblocker-only parameter streamout 338 DEBLOCKER_STREAMOUT_ENABLE_ENABLE = 1, //!< Enable deblocker-only parameter streamout 339 }; 340 341 //! \brief PAK_PIPELINE_STREAMOUT_ENABLE 342 //! \details 343 //! Pipeline Streamout Enable is only defined for encode. It is ignored for 344 //! decode. 345 enum PAK_PIPELINE_STREAMOUT_ENABLE 346 { 347 PAK_PIPELINE_STREAMOUT_ENABLE_DISABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 0, //!< No additional details 348 PAK_PIPELINE_STREAMOUT_ENABLE_ENABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 1, //!< No additional details 349 }; 350 351 enum PIC_STATUSERROR_REPORT_ENABLE 352 { 353 PIC_STATUSERROR_REPORT_ENABLE_DISABLE = 0, //!< Disable status/error reporting 354 PIC_STATUSERROR_REPORT_ENABLE_ENABLE = 1, //!< Status/Error reporting is written out once per picture. The Pic Status/Error Report ID in DWord3along with the status/error status bits are packed into one cache line and written to theStatus/Error Buffer address in the HCP_PIPE_BUF_ADDR_STATE command. Must be zero for encoder mode. 355 }; 356 357 enum CODEC_STANDARD_SELECT 358 { 359 CODEC_STANDARD_SELECT_HEVC = 0, //!< No additional details 360 CODEC_STANDARD_SELECT_VP9 = 1, //!< No additional details 361 }; 362 363 enum RDOQ_ENABLED_FLAG 364 { 365 RDOQ_ENABLED_FLAG_DISABLED = 0, //!< No additional details 366 RDOQ_ENABLED_FLAG_ENABLED = 1, //!< No additional details 367 }; 368 369 //! \brief MULTI_ENGINE_MODE 370 //! \details 371 //! <p>This indicates the current pipe is in single pipe mode or if in 372 //! scalable mode is in left/right/middle pipe in multi-engine mode.</p> 373 enum MULTI_ENGINE_MODE 374 { 375 MULTI_ENGINE_MODE_SINGLEENGINEMODEORCABACFEONLYDECODEMODE = 0, //!< This is for single engine mode (legacy) OR CABAC FE only decode mode During HEVC Decoder Scalability Real Tile Mode, for the last phase, it is possible to have single tile column left. In this case, it should be programmed with pipe as a single engine mode (using this value).For example, for 9 tile column running on 4 pipes. The first two phases will use all 4 pipes and finish 8 tile column. The remaining one column will be processed as last third phase as single tile column. 376 MULTI_ENGINE_MODE_PIPEISTHELEFTENGINEINAMULTI_ENGINEMODE = 1, //!< Current pipe is the most left engine while running in scalable multi-engine mode 377 MULTI_ENGINE_MODE_PIPEISTHERIGHTENGINEINAMULTI_ENGINEMODE = 2, //!< Current pipe is the most right engine while running in scalable multi-engine mode 378 MULTI_ENGINE_MODE_PIPEISONEOFTHEMIDDLEENGINEINAMULTI_ENGINEMODE = 3, //!< Current pipe is in one of the middle engine while running in scalable multi-engine mode 379 }; 380 381 //! \brief PIPE_WORKING_MODE 382 //! \details 383 //! <p>This programs the working mode for HCP pipe.</p> 384 enum PIPE_WORKING_MODE 385 { 386 PIPE_WORKING_MODE_LEGACYDECODERENCODERMODE_SINGLEPIPE = 0, //!< This is for single pipe mode non-scalable mode. It is used by both decoder and encoder. 387 PIPE_WORKING_MODE_CABACFEONLYDECODEMODE_SINGLECABACPIPE = 1, //!< This is for the single CABAC FE only in decoder mode. This will be only run CABAC and streamout syntax element. 388 PIPE_WORKING_MODE_DECODERBEONLYORENCODERMODE_SCALABLEMULTI_PIPE = 2, //!< This is for multiple-pipe scalable mode. In decoder, it is only on BE reconstruction. In ecoder, it is for PAK. 389 PIPE_WORKING_MODE_DECODERSCALABLEMODEWITHCABACINREALTILES_SCALABLEMULTI_PIPE = 3, //!< This is for multiple-pipe scalable mode decoder mode in real tiles. CABAC and reconstruction will run together. Each pipes will run in real tiles vertically. 390 }; 391 392 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 393 //! \details 394 //! In decoder modes, this counter value specifies the number of clocks (per 395 //! 1000) of GAC inactivity 396 //! before a media soft-reset is applied to the HCP and HuC. If counter 397 //! value is set to 0, the media 398 //! soft-reset feature is disabled and no reset will occur. 399 //! <p>In encoder modes, this counter must be set to 0 to disable media 400 //! soft reset. This feature is not 401 //! supported for the encoder.</p> 402 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 403 { 404 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 405 }; 406 407 //! \brief PIC_STATUSERROR_REPORT_ID 408 //! \details 409 //! The Pic Status/Error Report ID is a unique 32-bit unsigned integer 410 //! assigned to each picture 411 //! status/error output. Must be zero for encoder mode. 412 enum PIC_STATUSERROR_REPORT_ID 413 { 414 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 415 }; 416 417 //! \brief PHASE_INDICATOR 418 //! \details 419 //! <p>This is used to indicate whether this is first, middle or last phase 420 //! of programming during Real-Tile Decoder Mode. Since HEVC can have upto 421 //! 20 tile columns, maximum 10 phases are possible during 2 VDbox scalable 422 //! mode. This is used by hardware to know if the current programming is 423 //! first or last phases.</p> 424 //! <p>This field is ignored (programmed to 0) for other modes other than 425 //! HEVC Real-Tile Decoder Mode.</p> 426 enum PHASE_INDICATOR 427 { 428 PHASE_INDICATOR_FIRSTPHASE = 0, //!< No additional details 429 PHASE_INDICATOR_MIDDLEPHASE = 1, //!< No additional details 430 PHASE_INDICATOR_LASTPHASE = 2, //!< No additional details 431 }; 432 433 //! \name Initializations 434 435 //! \brief Explicit member initialization function HCP_PIPE_MODE_SELECT_CMDHCP_PIPE_MODE_SELECT_CMD436 HCP_PIPE_MODE_SELECT_CMD() 437 { 438 DW0.Value = 0x73800005; 439 //DW0.DwordLength = GetOpLength(dwSize); 440 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPIPEMODESELECT; 441 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 442 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 443 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 444 445 DW1.Value = 0x00000000; 446 //DW1.CodecSelect = CODEC_SELECT_DECODE; 447 //DW1.DeblockerStreamoutEnable = DEBLOCKER_STREAMOUT_ENABLE_DISABLE; 448 //DW1.PakPipelineStreamoutEnable = PAK_PIPELINE_STREAMOUT_ENABLE_DISABLEPIPELINESTATESANDPARAMETERSSTREAMOUT; 449 //DW1.PicStatusErrorReportEnable = PIC_STATUSERROR_REPORT_ENABLE_DISABLE; 450 //DW1.CodecStandardSelect = CODEC_STANDARD_SELECT_HEVC; 451 //DW1.RdoqEnabledFlag = RDOQ_ENABLED_FLAG_DISABLED; 452 //DW1.MultiEngineMode = MULTI_ENGINE_MODE_SINGLEENGINEMODEORCABACFEONLYDECODEMODE; 453 //DW1.PipeWorkingMode = PIPE_WORKING_MODE_LEGACYDECODERENCODERMODE_SINGLEPIPE; 454 455 DW2.Value = 0x00000000; 456 //DW2.MediaSoftResetCounterPer1000Clocks = MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE; 457 458 DW3.Value = 0x00000000; 459 //DW3.PicStatusErrorReportId = PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED; 460 461 DW4.Value = 0x00000000; 462 463 DW5.Value = 0x00000000; 464 465 DW6.Value = 0x00000000; 466 //DW6.PhaseIndicator = PHASE_INDICATOR_FIRSTPHASE; 467 } 468 469 static const size_t dwSize = 7; 470 static const size_t byteSize = 28; 471 }; 472 473 //! 474 //! \brief HCP_SURFACE_STATE 475 //! \details 476 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 477 //! Commands. Each HCP command has assigned a media instruction command as 478 //! defined in DWord 0, BitField 22:16. 479 //! 480 //! The HCP_SURFACE_STATE command is responsible for defining the frame 481 //! buffer pitch and the offset of the chroma component. This is a picture 482 //! level state command and is shared by both encoding and decoding 483 //! processes. Note : Only NV12 and Tile Y are being supported for HEVC. 484 //! Hence full pitch and interleaved UV is always in use. U and V Xoffset 485 //! must be set to 0; U and V Yoffset must be 16-pixel aligned. This Surface 486 //! State is not the same as that of the 3D engine and of the MFX pipeline. 487 //! 488 struct HCP_SURFACE_STATE_CMD 489 { 490 union 491 { 492 struct 493 { 494 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 495 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 496 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 497 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 498 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 499 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 500 }; 501 uint32_t Value; 502 } DW0; 503 union 504 { 505 struct 506 { 507 uint32_t SurfacePitchMinus1 : __CODEGEN_BITFIELD( 0, 16) ; //!< Surface Pitch Minus1 508 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 27) ; //!< Reserved 509 uint32_t SurfaceId : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_ID 510 }; 511 uint32_t Value; 512 } DW1; 513 union 514 { 515 struct 516 { 517 uint32_t YOffsetForUCbInPixel : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) in pixel 518 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 519 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 520 }; 521 uint32_t Value; 522 } DW2; 523 union 524 { 525 struct 526 { 527 uint32_t DefaultAlphaValue : __CODEGEN_BITFIELD( 0, 15) ; //!< Default Alpha Value 528 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(16, 31) ; //!< Y Offset for V(Cr) 529 }; 530 uint32_t Value; 531 } DW3; 532 union 533 { 534 struct 535 { 536 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 0, 7) ; //!< MEMORY_COMPRESSION_ENABLE 537 uint32_t CompressionType : __CODEGEN_BITFIELD( 8, 15) ; //!< COMPRESSION_TYPE 538 uint32_t CompressionFormat : __CODEGEN_BITFIELD(16, 20) ; //!< COMPRESSION_FORMAT 539 uint32_t Reserved149 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 540 }; 541 uint32_t Value; 542 } DW4; 543 544 //! \name Local enumerations 545 546 enum MEDIA_INSTRUCTION_COMMAND 547 { 548 MEDIA_INSTRUCTION_COMMAND_HCPSURFACESTATE = 1, //!< No additional details 549 }; 550 551 //! \brief MEDIA_INSTRUCTION_OPCODE 552 //! \details 553 //! Codec/Engine Name = HCP = 7h 554 enum MEDIA_INSTRUCTION_OPCODE 555 { 556 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 557 }; 558 559 enum PIPELINE_TYPE 560 { 561 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 562 }; 563 564 enum COMMAND_TYPE 565 { 566 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 567 }; 568 569 enum SURFACE_ID 570 { 571 SURFACE_ID_HEVCFORCURRENTDECODEDPICTURE = 0, //!< 8-bit uncompressed data 572 SURFACE_ID_SOURCEINPUTPICTURE_ENCODER = 1, //!< 8-bit uncompressed data 573 SURFACE_ID_PREVREFERENCEPICTURE = 2, //!< (VP9 only) Previous Reference 574 SURFACE_ID_GOLDENREFERENCEPICTURE = 3, //!< (VP9 only) Golden Reference 575 SURFACE_ID_ALTREFREFERENCEPICTURE = 4, //!< (VP9 only) AltRef Reference 576 SURFACE_ID_HEVCREFERENCEPICTURES = 5, //!< (HEVC only) Reference. Also, this will have separate compressible bits per reference surfaces for HEVC 577 }; 578 579 //! \brief SURFACE_FORMAT 580 //! \details 581 //! <p>Specifies the format of the surface.</p> 582 enum SURFACE_FORMAT 583 { 584 SURFACE_FORMAT_YUY2FORMAT = 0, //!< No additional details 585 SURFACE_FORMAT_RGB8FORMAT = 1, //!< No additional details 586 SURFACE_FORMAT_AYUV4444FORMAT = 2, //!< No additional details 587 SURFACE_FORMAT_P010VARIANT = 3, //!< No additional details 588 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 589 SURFACE_FORMAT_YCRCBSWAPYFORMAT = 5, //!< No additional details 590 SURFACE_FORMAT_YCRCBSWAPUVFORMAT = 6, //!< No additional details 591 SURFACE_FORMAT_YCRCBSWAPUVYFORMAT = 7, //!< No additional details 592 SURFACE_FORMAT_Y216Y210FORMAT = 8, //!< Same value is used to represent Y216 and Y210 593 SURFACE_FORMAT_RGB10FORMAT = 9, //!< No additional details 594 SURFACE_FORMAT_Y410FORMAT = 10, //!< No additional details 595 SURFACE_FORMAT_NV21PLANAR4208FORMAT = 11, //!< No additional details 596 SURFACE_FORMAT_Y416FORMAT = 12, //!< No additional details 597 SURFACE_FORMAT_P010 = 13, //!< No additional details 598 SURFACE_FORMAT_P016 = 14, //!< No additional details 599 SURFACE_FORMAT_Y8FORMAT = 15, //!< No additional details 600 SURFACE_FORMAT_Y16FORMAT = 16, //!< No additional details 601 SURFACE_FORMAT_Y216VARIANT = 17, //!< Y216Variant is the modifed Y210/Y216 format, 8 bit planar 422 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The chroma is UV interleaved with identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 602 SURFACE_FORMAT_Y416VARIANT = 18, //!< Y416Variant is the modifed Y410/Y412/Y416 format,8 bit planar 444 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The U channel is below the luma, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma The V channel is below the U, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 603 SURFACE_FORMAT_YUY2VARIANT = 19, //!< YUY2Variant is the modifed YUY2 format, 8 bit planar 422. The chroma is UV interleaved and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 604 SURFACE_FORMAT_AYUV4444VARIANT = 20, //!< AYUV4444Variant is the modifed AYUV4444 format, 8 bit planar 444 format. The U channel is below the luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. The V channel is below the and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 605 }; 606 607 //! \brief MEMORY_COMPRESSION_ENABLE 608 //! \details 609 //! <p>In HEVC mode, each bit is used for 1 reference starting with Bit 0 610 //! for Ref 0 in the ref list and Bit 1 for Ref 1 and so on.</p> 611 //! <p>In VP9 mode, Bit 0 is for Previous Reference; Bit 1 is for Golden 612 //! Reference and Bit 2 is for Alterante Reference; Bits 3-7 are unused and 613 //! should be programmed to 0.</p> 614 enum MEMORY_COMPRESSION_ENABLE 615 { 616 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONDISABLE = 0, //!< No additional details 617 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONENABLE = 1, //!< No additional details 618 }; 619 620 //! \brief COMPRESSION_TYPE 621 //! \details 622 //! <p>This field indicates if the compression type for the reference 623 //! surface is media or render compressed.</p> 624 //! <p>In HEVC mode, each bit is used for 1 reference starting with Bit 8for 625 //! Ref 0 in the ref list and Bit 9for Ref 1 and so on.</p> 626 //! <p>In VP9 mode, Bit 8is for Previous Reference; Bit 9is for Golden 627 //! Reference and Bit 10is for Alterante Reference; Bits11-15are unused and 628 //! should be programmed to 0</p> 629 enum COMPRESSION_TYPE 630 { 631 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED = 0, //!< No additional details 632 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLED = 1, //!< No additional details 633 }; 634 635 //! \name Initializations 636 637 //! \brief Explicit member initialization function HCP_SURFACE_STATE_CMDHCP_SURFACE_STATE_CMD638 HCP_SURFACE_STATE_CMD() 639 { 640 DW0.Value = 0x73810003; 641 //DW0.DwordLength = GetOpLength(dwSize); 642 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPSURFACESTATE; 643 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 644 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 645 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 646 647 DW1.Value = 0x00000000; 648 //DW1.SurfaceId = SURFACE_ID_HEVCFORCURRENTDECODEDPICTURE; 649 650 DW2.Value = 0x00000000; 651 //DW2.SurfaceFormat = SURFACE_FORMAT_YUY2FORMAT; 652 653 DW3.Value = 0x00000000; 654 655 DW4.Value = 0x00000000; 656 //DW4.MemoryCompressionEnable = MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONDISABLE; 657 //DW4.CompressionType = COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED; 658 //DW4.CompressionFormat = GMM_E2ECOMP_FORMAT_INVALID; 659 } 660 661 static const size_t dwSize = 5; 662 static const size_t byteSize = 20; 663 }; 664 665 //! 666 //! \brief HCP_PIPE_BUF_ADDR_STATE 667 //! \details 668 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 669 //! Commands. Each HCP command has assigned a media instruction command as 670 //! defined in DWord 0, BitField 22:16. 671 //! 672 //! This state command provides the memory base addresses for the row store 673 //! buffer and reconstructed picture output buffers required by the HCP. 674 //! This is a picture level state command and is shared by both encoding and 675 //! decoding processes. 676 //! 677 //! All pixel surface addresses must be 4K byte aligned. There is a max of 8 678 //! Reference Picture Buffer Addresses, and all share the same third address 679 //! DW in specifying 48-bit address. 680 //! 681 struct HCP_PIPE_BUF_ADDR_STATE_CMD 682 { 683 union 684 { 685 struct 686 { 687 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 688 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 689 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 690 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 691 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 692 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 693 }; 694 uint32_t Value; 695 } DW0; 696 SPLITBASEADDRESS4KBYTEALIGNED_CMD DecodedPicture; //!< DW1..2, Decoded Picture 697 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureMemoryAddressAttributes; //!< DW3, Decoded Picture Memory Address Attributes 698 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterLineBuffer; //!< DW4..5, Deblocking Filter Line Buffer 699 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterLineBufferMemoryAddressAttributes; //!< DW6, Deblocking Filter Line Buffer Memory Address Attributes 700 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileLineBuffer; //!< DW7..8, Deblocking Filter Tile Line Buffer 701 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileLineBufferMemoryAddressAttributes; //!< DW9, Deblocking Filter Tile Line Buffer Memory Address Attributes 702 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileColumnBuffer; //!< DW10..11, Deblocking Filter Tile Column Buffer 703 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileColumnBufferMemoryAddressAttributes; //!< DW12, Deblocking Filter Tile Column Buffer Memory Address Attributes 704 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataLineBuffer; //!< DW13..14, Metadata Line Buffer 705 MEMORYADDRESSATTRIBUTES_CMD MetadataLineBufferMemoryAddressAttributes; //!< DW15, Metadata Line Buffer Memory Address Attributes 706 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileLineBuffer; //!< DW16..17, Metadata Tile Line Buffer 707 MEMORYADDRESSATTRIBUTES_CMD MetadataTileLineBufferMemoryAddressAttributes; //!< DW18, Metadata Tile Line Buffer Memory Address Attributes 708 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileColumnBuffer; //!< DW19..20, Metadata Tile Column Buffer 709 MEMORYADDRESSATTRIBUTES_CMD MetadataTileColumnBufferMemoryAddressAttributes; //!< DW21, Metadata Tile Column Buffer Memory Address Attributes 710 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoLineBuffer; //!< DW22..23, SAO Line Buffer 711 MEMORYADDRESSATTRIBUTES_CMD SaoLineBufferMemoryAddressAttributes; //!< DW24, SAO Line Buffer Memory Address Attributes 712 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileLineBuffer; //!< DW25..26, SAO Tile Line Buffer 713 MEMORYADDRESSATTRIBUTES_CMD SaoTileLineBufferMemoryAddressAttributes; //!< DW27, SAO Tile Line Buffer Memory Address Attributes 714 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileColumnBuffer; //!< DW28..29, SAO Tile Column Buffer 715 MEMORYADDRESSATTRIBUTES_CMD SaoTileColumnBufferMemoryAddressAttributes; //!< DW30, SAO Tile Column Buffer Memory Address Attributes 716 SPLITBASEADDRESS64BYTEALIGNED_CMD CurrentMotionVectorTemporalBuffer; //!< DW31..32, Current Motion Vector Temporal Buffer 717 MEMORYADDRESSATTRIBUTES_CMD CurrentMotionVectorTemporalBufferMemoryAddressAttributes; //!< DW33, Current Motion Vector Temporal Buffer Memory Address Attributes 718 union 719 { 720 struct 721 { 722 uint64_t Reserved1088 ; //!< Reserved 723 }; 724 uint32_t Value[2]; 725 } DW34_35; 726 union 727 { 728 struct 729 { 730 uint32_t Reserved1152 ; //!< Reserved 731 }; 732 uint32_t Value; 733 } DW36; 734 SPLITBASEADDRESS64BYTEALIGNED_CMD ReferencePictureBaseAddressRefaddr07[8]; //!< DW37..52, Reference Picture Base Address (RefAddr[0-7]) 735 MEMORYADDRESSATTRIBUTES_CMD ReferencePictureBaseAddressMemoryAddressAttributes; //!< DW53, Reference Picture Base Address Memory Address Attributes 736 SPLITBASEADDRESS64BYTEALIGNED_CMD OriginalUncompressedPictureSource; //!< DW54..55, Original Uncompressed Picture Source 737 MEMORYADDRESSATTRIBUTES_CMD OriginalUncompressedPictureSourceMemoryAddressAttributes; //!< DW56, Original Uncompressed Picture Source Memory Address Attributes 738 SPLITBASEADDRESS64BYTEALIGNED_CMD StreamoutDataDestination; //!< DW57..58, Streamout Data Destination 739 MEMORYADDRESSATTRIBUTES_CMD StreamoutDataDestinationMemoryAddressAttributes; //!< DW59, Streamout Data Destination Memory Address Attributes, Decoder Only 740 SPLITBASEADDRESS64BYTEALIGNED_CMD DecodedPictureStatusErrorBufferBaseAddressOrEncodedSliceSizeStreamoutBaseAddress;//!< DW60..61, Decoded Picture Status/Error Buffer Base Address or Encoded slice size streamout Base Address 741 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureStatusErrorBufferBaseAddressMemoryAddressAttributes; //!< DW62, Decoded Picture Status/Error Buffer Base Address Memory Address Attributes 742 SPLITBASEADDRESS64BYTEALIGNED_CMD LcuIldbStreamoutBuffer; //!< DW63..64, LCU ILDB Streamout Buffer 743 MEMORYADDRESSATTRIBUTES_CMD LcuIldbStreamoutBufferMemoryAddressAttributes; //!< DW65, LCU ILDB Streamout Buffer Memory Address Attributes 744 SPLITBASEADDRESS64BYTEALIGNED_CMD CollocatedMotionVectorTemporalBuffer07[8]; //!< DW66..81, Collocated Motion Vector Temporal Buffer[0-7] 745 MEMORYADDRESSATTRIBUTES_CMD CollocatedMotionVectorTemporalBuffer07MemoryAddressAttributes; //!< DW82, Collocated Motion Vector Temporal Buffer[0-7] Memory Address Attributes 746 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9ProbabilityBufferReadWrite; //!< DW83..84, VP9 Probability Buffer Read/Write 747 MEMORYADDRESSATTRIBUTES_CMD Vp9ProbabilityBufferReadWriteMemoryAddressAttributes; //!< DW85, VP9 Probability Buffer Read/Write Memory Address Attributes 748 union 749 { 750 struct 751 { 752 uint64_t Vp9SegmentIdBufferReadWrite ; //!< VP9 Segment ID Buffer Read/Write 753 }; 754 uint32_t Value[2]; 755 } DW86_87; 756 MEMORYADDRESSATTRIBUTES_CMD Vp9SegmentIdBufferReadWriteMemoryAddressAttributes; //!< DW88, VP9 Segment ID buffer Read/Write Memory Address Attributes 757 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdLineRowstoreBufferReadWrite; //!< DW89..90, VP9 HVD Line Rowstore Buffer Read/Write 758 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdLineRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW91, VP9 HVD Line Rowstore buffer Read/Write Memory Address Attributes 759 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdTileRowstoreBufferReadWrite; //!< DW92..93, VP9 HVD Tile Rowstore Buffer Read/Write 760 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdTileRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW94, VP9 HVD Tile Rowstore buffer Read/Write Memory Address Attributes 761 union 762 { 763 struct 764 { 765 uint64_t SaoRowstoreBufferBaseAddress ; //!< SAO Rowstore Buffer Base Address 766 }; 767 uint32_t Value[2]; 768 } DW95_96; 769 MEMORYADDRESSATTRIBUTES_CMD SaoRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW97, SAO Rowstore Buffer Read/Write Memory Address Attributes 770 SPLITBASEADDRESS64BYTEALIGNED_CMD FrameStatisticsStreamoutDataDestinationBufferBaseAddress; //!< DW98..99, Frame Statistics Streamout Data Destination Buffer Base Address 771 MEMORYADDRESSATTRIBUTES_CMD FrameStatisticsStreamoutDataDestinationBufferAttributesReadWrite; //!< DW100, Frame Statistics Streamout Data Destination buffer (attributes) Read/Write 772 SPLITBASEADDRESS64BYTEALIGNED_CMD SseSourcePixelRowstoreBufferBaseAddress; //!< DW101..102, SSE Source Pixel RowStore Buffer Base Address 773 MEMORYADDRESSATTRIBUTES_CMD SseSourcePixelRowstoreBufferAttributesReadWrite; //!< DW103, SSE Source Pixel RowStore buffer (attributes) Read/Write 774 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySliceStateBufferBaseAddress; //!< DW104..105, HCP Scalability Slice State Buffer Base Address 775 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySliceStateBufferAttributesReadWrite; //!< DW106, HCP Scalability Slice State Buffer (attributes) Read/Write 776 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferBaseAddress; //!< DW107..108, HCP Scalability CABAC Decoded Syntax Elements Buffer Base Address 777 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferAttributesReadWrite; //!< DW109, HCP Scalability CABAC Decoded Syntax Elements Buffer (attributes) Read/Write 778 SPLITBASEADDRESS64BYTEALIGNED_CMD MotionVectorUpperRightColumnStoreBufferBaseAddress; //!< DW110..111, Motion Vector Upper Right Column Store Buffer Base Address 779 MEMORYADDRESSATTRIBUTES_CMD MotionVectorUpperRightColumnStoreBufferAttributesReadWrite; //!< DW112, Motion Vector Upper Right Column Store Buffer (attributes) Read/Write 780 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionUpperRightColumnStoreBufferBaseAddress; //!< DW113..114, Intra Prediction Upper Right Column Store Buffer Base Address 781 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionUpperRightColumnStoreBufferAttributesReadWrite; //!< DW115, Intra Prediction Upper Right Column Store Buffer (attributes) Read/Write 782 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionLeftReconColumnStoreBufferBaseAddress; //!< DW116..117, Intra Prediction Left Recon Column Store Buffer Base Address 783 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionLeftReconColumnStoreBufferAttributesReadWrite; //!< DW118, Intra Prediction Left Recon Column Store Buffer (attributes) Read/Write 784 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferMaxAddress; //!< DW119..120, HCP Scalability CABAC Decoded Syntax Elements Buffer Max Address 785 786 //! \name Local enumerations 787 788 enum MEDIA_INSTRUCTION_COMMAND 789 { 790 MEDIA_INSTRUCTION_COMMAND_HCPPIPEBUFADDRSTATE = 2, //!< No additional details 791 }; 792 793 //! \brief MEDIA_INSTRUCTION_OPCODE 794 //! \details 795 //! Codec/Engine Name = HCP = 7h 796 enum MEDIA_INSTRUCTION_OPCODE 797 { 798 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 799 }; 800 801 enum PIPELINE_TYPE 802 { 803 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 804 }; 805 806 enum COMMAND_TYPE 807 { 808 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 809 }; 810 811 //! \name Initializations 812 813 //! \brief Explicit member initialization function HCP_PIPE_BUF_ADDR_STATE_CMDHCP_PIPE_BUF_ADDR_STATE_CMD814 HCP_PIPE_BUF_ADDR_STATE_CMD() 815 { 816 DW0.Value = 0x73820077; 817 //DW0.DwordLength = GetOpLength(dwSize); 818 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPIPEBUFADDRSTATE; 819 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 820 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 821 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 822 823 DW34_35.Value[0] = DW34_35.Value[1] = 0x00000000; 824 825 DW36.Value = 0x00000000; 826 827 DW86_87.Value[0] = DW86_87.Value[1] = 0x00000000; 828 829 DW95_96.Value[0] = DW95_96.Value[1] = 0x00000000; 830 } 831 832 static const size_t dwSize = 121; 833 static const size_t byteSize = 484; 834 }; 835 836 //! 837 //! \brief HCP_IND_OBJ_BASE_ADDR_STATE 838 //! \details 839 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 840 //! Commands. Each HCP command has assigned a media instruction command as 841 //! defined in DWord 0, BitField 22:16. 842 //! 843 //! The HCP_IND_OBJ_BASE_ADDR_STATE command is used to define the indirect 844 //! object base address of the stream in graphics memory. This is a frame 845 //! level command. (Is it frame or picture level?) 846 //! This is a picture level state command and is issued in both encoding and 847 //! decoding processes. 848 //! 849 //! Compressed Header Format 850 //! 851 //! 852 //! 853 struct HCP_IND_OBJ_BASE_ADDR_STATE_CMD 854 { 855 union 856 { 857 struct 858 { 859 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 860 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 861 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 862 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 863 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 864 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 865 }; 866 uint32_t Value; 867 } DW0; 868 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectBaseAddress; //!< DW1..2, HCP Indirect Bitstream Object Base Address 869 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectBitstreamObjectMemoryAddressAttributes; //!< DW3, HCP Indirect Bitstream Object Memory Address Attributes 870 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectAccessUpperBound; //!< DW4..5, HCP Indirect Bitstream Object Access Upper Bound 871 union 872 { 873 struct 874 { 875 uint64_t HcpIndirectCuObjectBaseAddress ; //!< HCP Indirect CU Object Base Address 876 }; 877 uint32_t Value[2]; 878 } DW6_7; 879 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectCuObjectObjectMemoryAddressAttributes; //!< DW8, HCP Indirect CU Object Object Memory Address Attributes 880 union 881 { 882 struct 883 { 884 uint64_t HcpPakBseObjectBaseAddress ; //!< HCP PAK-BSE Object Base Address 885 }; 886 uint32_t Value[2]; 887 } DW9_10; 888 MEMORYADDRESSATTRIBUTES_CMD HcpPakBseObjectAddressMemoryAddressAttributes; //!< DW11, HCP PAK-BSE Object Address Memory Address Attributes 889 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpPakBseObjectAccessUpperBound; //!< DW12..13, HCP PAK-BSE Object Access Upper Bound 890 union 891 { 892 struct 893 { 894 uint64_t HcpVp9PakCompressedHeaderSyntaxStreaminBaseAddress ; //!< HCP VP9 PAK Compressed Header Syntax Streamin- Base Address 895 }; 896 uint32_t Value[2]; 897 } DW14_15; 898 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCompressedHeaderSyntaxStreaminMemoryAddressAttributes; //!< DW16, HCP VP9 PAK Compressed Header Syntax StreamIn Memory Address Attributes 899 union 900 { 901 struct 902 { 903 uint64_t HcpVp9PakProbabilityCounterStreamoutBaseAddress ; //!< HCP VP9 PAK Probability Counter StreamOut- Base Address 904 }; 905 uint32_t Value[2]; 906 } DW17_18; 907 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityCounterStreamoutMemoryAddressAttributes; //!< DW19, HCP VP9 PAK Probability Counter StreamOut Memory Address Attributes 908 union 909 { 910 struct 911 { 912 uint64_t HcpVp9PakProbabilityDeltasStreaminBaseAddress ; //!< HCP VP9 PAK Probability Deltas StreamIn- Base Address 913 }; 914 uint32_t Value[2]; 915 } DW20_21; 916 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityDeltasStreaminMemoryAddressAttributes; //!< DW22, HCP VP9 PAK Probability Deltas StreamIn Memory Address Attributes 917 union 918 { 919 struct 920 { 921 uint64_t HcpVp9PakTileRecordStreamoutBaseAddress ; //!< HCP VP9 PAK Tile Record StreamOut- Base Address 922 }; 923 uint32_t Value[2]; 924 } DW23_24; 925 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakTileRecordStreamoutMemoryAddressAttributes; //!< DW25, HCP VP9 PAK Tile Record StreamOut Memory Address Attributes 926 union 927 { 928 struct 929 { 930 uint64_t HcpVp9PakCuLevelStatisticStreamoutBaseAddress ; //!< HCP VP9 PAK CU Level Statistic StreamOut- Base Address 931 }; 932 uint32_t Value[2]; 933 } DW26_27; 934 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCuLevelStatisticStreamoutMemoryAddressAttributes; //!< DW28, HCP VP9 PAK CU Level Statistic StreamOut Memory Address Attributes 935 936 //! \name Local enumerations 937 938 enum MEDIA_INSTRUCTION_COMMAND 939 { 940 MEDIA_INSTRUCTION_COMMAND_HCPINDOBJBASEADDRSTATE = 3, //!< No additional details 941 }; 942 943 //! \brief MEDIA_INSTRUCTION_OPCODE 944 //! \details 945 //! Codec/Engine Name = HCP = 7h 946 enum MEDIA_INSTRUCTION_OPCODE 947 { 948 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 949 }; 950 951 enum PIPELINE_TYPE 952 { 953 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 954 }; 955 956 enum COMMAND_TYPE 957 { 958 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 959 }; 960 961 //! \name Initializations 962 963 //! \brief Explicit member initialization function HCP_IND_OBJ_BASE_ADDR_STATE_CMDHCP_IND_OBJ_BASE_ADDR_STATE_CMD964 HCP_IND_OBJ_BASE_ADDR_STATE_CMD() 965 { 966 DW0.Value = 0x7383001b; 967 //DW0.DwordLength = GetOpLength(dwSize); 968 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPINDOBJBASEADDRSTATE; 969 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 970 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 971 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 972 973 DW6_7.Value[0] = DW6_7.Value[1] = 0x00000000; 974 975 DW9_10.Value[0] = DW9_10.Value[1] = 0x00000000; 976 977 DW14_15.Value[0] = DW14_15.Value[1] = 0x00000000; 978 979 DW17_18.Value[0] = DW17_18.Value[1] = 0x00000000; 980 981 DW20_21.Value[0] = DW20_21.Value[1] = 0x00000000; 982 983 DW23_24.Value[0] = DW23_24.Value[1] = 0x00000000; 984 985 DW26_27.Value[0] = DW26_27.Value[1] = 0x00000000; 986 } 987 988 static const size_t dwSize = 29; 989 static const size_t byteSize = 116; 990 }; 991 992 //! 993 //! \brief HCP_QM_STATE 994 //! \details 995 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 996 //! Commands. Each HCP command has assigned a media instruction command as 997 //! defined in DWord 0, BitField 22:16. 998 //! 999 //! The HCP_QM_STATE command loads the custom HEVC quantization tables into 1000 //! local RAM and may be issued up to 20 times: 3x Colour Component plus 2x 1001 //! intra/inter plus 4x SizeID minus 4 for the 32x32 chroma components. When 1002 //! the scaling_list_enable_flag is set to disable, the scaling matrix is 1003 //! still sent to the decoder, and with all entries programmed to the same 1004 //! value = 16. This is a picture level state command and is issued in both 1005 //! encoding and decoding processes. 1006 //! 1007 //! Dwords 2-17 form a table for the DCT coefficients, 4 8-bit 1008 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-5. 1009 //! Size 8x8 for SizeID1/2/3, DWords 2-17. 1010 //! 1011 //! 1012 //! SizeID 0 (Table 4-10) 1013 //! 1014 struct HCP_QM_STATE_CMD 1015 { 1016 union 1017 { 1018 struct 1019 { 1020 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1021 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1022 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1023 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1024 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1025 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1026 }; 1027 uint32_t Value; 1028 } DW0; 1029 union 1030 { 1031 struct 1032 { 1033 uint32_t PredictionType : __CODEGEN_BITFIELD( 0, 0) ; //!< PREDICTION_TYPE 1034 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 1035 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 1036 uint32_t DcCoefficient : __CODEGEN_BITFIELD( 5, 12) ; //!< DC Coefficient 1037 uint32_t Reserved45 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1038 }; 1039 uint32_t Value; 1040 } DW1; 1041 uint32_t Quantizermatrix[16]; //!< QuantizerMatrix 1042 1043 //! \name Local enumerations 1044 1045 enum MEDIA_INSTRUCTION_COMMAND 1046 { 1047 MEDIA_INSTRUCTION_COMMAND_HCPQMSTATE = 4, //!< No additional details 1048 }; 1049 1050 //! \brief MEDIA_INSTRUCTION_OPCODE 1051 //! \details 1052 //! Codec/Engine Name = HCP = 7h 1053 enum MEDIA_INSTRUCTION_OPCODE 1054 { 1055 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1056 }; 1057 1058 enum PIPELINE_TYPE 1059 { 1060 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1061 }; 1062 1063 enum COMMAND_TYPE 1064 { 1065 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1066 }; 1067 1068 enum PREDICTION_TYPE 1069 { 1070 PREDICTION_TYPE_INTRA = 0, //!< No additional details 1071 PREDICTION_TYPE_INTER = 1, //!< No additional details 1072 }; 1073 1074 enum SIZEID 1075 { 1076 SIZEID_4X4 = 0, //!< No additional details 1077 SIZEID_8X8 = 1, //!< No additional details 1078 SIZEID_16X16 = 2, //!< No additional details 1079 SIZEID_32X32 = 3, //!< (Illegal Value for Colour Component Chroma Cr and Cb.) 1080 }; 1081 1082 //! \brief COLOR_COMPONENT 1083 //! \details 1084 //! Encoder: When RDOQ is enabled, scaling list for all 3 color components 1085 //! must be same. So this field is set to always 0. 1086 enum COLOR_COMPONENT 1087 { 1088 COLOR_COMPONENT_LUMA = 0, //!< No additional details 1089 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 1090 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 1091 }; 1092 1093 //! \name Initializations 1094 1095 //! \brief Explicit member initialization function HCP_QM_STATE_CMDHCP_QM_STATE_CMD1096 HCP_QM_STATE_CMD() 1097 { 1098 DW0.Value = 0x73840010; 1099 //DW0.DwordLength = GetOpLength(dwSize); 1100 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPQMSTATE; 1101 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 1102 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 1103 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 1104 1105 DW1.Value = 0x00000000; 1106 //DW1.PredictionType = PREDICTION_TYPE_INTRA; 1107 //DW1.Sizeid = SIZEID_4X4; 1108 //DW1.ColorComponent = COLOR_COMPONENT_LUMA; 1109 1110 memset(&Quantizermatrix, 0, sizeof(Quantizermatrix)); 1111 } 1112 1113 static const size_t dwSize = 18; 1114 static const size_t byteSize = 72; 1115 }; 1116 1117 //! 1118 //! \brief HCP_PIC_STATE 1119 //! \details 1120 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 1121 //! Commands. Each HCP command has assigned a media instruction command as 1122 //! defined in DWord 0, BitField 22:16. 1123 //! 1124 //! This is a picture level command and is issued only once per workload for 1125 //! both encoding and decoding processes. 1126 //! 1127 struct HCP_PIC_STATE_CMD 1128 { 1129 union 1130 { 1131 struct 1132 { 1133 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1134 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1135 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1136 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1137 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1138 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1139 }; 1140 uint32_t Value; 1141 } DW0; 1142 union 1143 { 1144 struct 1145 { 1146 uint32_t Framewidthinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< FrameWidthInMinCbMinus1 1147 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 14) ; //!< Reserved 1148 uint32_t PakTransformSkipEnable : __CODEGEN_BITFIELD(15, 15) ; //!< PAK Transform Skip Enable 1149 uint32_t Frameheightinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< FrameHeightInMinCbMinus1 1150 uint32_t Reserved59 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1151 }; 1152 uint32_t Value; 1153 } DW1; 1154 union 1155 { 1156 struct 1157 { 1158 uint32_t Mincusize : __CODEGEN_BITFIELD( 0, 1) ; //!< MINCUSIZE 1159 uint32_t CtbsizeLcusize : __CODEGEN_BITFIELD( 2, 3) ; //!< CTBSIZE_LCUSIZE 1160 uint32_t Mintusize : __CODEGEN_BITFIELD( 4, 5) ; //!< MINTUSIZE 1161 uint32_t Maxtusize : __CODEGEN_BITFIELD( 6, 7) ; //!< MAXTUSIZE 1162 uint32_t Minpcmsize : __CODEGEN_BITFIELD( 8, 9) ; //!< MINPCMSIZE 1163 uint32_t Maxpcmsize : __CODEGEN_BITFIELD(10, 11) ; //!< MAXPCMSIZE 1164 uint32_t Log2SaoOffsetScaleLuma : __CODEGEN_BITFIELD(12, 14) ; //!< LOG2_SAO_OFFSET_SCALE_LUMA 1165 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1166 uint32_t Log2SaoOffsetScaleChroma : __CODEGEN_BITFIELD(16, 18) ; //!< LOG2_SAO_OFFSET_SCALE_CHROMA 1167 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 1168 uint32_t ChromaQpOffsetListLenMinus1 : __CODEGEN_BITFIELD(20, 22) ; //!< chroma_qp_offset_list_len_minus1 1169 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 1170 uint32_t DiffCuChromaQpOffsetDepth : __CODEGEN_BITFIELD(24, 27) ; //!< diff_cu_chroma_qp_offset_depth 1171 uint32_t ChromaQpOffsetListEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< chroma_qp_offset_list_enabled_flag 1172 uint32_t ChromaSubsampling : __CODEGEN_BITFIELD(29, 31) ; //!< CHROMA_SUBSAMPLING 1173 }; 1174 uint32_t Value; 1175 } DW2; 1176 union 1177 { 1178 struct 1179 { 1180 uint32_t Colpicisi : __CODEGEN_BITFIELD( 0, 0) ; //!< COLPICISI 1181 uint32_t Curpicisi : __CODEGEN_BITFIELD( 1, 1) ; //!< CURPICISI 1182 uint32_t Inserttestflag : __CODEGEN_BITFIELD( 2, 2) ; //!< INSERTTESTFLAG 1183 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1184 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 1185 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame number 1186 uint32_t Reserved114 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 1187 uint32_t HighPrecisionOffsetsEnableFlag : __CODEGEN_BITFIELD(19, 19) ; //!< High Precision Offsets Enable Flag 1188 uint32_t Log2Maxtransformskipsize : __CODEGEN_BITFIELD(20, 22) ; //!< Log2MaxTransformSkipSize 1189 uint32_t CrossComponentPredictionEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cross_component_prediction_enabled_flag 1190 uint32_t CabacBypassAlignmentEnabledFlag : __CODEGEN_BITFIELD(24, 24) ; //!< cabac_bypass_alignment_enabled_flag 1191 uint32_t PersistentRiceAdaptationEnabledFlag : __CODEGEN_BITFIELD(25, 25) ; //!< persistent_rice_adaptation_enabled_flag 1192 uint32_t IntraSmoothingDisabledFlag : __CODEGEN_BITFIELD(26, 26) ; //!< intra_smoothing_disabled_flag 1193 uint32_t ExplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< explicit_rdpcm_enabled_flag 1194 uint32_t ImplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< implicit_rdpcm_enabled_flag 1195 uint32_t TransformSkipContextEnabledFlag : __CODEGEN_BITFIELD(29, 29) ; //!< transform_skip_context_enabled_flag 1196 uint32_t TransformSkipRotationEnabledFlag : __CODEGEN_BITFIELD(30, 30) ; //!< transform_skip_rotation_enabled_flag 1197 uint32_t SpsRangeExtensionEnableFlag : __CODEGEN_BITFIELD(31, 31) ; //!< sps_range_extension_enable_flag 1198 }; 1199 uint32_t Value; 1200 } DW3; 1201 union 1202 { 1203 struct 1204 { 1205 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1206 uint32_t SampleAdaptiveOffsetEnabledFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< sample_adaptive_offset_enabled_flag 1207 uint32_t PcmEnabledFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< pcm_enabled_flag 1208 uint32_t CuQpDeltaEnabledFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< CU_QP_DELTA_ENABLED_FLAG 1209 uint32_t DiffCuQpDeltaDepthOrNamedAsMaxDqpDepth : __CODEGEN_BITFIELD( 6, 7) ; //!< diff_cu_qp_delta_depth (or named as max_dqp_depth) 1210 uint32_t PcmLoopFilterDisableFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< pcm_loop_filter_disable_flag 1211 uint32_t ConstrainedIntraPredFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< constrained_intra_pred_flag 1212 uint32_t Log2ParallelMergeLevelMinus2 : __CODEGEN_BITFIELD(10, 12) ; //!< log2_parallel_merge_level_minus2 1213 uint32_t SignDataHidingFlag : __CODEGEN_BITFIELD(13, 13) ; //!< SIGN_DATA_HIDING_FLAG 1214 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 1215 uint32_t LoopFilterAcrossTilesEnabledFlag : __CODEGEN_BITFIELD(15, 15) ; //!< loop_filter_across_tiles_enabled_flag 1216 uint32_t EntropyCodingSyncEnabledFlag : __CODEGEN_BITFIELD(16, 16) ; //!< entropy_coding_sync_enabled_flag 1217 uint32_t TilesEnabledFlag : __CODEGEN_BITFIELD(17, 17) ; //!< tiles_enabled_flag 1218 uint32_t WeightedBipredFlag : __CODEGEN_BITFIELD(18, 18) ; //!< weighted_bipred_flag 1219 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(19, 19) ; //!< weighted_pred_flag 1220 uint32_t Fieldpic : __CODEGEN_BITFIELD(20, 20) ; //!< FIELDPIC 1221 uint32_t Bottomfield : __CODEGEN_BITFIELD(21, 21) ; //!< BOTTOMFIELD 1222 uint32_t TransformSkipEnabledFlag : __CODEGEN_BITFIELD(22, 22) ; //!< TRANSFORM_SKIP_ENABLED_FLAG 1223 uint32_t AmpEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< AMP_ENABLED_FLAG 1224 uint32_t Reserved152 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 1225 uint32_t TransquantBypassEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< TRANSQUANT_BYPASS_ENABLE_FLAG 1226 uint32_t StrongIntraSmoothingEnableFlag : __CODEGEN_BITFIELD(26, 26) ; //!< strong_intra_smoothing_enable_flag 1227 uint32_t CuPacketStructure : __CODEGEN_BITFIELD(27, 27) ; //!< CU packet structure 1228 uint32_t Reserved156 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1229 }; 1230 uint32_t Value; 1231 } DW4; 1232 union 1233 { 1234 struct 1235 { 1236 uint32_t PicCbQpOffset : __CODEGEN_BITFIELD( 0, 4) ; //!< pic_cb_qp_offset 1237 uint32_t PicCrQpOffset : __CODEGEN_BITFIELD( 5, 9) ; //!< pic_cr_qp_offset 1238 uint32_t MaxTransformHierarchyDepthIntraOrNamedAsTuMaxDepthIntra : __CODEGEN_BITFIELD(10, 12) ; //!< max_transform_hierarchy_depth_intra (or named as tu_max_depth_intra) 1239 uint32_t MaxTransformHierarchyDepthInterOrNamedAsTuMaxDepthInter : __CODEGEN_BITFIELD(13, 15) ; //!< max_transform_hierarchy_depth_inter(or named as tu_max_depth_inter) 1240 uint32_t PcmSampleBitDepthChromaMinus1 : __CODEGEN_BITFIELD(16, 19) ; //!< pcm_sample_bit_depth_chroma_minus1 1241 uint32_t PcmSampleBitDepthLumaMinus1 : __CODEGEN_BITFIELD(20, 23) ; //!< pcm_sample_bit_depth_luma_minus1 1242 uint32_t BitDepthChromaMinus8 : __CODEGEN_BITFIELD(24, 26) ; //!< BIT_DEPTH_CHROMA_MINUS8 1243 uint32_t BitDepthLumaMinus8 : __CODEGEN_BITFIELD(27, 29) ; //!< BIT_DEPTH_LUMA_MINUS8 1244 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 1245 uint32_t HRSUnitLevelClockGate_enChickenBit : __CODEGEN_BITFIELD(31, 31) ; 1246 }; 1247 uint32_t Value; 1248 } DW5; 1249 union 1250 { 1251 struct 1252 { 1253 uint32_t LcuMaxBitsizeAllowed : __CODEGEN_BITFIELD( 0, 15) ; //!< LCU Max BitSize Allowed 1254 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NonFirstPassFlag 1255 uint32_t LcuMaxBitSizeAllowedMsb2its : __CODEGEN_BITFIELD(17, 18) ; //!< LCU Max BitSize Allowed MSB 2bits 1256 uint32_t Reserved : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1257 uint32_t LcumaxbitstatusenLcumaxsizereportmask : __CODEGEN_BITFIELD(24, 24) ; //!< LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1258 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1259 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1260 uint32_t Reserved219 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 1261 uint32_t LoadSlicePointerFlag : __CODEGEN_BITFIELD(29, 29) ; //!< LOAD_SLICE_POINTER_FLAG 1262 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1263 }; 1264 uint32_t Value; 1265 } DW6; 1266 union 1267 { 1268 struct 1269 { 1270 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 1271 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1272 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 1273 }; 1274 uint32_t Value; 1275 } DW7; 1276 union 1277 { 1278 struct 1279 { 1280 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1281 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1282 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 1283 }; 1284 uint32_t Value; 1285 } DW8; 1286 union 1287 { 1288 struct 1289 { 1290 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FRAMEBITRATEMINDELTA 1291 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1292 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1293 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1294 }; 1295 uint32_t Value; 1296 } DW9; 1297 union 1298 { 1299 struct 1300 { 1301 uint64_t Framedeltaqpmax ; //!< FrameDeltaQpMax 1302 }; 1303 uint32_t Value[2]; 1304 } DW10_11; 1305 union 1306 { 1307 struct 1308 { 1309 uint64_t Framedeltaqpmin ; //!< FrameDeltaQpMin 1310 }; 1311 uint32_t Value[2]; 1312 } DW12_13; 1313 union 1314 { 1315 struct 1316 { 1317 uint64_t Framedeltaqpmaxrange ; //!< FrameDeltaQpMaxRange 1318 }; 1319 uint32_t Value[2]; 1320 } DW14_15; 1321 union 1322 { 1323 struct 1324 { 1325 uint64_t Framedeltaqpminrange ; //!< FrameDeltaQpMinRange 1326 }; 1327 uint32_t Value[2]; 1328 } DW16_17; 1329 union 1330 { 1331 struct 1332 { 1333 uint32_t Minframesize : __CODEGEN_BITFIELD( 0, 15) ; //!< MINFRAMESIZE 1334 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 1335 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 1336 }; 1337 uint32_t Value; 1338 } DW18; 1339 union 1340 { 1341 struct 1342 { 1343 uint32_t FractionalQpInput : __CODEGEN_BITFIELD( 0, 2) ; //!< Fractional QP Input 1344 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD( 3, 5) ; //!< Fractional QP Offset 1345 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RhoDomain Rate Control Enable 1346 uint32_t FractionalQpAdjustmentEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Fractional QP adjustment enable 1347 uint32_t Rhodomainframelevelqp : __CODEGEN_BITFIELD( 8, 13) ; //!< RhoDomainFrameLevelQP 1348 uint32_t PakDynamicSliceModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< PAK Dynamic Slice Mode Enable 1349 uint32_t NoOutputOfPriorPicsFlag : __CODEGEN_BITFIELD(15, 15) ; //!< no_output_of_prior_pics_flag 1350 uint32_t FirstSliceSegmentInPicFlag : __CODEGEN_BITFIELD(16, 16) ; //!< first_slice_segment_in_pic_flag 1351 uint32_t Nalunittypeflag : __CODEGEN_BITFIELD(17, 17) ; //!< NalUnitTypeFlag 1352 uint32_t SlicePicParameterSetId : __CODEGEN_BITFIELD(18, 23) ; //!< slice_pic_parameter_set_id 1353 uint32_t SseEnable : __CODEGEN_BITFIELD(24, 24) ; //!< SSE Enable 1354 uint32_t RdoqEnable : __CODEGEN_BITFIELD(25, 25) ; //!< RDOQ Enable 1355 uint32_t NumberoflcusinnormalSliceSizeConformanceMode : __CODEGEN_BITFIELD(26, 27) ; //!< NumberOfLCUsInNormal Slice size conformance Mode 1356 uint32_t Reserved636 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 1357 uint32_t PartialFrameUpdateMode : __CODEGEN_BITFIELD(30, 30) ; //!< Partial Frame Update Mode 1358 uint32_t TemporalMvPredDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Temporal MV pred disable 1359 }; 1360 uint32_t Value; 1361 } DW19; 1362 union 1363 { 1364 struct 1365 { 1366 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1367 uint32_t Intratucountbasedrdoqdisable : __CODEGEN_BITFIELD( 6, 6) ; //!< IntraTuCountBasedRDOQdisable 1368 uint32_t Reserved647 : __CODEGEN_BITFIELD( 7, 31) ; //!< Reserved 1369 }; 1370 uint32_t Value; 1371 } DW20; 1372 union 1373 { 1374 struct 1375 { 1376 uint32_t SliceSizeThresholdInBytes ; //!< Slice Size Threshold in Bytes 1377 }; 1378 uint32_t Value; 1379 } DW21; 1380 union 1381 { 1382 struct 1383 { 1384 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 1385 }; 1386 uint32_t Value; 1387 } DW22; 1388 union 1389 { 1390 struct 1391 { 1392 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 1393 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 1394 }; 1395 uint32_t Value; 1396 } DW23; 1397 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 1398 union 1399 { 1400 struct 1401 { 1402 uint32_t CbQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cb_qp_offset_list[0] 1403 uint32_t CbQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cb_qp_offset_list[1] 1404 uint32_t CbQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cb_qp_offset_list[2] 1405 uint32_t CbQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cb_qp_offset_list[3] 1406 uint32_t CbQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cb_qp_offset_list[4] 1407 uint32_t CbQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cb_qp_offset_list[5] 1408 uint32_t Reserved1054 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1409 }; 1410 uint32_t Value; 1411 } DW32; 1412 union 1413 { 1414 struct 1415 { 1416 uint32_t CrQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cr_qp_offset_list[0] 1417 uint32_t CrQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cr_qp_offset_list[1] 1418 uint32_t CrQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cr_qp_offset_list[2] 1419 uint32_t CrQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cr_qp_offset_list[3] 1420 uint32_t CrQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cr_qp_offset_list[4] 1421 uint32_t CrQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cr_qp_offset_list[5] 1422 uint32_t Reserved1086 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1423 }; 1424 uint32_t Value; 1425 } DW33; 1426 union 1427 { 1428 struct 1429 { 1430 uint32_t IbcMotionCompensationBufferReferenceIdc : __CODEGEN_BITFIELD( 0, 2) ; //!< IBC Motion Compensation Buffer Reference IDC 1431 uint32_t Reserved1091 : __CODEGEN_BITFIELD( 3, 5) ; //!< Reserved 1432 uint32_t DeblockingFilterOverrideEnabledFlag : __CODEGEN_BITFIELD( 6, 6) ; //!< deblocking_filter_override_enabled_flag 1433 uint32_t PpsDeblockingFilterDisabledFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< pps_deblocking_filter_disabled_flag 1434 uint32_t PpsActCrQpOffsetPlus3 : __CODEGEN_BITFIELD( 8, 13) ; //!< pps_act_cr_qp_offset_plus3 1435 uint32_t PpsActCbQpOffsetPlus5 : __CODEGEN_BITFIELD(14, 19) ; //!< pps_act_cb_qp_offset_plus5 1436 uint32_t PpsActYOffsetPlus5 : __CODEGEN_BITFIELD(20, 25) ; //!< pps_act_y_offset_plus5 1437 uint32_t PpsSliceActQpOffsetsPresentFlag : __CODEGEN_BITFIELD(26, 26) ; //!< pps_slice_act_qp_offsets_present_flag 1438 uint32_t ResidualAdaptiveColourTransformEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< residual_adaptive_colour_transform_enabled_flag 1439 uint32_t PpsCurrPicRefEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< pps_curr_pic_ref_enabled_flag 1440 uint32_t MotionVectorResolutionControlIdc : __CODEGEN_BITFIELD(29, 30) ; //!< MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1441 uint32_t IntraBoundaryFilteringDisabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< intra_boundary_filtering_disabled_flag 1442 }; 1443 uint32_t Value; 1444 } DW34; 1445 union 1446 { 1447 struct 1448 { 1449 uint32_t PaletteMaxSize : __CODEGEN_BITFIELD( 0, 6) ; //!< palette_max_size 1450 uint32_t Reserved1127 : __CODEGEN_BITFIELD( 7, 9) ; //!< Reserved 1451 uint32_t DeltaPaletteMaxPredictorSize : __CODEGEN_BITFIELD(10, 16) ; //!< delta_palette_max_predictor_size 1452 uint32_t Reserved1137 : __CODEGEN_BITFIELD(17, 18) ; //!< Reserved 1453 uint32_t IbcMotionVectorErrorHandlingDisable : __CODEGEN_BITFIELD(19, 19) ; //!< IBC Motion Vector Error Handling Disable 1454 uint32_t ChromaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(20, 23) ; //!< chroma_bit_depth_entry_minus8 1455 uint32_t LumaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(24, 27) ; //!< luma_bit_depth_entry_minus8 1456 uint32_t IbcConfiguration : __CODEGEN_BITFIELD(28, 29) ; //!< IBC_CONFIGURATION 1457 uint32_t MonochromePaletteFlag : __CODEGEN_BITFIELD(30, 30) ; //!< monochrome_palette_flag 1458 uint32_t PaletteModeEnabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< palette_mode_enabled_flag 1459 }; 1460 uint32_t Value; 1461 } DW35; 1462 union 1463 { 1464 struct 1465 { 1466 uint32_t EnableFpakMessaging : __CODEGEN_BITFIELD( 0, 0) ; //!< Enable FPAK Messaging 1467 uint32_t VDAQMEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Enable VDAQM 1468 uint32_t Reserved1154 : __CODEGEN_BITFIELD( 2, 29) ; //!< Reserved 1469 uint32_t FrameCrcType : __CODEGEN_BITFIELD(30, 30) ; //!< FRAME_CRC_TYPE 1470 uint32_t FrameCrcEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Frame CRC Enable 1471 }; 1472 uint32_t Value; 1473 } DW36; 1474 union 1475 { 1476 struct 1477 { 1478 uint32_t Rdoqintratuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntraTUThreshold 1479 uint32_t Reserved1200 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1480 }; 1481 uint32_t Value; 1482 } DW37; 1483 union 1484 { 1485 struct 1486 { 1487 uint32_t Rdoqintra16X16Tuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntra16x16TUThreshold 1488 uint32_t Rdoqintra32X32Tuthreshold : __CODEGEN_BITFIELD(16, 31) ; //!< RDOQIntra32x32TUThreshold 1489 }; 1490 uint32_t Value; 1491 } DW38; 1492 union 1493 { 1494 struct 1495 { 1496 uint64_t SsethresholdsForClass910 ; //!< SSEThresholds for Class9 ..10 1497 }; 1498 uint32_t Value[2]; 1499 } DW39_40; 1500 1501 //! \name Local enumerations 1502 1503 enum MEDIA_INSTRUCTION_COMMAND 1504 { 1505 MEDIA_INSTRUCTION_COMMAND_HCPPICSTATE = 16, //!< No additional details 1506 }; 1507 1508 //! \brief MEDIA_INSTRUCTION_OPCODE 1509 //! \details 1510 //! Codec/Engine Name = HCP = 7h 1511 enum MEDIA_INSTRUCTION_OPCODE 1512 { 1513 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1514 }; 1515 1516 enum PIPELINE_TYPE 1517 { 1518 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1519 }; 1520 1521 enum COMMAND_TYPE 1522 { 1523 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1524 }; 1525 1526 //! \brief MINCUSIZE 1527 //! \details 1528 //! Specifies the smallest coding block size. 1529 enum MINCUSIZE 1530 { 1531 MINCUSIZE_8X8 = 0, //!< No additional details 1532 MINCUSIZE_16X16 = 1, //!< No additional details 1533 MINCUSIZE_32X32 = 2, //!< No additional details 1534 MINCUSIZE_64X64 = 3, //!< No additional details 1535 }; 1536 1537 //! \brief CTBSIZE_LCUSIZE 1538 //! \details 1539 //! Specifies the coding tree block size. 1540 enum CTBSIZE_LCUSIZE 1541 { 1542 CTBSIZE_LCUSIZE_ILLEGALRESERVED = 0, //!< No additional details 1543 CTBSIZE_LCUSIZE_16X16 = 1, //!< No additional details 1544 CTBSIZE_LCUSIZE_32X32 = 2, //!< No additional details 1545 CTBSIZE_LCUSIZE_64X64 = 3, //!< No additional details 1546 }; 1547 1548 //! \brief MINTUSIZE 1549 //! \details 1550 //! Specifies the smallest allowed transform block size. 1551 enum MINTUSIZE 1552 { 1553 MINTUSIZE_4X4 = 0, //!< No additional details 1554 MINTUSIZE_8X8 = 1, //!< No additional details 1555 MINTUSIZE_16X16 = 2, //!< No additional details 1556 MINTUSIZE_32X32 = 3, //!< No additional details 1557 }; 1558 1559 //! \brief MAXTUSIZE 1560 //! \details 1561 //! Specifies the largest allowed transform block size. 1562 enum MAXTUSIZE 1563 { 1564 MAXTUSIZE_4X4 = 0, //!< No additional details 1565 MAXTUSIZE_8X8 = 1, //!< No additional details 1566 MAXTUSIZE_16X16 = 2, //!< No additional details 1567 MAXTUSIZE_32X32 = 3, //!< No additional details 1568 }; 1569 1570 //! \brief MINPCMSIZE 1571 //! \details 1572 //! Specifies the smallest allowed PCM coding block size. 1573 enum MINPCMSIZE 1574 { 1575 MINPCMSIZE_8X8 = 0, //!< No additional details 1576 MINPCMSIZE_16X16 = 1, //!< No additional details 1577 MINPCMSIZE_32X32 = 2, //!< No additional details 1578 }; 1579 1580 //! \brief MAXPCMSIZE 1581 //! \details 1582 //! Specifies the largest allowed PCM coding block size. 1583 enum MAXPCMSIZE 1584 { 1585 MAXPCMSIZE_8X8 = 0, //!< No additional details 1586 MAXPCMSIZE_16X16 = 1, //!< No additional details 1587 MAXPCMSIZE_32X32 = 2, //!< No additional details 1588 }; 1589 1590 //! \brief LOG2_SAO_OFFSET_SCALE_LUMA 1591 //! \details 1592 //! <p>To scale SAO offset values for luma samples</p> 1593 //! <p>0 to Max(0,BitDepth<sub><font size="2">C</font></sub>−10)</p> 1594 //! <p>Default = 0</p> 1595 enum LOG2_SAO_OFFSET_SCALE_LUMA 1596 { 1597 LOG2_SAO_OFFSET_SCALE_LUMA_0 = 0, //!< No additional details 1598 LOG2_SAO_OFFSET_SCALE_LUMA_1 = 1, //!< No additional details 1599 LOG2_SAO_OFFSET_SCALE_LUMA_2 = 2, //!< No additional details 1600 }; 1601 1602 //! \brief LOG2_SAO_OFFSET_SCALE_CHROMA 1603 //! \details 1604 //! <p>To scale SAO offset values for chroma samples.</p> 1605 //! <p>0 to Max(0,BitDepth<sub>C</sub>−10)</p> 1606 //! <p>default = 0</p> 1607 //! <p>Decoder Only</p> 1608 enum LOG2_SAO_OFFSET_SCALE_CHROMA 1609 { 1610 LOG2_SAO_OFFSET_SCALE_CHROMA_0 = 0, //!< No additional details 1611 LOG2_SAO_OFFSET_SCALE_CHROMA_1 = 1, //!< No additional details 1612 LOG2_SAO_OFFSET_SCALE_CHROMA_2 = 2, //!< No additional details 1613 }; 1614 1615 //! \brief CHROMA_SUBSAMPLING 1616 //! \details 1617 //! <p>Specify the chroma subsampling of the current bitstream to be decoded 1618 //! or encoded.</p> 1619 //! <p>000 (0h) - Reserved (This setting is reserved for Monochrome 1620 //! setting--currently not suppported)</p> 1621 //! <p>001 (1h) - 4:2:0</p> 1622 //! <p>010 (2h) - 4:2:2</p> 1623 //! <p>011 (3h) - 4:4:4</p> 1624 //! <p>All other values are invalid for both encoder and decoder.</p> 1625 enum CHROMA_SUBSAMPLING 1626 { 1627 CHROMA_SUBSAMPLING_420 = 1, //!< No additional details 1628 CHROMA_SUBSAMPLING_422 = 2, //!< No additional details 1629 CHROMA_SUBSAMPLING_444 = 3, //!< No additional details 1630 }; 1631 1632 //! \brief COLPICISI 1633 //! \details 1634 //! Specifies that the collocated picture is comprised solely of I slices 1635 //! and that there are no P or B slices in the picture. 1636 enum COLPICISI 1637 { 1638 COLPICISI_COLLOCATEDPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1639 }; 1640 1641 //! \brief CURPICISI 1642 //! \details 1643 //! Specifies that the current picture is comprised solely of I slices and 1644 //! that there are no P or B slices in the picture. 1645 enum CURPICISI 1646 { 1647 CURPICISI_CURRENTPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1648 }; 1649 1650 //! \brief INSERTTESTFLAG 1651 //! \details 1652 //! <p>CABAC 0 Word Insertion Test Enable (Encoder Only)This bit will modify 1653 //! CABAC K equation so that a positive K value can be generated easily. 1654 //! This is done for validation purpose only. In normal usage this bit 1655 //! should be set to 0.</p> 1656 //! <p>Regular equation for generating 'K' value when CABAC 0 Word Insertion 1657 //! Test Enable is set to 0.</p> 1658 //! <pre>K = {[((96 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs *3) 1659 //! + 1023) / 1024] - bytes_in_picture} / 3</pre> 1660 //! 1661 //! <p>Modified equation when CABAC 0 Word Insertion Test Enable bit set to 1662 //! 1.</p> 1663 //! 1664 //! <pre>K = {[((1536 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs 1665 //! *3) + 1023) / 1024] - bytes_in_picture} / 3</pre> 1666 //! 1667 //! <p>Encoder only feature.</p> 1668 enum INSERTTESTFLAG 1669 { 1670 INSERTTESTFLAG_UNNAMED0 = 0, //!< No additional details 1671 INSERTTESTFLAG_UNNAMED1 = 1, //!< No additional details 1672 }; 1673 1674 //! \brief CU_QP_DELTA_ENABLED_FLAG 1675 //! \details 1676 //! <p>cu_qp_delta_enabled_flag = 1 and Max_DQP_Level = 0 or 3 is supported 1677 //! for PAK standalone andVDEnc modes.</p> 1678 enum CU_QP_DELTA_ENABLED_FLAG 1679 { 1680 CU_QP_DELTA_ENABLED_FLAG_DISABLE = 0, //!< Does not allow QP change at CU or LCU level, the same QP is used for the entire slice. Max_DQP_Level = 0 (i.e. diff_cu_qp_delta_depath = 0). 1681 CU_QP_DELTA_ENABLED_FLAG_ENABLE = 1, //!< Allow QP change at CU level. MAX_DQP_level can be >0. 1682 }; 1683 1684 //! \brief SIGN_DATA_HIDING_FLAG 1685 //! \details 1686 //! Currently not supported in encoder, so must be set to 0 for encoding 1687 //! session. 1688 enum SIGN_DATA_HIDING_FLAG 1689 { 1690 SIGN_DATA_HIDING_FLAG_DISABLE = 0, //!< Specifies that sign bit hiding is disabled. 1691 SIGN_DATA_HIDING_FLAG_ENABLE = 1, //!< Specifies that sign bit hiding is enabled. 1692 }; 1693 1694 //! \brief FIELDPIC 1695 //! \details 1696 //! <p>Must be zero for encoder only.</p> 1697 enum FIELDPIC 1698 { 1699 FIELDPIC_VIDEOFRAME = 0, //!< No additional details 1700 FIELDPIC_VIDEOFIELD = 1, //!< No additional details 1701 }; 1702 1703 //! \brief BOTTOMFIELD 1704 //! \details 1705 //! <p>Must be zero for encoder only</p> 1706 enum BOTTOMFIELD 1707 { 1708 BOTTOMFIELD_BOTTOMFIELD = 0, //!< No additional details 1709 BOTTOMFIELD_TOPFIELD = 1, //!< No additional details 1710 }; 1711 1712 enum TRANSFORM_SKIP_ENABLED_FLAG 1713 { 1714 TRANSFORM_SKIP_ENABLED_FLAG_DISABLE = 0, //!< transform_skip_flag is not supported in the residual coding 1715 TRANSFORM_SKIP_ENABLED_FLAG_ENABLE = 1, //!< transform_skip_flag is supported 1716 }; 1717 1718 //! \brief AMP_ENABLED_FLAG 1719 //! \details 1720 //! In VDENC mode, this bit should be set to 1. 1721 enum AMP_ENABLED_FLAG 1722 { 1723 AMP_ENABLED_FLAG_DISABLE = 0, //!< Asymmetric motion partitions cannot be used in coding tree blocks. 1724 AMP_ENABLED_FLAG_ENABLE = 1, //!< Support asymmetric motion partitions, i.e. PartMode equal to PART_2NxnU, PART_2NxnD, PART_nLx2N, or PART_nRx2N. 1725 }; 1726 1727 enum TRANSQUANT_BYPASS_ENABLE_FLAG 1728 { 1729 TRANSQUANT_BYPASS_ENABLE_FLAG_DISABLE = 0, //!< cu_transquant_bypass is not supported 1730 TRANSQUANT_BYPASS_ENABLE_FLAG_ENABLE = 1, //!< cu_transquant_bypass is supported 1731 }; 1732 1733 //! \brief BIT_DEPTH_CHROMA_MINUS8 1734 //! \details 1735 //! This specifies the number of bit allow for Chroma pixels. In 8 bit mode, 1736 //! this must be set to 0. Encoder: Supports bit depths 8, 10 and 12 only. 1737 //! And also it must be same as Luma. Encoder: Does not support 10 or 12 bit 1738 //! Source Pixels and 8bit PAK. i.e. The source pixel depth should be less 1739 //! than or equal to the PAK bit depth. 1740 enum BIT_DEPTH_CHROMA_MINUS8 1741 { 1742 BIT_DEPTH_CHROMA_MINUS8_CHROMA8BIT = 0, //!< No additional details 1743 BIT_DEPTH_CHROMA_MINUS8_CHROMA9BIT = 1, //!< Only HEVC decoder supports 9 bits chroma.HEVC encoder does not supports 9 bits chroma. 1744 BIT_DEPTH_CHROMA_MINUS8_CHROMA10BIT = 2, //!< No additional details 1745 BIT_DEPTH_CHROMA_MINUS8_CHROMA11BIT = 3, //!< HEVC SCC does not support 11 bits chromaAlso only HEVC decoder (non-SCC) support 11 bits chromaHEVC encoder (non-SCC) does not support 11 bits chroma 1746 BIT_DEPTH_CHROMA_MINUS8_CHROMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1747 }; 1748 1749 //! \brief BIT_DEPTH_LUMA_MINUS8 1750 //! \details 1751 //! This specifies the number of bit allow for Luma pixels. In 8 bit mode, 1752 //! this must be set to 0. Encoder: Suports bit depths 8, 10 and 12 only. 1753 //! Encoder: Does not support 10 or 12 bit Source Pixels and 8bit PAK i.e. 1754 //! the source pixel depth should be less than or equal to PAK bit depth. 1755 enum BIT_DEPTH_LUMA_MINUS8 1756 { 1757 BIT_DEPTH_LUMA_MINUS8_LUMA8BIT = 0, //!< No additional details 1758 BIT_DEPTH_LUMA_MINUS8_LUMA9BIT = 1, //!< Only HEVC decoder supports 9 bits luma.HEVC encoder does not supports 9 bits luma. 1759 BIT_DEPTH_LUMA_MINUS8_LUMA10BIT = 2, //!< No additional details 1760 BIT_DEPTH_LUMA_MINUS8_LUMA11BIT = 3, //!< HEVC SCC does not support 11 bits LumaAlso only HEVC decoder (non-SCC) support 11 bits LumaHEVC encoder (non-SCC) does not support 11 bits Luma 1761 BIT_DEPTH_LUMA_MINUS8_LUMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1762 }; 1763 1764 //! \brief NONFIRSTPASSFLAG 1765 //! \details 1766 //! This signals the current pass is not the first pass. It will imply 1767 //! designate HW behavior. 1768 enum NONFIRSTPASSFLAG 1769 { 1770 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 1771 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 1772 }; 1773 1774 //! \brief LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1775 //! \details 1776 //! This is a mask bit controlling if the condition of any LCU in the frame 1777 //! exceeds LCUMaxSize. 1778 enum LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1779 { 1780 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit 0 of HCP_IMAGE_STATUS control register. 1781 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. 1782 }; 1783 1784 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1785 //! \details 1786 //! This is a mask bit controlling if the condition of frame level bit count 1787 //! exceeds FrameBitRateMax. 1788 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1789 { 1790 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_IMAGE_STATUS control register. 1791 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit inHCP_IMAGE_STATUS_MASK register 1792 }; 1793 1794 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1795 //! \details 1796 //! This is a mask bit controlling if the condition of frame level bit count 1797 //! is less than FrameBitRateMin. 1798 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1799 { 1800 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register. 1801 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit in HCP_IMAGE_STATUS_MASK register 1802 }; 1803 1804 //! \brief LOAD_SLICE_POINTER_FLAG 1805 //! \details 1806 //! <p>LoadBitStreamPointerPerSlice (Encoder-only)</p> 1807 //! <p>To support multiple slice picture and additional header/data 1808 //! insertion before and after an encoded slice. When this field is set to 1809 //! 0, bitstream pointer is only loaded once for the first slice of a frame. 1810 //! For subsequent slices in the frame, bitstream data are stitched together 1811 //! to form a single output data stream. When this field is set to 1, 1812 //! bitstream pointer is loaded for each slice of a frame. Basically 1813 //! bitstream data for different slices of a frame will be written to 1814 //! different memory locations.</p> 1815 enum LOAD_SLICE_POINTER_FLAG 1816 { 1817 LOAD_SLICE_POINTER_FLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame. 1818 LOAD_SLICE_POINTER_FLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of thebitstream buffer from the Indirect PAK-BSE Object Data Start Address field. 1819 }; 1820 1821 //! \brief FRAMEBITRATEMAXUNIT 1822 //! \details 1823 //! This field is the Frame Bitrate Maximum Limit Units. 1824 enum FRAMEBITRATEMAXUNIT 1825 { 1826 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 1827 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4kbyte unit 1828 }; 1829 1830 //! \brief FRAMEBITRATEMINUNIT 1831 //! \details 1832 //! This field is the Frame Bitrate Minimum Limit Units. 1833 enum FRAMEBITRATEMINUNIT 1834 { 1835 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 1836 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4kbyte unit 1837 }; 1838 1839 //! \brief FRAMEBITRATEMINDELTA 1840 //! \details 1841 //! This field is used to select the slice delta QP when FrameBitRateMin Is 1842 //! exceeded. It shares the same 1843 //! FrameBitrateMinUnit. 1844 enum FRAMEBITRATEMINDELTA 1845 { 1846 FRAMEBITRATEMINDELTA_UNNAMED0 = 0, //!< No additional details 1847 }; 1848 1849 //! \brief FRAMEBITRATEMAXDELTA 1850 //! \details 1851 //! This field is used to select the slice delta QP when FrameBitRateMax Is 1852 //! exceeded. It shares the same 1853 //! FrameBitrateMaxUnit. 1854 enum FRAMEBITRATEMAXDELTA 1855 { 1856 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 1857 }; 1858 1859 //! \brief MINFRAMESIZE 1860 //! \details 1861 //! <p>Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)</p> 1862 //! <p>Mininum Frame Size is specified to compensate for intel Rate Control 1863 //! Currently zero fill (no need to perform emulation byte insertion) is 1864 //! done only to the end of the CABAC_ZERO_WORD insertion (if any) at the 1865 //! last slice of a picture. It is needed for CBR. Intel encoder parameter. 1866 //! The caller should always make sure that the value, represented by 1867 //! Mininum Frame Size, is always less than maximum frame size 1868 //! FrameBitRateMax. This field is reserved in Decode mode.</p> 1869 enum MINFRAMESIZE 1870 { 1871 MINFRAMESIZE_UNNAMED0 = 0, //!< No additional details 1872 }; 1873 1874 //! \brief MINFRAMESIZEUNITS 1875 //! \details 1876 //! This field is the Minimum Frame Size Units 1877 enum MINFRAMESIZEUNITS 1878 { 1879 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 1880 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 16Kbytes. 1881 MINFRAMESIZEUNITS_COMPATIBILITYMODE = 2, //!< Minimum Frame Size is in 4bytes 1882 MINFRAMESIZEUNITS_16BYTES = 3, //!< Minimum Frame Size is 16 bytes. 1883 }; 1884 1885 //! \brief MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1886 //! \details 1887 //! <p>This controls the presense and inference of the use_integer_mv_flag 1888 //! that specifies the resolution of motion vectors for inter 1889 //! prediction.</p> 1890 //! <p>Decoder only (Encoder default to "00")</p> 1891 enum MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1892 { 1893 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_NOINTEGERMVFORTHEFRAME = 0, //!< No additional details 1894 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ONLYINTEGERMVFORTHEFRAME = 1, //!< No additional details 1895 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ADAPTIVEINTEGERMVFORTHEFRAME = 2, //!< Slice signal use_inter_mv_flag will indicate if the slice will use interger MV or not 1896 }; 1897 1898 //! \brief IBC_CONFIGURATION 1899 //! \details 1900 //! <p>IBC configuration is used configure Intra block copy.</p> 1901 //! <p>- Disable Intra block copy.</p> 1902 //! <p>- Limit Intra block copy from Left blocks only.</p> 1903 //! <p>- Allow full range of Intra block copy as specified in spec.</p> 1904 //! <p></p> 1905 enum IBC_CONFIGURATION 1906 { 1907 IBC_CONFIGURATION_UNNAMED0 = 0, //!< When IBC configuration is 0, intra block copy is disabled and it applies for both Fixed function encoder and decoder. 1908 IBC_CONFIGURATION_UNNAMED1 = 1, //!< When IBC configuration in fixed function encoder (VDENC) mode is set to 1, Intra block search includes only left region. 1909 IBC_CONFIGURATION_UNNAMED2 = 2, //!< No additional details 1910 IBC_CONFIGURATION_UNNAMED3 = 3, //!< When IBC configuration in VDENC mode is set to 3, Intra block search includes top and left regions.In decoder mode, When SCC is enabled this field should be set to 3. 1911 }; 1912 1913 //! \brief FRAME_CRC_TYPE 1914 //! \details 1915 //! <p>This indicates how CRC is generated. This bit is ignored and must be 1916 //! programmed to 0 if Frame CRC Enable is "0"</p> 1917 enum FRAME_CRC_TYPE 1918 { 1919 FRAME_CRC_TYPE_CRCWITHYUVVALUE = 0, //!< No additional details 1920 FRAME_CRC_TYPE_CRCWITHYVALUEONLY = 1, //!< No additional details 1921 }; 1922 1923 //! \name Initializations 1924 1925 //! \brief Explicit member initialization function HCP_PIC_STATE_CMDHCP_PIC_STATE_CMD1926 HCP_PIC_STATE_CMD() 1927 { 1928 DW0.Value = 0x73900027; 1929 //DW0.DwordLength = GetOpLength(dwSize); 1930 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPICSTATE; 1931 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 1932 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 1933 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 1934 1935 DW1.Value = 0x00000000; 1936 1937 DW2.Value = 0x00000000; 1938 //DW2.Mincusize = MINCUSIZE_8X8; 1939 //DW2.CtbsizeLcusize = CTBSIZE_LCUSIZE_ILLEGALRESERVED; 1940 //DW2.Mintusize = MINTUSIZE_4X4; 1941 //DW2.Maxtusize = MAXTUSIZE_4X4; 1942 //DW2.Minpcmsize = MINPCMSIZE_8X8; 1943 //DW2.Maxpcmsize = MAXPCMSIZE_8X8; 1944 //DW2.Log2SaoOffsetScaleLuma = LOG2_SAO_OFFSET_SCALE_LUMA_0; 1945 //DW2.Log2SaoOffsetScaleChroma = LOG2_SAO_OFFSET_SCALE_CHROMA_0; 1946 //DW2.ChromaSubsampling = 0; 1947 1948 DW3.Value = 0x00000000; 1949 //DW3.Colpicisi = COLPICISI_COLLOCATEDPICTUREHASATLEASTONEPORBSLICE; 1950 //DW3.Curpicisi = CURPICISI_CURRENTPICTUREHASATLEASTONEPORBSLICE; 1951 //DW3.Inserttestflag = INSERTTESTFLAG_UNNAMED0; 1952 1953 DW4.Value = 0x00000000; 1954 //DW4.CuQpDeltaEnabledFlag = CU_QP_DELTA_ENABLED_FLAG_DISABLE; 1955 //DW4.SignDataHidingFlag = SIGN_DATA_HIDING_FLAG_DISABLE; 1956 //DW4.Fieldpic = FIELDPIC_VIDEOFRAME; 1957 //DW4.Bottomfield = BOTTOMFIELD_BOTTOMFIELD; 1958 //DW4.TransformSkipEnabledFlag = TRANSFORM_SKIP_ENABLED_FLAG_DISABLE; 1959 //DW4.AmpEnabledFlag = AMP_ENABLED_FLAG_DISABLE; 1960 //DW4.TransquantBypassEnableFlag = TRANSQUANT_BYPASS_ENABLE_FLAG_DISABLE; 1961 1962 DW5.Value = 0x00000000; 1963 //DW5.BitDepthChromaMinus8 = BIT_DEPTH_CHROMA_MINUS8_CHROMA8BIT; 1964 //DW5.BitDepthLumaMinus8 = BIT_DEPTH_LUMA_MINUS8_LUMA8BIT; 1965 1966 DW6.Value = 0x00000000; 1967 //DW6.Nonfirstpassflag = NONFIRSTPASSFLAG_DISABLE; 1968 //DW6.LcumaxbitstatusenLcumaxsizereportmask = LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_DISABLE; 1969 //DW6.FrameszoverstatusenFramebitratemaxreportmask = FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE; 1970 //DW6.FrameszunderstatusenFramebitrateminreportmask = FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE; 1971 //DW6.LoadSlicePointerFlag = LOAD_SLICE_POINTER_FLAG_DISABLE; 1972 1973 DW7.Value = 0x00000000; 1974 //DW7.Framebitratemaxunit = FRAMEBITRATEMAXUNIT_BYTE; 1975 1976 DW8.Value = 0x00000000; 1977 //DW8.Framebitrateminunit = FRAMEBITRATEMINUNIT_BYTE; 1978 1979 DW9.Value = 0x00000000; 1980 //DW9.Framebitratemindelta = FRAMEBITRATEMINDELTA_UNNAMED0; 1981 //DW9.Framebitratemaxdelta = FRAMEBITRATEMAXDELTA_UNNAMED0; 1982 1983 DW10_11.Value[0] = DW10_11.Value[1] = 0x00000000; 1984 1985 DW12_13.Value[0] = DW12_13.Value[1] = 0x00000000; 1986 1987 DW14_15.Value[0] = DW14_15.Value[1] = 0x00000000; 1988 1989 DW16_17.Value[0] = DW16_17.Value[1] = 0x00000000; 1990 1991 DW18.Value = 0x00000000; 1992 //DW18.Minframesize = MINFRAMESIZE_UNNAMED0; 1993 //DW18.Minframesizeunits = MINFRAMESIZEUNITS_4KB; 1994 1995 DW19.Value = 0x00000000; 1996 1997 DW20.Value = 0x00000000; 1998 1999 DW21.Value = 0x00000000; 2000 2001 DW22.Value = 0x00000000; 2002 2003 DW23.Value = 0x00000000; 2004 2005 memset(&SseThresholdsForClass18, 0, sizeof(SseThresholdsForClass18)); 2006 2007 DW32.Value = 0x00000000; 2008 2009 DW33.Value = 0x00000000; 2010 2011 DW34.Value = 0x00000000; 2012 //DW34.MotionVectorResolutionControlIdc = MOTION_VECTOR_RESOLUTION_CONTROL_IDC_NOINTEGERMVFORTHEFRAME; 2013 2014 DW35.Value = 0x00000000; 2015 //DW35.IbcConfiguration = IBC_CONFIGURATION_UNNAMED0; 2016 2017 DW36.Value = 0x00000000; 2018 //DW36.FrameCrcType = FRAME_CRC_TYPE_CRCWITHYUVVALUE; 2019 2020 DW37.Value = 0x00000000; 2021 2022 DW38.Value = 0x00000000; 2023 2024 DW39_40.Value[0] = DW39_40.Value[1] = 0x00000000; 2025 } 2026 2027 static const size_t dwSize = 41; 2028 static const size_t byteSize = 164; 2029 }; 2030 2031 //! 2032 //! \brief HCP_TILE_POSITION_IN_CTB 2033 //! \details 2034 //! 2035 //! 2036 struct HCP_TILE_POSITION_IN_CTB_CMD 2037 { 2038 union 2039 { 2040 struct 2041 { 2042 uint32_t Ctbpos0I : __CODEGEN_BITFIELD( 0, 7) ; //!< CtbPos0+i 2043 uint32_t Ctbpos1I : __CODEGEN_BITFIELD( 8, 15) ; //!< CtbPos1+i 2044 uint32_t Ctbpos2I : __CODEGEN_BITFIELD(16, 23) ; //!< CtbPos2+i 2045 uint32_t Ctbpos3I : __CODEGEN_BITFIELD(24, 31) ; //!< CtbPos3+i 2046 }; 2047 uint32_t Value; 2048 } DW0; 2049 2050 //! \name Local enumerations 2051 2052 //! \name Initializations 2053 2054 //! \brief Explicit member initialization function HCP_TILE_POSITION_IN_CTB_CMDHCP_TILE_POSITION_IN_CTB_CMD2055 HCP_TILE_POSITION_IN_CTB_CMD() 2056 { 2057 DW0.Value = 0x00000000; 2058 } 2059 2060 static const size_t dwSize = 1; 2061 static const size_t byteSize = 4; 2062 }; 2063 2064 //! 2065 //! \brief HCP_TILE_POSITION_IN_CTB_MSB 2066 //! \details 2067 //! Added to support 16k picture size. 2068 //! 2069 struct HCP_TILE_POSITION_IN_CTB_MSB_CMD 2070 { 2071 union 2072 { 2073 struct 2074 { 2075 uint32_t CtbRowPositionOfTileColumn098 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 0 [9:8] 2076 uint32_t CtbRowPositionOfTileColumn198 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 1 [9:8] 2077 uint32_t CtbRowPositionOfTileColumn298 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 2 [9:8] 2078 uint32_t CtbRowPositionOfTileColumn398 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 3 [9:8] 2079 uint32_t CtbRowPositionOfTileColumn498 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 4 [9:8] 2080 uint32_t CtbRowPositionOfTileColumn598 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb row position of tile column 5 [9:8] 2081 uint32_t CtbRowPositionOfTileColumn698 : __CODEGEN_BITFIELD(12, 13) ; //!< Ctb row position of tile column 6 [9:8] 2082 uint32_t CtbRowPositionOfTileColumn798 : __CODEGEN_BITFIELD(14, 15) ; //!< Ctb row position of tile column 7 [9:8] 2083 uint32_t CtbRowPositionOfTileColumn898 : __CODEGEN_BITFIELD(16, 17) ; //!< Ctb row position of tile column 8 [9:8] 2084 uint32_t CtbRowPositionOfTileColumn998 : __CODEGEN_BITFIELD(18, 19) ; //!< Ctb row position of tile column 9 [9:8] 2085 uint32_t CtbRowPositionOfTileColumn1098 : __CODEGEN_BITFIELD(20, 21) ; //!< Ctb row position of tile column 10 [9:8] 2086 uint32_t CtbRowPositionOfTileColumn1198 : __CODEGEN_BITFIELD(22, 23) ; //!< Ctb row position of tile column 11 [9:8] 2087 uint32_t CtbRowPositionOfTileColumn1298 : __CODEGEN_BITFIELD(24, 25) ; //!< Ctb row position of tile column 12 [9:8] 2088 uint32_t CtbRowPositionOfTileColumn1398 : __CODEGEN_BITFIELD(26, 27) ; //!< Ctb row position of tile column 13 [9:8] 2089 uint32_t CtbRowPositionOfTileColumn1498 : __CODEGEN_BITFIELD(28, 29) ; //!< Ctb row position of tile column 14 [9:8] 2090 uint32_t CtbRowPositionOfTileColumn1598 : __CODEGEN_BITFIELD(30, 31) ; //!< Ctb row position of tile column 15 [9:8] 2091 }; 2092 uint32_t Value; 2093 } DW0; 2094 union 2095 { 2096 struct 2097 { 2098 uint32_t CtbRowPositionOfTileColumn1698 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 16 [9:8] 2099 uint32_t CtbRowPositionOfTileColumn1798 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 17 [9:8] 2100 uint32_t CtbRowPositionOfTileColumn1898 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 18 [9:8] 2101 uint32_t CtbRowPositionOfTileColumn1998 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 19 [9:8] 2102 uint32_t CtbRowPositionOfTileColumn2098 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 20 [9:8] 2103 uint32_t CtbPositionOfTile2198 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb position of tile 21 [9:8] 2104 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 2105 }; 2106 uint32_t Value; 2107 } DW1; 2108 2109 //! \name Local enumerations 2110 2111 //! \name Initializations 2112 2113 //! \brief Explicit member initialization function HCP_TILE_POSITION_IN_CTB_MSB_CMDHCP_TILE_POSITION_IN_CTB_MSB_CMD2114 HCP_TILE_POSITION_IN_CTB_MSB_CMD() 2115 { 2116 DW0.Value = 0x00000000; 2117 2118 DW1.Value = 0x00000000; 2119 } 2120 2121 static const size_t dwSize = 2; 2122 static const size_t byteSize = 8; 2123 }; 2124 2125 //! 2126 //! \brief HCP_TILE_STATE 2127 //! \details 2128 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2129 //! Commands. Each HCP command has assigned a media instruction command as 2130 //! defined in DWord 0, BitField 22:16. 2131 //! 2132 //! This command is valid for decoder only. 2133 //! 2134 struct HCP_TILE_STATE_CMD 2135 { 2136 union 2137 { 2138 struct 2139 { 2140 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2141 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2142 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2143 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2144 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2145 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2146 }; 2147 uint32_t Value; 2148 } DW0; 2149 union 2150 { 2151 struct 2152 { 2153 uint32_t Numtilerowsminus1 : __CODEGEN_BITFIELD( 0, 4) ; //!< NumTileRowsMinus1 2154 uint32_t Numtilecolumnsminus1 : __CODEGEN_BITFIELD( 5, 9) ; //!< NumTileColumnsMinus1 2155 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 2156 }; 2157 uint32_t Value; 2158 } DW1; 2159 HCP_TILE_POSITION_IN_CTB_CMD CtbColumnPositionOfTileColumn[5]; //!< DW2..6, Ctb column position of tile column 2160 HCP_TILE_POSITION_IN_CTB_CMD CtbRowPositionOfTileRow[6]; //!< DW7..12, Ctb row position of tile row 2161 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbColumnPositionMsb; //!< DW13..14, Ctb column position MSB 2162 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbRowPositionMsb; //!< DW15..16, Ctb row position MSB 2163 2164 //! \name Local enumerations 2165 2166 enum MEDIA_INSTRUCTION_COMMAND 2167 { 2168 MEDIA_INSTRUCTION_COMMAND_HCPTILESTATE = 17, //!< No additional details 2169 }; 2170 2171 //! \brief MEDIA_INSTRUCTION_OPCODE 2172 //! \details 2173 //! Codec/Engine Name = HCP = 7h 2174 enum MEDIA_INSTRUCTION_OPCODE 2175 { 2176 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2177 }; 2178 2179 enum PIPELINE_TYPE 2180 { 2181 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2182 }; 2183 2184 enum COMMAND_TYPE 2185 { 2186 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2187 }; 2188 2189 //! \name Initializations 2190 2191 //! \brief Explicit member initialization function HCP_TILE_STATE_CMDHCP_TILE_STATE_CMD2192 HCP_TILE_STATE_CMD() 2193 { 2194 DW0.Value = 0x7391000f; 2195 //DW0.DwordLength = GetOpLength(dwSize); 2196 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPTILESTATE; 2197 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 2198 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 2199 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2200 2201 DW1.Value = 0x00000000; 2202 } 2203 2204 static const size_t dwSize = 17; 2205 static const size_t byteSize = 68; 2206 }; 2207 2208 //! 2209 //! \brief HCP_REF_LIST_ENTRY 2210 //! \details 2211 //! 2212 //! 2213 struct HCP_REF_LIST_ENTRY_CMD 2214 { 2215 union 2216 { 2217 struct 2218 { 2219 uint32_t ReferencePictureTbValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Reference Picture tb Value 2220 uint32_t ListEntryLxReferencePictureFrameIdRefaddr07 : __CODEGEN_BITFIELD( 8, 10) ; //!< list_entry_lX: Reference Picture Frame ID (RefAddr[0-7]) 2221 uint32_t ChromaWeightLxFlag : __CODEGEN_BITFIELD(11, 11) ; //!< CHROMA_WEIGHT_LX_FLAG 2222 uint32_t LumaWeightLxFlag : __CODEGEN_BITFIELD(12, 12) ; //!< LUMA_WEIGHT_LX_FLAG 2223 uint32_t Longtermreference : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERMREFERENCE 2224 uint32_t FieldPicFlag : __CODEGEN_BITFIELD(14, 14) ; //!< FIELD_PIC_FLAG 2225 uint32_t BottomFieldFlag : __CODEGEN_BITFIELD(15, 15) ; //!< BOTTOM_FIELD_FLAG 2226 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2227 }; 2228 uint32_t Value; 2229 } DW0; 2230 2231 //! \name Local enumerations 2232 2233 //! \brief CHROMA_WEIGHT_LX_FLAG 2234 //! \details 2235 //! Where X is the RefPicListNum and i is the list entry number 0 through 2236 //! 15. DW2 corresponds to i=0, 2237 //! DW17 corresponds to i=15. 2238 enum CHROMA_WEIGHT_LX_FLAG 2239 { 2240 CHROMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORCHROMA = 0, //!< No additional details 2241 CHROMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORCHROMA = 1, //!< No additional details 2242 }; 2243 2244 //! \brief LUMA_WEIGHT_LX_FLAG 2245 //! \details 2246 //! Where X is the RefPicListNum and i is the list entry number 0 through 2247 //! 15. DW2 corresponds to i=0, 2248 //! DW17 corresponds to i=15. 2249 enum LUMA_WEIGHT_LX_FLAG 2250 { 2251 LUMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORLUMA = 0, //!< No additional details 2252 LUMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORLUMA = 1, //!< No additional details 2253 }; 2254 2255 //! \brief LONGTERMREFERENCE 2256 //! \details 2257 //! Where X is the RefPicListNum and i is the list entry number 0 through 2258 //! 15. DW2 corresponds to i=0, 2259 //! DW17 corresponds to i=15. 2260 enum LONGTERMREFERENCE 2261 { 2262 LONGTERMREFERENCE_SHORTTERMREFERENCE = 0, //!< No additional details 2263 LONGTERMREFERENCE_LONGTERMREFERENCE = 1, //!< No additional details 2264 }; 2265 2266 //! \brief FIELD_PIC_FLAG 2267 //! \details 2268 //! Where X is the RefPicListNum and i is the list entry number 0 through 2269 //! 15. DW2 corresponds to i=0, 2270 //! DW17 corresponds to i=15. 2271 enum FIELD_PIC_FLAG 2272 { 2273 FIELD_PIC_FLAG_VIDEOFRAME = 0, //!< No additional details 2274 FIELD_PIC_FLAG_VIDEOFIELD = 1, //!< No additional details 2275 }; 2276 2277 //! \brief BOTTOM_FIELD_FLAG 2278 //! \details 2279 //! Where X is the RefPicListNum and i is the list entry number 0 through 2280 //! 15. DW2 corresponds to i=0, 2281 //! DW17 corresponds to i=15. 2282 enum BOTTOM_FIELD_FLAG 2283 { 2284 BOTTOM_FIELD_FLAG_BOTTOMFIELD = 0, //!< No additional details 2285 BOTTOM_FIELD_FLAG_TOPFIELD = 1, //!< No additional details 2286 }; 2287 2288 //! \name Initializations 2289 2290 //! \brief Explicit member initialization function HCP_REF_LIST_ENTRY_CMDHCP_REF_LIST_ENTRY_CMD2291 HCP_REF_LIST_ENTRY_CMD() 2292 { 2293 DW0.Value = 0x00000000; 2294 //DW0.ChromaWeightLxFlag = CHROMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORCHROMA; 2295 //DW0.LumaWeightLxFlag = LUMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORLUMA; 2296 //DW0.Longtermreference = LONGTERMREFERENCE_SHORTTERMREFERENCE; 2297 //DW0.FieldPicFlag = FIELD_PIC_FLAG_VIDEOFRAME; 2298 //DW0.BottomFieldFlag = BOTTOM_FIELD_FLAG_BOTTOMFIELD; 2299 } 2300 2301 static const size_t dwSize = 1; 2302 static const size_t byteSize = 4; 2303 }; 2304 2305 //! 2306 //! \brief HCP_REF_IDX_STATE 2307 //! \details 2308 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2309 //! Commands. Each HCP command has assigned a media instruction command as 2310 //! defined in DWord 0, BitField 22:16. 2311 //! 2312 //! This is a slice level command used in both encoding and decoding 2313 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 2314 //! 2315 //! Unlike AVC, HEVC allows 16 reference idx entries in each of the L0 and 2316 //! L1 list for a progressive picture. Hence, a max total 32 reference idx 2317 //! in both lists together. The same when the picture is a field picture. 2318 //! Regardless the number of reference idx entries, there are only max 8 2319 //! reference pictures exist at any one time. Multiple reference idx can 2320 //! point to the same reference picture and can optionally pic a top or 2321 //! bottom field, or frame. 2322 //! 2323 //! For P-Slice, this command is issued only once, representing L0 list. For 2324 //! B-Slice, this command can be issued up to two times, one for L0 list and 2325 //! one for L1 list. 2326 //! 2327 struct HCP_REF_IDX_STATE_CMD 2328 { 2329 union 2330 { 2331 struct 2332 { 2333 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2334 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2335 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2336 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2337 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2338 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2339 }; 2340 uint32_t Value; 2341 } DW0; 2342 union 2343 { 2344 struct 2345 { 2346 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2347 uint32_t NumRefIdxLRefpiclistnumActiveMinus1 : __CODEGEN_BITFIELD( 1, 4) ; //!< num_ref_idx_l[RefPicListNum]_active_minus1 2348 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 2349 }; 2350 uint32_t Value; 2351 } DW1; 2352 HCP_REF_LIST_ENTRY_CMD Entries[16]; //!< DW2..17, Entries 2353 2354 //! \name Local enumerations 2355 2356 enum MEDIA_INSTRUCTION_COMMAND 2357 { 2358 MEDIA_INSTRUCTION_COMMAND_HCPREFIDXSTATE = 18, //!< No additional details 2359 }; 2360 2361 //! \brief MEDIA_INSTRUCTION_OPCODE 2362 //! \details 2363 //! Codec/Engine Name = HCP = 7h 2364 enum MEDIA_INSTRUCTION_OPCODE 2365 { 2366 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2367 }; 2368 2369 enum PIPELINE_TYPE 2370 { 2371 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2372 }; 2373 2374 enum COMMAND_TYPE 2375 { 2376 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2377 }; 2378 2379 enum REFPICLISTNUM 2380 { 2381 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2382 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2383 }; 2384 2385 //! \name Initializations 2386 2387 //! \brief Explicit member initialization function HCP_REF_IDX_STATE_CMDHCP_REF_IDX_STATE_CMD2388 HCP_REF_IDX_STATE_CMD() 2389 { 2390 DW0.Value = 0x73920010; 2391 //DW0.DwordLength = GetOpLength(dwSize); 2392 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPREFIDXSTATE; 2393 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 2394 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 2395 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2396 2397 DW1.Value = 0x00000000; 2398 //DW1.Refpiclistnum = REFPICLISTNUM_REFERENCEPICTURELIST0; 2399 } 2400 2401 static const size_t dwSize = 18; 2402 static const size_t byteSize = 72; 2403 }; 2404 2405 //! 2406 //! \brief HCP_WEIGHTOFFSET_LUMA_ENTRY 2407 //! \details 2408 //! 2409 //! 2410 struct HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD 2411 { 2412 union 2413 { 2414 struct 2415 { 2416 uint32_t DeltaLumaWeightLxI : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_luma_weight_lX[i] 2417 uint32_t LumaOffsetLxI : __CODEGEN_BITFIELD( 8, 15) ; //!< luma_offset_lX[i] 2418 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 2419 uint32_t LumaOffsetLxIMsbyte : __CODEGEN_BITFIELD(24, 31) ; //!< luma_offset_lX[i] MSByte 2420 }; 2421 uint32_t Value; 2422 } DW0; 2423 2424 //! \name Local enumerations 2425 2426 //! \name Initializations 2427 2428 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_LUMA_ENTRY_CMDHCP_WEIGHTOFFSET_LUMA_ENTRY_CMD2429 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD() 2430 { 2431 DW0.Value = 0x00000000; 2432 } 2433 2434 static const size_t dwSize = 1; 2435 static const size_t byteSize = 4; 2436 }; 2437 2438 //! 2439 //! \brief HCP_WEIGHTOFFSET_CHROMA_ENTRY 2440 //! \details 2441 //! 2442 //! 2443 struct HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD 2444 { 2445 union 2446 { 2447 struct 2448 { 2449 uint32_t DeltaChromaWeightLxI0 : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_chroma_weight_lX[i][0] 2450 uint32_t ChromaoffsetlxI0 : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i][0] 2451 uint32_t DeltaChromaWeightLxI1 : __CODEGEN_BITFIELD(16, 23) ; //!< delta_chroma_weight_lX[i][1] 2452 uint32_t ChromaoffsetlxI1 : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX [i][1] 2453 }; 2454 uint32_t Value; 2455 } DW0; 2456 2457 //! \name Local enumerations 2458 2459 //! \name Initializations 2460 2461 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMDHCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD2462 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD() 2463 { 2464 DW0.Value = 0x00000000; 2465 } 2466 2467 static const size_t dwSize = 1; 2468 static const size_t byteSize = 4; 2469 }; 2470 2471 //! 2472 //! \brief HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY 2473 //! \details 2474 //! 2475 //! 2476 struct HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD 2477 { 2478 union 2479 { 2480 struct 2481 { 2482 uint32_t ChromaoffsetlxI0Msbyte : __CODEGEN_BITFIELD( 0, 7) ; //!< ChromaOffsetLX[i][0] MSByte 2483 uint32_t ChromaoffsetlxI10Msbyte : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i+1][0] MSByte 2484 uint32_t ChromaoffsetlxI1Msbyte : __CODEGEN_BITFIELD(16, 23) ; //!< ChromaOffsetLX[i][1] MSByte 2485 uint32_t ChromaoffsetlxI11Msbyte : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX[i+1][1] MSByte 2486 }; 2487 uint32_t Value; 2488 } DW0; 2489 2490 //! \name Local enumerations 2491 2492 //! \name Initializations 2493 2494 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMDHCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD2495 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD() 2496 { 2497 DW0.Value = 0x00000000; 2498 } 2499 2500 static const size_t dwSize = 1; 2501 static const size_t byteSize = 4; 2502 }; 2503 2504 //! 2505 //! \brief HCP_WEIGHTOFFSET_STATE 2506 //! \details 2507 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2508 //! Commands. Each HCP command has assigned a media instruction command as 2509 //! defined in DWord 0, BitField 22:16. 2510 //! 2511 //! This slice level command is issued in both the encoding and decoding 2512 //! processes, if the weighted_pred_flag or weighted_bipred_flag equals one. 2513 //! If zero, then this command is not issued. Weight Prediction Values are 2514 //! provided in this command. Only Explicit Weight Prediction is supported 2515 //! in encoder. For P-Slice, this command is issued only once together with 2516 //! HCP_REF_IDX_STATE Command for L0 list. For B-Slice, this command can be 2517 //! issued up to two times together with HCP_REF_IDX_STATE Command, one for 2518 //! L0 list and one for L1 list. 2519 //! 2520 struct HCP_WEIGHTOFFSET_STATE_CMD 2521 { 2522 union 2523 { 2524 struct 2525 { 2526 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2527 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2528 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2529 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2530 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2531 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2532 }; 2533 uint32_t Value; 2534 } DW0; 2535 union 2536 { 2537 struct 2538 { 2539 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2540 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2541 }; 2542 uint32_t Value; 2543 } DW1; 2544 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD Lumaoffsets[16]; //!< DW2..17, LumaOffsets 2545 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD Chromaoffsets[16]; //!< DW18..33, ChromaOffsets 2546 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD Chromaoffsetsext[8]; //!< DW34..41, ChromaOffsetsExt 2547 2548 //! \name Local enumerations 2549 2550 enum MEDIA_INSTRUCTION_COMMAND 2551 { 2552 MEDIA_INSTRUCTION_COMMAND_HCPWEIGHTOFFSETSTATE = 19, //!< No additional details 2553 }; 2554 2555 //! \brief MEDIA_INSTRUCTION_OPCODE 2556 //! \details 2557 //! Codec/Engine Name = HCP = 7h 2558 enum MEDIA_INSTRUCTION_OPCODE 2559 { 2560 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2561 }; 2562 2563 enum PIPELINE_TYPE 2564 { 2565 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2566 }; 2567 2568 enum COMMAND_TYPE 2569 { 2570 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2571 }; 2572 2573 enum REFPICLISTNUM 2574 { 2575 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2576 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2577 }; 2578 2579 //! \name Initializations 2580 2581 //! \brief Explicit member initialization function HCP_WEIGHTOFFSET_STATE_CMDHCP_WEIGHTOFFSET_STATE_CMD2582 HCP_WEIGHTOFFSET_STATE_CMD() 2583 { 2584 DW0.Value = 0x73930028; 2585 //DW0.DwordLength = GetOpLength(dwSize); 2586 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPWEIGHTOFFSETSTATE; 2587 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 2588 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 2589 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 2590 2591 DW1.Value = 0x00000000; 2592 //DW1.Refpiclistnum = REFPICLISTNUM_REFERENCEPICTURELIST0; 2593 } 2594 2595 static const size_t dwSize = 42; 2596 static const size_t byteSize = 168; 2597 }; 2598 2599 //! 2600 //! \brief HCP_SLICE_STATE 2601 //! \details 2602 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2603 //! Commands. Each HCP command has assigned a media instruction command as 2604 //! defined in DWord 0, BitField 22:16. 2605 //! 2606 //! This is a slice level command used in both encoding and decoding 2607 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 2608 //! 2609 struct HCP_SLICE_STATE_CMD 2610 { 2611 union 2612 { 2613 struct 2614 { 2615 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2616 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2617 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2618 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2619 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2620 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2621 }; 2622 uint32_t Value; 2623 } DW0; 2624 union 2625 { 2626 struct 2627 { 2628 uint32_t SlicestartctbxOrSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< SliceStartCtbX or (slice_start_lcu_x encoder) 2629 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2630 uint32_t SlicestartctbyOrSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 25) ; //!< SliceStartCtbY or (slice_start_lcu_y encoder) 2631 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2632 }; 2633 uint32_t Value; 2634 } DW1; 2635 union 2636 { 2637 struct 2638 { 2639 uint32_t NextslicestartctbxOrNextSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSliceStartCtbX or (next_slice_start_lcu_x encoder) 2640 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2641 uint32_t NextslicestartctbyOrNextSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 26) ; //!< NextSliceStartCtbY or (next_slice_start_lcu_y encoder) 2642 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 2643 }; 2644 uint32_t Value; 2645 } DW2; 2646 union 2647 { 2648 struct 2649 { 2650 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 1) ; //!< SLICE_TYPE 2651 uint32_t Lastsliceofpic : __CODEGEN_BITFIELD( 2, 2) ; //!< LASTSLICEOFPIC 2652 uint32_t SliceqpSignFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< SliceQp Sign Flag 2653 uint32_t DependentSliceFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< dependent_slice_flag 2654 uint32_t SliceTemporalMvpEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< slice_temporal_mvp_enable_flag 2655 uint32_t Sliceqp : __CODEGEN_BITFIELD( 6, 11) ; //!< SliceQp 2656 uint32_t SliceCbQpOffset : __CODEGEN_BITFIELD(12, 16) ; //!< SLICE_CB_QP_OFFSET 2657 uint32_t SliceCrQpOffset : __CODEGEN_BITFIELD(17, 21) ; //!< SLICE_CR_QP_OFFSET 2658 uint32_t Intrareffetchdisable : __CODEGEN_BITFIELD(22, 22) ; //!< IntraRefFetchDisable 2659 uint32_t CuChromaQpOffsetEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cu_chroma_qp_offset_enabled_flag 2660 uint32_t Lastsliceoftile : __CODEGEN_BITFIELD(24, 24) ; //!< LastSliceOfTile 2661 uint32_t Lastsliceoftilecolumn : __CODEGEN_BITFIELD(25, 25) ; //!< LastSliceOfTileColumn 2662 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2663 }; 2664 uint32_t Value; 2665 } DW3; 2666 union 2667 { 2668 struct 2669 { 2670 uint32_t SliceHeaderDisableDeblockingFilterFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< slice_header_disable_deblocking_filter_flag 2671 uint32_t SliceTcOffsetDiv2OrFinalTcOffsetDiv2Encoder : __CODEGEN_BITFIELD( 1, 4) ; //!< slice_tc_offset_div2 or (final tc_offset_div2 Encoder) 2672 uint32_t SliceBetaOffsetDiv2OrFinalBetaOffsetDiv2Encoder : __CODEGEN_BITFIELD( 5, 8) ; //!< slice_beta_offset_div2 or (final Beta_Offset_div2 Encoder) 2673 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 2674 uint32_t SliceLoopFilterAcrossSlicesEnabledFlag : __CODEGEN_BITFIELD(10, 10) ; //!< slice_loop_filter_across_slices_enabled_flag 2675 uint32_t SliceSaoChromaFlag : __CODEGEN_BITFIELD(11, 11) ; //!< slice_sao_chroma_flag 2676 uint32_t SliceSaoLumaFlag : __CODEGEN_BITFIELD(12, 12) ; //!< slice_sao_luma_flag 2677 uint32_t MvdL1ZeroFlag : __CODEGEN_BITFIELD(13, 13) ; //!< mvd_l1_zero_flag 2678 uint32_t Islowdelay : __CODEGEN_BITFIELD(14, 14) ; //!< isLowDelay 2679 uint32_t CollocatedFromL0Flag : __CODEGEN_BITFIELD(15, 15) ; //!< collocated_from_l0_flag 2680 uint32_t Chromalog2Weightdenom : __CODEGEN_BITFIELD(16, 18) ; //!< ChromaLog2WeightDenom 2681 uint32_t LumaLog2WeightDenom : __CODEGEN_BITFIELD(19, 21) ; //!< luma_log2_weight_denom 2682 uint32_t CabacInitFlag : __CODEGEN_BITFIELD(22, 22) ; //!< cabac_init_flag 2683 uint32_t Maxmergeidx : __CODEGEN_BITFIELD(23, 25) ; //!< MAXMERGEIDX 2684 uint32_t Collocatedrefidx : __CODEGEN_BITFIELD(26, 28) ; //!< CollocatedRefIDX 2685 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2686 }; 2687 uint32_t Value; 2688 } DW4; 2689 union 2690 { 2691 struct 2692 { 2693 uint32_t Sliceheaderlength : __CODEGEN_BITFIELD( 0, 15) ; //!< SliceHeaderLength 2694 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2695 }; 2696 uint32_t Value; 2697 } DW5; 2698 union 2699 { 2700 struct 2701 { 2702 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 2703 uint32_t Roundintra : __CODEGEN_BITFIELD(20, 23) ; //!< ROUNDINTRA 2704 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 25) ; //!< Reserved 2705 uint32_t Roundinter : __CODEGEN_BITFIELD(26, 29) ; //!< ROUNDINTER 2706 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2707 }; 2708 uint32_t Value; 2709 } DW6; 2710 union 2711 { 2712 struct 2713 { 2714 uint32_t DependentSliceDueToTileSplit : __CODEGEN_BITFIELD( 0, 0) ; //!< Dependent Slice due to Tile Split 2715 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD( 1, 1) ; //!< CABACZEROWORDINSERTIONENABLE 2716 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD( 2, 2) ; //!< EMULATIONBYTESLICEINSERTENABLE 2717 uint32_t Reserved227 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2718 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< TAIL_INSERTION_ENABLE 2719 uint32_t SlicedataEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SLICEDATA_ENABLE 2720 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< HEADER_INSERTION_ENABLE 2721 uint32_t Reserved235 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 2722 }; 2723 uint32_t Value; 2724 } DW7; 2725 union 2726 { 2727 struct 2728 { 2729 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 2730 uint32_t IndirectPakBseDataStartOffsetWrite : __CODEGEN_BITFIELD( 6, 28) ; //!< Indirect PAK-BSE Data Start Offset (Write) 2731 uint32_t Reserved285 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2732 }; 2733 uint32_t Value; 2734 } DW8; 2735 union 2736 { 2737 struct 2738 { 2739 uint32_t TransformskipLambda : __CODEGEN_BITFIELD( 0, 15) ; //!< Transformskip_lambda 2740 uint32_t Reserved304 : __CODEGEN_BITFIELD(16, 30) ; //!< Reserved 2741 uint32_t ForceSaoParametersToZero : __CODEGEN_BITFIELD(31, 31) ; //!< Force SAO parameters to zero 2742 }; 2743 uint32_t Value; 2744 } DW9; 2745 union 2746 { 2747 struct 2748 { 2749 uint32_t TransformskipNumzerocoeffsFactor0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Transformskip_numzerocoeffs_factor0 2750 uint32_t TransformskipNumnonzerocoeffsFactor0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Transformskip_numnonzerocoeffs_factor0 2751 uint32_t TransformskipNumzerocoeffsFactor1 : __CODEGEN_BITFIELD(16, 23) ; //!< Transformskip_numzerocoeffs_factor1 2752 uint32_t TransformskipNumnonzerocoeffsFactor1 : __CODEGEN_BITFIELD(24, 31) ; //!< Transformskip_numnonzerocoeffs_factor1 2753 }; 2754 uint32_t Value; 2755 } DW10; 2756 union 2757 { 2758 struct 2759 { 2760 uint32_t Originalslicestartctbx : __CODEGEN_BITFIELD( 0, 9) ; //!< OriginalSliceStartCtbX 2761 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2762 uint32_t Originalslicestartctby : __CODEGEN_BITFIELD(16, 25) ; //!< OriginalSliceStartCtbY 2763 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2764 }; 2765 uint32_t Value; 2766 } DW11; 2767 union 2768 { 2769 struct 2770 { 2771 uint32_t SliceActCrQpOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< slice_act_cr_qp_offset 2772 uint32_t SliceActCbQpOffset : __CODEGEN_BITFIELD( 6, 11) ; //!< slice_act_cb_qp_offset 2773 uint32_t SliceActYQpOffset : __CODEGEN_BITFIELD(12, 17) ; //!< slice_act_y_qp_offset 2774 uint32_t Reserved402 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 2775 uint32_t UseIntegerMvFlag : __CODEGEN_BITFIELD(31, 31) ; //!< use_integer_mv_flag 2776 }; 2777 uint32_t Value; 2778 } DW12; 2779 2780 //! \name Local enumerations 2781 2782 enum MEDIA_INSTRUCTION_COMMAND 2783 { 2784 MEDIA_INSTRUCTION_COMMAND_HCPSLICESTATE = 20, //!< No additional details 2785 }; 2786 2787 //! \brief MEDIA_INSTRUCTION_OPCODE 2788 //! \details 2789 //! Codec/Engine Name = HCP = 7h 2790 enum MEDIA_INSTRUCTION_OPCODE 2791 { 2792 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2793 }; 2794 2795 enum PIPELINE_TYPE 2796 { 2797 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2798 }; 2799 2800 enum COMMAND_TYPE 2801 { 2802 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2803 }; 2804 2805 //! \brief SLICE_TYPE 2806 //! \details 2807 //! In VDENC mode, for HEVC standard this field can be 0 or 2 only. 2808 enum SLICE_TYPE 2809 { 2810 SLICE_TYPE_B_SLICE = 0, //!< No additional details 2811 SLICE_TYPE_P_SLICE = 1, //!< No additional details 2812 SLICE_TYPE_I_SLICE = 2, //!< No additional details 2813 SLICE_TYPE_ILLEGALRESERVED = 3, //!< No additional details 2814 }; 2815 2816 //! \brief LASTSLICEOFPIC 2817 //! \details 2818 //! This indicates the current slice is the very last slice of the current 2819 //! picture 2820 enum LASTSLICEOFPIC 2821 { 2822 LASTSLICEOFPIC_NOTTHELASTSLICEOFTHEPICTURE = 0, //!< No additional details 2823 LASTSLICEOFPIC_LASTSLICEOFTHEPICTURE = 1, //!< No additional details 2824 }; 2825 2826 //! \brief SLICE_CB_QP_OFFSET 2827 //! \details 2828 //! For deblocking purpose, the pic and slice level cb qp offset must be 2829 //! provided separately. 2830 enum SLICE_CB_QP_OFFSET 2831 { 2832 SLICE_CB_QP_OFFSET_0 = 0, //!< No additional details 2833 SLICE_CB_QP_OFFSET_1 = 1, //!< No additional details 2834 SLICE_CB_QP_OFFSET_2 = 2, //!< No additional details 2835 SLICE_CB_QP_OFFSET_3 = 3, //!< No additional details 2836 SLICE_CB_QP_OFFSET_4 = 4, //!< No additional details 2837 SLICE_CB_QP_OFFSET_5 = 5, //!< No additional details 2838 SLICE_CB_QP_OFFSET_6 = 6, //!< No additional details 2839 SLICE_CB_QP_OFFSET_7 = 7, //!< No additional details 2840 SLICE_CB_QP_OFFSET_8 = 8, //!< No additional details 2841 SLICE_CB_QP_OFFSET_9 = 9, //!< No additional details 2842 SLICE_CB_QP_OFFSET_10 = 10, //!< No additional details 2843 SLICE_CB_QP_OFFSET_11 = 11, //!< No additional details 2844 SLICE_CB_QP_OFFSET_12 = 12, //!< No additional details 2845 SLICE_CB_QP_OFFSET_NEG_12 = 20, //!< No additional details 2846 SLICE_CB_QP_OFFSET_NEG_11 = 21, //!< No additional details 2847 SLICE_CB_QP_OFFSET_NEG_10 = 22, //!< No additional details 2848 SLICE_CB_QP_OFFSET_NEG_9 = 23, //!< No additional details 2849 SLICE_CB_QP_OFFSET_NEG_8 = 24, //!< No additional details 2850 SLICE_CB_QP_OFFSET_NEG_7 = 25, //!< No additional details 2851 SLICE_CB_QP_OFFSET_NEG_6 = 26, //!< No additional details 2852 SLICE_CB_QP_OFFSET_NEG_5 = 27, //!< No additional details 2853 SLICE_CB_QP_OFFSET_NEG_4 = 28, //!< No additional details 2854 SLICE_CB_QP_OFFSET_NEG_3 = 29, //!< No additional details 2855 SLICE_CB_QP_OFFSET_NEG_2 = 30, //!< No additional details 2856 SLICE_CB_QP_OFFSET_NEG_1 = 31, //!< No additional details 2857 }; 2858 2859 //! \brief SLICE_CR_QP_OFFSET 2860 //! \details 2861 //! For deblocking purpose, the pic and slice level cr qp offset must be 2862 //! provided separately. 2863 enum SLICE_CR_QP_OFFSET 2864 { 2865 SLICE_CR_QP_OFFSET_0 = 0, //!< No additional details 2866 SLICE_CR_QP_OFFSET_1 = 1, //!< No additional details 2867 SLICE_CR_QP_OFFSET_2 = 2, //!< No additional details 2868 SLICE_CR_QP_OFFSET_3 = 3, //!< No additional details 2869 SLICE_CR_QP_OFFSET_4 = 4, //!< No additional details 2870 SLICE_CR_QP_OFFSET_5 = 5, //!< No additional details 2871 SLICE_CR_QP_OFFSET_6 = 6, //!< No additional details 2872 SLICE_CR_QP_OFFSET_7 = 7, //!< No additional details 2873 SLICE_CR_QP_OFFSET_8 = 8, //!< No additional details 2874 SLICE_CR_QP_OFFSET_9 = 9, //!< No additional details 2875 SLICE_CR_QP_OFFSET_10 = 10, //!< No additional details 2876 SLICE_CR_QP_OFFSET_11 = 11, //!< No additional details 2877 SLICE_CR_QP_OFFSET_12 = 12, //!< No additional details 2878 SLICE_CR_QP_OFFSET_NEG_12 = 20, //!< No additional details 2879 SLICE_CR_QP_OFFSET_NEG_11 = 21, //!< No additional details 2880 SLICE_CR_QP_OFFSET_NEG_10 = 22, //!< No additional details 2881 SLICE_CR_QP_OFFSET_NEG_9 = 23, //!< No additional details 2882 SLICE_CR_QP_OFFSET_NEG_8 = 24, //!< No additional details 2883 SLICE_CR_QP_OFFSET_NEG_7 = 25, //!< No additional details 2884 SLICE_CR_QP_OFFSET_NEG_6 = 26, //!< No additional details 2885 SLICE_CR_QP_OFFSET_NEG_5 = 27, //!< No additional details 2886 SLICE_CR_QP_OFFSET_NEG_4 = 28, //!< No additional details 2887 SLICE_CR_QP_OFFSET_NEG_3 = 29, //!< No additional details 2888 SLICE_CR_QP_OFFSET_NEG_2 = 30, //!< No additional details 2889 SLICE_CR_QP_OFFSET_NEG_1 = 31, //!< No additional details 2890 }; 2891 2892 //! \brief MAXMERGEIDX 2893 //! \details 2894 //! MaxNumMergeCand = 5 - five_minus_max_num_merge_cand -1. 2895 enum MAXMERGEIDX 2896 { 2897 MAXMERGEIDX_0 = 0, //!< No additional details 2898 MAXMERGEIDX_1 = 1, //!< No additional details 2899 MAXMERGEIDX_2 = 2, //!< No additional details 2900 MAXMERGEIDX_3 = 3, //!< No additional details 2901 MAXMERGEIDX_4 = 4, //!< No additional details 2902 }; 2903 2904 //! \brief ROUNDINTRA 2905 //! \details 2906 //! In VDENC mode, this field is ignored. 2907 enum ROUNDINTRA 2908 { 2909 ROUNDINTRA_132 = 0, //!< No additional details 2910 ROUNDINTRA_232 = 1, //!< No additional details 2911 ROUNDINTRA_332 = 2, //!< No additional details 2912 ROUNDINTRA_432 = 3, //!< No additional details 2913 ROUNDINTRA_532 = 4, //!< No additional details 2914 ROUNDINTRA_632 = 5, //!< No additional details 2915 ROUNDINTRA_732 = 6, //!< No additional details 2916 ROUNDINTRA_832 = 7, //!< No additional details 2917 ROUNDINTRA_932 = 8, //!< No additional details 2918 ROUNDINTRA_1032 = 9, //!< No additional details 2919 ROUNDINTRA_1132 = 10, //!< No additional details 2920 ROUNDINTRA_1232 = 11, //!< No additional details 2921 ROUNDINTRA_1332 = 12, //!< No additional details 2922 ROUNDINTRA_1432 = 13, //!< No additional details 2923 ROUNDINTRA_1532 = 14, //!< No additional details 2924 ROUNDINTRA_1632 = 15, //!< No additional details 2925 }; 2926 2927 //! \brief ROUNDINTER 2928 //! \details 2929 //! In VDENC mode, this field is ignored. 2930 enum ROUNDINTER 2931 { 2932 ROUNDINTER_132 = 0, //!< No additional details 2933 ROUNDINTER_232 = 1, //!< No additional details 2934 ROUNDINTER_332 = 2, //!< No additional details 2935 ROUNDINTER_432 = 3, //!< No additional details 2936 ROUNDINTER_532 = 4, //!< No additional details 2937 ROUNDINTER_632 = 5, //!< No additional details 2938 ROUNDINTER_732 = 6, //!< No additional details 2939 ROUNDINTER_832 = 7, //!< No additional details 2940 ROUNDINTER_932 = 8, //!< No additional details 2941 ROUNDINTER_1032 = 9, //!< No additional details 2942 ROUNDINTER_1132 = 10, //!< No additional details 2943 ROUNDINTER_1232 = 11, //!< No additional details 2944 ROUNDINTER_1332 = 12, //!< No additional details 2945 ROUNDINTER_1432 = 13, //!< No additional details 2946 ROUNDINTER_1532 = 14, //!< No additional details 2947 ROUNDINTER_1632 = 15, //!< No additional details 2948 }; 2949 2950 //! \brief CABACZEROWORDINSERTIONENABLE 2951 //! \details 2952 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2953 //! requirement. 2954 enum CABACZEROWORDINSERTIONENABLE 2955 { 2956 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion. 2957 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP (effectively can be usedas an indicator for last slice of a picture, if the assumption is only the last slice of a pictureneeds to insert CABAC_ZERO_WORDs). 2958 }; 2959 2960 //! \brief EMULATIONBYTESLICEINSERTENABLE 2961 //! \details 2962 //! To have PAK outputting SODB or EBSP to the output bitstream buffer. 2963 enum EMULATIONBYTESLICEINSERTENABLE 2964 { 2965 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGRBSP = 0, //!< No additional details 2966 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGEBSP = 1, //!< No additional details 2967 }; 2968 2969 //! \brief TAIL_INSERTION_ENABLE 2970 //! \details 2971 //! Must be followed by the PAK Insertion Object Command to perform the 2972 //! actual insertion. 2973 enum TAIL_INSERTION_ENABLE 2974 { 2975 TAIL_INSERTION_ENABLE_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits. 2976 TAIL_INSERTION_ENABLE_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits.SKL restriction: Tail insertion is only possible at the end of frame but not in the middle (say slice end) 2977 }; 2978 2979 //! \brief SLICEDATA_ENABLE 2980 //! \details 2981 //! <p>Must always be enabled.</p> 2982 //! <p>Encoder only feature.</p> 2983 enum SLICEDATA_ENABLE 2984 { 2985 SLICEDATA_ENABLE_UNNAMED0 = 0, //!< No operation; no insertion. 2986 SLICEDATA_ENABLE_UNNAMED1 = 1, //!< Slice Data insertion by PAK Object Commands into the output bitstream buffer. 2987 }; 2988 2989 //! \brief HEADER_INSERTION_ENABLE 2990 //! \details 2991 //! Must be followed by the PAK Insertion Object Command to perform the 2992 //! actual insertion. 2993 enum HEADER_INSERTION_ENABLE 2994 { 2995 HEADER_INSERTION_ENABLE_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, before the current slice encoded bits. 2996 HEADER_INSERTION_ENABLE_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is before the current slice encoded bits. 2997 }; 2998 2999 //! \name Initializations 3000 3001 //! \brief Explicit member initialization function HCP_SLICE_STATE_CMDHCP_SLICE_STATE_CMD3002 HCP_SLICE_STATE_CMD() 3003 { 3004 DW0.Value = 0x7394000b; 3005 //DW0.DwordLength = GetOpLength(dwSize); 3006 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPSLICESTATE; 3007 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3008 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3009 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3010 3011 DW1.Value = 0x00000000; 3012 3013 DW2.Value = 0x00000000; 3014 3015 DW3.Value = 0x00000000; 3016 //DW3.SliceType = SLICE_TYPE_B_SLICE; 3017 //DW3.Lastsliceofpic = LASTSLICEOFPIC_NOTTHELASTSLICEOFTHEPICTURE; 3018 //DW3.SliceCbQpOffset = SLICE_CB_QP_OFFSET_0; 3019 //DW3.SliceCrQpOffset = SLICE_CR_QP_OFFSET_0; 3020 3021 DW4.Value = 0x00000000; 3022 //DW4.Maxmergeidx = MAXMERGEIDX_0; 3023 3024 DW5.Value = 0x00000000; 3025 3026 DW6.Value = 0x10400000; 3027 //DW6.Roundintra = ROUNDINTRA_532; 3028 //DW6.Roundinter = ROUNDINTER_532; 3029 3030 DW7.Value = 0x00000000; 3031 //DW7.Cabaczerowordinsertionenable = CABACZEROWORDINSERTIONENABLE_UNNAMED0; 3032 //DW7.Emulationbytesliceinsertenable = EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGRBSP; 3033 //DW7.TailInsertionEnable = TAIL_INSERTION_ENABLE_UNNAMED0; 3034 //DW7.SlicedataEnable = SLICEDATA_ENABLE_UNNAMED0; 3035 //DW7.HeaderInsertionEnable = HEADER_INSERTION_ENABLE_UNNAMED0; 3036 3037 DW8.Value = 0x00000000; 3038 3039 DW9.Value = 0x00000000; 3040 3041 DW10.Value = 0x00000000; 3042 3043 DW11.Value = 0x00000000; 3044 3045 DW12.Value = 0x00000000; 3046 } 3047 3048 static const size_t dwSize = 13; 3049 static const size_t byteSize = 52; 3050 }; 3051 3052 //! 3053 //! \brief HCP_BSD_OBJECT 3054 //! \details 3055 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 3056 //! Commands. Each HCP command has assigned a media instruction command as 3057 //! defined in DWord 0, BitField 22:16. 3058 //! 3059 //! The HCP_BSD_OBJECT command fetches the HEVC bit stream for a slice 3060 //! starting with the first byte in the slice. The bit stream ends with the 3061 //! last non-zero bit of the frame and does not include any zero-padding at 3062 //! the end of the bit stream. There can be multiple slices in a HEVC frame 3063 //! and thus this command can be issued multiple times per frame. 3064 //! 3065 //! The HCP_BSD_OBJECT command must be the last command issued in the 3066 //! sequence of batch commands before the HCP starts decoding. Prior to 3067 //! issuing this command, it is assumed that all configuration parameters in 3068 //! the HCP have been loaded including workload configuration registers and 3069 //! configuration tables. When this command is issued, the HCP is waiting 3070 //! for bit stream data to be presented to the shift register. 3071 //! 3072 struct HCP_BSD_OBJECT_CMD 3073 { 3074 union 3075 { 3076 struct 3077 { 3078 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3079 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3080 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3081 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3082 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3083 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3084 }; 3085 uint32_t Value; 3086 } DW0; 3087 union 3088 { 3089 struct 3090 { 3091 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3092 }; 3093 uint32_t Value; 3094 } DW1; 3095 union 3096 { 3097 struct 3098 { 3099 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 3100 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3101 }; 3102 uint32_t Value; 3103 } DW2; 3104 3105 //! \name Local enumerations 3106 3107 enum MEDIA_INSTRUCTION_COMMAND 3108 { 3109 MEDIA_INSTRUCTION_COMMAND_HCPBSDOBJECTSTATE = 32, //!< No additional details 3110 }; 3111 3112 //! \brief MEDIA_INSTRUCTION_OPCODE 3113 //! \details 3114 //! Codec/Engine Name = HCP = 7h 3115 enum MEDIA_INSTRUCTION_OPCODE 3116 { 3117 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3118 }; 3119 3120 enum PIPELINE_TYPE 3121 { 3122 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3123 }; 3124 3125 enum COMMAND_TYPE 3126 { 3127 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3128 }; 3129 3130 //! \name Initializations 3131 3132 //! \brief Explicit member initialization function HCP_BSD_OBJECT_CMDHCP_BSD_OBJECT_CMD3133 HCP_BSD_OBJECT_CMD() 3134 { 3135 DW0.Value = 0x73a00001; 3136 //DW0.DwordLength = GetOpLength(dwSize); 3137 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPBSDOBJECTSTATE; 3138 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3139 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3140 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3141 3142 DW1.Value = 0x00000000; 3143 3144 DW2.Value = 0x00000000; 3145 } 3146 3147 static const size_t dwSize = 3; 3148 static const size_t byteSize = 12; 3149 }; 3150 3151 //! 3152 //! \brief HCP_VP9_SEGMENT_STATE 3153 //! \details 3154 //! 3155 //! 3156 struct HCP_VP9_SEGMENT_STATE_CMD 3157 { 3158 union 3159 { 3160 struct 3161 { 3162 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3163 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3164 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3165 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3166 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3167 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3168 }; 3169 uint32_t Value; 3170 } DW0; 3171 union 3172 { 3173 struct 3174 { 3175 uint32_t SegmentId : __CODEGEN_BITFIELD( 0, 2) ; //!< Segment ID 3176 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved 3177 }; 3178 uint32_t Value; 3179 } DW1; 3180 union 3181 { 3182 struct 3183 { 3184 uint32_t SegmentSkipped : __CODEGEN_BITFIELD( 0, 0) ; //!< Segment Skipped 3185 uint32_t SegmentReference : __CODEGEN_BITFIELD( 1, 2) ; //!< Segment Reference 3186 uint32_t SegmentReferenceEnabled : __CODEGEN_BITFIELD( 3, 3) ; //!< Segment Reference Enabled 3187 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 3188 }; 3189 uint32_t Value; 3190 } DW2; 3191 union 3192 { 3193 struct 3194 { 3195 uint32_t Filterlevelref0Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef0Mode0 3196 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 3197 uint32_t Filterlevelref0Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef0Mode1 3198 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3199 uint32_t Filterlevelref1Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef1Mode0 3200 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3201 uint32_t Filterlevelref1Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef1Mode1 3202 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3203 }; 3204 uint32_t Value; 3205 } DW3; 3206 union 3207 { 3208 struct 3209 { 3210 uint32_t Filterlevelref2Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef2Mode0 3211 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 3212 uint32_t Filterlevelref2Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef2Mode1 3213 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3214 uint32_t Filterlevelref3Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef3Mode0 3215 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3216 uint32_t Filterlevelref3Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef3Mode1 3217 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3218 }; 3219 uint32_t Value; 3220 } DW4; 3221 union 3222 { 3223 struct 3224 { 3225 uint32_t LumaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Luma DC Quant Scale (Decode mode Only) 3226 uint32_t LumaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Luma AC Quant Scale (Decode mode Only) 3227 }; 3228 uint32_t Value; 3229 } DW5; 3230 union 3231 { 3232 struct 3233 { 3234 uint32_t ChromaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Chroma DC Quant Scale (Decode mode Only) 3235 uint32_t ChromaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Chroma AC Quant Scale (Decode mode Only) 3236 }; 3237 uint32_t Value; 3238 } DW6; 3239 union 3240 { 3241 struct 3242 { 3243 uint32_t SegmentQindexDeltaEncodeModeOnly : __CODEGEN_BITFIELD( 0, 8) ; //!< Segment QIndex Delta (encode mode only) 3244 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 3245 uint32_t SegmentLfLevelDeltaEncodeModeOnly : __CODEGEN_BITFIELD(16, 22) ; //!< Segment LF Level Delta (Encode mode Only) 3246 uint32_t Reserved247 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 3247 }; 3248 uint32_t Value; 3249 } DW7; 3250 3251 //! \name Local enumerations 3252 3253 enum MEDIA_INSTRUCTION_COMMAND 3254 { 3255 MEDIA_INSTRUCTION_COMMAND_HCPVP9SEGMENTSTATE = 50, //!< No additional details 3256 }; 3257 3258 //! \brief MEDIA_INSTRUCTION_OPCODE 3259 //! \details 3260 //! Codec/Engine Name = HUC = Bh 3261 enum MEDIA_INSTRUCTION_OPCODE 3262 { 3263 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3264 }; 3265 3266 enum PIPELINE_TYPE 3267 { 3268 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3269 }; 3270 3271 enum COMMAND_TYPE 3272 { 3273 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3274 }; 3275 3276 //! \name Initializations 3277 3278 //! \brief Explicit member initialization function HCP_VP9_SEGMENT_STATE_CMDHCP_VP9_SEGMENT_STATE_CMD3279 HCP_VP9_SEGMENT_STATE_CMD() 3280 { 3281 DW0.Value = 0x73b20006; 3282 //DW0.DwordLength = GetOpLength(dwSize); 3283 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPVP9SEGMENTSTATE; 3284 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3285 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3286 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3287 3288 DW1.Value = 0x00000000; 3289 3290 DW2.Value = 0x00000000; 3291 3292 DW3.Value = 0x00000000; 3293 3294 DW4.Value = 0x00000000; 3295 3296 DW5.Value = 0x00000000; 3297 3298 DW6.Value = 0x00000000; 3299 3300 DW7.Value = 0x00000000; 3301 } 3302 3303 static const size_t dwSize = 8; 3304 static const size_t byteSize = 32; 3305 }; 3306 3307 //! 3308 //! \brief HCP_FQM_STATE 3309 //! \details 3310 //! The HCP_FQM_STATE command loads the custom HEVC quantization tables into 3311 //! local RAM and may be issued up to 8 times: 4 scaling list per intra and 3312 //! inter. 3313 //! 3314 //! Driver is responsible for performing the Scaling List division. So, save 3315 //! the division HW cost in HW. The 1/x value is provided in 16-bit 3316 //! fixed-point precision as ((1<<17)/QM +1) >> 1. . 3317 //! 3318 //! Note: FQM is computed as (2^16)/QM. If QM=1, FQM=all 1's. 3319 //! 3320 //! To simplify the design, only a limited number of scaling lists are 3321 //! provided at the PAK interface: default two SizeID0 and two SizeID123 3322 //! (one set for inter and the other set for intra), and the encoder only 3323 //! allows custom entries for these four matrices. The DC value of SizeID2 3324 //! and SizeID3 will be provided. 3325 //! 3326 //! When the scaling_list_enable_flag is set to disable, the scaling matrix 3327 //! is still sent to the PAK, and with all entries programmed to the same 3328 //! value of 16. 3329 //! 3330 //! This is a picture level state command and is issued in encoding 3331 //! processes only. 3332 //! 3333 //! Dwords 2-33 form a table for the DCT coefficients, 2 16-bit 3334 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-9. 3335 //! Size 8x8 for SizeID1/2/3, DWords 2-33. 3336 //! 3337 //! 3338 //! SizeID 0 (Table 4-13) 3339 //! 3340 struct HCP_FQM_STATE_CMD 3341 { 3342 union 3343 { 3344 struct 3345 { 3346 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3347 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3348 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3349 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3350 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3351 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3352 }; 3353 uint32_t Value; 3354 } DW0; 3355 union 3356 { 3357 struct 3358 { 3359 uint32_t IntraInter : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAINTER 3360 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 3361 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 3362 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 3363 uint32_t FqmDcValue1Dc : __CODEGEN_BITFIELD(16, 31) ; //!< FQM DC Value: (1/DC): 3364 }; 3365 uint32_t Value; 3366 } DW1; 3367 uint32_t Quantizermatrix[32]; //!< QuantizerMatrix 3368 3369 //! \name Local enumerations 3370 3371 enum MEDIA_INSTRUCTION_COMMAND 3372 { 3373 MEDIA_INSTRUCTION_COMMAND_HCPFQMSTATE = 5, //!< No additional details 3374 }; 3375 3376 //! \brief MEDIA_INSTRUCTION_OPCODE 3377 //! \details 3378 //! Codec/Engine Name = HCP = 7h 3379 enum MEDIA_INSTRUCTION_OPCODE 3380 { 3381 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3382 }; 3383 3384 enum PIPELINE_TYPE 3385 { 3386 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3387 }; 3388 3389 enum COMMAND_TYPE 3390 { 3391 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3392 }; 3393 3394 //! \brief INTRAINTER 3395 //! \details 3396 //! This field specifies the quant matrix intra or inter type. 3397 enum INTRAINTER 3398 { 3399 INTRAINTER_INTRA = 0, //!< No additional details 3400 INTRAINTER_INTER = 1, //!< No additional details 3401 }; 3402 3403 enum SIZEID 3404 { 3405 SIZEID_SIZEID04X4 = 0, //!< No additional details 3406 SIZEID_SIZEID1_2_3_8X8_16X16_32X32 = 1, //!< No additional details 3407 SIZEID_SIZEID2_FORDCVALUEIN16X16 = 2, //!< No additional details 3408 SIZEID_SIZEID3_FORDCVALUEIN32X32 = 3, //!< No additional details 3409 }; 3410 3411 //! \brief COLOR_COMPONENT 3412 //! \details 3413 //! <p>Luma and Chroma's share the same scaling list and DC value for the 3414 //! same SizeID.</p> 3415 enum COLOR_COMPONENT 3416 { 3417 COLOR_COMPONENT_LUMA = 0, //!< No additional details 3418 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 3419 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 3420 }; 3421 3422 //! \name Initializations 3423 3424 //! \brief Explicit member initialization function HCP_FQM_STATE_CMDHCP_FQM_STATE_CMD3425 HCP_FQM_STATE_CMD() 3426 { 3427 DW0.Value = 0x73850020; 3428 //DW0.DwordLength = GetOpLength(dwSize); 3429 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPFQMSTATE; 3430 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3431 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3432 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3433 3434 DW1.Value = 0x00000000; 3435 //DW1.IntraInter = INTRAINTER_INTRA; 3436 //DW1.Sizeid = SIZEID_SIZEID04X4; 3437 //DW1.ColorComponent = COLOR_COMPONENT_LUMA; 3438 3439 memset(&Quantizermatrix, 0, sizeof(Quantizermatrix)); 3440 } 3441 3442 static const size_t dwSize = 34; 3443 static const size_t byteSize = 136; 3444 }; 3445 3446 //! 3447 //! \brief HCP_PAK_INSERT_OBJECT 3448 //! \details 3449 //! It is an encoder only command, operating at bitstream level, before and 3450 //! after SliceData compressed bitstream. It is setup by the header and tail 3451 //! present flags in the Slice State command. If these flags are set and no 3452 //! subsequent PAK_INSERT_OBJECT commands are issued, the pipeline will 3453 //! hang. 3454 //! 3455 //! The HCP_ PAK_ INSERT _OBJECT command supports both inline and indirect 3456 //! data payload, but only one can be active at any time. It is issued to 3457 //! insert a chunk of bits (payload) into the current compressed bitstream 3458 //! output buffer (specified in the HCP_PAK-BSE Object Base Address field of 3459 //! the HCP_IND_OBJ_BASE_ADDR_STATE command) starting at its current write 3460 //! pointer bit position. Hardware will keep track of this write pointer's 3461 //! byte position and the associated next bit insertion position index. 3462 //! 3463 //! It is a variable length command when the payload (data to be inserted) 3464 //! is presented as inline data within the command itself. The inline 3465 //! payload is a multiple of 32-bit (1 DW), as the data bus to the 3466 //! compressed bitstream output buffer is 32-bit wide. 3467 //! 3468 //! The payload data is required to be byte aligned on the left (first 3469 //! transmitted bit order) and may or may not be byte aligned on the right 3470 //! (last transmitted bits). The command will specify the bit offset of the 3471 //! last valid DW. Note that : Stitch Command is used if the beginning 3472 //! position of data is in bit position. When PAK Insert Command is used the 3473 //! beginning position must be in byte position. 3474 //! 3475 //! Multiple insertion commands can be issued back to back in a series. It 3476 //! is host software's responsibility to make sure their corresponding data 3477 //! will properly stitch together to form a valid bitstream. 3478 //! 3479 //! Internally, HCP hardware will keep track of the very last two bytes' 3480 //! (the very last byte can be a partial byte) values of the previous 3481 //! insertion. It is required that the next Insertion Object Command or the 3482 //! next PAK Object Command to perform the start code emulation sequence 3483 //! check and prevention 0x03 byte insertion with this end condition of the 3484 //! previous insertion. 3485 //! 3486 //! The payload data may have already been processed for start code 3487 //! emulation byte insertion, except the possibility of the last 2 bytes 3488 //! plus the very last partial byte (if any). Hence, when hardware 3489 //! performing the concatenation of multiple consecutive insertion commands, 3490 //! or concatenation of an insertion command and a PAK object command, it 3491 //! must check and perform the necessary start code emulation byte insert at 3492 //! the junction. 3493 //! 3494 //! Data to be inserted can be a valid NAL units or a partial NAL unit. It 3495 //! can be any encoded syntax elements bit data before the encoded Slice 3496 //! Data (PAK Object Command) of the current Slice - SPS NAL, PPS NAL, SEI 3497 //! NAL and Other Non-Slice NAL, Leading_Zero_8_bits (as many bytes as there 3498 //! is), Start Code , Slice Header. Any encoded syntax elements bit data 3499 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3500 //! and prior to the next encoded Slice Data of the next Slice or prior to 3501 //! the end of the bitstream, whichever comes first Cabac_Zero_Word or 3502 //! Trailing_Zero_8bits (as many bytes as there is). 3503 //! 3504 //! Certain NAL unit has a minimum byte size requirement. As such the 3505 //! hardware will optionally (enabled by SLICE STATE Command) determines the 3506 //! number of CABAC_ZERO_WORD to be inserted to the end of the current NAL, 3507 //! based on the minimum byte size of a NAL and the actual bin count of the 3508 //! encoded Slice. Since prior to the CABAC_ZERO_WORD insertion, the RBSP or 3509 //! EBSP is already byte-aligned, so each CABAC_ZERO_WORD insertion is 3510 //! actually a 3-byte sequence 0x00 00 03. 3511 //! 3512 //! Context switch interrupt is not supported by this command. 3513 //! 3514 struct HCP_PAK_INSERT_OBJECT_CMD 3515 { 3516 union 3517 { 3518 struct 3519 { 3520 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Dword Length 3521 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3522 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3523 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3524 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3525 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3526 }; 3527 uint32_t Value; 3528 } DW0; 3529 union 3530 { 3531 struct 3532 { 3533 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3534 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3535 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3536 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3537 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 3538 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3539 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< Slice Header Indicator 3540 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3541 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3542 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 3543 uint32_t IndirectPayloadEnable : __CODEGEN_BITFIELD(31, 31) ; //!< INDIRECT_PAYLOAD_ENABLE 3544 }; 3545 uint32_t Value; 3546 } DW1; 3547 3548 //! \name Local enumerations 3549 3550 enum MEDIA_INSTRUCTION_COMMAND 3551 { 3552 MEDIA_INSTRUCTION_COMMAND_HCPPAKINSERTOBJECT = 34, //!< No additional details 3553 }; 3554 3555 //! \brief MEDIA_INSTRUCTION_OPCODE 3556 //! \details 3557 //! Codec/Engine Name = HCP = 7h 3558 enum MEDIA_INSTRUCTION_OPCODE 3559 { 3560 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3561 }; 3562 3563 enum PIPELINE_TYPE 3564 { 3565 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3566 }; 3567 3568 enum COMMAND_TYPE 3569 { 3570 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3571 }; 3572 3573 //! \brief EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3574 //! \details 3575 //! Only valid for HEVC and reserved for VP9. 3576 enum EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3577 { 3578 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_STARTCODEPREFIX = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between. 3579 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_INSERTIONCOMMAND = 2, //!< Insertion commands, or an insertion command followed by a PAK Object command. 3580 }; 3581 3582 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 3583 //! \details 3584 //! <p>In case this flag is on, bits are NOT accumulated during current 3585 //! access unit coding neither for Cabac Zero Word insertion bits counting 3586 //! or for output in MMIO register 3587 //! HCP_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER.</p> 3588 //! <p>When using HeaderLenghtExcludeFrmSize for header insertion, the 3589 //! software needs to make sure that data comes already with inserted start 3590 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 3591 //! DWORD1 of HCP_PAK_INSERT_OBJECT).</p> 3592 //! <table border="1" cellpadding="0" cellspacing="0" style="width: 100%;" 3593 //! width="100%"> 3594 //! <tbody> 3595 //! <tr> 3596 //! <td> 3597 //! <p align="center"><b>Value</b></p></td> 3598 //! <td> 3599 //! <p align="center"><b style="text-align: 3600 //! -webkit-center;">Description</b></p></td> 3601 //! </tr> 3602 //! <tr> 3603 //! <td> 3604 //! <p>0</p></td> 3605 //! <td> 3606 //! <p>All bits accumulated</p></td> 3607 //! </tr> 3608 //! <tr> 3609 //! <td> 3610 //! <p>1</p></td> 3611 //! <td> 3612 //! <p>Bits during current call are not accumulated</p></td> 3613 //! </tr> 3614 //! </tbody> 3615 //! </table> 3616 //! 3617 //! <p></p> 3618 enum HEADERLENGTHEXCLUDEFRMSIZE_ 3619 { 3620 HEADERLENGTHEXCLUDEFRMSIZE_ALLBITSACCUMULATED = 0, //!< No additional details 3621 HEADERLENGTHEXCLUDEFRMSIZE_BITSDURINGCURRENTCALLARENOTACCUMULATED = 1, //!< No additional details 3622 }; 3623 3624 //! \brief INDIRECT_PAYLOAD_ENABLE 3625 //! \details 3626 //! <p>Only one of these two payload modes can be active at any time.</p> 3627 //! <p>When Slice Size Conformance is enable the Payload(header) must be 3628 //! inline only so this bit set to MBZ.</p> 3629 enum INDIRECT_PAYLOAD_ENABLE 3630 { 3631 INDIRECT_PAYLOAD_ENABLE_INLINEPAYLOADISUSED = 0, //!< No additional details 3632 INDIRECT_PAYLOAD_ENABLE_INDIRECTPAYLOADISUSED = 1, //!< No additional details 3633 }; 3634 3635 //! \name Initializations 3636 3637 //! \brief Explicit member initialization function HCP_PAK_INSERT_OBJECT_CMDHCP_PAK_INSERT_OBJECT_CMD3638 HCP_PAK_INSERT_OBJECT_CMD() 3639 { 3640 DW0.Value = 0x73a20000; 3641 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPAKINSERTOBJECT; 3642 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 3643 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 3644 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 3645 3646 DW1.Value = 0x00000000; 3647 //DW1.EmulationflagEmulationbytebitsinsertenable = 0; 3648 //DW1.Headerlengthexcludefrmsize = HEADERLENGTHEXCLUDEFRMSIZE_ALLBITSACCUMULATED; 3649 //DW1.IndirectPayloadEnable = INDIRECT_PAYLOAD_ENABLE_INLINEPAYLOADISUSED; 3650 } 3651 3652 static const size_t dwSize = 2; 3653 static const size_t byteSize = 8; 3654 }; 3655 3656 //! 3657 //! \brief HCP_VP9_PIC_STATE 3658 //! \details 3659 //! 3660 //! 3661 struct HCP_VP9_PIC_STATE_CMD 3662 { 3663 union 3664 { 3665 struct 3666 { 3667 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3668 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3669 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3670 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3671 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3672 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3673 }; 3674 uint32_t Value; 3675 } DW0; 3676 union 3677 { 3678 struct 3679 { 3680 uint32_t FrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Width In Pixels Minus 1 3681 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3682 uint32_t FrameHeightInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Height In Pixels Minus 1 3683 uint32_t Reserved62 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3684 }; 3685 uint32_t Value; 3686 } DW1; 3687 union 3688 { 3689 struct 3690 { 3691 uint32_t FrameType : __CODEGEN_BITFIELD( 0, 0) ; //!< FRAME_TYPE 3692 uint32_t AdaptProbabilitiesFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPT_PROBABILITIES_FLAG 3693 uint32_t IntraonlyFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< IntraOnly Flag 3694 uint32_t AllowHiPrecisionMv : __CODEGEN_BITFIELD( 3, 3) ; //!< ALLOW_HI_PRECISION_MV 3695 uint32_t McompFilterType : __CODEGEN_BITFIELD( 4, 6) ; //!< MCOMP_FILTER_TYPE 3696 uint32_t RefFrameSignBias02 : __CODEGEN_BITFIELD( 7, 9) ; //!< Ref Frame Sign Bias[0..2] 3697 uint32_t UsePrevInFindMvReferences : __CODEGEN_BITFIELD(10, 10) ; //!< Use Prev in Find MV References 3698 uint32_t HybridPredictionMode : __CODEGEN_BITFIELD(11, 11) ; //!< HYBRID_PREDICTION_MODE 3699 uint32_t SelectableTxMode : __CODEGEN_BITFIELD(12, 12) ; //!< SELECTABLE_TX_MODE 3700 uint32_t LastFrameType : __CODEGEN_BITFIELD(13, 13) ; //!< LAST_FRAME_TYPE 3701 uint32_t RefreshFrameContext : __CODEGEN_BITFIELD(14, 14) ; //!< REFRESH_FRAME_CONTEXT 3702 uint32_t ErrorResilientMode : __CODEGEN_BITFIELD(15, 15) ; //!< ERROR_RESILIENT_MODE 3703 uint32_t FrameParallelDecodingMode : __CODEGEN_BITFIELD(16, 16) ; //!< FRAME_PARALLEL_DECODING_MODE 3704 uint32_t FilterLevel : __CODEGEN_BITFIELD(17, 22) ; //!< Filter Level 3705 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(23, 25) ; //!< Sharpness Level 3706 uint32_t SegmentationEnabled : __CODEGEN_BITFIELD(26, 26) ; //!< SEGMENTATION_ENABLED 3707 uint32_t SegmentationUpdateMap : __CODEGEN_BITFIELD(27, 27) ; //!< SEGMENTATION_UPDATE_MAP 3708 uint32_t SegmentationTemporalUpdate : __CODEGEN_BITFIELD(28, 28) ; //!< SEGMENTATION_TEMPORAL_UPDATE 3709 uint32_t LosslessMode : __CODEGEN_BITFIELD(29, 29) ; //!< LOSSLESS_MODE 3710 uint32_t SegmentIdStreamoutEnable : __CODEGEN_BITFIELD(30, 30) ; //!< SEGMENT_ID_STREAMOUT_ENABLE 3711 uint32_t SegmentIdStreaminEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SEGMENT_ID_STREAMIN_ENABLE 3712 }; 3713 uint32_t Value; 3714 } DW2; 3715 union 3716 { 3717 struct 3718 { 3719 uint32_t Log2TileColumn : __CODEGEN_BITFIELD( 0, 3) ; //!< LOG2_TILE_COLUMN 3720 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 3721 uint32_t Log2TileRow : __CODEGEN_BITFIELD( 8, 9) ; //!< LOG2_TILE_ROW 3722 uint32_t Reserved106 : __CODEGEN_BITFIELD(10, 20) ; //!< Reserved 3723 uint32_t SseEnable : __CODEGEN_BITFIELD(21, 21) ; //!< SSE Enable 3724 uint32_t ChromaSamplingFormat : __CODEGEN_BITFIELD(22, 23) ; //!< CHROMA_SAMPLING_FORMAT 3725 uint32_t Bitdepthminus8 : __CODEGEN_BITFIELD(24, 27) ; //!< BITDEPTHMINUS8 3726 uint32_t ProfileLevel : __CODEGEN_BITFIELD(28, 31) ; //!< PROFILE_LEVEL 3727 }; 3728 uint32_t Value; 3729 } DW3; 3730 union 3731 { 3732 struct 3733 { 3734 uint32_t VerticalScaleFactorForLast : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for LAST 3735 uint32_t HorizontalScaleFactorForLast : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for LAST 3736 }; 3737 uint32_t Value; 3738 } DW4; 3739 union 3740 { 3741 struct 3742 { 3743 uint32_t VerticalScaleFactorForGolden : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for GOLDEN 3744 uint32_t HorizontalScaleFactorForGolden : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for GOLDEN 3745 }; 3746 uint32_t Value; 3747 } DW5; 3748 union 3749 { 3750 struct 3751 { 3752 uint32_t VerticalScaleFactorForAltref : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for ALTREF 3753 uint32_t HorizontalScaleFactorForAltref : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for ALTREF 3754 }; 3755 uint32_t Value; 3756 } DW6; 3757 union 3758 { 3759 struct 3760 { 3761 uint32_t LastFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Last Frame Width In Pixels Minus 1 3762 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3763 uint32_t LastFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Last Frame Hieght In Pixels Minus 1 3764 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3765 }; 3766 uint32_t Value; 3767 } DW7; 3768 union 3769 { 3770 struct 3771 { 3772 uint32_t GoldenFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Golden Frame Width In Pixels Minus 1 3773 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3774 uint32_t GoldenFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Golden Frame Hieght In Pixels Minus 1 3775 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3776 }; 3777 uint32_t Value; 3778 } DW8; 3779 union 3780 { 3781 struct 3782 { 3783 uint32_t AltrefFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Altref Frame Width In Pixels Minus 1 3784 uint32_t Reserved302 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3785 uint32_t AltrefFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Altref Frame Hieght In Pixels Minus 1 3786 uint32_t Reserved318 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3787 }; 3788 uint32_t Value; 3789 } DW9; 3790 union 3791 { 3792 struct 3793 { 3794 uint32_t UncompressedHeaderLengthInBytes70 : __CODEGEN_BITFIELD( 0, 7) ; //!< Uncompressed Header Length in Bytes [7:0] 3795 uint32_t Reserved328 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3796 uint32_t FirstPartitionSizeInBytes150 : __CODEGEN_BITFIELD(16, 31) ; //!< First Partition Size in Bytes [15:0] 3797 }; 3798 uint32_t Value; 3799 } DW10; 3800 union 3801 { 3802 struct 3803 { 3804 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3805 uint32_t MotionCompScalingEnableBit : __CODEGEN_BITFIELD( 1, 1) ; //!< MOTION_COMP_SCALING_ENABLE_BIT 3806 uint32_t Reserved354 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 3807 }; 3808 uint32_t Value; 3809 } DW11; 3810 union 3811 { 3812 struct 3813 { 3814 uint32_t Reserved384 ; //!< Reserved 3815 }; 3816 uint32_t Value; 3817 } DW12; 3818 union 3819 { 3820 struct 3821 { 3822 uint32_t CompressedHeaderBinCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Compressed header BIN count 3823 uint32_t BaseQIndexSameAsLumaAc : __CODEGEN_BITFIELD(16, 23) ; //!< Base Q Index (Same as Luma AC) 3824 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< Tail Insertion Enable 3825 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(25, 25) ; //!< Header Insertion Enable 3826 uint32_t VDAQMEnable : __CODEGEN_BITFIELD(26, 26) ; //!< VDAQM Enable 3827 uint32_t Reserved443 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3828 }; 3829 uint32_t Value; 3830 } DW13; 3831 union 3832 { 3833 struct 3834 { 3835 uint32_t ChromaacQindexdelta : __CODEGEN_BITFIELD( 0, 4) ; //!< ChromaAC_QindexDelta 3836 uint32_t Reserved453 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved 3837 uint32_t ChromadcQindexdelta : __CODEGEN_BITFIELD( 8, 12) ; //!< ChromaDC_QindexDelta 3838 uint32_t Reserved461 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 3839 uint32_t LumaDcQIndexDelta : __CODEGEN_BITFIELD(16, 20) ; //!< Luma DC Q Index Delta 3840 uint32_t Reserved469 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 3841 }; 3842 uint32_t Value; 3843 } DW14; 3844 union 3845 { 3846 struct 3847 { 3848 uint32_t LfRefDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF_ref_delta0 3849 uint32_t Reserved487 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3850 uint32_t LfRefDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF_ref_delta1 3851 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3852 uint32_t LfRefDelta2 : __CODEGEN_BITFIELD(16, 22) ; //!< LF_ref_delta2 3853 uint32_t Reserved503 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 3854 uint32_t LfRefDelta3 : __CODEGEN_BITFIELD(24, 30) ; //!< LF_ref_delta3 3855 uint32_t Reserved511 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3856 }; 3857 uint32_t Value; 3858 } DW15; 3859 union 3860 { 3861 struct 3862 { 3863 uint32_t LfModeDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF Mode Delta 0 3864 uint32_t Reserved519 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3865 uint32_t LfModeDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF Mode Delta 1 3866 uint32_t Reserved527 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 3867 }; 3868 uint32_t Value; 3869 } DW16; 3870 union 3871 { 3872 struct 3873 { 3874 uint32_t Bitoffsetforlfrefdelta : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForLFRefDelta 3875 uint32_t Bitoffsetforlfmodedelta : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFModeDelta 3876 }; 3877 uint32_t Value; 3878 } DW17; 3879 union 3880 { 3881 struct 3882 { 3883 uint32_t Bitoffsetforqindex : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForQindex 3884 uint32_t Bitoffsetforlflevel : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFLevel 3885 }; 3886 uint32_t Value; 3887 } DW18; 3888 union 3889 { 3890 struct 3891 { 3892 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 3893 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 3894 uint32_t VdencPakOnlyPass : __CODEGEN_BITFIELD(17, 17) ; //!< VDENC PAK_ONLY PASS 3895 uint32_t Reserved626 : __CODEGEN_BITFIELD(18, 24) ; //!< Reserved 3896 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3897 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3898 uint32_t Reserved635 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3899 }; 3900 uint32_t Value; 3901 } DW19; 3902 union 3903 { 3904 struct 3905 { 3906 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 3907 uint32_t Reserved654 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3908 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 3909 }; 3910 uint32_t Value; 3911 } DW20; 3912 union 3913 { 3914 struct 3915 { 3916 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 3917 uint32_t Reserved686 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3918 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 3919 }; 3920 uint32_t Value; 3921 } DW21; 3922 union 3923 { 3924 struct 3925 { 3926 uint64_t Framedeltaqindexmax ; //!< FrameDeltaQindexMax 3927 }; 3928 uint32_t Value[2]; 3929 } DW22_23; 3930 union 3931 { 3932 struct 3933 { 3934 uint32_t Framedeltaqindexmin ; //!< FrameDeltaQindexMin 3935 }; 3936 uint32_t Value; 3937 } DW24; 3938 union 3939 { 3940 struct 3941 { 3942 uint64_t Framedeltalfmax ; //!< FrameDeltaLFMax 3943 }; 3944 uint32_t Value[2]; 3945 } DW25_26; 3946 union 3947 { 3948 struct 3949 { 3950 uint32_t Framedeltalfmin ; //!< FrameDeltaLFMin 3951 }; 3952 uint32_t Value; 3953 } DW27; 3954 union 3955 { 3956 struct 3957 { 3958 uint64_t Framedeltaqindexlfmaxrange ; //!< FrameDeltaQindexLFMaxRange 3959 }; 3960 uint32_t Value[2]; 3961 } DW28_29; 3962 union 3963 { 3964 struct 3965 { 3966 uint32_t Framedeltaqindexlfminrange ; //!< FrameDeltaQindexLFMinRange 3967 }; 3968 uint32_t Value; 3969 } DW30; 3970 union 3971 { 3972 struct 3973 { 3974 uint32_t Minframsize : __CODEGEN_BITFIELD( 0, 15) ; //!< MinFramSize 3975 uint32_t Reserved1008 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 3976 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 3977 }; 3978 uint32_t Value; 3979 } DW31; 3980 union 3981 { 3982 struct 3983 { 3984 uint32_t Bitoffsetforfirstpartitionsize : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForFirstPartitionSize 3985 uint32_t Reserved1040 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 3986 }; 3987 uint32_t Value; 3988 } DW32; 3989 union 3990 { 3991 struct 3992 { 3993 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 3994 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 3995 }; 3996 uint32_t Value; 3997 } DW33; 3998 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 3999 4000 //! \name Local enumerations 4001 4002 enum MEDIA_INSTRUCTION_COMMAND 4003 { 4004 MEDIA_INSTRUCTION_COMMAND_HCPVP9PICSTATE = 48, //!< No additional details 4005 }; 4006 4007 //! \brief MEDIA_INSTRUCTION_OPCODE 4008 //! \details 4009 //! Codec/Engine Name = HUC = Bh 4010 enum MEDIA_INSTRUCTION_OPCODE 4011 { 4012 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4013 }; 4014 4015 enum PIPELINE_TYPE 4016 { 4017 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4018 }; 4019 4020 enum COMMAND_TYPE 4021 { 4022 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4023 }; 4024 4025 //! \brief FRAME_TYPE 4026 //! \details 4027 //! Specifies the VP9 frame type 4028 enum FRAME_TYPE 4029 { 4030 FRAME_TYPE_KEYFRAME = 0, //!< No additional details 4031 FRAME_TYPE_INTERFRAME = 1, //!< No additional details 4032 }; 4033 4034 //! \brief ADAPT_PROBABILITIES_FLAG 4035 //! \details 4036 //! Indicates that the probabilities used to decode this frame should be 4037 //! adapted 4038 enum ADAPT_PROBABILITIES_FLAG 4039 { 4040 ADAPT_PROBABILITIES_FLAG_0DONOTADAPT_ERRORRESILIENTORFRAMEPARALLELMODEARESET = 0, //!< No additional details 4041 ADAPT_PROBABILITIES_FLAG_1ADAPT_NOTERRORRESILIENTANDNOTFRAMEPARALLELMODE = 1, //!< No additional details 4042 }; 4043 4044 //! \brief ALLOW_HI_PRECISION_MV 4045 //! \details 4046 //! Indicate high precision mode for Motion Vector prediction 4047 enum ALLOW_HI_PRECISION_MV 4048 { 4049 ALLOW_HI_PRECISION_MV_NORMALMODE = 0, //!< No additional details 4050 ALLOW_HI_PRECISION_MV_HIGHPRECISIONMODE = 1, //!< No additional details 4051 }; 4052 4053 //! \brief MCOMP_FILTER_TYPE 4054 //! \details 4055 //! Indicate Motion Compensation Filter type. 4056 enum MCOMP_FILTER_TYPE 4057 { 4058 MCOMP_FILTER_TYPE_EIGHT_TAP = 0, //!< No additional details 4059 MCOMP_FILTER_TYPE_EIGHT_TAP_SMOOTH = 1, //!< No additional details 4060 MCOMP_FILTER_TYPE_EIGHT_TAP_SHARP = 2, //!< No additional details 4061 MCOMP_FILTER_TYPE_BILINEAR = 3, //!< No additional details 4062 MCOMP_FILTER_TYPE_SWITCHABLE = 4, //!< No additional details 4063 }; 4064 4065 //! \brief HYBRID_PREDICTION_MODE 4066 //! \details 4067 //! Indicates if comp_pred_mode is hybrid 4068 enum HYBRID_PREDICTION_MODE 4069 { 4070 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERDOESNOTPACKCOMPPREDMODEINTERPREDCOMPINPAKOBJINTOBITSTREAM = 0, //!< No additional details 4071 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERPACKSCOMPPREDMODEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 1, //!< No additional details 4072 }; 4073 4074 //! \brief SELECTABLE_TX_MODE 4075 //! \details 4076 //! Indicates if tx_mode is selectable 4077 enum SELECTABLE_TX_MODE 4078 { 4079 SELECTABLE_TX_MODE_ENCODERDOESNOTPACKTUSIZEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 0, //!< No additional details 4080 SELECTABLE_TX_MODE_ENCODERPACKSTUSIZEINTOBITSTREAM = 1, //!< No additional details 4081 }; 4082 4083 //! \brief LAST_FRAME_TYPE 4084 //! \details 4085 //! <p>It indicates the frame type of previous frame (Key or Non-Key 4086 //! Frame)</p> 4087 enum LAST_FRAME_TYPE 4088 { 4089 LAST_FRAME_TYPE_KEYFRAME = 0, //!< No additional details 4090 LAST_FRAME_TYPE_NONKEYFRAME = 1, //!< No additional details 4091 }; 4092 4093 //! \brief REFRESH_FRAME_CONTEXT 4094 //! \details 4095 //! <p>Indicates if Frame Context should be refresh. This bit should come 4096 //! from Uncompressed header</p> 4097 enum REFRESH_FRAME_CONTEXT 4098 { 4099 REFRESH_FRAME_CONTEXT_DISABLE = 0, //!< No additional details 4100 REFRESH_FRAME_CONTEXT_ENABLE = 1, //!< No additional details 4101 }; 4102 4103 //! \brief ERROR_RESILIENT_MODE 4104 //! \details 4105 //! <p>Indicates if error resilient mode is enabled. This bit should come 4106 //! from Uncompressed header.When error resilient is 1, Frame Parallel 4107 //! Decoding Mode will be 1, and Refresh Frame Context will be 0.When error 4108 //! resilient is 0, Frame Parallel Decoding Mode and Refresh Frame Context 4109 //! read from bit stream.Together with Frame Parallel Decoding mode, they 4110 //! decide the value of AdaptProbabilityFlag.</p> 4111 enum ERROR_RESILIENT_MODE 4112 { 4113 ERROR_RESILIENT_MODE_DISABLE = 0, //!< No additional details 4114 ERROR_RESILIENT_MODE_ENABLE = 1, //!< No additional details 4115 }; 4116 4117 //! \brief FRAME_PARALLEL_DECODING_MODE 4118 //! \details 4119 //! <p>Indicates if parallel decoding mode is enabled. This bit should come 4120 //! from Uncompressed header. Together with Error Resilient mode, they 4121 //! decide the value of AdaptProbabilityFlag.</p> 4122 enum FRAME_PARALLEL_DECODING_MODE 4123 { 4124 FRAME_PARALLEL_DECODING_MODE_DISABLE = 0, //!< No additional details 4125 FRAME_PARALLEL_DECODING_MODE_ENABLE = 1, //!< No additional details 4126 }; 4127 4128 //! \brief SEGMENTATION_ENABLED 4129 //! \details 4130 //! Indicate if segementation is enabled or not 4131 enum SEGMENTATION_ENABLED 4132 { 4133 SEGMENTATION_ENABLED_ALLBLOCKSAREIMPLIEDTOBELONGTOSEGMENT0 = 0, //!< No additional details 4134 SEGMENTATION_ENABLED_SEGIDDETERMINATIONDEPENDSONSEGMENTATIONUPDATEMAPSETTING = 1, //!< No additional details 4135 }; 4136 4137 //! \brief SEGMENTATION_UPDATE_MAP 4138 //! \details 4139 //! Indicates how hardware determines segmentation ID 4140 enum SEGMENTATION_UPDATE_MAP 4141 { 4142 SEGMENTATION_UPDATE_MAP_UNNAMED0 = 0, //!< Intra block: segment ID is zero Inter block: get segment ID from previous frame (streamIN) 4143 SEGMENTATION_UPDATE_MAP_UNNAMED1 = 1, //!< Intra block: decode segment ID from bitstream. Inter block: determins from segmentation_temporal_update setting 4144 }; 4145 4146 //! \brief SEGMENTATION_TEMPORAL_UPDATE 4147 //! \details 4148 //! Indicates whether segID is decoding from bitstream or predicted from 4149 //! previous frame. 4150 enum SEGMENTATION_TEMPORAL_UPDATE 4151 { 4152 SEGMENTATION_TEMPORAL_UPDATE_DECODESEGIDFROMBITSTREAM = 0, //!< No additional details 4153 SEGMENTATION_TEMPORAL_UPDATE_GETSEGIDEITHERFROMBITSTREAMORFROMPREVIOUSFRAME = 1, //!< No additional details 4154 }; 4155 4156 //! \brief LOSSLESS_MODE 4157 //! \details 4158 //! This bitSet to indicate lossless coding mode. 4159 enum LOSSLESS_MODE 4160 { 4161 LOSSLESS_MODE_NORMALMODE = 0, //!< No additional details 4162 LOSSLESS_MODE_LOLESSMODE = 1, //!< No additional details 4163 }; 4164 4165 //! \brief SEGMENT_ID_STREAMOUT_ENABLE 4166 //! \details 4167 //! Indicates SegmentID of current frame needs to be streamOut for next 4168 //! frame 4169 enum SEGMENT_ID_STREAMOUT_ENABLE 4170 { 4171 SEGMENT_ID_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 4172 SEGMENT_ID_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 4173 }; 4174 4175 //! \brief SEGMENT_ID_STREAMIN_ENABLE 4176 //! \details 4177 //! Indicates SegmentID from previous frame needs to be streamIn for Segment 4178 //! ID prediction 4179 enum SEGMENT_ID_STREAMIN_ENABLE 4180 { 4181 SEGMENT_ID_STREAMIN_ENABLE_DISABLE = 0, //!< No additional details 4182 SEGMENT_ID_STREAMIN_ENABLE_ENABLE = 1, //!< No additional details 4183 }; 4184 4185 //! \brief LOG2_TILE_COLUMN 4186 //! \details 4187 //! This indicates the number of tile rows (log2). 4188 enum LOG2_TILE_COLUMN 4189 { 4190 LOG2_TILE_COLUMN_1TILECOLUMN = 0, //!< No additional details 4191 LOG2_TILE_COLUMN_2TILECOLUMN = 1, //!< No additional details 4192 LOG2_TILE_COLUMN_4TILECOLUMN = 2, //!< No additional details 4193 LOG2_TILE_COLUMN_8TILECOLUMN = 3, //!< No additional details 4194 LOG2_TILE_COLUMN_16TILECOLUMN = 4, //!< No additional details 4195 LOG2_TILE_COLUMN_32TILECOLUMN = 5, //!< No additional details 4196 LOG2_TILE_COLUMN_64TILECOLUMN = 6, //!< No additional details 4197 }; 4198 4199 //! \brief LOG2_TILE_ROW 4200 //! \details 4201 //! This indicates the number of tile rows (log2). 4202 enum LOG2_TILE_ROW 4203 { 4204 LOG2_TILE_ROW_1TILEROW = 0, //!< No additional details 4205 LOG2_TILE_ROW_2TILEROW = 1, //!< No additional details 4206 LOG2_TILE_ROW_4TILEROW = 2, //!< No additional details 4207 }; 4208 4209 //! \brief CHROMA_SAMPLING_FORMAT 4210 //! \details 4211 //! This indicates the chroma sampling format of the bitstream 4212 enum CHROMA_SAMPLING_FORMAT 4213 { 4214 CHROMA_SAMPLING_FORMAT_FORMAT420 = 0, //!< No additional details 4215 CHROMA_SAMPLING_FORMAT_FORMAT444 = 2, //!< No additional details 4216 }; 4217 4218 //! \brief BITDEPTHMINUS8 4219 //! \details 4220 //! This indicates the bitdepth (minus 8) of the pixels 4221 enum BITDEPTHMINUS8 4222 { 4223 BITDEPTHMINUS8_BITDEPTH8 = 0, //!< No additional details 4224 BITDEPTHMINUS8_BITDEPTH10 = 2, //!< No additional details 4225 BITDEPTHMINUS8_BITDEPTH12 = 4, //!< No additional details 4226 }; 4227 4228 //! \brief PROFILE_LEVEL 4229 //! \details 4230 //! This indicates VP9 Profile level from bitstream 4231 enum PROFILE_LEVEL 4232 { 4233 PROFILE_LEVEL_PROFILE0 = 0, //!< Profile 0 only supports 8 bit 420 only 4234 PROFILE_LEVEL_PROFILE1 = 1, //!< Profile 1 only supports 8 bit 444 only 4235 PROFILE_LEVEL_PROFILE2 = 2, //!< Profile 2 only supports 10 bits 420 only 4236 PROFILE_LEVEL_PROFILE3 = 3, //!< Profile 3 only supports 10-bit 444 only 4237 }; 4238 4239 //! \brief MOTION_COMP_SCALING_ENABLE_BIT 4240 //! \details 4241 //! This bit must be set to "1" 4242 enum MOTION_COMP_SCALING_ENABLE_BIT 4243 { 4244 MOTION_COMP_SCALING_ENABLE_BIT_ENABLE = 1, //!< This enables Motion Comp Scaling 4245 }; 4246 4247 //! \brief NONFIRSTPASSFLAG 4248 //! \details 4249 //! This signals the current pass is not the first pass. It will imply 4250 //! designate HW behavior. 4251 enum NONFIRSTPASSFLAG 4252 { 4253 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 4254 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 4255 }; 4256 4257 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 4258 //! \details 4259 //! This is a mask bit controlling if the condition of frame level bit count 4260 //! exceeds FrameBitRateMax. 4261 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 4262 { 4263 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_VP9_IMAGE_STATUS control register. 4264 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit 1 of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit Rate Maximum limit. 4265 }; 4266 4267 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 4268 //! \details 4269 //! This is a mask bit controlling if the condition of frame level bit count 4270 //! is less than FrameBitRateMin. 4271 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 4272 { 4273 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register. 4274 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. 4275 }; 4276 4277 //! \brief FRAMEBITRATEMAXUNIT 4278 //! \details 4279 //! This field is the Frame Bitrate Maximum Limit Units. 4280 enum FRAMEBITRATEMAXUNIT 4281 { 4282 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 4283 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4Kbyte unit 4284 }; 4285 4286 //! \brief FRAMEBITRATEMINUNIT 4287 //! \details 4288 //! This field is the Frame Bitrate Maximum Limit Units. 4289 enum FRAMEBITRATEMINUNIT 4290 { 4291 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 4292 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4Kbyte unit 4293 }; 4294 4295 //! \brief MINFRAMESIZEUNITS 4296 //! \details 4297 //! This field is the Minimum Frame Size Units 4298 enum MINFRAMESIZEUNITS 4299 { 4300 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 4301 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 4Kbytes. 4302 MINFRAMESIZEUNITS_COMAPTIBILITYMODE = 2, //!< No additional details 4303 MINFRAMESIZEUNITS_6BYTES = 3, //!< No additional details 4304 }; 4305 4306 //! \name Initializations 4307 4308 //! \brief Explicit member initialization function HCP_VP9_PIC_STATE_CMDHCP_VP9_PIC_STATE_CMD4309 HCP_VP9_PIC_STATE_CMD() 4310 { 4311 DW0.Value = 0x73b00028; 4312 //DW0.DwordLength = GetOpLength(dwSize); 4313 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPVP9PICSTATE; 4314 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 4315 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 4316 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4317 4318 DW1.Value = 0x00000000; 4319 4320 DW2.Value = 0x00000000; 4321 //DW2.FrameType = FRAME_TYPE_KEYFRAME; 4322 //DW2.AdaptProbabilitiesFlag = ADAPT_PROBABILITIES_FLAG_0DONOTADAPT_ERRORRESILIENTORFRAMEPARALLELMODEARESET; 4323 //DW2.AllowHiPrecisionMv = ALLOW_HI_PRECISION_MV_NORMALMODE; 4324 //DW2.McompFilterType = MCOMP_FILTER_TYPE_EIGHT_TAP; 4325 //DW2.HybridPredictionMode = HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERDOESNOTPACKCOMPPREDMODEINTERPREDCOMPINPAKOBJINTOBITSTREAM; 4326 //DW2.SelectableTxMode = SELECTABLE_TX_MODE_ENCODERDOESNOTPACKTUSIZEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER; 4327 //DW2.LastFrameType = LAST_FRAME_TYPE_KEYFRAME; 4328 //DW2.RefreshFrameContext = REFRESH_FRAME_CONTEXT_DISABLE; 4329 //DW2.ErrorResilientMode = ERROR_RESILIENT_MODE_DISABLE; 4330 //DW2.FrameParallelDecodingMode = FRAME_PARALLEL_DECODING_MODE_DISABLE; 4331 //DW2.SegmentationEnabled = SEGMENTATION_ENABLED_ALLBLOCKSAREIMPLIEDTOBELONGTOSEGMENT0; 4332 //DW2.SegmentationUpdateMap = SEGMENTATION_UPDATE_MAP_UNNAMED0; 4333 //DW2.SegmentationTemporalUpdate = SEGMENTATION_TEMPORAL_UPDATE_DECODESEGIDFROMBITSTREAM; 4334 //DW2.LosslessMode = LOSSLESS_MODE_NORMALMODE; 4335 //DW2.SegmentIdStreamoutEnable = SEGMENT_ID_STREAMOUT_ENABLE_DISABLE; 4336 //DW2.SegmentIdStreaminEnable = SEGMENT_ID_STREAMIN_ENABLE_DISABLE; 4337 4338 DW3.Value = 0x00000000; 4339 //DW3.Log2TileColumn = LOG2_TILE_COLUMN_1TILECOLUMN; 4340 //DW3.Log2TileRow = LOG2_TILE_ROW_1TILEROW; 4341 //DW3.ChromaSamplingFormat = CHROMA_SAMPLING_FORMAT_FORMAT420; 4342 //DW3.Bitdepthminus8 = BITDEPTHMINUS8_BITDEPTH8; 4343 //DW3.ProfileLevel = PROFILE_LEVEL_PROFILE0; 4344 4345 DW4.Value = 0x00000000; 4346 4347 DW5.Value = 0x00000000; 4348 4349 DW6.Value = 0x00000000; 4350 4351 DW7.Value = 0x00000000; 4352 4353 DW8.Value = 0x00000000; 4354 4355 DW9.Value = 0x00000000; 4356 4357 DW10.Value = 0x00000000; 4358 4359 DW11.Value = 0x00000002; 4360 //DW11.MotionCompScalingEnableBit = MOTION_COMP_SCALING_ENABLE_BIT_ENABLE; 4361 4362 DW12.Value = 0x00000000; 4363 4364 DW13.Value = 0x00000000; 4365 4366 DW14.Value = 0x00000000; 4367 4368 DW15.Value = 0x00000000; 4369 4370 DW16.Value = 0x00000000; 4371 4372 DW17.Value = 0x00000000; 4373 4374 DW18.Value = 0x00000000; 4375 4376 DW19.Value = 0x00000000; 4377 //DW19.Nonfirstpassflag = NONFIRSTPASSFLAG_DISABLE; 4378 //DW19.FrameszoverstatusenFramebitratemaxreportmask = FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE; 4379 //DW19.FrameszunderstatusenFramebitrateminreportmask = FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE; 4380 4381 DW20.Value = 0x00000000; 4382 //DW20.Framebitratemaxunit = FRAMEBITRATEMAXUNIT_BYTE; 4383 4384 DW21.Value = 0x00000000; 4385 //DW21.Framebitrateminunit = FRAMEBITRATEMINUNIT_BYTE; 4386 4387 DW22_23.Value[0] = DW22_23.Value[1] = 0x00000000; 4388 4389 DW24.Value = 0x00000000; 4390 4391 DW25_26.Value[0] = DW25_26.Value[1] = 0x00000000; 4392 4393 DW27.Value = 0x00000000; 4394 4395 DW28_29.Value[0] = DW28_29.Value[1] = 0x00000000; 4396 4397 DW30.Value = 0x00000000; 4398 4399 DW31.Value = 0x00000000; 4400 //DW31.Minframesizeunits = MINFRAMESIZEUNITS_4KB; 4401 4402 DW32.Value = 0x00000000; 4403 4404 DW33.Value = 0x00000000; 4405 4406 memset(&SseThresholdsForClass18, 0, sizeof(SseThresholdsForClass18)); 4407 } 4408 4409 static const size_t dwSize = 42; 4410 static const size_t byteSize = 168; 4411 }; 4412 4413 //! 4414 //! \brief HEVC_VP9_RDOQ_LAMBDA_FIELDS 4415 //! \details 4416 //! 4417 //! 4418 struct HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD 4419 { 4420 union 4421 { 4422 struct 4423 { 4424 uint32_t Lambdavalue0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LambdaValue0 4425 uint32_t Lambdavalue1 : __CODEGEN_BITFIELD(16, 31) ; //!< LambdaValue1 4426 }; 4427 uint32_t Value; 4428 } DW0; 4429 4430 //! \name Local enumerations 4431 4432 //! \name Initializations 4433 4434 //! \brief Explicit member initialization function HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMDHEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD4435 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD() 4436 { 4437 DW0.Value = 0x00000000; 4438 } 4439 4440 static const size_t dwSize = 1; 4441 static const size_t byteSize = 4; 4442 }; 4443 4444 //! 4445 //! \brief HEVC_VP9_RDOQ_STATE 4446 //! \details 4447 //! 4448 //! 4449 struct HEVC_VP9_RDOQ_STATE_CMD 4450 { 4451 union 4452 { 4453 struct 4454 { 4455 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4456 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4457 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 4458 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 4459 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 4460 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4461 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4462 }; 4463 uint32_t Value; 4464 } DW0; 4465 union 4466 { 4467 struct 4468 { 4469 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 4470 uint32_t DisableHtqPerformanceFix1 : __CODEGEN_BITFIELD(30, 30) ; //!< Disable HTQ performance fix1 4471 uint32_t DisableHtqPerformanceFix0 : __CODEGEN_BITFIELD(31, 31) ; //!< Disable HTQ performance fix0 4472 }; 4473 uint32_t Value; 4474 } DW1; 4475 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda[32]; //!< DW2..33, IntraLumaLambda 4476 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda[32]; //!< DW34..65, IntraChromaLambda 4477 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda[32]; //!< DW66..97, InterLumaLambda 4478 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda[32]; //!< DW98..129, InterChromaLambda 4479 4480 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda12bit[6]; //!< DW130..135, IntraLumaLambda 4481 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda12bit[6]; //!< DW136..141, IntraChromaLambda 4482 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda12bit[6]; //!< DW142..147, InterLumaLambda 4483 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda12bit[6]; //!< DW148..153, InterChromaLambda 4484 4485 //! \name Local enumerations 4486 4487 enum SUBOPB 4488 { 4489 SUBOPB_UNNAMED8 = 8, //!< No additional details 4490 }; 4491 4492 enum SUBOPA 4493 { 4494 SUBOPA_UNNAMED0 = 0, //!< No additional details 4495 }; 4496 4497 //! \brief OPCODE 4498 //! \details 4499 //! Codec/Engine Name = HCP = 7h 4500 enum OPCODE 4501 { 4502 OPCODE_UNNAMED7 = 7, //!< No additional details 4503 }; 4504 4505 //! \brief PIPELINE 4506 //! \details 4507 //! MFX_COMMON 4508 enum PIPELINE 4509 { 4510 PIPELINE_UNNAMED2 = 2, //!< No additional details 4511 }; 4512 4513 //! \brief COMMAND_TYPE 4514 //! \details 4515 //! PARALLEL_VIDEO_PIPE 4516 enum COMMAND_TYPE 4517 { 4518 COMMAND_TYPE_UNNAMED3 = 3, //!< No additional details 4519 }; 4520 4521 //! \name Initializations 4522 4523 //! \brief Explicit member initialization function HEVC_VP9_RDOQ_STATE_CMDHEVC_VP9_RDOQ_STATE_CMD4524 HEVC_VP9_RDOQ_STATE_CMD() 4525 { 4526 DW0.Value = 0x73880098; 4527 //DW0.DwordLength = GetOpLength(dwSize); 4528 //DW0.Subopb = SUBOPB_UNNAMED8; 4529 //DW0.Subopa = SUBOPA_UNNAMED0; 4530 //DW0.Opcode = OPCODE_UNNAMED7; 4531 //DW0.Pipeline = PIPELINE_UNNAMED2; 4532 //DW0.CommandType = COMMAND_TYPE_UNNAMED3; 4533 4534 DW1.Value = 0x00000000; 4535 } 4536 4537 static const size_t dwSize = 154; 4538 static const size_t byteSize = 616; 4539 }; 4540 4541 //! 4542 //! \brief HCP_TILE_CODING 4543 //! \details 4544 //! This command is used for both HEVC and VP9 codecs 4545 //! 4546 struct HCP_TILE_CODING_CMD 4547 { 4548 union 4549 { 4550 struct 4551 { 4552 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4553 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4554 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4555 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4556 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4557 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4558 }; 4559 uint32_t Value; 4560 } DW0; 4561 union 4562 { 4563 struct 4564 { 4565 uint32_t NumberOfActiveBePipes : __CODEGEN_BITFIELD( 0, 7) ; //!< Number of Active BE Pipes 4566 uint32_t TileRowStoreSelect : __CODEGEN_BITFIELD( 8, 8) ; //!< Tile Row store Select 4567 uint32_t TileColumnStoreSelect : __CODEGEN_BITFIELD( 9, 9) ; //!< Tile Column store Select 4568 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved MBZ 4569 uint32_t NumOfTileColumnsInAFrame : __CODEGEN_BITFIELD(16, 31) ; //!< Num of Tile columns in a Frame 4570 }; 4571 uint32_t Value; 4572 } DW1; 4573 union 4574 { 4575 struct 4576 { 4577 uint32_t TileColumnPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< Tile Column Position 4578 uint32_t NonFirstPassTile : __CODEGEN_BITFIELD(10, 10) ; //!< Non First Pass Tile 4579 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4580 uint32_t TileRowPosition : __CODEGEN_BITFIELD(16, 25) ; //!< Tile Row Position 4581 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 29) ; //!< Reserved 4582 uint32_t Islasttileofrow : __CODEGEN_BITFIELD(30, 30) ; //!< IsLastTileOfRow 4583 uint32_t Islasttileofcolumn : __CODEGEN_BITFIELD(31, 31) ; //!< IsLastTileOfColumn 4584 }; 4585 uint32_t Value; 4586 } DW2; 4587 union 4588 { 4589 struct 4590 { 4591 uint32_t Tileheightinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< TileHeightInMinCbMinus1 4592 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4593 uint32_t Tilewidthinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< TileWidthInMinCbMinus1 4594 uint32_t Reserved123 : __CODEGEN_BITFIELD(27, 30) ; //!< Reserved 4595 uint32_t LastpassoftileValidationonly : __CODEGEN_BITFIELD(31, 31) ; //!< LastPassOfTile (ValidationOnly) 4596 }; 4597 uint32_t Value; 4598 } DW3; 4599 union 4600 { 4601 struct 4602 { 4603 uint32_t BitstreamByteOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Bitstream Byte Offset Enable 4604 uint32_t Reserved129 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 4605 uint32_t BitstreamByteOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitstream Byte Offset 4606 }; 4607 uint32_t Value; 4608 } DW4; 4609 union 4610 { 4611 struct 4612 { 4613 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4614 uint32_t PakFrameStatisticsOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< PAK Frame Statistics Offset 4615 }; 4616 uint32_t Value; 4617 } DW5; 4618 union 4619 { 4620 struct 4621 { 4622 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4623 uint32_t CuLevelStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU Level Streamout Offset 4624 }; 4625 uint32_t Value; 4626 } DW6; 4627 union 4628 { 4629 struct 4630 { 4631 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4632 uint32_t SliceSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Slice Size Streamout Offset 4633 }; 4634 uint32_t Value; 4635 } DW7; 4636 union 4637 { 4638 struct 4639 { 4640 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4641 uint32_t CuRecordOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU record offset 4642 }; 4643 uint32_t Value; 4644 } DW8; 4645 union 4646 { 4647 struct 4648 { 4649 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4650 uint32_t SseRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SSE RowStore offset 4651 }; 4652 uint32_t Value; 4653 } DW9; 4654 union 4655 { 4656 struct 4657 { 4658 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4659 uint32_t SaoRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SAO RowStore offset 4660 }; 4661 uint32_t Value; 4662 } DW10; 4663 union 4664 { 4665 struct 4666 { 4667 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4668 uint32_t TileSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Size StreamOut Offset 4669 }; 4670 uint32_t Value; 4671 } DW11; 4672 union 4673 { 4674 struct 4675 { 4676 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4677 uint32_t Vp9ProbabilityCounterStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< VP9 Probability Counter Streamout Offset 4678 }; 4679 uint32_t Value; 4680 } DW12; 4681 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySynchronizeBufferBaseAddress; //!< DW13..14, HCP Scalability Synchronize Buffer - Base Address 4682 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySynchronizeBufferAttributes; //!< DW15, HCP Scalability Synchronize Buffer - Attributes 4683 union 4684 { 4685 struct 4686 { 4687 uint32_t Reserved512 ; //!< Reserved 4688 }; 4689 uint32_t Value; 4690 } DW16; 4691 union 4692 { 4693 struct 4694 { 4695 uint32_t Reserved544 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 4696 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 4697 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame Number 4698 uint32_t Reserved562 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 4699 }; 4700 uint32_t Value; 4701 } DW17; 4702 union 4703 { 4704 struct 4705 { 4706 uint32_t TilemetadataDw1 ; //!< TileMetaData_DW1 4707 }; 4708 uint32_t Value; 4709 } DW18; 4710 union 4711 { 4712 struct 4713 { 4714 uint32_t TilemetadataDw2 ; //!< TileMetaData_DW2 4715 }; 4716 uint32_t Value; 4717 } DW19; 4718 4719 //! \name Local enumerations 4720 4721 enum MEDIA_INSTRUCTION_COMMAND 4722 { 4723 MEDIA_INSTRUCTION_COMMAND_HCPTILECODING = 21, //!< No additional details 4724 }; 4725 4726 enum MEDIA_INSTRUCTION_OPCODE 4727 { 4728 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4729 }; 4730 4731 enum PIPELINE_TYPE 4732 { 4733 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4734 }; 4735 4736 enum COMMAND_TYPE 4737 { 4738 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4739 }; 4740 4741 //! \name Initializations 4742 4743 //! \brief Explicit member initialization function HCP_TILE_CODING_CMDHCP_TILE_CODING_CMD4744 HCP_TILE_CODING_CMD() 4745 { 4746 DW0.Value = 0x73950012; 4747 //DW0.DwordLength = GetOpLength(dwSize); 4748 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPTILECODING; 4749 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 4750 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 4751 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4752 4753 DW1.Value = 0x00000000; 4754 4755 DW2.Value = 0x00000000; 4756 4757 DW3.Value = 0x00000000; 4758 4759 DW4.Value = 0x00000000; 4760 4761 DW5.Value = 0x00000000; 4762 4763 DW6.Value = 0x00000000; 4764 4765 DW7.Value = 0x00000000; 4766 4767 DW8.Value = 0x00000000; 4768 4769 DW9.Value = 0x00000000; 4770 4771 DW10.Value = 0x00000000; 4772 4773 DW11.Value = 0x00000000; 4774 4775 DW12.Value = 0x00000000; 4776 4777 DW16.Value = 0x00000000; 4778 4779 DW17.Value = 0x00000000; 4780 4781 DW18.Value = 0x00000000; 4782 4783 DW19.Value = 0x00000000; 4784 } 4785 4786 static const size_t dwSize = 20; 4787 static const size_t byteSize = 80; 4788 }; 4789 4790 //! 4791 //! \brief HCP_PALETTE_INITIALIZER_STATE 4792 //! \details 4793 //! The HCP is selected with theMedia Instruction Opcode "7h"for all HCP 4794 //! Commands. Each HCP command has assigned a media instruction command as 4795 //! defined in DWord 0, BitField 22:16. 4796 //! 4797 //! The HCP_PALETTE_INITIALIZER_STATE command loads in the SCC Palette 4798 //! Initilizer Table to the HW. 4799 //! Decoder only command. 4800 //! 4801 //! Dword#2 - 193form a fixed size table for the Palette Initializer Table. 4802 //! Max PaletteInitializer Table is 128entries. Each entry has 3 components 4803 //! (Y, Cb and Cr) for a color. 4804 //! Each component is 16-bits, even though currently only support up to 4805 //! 10-bit SCC extension. The upper (higher bits) 6 bits are set to zero - 4806 //! that is Least Significant Bit alignment. 4807 //! Each entry of thePalette Initializer Table will consume 1.5 Dwords. 4808 //! Every two entries will consume 2 Dwords. Hence, total requires 96 4809 //! Dwords. 4810 //! Dword#2 Bit 31 Cb#0 15:0 Luma#0 15:0 Bit 0 4811 //! Dword#3 Bit 31 Luma#115:0 Cr#015:0 Bit 0 4812 //! Dword#4 Bit 31 Cr#115:0 Cb#115:0 Bit 0 4813 //! Dword#2 correspondsto the entry# 0 of thePalette Initializer Table. 4814 //! Dword#193correspondsto the entry# 127of thePalette Initializer Table. 4815 //! 4816 //! Palette Initialization needs to happen at the beginning of each 4817 //! frame/tiles or start of each independent slice. Palette initialization 4818 //! is not needed at the start of dependent slices (except the start of a 4819 //! new tiles since each tile needs to re-initialize the palette list) and 4820 //! the palette list is inherited from previous slice. 4821 //! The following is the programming restriction: 4822 //! (1) Palette Initialization commandmust be programmedin palette mode at 4823 //! the beginning of each frame and tiles (regardless if the slice 4824 //! isindependent/dependent)and also the start of each independent slices. 4825 //! (2) Palette Initialization command must not be programmed for dependent 4826 //! slices except the dependent slices are start of tiles (first slice in 4827 //! frame must be independent slice). 4828 //! 4829 //! 4830 struct HCP_PALETTE_INITIALIZER_STATE_CMD 4831 { 4832 union 4833 { 4834 struct 4835 { 4836 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4837 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4838 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4839 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4840 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4841 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4842 }; 4843 uint32_t Value; 4844 } DW0; 4845 union 4846 { 4847 struct 4848 { 4849 uint32_t ActivePaletteInitializerTableEntries : __CODEGEN_BITFIELD( 0, 7) ; //!< Active Palette Initializer Table Entries 4850 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 4851 }; 4852 uint32_t Value; 4853 } DW1; 4854 uint32_t First64ColorEntries[96]; //!< First 64 Color Entries 4855 uint32_t Second64ColorEntries[96]; //!< Second 64 Color Entries 4856 4857 //! \name Local enumerations 4858 4859 enum MEDIA_INSTRUCTION_COMMAND 4860 { 4861 MEDIA_INSTRUCTION_COMMAND_HCPPALETTEINITIALIZERSTATE = 9, //!< No additional details 4862 }; 4863 4864 //! \brief MEDIA_INSTRUCTION_OPCODE 4865 //! \details 4866 //! Codec/Engine Name = HCP = 7h 4867 enum MEDIA_INSTRUCTION_OPCODE 4868 { 4869 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4870 }; 4871 4872 enum PIPELINE_TYPE 4873 { 4874 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4875 }; 4876 4877 enum COMMAND_TYPE 4878 { 4879 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4880 }; 4881 4882 //! \name Initializations 4883 4884 //! \brief Explicit member initialization function HCP_PALETTE_INITIALIZER_STATE_CMDHCP_PALETTE_INITIALIZER_STATE_CMD4885 HCP_PALETTE_INITIALIZER_STATE_CMD() 4886 { 4887 DW0.Value = 0x738900c0; 4888 //DW0.DwordLength = GetOpLength(dwSize); 4889 //DW0.MediaInstructionCommand = MEDIA_INSTRUCTION_COMMAND_HCPPALETTEINITIALIZERSTATE; 4890 //DW0.MediaInstructionOpcode = MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME; 4891 //DW0.PipelineType = PIPELINE_TYPE_UNNAMED2; 4892 //DW0.CommandType = COMMAND_TYPE_PARALLELVIDEOPIPE; 4893 4894 DW1.Value = 0x00000000; 4895 4896 memset(&First64ColorEntries, 0, sizeof(First64ColorEntries)); 4897 4898 memset(&Second64ColorEntries, 0, sizeof(Second64ColorEntries)); 4899 } 4900 4901 static const size_t dwSize = 194; 4902 static const size_t byteSize = 776; 4903 }; 4904 MEDIA_CLASS_DEFINE_END(mhw__vdbox__hcp__xe_lpm_plus_base__v1__Cmd) 4905 }; 4906 } // namespace v1 4907 } // namespace xe_lpm_plus_base 4908 } // namespace hcp 4909 } // namespace vdbox 4910 } // namespace mhw 4911 4912 #pragma pack() 4913 4914 #endif // __MHW_VDBOX_HCP_HWCMD_XE2_HPM_H__ 4915