1 /*===================== begin_copyright_notice ================================== 2 3 Copyright (c) 2018-2019, Intel Corporation 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included 13 in all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_vdbox_hcp_hwcmd_g12_X.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of g12_X as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 31 // DO NOT EDIT 32 33 #ifndef __MHW_VDBOX_HCP_HWCMD_G12_X_H__ 34 #define __MHW_VDBOX_HCP_HWCMD_G12_X_H__ 35 36 #pragma once 37 #pragma pack(1) 38 39 #include <cstdint> 40 #include <cstddef> 41 42 class mhw_vdbox_hcp_g12_X 43 { 44 public: 45 // Internal Macros 46 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 47 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 48 #define __CODEGEN_OP_LENGTH_BIAS 2 49 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 50 GetOpLength(uint32_t uiLength)51 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 52 53 //! 54 //! \brief MEMORYADDRESSATTRIBUTES 55 //! \details 56 //! This field controls the priority of arbitration used in the GAC/GAM 57 //! pipeline for this surface. It defines the attributes for VDBOX addresses 58 //! on BDW+. 59 //! 60 struct MEMORYADDRESSATTRIBUTES_CMD 61 { 62 union 63 { 64 struct 65 { 66 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 67 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Base Address - Index to Memory Object Control State (MOCS) Tables 68 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Base Address - Arbitration Priority Control 69 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Base Address - Memory Compression Enable 70 uint32_t CompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< COMPRESSION_TYPE 71 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 72 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 73 uint32_t BaseAddressTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BASE_ADDRESS_TILED_RESOURCE_MODE 74 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 75 }; 76 uint32_t Value; 77 } DW0; 78 79 //! \name Local enumerations 80 81 //! \brief COMPRESSION_TYPE 82 //! \details 83 //! Indicates if buffer is render/media compressed. 84 enum COMPRESSION_TYPE 85 { 86 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLE = 0, //!< No additional details 87 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLE = 1, //!< No additional details 88 }; 89 90 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 91 //! \details 92 //! This field controls if the Row Store is going to store inside Media 93 //! Cache (rowstore cache) or to LLC. 94 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 95 { 96 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 97 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 98 }; 99 100 //! \brief BASE_ADDRESS_TILED_RESOURCE_MODE 101 //! \details 102 //! <b>For Media Surfaces:</b> This field specifies the tiled resource mode. 103 enum BASE_ADDRESS_TILED_RESOURCE_MODE 104 { 105 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< TileY resources 106 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 107 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 108 }; 109 110 //! \name Initializations 111 112 //! \brief Explicit member initialization function 113 MEMORYADDRESSATTRIBUTES_CMD(); 114 115 static const size_t dwSize = 1; 116 static const size_t byteSize = 4; 117 }; 118 119 //! 120 //! \brief SPLITBASEADDRESS64BYTEALIGNED 121 //! \details 122 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 123 //! address. 124 //! 125 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 126 { 127 union 128 { 129 struct 130 { 131 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 132 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD( 6, 47) ; //!< GraphicsAddress47-6 133 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 134 }; 135 uint32_t Value[2]; 136 } DW0_1; 137 138 //! \name Local enumerations 139 140 //! \name Initializations 141 142 //! \brief Explicit member initialization function 143 SPLITBASEADDRESS64BYTEALIGNED_CMD(); 144 145 static const size_t dwSize = 2; 146 static const size_t byteSize = 8; 147 }; 148 149 //! 150 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 151 //! \details 152 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 153 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 154 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 155 //! 156 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 157 { 158 union 159 { 160 struct 161 { 162 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 163 uint64_t Graphicsaddress4712 : __CODEGEN_BITFIELD(12, 47) ; //!< GraphicsAddress47-12 164 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 165 }; 166 uint32_t Value[2]; 167 } DW0_1; 168 169 //! \name Local enumerations 170 171 //! \name Initializations 172 173 //! \brief Explicit member initialization function 174 SPLITBASEADDRESS4KBYTEALIGNED_CMD(); 175 176 static const size_t dwSize = 2; 177 static const size_t byteSize = 8; 178 }; 179 180 //! 181 //! \brief HCP_PIPE_MODE_SELECT 182 //! \details 183 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 184 //! Commands. Each HCP command has assigned a media instruction command as 185 //! defined in DWord 0, BitField 22:16. 186 //! 187 //! The workload for the HCP is based upon a single frame decode. There are 188 //! no states saved between frame decodes in the HCP. Once the bit stream 189 //! DMA is configured with the HCP_BSD_OBJECT command, and the bit stream is 190 //! presented to the HCP, the frame decode will begin. The 191 //! HCP_PIPE_MODE_SELECT command is responsible for general pipeline level 192 //! configuration that would normally be set once for a single stream encode 193 //! or decode and would not be modified on a frame workload basis. This is a 194 //! picture level state command and is shared by both encoding and decoding 195 //! processes. 196 //! 197 struct HCP_PIPE_MODE_SELECT_CMD 198 { 199 union 200 { 201 struct 202 { 203 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 204 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 205 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 206 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 207 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 208 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 209 }; 210 uint32_t Value; 211 } DW0; 212 union 213 { 214 struct 215 { 216 uint32_t CodecSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< CODEC_SELECT 217 uint32_t DeblockerStreamoutEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< DEBLOCKER_STREAMOUT_ENABLE 218 uint32_t PakPipelineStreamoutEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< PAK_PIPELINE_STREAMOUT_ENABLE 219 uint32_t PicStatusErrorReportEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< PIC_STATUSERROR_REPORT_ENABLE 220 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 221 uint32_t CodecStandardSelect : __CODEGEN_BITFIELD( 5, 7) ; //!< CODEC_STANDARD_SELECT 222 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 223 uint32_t AdvancedRateControlEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Advanced Rate Control Enable 224 uint32_t VdencMode : __CODEGEN_BITFIELD(10, 10) ; //!< VDEnc_Mode 225 uint32_t RdoqEnabledFlag : __CODEGEN_BITFIELD(11, 11) ; //!< RDOQ_ENABLED_FLAG 226 uint32_t PakFrameLevelStreamoutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< PAK Frame Level StreamOut enable 227 uint32_t MultiEngineMode : __CODEGEN_BITFIELD(13, 14) ; //!< MULTI_ENGINE_MODE 228 uint32_t PipeWorkingMode : __CODEGEN_BITFIELD(15, 16) ; //!< PIPE_WORKING_MODE 229 uint32_t TileBasedEngine : __CODEGEN_BITFIELD(17, 17) ; //!< Tile Based Engine 230 uint32_t PrefetchDisable : __CODEGEN_BITFIELD(18, 18) ; //!< Prefetch Disable 231 uint32_t Vp9DynamicScalingEnable : __CODEGEN_BITFIELD(19, 19) ; //!< VP9 Dynamic scaling enable 232 uint32_t Reserved52 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 233 uint32_t MotionCompMemoryTrackerCounterEnable : __CODEGEN_BITFIELD(23, 23) ; //!< Motion Comp Memory Tracker Counter Enable 234 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 235 }; 236 uint32_t Value; 237 } DW1; 238 union 239 { 240 struct 241 { 242 uint32_t MediaSoftResetCounterPer1000Clocks ; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 243 }; 244 uint32_t Value; 245 } DW2; 246 union 247 { 248 struct 249 { 250 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 251 }; 252 uint32_t Value; 253 } DW3; 254 union 255 { 256 struct 257 { 258 uint32_t Reserved128 ; //!< Reserved 259 }; 260 uint32_t Value; 261 } DW4; 262 union 263 { 264 struct 265 { 266 uint32_t Reserved160 ; //!< Reserved 267 }; 268 uint32_t Value; 269 } DW5; 270 union 271 { 272 struct 273 { 274 uint32_t PhaseIndicator : __CODEGEN_BITFIELD( 0, 1) ; //!< PHASE_INDICATOR 275 uint32_t HevcSeparateTileProgramming : __CODEGEN_BITFIELD( 2, 2) ; //!< HEVC Separate Tile Programming 276 uint32_t FrameReconstructionDisable : __CODEGEN_BITFIELD( 3, 3) ; //!< Frame reconstruction disable 277 uint32_t Reserved196 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 278 }; 279 uint32_t Value; 280 } DW6; 281 282 //! \name Local enumerations 283 284 enum MEDIA_INSTRUCTION_COMMAND 285 { 286 MEDIA_INSTRUCTION_COMMAND_HCPPIPEMODESELECT = 0, //!< No additional details 287 }; 288 289 //! \brief MEDIA_INSTRUCTION_OPCODE 290 //! \details 291 //! Codec/Engine Name = HCP = 7h 292 enum MEDIA_INSTRUCTION_OPCODE 293 { 294 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 295 }; 296 297 enum PIPELINE_TYPE 298 { 299 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 300 }; 301 302 enum COMMAND_TYPE 303 { 304 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 305 }; 306 307 enum CODEC_SELECT 308 { 309 CODEC_SELECT_DECODE = 0, //!< No additional details 310 CODEC_SELECT_ENCODE = 1, //!< No additional details 311 }; 312 313 //! \brief DEBLOCKER_STREAMOUT_ENABLE 314 //! \details 315 //! Deblocker Streamout Enable not currently supported for Encode or Decode 316 enum DEBLOCKER_STREAMOUT_ENABLE 317 { 318 DEBLOCKER_STREAMOUT_ENABLE_DISABLE = 0, //!< Disable deblocker-only parameter streamout 319 DEBLOCKER_STREAMOUT_ENABLE_ENABLE = 1, //!< Enable deblocker-only parameter streamout 320 }; 321 322 //! \brief PAK_PIPELINE_STREAMOUT_ENABLE 323 //! \details 324 //! Pipeline Streamout Enable is only defined for encode. It is ignored for 325 //! decode. 326 enum PAK_PIPELINE_STREAMOUT_ENABLE 327 { 328 PAK_PIPELINE_STREAMOUT_ENABLE_DISABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 0, //!< No additional details 329 PAK_PIPELINE_STREAMOUT_ENABLE_ENABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 1, //!< No additional details 330 }; 331 332 enum PIC_STATUSERROR_REPORT_ENABLE 333 { 334 PIC_STATUSERROR_REPORT_ENABLE_DISABLE = 0, //!< Disable status/error reporting 335 PIC_STATUSERROR_REPORT_ENABLE_ENABLE = 1, //!< Status/Error reporting is written out once per picture. The Pic Status/Error Report ID in DWord3along with the status/error status bits are packed into one cache line and written to theStatus/Error Buffer address in the HCP_PIPE_BUF_ADDR_STATE command. Must be zero for encoder mode. 336 }; 337 338 enum CODEC_STANDARD_SELECT 339 { 340 CODEC_STANDARD_SELECT_HEVC = 0, //!< No additional details 341 CODEC_STANDARD_SELECT_VP9 = 1, //!< No additional details 342 }; 343 344 enum RDOQ_ENABLED_FLAG 345 { 346 RDOQ_ENABLED_FLAG_DISABLED = 0, //!< No additional details 347 RDOQ_ENABLED_FLAG_ENABLED = 1, //!< No additional details 348 }; 349 350 //! \brief MULTI_ENGINE_MODE 351 //! \details 352 //! <p>This indicates the current pipe is in single pipe mode or if in 353 //! scalable mode is in left/right/middle pipe in multi-engine mode.</p> 354 enum MULTI_ENGINE_MODE 355 { 356 MULTI_ENGINE_MODE_SINGLEENGINEMODEORCABACFEONLYDECODEMODE = 0, //!< This is for single engine mode (legacy) OR CABAC FE only decode mode During HEVC Decoder Scalability Real Tile Mode, for the last phase, it is possible to have single tile column left. In this case, it should be programmed with pipe as a single engine mode (using this value).For example, for 9 tile column running on 4 pipes. The first two phases will use all 4 pipes and finish 8 tile column. The remaining one column will be processed as last third phase as single tile column. 357 MULTI_ENGINE_MODE_PIPEISTHELEFTENGINEINAMULTI_ENGINEMODE = 1, //!< Current pipe is the most left engine while running in scalable multi-engine mode 358 MULTI_ENGINE_MODE_PIPEISTHERIGHTENGINEINAMULTI_ENGINEMODE = 2, //!< Current pipe is the most right engine while running in scalable multi-engine mode 359 MULTI_ENGINE_MODE_PIPEISONEOFTHEMIDDLEENGINEINAMULTI_ENGINEMODE = 3, //!< Current pipe is in one of the middle engine while running in scalable multi-engine mode 360 }; 361 362 //! \brief PIPE_WORKING_MODE 363 //! \details 364 //! <p>This programs the working mode for HCP pipe.</p> 365 enum PIPE_WORKING_MODE 366 { 367 PIPE_WORKING_MODE_LEGACYDECODERENCODERMODE_SINGLEPIPE = 0, //!< This is for single pipe mode non-scalable mode. It is used by both decoder and encoder. 368 PIPE_WORKING_MODE_CABACFEONLYDECODEMODE_SINGLECABACPIPE = 1, //!< This is for the single CABAC FE only in decoder mode. This will be only run CABAC and streamout syntax element. 369 PIPE_WORKING_MODE_DECODERBEONLYORENCODERMODE_SCALABLEMULTI_PIPE = 2, //!< This is for multiple-pipe scalable mode. In decoder, it is only on BE reconstruction. In ecoder, it is for PAK. 370 PIPE_WORKING_MODE_DECODERSCALABLEMODEWITHCABACINREALTILES_SCALABLEMULTI_PIPE = 3, //!< This is for multiple-pipe scalable mode decoder mode in real tiles. CABAC and reconstruction will run together. Each pipes will run in real tiles vertically. 371 }; 372 373 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 374 //! \details 375 //! In decoder modes, this counter value specifies the number of clocks (per 376 //! 1000) of GAC inactivity 377 //! before a media soft-reset is applied to the HCP and HuC. If counter 378 //! value is set to 0, the media 379 //! soft-reset feature is disabled and no reset will occur. 380 //! <p>In encoder modes, this counter must be set to 0 to disable media 381 //! soft reset. This feature is not 382 //! supported for the encoder.</p> 383 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 384 { 385 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 386 }; 387 388 //! \brief PIC_STATUSERROR_REPORT_ID 389 //! \details 390 //! The Pic Status/Error Report ID is a unique 32-bit unsigned integer 391 //! assigned to each picture 392 //! status/error output. Must be zero for encoder mode. 393 enum PIC_STATUSERROR_REPORT_ID 394 { 395 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 396 }; 397 398 //! \brief PHASE_INDICATOR 399 //! \details 400 //! <p>This is used to indicate whether this is first, middle or last phase 401 //! of programming during Real-Tile Decoder Mode. Since HEVC can have upto 402 //! 20 tile columns, maximum 10 phases are possible during 2 VDbox scalable 403 //! mode. This is used by hardware to know if the current programming is 404 //! first or last phases.</p> 405 //! <p>This field is ignored (programmed to 0) for other modes other than 406 //! HEVC Real-Tile Decoder Mode.</p> 407 enum PHASE_INDICATOR 408 { 409 PHASE_INDICATOR_FIRSTPHASE = 0, //!< No additional details 410 PHASE_INDICATOR_MIDDLEPHASE = 1, //!< No additional details 411 PHASE_INDICATOR_LASTPHASE = 2, //!< No additional details 412 }; 413 414 //! \name Initializations 415 416 //! \brief Explicit member initialization function 417 HCP_PIPE_MODE_SELECT_CMD(); 418 419 static const size_t dwSize = 7; 420 static const size_t byteSize = 28; 421 }; 422 423 //! 424 //! \brief HCP_SURFACE_STATE 425 //! \details 426 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 427 //! Commands. Each HCP command has assigned a media instruction command as 428 //! defined in DWord 0, BitField 22:16. 429 //! 430 //! The HCP_SURFACE_STATE command is responsible for defining the frame 431 //! buffer pitch and the offset of the chroma component. This is a picture 432 //! level state command and is shared by both encoding and decoding 433 //! processes. Note : Only NV12 and Tile Y are being supported for HEVC. 434 //! Hence full pitch and interleaved UV is always in use. U and V Xoffset 435 //! must be set to 0; U and V Yoffset must be 16-pixel aligned. This Surface 436 //! State is not the same as that of the 3D engine and of the MFX pipeline. 437 //! 438 struct HCP_SURFACE_STATE_CMD 439 { 440 union 441 { 442 struct 443 { 444 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 445 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 446 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 447 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 448 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 449 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 450 }; 451 uint32_t Value; 452 } DW0; 453 union 454 { 455 struct 456 { 457 uint32_t SurfacePitchMinus1 : __CODEGEN_BITFIELD( 0, 16) ; //!< Surface Pitch Minus1 458 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 27) ; //!< Reserved 459 uint32_t SurfaceId : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_ID 460 }; 461 uint32_t Value; 462 } DW1; 463 union 464 { 465 struct 466 { 467 uint32_t YOffsetForUCbInPixel : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) in pixel 468 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 469 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 470 }; 471 uint32_t Value; 472 } DW2; 473 union 474 { 475 struct 476 { 477 uint32_t DefaultAlphaValue : __CODEGEN_BITFIELD( 0, 15) ; //!< Default Alpha Value 478 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(16, 31) ; //!< Y Offset for V(Cr) 479 }; 480 uint32_t Value; 481 } DW3; 482 union 483 { 484 struct 485 { 486 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD( 0, 7) ; //!< MEMORY_COMPRESSION_ENABLE 487 uint32_t CompressionType : __CODEGEN_BITFIELD( 8, 15) ; //!< COMPRESSION_TYPE 488 uint32_t CompressionFormat : __CODEGEN_BITFIELD(16, 20) ; //!< COMPRESSION_FORMAT 489 uint32_t Reserved144 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 490 }; 491 uint32_t Value; 492 } DW4; 493 494 //! \name Local enumerations 495 496 enum MEDIA_INSTRUCTION_COMMAND 497 { 498 MEDIA_INSTRUCTION_COMMAND_HCPSURFACESTATE = 1, //!< No additional details 499 }; 500 501 //! \brief MEDIA_INSTRUCTION_OPCODE 502 //! \details 503 //! Codec/Engine Name = HCP = 7h 504 enum MEDIA_INSTRUCTION_OPCODE 505 { 506 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 507 }; 508 509 enum PIPELINE_TYPE 510 { 511 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 512 }; 513 514 enum COMMAND_TYPE 515 { 516 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 517 }; 518 519 enum SURFACE_ID 520 { 521 SURFACE_ID_HEVCFORCURRENTDECODEDPICTURE = 0, //!< 8-bit uncompressed data 522 SURFACE_ID_SOURCEINPUTPICTURE_ENCODER = 1, //!< 8-bit uncompressed data 523 SURFACE_ID_PREVREFERENCEPICTURE = 2, //!< (VP9 only) Previous Reference 524 SURFACE_ID_GOLDENREFERENCEPICTURE = 3, //!< (VP9 only) Golden Reference 525 SURFACE_ID_ALTREFREFERENCEPICTURE = 4, //!< (VP9 only) AltRef Reference 526 SURFACE_ID_HEVCREFERENCEPICTURES = 5, //!< (HEVC only) Reference. Also, this will have separate compressible bits per reference surfaces for HEVC 527 }; 528 529 //! \brief SURFACE_FORMAT 530 //! \details 531 //! <p>Specifies the format of the surface.</p> 532 enum SURFACE_FORMAT 533 { 534 SURFACE_FORMAT_YUY2FORMAT = 0, //!< No additional details 535 SURFACE_FORMAT_RGB8FORMAT = 1, //!< No additional details 536 SURFACE_FORMAT_AYUV4444FORMAT = 2, //!< No additional details 537 SURFACE_FORMAT_P010VARIANT = 3, //!< No additional details 538 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 539 SURFACE_FORMAT_YCRCBSWAPYFORMAT = 5, //!< No additional details 540 SURFACE_FORMAT_YCRCBSWAPUVFORMAT = 6, //!< No additional details 541 SURFACE_FORMAT_YCRCBSWAPUVYFORMAT = 7, //!< No additional details 542 SURFACE_FORMAT_Y216Y210FORMAT = 8, //!< Same value is used to represent Y216 and Y210 543 SURFACE_FORMAT_RGB10FORMAT = 9, //!< No additional details 544 SURFACE_FORMAT_Y410FORMAT = 10, //!< No additional details 545 SURFACE_FORMAT_NV21PLANAR4208FORMAT = 11, //!< No additional details 546 SURFACE_FORMAT_Y416FORMAT = 12, //!< No additional details 547 SURFACE_FORMAT_P010 = 13, //!< No additional details 548 SURFACE_FORMAT_P016 = 14, //!< No additional details 549 SURFACE_FORMAT_Y8FORMAT = 15, //!< No additional details 550 SURFACE_FORMAT_Y16FORMAT = 16, //!< No additional details 551 SURFACE_FORMAT_Y216VARIANT = 17, //!< Y216Variant is the modifed Y210/Y216 format, 8 bit planar 422 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The chroma is UV interleaved with identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 552 SURFACE_FORMAT_Y416VARIANT = 18, //!< Y416Variant is the modifed Y410/Y412/Y416 format,8 bit planar 444 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The U channel is below the luma, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma The V channel is below the U, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 553 SURFACE_FORMAT_YUY2VARIANT = 19, //!< YUY2Variant is the modifed YUY2 format, 8 bit planar 422. The chroma is UV interleaved and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 554 SURFACE_FORMAT_AYUV4444VARIANT = 20, //!< AYUV4444Variant is the modifed AYUV4444 format, 8 bit planar 444 format. The U channel is below the luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. The V channel is below the and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 555 }; 556 557 //! \brief MEMORY_COMPRESSION_ENABLE 558 //! \details 559 //! <p>In HEVC mode, each bit is used for 1 reference starting with Bit 0 560 //! for Ref 0 in the ref list and Bit 1 for Ref 1 and so on.</p> 561 //! <p>In VP9 mode, Bit 0 is for Previous Reference; Bit 1 is for Golden 562 //! Reference and Bit 2 is for Alterante Reference; Bits 3-7 are unused and 563 //! should be programmed to 0.</p> 564 enum MEMORY_COMPRESSION_ENABLE 565 { 566 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONDISABLE = 0, //!< No additional details 567 MEMORY_COMPRESSION_ENABLE_MEMORYCOMPRESSIONENABLE = 1, //!< No additional details 568 }; 569 570 //! \brief COMPRESSION_TYPE 571 //! \details 572 //! <p>This field indicates if the compression type for the reference 573 //! surface is media or render compressed.</p> 574 //! <p>In HEVC mode, each bit is used for 1 reference starting with Bit 8for 575 //! Ref 0 in the ref list and Bit 9for Ref 1 and so on.</p> 576 //! <p>In VP9 mode, Bit 8is for Previous Reference; Bit 9is for Golden 577 //! Reference and Bit 10is for Alterante Reference; Bits11-15are unused and 578 //! should be programmed to 0</p> 579 enum COMPRESSION_TYPE 580 { 581 COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED = 0, //!< No additional details 582 COMPRESSION_TYPE_RENDERCOMPRESSIONENABLED = 1, //!< No additional details 583 }; 584 585 //! \name Initializations 586 587 //! \brief Explicit member initialization function 588 HCP_SURFACE_STATE_CMD(); 589 590 static const size_t dwSize = 5; 591 static const size_t byteSize = 20; 592 }; 593 594 //! 595 //! \brief HCP_PIPE_BUF_ADDR_STATE 596 //! \details 597 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 598 //! Commands. Each HCP command has assigned a media instruction command as 599 //! defined in DWord 0, BitField 22:16. 600 //! 601 //! This state command provides the memory base addresses for the row store 602 //! buffer and reconstructed picture output buffers required by the HCP. 603 //! This is a picture level state command and is shared by both encoding and 604 //! decoding processes. 605 //! 606 //! All pixel surface addresses must be 4K byte aligned. There is a max of 8 607 //! Reference Picture Buffer Addresses, and all share the same third address 608 //! DW in specifying 48-bit address. 609 //! 610 struct HCP_PIPE_BUF_ADDR_STATE_CMD 611 { 612 union 613 { 614 struct 615 { 616 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 617 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 618 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 619 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 620 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 621 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 622 }; 623 uint32_t Value; 624 } DW0; 625 SPLITBASEADDRESS4KBYTEALIGNED_CMD DecodedPicture; //!< DW1..2, Decoded Picture 626 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureMemoryAddressAttributes; //!< DW3, Decoded Picture Memory Address Attributes 627 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterLineBuffer; //!< DW4..5, Deblocking Filter Line Buffer 628 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterLineBufferMemoryAddressAttributes; //!< DW6, Deblocking Filter Line Buffer Memory Address Attributes 629 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileLineBuffer; //!< DW7..8, Deblocking Filter Tile Line Buffer 630 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileLineBufferMemoryAddressAttributes; //!< DW9, Deblocking Filter Tile Line Buffer Memory Address Attributes 631 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileColumnBuffer; //!< DW10..11, Deblocking Filter Tile Column Buffer 632 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileColumnBufferMemoryAddressAttributes; //!< DW12, Deblocking Filter Tile Column Buffer Memory Address Attributes 633 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataLineBuffer; //!< DW13..14, Metadata Line Buffer 634 MEMORYADDRESSATTRIBUTES_CMD MetadataLineBufferMemoryAddressAttributes; //!< DW15, Metadata Line Buffer Memory Address Attributes 635 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileLineBuffer; //!< DW16..17, Metadata Tile Line Buffer 636 MEMORYADDRESSATTRIBUTES_CMD MetadataTileLineBufferMemoryAddressAttributes; //!< DW18, Metadata Tile Line Buffer Memory Address Attributes 637 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileColumnBuffer; //!< DW19..20, Metadata Tile Column Buffer 638 MEMORYADDRESSATTRIBUTES_CMD MetadataTileColumnBufferMemoryAddressAttributes; //!< DW21, Metadata Tile Column Buffer Memory Address Attributes 639 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoLineBuffer; //!< DW22..23, SAO Line Buffer 640 MEMORYADDRESSATTRIBUTES_CMD SaoLineBufferMemoryAddressAttributes; //!< DW24, SAO Line Buffer Memory Address Attributes 641 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileLineBuffer; //!< DW25..26, SAO Tile Line Buffer 642 MEMORYADDRESSATTRIBUTES_CMD SaoTileLineBufferMemoryAddressAttributes; //!< DW27, SAO Tile Line Buffer Memory Address Attributes 643 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileColumnBuffer; //!< DW28..29, SAO Tile Column Buffer 644 MEMORYADDRESSATTRIBUTES_CMD SaoTileColumnBufferMemoryAddressAttributes; //!< DW30, SAO Tile Column Buffer Memory Address Attributes 645 SPLITBASEADDRESS64BYTEALIGNED_CMD CurrentMotionVectorTemporalBuffer; //!< DW31..32, Current Motion Vector Temporal Buffer 646 MEMORYADDRESSATTRIBUTES_CMD CurrentMotionVectorTemporalBufferMemoryAddressAttributes; //!< DW33, Current Motion Vector Temporal Buffer Memory Address Attributes 647 union 648 { 649 struct 650 { 651 uint64_t Reserved1088 ; //!< Reserved 652 }; 653 uint32_t Value[2]; 654 } DW34_35; 655 union 656 { 657 struct 658 { 659 uint32_t Reserved1152 ; //!< Reserved 660 }; 661 uint32_t Value; 662 } DW36; 663 SPLITBASEADDRESS64BYTEALIGNED_CMD ReferencePictureBaseAddressRefaddr07[8]; //!< DW37..52, Reference Picture Base Address (RefAddr[0-7]) 664 MEMORYADDRESSATTRIBUTES_CMD ReferencePictureBaseAddressMemoryAddressAttributes; //!< DW53, Reference Picture Base Address Memory Address Attributes 665 SPLITBASEADDRESS64BYTEALIGNED_CMD OriginalUncompressedPictureSource; //!< DW54..55, Original Uncompressed Picture Source 666 MEMORYADDRESSATTRIBUTES_CMD OriginalUncompressedPictureSourceMemoryAddressAttributes; //!< DW56, Original Uncompressed Picture Source Memory Address Attributes 667 SPLITBASEADDRESS64BYTEALIGNED_CMD StreamoutDataDestination; //!< DW57..58, Streamout Data Destination 668 MEMORYADDRESSATTRIBUTES_CMD StreamoutDataDestinationMemoryAddressAttributes; //!< DW59, Streamout Data Destination Memory Address Attributes, Decoder Only 669 SPLITBASEADDRESS64BYTEALIGNED_CMD DecodedPictureStatusErrorBufferBaseAddressOrEncodedSliceSizeStreamoutBaseAddress;//!< DW60..61, Decoded Picture Status/Error Buffer Base Address or Encoded slice size streamout Base Address 670 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureStatusErrorBufferBaseAddressMemoryAddressAttributes; //!< DW62, Decoded Picture Status/Error Buffer Base Address Memory Address Attributes 671 SPLITBASEADDRESS64BYTEALIGNED_CMD LcuIldbStreamoutBuffer; //!< DW63..64, LCU ILDB Streamout Buffer 672 MEMORYADDRESSATTRIBUTES_CMD LcuIldbStreamoutBufferMemoryAddressAttributes; //!< DW65, LCU ILDB Streamout Buffer Memory Address Attributes 673 SPLITBASEADDRESS64BYTEALIGNED_CMD CollocatedMotionVectorTemporalBuffer07[8]; //!< DW66..81, Collocated Motion Vector Temporal Buffer[0-7] 674 MEMORYADDRESSATTRIBUTES_CMD CollocatedMotionVectorTemporalBuffer07MemoryAddressAttributes; //!< DW82, Collocated Motion Vector Temporal Buffer[0-7] Memory Address Attributes 675 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9ProbabilityBufferReadWrite; //!< DW83..84, VP9 Probability Buffer Read/Write 676 MEMORYADDRESSATTRIBUTES_CMD Vp9ProbabilityBufferReadWriteMemoryAddressAttributes; //!< DW85, VP9 Probability Buffer Read/Write Memory Address Attributes 677 union 678 { 679 struct 680 { 681 uint64_t Vp9SegmentIdBufferReadWrite ; //!< VP9 Segment ID Buffer Read/Write 682 }; 683 uint32_t Value[2]; 684 } DW86_87; 685 MEMORYADDRESSATTRIBUTES_CMD Vp9SegmentIdBufferReadWriteMemoryAddressAttributes; //!< DW88, VP9 Segment ID buffer Read/Write Memory Address Attributes 686 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdLineRowstoreBufferReadWrite; //!< DW89..90, VP9 HVD Line Rowstore Buffer Read/Write 687 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdLineRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW91, VP9 HVD Line Rowstore buffer Read/Write Memory Address Attributes 688 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdTileRowstoreBufferReadWrite; //!< DW92..93, VP9 HVD Tile Rowstore Buffer Read/Write 689 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdTileRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW94, VP9 HVD Tile Rowstore buffer Read/Write Memory Address Attributes 690 union 691 { 692 struct 693 { 694 uint64_t SaoRowstoreBufferBaseAddress ; //!< SAO Rowstore Buffer Base Address 695 }; 696 uint32_t Value[2]; 697 } DW95_96; 698 MEMORYADDRESSATTRIBUTES_CMD SaoRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW97, SAO Rowstore Buffer Read/Write Memory Address Attributes 699 SPLITBASEADDRESS64BYTEALIGNED_CMD FrameStatisticsStreamoutDataDestinationBufferBaseAddress; //!< DW98..99, Frame Statistics Streamout Data Destination Buffer Base Address 700 MEMORYADDRESSATTRIBUTES_CMD FrameStatisticsStreamoutDataDestinationBufferAttributesReadWrite; //!< DW100, Frame Statistics Streamout Data Destination buffer (attributes) Read/Write 701 SPLITBASEADDRESS64BYTEALIGNED_CMD SseSourcePixelRowstoreBufferBaseAddress; //!< DW101..102, SSE Source Pixel RowStore Buffer Base Address 702 MEMORYADDRESSATTRIBUTES_CMD SseSourcePixelRowstoreBufferAttributesReadWrite; //!< DW103, SSE Source Pixel RowStore buffer (attributes) Read/Write 703 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySliceStateBufferBaseAddress; //!< DW104..105, HCP Scalability Slice State Buffer Base Address 704 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySliceStateBufferAttributesReadWrite; //!< DW106, HCP Scalability Slice State Buffer (attributes) Read/Write 705 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferBaseAddress; //!< DW107..108, HCP Scalability CABAC Decoded Syntax Elements Buffer Base Address 706 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferAttributesReadWrite; //!< DW109, HCP Scalability CABAC Decoded Syntax Elements Buffer (attributes) Read/Write 707 SPLITBASEADDRESS64BYTEALIGNED_CMD MotionVectorUpperRightColumnStoreBufferBaseAddress; //!< DW110..111, Motion Vector Upper Right Column Store Buffer Base Address 708 MEMORYADDRESSATTRIBUTES_CMD MotionVectorUpperRightColumnStoreBufferAttributesReadWrite; //!< DW112, Motion Vector Upper Right Column Store Buffer (attributes) Read/Write 709 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionUpperRightColumnStoreBufferBaseAddress; //!< DW113..114, Intra Prediction Upper Right Column Store Buffer Base Address 710 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionUpperRightColumnStoreBufferAttributesReadWrite; //!< DW115, Intra Prediction Upper Right Column Store Buffer (attributes) Read/Write 711 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionLeftReconColumnStoreBufferBaseAddress; //!< DW116..117, Intra Prediction Left Recon Column Store Buffer Base Address 712 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionLeftReconColumnStoreBufferAttributesReadWrite; //!< DW118, Intra Prediction Left Recon Column Store Buffer (attributes) Read/Write 713 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferMaxAddress; //!< DW119..120, HCP Scalability CABAC Decoded Syntax Elements Buffer Max Address 714 715 //! \name Local enumerations 716 717 enum MEDIA_INSTRUCTION_COMMAND 718 { 719 MEDIA_INSTRUCTION_COMMAND_HCPPIPEBUFADDRSTATE = 2, //!< No additional details 720 }; 721 722 //! \brief MEDIA_INSTRUCTION_OPCODE 723 //! \details 724 //! Codec/Engine Name = HCP = 7h 725 enum MEDIA_INSTRUCTION_OPCODE 726 { 727 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 728 }; 729 730 enum PIPELINE_TYPE 731 { 732 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 733 }; 734 735 enum COMMAND_TYPE 736 { 737 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 738 }; 739 740 //! \name Initializations 741 742 //! \brief Explicit member initialization function 743 HCP_PIPE_BUF_ADDR_STATE_CMD(); 744 745 static const size_t dwSize = 121; 746 static const size_t byteSize = 484; 747 }; 748 749 //! 750 //! \brief HCP_IND_OBJ_BASE_ADDR_STATE 751 //! \details 752 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 753 //! Commands. Each HCP command has assigned a media instruction command as 754 //! defined in DWord 0, BitField 22:16. 755 //! 756 //! The HCP_IND_OBJ_BASE_ADDR_STATE command is used to define the indirect 757 //! object base address of the stream in graphics memory. This is a frame 758 //! level command. (Is it frame or picture level?) 759 //! This is a picture level state command and is issued in both encoding and 760 //! decoding processes. 761 //! 762 //! Compressed Header Format 763 //! 764 //! 765 //! 766 struct HCP_IND_OBJ_BASE_ADDR_STATE_CMD 767 { 768 union 769 { 770 struct 771 { 772 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 773 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 774 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 775 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 776 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 777 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 778 }; 779 uint32_t Value; 780 } DW0; 781 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectBaseAddress; //!< DW1..2, HCP Indirect Bitstream Object Base Address 782 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectBitstreamObjectMemoryAddressAttributes; //!< DW3, HCP Indirect Bitstream Object Memory Address Attributes 783 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectAccessUpperBound; //!< DW4..5, HCP Indirect Bitstream Object Access Upper Bound 784 union 785 { 786 struct 787 { 788 uint64_t HcpIndirectCuObjectBaseAddress ; //!< HCP Indirect CU Object Base Address 789 }; 790 uint32_t Value[2]; 791 } DW6_7; 792 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectCuObjectObjectMemoryAddressAttributes; //!< DW8, HCP Indirect CU Object Object Memory Address Attributes 793 union 794 { 795 struct 796 { 797 uint64_t HcpPakBseObjectBaseAddress ; //!< HCP PAK-BSE Object Base Address 798 }; 799 uint32_t Value[2]; 800 } DW9_10; 801 MEMORYADDRESSATTRIBUTES_CMD HcpPakBseObjectAddressMemoryAddressAttributes; //!< DW11, HCP PAK-BSE Object Address Memory Address Attributes 802 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpPakBseObjectAccessUpperBound; //!< DW12..13, HCP PAK-BSE Object Access Upper Bound 803 union 804 { 805 struct 806 { 807 uint64_t HcpVp9PakCompressedHeaderSyntaxStreaminBaseAddress ; //!< HCP VP9 PAK Compressed Header Syntax Streamin- Base Address 808 }; 809 uint32_t Value[2]; 810 } DW14_15; 811 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCompressedHeaderSyntaxStreaminMemoryAddressAttributes; //!< DW16, HCP VP9 PAK Compressed Header Syntax StreamIn Memory Address Attributes 812 union 813 { 814 struct 815 { 816 uint64_t HcpVp9PakProbabilityCounterStreamoutBaseAddress ; //!< HCP VP9 PAK Probability Counter StreamOut- Base Address 817 }; 818 uint32_t Value[2]; 819 } DW17_18; 820 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityCounterStreamoutMemoryAddressAttributes; //!< DW19, HCP VP9 PAK Probability Counter StreamOut Memory Address Attributes 821 union 822 { 823 struct 824 { 825 uint64_t HcpVp9PakProbabilityDeltasStreaminBaseAddress ; //!< HCP VP9 PAK Probability Deltas StreamIn- Base Address 826 }; 827 uint32_t Value[2]; 828 } DW20_21; 829 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityDeltasStreaminMemoryAddressAttributes; //!< DW22, HCP VP9 PAK Probability Deltas StreamIn Memory Address Attributes 830 union 831 { 832 struct 833 { 834 uint64_t HcpVp9PakTileRecordStreamoutBaseAddress ; //!< HCP VP9 PAK Tile Record StreamOut- Base Address 835 }; 836 uint32_t Value[2]; 837 } DW23_24; 838 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakTileRecordStreamoutMemoryAddressAttributes; //!< DW25, HCP VP9 PAK Tile Record StreamOut Memory Address Attributes 839 union 840 { 841 struct 842 { 843 uint64_t HcpVp9PakCuLevelStatisticStreamoutBaseAddress ; //!< HCP VP9 PAK CU Level Statistic StreamOut- Base Address 844 }; 845 uint32_t Value[2]; 846 } DW26_27; 847 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCuLevelStatisticStreamoutMemoryAddressAttributes; //!< DW28, HCP VP9 PAK CU Level Statistic StreamOut Memory Address Attributes 848 849 //! \name Local enumerations 850 851 enum MEDIA_INSTRUCTION_COMMAND 852 { 853 MEDIA_INSTRUCTION_COMMAND_HCPINDOBJBASEADDRSTATE = 3, //!< No additional details 854 }; 855 856 //! \brief MEDIA_INSTRUCTION_OPCODE 857 //! \details 858 //! Codec/Engine Name = HCP = 7h 859 enum MEDIA_INSTRUCTION_OPCODE 860 { 861 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 862 }; 863 864 enum PIPELINE_TYPE 865 { 866 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 867 }; 868 869 enum COMMAND_TYPE 870 { 871 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 872 }; 873 874 //! \name Initializations 875 876 //! \brief Explicit member initialization function 877 HCP_IND_OBJ_BASE_ADDR_STATE_CMD(); 878 879 static const size_t dwSize = 29; 880 static const size_t byteSize = 116; 881 }; 882 883 //! 884 //! \brief HCP_QM_STATE 885 //! \details 886 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 887 //! Commands. Each HCP command has assigned a media instruction command as 888 //! defined in DWord 0, BitField 22:16. 889 //! 890 //! The HCP_QM_STATE command loads the custom HEVC quantization tables into 891 //! local RAM and may be issued up to 20 times: 3x Colour Component plus 2x 892 //! intra/inter plus 4x SizeID minus 4 for the 32x32 chroma components. When 893 //! the scaling_list_enable_flag is set to disable, the scaling matrix is 894 //! still sent to the decoder, and with all entries programmed to the same 895 //! value = 16. This is a picture level state command and is issued in both 896 //! encoding and decoding processes. 897 //! 898 //! Dwords 2-17 form a table for the DCT coefficients, 4 8-bit 899 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-5. 900 //! Size 8x8 for SizeID1/2/3, DWords 2-17. 901 //! 902 //! 903 //! SizeID 0 (Table 4-10) 904 //! 905 struct HCP_QM_STATE_CMD 906 { 907 union 908 { 909 struct 910 { 911 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 912 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 913 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 914 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 915 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 916 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 917 }; 918 uint32_t Value; 919 } DW0; 920 union 921 { 922 struct 923 { 924 uint32_t PredictionType : __CODEGEN_BITFIELD( 0, 0) ; //!< PREDICTION_TYPE 925 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 926 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 927 uint32_t DcCoefficient : __CODEGEN_BITFIELD( 5, 12) ; //!< DC Coefficient 928 uint32_t Reserved45 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 929 }; 930 uint32_t Value; 931 } DW1; 932 uint32_t Quantizermatrix[16]; //!< QuantizerMatrix 933 934 //! \name Local enumerations 935 936 enum MEDIA_INSTRUCTION_COMMAND 937 { 938 MEDIA_INSTRUCTION_COMMAND_HCPQMSTATE = 4, //!< No additional details 939 }; 940 941 //! \brief MEDIA_INSTRUCTION_OPCODE 942 //! \details 943 //! Codec/Engine Name = HCP = 7h 944 enum MEDIA_INSTRUCTION_OPCODE 945 { 946 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 947 }; 948 949 enum PIPELINE_TYPE 950 { 951 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 952 }; 953 954 enum COMMAND_TYPE 955 { 956 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 957 }; 958 959 enum PREDICTION_TYPE 960 { 961 PREDICTION_TYPE_INTRA = 0, //!< No additional details 962 PREDICTION_TYPE_INTER = 1, //!< No additional details 963 }; 964 965 enum SIZEID 966 { 967 SIZEID_4X4 = 0, //!< No additional details 968 SIZEID_8X8 = 1, //!< No additional details 969 SIZEID_16X16 = 2, //!< No additional details 970 SIZEID_32X32 = 3, //!< (Illegal Value for Colour Component Chroma Cr and Cb.) 971 }; 972 973 //! \brief COLOR_COMPONENT 974 //! \details 975 //! Encoder: When RDOQ is enabled, scaling list for all 3 color components 976 //! must be same. So this field is set to always 0. 977 enum COLOR_COMPONENT 978 { 979 COLOR_COMPONENT_LUMA = 0, //!< No additional details 980 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 981 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 982 }; 983 984 //! \name Initializations 985 986 //! \brief Explicit member initialization function 987 HCP_QM_STATE_CMD(); 988 989 static const size_t dwSize = 18; 990 static const size_t byteSize = 72; 991 }; 992 993 //! 994 //! \brief HCP_PIC_STATE 995 //! \details 996 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 997 //! Commands. Each HCP command has assigned a media instruction command as 998 //! defined in DWord 0, BitField 22:16. 999 //! 1000 //! This is a picture level command and is issued only once per workload for 1001 //! both encoding and decoding processes. 1002 //! 1003 struct HCP_PIC_STATE_CMD 1004 { 1005 union 1006 { 1007 struct 1008 { 1009 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1010 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1011 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1012 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1013 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1014 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1015 }; 1016 uint32_t Value; 1017 } DW0; 1018 union 1019 { 1020 struct 1021 { 1022 uint32_t Framewidthinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< FrameWidthInMinCbMinus1 1023 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 14) ; //!< Reserved 1024 uint32_t PakTransformSkipEnable : __CODEGEN_BITFIELD(15, 15) ; //!< PAK Transform Skip Enable 1025 uint32_t Frameheightinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< FrameHeightInMinCbMinus1 1026 uint32_t Reserved59 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1027 }; 1028 uint32_t Value; 1029 } DW1; 1030 union 1031 { 1032 struct 1033 { 1034 uint32_t Mincusize : __CODEGEN_BITFIELD( 0, 1) ; //!< MINCUSIZE 1035 uint32_t CtbsizeLcusize : __CODEGEN_BITFIELD( 2, 3) ; //!< CTBSIZE_LCUSIZE 1036 uint32_t Mintusize : __CODEGEN_BITFIELD( 4, 5) ; //!< MINTUSIZE 1037 uint32_t Maxtusize : __CODEGEN_BITFIELD( 6, 7) ; //!< MAXTUSIZE 1038 uint32_t Minpcmsize : __CODEGEN_BITFIELD( 8, 9) ; //!< MINPCMSIZE 1039 uint32_t Maxpcmsize : __CODEGEN_BITFIELD(10, 11) ; //!< MAXPCMSIZE 1040 uint32_t Log2SaoOffsetScaleLuma : __CODEGEN_BITFIELD(12, 14) ; //!< LOG2_SAO_OFFSET_SCALE_LUMA 1041 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1042 uint32_t Log2SaoOffsetScaleChroma : __CODEGEN_BITFIELD(16, 18) ; //!< LOG2_SAO_OFFSET_SCALE_CHROMA 1043 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 1044 uint32_t ChromaQpOffsetListLenMinus1 : __CODEGEN_BITFIELD(20, 22) ; //!< chroma_qp_offset_list_len_minus1 1045 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 1046 uint32_t DiffCuChromaQpOffsetDepth : __CODEGEN_BITFIELD(24, 27) ; //!< diff_cu_chroma_qp_offset_depth 1047 uint32_t ChromaQpOffsetListEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< chroma_qp_offset_list_enabled_flag 1048 uint32_t ChromaSubsampling : __CODEGEN_BITFIELD(29, 31) ; //!< CHROMA_SUBSAMPLING 1049 }; 1050 uint32_t Value; 1051 } DW2; 1052 union 1053 { 1054 struct 1055 { 1056 uint32_t Colpicisi : __CODEGEN_BITFIELD( 0, 0) ; //!< COLPICISI 1057 uint32_t Curpicisi : __CODEGEN_BITFIELD( 1, 1) ; //!< CURPICISI 1058 uint32_t Inserttestflag : __CODEGEN_BITFIELD( 2, 2) ; //!< INSERTTESTFLAG 1059 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1060 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 1061 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame number 1062 uint32_t Reserved114 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 1063 uint32_t HighPrecisionOffsetsEnableFlag : __CODEGEN_BITFIELD(19, 19) ; //!< High Precision Offsets Enable Flag 1064 uint32_t Log2Maxtransformskipsize : __CODEGEN_BITFIELD(20, 22) ; //!< Log2MaxTransformSkipSize 1065 uint32_t CrossComponentPredictionEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cross_component_prediction_enabled_flag 1066 uint32_t CabacBypassAlignmentEnabledFlag : __CODEGEN_BITFIELD(24, 24) ; //!< cabac_bypass_alignment_enabled_flag 1067 uint32_t PersistentRiceAdaptationEnabledFlag : __CODEGEN_BITFIELD(25, 25) ; //!< persistent_rice_adaptation_enabled_flag 1068 uint32_t IntraSmoothingDisabledFlag : __CODEGEN_BITFIELD(26, 26) ; //!< intra_smoothing_disabled_flag 1069 uint32_t ExplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< explicit_rdpcm_enabled_flag 1070 uint32_t ImplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< implicit_rdpcm_enabled_flag 1071 uint32_t TransformSkipContextEnabledFlag : __CODEGEN_BITFIELD(29, 29) ; //!< transform_skip_context_enabled_flag 1072 uint32_t TransformSkipRotationEnabledFlag : __CODEGEN_BITFIELD(30, 30) ; //!< transform_skip_rotation_enabled_flag 1073 uint32_t SpsRangeExtensionEnableFlag : __CODEGEN_BITFIELD(31, 31) ; //!< sps_range_extension_enable_flag 1074 }; 1075 uint32_t Value; 1076 } DW3; 1077 union 1078 { 1079 struct 1080 { 1081 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1082 uint32_t SampleAdaptiveOffsetEnabledFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< sample_adaptive_offset_enabled_flag 1083 uint32_t PcmEnabledFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< pcm_enabled_flag 1084 uint32_t CuQpDeltaEnabledFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< CU_QP_DELTA_ENABLED_FLAG 1085 uint32_t DiffCuQpDeltaDepthOrNamedAsMaxDqpDepth : __CODEGEN_BITFIELD( 6, 7) ; //!< diff_cu_qp_delta_depth (or named as max_dqp_depth) 1086 uint32_t PcmLoopFilterDisableFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< pcm_loop_filter_disable_flag 1087 uint32_t ConstrainedIntraPredFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< constrained_intra_pred_flag 1088 uint32_t Log2ParallelMergeLevelMinus2 : __CODEGEN_BITFIELD(10, 12) ; //!< log2_parallel_merge_level_minus2 1089 uint32_t SignDataHidingFlag : __CODEGEN_BITFIELD(13, 13) ; //!< SIGN_DATA_HIDING_FLAG 1090 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 1091 uint32_t LoopFilterAcrossTilesEnabledFlag : __CODEGEN_BITFIELD(15, 15) ; //!< loop_filter_across_tiles_enabled_flag 1092 uint32_t EntropyCodingSyncEnabledFlag : __CODEGEN_BITFIELD(16, 16) ; //!< entropy_coding_sync_enabled_flag 1093 uint32_t TilesEnabledFlag : __CODEGEN_BITFIELD(17, 17) ; //!< tiles_enabled_flag 1094 uint32_t WeightedBipredFlag : __CODEGEN_BITFIELD(18, 18) ; //!< weighted_bipred_flag 1095 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(19, 19) ; //!< weighted_pred_flag 1096 uint32_t Fieldpic : __CODEGEN_BITFIELD(20, 20) ; //!< FIELDPIC 1097 uint32_t Bottomfield : __CODEGEN_BITFIELD(21, 21) ; //!< BOTTOMFIELD 1098 uint32_t TransformSkipEnabledFlag : __CODEGEN_BITFIELD(22, 22) ; //!< TRANSFORM_SKIP_ENABLED_FLAG 1099 uint32_t AmpEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< AMP_ENABLED_FLAG 1100 uint32_t Reserved152 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 1101 uint32_t TransquantBypassEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< TRANSQUANT_BYPASS_ENABLE_FLAG 1102 uint32_t StrongIntraSmoothingEnableFlag : __CODEGEN_BITFIELD(26, 26) ; //!< strong_intra_smoothing_enable_flag 1103 uint32_t CuPacketStructure : __CODEGEN_BITFIELD(27, 27) ; //!< CU packet structure 1104 uint32_t Reserved156 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1105 }; 1106 uint32_t Value; 1107 } DW4; 1108 union 1109 { 1110 struct 1111 { 1112 uint32_t PicCbQpOffset : __CODEGEN_BITFIELD( 0, 4) ; //!< pic_cb_qp_offset 1113 uint32_t PicCrQpOffset : __CODEGEN_BITFIELD( 5, 9) ; //!< pic_cr_qp_offset 1114 uint32_t MaxTransformHierarchyDepthIntraOrNamedAsTuMaxDepthIntra : __CODEGEN_BITFIELD(10, 12) ; //!< max_transform_hierarchy_depth_intra (or named as tu_max_depth_intra) 1115 uint32_t MaxTransformHierarchyDepthInterOrNamedAsTuMaxDepthInter : __CODEGEN_BITFIELD(13, 15) ; //!< max_transform_hierarchy_depth_inter(or named as tu_max_depth_inter) 1116 uint32_t PcmSampleBitDepthChromaMinus1 : __CODEGEN_BITFIELD(16, 19) ; //!< pcm_sample_bit_depth_chroma_minus1 1117 uint32_t PcmSampleBitDepthLumaMinus1 : __CODEGEN_BITFIELD(20, 23) ; //!< pcm_sample_bit_depth_luma_minus1 1118 uint32_t BitDepthChromaMinus8 : __CODEGEN_BITFIELD(24, 26) ; //!< BIT_DEPTH_CHROMA_MINUS8 1119 uint32_t BitDepthLumaMinus8 : __CODEGEN_BITFIELD(27, 29) ; //!< BIT_DEPTH_LUMA_MINUS8 1120 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1121 }; 1122 uint32_t Value; 1123 } DW5; 1124 union 1125 { 1126 struct 1127 { 1128 uint32_t LcuMaxBitsizeAllowed : __CODEGEN_BITFIELD( 0, 15) ; //!< LCU Max BitSize Allowed 1129 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NonFirstPassFlag 1130 uint32_t Reserved209 : __CODEGEN_BITFIELD(17, 23) ; //!< Reserved 1131 uint32_t LcumaxbitstatusenLcumaxsizereportmask : __CODEGEN_BITFIELD(24, 24) ; //!< LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1132 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1133 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1134 uint32_t Reserved219 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 1135 uint32_t LoadSlicePointerFlag : __CODEGEN_BITFIELD(29, 29) ; //!< LOAD_SLICE_POINTER_FLAG 1136 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1137 }; 1138 uint32_t Value; 1139 } DW6; 1140 union 1141 { 1142 struct 1143 { 1144 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 1145 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1146 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 1147 }; 1148 uint32_t Value; 1149 } DW7; 1150 union 1151 { 1152 struct 1153 { 1154 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1155 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1156 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 1157 }; 1158 uint32_t Value; 1159 } DW8; 1160 union 1161 { 1162 struct 1163 { 1164 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FRAMEBITRATEMINDELTA 1165 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1166 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1167 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1168 }; 1169 uint32_t Value; 1170 } DW9; 1171 union 1172 { 1173 struct 1174 { 1175 uint64_t Framedeltaqpmax ; //!< FrameDeltaQpMax 1176 }; 1177 uint32_t Value[2]; 1178 } DW10_11; 1179 union 1180 { 1181 struct 1182 { 1183 uint64_t Framedeltaqpmin ; //!< FrameDeltaQpMin 1184 }; 1185 uint32_t Value[2]; 1186 } DW12_13; 1187 union 1188 { 1189 struct 1190 { 1191 uint64_t Framedeltaqpmaxrange ; //!< FrameDeltaQpMaxRange 1192 }; 1193 uint32_t Value[2]; 1194 } DW14_15; 1195 union 1196 { 1197 struct 1198 { 1199 uint64_t Framedeltaqpminrange ; //!< FrameDeltaQpMinRange 1200 }; 1201 uint32_t Value[2]; 1202 } DW16_17; 1203 union 1204 { 1205 struct 1206 { 1207 uint32_t Minframesize : __CODEGEN_BITFIELD( 0, 15) ; //!< MINFRAMESIZE 1208 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 1209 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 1210 }; 1211 uint32_t Value; 1212 } DW18; 1213 union 1214 { 1215 struct 1216 { 1217 uint32_t FractionalQpInput : __CODEGEN_BITFIELD( 0, 2) ; //!< Fractional QP Input 1218 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD( 3, 5) ; //!< Fractional QP Offset 1219 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RhoDomain Rate Control Enable 1220 uint32_t FractionalQpAdjustmentEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Fractional QP adjustment enable 1221 uint32_t Rhodomainframelevelqp : __CODEGEN_BITFIELD( 8, 13) ; //!< RhoDomainFrameLevelQP 1222 uint32_t PakDynamicSliceModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< PAK Dynamic Slice Mode Enable 1223 uint32_t NoOutputOfPriorPicsFlag : __CODEGEN_BITFIELD(15, 15) ; //!< no_output_of_prior_pics_flag 1224 uint32_t FirstSliceSegmentInPicFlag : __CODEGEN_BITFIELD(16, 16) ; //!< first_slice_segment_in_pic_flag 1225 uint32_t Nalunittypeflag : __CODEGEN_BITFIELD(17, 17) ; //!< NalUnitTypeFlag 1226 uint32_t SlicePicParameterSetId : __CODEGEN_BITFIELD(18, 23) ; //!< slice_pic_parameter_set_id 1227 uint32_t SseEnable : __CODEGEN_BITFIELD(24, 24) ; //!< SSE Enable 1228 uint32_t RdoqEnable : __CODEGEN_BITFIELD(25, 25) ; //!< RDOQ Enable 1229 uint32_t NumberoflcusinnormalSliceSizeConformanceMode : __CODEGEN_BITFIELD(26, 27) ; //!< NumberOfLCUsInNormal Slice size conformance Mode 1230 uint32_t Reserved636 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 1231 uint32_t PartialFrameUpdateMode : __CODEGEN_BITFIELD(30, 30) ; //!< Partial Frame Update Mode 1232 uint32_t TemporalMvPredDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Temporal MV pred disable 1233 }; 1234 uint32_t Value; 1235 } DW19; 1236 union 1237 { 1238 struct 1239 { 1240 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1241 uint32_t Intratucountbasedrdoqdisable : __CODEGEN_BITFIELD( 6, 6) ; //!< IntraTuCountBasedRDOQdisable 1242 uint32_t Reserved647 : __CODEGEN_BITFIELD( 7, 31) ; //!< Reserved 1243 }; 1244 uint32_t Value; 1245 } DW20; 1246 union 1247 { 1248 struct 1249 { 1250 uint32_t SliceSizeThresholdInBytes ; //!< Slice Size Threshold in Bytes 1251 }; 1252 uint32_t Value; 1253 } DW21; 1254 union 1255 { 1256 struct 1257 { 1258 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 1259 }; 1260 uint32_t Value; 1261 } DW22; 1262 union 1263 { 1264 struct 1265 { 1266 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 1267 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 1268 }; 1269 uint32_t Value; 1270 } DW23; 1271 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 1272 union 1273 { 1274 struct 1275 { 1276 uint32_t CbQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cb_qp_offset_list[0] 1277 uint32_t CbQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cb_qp_offset_list[1] 1278 uint32_t CbQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cb_qp_offset_list[2] 1279 uint32_t CbQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cb_qp_offset_list[3] 1280 uint32_t CbQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cb_qp_offset_list[4] 1281 uint32_t CbQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cb_qp_offset_list[5] 1282 uint32_t Reserved1054 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1283 }; 1284 uint32_t Value; 1285 } DW32; 1286 union 1287 { 1288 struct 1289 { 1290 uint32_t CrQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cr_qp_offset_list[0] 1291 uint32_t CrQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cr_qp_offset_list[1] 1292 uint32_t CrQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cr_qp_offset_list[2] 1293 uint32_t CrQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cr_qp_offset_list[3] 1294 uint32_t CrQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cr_qp_offset_list[4] 1295 uint32_t CrQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cr_qp_offset_list[5] 1296 uint32_t Reserved1086 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1297 }; 1298 uint32_t Value; 1299 } DW33; 1300 union 1301 { 1302 struct 1303 { 1304 uint32_t IbcMotionCompensationBufferReferenceIdc : __CODEGEN_BITFIELD( 0, 2) ; //!< IBC Motion Compensation Buffer Reference IDC 1305 uint32_t Reserved1091 : __CODEGEN_BITFIELD( 3, 5) ; //!< Reserved 1306 uint32_t DeblockingFilterOverrideEnabledFlag : __CODEGEN_BITFIELD( 6, 6) ; //!< deblocking_filter_override_enabled_flag 1307 uint32_t PpsDeblockingFilterDisabledFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< pps_deblocking_filter_disabled_flag 1308 uint32_t PpsActCrQpOffsetPlus3 : __CODEGEN_BITFIELD( 8, 13) ; //!< pps_act_cr_qp_offset_plus3 1309 uint32_t PpsActCbQpOffsetPlus5 : __CODEGEN_BITFIELD(14, 19) ; //!< pps_act_cb_qp_offset_plus5 1310 uint32_t PpsActYOffsetPlus5 : __CODEGEN_BITFIELD(20, 25) ; //!< pps_act_y_offset_plus5 1311 uint32_t PpsSliceActQpOffsetsPresentFlag : __CODEGEN_BITFIELD(26, 26) ; //!< pps_slice_act_qp_offsets_present_flag 1312 uint32_t ResidualAdaptiveColourTransformEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< residual_adaptive_colour_transform_enabled_flag 1313 uint32_t PpsCurrPicRefEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< pps_curr_pic_ref_enabled_flag 1314 uint32_t MotionVectorResolutionControlIdc : __CODEGEN_BITFIELD(29, 30) ; //!< MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1315 uint32_t IntraBoundaryFilteringDisabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< intra_boundary_filtering_disabled_flag 1316 }; 1317 uint32_t Value; 1318 } DW34; 1319 union 1320 { 1321 struct 1322 { 1323 uint32_t PaletteMaxSize : __CODEGEN_BITFIELD( 0, 6) ; //!< palette_max_size 1324 uint32_t Reserved1127 : __CODEGEN_BITFIELD( 7, 9) ; //!< Reserved 1325 uint32_t DeltaPaletteMaxPredictorSize : __CODEGEN_BITFIELD(10, 16) ; //!< delta_palette_max_predictor_size 1326 uint32_t Reserved1137 : __CODEGEN_BITFIELD(17, 18) ; //!< Reserved 1327 uint32_t IbcMotionVectorErrorHandlingDisable : __CODEGEN_BITFIELD(19, 19) ; //!< IBC Motion Vector Error Handling Disable 1328 uint32_t ChromaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(20, 23) ; //!< chroma_bit_depth_entry_minus8 1329 uint32_t LumaBitDepthEntryMinus8 : __CODEGEN_BITFIELD(24, 27) ; //!< luma_bit_depth_entry_minus8 1330 uint32_t IbcConfiguration : __CODEGEN_BITFIELD(28, 29) ; //!< IBC_CONFIGURATION 1331 uint32_t MonochromePaletteFlag : __CODEGEN_BITFIELD(30, 30) ; //!< monochrome_palette_flag 1332 uint32_t PaletteModeEnabledFlag : __CODEGEN_BITFIELD(31, 31) ; //!< palette_mode_enabled_flag 1333 }; 1334 uint32_t Value; 1335 } DW35; 1336 union 1337 { 1338 struct 1339 { 1340 uint32_t EnableFpakMessaging : __CODEGEN_BITFIELD( 0, 0) ; //!< Enable FPAK Messaging 1341 uint32_t Reserved1153 : __CODEGEN_BITFIELD( 1, 29) ; //!< Reserved 1342 uint32_t FrameCrcType : __CODEGEN_BITFIELD(30, 30) ; //!< FRAME_CRC_TYPE 1343 uint32_t FrameCrcEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Frame CRC Enable 1344 }; 1345 uint32_t Value; 1346 } DW36; 1347 union 1348 { 1349 struct 1350 { 1351 uint32_t Rdoqintratuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntraTUThreshold 1352 uint32_t Reserved1200 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1353 }; 1354 uint32_t Value; 1355 } DW37; 1356 union 1357 { 1358 struct 1359 { 1360 uint32_t Rdoqintra16X16Tuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntra16x16TUThreshold 1361 uint32_t Rdoqintra32X32Tuthreshold : __CODEGEN_BITFIELD(16, 31) ; //!< RDOQIntra32x32TUThreshold 1362 }; 1363 uint32_t Value; 1364 } DW38; 1365 union 1366 { 1367 struct 1368 { 1369 uint64_t SsethresholdsForClass910 ; //!< SSEThresholds for Class9 ..10 1370 }; 1371 uint32_t Value[2]; 1372 } DW39_40; 1373 1374 //! \name Local enumerations 1375 1376 enum MEDIA_INSTRUCTION_COMMAND 1377 { 1378 MEDIA_INSTRUCTION_COMMAND_HCPPICSTATE = 16, //!< No additional details 1379 }; 1380 1381 //! \brief MEDIA_INSTRUCTION_OPCODE 1382 //! \details 1383 //! Codec/Engine Name = HCP = 7h 1384 enum MEDIA_INSTRUCTION_OPCODE 1385 { 1386 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1387 }; 1388 1389 enum PIPELINE_TYPE 1390 { 1391 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1392 }; 1393 1394 enum COMMAND_TYPE 1395 { 1396 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1397 }; 1398 1399 //! \brief MINCUSIZE 1400 //! \details 1401 //! Specifies the smallest coding block size. 1402 enum MINCUSIZE 1403 { 1404 MINCUSIZE_8X8 = 0, //!< No additional details 1405 MINCUSIZE_16X16 = 1, //!< No additional details 1406 MINCUSIZE_32X32 = 2, //!< No additional details 1407 MINCUSIZE_64X64 = 3, //!< No additional details 1408 }; 1409 1410 //! \brief CTBSIZE_LCUSIZE 1411 //! \details 1412 //! Specifies the coding tree block size. 1413 enum CTBSIZE_LCUSIZE 1414 { 1415 CTBSIZE_LCUSIZE_ILLEGALRESERVED = 0, //!< No additional details 1416 CTBSIZE_LCUSIZE_16X16 = 1, //!< No additional details 1417 CTBSIZE_LCUSIZE_32X32 = 2, //!< No additional details 1418 CTBSIZE_LCUSIZE_64X64 = 3, //!< No additional details 1419 }; 1420 1421 //! \brief MINTUSIZE 1422 //! \details 1423 //! Specifies the smallest allowed transform block size. 1424 enum MINTUSIZE 1425 { 1426 MINTUSIZE_4X4 = 0, //!< No additional details 1427 MINTUSIZE_8X8 = 1, //!< No additional details 1428 MINTUSIZE_16X16 = 2, //!< No additional details 1429 MINTUSIZE_32X32 = 3, //!< No additional details 1430 }; 1431 1432 //! \brief MAXTUSIZE 1433 //! \details 1434 //! Specifies the largest allowed transform block size. 1435 enum MAXTUSIZE 1436 { 1437 MAXTUSIZE_4X4 = 0, //!< No additional details 1438 MAXTUSIZE_8X8 = 1, //!< No additional details 1439 MAXTUSIZE_16X16 = 2, //!< No additional details 1440 MAXTUSIZE_32X32 = 3, //!< No additional details 1441 }; 1442 1443 //! \brief MINPCMSIZE 1444 //! \details 1445 //! Specifies the smallest allowed PCM coding block size. 1446 enum MINPCMSIZE 1447 { 1448 MINPCMSIZE_8X8 = 0, //!< No additional details 1449 MINPCMSIZE_16X16 = 1, //!< No additional details 1450 MINPCMSIZE_32X32 = 2, //!< No additional details 1451 }; 1452 1453 //! \brief MAXPCMSIZE 1454 //! \details 1455 //! Specifies the largest allowed PCM coding block size. 1456 enum MAXPCMSIZE 1457 { 1458 MAXPCMSIZE_8X8 = 0, //!< No additional details 1459 MAXPCMSIZE_16X16 = 1, //!< No additional details 1460 MAXPCMSIZE_32X32 = 2, //!< No additional details 1461 }; 1462 1463 //! \brief LOG2_SAO_OFFSET_SCALE_LUMA 1464 //! \details 1465 //! <p>To scale SAO offset values for luma samples</p> 1466 //! <p>0 to Max(0,BitDepth<sub><font size="2">C</font></sub>−10)</p> 1467 //! <p>Default = 0</p> 1468 enum LOG2_SAO_OFFSET_SCALE_LUMA 1469 { 1470 LOG2_SAO_OFFSET_SCALE_LUMA_0 = 0, //!< No additional details 1471 LOG2_SAO_OFFSET_SCALE_LUMA_1 = 1, //!< No additional details 1472 LOG2_SAO_OFFSET_SCALE_LUMA_2 = 2, //!< No additional details 1473 }; 1474 1475 //! \brief LOG2_SAO_OFFSET_SCALE_CHROMA 1476 //! \details 1477 //! <p>To scale SAO offset values for chroma samples.</p> 1478 //! <p>0 to Max(0,BitDepth<sub>C</sub>−10)</p> 1479 //! <p>default = 0</p> 1480 //! <p>Decoder Only</p> 1481 enum LOG2_SAO_OFFSET_SCALE_CHROMA 1482 { 1483 LOG2_SAO_OFFSET_SCALE_CHROMA_0 = 0, //!< No additional details 1484 LOG2_SAO_OFFSET_SCALE_CHROMA_1 = 1, //!< No additional details 1485 LOG2_SAO_OFFSET_SCALE_CHROMA_2 = 2, //!< No additional details 1486 }; 1487 1488 //! \brief CHROMA_SUBSAMPLING 1489 //! \details 1490 //! <p>Specify the chroma subsampling of the current bitstream to be decoded 1491 //! or encoded.</p> 1492 //! <p>000 (0h) - Reserved (This setting is reserved for Monochrome 1493 //! setting--currently not suppported)</p> 1494 //! <p>001 (1h) - 4:2:0</p> 1495 //! <p>010 (2h) - 4:2:2</p> 1496 //! <p>011 (3h) - 4:4:4</p> 1497 //! <p>All other values are invalid for both encoder and decoder.</p> 1498 enum CHROMA_SUBSAMPLING 1499 { 1500 CHROMA_SUBSAMPLING_420 = 1, //!< No additional details 1501 CHROMA_SUBSAMPLING_422 = 2, //!< No additional details 1502 CHROMA_SUBSAMPLING_444 = 3, //!< No additional details 1503 }; 1504 1505 //! \brief COLPICISI 1506 //! \details 1507 //! Specifies that the collocated picture is comprised solely of I slices 1508 //! and that there are no P or B slices in the picture. 1509 enum COLPICISI 1510 { 1511 COLPICISI_COLLOCATEDPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1512 }; 1513 1514 //! \brief CURPICISI 1515 //! \details 1516 //! Specifies that the current picture is comprised solely of I slices and 1517 //! that there are no P or B slices in the picture. 1518 enum CURPICISI 1519 { 1520 CURPICISI_CURRENTPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1521 }; 1522 1523 //! \brief INSERTTESTFLAG 1524 //! \details 1525 //! <p>CABAC 0 Word Insertion Test Enable (Encoder Only)This bit will modify 1526 //! CABAC K equation so that a positive K value can be generated easily. 1527 //! This is done for validation purpose only. In normal usage this bit 1528 //! should be set to 0.</p> 1529 //! <p>Regular equation for generating 'K' value when CABAC 0 Word Insertion 1530 //! Test Enable is set to 0.</p> 1531 //! <pre>K = {[((96 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs *3) 1532 //! + 1023) / 1024] - bytes_in_picture} / 3</pre> 1533 //! 1534 //! <p>Modified equation when CABAC 0 Word Insertion Test Enable bit set to 1535 //! 1.</p> 1536 //! 1537 //! <pre>K = {[((1536 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs 1538 //! *3) + 1023) / 1024] - bytes_in_picture} / 3</pre> 1539 //! 1540 //! <p>Encoder only feature.</p> 1541 enum INSERTTESTFLAG 1542 { 1543 INSERTTESTFLAG_UNNAMED0 = 0, //!< No additional details 1544 INSERTTESTFLAG_UNNAMED1 = 1, //!< No additional details 1545 }; 1546 1547 //! \brief CU_QP_DELTA_ENABLED_FLAG 1548 //! \details 1549 //! <p>cu_qp_delta_enabled_flag = 1 and Max_DQP_Level = 0 or 3 is supported 1550 //! for PAK standalone andVDEnc modes.</p> 1551 enum CU_QP_DELTA_ENABLED_FLAG 1552 { 1553 CU_QP_DELTA_ENABLED_FLAG_DISABLE = 0, //!< Does not allow QP change at CU or LCU level, the same QP is used for the entire slice. Max_DQP_Level = 0 (i.e. diff_cu_qp_delta_depath = 0). 1554 CU_QP_DELTA_ENABLED_FLAG_ENABLE = 1, //!< Allow QP change at CU level. MAX_DQP_level can be >0. 1555 }; 1556 1557 //! \brief SIGN_DATA_HIDING_FLAG 1558 //! \details 1559 //! Currently not supported in encoder, so must be set to 0 for encoding 1560 //! session. 1561 enum SIGN_DATA_HIDING_FLAG 1562 { 1563 SIGN_DATA_HIDING_FLAG_DISABLE = 0, //!< Specifies that sign bit hiding is disabled. 1564 SIGN_DATA_HIDING_FLAG_ENABLE = 1, //!< Specifies that sign bit hiding is enabled. 1565 }; 1566 1567 //! \brief FIELDPIC 1568 //! \details 1569 //! <p>Must be zero for encoder only.</p> 1570 enum FIELDPIC 1571 { 1572 FIELDPIC_VIDEOFRAME = 0, //!< No additional details 1573 FIELDPIC_VIDEOFIELD = 1, //!< No additional details 1574 }; 1575 1576 //! \brief BOTTOMFIELD 1577 //! \details 1578 //! <p>Must be zero for encoder only</p> 1579 enum BOTTOMFIELD 1580 { 1581 BOTTOMFIELD_BOTTOMFIELD = 0, //!< No additional details 1582 BOTTOMFIELD_TOPFIELD = 1, //!< No additional details 1583 }; 1584 1585 enum TRANSFORM_SKIP_ENABLED_FLAG 1586 { 1587 TRANSFORM_SKIP_ENABLED_FLAG_DISABLE = 0, //!< transform_skip_flag is not supported in the residual coding 1588 TRANSFORM_SKIP_ENABLED_FLAG_ENABLE = 1, //!< transform_skip_flag is supported 1589 }; 1590 1591 //! \brief AMP_ENABLED_FLAG 1592 //! \details 1593 //! In VDENC mode, this bit should be set to 1. 1594 enum AMP_ENABLED_FLAG 1595 { 1596 AMP_ENABLED_FLAG_DISABLE = 0, //!< Asymmetric motion partitions cannot be used in coding tree blocks. 1597 AMP_ENABLED_FLAG_ENABLE = 1, //!< Support asymmetric motion partitions, i.e. PartMode equal to PART_2NxnU, PART_2NxnD, PART_nLx2N, or PART_nRx2N. 1598 }; 1599 1600 enum TRANSQUANT_BYPASS_ENABLE_FLAG 1601 { 1602 TRANSQUANT_BYPASS_ENABLE_FLAG_DISABLE = 0, //!< cu_transquant_bypass is not supported 1603 TRANSQUANT_BYPASS_ENABLE_FLAG_ENABLE = 1, //!< cu_transquant_bypass is supported 1604 }; 1605 1606 //! \brief BIT_DEPTH_CHROMA_MINUS8 1607 //! \details 1608 //! This specifies the number of bit allow for Chroma pixels. In 8 bit mode, 1609 //! this must be set to 0. Encoder: Supports bit depths 8, 10 and 12 only. 1610 //! And also it must be same as Luma. Encoder: Does not support 10 or 12 bit 1611 //! Source Pixels and 8bit PAK. i.e. The source pixel depth should be less 1612 //! than or equal to the PAK bit depth. 1613 enum BIT_DEPTH_CHROMA_MINUS8 1614 { 1615 BIT_DEPTH_CHROMA_MINUS8_CHROMA8BIT = 0, //!< No additional details 1616 BIT_DEPTH_CHROMA_MINUS8_CHROMA9BIT = 1, //!< Only HEVC decoder supports 9 bits chroma.HEVC encoder does not supports 9 bits chroma. 1617 BIT_DEPTH_CHROMA_MINUS8_CHROMA10BIT = 2, //!< No additional details 1618 BIT_DEPTH_CHROMA_MINUS8_CHROMA11BIT = 3, //!< HEVC SCC does not support 11 bits chromaAlso only HEVC decoder (non-SCC) support 11 bits chromaHEVC encoder (non-SCC) does not support 11 bits chroma 1619 BIT_DEPTH_CHROMA_MINUS8_CHROMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1620 }; 1621 1622 //! \brief BIT_DEPTH_LUMA_MINUS8 1623 //! \details 1624 //! This specifies the number of bit allow for Luma pixels. In 8 bit mode, 1625 //! this must be set to 0. Encoder: Suports bit depths 8, 10 and 12 only. 1626 //! Encoder: Does not support 10 or 12 bit Source Pixels and 8bit PAK i.e. 1627 //! the source pixel depth should be less than or equal to PAK bit depth. 1628 enum BIT_DEPTH_LUMA_MINUS8 1629 { 1630 BIT_DEPTH_LUMA_MINUS8_LUMA8BIT = 0, //!< No additional details 1631 BIT_DEPTH_LUMA_MINUS8_LUMA9BIT = 1, //!< Only HEVC decoder supports 9 bits luma.HEVC encoder does not supports 9 bits luma. 1632 BIT_DEPTH_LUMA_MINUS8_LUMA10BIT = 2, //!< No additional details 1633 BIT_DEPTH_LUMA_MINUS8_LUMA11BIT = 3, //!< HEVC SCC does not support 11 bits LumaAlso only HEVC decoder (non-SCC) support 11 bits LumaHEVC encoder (non-SCC) does not support 11 bits Luma 1634 BIT_DEPTH_LUMA_MINUS8_LUMA12BIT = 4, //!< HEVC SCC does not support 12bits Luma 1635 }; 1636 1637 //! \brief NONFIRSTPASSFLAG 1638 //! \details 1639 //! This signals the current pass is not the first pass. It will imply 1640 //! designate HW behavior. 1641 enum NONFIRSTPASSFLAG 1642 { 1643 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 1644 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 1645 }; 1646 1647 //! \brief LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1648 //! \details 1649 //! This is a mask bit controlling if the condition of any LCU in the frame 1650 //! exceeds LCUMaxSize. 1651 enum LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1652 { 1653 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit 0 of HCP_IMAGE_STATUS control register. 1654 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. 1655 }; 1656 1657 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1658 //! \details 1659 //! This is a mask bit controlling if the condition of frame level bit count 1660 //! exceeds FrameBitRateMax. 1661 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1662 { 1663 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_IMAGE_STATUS control register. 1664 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit inHCP_IMAGE_STATUS_MASK register 1665 }; 1666 1667 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1668 //! \details 1669 //! This is a mask bit controlling if the condition of frame level bit count 1670 //! is less than FrameBitRateMin. 1671 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1672 { 1673 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register. 1674 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit in HCP_IMAGE_STATUS_MASK register 1675 }; 1676 1677 //! \brief LOAD_SLICE_POINTER_FLAG 1678 //! \details 1679 //! <p>LoadBitStreamPointerPerSlice (Encoder-only)</p> 1680 //! <p>To support multiple slice picture and additional header/data 1681 //! insertion before and after an encoded slice. When this field is set to 1682 //! 0, bitstream pointer is only loaded once for the first slice of a frame. 1683 //! For subsequent slices in the frame, bitstream data are stitched together 1684 //! to form a single output data stream. When this field is set to 1, 1685 //! bitstream pointer is loaded for each slice of a frame. Basically 1686 //! bitstream data for different slices of a frame will be written to 1687 //! different memory locations.</p> 1688 enum LOAD_SLICE_POINTER_FLAG 1689 { 1690 LOAD_SLICE_POINTER_FLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame. 1691 LOAD_SLICE_POINTER_FLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of thebitstream buffer from the Indirect PAK-BSE Object Data Start Address field. 1692 }; 1693 1694 //! \brief FRAMEBITRATEMAXUNIT 1695 //! \details 1696 //! This field is the Frame Bitrate Maximum Limit Units. 1697 enum FRAMEBITRATEMAXUNIT 1698 { 1699 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 1700 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4kbyte unit 1701 }; 1702 1703 //! \brief FRAMEBITRATEMINUNIT 1704 //! \details 1705 //! This field is the Frame Bitrate Minimum Limit Units. 1706 enum FRAMEBITRATEMINUNIT 1707 { 1708 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 1709 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4kbyte unit 1710 }; 1711 1712 //! \brief FRAMEBITRATEMINDELTA 1713 //! \details 1714 //! This field is used to select the slice delta QP when FrameBitRateMin Is 1715 //! exceeded. It shares the same 1716 //! FrameBitrateMinUnit. 1717 enum FRAMEBITRATEMINDELTA 1718 { 1719 FRAMEBITRATEMINDELTA_UNNAMED0 = 0, //!< No additional details 1720 }; 1721 1722 //! \brief FRAMEBITRATEMAXDELTA 1723 //! \details 1724 //! This field is used to select the slice delta QP when FrameBitRateMax Is 1725 //! exceeded. It shares the same 1726 //! FrameBitrateMaxUnit. 1727 enum FRAMEBITRATEMAXDELTA 1728 { 1729 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 1730 }; 1731 1732 //! \brief MINFRAMESIZE 1733 //! \details 1734 //! <p>Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)</p> 1735 //! <p>Mininum Frame Size is specified to compensate for intel Rate Control 1736 //! Currently zero fill (no need to perform emulation byte insertion) is 1737 //! done only to the end of the CABAC_ZERO_WORD insertion (if any) at the 1738 //! last slice of a picture. It is needed for CBR. Intel encoder parameter. 1739 //! The caller should always make sure that the value, represented by 1740 //! Mininum Frame Size, is always less than maximum frame size 1741 //! FrameBitRateMax. This field is reserved in Decode mode.</p> 1742 enum MINFRAMESIZE 1743 { 1744 MINFRAMESIZE_UNNAMED0 = 0, //!< No additional details 1745 }; 1746 1747 //! \brief MINFRAMESIZEUNITS 1748 //! \details 1749 //! This field is the Minimum Frame Size Units 1750 enum MINFRAMESIZEUNITS 1751 { 1752 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 1753 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 16Kbytes. 1754 MINFRAMESIZEUNITS_COMPATIBILITYMODE = 2, //!< Minimum Frame Size is in 4bytes 1755 MINFRAMESIZEUNITS_16BYTES = 3, //!< Minimum Frame Size is 16 bytes. 1756 }; 1757 1758 //! \brief MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1759 //! \details 1760 //! <p>This controls the presense and inference of the use_integer_mv_flag 1761 //! that specifies the resolution of motion vectors for inter 1762 //! prediction.</p> 1763 //! <p>Decoder only (Encoder default to "00")</p> 1764 enum MOTION_VECTOR_RESOLUTION_CONTROL_IDC 1765 { 1766 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_NOINTEGERMVFORTHEFRAME = 0, //!< No additional details 1767 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ONLYINTEGERMVFORTHEFRAME = 1, //!< No additional details 1768 MOTION_VECTOR_RESOLUTION_CONTROL_IDC_ADAPTIVEINTEGERMVFORTHEFRAME = 2, //!< Slice signal use_inter_mv_flag will indicate if the slice will use interger MV or not 1769 }; 1770 1771 //! \brief IBC_CONFIGURATION 1772 //! \details 1773 //! <p>IBC configuration is used configure Intra block copy.</p> 1774 //! <p>- Disable Intra block copy.</p> 1775 //! <p>- Limit Intra block copy from Left blocks only.</p> 1776 //! <p>- Allow full range of Intra block copy as specified in spec.</p> 1777 //! <p></p> 1778 enum IBC_CONFIGURATION 1779 { 1780 IBC_CONFIGURATION_UNNAMED0 = 0, //!< When IBC configuration is 0, intra block copy is disabled and it applies for both Fixed function encoder and decoder. 1781 IBC_CONFIGURATION_UNNAMED1 = 1, //!< When IBC configuration in fixed function encoder (VDENC) mode is set to 1, Intra block search includes only left region. 1782 IBC_CONFIGURATION_UNNAMED2 = 2, //!< No additional details 1783 IBC_CONFIGURATION_UNNAMED3 = 3, //!< When IBC configuration in VDENC mode is set to 3, Intra block search includes top and left regions.In decoder mode, When SCC is enabled this field should be set to 3. 1784 }; 1785 1786 //! \brief FRAME_CRC_TYPE 1787 //! \details 1788 //! <p>This indicates how CRC is generated. This bit is ignored and must be 1789 //! programmed to 0 if Frame CRC Enable is "0"</p> 1790 enum FRAME_CRC_TYPE 1791 { 1792 FRAME_CRC_TYPE_CRCWITHYUVVALUE = 0, //!< No additional details 1793 FRAME_CRC_TYPE_CRCWITHYVALUEONLY = 1, //!< No additional details 1794 }; 1795 1796 //! \name Initializations 1797 1798 //! \brief Explicit member initialization function 1799 HCP_PIC_STATE_CMD(); 1800 1801 static const size_t dwSize = 41; 1802 static const size_t byteSize = 164; 1803 }; 1804 1805 //! 1806 //! \brief HCP_TILE_POSITION_IN_CTB 1807 //! \details 1808 //! 1809 //! 1810 struct HCP_TILE_POSITION_IN_CTB_CMD 1811 { 1812 union 1813 { 1814 struct 1815 { 1816 uint32_t Ctbpos0I : __CODEGEN_BITFIELD( 0, 7) ; //!< CtbPos0+i 1817 uint32_t Ctbpos1I : __CODEGEN_BITFIELD( 8, 15) ; //!< CtbPos1+i 1818 uint32_t Ctbpos2I : __CODEGEN_BITFIELD(16, 23) ; //!< CtbPos2+i 1819 uint32_t Ctbpos3I : __CODEGEN_BITFIELD(24, 31) ; //!< CtbPos3+i 1820 }; 1821 uint32_t Value; 1822 } DW0; 1823 1824 //! \name Local enumerations 1825 1826 //! \name Initializations 1827 1828 //! \brief Explicit member initialization function 1829 HCP_TILE_POSITION_IN_CTB_CMD(); 1830 1831 static const size_t dwSize = 1; 1832 static const size_t byteSize = 4; 1833 }; 1834 1835 //! 1836 //! \brief HCP_TILE_POSITION_IN_CTB_MSB 1837 //! \details 1838 //! Added to support 16k picture size. 1839 //! 1840 struct HCP_TILE_POSITION_IN_CTB_MSB_CMD 1841 { 1842 union 1843 { 1844 struct 1845 { 1846 uint32_t CtbRowPositionOfTileColumn098 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 0 [9:8] 1847 uint32_t CtbRowPositionOfTileColumn198 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 1 [9:8] 1848 uint32_t CtbRowPositionOfTileColumn298 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 2 [9:8] 1849 uint32_t CtbRowPositionOfTileColumn398 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 3 [9:8] 1850 uint32_t CtbRowPositionOfTileColumn498 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 4 [9:8] 1851 uint32_t CtbRowPositionOfTileColumn598 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb row position of tile column 5 [9:8] 1852 uint32_t CtbRowPositionOfTileColumn698 : __CODEGEN_BITFIELD(12, 13) ; //!< Ctb row position of tile column 6 [9:8] 1853 uint32_t CtbRowPositionOfTileColumn798 : __CODEGEN_BITFIELD(14, 15) ; //!< Ctb row position of tile column 7 [9:8] 1854 uint32_t CtbRowPositionOfTileColumn898 : __CODEGEN_BITFIELD(16, 17) ; //!< Ctb row position of tile column 8 [9:8] 1855 uint32_t CtbRowPositionOfTileColumn998 : __CODEGEN_BITFIELD(18, 19) ; //!< Ctb row position of tile column 9 [9:8] 1856 uint32_t CtbRowPositionOfTileColumn1098 : __CODEGEN_BITFIELD(20, 21) ; //!< Ctb row position of tile column 10 [9:8] 1857 uint32_t CtbRowPositionOfTileColumn1198 : __CODEGEN_BITFIELD(22, 23) ; //!< Ctb row position of tile column 11 [9:8] 1858 uint32_t CtbRowPositionOfTileColumn1298 : __CODEGEN_BITFIELD(24, 25) ; //!< Ctb row position of tile column 12 [9:8] 1859 uint32_t CtbRowPositionOfTileColumn1398 : __CODEGEN_BITFIELD(26, 27) ; //!< Ctb row position of tile column 13 [9:8] 1860 uint32_t CtbRowPositionOfTileColumn1498 : __CODEGEN_BITFIELD(28, 29) ; //!< Ctb row position of tile column 14 [9:8] 1861 uint32_t CtbRowPositionOfTileColumn1598 : __CODEGEN_BITFIELD(30, 31) ; //!< Ctb row position of tile column 15 [9:8] 1862 }; 1863 uint32_t Value; 1864 } DW0; 1865 union 1866 { 1867 struct 1868 { 1869 uint32_t CtbRowPositionOfTileColumn1698 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 16 [9:8] 1870 uint32_t CtbRowPositionOfTileColumn1798 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 17 [9:8] 1871 uint32_t CtbRowPositionOfTileColumn1898 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 18 [9:8] 1872 uint32_t CtbRowPositionOfTileColumn1998 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 19 [9:8] 1873 uint32_t CtbRowPositionOfTileColumn2098 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 20 [9:8] 1874 uint32_t CtbPositionOfTile2198 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb position of tile 21 [9:8] 1875 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 1876 }; 1877 uint32_t Value; 1878 } DW1; 1879 1880 //! \name Local enumerations 1881 1882 //! \name Initializations 1883 1884 //! \brief Explicit member initialization function 1885 HCP_TILE_POSITION_IN_CTB_MSB_CMD(); 1886 1887 static const size_t dwSize = 2; 1888 static const size_t byteSize = 8; 1889 }; 1890 1891 //! 1892 //! \brief HCP_TILE_STATE 1893 //! \details 1894 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 1895 //! Commands. Each HCP command has assigned a media instruction command as 1896 //! defined in DWord 0, BitField 22:16. 1897 //! 1898 //! This command is valid for decoder only. 1899 //! 1900 struct HCP_TILE_STATE_CMD 1901 { 1902 union 1903 { 1904 struct 1905 { 1906 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1907 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1908 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1909 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1910 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1911 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1912 }; 1913 uint32_t Value; 1914 } DW0; 1915 union 1916 { 1917 struct 1918 { 1919 uint32_t Numtilerowsminus1 : __CODEGEN_BITFIELD( 0, 4) ; //!< NumTileRowsMinus1 1920 uint32_t Numtilecolumnsminus1 : __CODEGEN_BITFIELD( 5, 9) ; //!< NumTileColumnsMinus1 1921 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 1922 }; 1923 uint32_t Value; 1924 } DW1; 1925 HCP_TILE_POSITION_IN_CTB_CMD CtbColumnPositionOfTileColumn[5]; //!< DW2..6, Ctb column position of tile column 1926 HCP_TILE_POSITION_IN_CTB_CMD CtbRowPositionOfTileRow[6]; //!< DW7..12, Ctb row position of tile row 1927 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbColumnPositionMsb; //!< DW13..14, Ctb column position MSB 1928 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbRowPositionMsb; //!< DW15..16, Ctb row position MSB 1929 1930 //! \name Local enumerations 1931 1932 enum MEDIA_INSTRUCTION_COMMAND 1933 { 1934 MEDIA_INSTRUCTION_COMMAND_HCPTILESTATE = 17, //!< No additional details 1935 }; 1936 1937 //! \brief MEDIA_INSTRUCTION_OPCODE 1938 //! \details 1939 //! Codec/Engine Name = HCP = 7h 1940 enum MEDIA_INSTRUCTION_OPCODE 1941 { 1942 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1943 }; 1944 1945 enum PIPELINE_TYPE 1946 { 1947 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1948 }; 1949 1950 enum COMMAND_TYPE 1951 { 1952 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1953 }; 1954 1955 //! \name Initializations 1956 1957 //! \brief Explicit member initialization function 1958 HCP_TILE_STATE_CMD(); 1959 1960 static const size_t dwSize = 17; 1961 static const size_t byteSize = 68; 1962 }; 1963 1964 //! 1965 //! \brief HCP_REF_LIST_ENTRY 1966 //! \details 1967 //! 1968 //! 1969 struct HCP_REF_LIST_ENTRY_CMD 1970 { 1971 union 1972 { 1973 struct 1974 { 1975 uint32_t ReferencePictureTbValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Reference Picture tb Value 1976 uint32_t ListEntryLxReferencePictureFrameIdRefaddr07 : __CODEGEN_BITFIELD( 8, 10) ; //!< list_entry_lX: Reference Picture Frame ID (RefAddr[0-7]) 1977 uint32_t ChromaWeightLxFlag : __CODEGEN_BITFIELD(11, 11) ; //!< CHROMA_WEIGHT_LX_FLAG 1978 uint32_t LumaWeightLxFlag : __CODEGEN_BITFIELD(12, 12) ; //!< LUMA_WEIGHT_LX_FLAG 1979 uint32_t Longtermreference : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERMREFERENCE 1980 uint32_t FieldPicFlag : __CODEGEN_BITFIELD(14, 14) ; //!< FIELD_PIC_FLAG 1981 uint32_t BottomFieldFlag : __CODEGEN_BITFIELD(15, 15) ; //!< BOTTOM_FIELD_FLAG 1982 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1983 }; 1984 uint32_t Value; 1985 } DW0; 1986 1987 //! \name Local enumerations 1988 1989 //! \brief CHROMA_WEIGHT_LX_FLAG 1990 //! \details 1991 //! Where X is the RefPicListNum and i is the list entry number 0 through 1992 //! 15. DW2 corresponds to i=0, 1993 //! DW17 corresponds to i=15. 1994 enum CHROMA_WEIGHT_LX_FLAG 1995 { 1996 CHROMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORCHROMA = 0, //!< No additional details 1997 CHROMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORCHROMA = 1, //!< No additional details 1998 }; 1999 2000 //! \brief LUMA_WEIGHT_LX_FLAG 2001 //! \details 2002 //! Where X is the RefPicListNum and i is the list entry number 0 through 2003 //! 15. DW2 corresponds to i=0, 2004 //! DW17 corresponds to i=15. 2005 enum LUMA_WEIGHT_LX_FLAG 2006 { 2007 LUMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORLUMA = 0, //!< No additional details 2008 LUMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORLUMA = 1, //!< No additional details 2009 }; 2010 2011 //! \brief LONGTERMREFERENCE 2012 //! \details 2013 //! Where X is the RefPicListNum and i is the list entry number 0 through 2014 //! 15. DW2 corresponds to i=0, 2015 //! DW17 corresponds to i=15. 2016 enum LONGTERMREFERENCE 2017 { 2018 LONGTERMREFERENCE_SHORTTERMREFERENCE = 0, //!< No additional details 2019 LONGTERMREFERENCE_LONGTERMREFERENCE = 1, //!< No additional details 2020 }; 2021 2022 //! \brief FIELD_PIC_FLAG 2023 //! \details 2024 //! Where X is the RefPicListNum and i is the list entry number 0 through 2025 //! 15. DW2 corresponds to i=0, 2026 //! DW17 corresponds to i=15. 2027 enum FIELD_PIC_FLAG 2028 { 2029 FIELD_PIC_FLAG_VIDEOFRAME = 0, //!< No additional details 2030 FIELD_PIC_FLAG_VIDEOFIELD = 1, //!< No additional details 2031 }; 2032 2033 //! \brief BOTTOM_FIELD_FLAG 2034 //! \details 2035 //! Where X is the RefPicListNum and i is the list entry number 0 through 2036 //! 15. DW2 corresponds to i=0, 2037 //! DW17 corresponds to i=15. 2038 enum BOTTOM_FIELD_FLAG 2039 { 2040 BOTTOM_FIELD_FLAG_BOTTOMFIELD = 0, //!< No additional details 2041 BOTTOM_FIELD_FLAG_TOPFIELD = 1, //!< No additional details 2042 }; 2043 2044 //! \name Initializations 2045 2046 //! \brief Explicit member initialization function 2047 HCP_REF_LIST_ENTRY_CMD(); 2048 2049 static const size_t dwSize = 1; 2050 static const size_t byteSize = 4; 2051 }; 2052 2053 //! 2054 //! \brief HCP_REF_IDX_STATE 2055 //! \details 2056 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2057 //! Commands. Each HCP command has assigned a media instruction command as 2058 //! defined in DWord 0, BitField 22:16. 2059 //! 2060 //! This is a slice level command used in both encoding and decoding 2061 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 2062 //! 2063 //! Unlike AVC, HEVC allows 16 reference idx entries in each of the L0 and 2064 //! L1 list for a progressive picture. Hence, a max total 32 reference idx 2065 //! in both lists together. The same when the picture is a field picture. 2066 //! Regardless the number of reference idx entries, there are only max 8 2067 //! reference pictures exist at any one time. Multiple reference idx can 2068 //! point to the same reference picture and can optionally pic a top or 2069 //! bottom field, or frame. 2070 //! 2071 //! For P-Slice, this command is issued only once, representing L0 list. For 2072 //! B-Slice, this command can be issued up to two times, one for L0 list and 2073 //! one for L1 list. 2074 //! 2075 struct HCP_REF_IDX_STATE_CMD 2076 { 2077 union 2078 { 2079 struct 2080 { 2081 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2082 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2083 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2084 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2085 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2086 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2087 }; 2088 uint32_t Value; 2089 } DW0; 2090 union 2091 { 2092 struct 2093 { 2094 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2095 uint32_t NumRefIdxLRefpiclistnumActiveMinus1 : __CODEGEN_BITFIELD( 1, 4) ; //!< num_ref_idx_l[RefPicListNum]_active_minus1 2096 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 2097 }; 2098 uint32_t Value; 2099 } DW1; 2100 HCP_REF_LIST_ENTRY_CMD Entries[16]; //!< DW2..17, Entries 2101 2102 //! \name Local enumerations 2103 2104 enum MEDIA_INSTRUCTION_COMMAND 2105 { 2106 MEDIA_INSTRUCTION_COMMAND_HCPREFIDXSTATE = 18, //!< No additional details 2107 }; 2108 2109 //! \brief MEDIA_INSTRUCTION_OPCODE 2110 //! \details 2111 //! Codec/Engine Name = HCP = 7h 2112 enum MEDIA_INSTRUCTION_OPCODE 2113 { 2114 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2115 }; 2116 2117 enum PIPELINE_TYPE 2118 { 2119 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2120 }; 2121 2122 enum COMMAND_TYPE 2123 { 2124 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2125 }; 2126 2127 enum REFPICLISTNUM 2128 { 2129 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2130 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2131 }; 2132 2133 //! \name Initializations 2134 2135 //! \brief Explicit member initialization function 2136 HCP_REF_IDX_STATE_CMD(); 2137 2138 static const size_t dwSize = 18; 2139 static const size_t byteSize = 72; 2140 }; 2141 2142 //! 2143 //! \brief HCP_WEIGHTOFFSET_LUMA_ENTRY 2144 //! \details 2145 //! 2146 //! 2147 struct HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD 2148 { 2149 union 2150 { 2151 struct 2152 { 2153 uint32_t DeltaLumaWeightLxI : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_luma_weight_lX[i] 2154 uint32_t LumaOffsetLxI : __CODEGEN_BITFIELD( 8, 15) ; //!< luma_offset_lX[i] 2155 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 2156 uint32_t LumaOffsetLxIMsbyte : __CODEGEN_BITFIELD(24, 31) ; //!< luma_offset_lX[i] MSByte 2157 }; 2158 uint32_t Value; 2159 } DW0; 2160 2161 //! \name Local enumerations 2162 2163 //! \name Initializations 2164 2165 //! \brief Explicit member initialization function 2166 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD(); 2167 2168 static const size_t dwSize = 1; 2169 static const size_t byteSize = 4; 2170 }; 2171 2172 //! 2173 //! \brief HCP_WEIGHTOFFSET_CHROMA_ENTRY 2174 //! \details 2175 //! 2176 //! 2177 struct HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD 2178 { 2179 union 2180 { 2181 struct 2182 { 2183 uint32_t DeltaChromaWeightLxI0 : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_chroma_weight_lX[i][0] 2184 uint32_t ChromaoffsetlxI0 : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i][0] 2185 uint32_t DeltaChromaWeightLxI1 : __CODEGEN_BITFIELD(16, 23) ; //!< delta_chroma_weight_lX[i][1] 2186 uint32_t ChromaoffsetlxI1 : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX [i][1] 2187 }; 2188 uint32_t Value; 2189 } DW0; 2190 2191 //! \name Local enumerations 2192 2193 //! \name Initializations 2194 2195 //! \brief Explicit member initialization function 2196 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD(); 2197 2198 static const size_t dwSize = 1; 2199 static const size_t byteSize = 4; 2200 }; 2201 2202 //! 2203 //! \brief HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY 2204 //! \details 2205 //! 2206 //! 2207 struct HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD 2208 { 2209 union 2210 { 2211 struct 2212 { 2213 uint32_t ChromaoffsetlxI0Msbyte : __CODEGEN_BITFIELD( 0, 7) ; //!< ChromaOffsetLX[i][0] MSByte 2214 uint32_t ChromaoffsetlxI10Msbyte : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i+1][0] MSByte 2215 uint32_t ChromaoffsetlxI1Msbyte : __CODEGEN_BITFIELD(16, 23) ; //!< ChromaOffsetLX[i][1] MSByte 2216 uint32_t ChromaoffsetlxI11Msbyte : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX[i+1][1] MSByte 2217 }; 2218 uint32_t Value; 2219 } DW0; 2220 2221 //! \name Local enumerations 2222 2223 //! \name Initializations 2224 2225 //! \brief Explicit member initialization function 2226 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD(); 2227 2228 static const size_t dwSize = 1; 2229 static const size_t byteSize = 4; 2230 }; 2231 2232 //! 2233 //! \brief HCP_WEIGHTOFFSET_STATE 2234 //! \details 2235 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2236 //! Commands. Each HCP command has assigned a media instruction command as 2237 //! defined in DWord 0, BitField 22:16. 2238 //! 2239 //! This slice level command is issued in both the encoding and decoding 2240 //! processes, if the weighted_pred_flag or weighted_bipred_flag equals one. 2241 //! If zero, then this command is not issued. Weight Prediction Values are 2242 //! provided in this command. Only Explicit Weight Prediction is supported 2243 //! in encoder. For P-Slice, this command is issued only once together with 2244 //! HCP_REF_IDX_STATE Command for L0 list. For B-Slice, this command can be 2245 //! issued up to two times together with HCP_REF_IDX_STATE Command, one for 2246 //! L0 list and one for L1 list. 2247 //! 2248 struct HCP_WEIGHTOFFSET_STATE_CMD 2249 { 2250 union 2251 { 2252 struct 2253 { 2254 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2255 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2256 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2257 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2258 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2259 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2260 }; 2261 uint32_t Value; 2262 } DW0; 2263 union 2264 { 2265 struct 2266 { 2267 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2268 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2269 }; 2270 uint32_t Value; 2271 } DW1; 2272 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD Lumaoffsets[16]; //!< DW2..17, LumaOffsets 2273 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD Chromaoffsets[16]; //!< DW18..33, ChromaOffsets 2274 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD Chromaoffsetsext[8]; //!< DW34..41, ChromaOffsetsExt 2275 2276 //! \name Local enumerations 2277 2278 enum MEDIA_INSTRUCTION_COMMAND 2279 { 2280 MEDIA_INSTRUCTION_COMMAND_HCPWEIGHTOFFSETSTATE = 19, //!< No additional details 2281 }; 2282 2283 //! \brief MEDIA_INSTRUCTION_OPCODE 2284 //! \details 2285 //! Codec/Engine Name = HCP = 7h 2286 enum MEDIA_INSTRUCTION_OPCODE 2287 { 2288 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2289 }; 2290 2291 enum PIPELINE_TYPE 2292 { 2293 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2294 }; 2295 2296 enum COMMAND_TYPE 2297 { 2298 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2299 }; 2300 2301 enum REFPICLISTNUM 2302 { 2303 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2304 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2305 }; 2306 2307 //! \name Initializations 2308 2309 //! \brief Explicit member initialization function 2310 HCP_WEIGHTOFFSET_STATE_CMD(); 2311 2312 static const size_t dwSize = 42; 2313 static const size_t byteSize = 168; 2314 }; 2315 2316 //! 2317 //! \brief HCP_SLICE_STATE 2318 //! \details 2319 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2320 //! Commands. Each HCP command has assigned a media instruction command as 2321 //! defined in DWord 0, BitField 22:16. 2322 //! 2323 //! This is a slice level command used in both encoding and decoding 2324 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 2325 //! 2326 struct HCP_SLICE_STATE_CMD 2327 { 2328 union 2329 { 2330 struct 2331 { 2332 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2333 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2334 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2335 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2336 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2337 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2338 }; 2339 uint32_t Value; 2340 } DW0; 2341 union 2342 { 2343 struct 2344 { 2345 uint32_t SlicestartctbxOrSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< SliceStartCtbX or (slice_start_lcu_x encoder) 2346 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2347 uint32_t SlicestartctbyOrSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 25) ; //!< SliceStartCtbY or (slice_start_lcu_y encoder) 2348 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2349 }; 2350 uint32_t Value; 2351 } DW1; 2352 union 2353 { 2354 struct 2355 { 2356 uint32_t NextslicestartctbxOrNextSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSliceStartCtbX or (next_slice_start_lcu_x encoder) 2357 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2358 uint32_t NextslicestartctbyOrNextSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 26) ; //!< NextSliceStartCtbY or (next_slice_start_lcu_y encoder) 2359 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 2360 }; 2361 uint32_t Value; 2362 } DW2; 2363 union 2364 { 2365 struct 2366 { 2367 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 1) ; //!< SLICE_TYPE 2368 uint32_t Lastsliceofpic : __CODEGEN_BITFIELD( 2, 2) ; //!< LASTSLICEOFPIC 2369 uint32_t SliceqpSignFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< SliceQp Sign Flag 2370 uint32_t DependentSliceFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< dependent_slice_flag 2371 uint32_t SliceTemporalMvpEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< slice_temporal_mvp_enable_flag 2372 uint32_t Sliceqp : __CODEGEN_BITFIELD( 6, 11) ; //!< SliceQp 2373 uint32_t SliceCbQpOffset : __CODEGEN_BITFIELD(12, 16) ; //!< SLICE_CB_QP_OFFSET 2374 uint32_t SliceCrQpOffset : __CODEGEN_BITFIELD(17, 21) ; //!< SLICE_CR_QP_OFFSET 2375 uint32_t Intrareffetchdisable : __CODEGEN_BITFIELD(22, 22) ; //!< IntraRefFetchDisable 2376 uint32_t CuChromaQpOffsetEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cu_chroma_qp_offset_enabled_flag 2377 uint32_t Lastsliceoftile : __CODEGEN_BITFIELD(24, 24) ; //!< LastSliceOfTile 2378 uint32_t Lastsliceoftilecolumn : __CODEGEN_BITFIELD(25, 25) ; //!< LastSliceOfTileColumn 2379 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2380 }; 2381 uint32_t Value; 2382 } DW3; 2383 union 2384 { 2385 struct 2386 { 2387 uint32_t SliceHeaderDisableDeblockingFilterFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< slice_header_disable_deblocking_filter_flag 2388 uint32_t SliceTcOffsetDiv2OrFinalTcOffsetDiv2Encoder : __CODEGEN_BITFIELD( 1, 4) ; //!< slice_tc_offset_div2 or (final tc_offset_div2 Encoder) 2389 uint32_t SliceBetaOffsetDiv2OrFinalBetaOffsetDiv2Encoder : __CODEGEN_BITFIELD( 5, 8) ; //!< slice_beta_offset_div2 or (final Beta_Offset_div2 Encoder) 2390 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 2391 uint32_t SliceLoopFilterAcrossSlicesEnabledFlag : __CODEGEN_BITFIELD(10, 10) ; //!< slice_loop_filter_across_slices_enabled_flag 2392 uint32_t SliceSaoChromaFlag : __CODEGEN_BITFIELD(11, 11) ; //!< slice_sao_chroma_flag 2393 uint32_t SliceSaoLumaFlag : __CODEGEN_BITFIELD(12, 12) ; //!< slice_sao_luma_flag 2394 uint32_t MvdL1ZeroFlag : __CODEGEN_BITFIELD(13, 13) ; //!< mvd_l1_zero_flag 2395 uint32_t Islowdelay : __CODEGEN_BITFIELD(14, 14) ; //!< isLowDelay 2396 uint32_t CollocatedFromL0Flag : __CODEGEN_BITFIELD(15, 15) ; //!< collocated_from_l0_flag 2397 uint32_t Chromalog2Weightdenom : __CODEGEN_BITFIELD(16, 18) ; //!< ChromaLog2WeightDenom 2398 uint32_t LumaLog2WeightDenom : __CODEGEN_BITFIELD(19, 21) ; //!< luma_log2_weight_denom 2399 uint32_t CabacInitFlag : __CODEGEN_BITFIELD(22, 22) ; //!< cabac_init_flag 2400 uint32_t Maxmergeidx : __CODEGEN_BITFIELD(23, 25) ; //!< MAXMERGEIDX 2401 uint32_t Collocatedrefidx : __CODEGEN_BITFIELD(26, 28) ; //!< CollocatedRefIDX 2402 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2403 }; 2404 uint32_t Value; 2405 } DW4; 2406 union 2407 { 2408 struct 2409 { 2410 uint32_t Sliceheaderlength : __CODEGEN_BITFIELD( 0, 15) ; //!< SliceHeaderLength 2411 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2412 }; 2413 uint32_t Value; 2414 } DW5; 2415 union 2416 { 2417 struct 2418 { 2419 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 2420 uint32_t Roundintra : __CODEGEN_BITFIELD(20, 23) ; //!< ROUNDINTRA 2421 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 25) ; //!< Reserved 2422 uint32_t Roundinter : __CODEGEN_BITFIELD(26, 29) ; //!< ROUNDINTER 2423 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2424 }; 2425 uint32_t Value; 2426 } DW6; 2427 union 2428 { 2429 struct 2430 { 2431 uint32_t DependentSliceDueToTileSplit : __CODEGEN_BITFIELD( 0, 0) ; //!< Dependent Slice due to Tile Split 2432 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD( 1, 1) ; //!< CABACZEROWORDINSERTIONENABLE 2433 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD( 2, 2) ; //!< EMULATIONBYTESLICEINSERTENABLE 2434 uint32_t Reserved227 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2435 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< TAIL_INSERTION_ENABLE 2436 uint32_t SlicedataEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SLICEDATA_ENABLE 2437 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< HEADER_INSERTION_ENABLE 2438 uint32_t Reserved235 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 2439 }; 2440 uint32_t Value; 2441 } DW7; 2442 union 2443 { 2444 struct 2445 { 2446 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 2447 uint32_t IndirectPakBseDataStartOffsetWrite : __CODEGEN_BITFIELD( 6, 28) ; //!< Indirect PAK-BSE Data Start Offset (Write) 2448 uint32_t Reserved285 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2449 }; 2450 uint32_t Value; 2451 } DW8; 2452 union 2453 { 2454 struct 2455 { 2456 uint32_t TransformskipLambda : __CODEGEN_BITFIELD( 0, 15) ; //!< Transformskip_lambda 2457 uint32_t Reserved304 : __CODEGEN_BITFIELD(16, 30) ; //!< Reserved 2458 uint32_t ForceSaoParametersToZero : __CODEGEN_BITFIELD(31, 31) ; //!< Force SAO parameters to zero 2459 }; 2460 uint32_t Value; 2461 } DW9; 2462 union 2463 { 2464 struct 2465 { 2466 uint32_t TransformskipNumzerocoeffsFactor0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Transformskip_numzerocoeffs_factor0 2467 uint32_t TransformskipNumnonzerocoeffsFactor0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Transformskip_numnonzerocoeffs_factor0 2468 uint32_t TransformskipNumzerocoeffsFactor1 : __CODEGEN_BITFIELD(16, 23) ; //!< Transformskip_numzerocoeffs_factor1 2469 uint32_t TransformskipNumnonzerocoeffsFactor1 : __CODEGEN_BITFIELD(24, 31) ; //!< Transformskip_numnonzerocoeffs_factor1 2470 }; 2471 uint32_t Value; 2472 } DW10; 2473 union 2474 { 2475 struct 2476 { 2477 uint32_t Originalslicestartctbx : __CODEGEN_BITFIELD( 0, 9) ; //!< OriginalSliceStartCtbX 2478 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2479 uint32_t Originalslicestartctby : __CODEGEN_BITFIELD(16, 25) ; //!< OriginalSliceStartCtbY 2480 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2481 }; 2482 uint32_t Value; 2483 } DW11; 2484 union 2485 { 2486 struct 2487 { 2488 uint32_t SliceActCrQpOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< slice_act_cr_qp_offset 2489 uint32_t SliceActCbQpOffset : __CODEGEN_BITFIELD( 6, 11) ; //!< slice_act_cb_qp_offset 2490 uint32_t SliceActYQpOffset : __CODEGEN_BITFIELD(12, 17) ; //!< slice_act_y_qp_offset 2491 uint32_t Reserved402 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 2492 uint32_t UseIntegerMvFlag : __CODEGEN_BITFIELD(31, 31) ; //!< use_integer_mv_flag 2493 }; 2494 uint32_t Value; 2495 } DW12; 2496 2497 //! \name Local enumerations 2498 2499 enum MEDIA_INSTRUCTION_COMMAND 2500 { 2501 MEDIA_INSTRUCTION_COMMAND_HCPSLICESTATE = 20, //!< No additional details 2502 }; 2503 2504 //! \brief MEDIA_INSTRUCTION_OPCODE 2505 //! \details 2506 //! Codec/Engine Name = HCP = 7h 2507 enum MEDIA_INSTRUCTION_OPCODE 2508 { 2509 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2510 }; 2511 2512 enum PIPELINE_TYPE 2513 { 2514 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2515 }; 2516 2517 enum COMMAND_TYPE 2518 { 2519 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2520 }; 2521 2522 //! \brief SLICE_TYPE 2523 //! \details 2524 //! In VDENC mode, for HEVC standard this field can be 0 or 2 only. 2525 enum SLICE_TYPE 2526 { 2527 SLICE_TYPE_B_SLICE = 0, //!< No additional details 2528 SLICE_TYPE_P_SLICE = 1, //!< No additional details 2529 SLICE_TYPE_I_SLICE = 2, //!< No additional details 2530 SLICE_TYPE_ILLEGALRESERVED = 3, //!< No additional details 2531 }; 2532 2533 //! \brief LASTSLICEOFPIC 2534 //! \details 2535 //! This indicates the current slice is the very last slice of the current 2536 //! picture 2537 enum LASTSLICEOFPIC 2538 { 2539 LASTSLICEOFPIC_NOTTHELASTSLICEOFTHEPICTURE = 0, //!< No additional details 2540 LASTSLICEOFPIC_LASTSLICEOFTHEPICTURE = 1, //!< No additional details 2541 }; 2542 2543 //! \brief SLICE_CB_QP_OFFSET 2544 //! \details 2545 //! For deblocking purpose, the pic and slice level cb qp offset must be 2546 //! provided separately. 2547 enum SLICE_CB_QP_OFFSET 2548 { 2549 SLICE_CB_QP_OFFSET_0 = 0, //!< No additional details 2550 SLICE_CB_QP_OFFSET_1 = 1, //!< No additional details 2551 SLICE_CB_QP_OFFSET_2 = 2, //!< No additional details 2552 SLICE_CB_QP_OFFSET_3 = 3, //!< No additional details 2553 SLICE_CB_QP_OFFSET_4 = 4, //!< No additional details 2554 SLICE_CB_QP_OFFSET_5 = 5, //!< No additional details 2555 SLICE_CB_QP_OFFSET_6 = 6, //!< No additional details 2556 SLICE_CB_QP_OFFSET_7 = 7, //!< No additional details 2557 SLICE_CB_QP_OFFSET_8 = 8, //!< No additional details 2558 SLICE_CB_QP_OFFSET_9 = 9, //!< No additional details 2559 SLICE_CB_QP_OFFSET_10 = 10, //!< No additional details 2560 SLICE_CB_QP_OFFSET_11 = 11, //!< No additional details 2561 SLICE_CB_QP_OFFSET_12 = 12, //!< No additional details 2562 SLICE_CB_QP_OFFSET_NEG_12 = 20, //!< No additional details 2563 SLICE_CB_QP_OFFSET_NEG_11 = 21, //!< No additional details 2564 SLICE_CB_QP_OFFSET_NEG_10 = 22, //!< No additional details 2565 SLICE_CB_QP_OFFSET_NEG_9 = 23, //!< No additional details 2566 SLICE_CB_QP_OFFSET_NEG_8 = 24, //!< No additional details 2567 SLICE_CB_QP_OFFSET_NEG_7 = 25, //!< No additional details 2568 SLICE_CB_QP_OFFSET_NEG_6 = 26, //!< No additional details 2569 SLICE_CB_QP_OFFSET_NEG_5 = 27, //!< No additional details 2570 SLICE_CB_QP_OFFSET_NEG_4 = 28, //!< No additional details 2571 SLICE_CB_QP_OFFSET_NEG_3 = 29, //!< No additional details 2572 SLICE_CB_QP_OFFSET_NEG_2 = 30, //!< No additional details 2573 SLICE_CB_QP_OFFSET_NEG_1 = 31, //!< No additional details 2574 }; 2575 2576 //! \brief SLICE_CR_QP_OFFSET 2577 //! \details 2578 //! For deblocking purpose, the pic and slice level cr qp offset must be 2579 //! provided separately. 2580 enum SLICE_CR_QP_OFFSET 2581 { 2582 SLICE_CR_QP_OFFSET_0 = 0, //!< No additional details 2583 SLICE_CR_QP_OFFSET_1 = 1, //!< No additional details 2584 SLICE_CR_QP_OFFSET_2 = 2, //!< No additional details 2585 SLICE_CR_QP_OFFSET_3 = 3, //!< No additional details 2586 SLICE_CR_QP_OFFSET_4 = 4, //!< No additional details 2587 SLICE_CR_QP_OFFSET_5 = 5, //!< No additional details 2588 SLICE_CR_QP_OFFSET_6 = 6, //!< No additional details 2589 SLICE_CR_QP_OFFSET_7 = 7, //!< No additional details 2590 SLICE_CR_QP_OFFSET_8 = 8, //!< No additional details 2591 SLICE_CR_QP_OFFSET_9 = 9, //!< No additional details 2592 SLICE_CR_QP_OFFSET_10 = 10, //!< No additional details 2593 SLICE_CR_QP_OFFSET_11 = 11, //!< No additional details 2594 SLICE_CR_QP_OFFSET_12 = 12, //!< No additional details 2595 SLICE_CR_QP_OFFSET_NEG_12 = 20, //!< No additional details 2596 SLICE_CR_QP_OFFSET_NEG_11 = 21, //!< No additional details 2597 SLICE_CR_QP_OFFSET_NEG_10 = 22, //!< No additional details 2598 SLICE_CR_QP_OFFSET_NEG_9 = 23, //!< No additional details 2599 SLICE_CR_QP_OFFSET_NEG_8 = 24, //!< No additional details 2600 SLICE_CR_QP_OFFSET_NEG_7 = 25, //!< No additional details 2601 SLICE_CR_QP_OFFSET_NEG_6 = 26, //!< No additional details 2602 SLICE_CR_QP_OFFSET_NEG_5 = 27, //!< No additional details 2603 SLICE_CR_QP_OFFSET_NEG_4 = 28, //!< No additional details 2604 SLICE_CR_QP_OFFSET_NEG_3 = 29, //!< No additional details 2605 SLICE_CR_QP_OFFSET_NEG_2 = 30, //!< No additional details 2606 SLICE_CR_QP_OFFSET_NEG_1 = 31, //!< No additional details 2607 }; 2608 2609 //! \brief MAXMERGEIDX 2610 //! \details 2611 //! MaxNumMergeCand = 5 - five_minus_max_num_merge_cand -1. 2612 enum MAXMERGEIDX 2613 { 2614 MAXMERGEIDX_0 = 0, //!< No additional details 2615 MAXMERGEIDX_1 = 1, //!< No additional details 2616 MAXMERGEIDX_2 = 2, //!< No additional details 2617 MAXMERGEIDX_3 = 3, //!< No additional details 2618 MAXMERGEIDX_4 = 4, //!< No additional details 2619 }; 2620 2621 //! \brief ROUNDINTRA 2622 //! \details 2623 //! In VDENC mode, this field is ignored. 2624 enum ROUNDINTRA 2625 { 2626 ROUNDINTRA_132 = 0, //!< No additional details 2627 ROUNDINTRA_232 = 1, //!< No additional details 2628 ROUNDINTRA_332 = 2, //!< No additional details 2629 ROUNDINTRA_432 = 3, //!< No additional details 2630 ROUNDINTRA_532 = 4, //!< No additional details 2631 ROUNDINTRA_632 = 5, //!< No additional details 2632 ROUNDINTRA_732 = 6, //!< No additional details 2633 ROUNDINTRA_832 = 7, //!< No additional details 2634 ROUNDINTRA_932 = 8, //!< No additional details 2635 ROUNDINTRA_1032 = 9, //!< No additional details 2636 ROUNDINTRA_1132 = 10, //!< No additional details 2637 ROUNDINTRA_1232 = 11, //!< No additional details 2638 ROUNDINTRA_1332 = 12, //!< No additional details 2639 ROUNDINTRA_1432 = 13, //!< No additional details 2640 ROUNDINTRA_1532 = 14, //!< No additional details 2641 ROUNDINTRA_1632 = 15, //!< No additional details 2642 }; 2643 2644 //! \brief ROUNDINTER 2645 //! \details 2646 //! In VDENC mode, this field is ignored. 2647 enum ROUNDINTER 2648 { 2649 ROUNDINTER_132 = 0, //!< No additional details 2650 ROUNDINTER_232 = 1, //!< No additional details 2651 ROUNDINTER_332 = 2, //!< No additional details 2652 ROUNDINTER_432 = 3, //!< No additional details 2653 ROUNDINTER_532 = 4, //!< No additional details 2654 ROUNDINTER_632 = 5, //!< No additional details 2655 ROUNDINTER_732 = 6, //!< No additional details 2656 ROUNDINTER_832 = 7, //!< No additional details 2657 ROUNDINTER_932 = 8, //!< No additional details 2658 ROUNDINTER_1032 = 9, //!< No additional details 2659 ROUNDINTER_1132 = 10, //!< No additional details 2660 ROUNDINTER_1232 = 11, //!< No additional details 2661 ROUNDINTER_1332 = 12, //!< No additional details 2662 ROUNDINTER_1432 = 13, //!< No additional details 2663 ROUNDINTER_1532 = 14, //!< No additional details 2664 ROUNDINTER_1632 = 15, //!< No additional details 2665 }; 2666 2667 //! \brief CABACZEROWORDINSERTIONENABLE 2668 //! \details 2669 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2670 //! requirement. 2671 enum CABACZEROWORDINSERTIONENABLE 2672 { 2673 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion. 2674 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP (effectively can be usedas an indicator for last slice of a picture, if the assumption is only the last slice of a pictureneeds to insert CABAC_ZERO_WORDs). 2675 }; 2676 2677 //! \brief EMULATIONBYTESLICEINSERTENABLE 2678 //! \details 2679 //! To have PAK outputting SODB or EBSP to the output bitstream buffer. 2680 enum EMULATIONBYTESLICEINSERTENABLE 2681 { 2682 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGRBSP = 0, //!< No additional details 2683 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGEBSP = 1, //!< No additional details 2684 }; 2685 2686 //! \brief TAIL_INSERTION_ENABLE 2687 //! \details 2688 //! Must be followed by the PAK Insertion Object Command to perform the 2689 //! actual insertion. 2690 enum TAIL_INSERTION_ENABLE 2691 { 2692 TAIL_INSERTION_ENABLE_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits. 2693 TAIL_INSERTION_ENABLE_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits.SKL restriction: Tail insertion is only possible at the end of frame but not in the middle (say slice end) 2694 }; 2695 2696 //! \brief SLICEDATA_ENABLE 2697 //! \details 2698 //! <p>Must always be enabled.</p> 2699 //! <p>Encoder only feature.</p> 2700 enum SLICEDATA_ENABLE 2701 { 2702 SLICEDATA_ENABLE_UNNAMED0 = 0, //!< No operation; no insertion. 2703 SLICEDATA_ENABLE_UNNAMED1 = 1, //!< Slice Data insertion by PAK Object Commands into the output bitstream buffer. 2704 }; 2705 2706 //! \brief HEADER_INSERTION_ENABLE 2707 //! \details 2708 //! Must be followed by the PAK Insertion Object Command to perform the 2709 //! actual insertion. 2710 enum HEADER_INSERTION_ENABLE 2711 { 2712 HEADER_INSERTION_ENABLE_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, before the current slice encoded bits. 2713 HEADER_INSERTION_ENABLE_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is before the current slice encoded bits. 2714 }; 2715 2716 //! \name Initializations 2717 2718 //! \brief Explicit member initialization function 2719 HCP_SLICE_STATE_CMD(); 2720 2721 static const size_t dwSize = 13; 2722 static const size_t byteSize = 52; 2723 }; 2724 2725 //! 2726 //! \brief HCP_BSD_OBJECT 2727 //! \details 2728 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2729 //! Commands. Each HCP command has assigned a media instruction command as 2730 //! defined in DWord 0, BitField 22:16. 2731 //! 2732 //! The HCP_BSD_OBJECT command fetches the HEVC bit stream for a slice 2733 //! starting with the first byte in the slice. The bit stream ends with the 2734 //! last non-zero bit of the frame and does not include any zero-padding at 2735 //! the end of the bit stream. There can be multiple slices in a HEVC frame 2736 //! and thus this command can be issued multiple times per frame. 2737 //! 2738 //! The HCP_BSD_OBJECT command must be the last command issued in the 2739 //! sequence of batch commands before the HCP starts decoding. Prior to 2740 //! issuing this command, it is assumed that all configuration parameters in 2741 //! the HCP have been loaded including workload configuration registers and 2742 //! configuration tables. When this command is issued, the HCP is waiting 2743 //! for bit stream data to be presented to the shift register. 2744 //! 2745 struct HCP_BSD_OBJECT_CMD 2746 { 2747 union 2748 { 2749 struct 2750 { 2751 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2752 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2753 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2754 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2755 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2756 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2757 }; 2758 uint32_t Value; 2759 } DW0; 2760 union 2761 { 2762 struct 2763 { 2764 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 2765 }; 2766 uint32_t Value; 2767 } DW1; 2768 union 2769 { 2770 struct 2771 { 2772 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 2773 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2774 }; 2775 uint32_t Value; 2776 } DW2; 2777 2778 //! \name Local enumerations 2779 2780 enum MEDIA_INSTRUCTION_COMMAND 2781 { 2782 MEDIA_INSTRUCTION_COMMAND_HCPBSDOBJECTSTATE = 32, //!< No additional details 2783 }; 2784 2785 //! \brief MEDIA_INSTRUCTION_OPCODE 2786 //! \details 2787 //! Codec/Engine Name = HCP = 7h 2788 enum MEDIA_INSTRUCTION_OPCODE 2789 { 2790 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2791 }; 2792 2793 enum PIPELINE_TYPE 2794 { 2795 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2796 }; 2797 2798 enum COMMAND_TYPE 2799 { 2800 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2801 }; 2802 2803 //! \name Initializations 2804 2805 //! \brief Explicit member initialization function 2806 HCP_BSD_OBJECT_CMD(); 2807 2808 static const size_t dwSize = 3; 2809 static const size_t byteSize = 12; 2810 }; 2811 2812 //! 2813 //! \brief HCP_VP9_SEGMENT_STATE 2814 //! \details 2815 //! 2816 //! 2817 struct HCP_VP9_SEGMENT_STATE_CMD 2818 { 2819 union 2820 { 2821 struct 2822 { 2823 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2824 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2825 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2826 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2827 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2828 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2829 }; 2830 uint32_t Value; 2831 } DW0; 2832 union 2833 { 2834 struct 2835 { 2836 uint32_t SegmentId : __CODEGEN_BITFIELD( 0, 2) ; //!< Segment ID 2837 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved 2838 }; 2839 uint32_t Value; 2840 } DW1; 2841 union 2842 { 2843 struct 2844 { 2845 uint32_t SegmentSkipped : __CODEGEN_BITFIELD( 0, 0) ; //!< Segment Skipped 2846 uint32_t SegmentReference : __CODEGEN_BITFIELD( 1, 2) ; //!< Segment Reference 2847 uint32_t SegmentReferenceEnabled : __CODEGEN_BITFIELD( 3, 3) ; //!< Segment Reference Enabled 2848 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 2849 }; 2850 uint32_t Value; 2851 } DW2; 2852 union 2853 { 2854 struct 2855 { 2856 uint32_t Filterlevelref0Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef0Mode0 2857 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 2858 uint32_t Filterlevelref0Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef0Mode1 2859 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2860 uint32_t Filterlevelref1Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef1Mode0 2861 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2862 uint32_t Filterlevelref1Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef1Mode1 2863 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2864 }; 2865 uint32_t Value; 2866 } DW3; 2867 union 2868 { 2869 struct 2870 { 2871 uint32_t Filterlevelref2Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef2Mode0 2872 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 2873 uint32_t Filterlevelref2Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef2Mode1 2874 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2875 uint32_t Filterlevelref3Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef3Mode0 2876 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2877 uint32_t Filterlevelref3Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef3Mode1 2878 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2879 }; 2880 uint32_t Value; 2881 } DW4; 2882 union 2883 { 2884 struct 2885 { 2886 uint32_t LumaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Luma DC Quant Scale (Decode mode Only) 2887 uint32_t LumaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Luma AC Quant Scale (Decode mode Only) 2888 }; 2889 uint32_t Value; 2890 } DW5; 2891 union 2892 { 2893 struct 2894 { 2895 uint32_t ChromaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Chroma DC Quant Scale (Decode mode Only) 2896 uint32_t ChromaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Chroma AC Quant Scale (Decode mode Only) 2897 }; 2898 uint32_t Value; 2899 } DW6; 2900 union 2901 { 2902 struct 2903 { 2904 uint32_t SegmentQindexDeltaEncodeModeOnly : __CODEGEN_BITFIELD( 0, 8) ; //!< Segment QIndex Delta (encode mode only) 2905 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2906 uint32_t SegmentLfLevelDeltaEncodeModeOnly : __CODEGEN_BITFIELD(16, 22) ; //!< Segment LF Level Delta (Encode mode Only) 2907 uint32_t Reserved247 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 2908 }; 2909 uint32_t Value; 2910 } DW7; 2911 2912 //! \name Local enumerations 2913 2914 enum MEDIA_INSTRUCTION_COMMAND 2915 { 2916 MEDIA_INSTRUCTION_COMMAND_HCPVP9SEGMENTSTATE = 50, //!< No additional details 2917 }; 2918 2919 //! \brief MEDIA_INSTRUCTION_OPCODE 2920 //! \details 2921 //! Codec/Engine Name = HUC = Bh 2922 enum MEDIA_INSTRUCTION_OPCODE 2923 { 2924 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2925 }; 2926 2927 enum PIPELINE_TYPE 2928 { 2929 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2930 }; 2931 2932 enum COMMAND_TYPE 2933 { 2934 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2935 }; 2936 2937 //! \name Initializations 2938 2939 //! \brief Explicit member initialization function 2940 HCP_VP9_SEGMENT_STATE_CMD(); 2941 2942 static const size_t dwSize = 8; 2943 static const size_t byteSize = 32; 2944 }; 2945 2946 //! 2947 //! \brief HCP_FQM_STATE 2948 //! \details 2949 //! The HCP_FQM_STATE command loads the custom HEVC quantization tables into 2950 //! local RAM and may be issued up to 8 times: 4 scaling list per intra and 2951 //! inter. 2952 //! 2953 //! Driver is responsible for performing the Scaling List division. So, save 2954 //! the division HW cost in HW. The 1/x value is provided in 16-bit 2955 //! fixed-point precision as ((1<<17)/QM +1) >> 1. . 2956 //! 2957 //! Note: FQM is computed as (2^16)/QM. If QM=1, FQM=all 1's. 2958 //! 2959 //! To simplify the design, only a limited number of scaling lists are 2960 //! provided at the PAK interface: default two SizeID0 and two SizeID123 2961 //! (one set for inter and the other set for intra), and the encoder only 2962 //! allows custom entries for these four matrices. The DC value of SizeID2 2963 //! and SizeID3 will be provided. 2964 //! 2965 //! When the scaling_list_enable_flag is set to disable, the scaling matrix 2966 //! is still sent to the PAK, and with all entries programmed to the same 2967 //! value of 16. 2968 //! 2969 //! This is a picture level state command and is issued in encoding 2970 //! processes only. 2971 //! 2972 //! Dwords 2-33 form a table for the DCT coefficients, 2 16-bit 2973 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-9. 2974 //! Size 8x8 for SizeID1/2/3, DWords 2-33. 2975 //! 2976 //! 2977 //! SizeID 0 (Table 4-13) 2978 //! 2979 struct HCP_FQM_STATE_CMD 2980 { 2981 union 2982 { 2983 struct 2984 { 2985 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2986 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2987 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2988 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2989 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2990 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2991 }; 2992 uint32_t Value; 2993 } DW0; 2994 union 2995 { 2996 struct 2997 { 2998 uint32_t IntraInter : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAINTER 2999 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 3000 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 3001 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 3002 uint32_t FqmDcValue1Dc : __CODEGEN_BITFIELD(16, 31) ; //!< FQM DC Value: (1/DC): 3003 }; 3004 uint32_t Value; 3005 } DW1; 3006 uint32_t Quantizermatrix[32]; //!< QuantizerMatrix 3007 3008 //! \name Local enumerations 3009 3010 enum MEDIA_INSTRUCTION_COMMAND 3011 { 3012 MEDIA_INSTRUCTION_COMMAND_HCPFQMSTATE = 5, //!< No additional details 3013 }; 3014 3015 //! \brief MEDIA_INSTRUCTION_OPCODE 3016 //! \details 3017 //! Codec/Engine Name = HCP = 7h 3018 enum MEDIA_INSTRUCTION_OPCODE 3019 { 3020 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3021 }; 3022 3023 enum PIPELINE_TYPE 3024 { 3025 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3026 }; 3027 3028 enum COMMAND_TYPE 3029 { 3030 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3031 }; 3032 3033 //! \brief INTRAINTER 3034 //! \details 3035 //! This field specifies the quant matrix intra or inter type. 3036 enum INTRAINTER 3037 { 3038 INTRAINTER_INTRA = 0, //!< No additional details 3039 INTRAINTER_INTER = 1, //!< No additional details 3040 }; 3041 3042 enum SIZEID 3043 { 3044 SIZEID_SIZEID04X4 = 0, //!< No additional details 3045 SIZEID_SIZEID1_2_3_8X8_16X16_32X32 = 1, //!< No additional details 3046 SIZEID_SIZEID2_FORDCVALUEIN16X16 = 2, //!< No additional details 3047 SIZEID_SIZEID3_FORDCVALUEIN32X32 = 3, //!< No additional details 3048 }; 3049 3050 //! \brief COLOR_COMPONENT 3051 //! \details 3052 //! <p>Luma and Chroma's share the same scaling list and DC value for the 3053 //! same SizeID.</p> 3054 enum COLOR_COMPONENT 3055 { 3056 COLOR_COMPONENT_LUMA = 0, //!< No additional details 3057 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 3058 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 3059 }; 3060 3061 //! \name Initializations 3062 3063 //! \brief Explicit member initialization function 3064 HCP_FQM_STATE_CMD(); 3065 3066 static const size_t dwSize = 34; 3067 static const size_t byteSize = 136; 3068 }; 3069 3070 //! 3071 //! \brief HCP_PAK_INSERT_OBJECT 3072 //! \details 3073 //! It is an encoder only command, operating at bitstream level, before and 3074 //! after SliceData compressed bitstream. It is setup by the header and tail 3075 //! present flags in the Slice State command. If these flags are set and no 3076 //! subsequent PAK_INSERT_OBJECT commands are issued, the pipeline will 3077 //! hang. 3078 //! 3079 //! The HCP_ PAK_ INSERT _OBJECT command supports both inline and indirect 3080 //! data payload, but only one can be active at any time. It is issued to 3081 //! insert a chunk of bits (payload) into the current compressed bitstream 3082 //! output buffer (specified in the HCP_PAK-BSE Object Base Address field of 3083 //! the HCP_IND_OBJ_BASE_ADDR_STATE command) starting at its current write 3084 //! pointer bit position. Hardware will keep track of this write pointer's 3085 //! byte position and the associated next bit insertion position index. 3086 //! 3087 //! It is a variable length command when the payload (data to be inserted) 3088 //! is presented as inline data within the command itself. The inline 3089 //! payload is a multiple of 32-bit (1 DW), as the data bus to the 3090 //! compressed bitstream output buffer is 32-bit wide. 3091 //! 3092 //! The payload data is required to be byte aligned on the left (first 3093 //! transmitted bit order) and may or may not be byte aligned on the right 3094 //! (last transmitted bits). The command will specify the bit offset of the 3095 //! last valid DW. Note that : Stitch Command is used if the beginning 3096 //! position of data is in bit position. When PAK Insert Command is used the 3097 //! beginning position must be in byte position. 3098 //! 3099 //! Multiple insertion commands can be issued back to back in a series. It 3100 //! is host software's responsibility to make sure their corresponding data 3101 //! will properly stitch together to form a valid bitstream. 3102 //! 3103 //! Internally, HCP hardware will keep track of the very last two bytes' 3104 //! (the very last byte can be a partial byte) values of the previous 3105 //! insertion. It is required that the next Insertion Object Command or the 3106 //! next PAK Object Command to perform the start code emulation sequence 3107 //! check and prevention 0x03 byte insertion with this end condition of the 3108 //! previous insertion. 3109 //! 3110 //! The payload data may have already been processed for start code 3111 //! emulation byte insertion, except the possibility of the last 2 bytes 3112 //! plus the very last partial byte (if any). Hence, when hardware 3113 //! performing the concatenation of multiple consecutive insertion commands, 3114 //! or concatenation of an insertion command and a PAK object command, it 3115 //! must check and perform the necessary start code emulation byte insert at 3116 //! the junction. 3117 //! 3118 //! Data to be inserted can be a valid NAL units or a partial NAL unit. It 3119 //! can be any encoded syntax elements bit data before the encoded Slice 3120 //! Data (PAK Object Command) of the current Slice - SPS NAL, PPS NAL, SEI 3121 //! NAL and Other Non-Slice NAL, Leading_Zero_8_bits (as many bytes as there 3122 //! is), Start Code , Slice Header. Any encoded syntax elements bit data 3123 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3124 //! and prior to the next encoded Slice Data of the next Slice or prior to 3125 //! the end of the bitstream, whichever comes first Cabac_Zero_Word or 3126 //! Trailing_Zero_8bits (as many bytes as there is). 3127 //! 3128 //! Certain NAL unit has a minimum byte size requirement. As such the 3129 //! hardware will optionally (enabled by SLICE STATE Command) determines the 3130 //! number of CABAC_ZERO_WORD to be inserted to the end of the current NAL, 3131 //! based on the minimum byte size of a NAL and the actual bin count of the 3132 //! encoded Slice. Since prior to the CABAC_ZERO_WORD insertion, the RBSP or 3133 //! EBSP is already byte-aligned, so each CABAC_ZERO_WORD insertion is 3134 //! actually a 3-byte sequence 0x00 00 03. 3135 //! 3136 //! Context switch interrupt is not supported by this command. 3137 //! 3138 struct HCP_PAK_INSERT_OBJECT_CMD 3139 { 3140 union 3141 { 3142 struct 3143 { 3144 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Dword Length 3145 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3146 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3147 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3148 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3149 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3150 }; 3151 uint32_t Value; 3152 } DW0; 3153 union 3154 { 3155 struct 3156 { 3157 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3158 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3159 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3160 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3161 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 3162 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3163 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< Slice Header Indicator 3164 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3165 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3166 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 3167 uint32_t IndirectPayloadEnable : __CODEGEN_BITFIELD(31, 31) ; //!< INDIRECT_PAYLOAD_ENABLE 3168 }; 3169 uint32_t Value; 3170 } DW1; 3171 3172 //! \name Local enumerations 3173 3174 enum MEDIA_INSTRUCTION_COMMAND 3175 { 3176 MEDIA_INSTRUCTION_COMMAND_HCPPAKINSERTOBJECT = 34, //!< No additional details 3177 }; 3178 3179 //! \brief MEDIA_INSTRUCTION_OPCODE 3180 //! \details 3181 //! Codec/Engine Name = HCP = 7h 3182 enum MEDIA_INSTRUCTION_OPCODE 3183 { 3184 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3185 }; 3186 3187 enum PIPELINE_TYPE 3188 { 3189 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3190 }; 3191 3192 enum COMMAND_TYPE 3193 { 3194 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3195 }; 3196 3197 //! \brief EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3198 //! \details 3199 //! Only valid for HEVC and reserved for VP9. 3200 enum EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 3201 { 3202 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_STARTCODEPREFIX = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between. 3203 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_INSERTIONCOMMAND = 2, //!< Insertion commands, or an insertion command followed by a PAK Object command. 3204 }; 3205 3206 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 3207 //! \details 3208 //! <p>In case this flag is on, bits are NOT accumulated during current 3209 //! access unit coding neither for Cabac Zero Word insertion bits counting 3210 //! or for output in MMIO register 3211 //! HCP_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER.</p> 3212 //! <p>When using HeaderLenghtExcludeFrmSize for header insertion, the 3213 //! software needs to make sure that data comes already with inserted start 3214 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 3215 //! DWORD1 of HCP_PAK_INSERT_OBJECT).</p> 3216 //! <table border="1" cellpadding="0" cellspacing="0" style="width: 100%;" 3217 //! width="100%"> 3218 //! <tbody> 3219 //! <tr> 3220 //! <td> 3221 //! <p align="center"><b>Value</b></p></td> 3222 //! <td> 3223 //! <p align="center"><b style="text-align: 3224 //! -webkit-center;">Description</b></p></td> 3225 //! </tr> 3226 //! <tr> 3227 //! <td> 3228 //! <p>0</p></td> 3229 //! <td> 3230 //! <p>All bits accumulated</p></td> 3231 //! </tr> 3232 //! <tr> 3233 //! <td> 3234 //! <p>1</p></td> 3235 //! <td> 3236 //! <p>Bits during current call are not accumulated</p></td> 3237 //! </tr> 3238 //! </tbody> 3239 //! </table> 3240 //! 3241 //! <p></p> 3242 enum HEADERLENGTHEXCLUDEFRMSIZE_ 3243 { 3244 HEADERLENGTHEXCLUDEFRMSIZE_ALLBITSACCUMULATED = 0, //!< No additional details 3245 HEADERLENGTHEXCLUDEFRMSIZE_BITSDURINGCURRENTCALLARENOTACCUMULATED = 1, //!< No additional details 3246 }; 3247 3248 //! \brief INDIRECT_PAYLOAD_ENABLE 3249 //! \details 3250 //! <p>Only one of these two payload modes can be active at any time.</p> 3251 //! <p>When Slice Size Conformance is enable the Payload(header) must be 3252 //! inline only so this bit set to MBZ.</p> 3253 enum INDIRECT_PAYLOAD_ENABLE 3254 { 3255 INDIRECT_PAYLOAD_ENABLE_INLINEPAYLOADISUSED = 0, //!< No additional details 3256 INDIRECT_PAYLOAD_ENABLE_INDIRECTPAYLOADISUSED = 1, //!< No additional details 3257 }; 3258 3259 //! \name Initializations 3260 3261 //! \brief Explicit member initialization function 3262 HCP_PAK_INSERT_OBJECT_CMD(); 3263 3264 static const size_t dwSize = 2; 3265 static const size_t byteSize = 8; 3266 }; 3267 3268 //! 3269 //! \brief HCP_VP9_PIC_STATE 3270 //! \details 3271 //! 3272 //! 3273 struct HCP_VP9_PIC_STATE_CMD 3274 { 3275 union 3276 { 3277 struct 3278 { 3279 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3280 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3281 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3282 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3283 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3284 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3285 }; 3286 uint32_t Value; 3287 } DW0; 3288 union 3289 { 3290 struct 3291 { 3292 uint32_t FrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Width In Pixels Minus 1 3293 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3294 uint32_t FrameHeightInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Height In Pixels Minus 1 3295 uint32_t Reserved62 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3296 }; 3297 uint32_t Value; 3298 } DW1; 3299 union 3300 { 3301 struct 3302 { 3303 uint32_t FrameType : __CODEGEN_BITFIELD( 0, 0) ; //!< FRAME_TYPE 3304 uint32_t AdaptProbabilitiesFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPT_PROBABILITIES_FLAG 3305 uint32_t IntraonlyFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< IntraOnly Flag 3306 uint32_t AllowHiPrecisionMv : __CODEGEN_BITFIELD( 3, 3) ; //!< ALLOW_HI_PRECISION_MV 3307 uint32_t McompFilterType : __CODEGEN_BITFIELD( 4, 6) ; //!< MCOMP_FILTER_TYPE 3308 uint32_t RefFrameSignBias02 : __CODEGEN_BITFIELD( 7, 9) ; //!< Ref Frame Sign Bias[0..2] 3309 uint32_t UsePrevInFindMvReferences : __CODEGEN_BITFIELD(10, 10) ; //!< Use Prev in Find MV References 3310 uint32_t HybridPredictionMode : __CODEGEN_BITFIELD(11, 11) ; //!< HYBRID_PREDICTION_MODE 3311 uint32_t SelectableTxMode : __CODEGEN_BITFIELD(12, 12) ; //!< SELECTABLE_TX_MODE 3312 uint32_t LastFrameType : __CODEGEN_BITFIELD(13, 13) ; //!< LAST_FRAME_TYPE 3313 uint32_t RefreshFrameContext : __CODEGEN_BITFIELD(14, 14) ; //!< REFRESH_FRAME_CONTEXT 3314 uint32_t ErrorResilientMode : __CODEGEN_BITFIELD(15, 15) ; //!< ERROR_RESILIENT_MODE 3315 uint32_t FrameParallelDecodingMode : __CODEGEN_BITFIELD(16, 16) ; //!< FRAME_PARALLEL_DECODING_MODE 3316 uint32_t FilterLevel : __CODEGEN_BITFIELD(17, 22) ; //!< Filter Level 3317 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(23, 25) ; //!< Sharpness Level 3318 uint32_t SegmentationEnabled : __CODEGEN_BITFIELD(26, 26) ; //!< SEGMENTATION_ENABLED 3319 uint32_t SegmentationUpdateMap : __CODEGEN_BITFIELD(27, 27) ; //!< SEGMENTATION_UPDATE_MAP 3320 uint32_t SegmentationTemporalUpdate : __CODEGEN_BITFIELD(28, 28) ; //!< SEGMENTATION_TEMPORAL_UPDATE 3321 uint32_t LosslessMode : __CODEGEN_BITFIELD(29, 29) ; //!< LOSSLESS_MODE 3322 uint32_t SegmentIdStreamoutEnable : __CODEGEN_BITFIELD(30, 30) ; //!< SEGMENT_ID_STREAMOUT_ENABLE 3323 uint32_t SegmentIdStreaminEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SEGMENT_ID_STREAMIN_ENABLE 3324 }; 3325 uint32_t Value; 3326 } DW2; 3327 union 3328 { 3329 struct 3330 { 3331 uint32_t Log2TileColumn : __CODEGEN_BITFIELD( 0, 3) ; //!< LOG2_TILE_COLUMN 3332 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 3333 uint32_t Log2TileRow : __CODEGEN_BITFIELD( 8, 9) ; //!< LOG2_TILE_ROW 3334 uint32_t Reserved106 : __CODEGEN_BITFIELD(10, 20) ; //!< Reserved 3335 uint32_t SseEnable : __CODEGEN_BITFIELD(21, 21) ; //!< SSE Enable 3336 uint32_t ChromaSamplingFormat : __CODEGEN_BITFIELD(22, 23) ; //!< CHROMA_SAMPLING_FORMAT 3337 uint32_t Bitdepthminus8 : __CODEGEN_BITFIELD(24, 27) ; //!< BITDEPTHMINUS8 3338 uint32_t ProfileLevel : __CODEGEN_BITFIELD(28, 31) ; //!< PROFILE_LEVEL 3339 }; 3340 uint32_t Value; 3341 } DW3; 3342 union 3343 { 3344 struct 3345 { 3346 uint32_t VerticalScaleFactorForLast : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for LAST 3347 uint32_t HorizontalScaleFactorForLast : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for LAST 3348 }; 3349 uint32_t Value; 3350 } DW4; 3351 union 3352 { 3353 struct 3354 { 3355 uint32_t VerticalScaleFactorForGolden : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for GOLDEN 3356 uint32_t HorizontalScaleFactorForGolden : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for GOLDEN 3357 }; 3358 uint32_t Value; 3359 } DW5; 3360 union 3361 { 3362 struct 3363 { 3364 uint32_t VerticalScaleFactorForAltref : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for ALTREF 3365 uint32_t HorizontalScaleFactorForAltref : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for ALTREF 3366 }; 3367 uint32_t Value; 3368 } DW6; 3369 union 3370 { 3371 struct 3372 { 3373 uint32_t LastFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Last Frame Width In Pixels Minus 1 3374 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3375 uint32_t LastFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Last Frame Hieght In Pixels Minus 1 3376 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3377 }; 3378 uint32_t Value; 3379 } DW7; 3380 union 3381 { 3382 struct 3383 { 3384 uint32_t GoldenFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Golden Frame Width In Pixels Minus 1 3385 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3386 uint32_t GoldenFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Golden Frame Hieght In Pixels Minus 1 3387 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3388 }; 3389 uint32_t Value; 3390 } DW8; 3391 union 3392 { 3393 struct 3394 { 3395 uint32_t AltrefFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Altref Frame Width In Pixels Minus 1 3396 uint32_t Reserved302 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3397 uint32_t AltrefFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Altref Frame Hieght In Pixels Minus 1 3398 uint32_t Reserved318 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3399 }; 3400 uint32_t Value; 3401 } DW9; 3402 union 3403 { 3404 struct 3405 { 3406 uint32_t UncompressedHeaderLengthInBytes70 : __CODEGEN_BITFIELD( 0, 7) ; //!< Uncompressed Header Length in Bytes [7:0] 3407 uint32_t Reserved328 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3408 uint32_t FirstPartitionSizeInBytes150 : __CODEGEN_BITFIELD(16, 31) ; //!< First Partition Size in Bytes [15:0] 3409 }; 3410 uint32_t Value; 3411 } DW10; 3412 union 3413 { 3414 struct 3415 { 3416 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3417 uint32_t MotionCompScalingEnableBit : __CODEGEN_BITFIELD( 1, 1) ; //!< MOTION_COMP_SCALING_ENABLE_BIT 3418 uint32_t Reserved354 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 3419 }; 3420 uint32_t Value; 3421 } DW11; 3422 union 3423 { 3424 struct 3425 { 3426 uint32_t Reserved384 ; //!< Reserved 3427 }; 3428 uint32_t Value; 3429 } DW12; 3430 union 3431 { 3432 struct 3433 { 3434 uint32_t CompressedHeaderBinCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Compressed header BIN count 3435 uint32_t BaseQIndexSameAsLumaAc : __CODEGEN_BITFIELD(16, 23) ; //!< Base Q Index (Same as Luma AC) 3436 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< Tail Insertion Enable 3437 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(25, 25) ; //!< Header Insertion Enable 3438 uint32_t Reserved442 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 3439 }; 3440 uint32_t Value; 3441 } DW13; 3442 union 3443 { 3444 struct 3445 { 3446 uint32_t ChromaacQindexdelta : __CODEGEN_BITFIELD( 0, 4) ; //!< ChromaAC_QindexDelta 3447 uint32_t Reserved453 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved 3448 uint32_t ChromadcQindexdelta : __CODEGEN_BITFIELD( 8, 12) ; //!< ChromaDC_QindexDelta 3449 uint32_t Reserved461 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 3450 uint32_t LumaDcQIndexDelta : __CODEGEN_BITFIELD(16, 20) ; //!< Luma DC Q Index Delta 3451 uint32_t Reserved469 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 3452 }; 3453 uint32_t Value; 3454 } DW14; 3455 union 3456 { 3457 struct 3458 { 3459 uint32_t LfRefDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF_ref_delta0 3460 uint32_t Reserved487 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3461 uint32_t LfRefDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF_ref_delta1 3462 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3463 uint32_t LfRefDelta2 : __CODEGEN_BITFIELD(16, 22) ; //!< LF_ref_delta2 3464 uint32_t Reserved503 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 3465 uint32_t LfRefDelta3 : __CODEGEN_BITFIELD(24, 30) ; //!< LF_ref_delta3 3466 uint32_t Reserved511 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3467 }; 3468 uint32_t Value; 3469 } DW15; 3470 union 3471 { 3472 struct 3473 { 3474 uint32_t LfModeDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF Mode Delta 0 3475 uint32_t Reserved519 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3476 uint32_t LfModeDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF Mode Delta 1 3477 uint32_t Reserved527 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 3478 }; 3479 uint32_t Value; 3480 } DW16; 3481 union 3482 { 3483 struct 3484 { 3485 uint32_t Bitoffsetforlfrefdelta : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForLFRefDelta 3486 uint32_t Bitoffsetforlfmodedelta : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFModeDelta 3487 }; 3488 uint32_t Value; 3489 } DW17; 3490 union 3491 { 3492 struct 3493 { 3494 uint32_t Bitoffsetforqindex : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForQindex 3495 uint32_t Bitoffsetforlflevel : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFLevel 3496 }; 3497 uint32_t Value; 3498 } DW18; 3499 union 3500 { 3501 struct 3502 { 3503 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 3504 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 3505 uint32_t VdencPakOnlyPass : __CODEGEN_BITFIELD(17, 17) ; //!< VDENC PAK_ONLY PASS 3506 uint32_t Reserved626 : __CODEGEN_BITFIELD(18, 24) ; //!< Reserved 3507 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3508 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3509 uint32_t Reserved635 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3510 }; 3511 uint32_t Value; 3512 } DW19; 3513 union 3514 { 3515 struct 3516 { 3517 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 3518 uint32_t Reserved654 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3519 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 3520 }; 3521 uint32_t Value; 3522 } DW20; 3523 union 3524 { 3525 struct 3526 { 3527 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 3528 uint32_t Reserved686 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3529 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 3530 }; 3531 uint32_t Value; 3532 } DW21; 3533 union 3534 { 3535 struct 3536 { 3537 uint64_t Framedeltaqindexmax ; //!< FrameDeltaQindexMax 3538 }; 3539 uint32_t Value[2]; 3540 } DW22_23; 3541 union 3542 { 3543 struct 3544 { 3545 uint32_t Framedeltaqindexmin ; //!< FrameDeltaQindexMin 3546 }; 3547 uint32_t Value; 3548 } DW24; 3549 union 3550 { 3551 struct 3552 { 3553 uint64_t Framedeltalfmax ; //!< FrameDeltaLFMax 3554 }; 3555 uint32_t Value[2]; 3556 } DW25_26; 3557 union 3558 { 3559 struct 3560 { 3561 uint32_t Framedeltalfmin ; //!< FrameDeltaLFMin 3562 }; 3563 uint32_t Value; 3564 } DW27; 3565 union 3566 { 3567 struct 3568 { 3569 uint64_t Framedeltaqindexlfmaxrange ; //!< FrameDeltaQindexLFMaxRange 3570 }; 3571 uint32_t Value[2]; 3572 } DW28_29; 3573 union 3574 { 3575 struct 3576 { 3577 uint32_t Framedeltaqindexlfminrange ; //!< FrameDeltaQindexLFMinRange 3578 }; 3579 uint32_t Value; 3580 } DW30; 3581 union 3582 { 3583 struct 3584 { 3585 uint32_t Minframsize : __CODEGEN_BITFIELD( 0, 15) ; //!< MinFramSize 3586 uint32_t Reserved1008 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 3587 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 3588 }; 3589 uint32_t Value; 3590 } DW31; 3591 union 3592 { 3593 struct 3594 { 3595 uint32_t Bitoffsetforfirstpartitionsize : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForFirstPartitionSize 3596 uint32_t Reserved1040 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 3597 }; 3598 uint32_t Value; 3599 } DW32; 3600 union 3601 { 3602 struct 3603 { 3604 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 3605 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 3606 }; 3607 uint32_t Value; 3608 } DW33; 3609 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 3610 3611 //! \name Local enumerations 3612 3613 enum MEDIA_INSTRUCTION_COMMAND 3614 { 3615 MEDIA_INSTRUCTION_COMMAND_HCPVP9PICSTATE = 48, //!< No additional details 3616 }; 3617 3618 //! \brief MEDIA_INSTRUCTION_OPCODE 3619 //! \details 3620 //! Codec/Engine Name = HUC = Bh 3621 enum MEDIA_INSTRUCTION_OPCODE 3622 { 3623 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3624 }; 3625 3626 enum PIPELINE_TYPE 3627 { 3628 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3629 }; 3630 3631 enum COMMAND_TYPE 3632 { 3633 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3634 }; 3635 3636 //! \brief FRAME_TYPE 3637 //! \details 3638 //! Specifies the VP9 frame type 3639 enum FRAME_TYPE 3640 { 3641 FRAME_TYPE_KEYFRAME = 0, //!< No additional details 3642 FRAME_TYPE_INTERFRAME = 1, //!< No additional details 3643 }; 3644 3645 //! \brief ADAPT_PROBABILITIES_FLAG 3646 //! \details 3647 //! Indicates that the probabilities used to decode this frame should be 3648 //! adapted 3649 enum ADAPT_PROBABILITIES_FLAG 3650 { 3651 ADAPT_PROBABILITIES_FLAG_0DONOTADAPT_ERRORRESILIENTORFRAMEPARALLELMODEARESET = 0, //!< No additional details 3652 ADAPT_PROBABILITIES_FLAG_1ADAPT_NOTERRORRESILIENTANDNOTFRAMEPARALLELMODE = 1, //!< No additional details 3653 }; 3654 3655 //! \brief ALLOW_HI_PRECISION_MV 3656 //! \details 3657 //! Indicate high precision mode for Motion Vector prediction 3658 enum ALLOW_HI_PRECISION_MV 3659 { 3660 ALLOW_HI_PRECISION_MV_NORMALMODE = 0, //!< No additional details 3661 ALLOW_HI_PRECISION_MV_HIGHPRECISIONMODE = 1, //!< No additional details 3662 }; 3663 3664 //! \brief MCOMP_FILTER_TYPE 3665 //! \details 3666 //! Indicate Motion Compensation Filter type. 3667 enum MCOMP_FILTER_TYPE 3668 { 3669 MCOMP_FILTER_TYPE_EIGHT_TAP = 0, //!< No additional details 3670 MCOMP_FILTER_TYPE_EIGHT_TAP_SMOOTH = 1, //!< No additional details 3671 MCOMP_FILTER_TYPE_EIGHT_TAP_SHARP = 2, //!< No additional details 3672 MCOMP_FILTER_TYPE_BILINEAR = 3, //!< No additional details 3673 MCOMP_FILTER_TYPE_SWITCHABLE = 4, //!< No additional details 3674 }; 3675 3676 //! \brief HYBRID_PREDICTION_MODE 3677 //! \details 3678 //! Indicates if comp_pred_mode is hybrid 3679 enum HYBRID_PREDICTION_MODE 3680 { 3681 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERDOESNOTPACKCOMPPREDMODEINTERPREDCOMPINPAKOBJINTOBITSTREAM = 0, //!< No additional details 3682 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERPACKSCOMPPREDMODEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 1, //!< No additional details 3683 }; 3684 3685 //! \brief SELECTABLE_TX_MODE 3686 //! \details 3687 //! Indicates if tx_mode is selectable 3688 enum SELECTABLE_TX_MODE 3689 { 3690 SELECTABLE_TX_MODE_ENCODERDOESNOTPACKTUSIZEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 0, //!< No additional details 3691 SELECTABLE_TX_MODE_ENCODERPACKSTUSIZEINTOBITSTREAM = 1, //!< No additional details 3692 }; 3693 3694 //! \brief LAST_FRAME_TYPE 3695 //! \details 3696 //! <p>It indicates the frame type of previous frame (Key or Non-Key 3697 //! Frame)</p> 3698 enum LAST_FRAME_TYPE 3699 { 3700 LAST_FRAME_TYPE_KEYFRAME = 0, //!< No additional details 3701 LAST_FRAME_TYPE_NONKEYFRAME = 1, //!< No additional details 3702 }; 3703 3704 //! \brief REFRESH_FRAME_CONTEXT 3705 //! \details 3706 //! <p>Indicates if Frame Context should be refresh. This bit should come 3707 //! from Uncompressed header</p> 3708 enum REFRESH_FRAME_CONTEXT 3709 { 3710 REFRESH_FRAME_CONTEXT_DISABLE = 0, //!< No additional details 3711 REFRESH_FRAME_CONTEXT_ENABLE = 1, //!< No additional details 3712 }; 3713 3714 //! \brief ERROR_RESILIENT_MODE 3715 //! \details 3716 //! <p>Indicates if error resilient mode is enabled. This bit should come 3717 //! from Uncompressed header.When error resilient is 1, Frame Parallel 3718 //! Decoding Mode will be 1, and Refresh Frame Context will be 0.When error 3719 //! resilient is 0, Frame Parallel Decoding Mode and Refresh Frame Context 3720 //! read from bit stream.Together with Frame Parallel Decoding mode, they 3721 //! decide the value of AdaptProbabilityFlag.</p> 3722 enum ERROR_RESILIENT_MODE 3723 { 3724 ERROR_RESILIENT_MODE_DISABLE = 0, //!< No additional details 3725 ERROR_RESILIENT_MODE_ENABLE = 1, //!< No additional details 3726 }; 3727 3728 //! \brief FRAME_PARALLEL_DECODING_MODE 3729 //! \details 3730 //! <p>Indicates if parallel decoding mode is enabled. This bit should come 3731 //! from Uncompressed header. Together with Error Resilient mode, they 3732 //! decide the value of AdaptProbabilityFlag.</p> 3733 enum FRAME_PARALLEL_DECODING_MODE 3734 { 3735 FRAME_PARALLEL_DECODING_MODE_DISABLE = 0, //!< No additional details 3736 FRAME_PARALLEL_DECODING_MODE_ENABLE = 1, //!< No additional details 3737 }; 3738 3739 //! \brief SEGMENTATION_ENABLED 3740 //! \details 3741 //! Indicate if segementation is enabled or not 3742 enum SEGMENTATION_ENABLED 3743 { 3744 SEGMENTATION_ENABLED_ALLBLOCKSAREIMPLIEDTOBELONGTOSEGMENT0 = 0, //!< No additional details 3745 SEGMENTATION_ENABLED_SEGIDDETERMINATIONDEPENDSONSEGMENTATIONUPDATEMAPSETTING = 1, //!< No additional details 3746 }; 3747 3748 //! \brief SEGMENTATION_UPDATE_MAP 3749 //! \details 3750 //! Indicates how hardware determines segmentation ID 3751 enum SEGMENTATION_UPDATE_MAP 3752 { 3753 SEGMENTATION_UPDATE_MAP_UNNAMED0 = 0, //!< Intra block: segment ID is zero Inter block: get segment ID from previous frame (streamIN) 3754 SEGMENTATION_UPDATE_MAP_UNNAMED1 = 1, //!< Intra block: decode segment ID from bitstream. Inter block: determins from segmentation_temporal_update setting 3755 }; 3756 3757 //! \brief SEGMENTATION_TEMPORAL_UPDATE 3758 //! \details 3759 //! Indicates whether segID is decoding from bitstream or predicted from 3760 //! previous frame. 3761 enum SEGMENTATION_TEMPORAL_UPDATE 3762 { 3763 SEGMENTATION_TEMPORAL_UPDATE_DECODESEGIDFROMBITSTREAM = 0, //!< No additional details 3764 SEGMENTATION_TEMPORAL_UPDATE_GETSEGIDEITHERFROMBITSTREAMORFROMPREVIOUSFRAME = 1, //!< No additional details 3765 }; 3766 3767 //! \brief LOSSLESS_MODE 3768 //! \details 3769 //! This bitSet to indicate lossless coding mode. 3770 enum LOSSLESS_MODE 3771 { 3772 LOSSLESS_MODE_NORMALMODE = 0, //!< No additional details 3773 LOSSLESS_MODE_LOLESSMODE = 1, //!< No additional details 3774 }; 3775 3776 //! \brief SEGMENT_ID_STREAMOUT_ENABLE 3777 //! \details 3778 //! Indicates SegmentID of current frame needs to be streamOut for next 3779 //! frame 3780 enum SEGMENT_ID_STREAMOUT_ENABLE 3781 { 3782 SEGMENT_ID_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 3783 SEGMENT_ID_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 3784 }; 3785 3786 //! \brief SEGMENT_ID_STREAMIN_ENABLE 3787 //! \details 3788 //! Indicates SegmentID from previous frame needs to be streamIn for Segment 3789 //! ID prediction 3790 enum SEGMENT_ID_STREAMIN_ENABLE 3791 { 3792 SEGMENT_ID_STREAMIN_ENABLE_DISABLE = 0, //!< No additional details 3793 SEGMENT_ID_STREAMIN_ENABLE_ENABLE = 1, //!< No additional details 3794 }; 3795 3796 //! \brief LOG2_TILE_COLUMN 3797 //! \details 3798 //! This indicates the number of tile rows (log2). 3799 enum LOG2_TILE_COLUMN 3800 { 3801 LOG2_TILE_COLUMN_1TILECOLUMN = 0, //!< No additional details 3802 LOG2_TILE_COLUMN_2TILECOLUMN = 1, //!< No additional details 3803 LOG2_TILE_COLUMN_4TILECOLUMN = 2, //!< No additional details 3804 LOG2_TILE_COLUMN_8TILECOLUMN = 3, //!< No additional details 3805 LOG2_TILE_COLUMN_16TILECOLUMN = 4, //!< No additional details 3806 LOG2_TILE_COLUMN_32TILECOLUMN = 5, //!< No additional details 3807 LOG2_TILE_COLUMN_64TILECOLUMN = 6, //!< No additional details 3808 }; 3809 3810 //! \brief LOG2_TILE_ROW 3811 //! \details 3812 //! This indicates the number of tile rows (log2). 3813 enum LOG2_TILE_ROW 3814 { 3815 LOG2_TILE_ROW_1TILEROW = 0, //!< No additional details 3816 LOG2_TILE_ROW_2TILEROW = 1, //!< No additional details 3817 LOG2_TILE_ROW_4TILEROW = 2, //!< No additional details 3818 }; 3819 3820 //! \brief CHROMA_SAMPLING_FORMAT 3821 //! \details 3822 //! This indicates the chroma sampling format of the bitstream 3823 enum CHROMA_SAMPLING_FORMAT 3824 { 3825 CHROMA_SAMPLING_FORMAT_FORMAT420 = 0, //!< No additional details 3826 CHROMA_SAMPLING_FORMAT_FORMAT444 = 2, //!< No additional details 3827 }; 3828 3829 //! \brief BITDEPTHMINUS8 3830 //! \details 3831 //! This indicates the bitdepth (minus 8) of the pixels 3832 enum BITDEPTHMINUS8 3833 { 3834 BITDEPTHMINUS8_BITDEPTH8 = 0, //!< No additional details 3835 BITDEPTHMINUS8_BITDEPTH10 = 2, //!< No additional details 3836 BITDEPTHMINUS8_BITDEPTH12 = 4, //!< No additional details 3837 }; 3838 3839 //! \brief PROFILE_LEVEL 3840 //! \details 3841 //! This indicates VP9 Profile level from bitstream 3842 enum PROFILE_LEVEL 3843 { 3844 PROFILE_LEVEL_PROFILE0 = 0, //!< Profile 0 only supports 8 bit 420 only 3845 PROFILE_LEVEL_PROFILE1 = 1, //!< Profile 1 only supports 8 bit 444 only 3846 PROFILE_LEVEL_PROFILE2 = 2, //!< Profile 2 only supports 10 bits 420 only 3847 PROFILE_LEVEL_PROFILE3 = 3, //!< Profile 3 only supports 10-bit 444 only 3848 }; 3849 3850 //! \brief MOTION_COMP_SCALING_ENABLE_BIT 3851 //! \details 3852 //! This bit must be set to "1" 3853 enum MOTION_COMP_SCALING_ENABLE_BIT 3854 { 3855 MOTION_COMP_SCALING_ENABLE_BIT_ENABLE = 1, //!< This enables Motion Comp Scaling 3856 }; 3857 3858 //! \brief NONFIRSTPASSFLAG 3859 //! \details 3860 //! This signals the current pass is not the first pass. It will imply 3861 //! designate HW behavior. 3862 enum NONFIRSTPASSFLAG 3863 { 3864 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 3865 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 3866 }; 3867 3868 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3869 //! \details 3870 //! This is a mask bit controlling if the condition of frame level bit count 3871 //! exceeds FrameBitRateMax. 3872 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3873 { 3874 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_VP9_IMAGE_STATUS control register. 3875 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit 1 of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit Rate Maximum limit. 3876 }; 3877 3878 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3879 //! \details 3880 //! This is a mask bit controlling if the condition of frame level bit count 3881 //! is less than FrameBitRateMin. 3882 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3883 { 3884 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register. 3885 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. 3886 }; 3887 3888 //! \brief FRAMEBITRATEMAXUNIT 3889 //! \details 3890 //! This field is the Frame Bitrate Maximum Limit Units. 3891 enum FRAMEBITRATEMAXUNIT 3892 { 3893 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 3894 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4Kbyte unit 3895 }; 3896 3897 //! \brief FRAMEBITRATEMINUNIT 3898 //! \details 3899 //! This field is the Frame Bitrate Maximum Limit Units. 3900 enum FRAMEBITRATEMINUNIT 3901 { 3902 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 3903 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4Kbyte unit 3904 }; 3905 3906 //! \brief MINFRAMESIZEUNITS 3907 //! \details 3908 //! This field is the Minimum Frame Size Units 3909 enum MINFRAMESIZEUNITS 3910 { 3911 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 3912 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 4Kbytes. 3913 MINFRAMESIZEUNITS_COMAPTIBILITYMODE = 2, //!< No additional details 3914 MINFRAMESIZEUNITS_6BYTES = 3, //!< No additional details 3915 }; 3916 3917 //! \name Initializations 3918 3919 //! \brief Explicit member initialization function 3920 HCP_VP9_PIC_STATE_CMD(); 3921 3922 static const size_t dwSize = 42; 3923 static const size_t byteSize = 168; 3924 }; 3925 3926 //! 3927 //! \brief HEVC_VP9_RDOQ_LAMBDA_FIELDS 3928 //! \details 3929 //! 3930 //! 3931 struct HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD 3932 { 3933 union 3934 { 3935 struct 3936 { 3937 uint32_t Lambdavalue0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LambdaValue0 3938 uint32_t Lambdavalue1 : __CODEGEN_BITFIELD(16, 31) ; //!< LambdaValue1 3939 }; 3940 uint32_t Value; 3941 } DW0; 3942 3943 //! \name Local enumerations 3944 3945 //! \name Initializations 3946 3947 //! \brief Explicit member initialization function 3948 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD(); 3949 3950 static const size_t dwSize = 1; 3951 static const size_t byteSize = 4; 3952 }; 3953 3954 //! 3955 //! \brief HEVC_VP9_RDOQ_STATE 3956 //! \details 3957 //! 3958 //! 3959 struct HEVC_VP9_RDOQ_STATE_CMD 3960 { 3961 union 3962 { 3963 struct 3964 { 3965 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3966 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3967 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3968 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3969 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3970 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3971 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3972 }; 3973 uint32_t Value; 3974 } DW0; 3975 union 3976 { 3977 struct 3978 { 3979 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 3980 uint32_t DisableHtqPerformanceFix1 : __CODEGEN_BITFIELD(30, 30) ; //!< Disable HTQ performance fix1 3981 uint32_t DisableHtqPerformanceFix0 : __CODEGEN_BITFIELD(31, 31) ; //!< Disable HTQ performance fix0 3982 }; 3983 uint32_t Value; 3984 } DW1; 3985 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda[32]; //!< DW2..33, IntraLumaLambda 3986 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda[32]; //!< DW34..65, IntraChromaLambda 3987 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda[32]; //!< DW66..97, InterLumaLambda 3988 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda[32]; //!< DW98..129, InterChromaLambda 3989 3990 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda12bit[6]; //!< DW130..135, IntraLumaLambda 3991 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda12bit[6]; //!< DW136..141, IntraChromaLambda 3992 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda12bit[6]; //!< DW142..147, InterLumaLambda 3993 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda12bit[6]; //!< DW148..153, InterChromaLambda 3994 3995 //! \name Local enumerations 3996 3997 enum SUBOPB 3998 { 3999 SUBOPB_UNNAMED8 = 8, //!< No additional details 4000 }; 4001 4002 enum SUBOPA 4003 { 4004 SUBOPA_UNNAMED0 = 0, //!< No additional details 4005 }; 4006 4007 //! \brief OPCODE 4008 //! \details 4009 //! Codec/Engine Name = HCP = 7h 4010 enum OPCODE 4011 { 4012 OPCODE_UNNAMED7 = 7, //!< No additional details 4013 }; 4014 4015 //! \brief PIPELINE 4016 //! \details 4017 //! MFX_COMMON 4018 enum PIPELINE 4019 { 4020 PIPELINE_UNNAMED2 = 2, //!< No additional details 4021 }; 4022 4023 //! \brief COMMAND_TYPE 4024 //! \details 4025 //! PARALLEL_VIDEO_PIPE 4026 enum COMMAND_TYPE 4027 { 4028 COMMAND_TYPE_UNNAMED3 = 3, //!< No additional details 4029 }; 4030 4031 //! \name Initializations 4032 4033 //! \brief Explicit member initialization function 4034 HEVC_VP9_RDOQ_STATE_CMD(); 4035 4036 static const size_t dwSize = 154; 4037 static const size_t byteSize = 616; 4038 }; 4039 4040 //! 4041 //! \brief HCP_TILE_CODING 4042 //! \details 4043 //! This command is used for both HEVC and VP9 codecs 4044 //! 4045 struct HCP_TILE_CODING_CMD 4046 { 4047 union 4048 { 4049 struct 4050 { 4051 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4052 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4053 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4054 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4055 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4056 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4057 }; 4058 uint32_t Value; 4059 } DW0; 4060 union 4061 { 4062 struct 4063 { 4064 uint32_t NumberOfActiveBePipes : __CODEGEN_BITFIELD( 0, 7) ; //!< Number of Active BE Pipes 4065 uint32_t TileRowStoreSelect : __CODEGEN_BITFIELD( 8, 8) ; //!< Tile Row store Select 4066 uint32_t TileColumnStoreSelect : __CODEGEN_BITFIELD( 9, 9) ; //!< Tile Column store Select 4067 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved MBZ 4068 uint32_t NumOfTileColumnsInAFrame : __CODEGEN_BITFIELD(16, 31) ; //!< Num of Tile columns in a Frame 4069 }; 4070 uint32_t Value; 4071 } DW1; 4072 union 4073 { 4074 struct 4075 { 4076 uint32_t TileColumnPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< Tile Column Position 4077 uint32_t NonFirstPassTile : __CODEGEN_BITFIELD(10, 10) ; //!< Non First Pass Tile 4078 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4079 uint32_t TileRowPosition : __CODEGEN_BITFIELD(16, 25) ; //!< Tile Row Position 4080 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 29) ; //!< Reserved 4081 uint32_t Islasttileofrow : __CODEGEN_BITFIELD(30, 30) ; //!< IsLastTileOfRow 4082 uint32_t Islasttileofcolumn : __CODEGEN_BITFIELD(31, 31) ; //!< IsLastTileOfColumn 4083 }; 4084 uint32_t Value; 4085 } DW2; 4086 union 4087 { 4088 struct 4089 { 4090 uint32_t Tileheightinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< TileHeightInMinCbMinus1 4091 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 4092 uint32_t Tilewidthinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< TileWidthInMinCbMinus1 4093 uint32_t Reserved123 : __CODEGEN_BITFIELD(27, 30) ; //!< Reserved 4094 uint32_t LastpassoftileValidationonly : __CODEGEN_BITFIELD(31, 31) ; //!< LastPassOfTile (ValidationOnly) 4095 }; 4096 uint32_t Value; 4097 } DW3; 4098 union 4099 { 4100 struct 4101 { 4102 uint32_t BitstreamByteOffsetEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Bitstream Byte Offset Enable 4103 uint32_t Reserved129 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 4104 uint32_t BitstreamByteOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitstream Byte Offset 4105 }; 4106 uint32_t Value; 4107 } DW4; 4108 union 4109 { 4110 struct 4111 { 4112 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4113 uint32_t PakFrameStatisticsOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< PAK Frame Statistics Offset 4114 }; 4115 uint32_t Value; 4116 } DW5; 4117 union 4118 { 4119 struct 4120 { 4121 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4122 uint32_t CuLevelStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU Level Streamout Offset 4123 }; 4124 uint32_t Value; 4125 } DW6; 4126 union 4127 { 4128 struct 4129 { 4130 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4131 uint32_t SliceSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Slice Size Streamout Offset 4132 }; 4133 uint32_t Value; 4134 } DW7; 4135 union 4136 { 4137 struct 4138 { 4139 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4140 uint32_t CuRecordOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU record offset 4141 }; 4142 uint32_t Value; 4143 } DW8; 4144 union 4145 { 4146 struct 4147 { 4148 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4149 uint32_t SseRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SSE RowStore offset 4150 }; 4151 uint32_t Value; 4152 } DW9; 4153 union 4154 { 4155 struct 4156 { 4157 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4158 uint32_t SaoRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SAO RowStore offset 4159 }; 4160 uint32_t Value; 4161 } DW10; 4162 union 4163 { 4164 struct 4165 { 4166 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4167 uint32_t TileSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Size StreamOut Offset 4168 }; 4169 uint32_t Value; 4170 } DW11; 4171 union 4172 { 4173 struct 4174 { 4175 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4176 uint32_t Vp9ProbabilityCounterStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< VP9 Probability Counter Streamout Offset 4177 }; 4178 uint32_t Value; 4179 } DW12; 4180 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySynchronizeBufferBaseAddress; //!< DW13..14, HCP Scalability Synchronize Buffer - Base Address 4181 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySynchronizeBufferAttributes; //!< DW15, HCP Scalability Synchronize Buffer - Attributes 4182 union 4183 { 4184 struct 4185 { 4186 uint32_t Reserved512 ; //!< Reserved 4187 }; 4188 uint32_t Value; 4189 } DW16; 4190 union 4191 { 4192 struct 4193 { 4194 uint32_t Reserved544 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 4195 uint32_t TileNumber : __CODEGEN_BITFIELD( 8, 13) ; //!< Tile number 4196 uint32_t FrameNumber : __CODEGEN_BITFIELD(14, 17) ; //!< Frame Number 4197 uint32_t Reserved562 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 4198 }; 4199 uint32_t Value; 4200 } DW17; 4201 union 4202 { 4203 struct 4204 { 4205 uint32_t TilemetadataDw1 ; //!< TileMetaData_DW1 4206 }; 4207 uint32_t Value; 4208 } DW18; 4209 union 4210 { 4211 struct 4212 { 4213 uint32_t TilemetadataDw2 ; //!< TileMetaData_DW2 4214 }; 4215 uint32_t Value; 4216 } DW19; 4217 4218 //! \name Local enumerations 4219 4220 enum MEDIA_INSTRUCTION_COMMAND 4221 { 4222 MEDIA_INSTRUCTION_COMMAND_HCPTILECODING = 21, //!< No additional details 4223 }; 4224 4225 enum MEDIA_INSTRUCTION_OPCODE 4226 { 4227 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4228 }; 4229 4230 enum PIPELINE_TYPE 4231 { 4232 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4233 }; 4234 4235 enum COMMAND_TYPE 4236 { 4237 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4238 }; 4239 4240 //! \name Initializations 4241 4242 //! \brief Explicit member initialization function 4243 HCP_TILE_CODING_CMD(); 4244 4245 static const size_t dwSize = 20; 4246 static const size_t byteSize = 80; 4247 }; 4248 4249 //! 4250 //! \brief VDENC_CONTROL_STATE 4251 //! \details 4252 //! 4253 //! 4254 struct VDENC_CONTROL_STATE_CMD 4255 { 4256 union 4257 { 4258 struct 4259 { 4260 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4261 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4262 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4263 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4264 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4265 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4266 }; 4267 uint32_t Value; 4268 } DW0; 4269 union 4270 { 4271 struct 4272 { 4273 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 4274 uint32_t VdencInitialization : __CODEGEN_BITFIELD( 1, 1) ; //!< VDenc Initialization 4275 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 4276 }; 4277 uint32_t Value; 4278 } DW1; 4279 4280 //! \name Local enumerations 4281 4282 enum MEDIA_INSTRUCTION_COMMAND 4283 { 4284 MEDIA_INSTRUCTION_COMMAND_VDCONTROLSTATEFORVDNEC = 11, //!< No additional details 4285 }; 4286 4287 //! \brief MEDIA_INSTRUCTION_OPCODE 4288 //! \details 4289 //! <p></p> 4290 //! <p>Codec/Engine Name = VDNEC = 1h;</p> 4291 enum MEDIA_INSTRUCTION_OPCODE 4292 { 4293 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAMEFORVDENC = 1, //!< No additional details 4294 }; 4295 4296 enum PIPELINE_TYPE 4297 { 4298 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4299 }; 4300 4301 enum COMMAND_TYPE 4302 { 4303 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4304 }; 4305 4306 //! \name Initializations 4307 4308 //! \brief Explicit member initialization function 4309 VDENC_CONTROL_STATE_CMD(); 4310 4311 static const size_t dwSize = 2; 4312 static const size_t byteSize = 8; 4313 }; 4314 4315 //! 4316 //! \brief HCP_PALETTE_INITIALIZER_STATE 4317 //! \details 4318 //! The HCP is selected with theMedia Instruction Opcode "7h"for all HCP 4319 //! Commands. Each HCP command has assigned a media instruction command as 4320 //! defined in DWord 0, BitField 22:16. 4321 //! 4322 //! The HCP_PALETTE_INITIALIZER_STATE command loads in the SCC Palette 4323 //! Initilizer Table to the HW. 4324 //! Decoder only command. 4325 //! 4326 //! Dword#2 - 193form a fixed size table for the Palette Initializer Table. 4327 //! Max PaletteInitializer Table is 128entries. Each entry has 3 components 4328 //! (Y, Cb and Cr) for a color. 4329 //! Each component is 16-bits, even though currently only support up to 4330 //! 10-bit SCC extension. The upper (higher bits) 6 bits are set to zero - 4331 //! that is Least Significant Bit alignment. 4332 //! Each entry of thePalette Initializer Table will consume 1.5 Dwords. 4333 //! Every two entries will consume 2 Dwords. Hence, total requires 96 4334 //! Dwords. 4335 //! Dword#2 Bit 31 Cb#0 15:0 Luma#0 15:0 Bit 0 4336 //! Dword#3 Bit 31 Luma#115:0 Cr#015:0 Bit 0 4337 //! Dword#4 Bit 31 Cr#115:0 Cb#115:0 Bit 0 4338 //! Dword#2 correspondsto the entry# 0 of thePalette Initializer Table. 4339 //! Dword#193correspondsto the entry# 127of thePalette Initializer Table. 4340 //! 4341 //! Palette Initialization needs to happen at the beginning of each 4342 //! frame/tiles or start of each independent slice. Palette initialization 4343 //! is not needed at the start of dependent slices (except the start of a 4344 //! new tiles since each tile needs to re-initialize the palette list) and 4345 //! the palette list is inherited from previous slice. 4346 //! The following is the programming restriction: 4347 //! (1) Palette Initialization commandmust be programmedin palette mode at 4348 //! the beginning of each frame and tiles (regardless if the slice 4349 //! isindependent/dependent)and also the start of each independent slices. 4350 //! (2) Palette Initialization command must not be programmed for dependent 4351 //! slices except the dependent slices are start of tiles (first slice in 4352 //! frame must be independent slice). 4353 //! 4354 //! 4355 struct HCP_PALETTE_INITIALIZER_STATE_CMD 4356 { 4357 union 4358 { 4359 struct 4360 { 4361 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4362 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4363 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 4364 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 4365 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 4366 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4367 }; 4368 uint32_t Value; 4369 } DW0; 4370 union 4371 { 4372 struct 4373 { 4374 uint32_t ActivePaletteInitializerTableEntries : __CODEGEN_BITFIELD( 0, 7) ; //!< Active Palette Initializer Table Entries 4375 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 4376 }; 4377 uint32_t Value; 4378 } DW1; 4379 uint32_t First64ColorEntries[96]; //!< First 64 Color Entries 4380 uint32_t Second64ColorEntries[96]; //!< Second 64 Color Entries 4381 4382 //! \name Local enumerations 4383 4384 enum MEDIA_INSTRUCTION_COMMAND 4385 { 4386 MEDIA_INSTRUCTION_COMMAND_HCPPALETTEINITIALIZERSTATE = 9, //!< No additional details 4387 }; 4388 4389 //! \brief MEDIA_INSTRUCTION_OPCODE 4390 //! \details 4391 //! Codec/Engine Name = HCP = 7h 4392 enum MEDIA_INSTRUCTION_OPCODE 4393 { 4394 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 4395 }; 4396 4397 enum PIPELINE_TYPE 4398 { 4399 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 4400 }; 4401 4402 enum COMMAND_TYPE 4403 { 4404 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4405 }; 4406 4407 //! \name Initializations 4408 4409 //! \brief Explicit member initialization function 4410 HCP_PALETTE_INITIALIZER_STATE_CMD(); 4411 4412 static const size_t dwSize = 194; 4413 static const size_t byteSize = 776; 4414 }; 4415 4416 }; 4417 4418 #pragma pack() 4419 4420 #endif // __MHW_VDBOX_HCP_HWCMD_G12_X_H__