1 /* 2 * Copyright (c) 2020-2023, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_avp_itf.h 24 //! \brief MHW VDBOX AVP interface common base 25 //! \details 26 //! 27 28 #ifndef __MHW_VDBOX_AVP_ITF_H__ 29 #define __MHW_VDBOX_AVP_ITF_H__ 30 31 #include "mhw_itf.h" 32 #include "mhw_vdbox_avp_cmdpar.h" 33 34 #define _AVP_CMD_DEF(DEF) \ 35 DEF(AVP_PIPE_MODE_SELECT); \ 36 DEF(AVP_PIC_STATE); \ 37 DEF(AVP_INLOOP_FILTER_STATE); \ 38 DEF(AVP_TILE_CODING); \ 39 DEF(AVP_SEGMENT_STATE); \ 40 DEF(AVP_PIPE_BUF_ADDR_STATE); \ 41 DEF(AVP_INTER_PRED_STATE); \ 42 DEF(AVP_IND_OBJ_BASE_ADDR_STATE); \ 43 DEF(AVP_SURFACE_STATE); \ 44 DEF(AVP_BSD_OBJECT); \ 45 DEF(AVP_PAK_INSERT_OBJECT); \ 46 DEF(AVP_FILM_GRAIN_STATE) 47 48 namespace mhw 49 { 50 namespace vdbox 51 { 52 namespace avp 53 { 54 //! \struct MmioRegistersAvp 55 //! \brief MMIO registers AVP 56 //! 57 struct AvpMmioRegisters 58 { 59 uint32_t avpAv1BitstreamByteCountTileRegOffset = 0; 60 uint32_t avpAv1BitstreamByteCountTileNoHeaderRegOffset = 0; 61 uint32_t avpAv1CabacBinCountTileRegOffset = 0; 62 uint32_t avpAv1CabacInsertionCountRegOffset = 0; 63 uint32_t avpAv1MinSizePaddingCountRegOffset = 0; 64 uint32_t avpAv1ImageStatusMaskRegOffset = 0; 65 uint32_t avpAv1ImageStatusControlRegOffset = 0; 66 uint32_t avpAv1QpStatusCountRegOffset = 0; 67 uint32_t avpAv1DecErrorStatusAddrRegOffset = 0; 68 }; 69 70 class Itf 71 { 72 public: 73 74 enum CommandsNumberOfAddress 75 { 76 AVP_PIPE_MODE_SELECT_CMD_NUMBER_OF_ADDRESSES = 0, 77 AVP_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 78 AVP_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 65, 79 AVP_IND_OBJ_BASE_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 3, 80 AVP_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 81 AVP_REF_IDX_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 82 AVP_SEGMENT_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 83 AVP_TILE_CODING_CMD_LST_NUMBER_OF_ADDRESSES = 0, 84 AVP_TILE_CODING_CMD_NUMBER_OF_ADDRESSES = 0, 85 AVP_BSD_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, 86 AVP_INLOOP_FILTER_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 87 AVP_INTER_PRED_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 88 AVP_PAK_INSERT_OBJECT_CMD_NUMBER_OF_ADDRESSES = 0, 89 VD_PIPELINE_FLUSH_CMD_NUMBER_OF_ADDRESSES = 0, 90 AVP_FILM_GRAIN_STATE_CMD_NUMBER_OF_ADDRESSES = 0 91 }; 92 93 class ParSetting 94 { 95 public: 96 virtual ~ParSetting() = default; 97 98 _AVP_CMD_DEF(_MHW_SETPAR_DEF); 99 }; 100 101 virtual ~Itf() = default; 102 103 virtual MOS_STATUS SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS settings[MOS_CODEC_RESOURCE_USAGE_END_CODEC]) = 0; 104 virtual MOS_STATUS GetAvpBufSize(AvpBufferType bufferType, AvpBufferSizePar *avpBufSizeParam) = 0; 105 virtual bool IsRowStoreCachingSupported() = 0; // Judge if row store caching is supported, overall flag for AVP 106 virtual bool IsBufferRowstoreCacheEnabled(AvpBufferType bufferType) = 0; // If row store cache of a particular buffer is enabled 107 virtual MOS_STATUS GetAvpPrimitiveCmdSize(uint32_t *commandsSize, uint32_t *patchListSize, PMHW_VDBOX_STATE_CMDSIZE_PARAMS params) = 0; 108 virtual MOS_STATUS GetAvpStateCmdSize(uint32_t *commandsSize, uint32_t *patchListSize, PMHW_VDBOX_STATE_CMDSIZE_PARAMS params) = 0; 109 virtual AvpMmioRegisters* GetMmioRegisters(MHW_VDBOX_NODE_IND index) = 0; 110 virtual MOS_STATUS GetRowstoreCachingAddrs(mhw::vdbox::avp::AvpVdboxRowStorePar rowstoreParams) = 0; 111 112 _AVP_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_ITF); 113 MEDIA_CLASS_DEFINE_END(mhw__vdbox__avp__Itf) 114 }; 115 } // namespace avp 116 } // namespace vdbox 117 } // namespace mhw 118 119 #endif // __MHW_VDBOX_AVP_ITF_H__ 120