1 /* 2 * Copyright (c) 2021-2024, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_aqm_itf.h 24 //! \brief MHW VDBOX AQM interface common base 25 //! \details 26 //! 27 28 #ifndef __MHW_VDBOX_AQM_ITF_H__ 29 #define __MHW_VDBOX_AQM_ITF_H__ 30 31 #include "mhw_impl.h" 32 #include "mhw_vdbox_aqm_cmdpar.h" 33 34 #ifdef IGFX_AQM_INTERFACE_EXT_SUPPORT 35 #include "mhw_vdbox_aqm_itf_ext.h" 36 #endif 37 38 #define _AQM_CMD_DEF(DEF) \ 39 DEF(AQM_FRAME_START); \ 40 DEF(AQM_PIC_STATE); \ 41 DEF(AQM_SURFACE_STATE); \ 42 DEF(AQM_PIPE_BUF_ADDR_STATE); \ 43 DEF(AQM_TILE_CODING); \ 44 DEF(AQM_VD_CONTROL_STATE); \ 45 DEF(AQM_SLICE_STATE) 46 47 namespace mhw 48 { 49 namespace vdbox 50 { 51 namespace aqm 52 { 53 class Itf 54 { 55 public: 56 57 enum CommandsNumberOfAddresses 58 { 59 AQM_VD_CONTROL_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 60 AQM_SURFACE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 61 AQM_PIPE_BUF_ADDR_STATE_CMD_NUMBER_OF_ADDRESSES = 16, 62 AQM_PIC_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 63 AQM_TILE_CODING_CMD_NUMBER_OF_ADDRESSES = 0, 64 AQM_FRAME_START_CMD_NUMBER_OF_ADDRESSES = 0, 65 AQM_SLICE_STATE_CMD_NUMBER_OF_ADDRESSES = 0, 66 #if _MEDIA_RESERVED 67 __MHW_VDBOX_AQM_WRAPPER_EXT(AQM_CMD_ADDRESS_EXT) 68 #endif 69 }; 70 71 class ParSetting 72 { 73 public: 74 virtual ~ParSetting() = default; 75 76 _AQM_CMD_DEF(_MHW_SETPAR_DEF); 77 #if _MEDIA_RESERVED 78 _AQM_CMD_DEF_EXT(_MHW_SETPAR_DEF); 79 #endif 80 }; 81 82 virtual ~Itf() = default; 83 84 virtual MOS_STATUS SetCacheabilitySettings(MHW_MEMORY_OBJECT_CONTROL_PARAMS settings[MOS_CODEC_RESOURCE_USAGE_END_CODEC]) = 0; 85 86 _AQM_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_ITF); 87 #if _MEDIA_RESERVED 88 _AQM_CMD_DEF_EXT(_MHW_CMD_ALL_DEF_FOR_ITF); 89 #endif 90 91 MEDIA_CLASS_DEFINE_END(mhw__vdbox__aqm__Itf) 92 }; 93 } // namespace aqm 94 } // namespace vdbox 95 } // namespace mhw 96 97 #endif // __MHW_VDBOX_AQM_ITF_H__ 98