1 /*===================== begin_copyright_notice ================================== 2 3 * Copyright (c) 2024, Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 23 ======================= end_copyright_notice ==================================*/ 24 //! 25 //! \file mhw_state_heap_xe2_hpg.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of Xe2_HPG as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 31 #ifndef __MHW_STATE_HEAP_HWCMD_XE2_HPG_H__ 32 #define __MHW_STATE_HEAP_HWCMD_XE2_HPG_H__ 33 34 #pragma once 35 #pragma pack(1) 36 37 #include <cstdint> 38 #include <cstddef> 39 #include "media_class_trace.h" 40 41 class mhw_state_heap_xe2_hpg 42 { 43 public: 44 // Internal Macros 45 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 46 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 47 #define __CODEGEN_OP_LENGTH_BIAS 2 48 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 49 GetOpLength(uint32_t uiLength)50 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 51 52 //! 53 //! \brief INTERFACE_DESCRIPTOR_DATA 54 //! \details 55 //! 56 //! 57 struct INTERFACE_DESCRIPTOR_DATA_CMD 58 { 59 union 60 { 61 struct 62 { 63 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 64 uint32_t KernelStartPointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Kernel Start Pointer 65 }; 66 uint32_t Value; 67 } DW0; 68 union 69 { 70 struct 71 { 72 uint32_t Reserved32 ; //!< Reserved 73 }; 74 uint32_t Value; 75 } DW1; 76 union 77 { 78 struct 79 { 80 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 81 uint32_t SoftwareExceptionEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Software Exception Enable 82 uint32_t RegistersPerThread : __CODEGEN_BITFIELD( 8, 10) ; //!< REGISTERS_PER_THREAD 83 uint32_t MaskStackExceptionEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Mask Stack Exception Enable 84 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 12) ; //!< Reserved 85 uint32_t IllegalOpcodeExceptionEnable : __CODEGEN_BITFIELD(13, 13) ; //!< Illegal Opcode Exception Enable 86 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 87 uint32_t FloatingPointMode : __CODEGEN_BITFIELD(16, 16) ; //!< FLOATING_POINT_MODE 88 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 17) ; //!< Reserved 89 uint32_t SingleProgramFlow : __CODEGEN_BITFIELD(18, 18) ; //!< SINGLE_PROGRAM_FLOW 90 uint32_t DenormMode : __CODEGEN_BITFIELD(19, 19) ; //!< DENORM_MODE 91 uint32_t ThreadPreemption : __CODEGEN_BITFIELD(20, 20) ; //!< THREAD_PREEMPTION 92 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 93 }; 94 uint32_t Value; 95 } DW2; 96 union 97 { 98 struct 99 { 100 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 101 uint32_t SamplerCount : __CODEGEN_BITFIELD( 2, 4) ; //!< SAMPLER_COUNT 102 uint32_t SamplerStatePointer : __CODEGEN_BITFIELD( 5, 31) ; //!< Sampler State Pointer 103 }; 104 uint32_t Value; 105 } DW3; 106 union 107 { 108 struct 109 { 110 uint32_t BindingTableEntryCount : __CODEGEN_BITFIELD( 0, 4) ; //!< BINDING_TABLE_ENTRY_COUNT 111 uint32_t BindingTablePointer : __CODEGEN_BITFIELD( 5, 20) ; //!< Binding Table Pointer 112 uint32_t Reserved149 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 113 }; 114 uint32_t Value; 115 } DW4; 116 union 117 { 118 struct 119 { 120 uint32_t NumberOfThreadsInGpgpuThreadGroup : __CODEGEN_BITFIELD( 0, 9) ; //!< Number of Threads in GPGPU Thread Group 121 uint32_t Reserved170 : __CODEGEN_BITFIELD(10, 12) ; //!< Reserved 122 uint32_t ThreadGroupForwardProgressGuarantee : __CODEGEN_BITFIELD(13, 13) ; //!< THREAD_GROUP_FORWARD_PROGRESS_GUARANTEE 123 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 124 uint32_t SharedLocalMemorySize : __CODEGEN_BITFIELD(16, 20) ; //!< SHARED_LOCAL_MEMORY_SIZE 125 uint32_t Reserved181 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 126 uint32_t RoundingMode : __CODEGEN_BITFIELD(22, 23) ; //!< ROUNDING_MODE 127 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 25) ; //!< Reserved 128 uint32_t ThreadGroupDispatchSize : __CODEGEN_BITFIELD(26, 27) ; //!< THREAD_GROUP_DISPATCH_SIZE 129 uint32_t NumberOfBarriers : __CODEGEN_BITFIELD(28, 30) ; //!< NUMBER_OF_BARRIERS 130 uint32_t BtdMode : __CODEGEN_BITFIELD(31, 31) ; //!< BTD_MODE 131 }; 132 uint32_t Value; 133 } DW5; 134 union 135 { 136 struct 137 { 138 uint32_t PreferredSlmSizeOverride : __CODEGEN_BITFIELD( 0, 0) ; //!< PREFERRED_SLM_SIZE_OVERRIDE 139 uint32_t Reserved193 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 140 }; 141 uint32_t Value; 142 } DW6; 143 union 144 { 145 struct 146 { 147 uint32_t PreferredSlmAllocationSizePerSubslice : __CODEGEN_BITFIELD( 0, 3) ; //!< PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE 148 uint32_t Reserved228 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 149 }; 150 uint32_t Value; 151 } DW7; 152 153 //! \name Local enumerations 154 155 //! \brief REGISTERS_PER_THREAD 156 //! \details 157 //! Specifies the minimum number of registers allocated for each thread 158 //! dispatch. 159 enum REGISTERS_PER_THREAD 160 { 161 REGISTERS_PER_THREAD_DEFAULT = 0, //!< Use 128 registers 162 REGISTERS_PER_THREAD_64REGISTERS = 1, //!< Override default, use 64 registers. 163 REGISTERS_PER_THREAD_256REGISTERS = 6, //!< Override default, use 256 registers. 164 }; 165 166 //! \brief FLOATING_POINT_MODE 167 //! \details 168 //! Specifies the floating point mode used by the dispatched thread. 169 enum FLOATING_POINT_MODE 170 { 171 FLOATING_POINT_MODE_IEEE_754 = 0, //!< No additional details 172 FLOATING_POINT_MODE_ALTERNATE = 1, //!< No additional details 173 }; 174 175 //! \brief SINGLE_PROGRAM_FLOW 176 //! \details 177 //! Specifies whether the kernel program has a single program flow (SIMDnxm 178 //! with m = 1) or multiple program flows (SIMDnxm with m > 1). 179 enum SINGLE_PROGRAM_FLOW 180 { 181 SINGLE_PROGRAM_FLOW_MULTIPLE = 0, //!< No additional details 182 SINGLE_PROGRAM_FLOW_SINGLE = 1, //!< No additional details 183 }; 184 185 //! \brief DENORM_MODE 186 //! \details 187 //! This field specifies how Float denormalized numbers are handles in the 188 //! dispatched thread. 189 enum DENORM_MODE 190 { 191 DENORM_MODE_FTZ = 0, //!< Float denorms will be flushed to zero when appearing as inputs; denorms will never come out of instructions. Double precision float and half precision float numbers are not flushed to zero. 192 DENORM_MODE_SETBYKERNEL = 1, //!< Denorms will be handled in by kernel. 193 }; 194 195 //! \brief THREAD_PREEMPTION 196 //! \details 197 //! This field specifies whether, when dispatched, the thread is allowed to 198 //! stop in middle on receiving mid-thread pre-emption request. 199 enum THREAD_PREEMPTION 200 { 201 THREAD_PREEMPTION_DISABLE = 0, //!< Thread is preempted only in case of page-fault. 202 THREAD_PREEMPTION_ENABLE = 1, //!< Thread is pre-empted on receiving pre-emption indication. 203 }; 204 205 //! \brief SAMPLER_COUNT 206 //! \details 207 //! Specifies how many samplers (in multiples of 4) the kernel uses. Used 208 //! only for prefetching the associated sampler state entries. 209 enum SAMPLER_COUNT 210 { 211 SAMPLER_COUNT_NOSAMPLERSUSED = 0, //!< No additional details 212 SAMPLER_COUNT_BETWEEN1AND4SAMPLERSUSED = 1, //!< No additional details 213 SAMPLER_COUNT_BETWEEN5AND8SAMPLERSUSED = 2, //!< No additional details 214 SAMPLER_COUNT_BETWEEN9AND12SAMPLERSUSED = 3, //!< No additional details 215 SAMPLER_COUNT_BETWEEN13AND16SAMPLERSUSED = 4, //!< No additional details 216 }; 217 218 //! \brief BINDING_TABLE_ENTRY_COUNT 219 //! \details 220 //! Specifies how many binding table entries the kernel uses. Used only for 221 //! prefetching of the binding table entries and associated surface state. 222 enum BINDING_TABLE_ENTRY_COUNT 223 { 224 BINDING_TABLE_ENTRY_COUNT_PREFETCHDISABLED = 0, //!< No additional details 225 }; 226 227 //! \brief THREAD_GROUP_FORWARD_PROGRESS_GUARANTEE 228 //! \details 229 //! Set by the kernel if TG requires synchonization at memory. If this bit 230 //! is set, CFEG must enable the barrier when mid thread preemption is 231 //! enabled. 232 enum THREAD_GROUP_FORWARD_PROGRESS_GUARANTEE 233 { 234 THREAD_GROUP_FORWARD_PROGRESS_GUARANTEE_DISABLE = 0, //!< CFEG HW does not set an implicit barrier when WMTP is enabled 235 THREAD_GROUP_FORWARD_PROGRESS_GUARANTEE_ENABLE = 1, //!< CFEG HW forces an implicit barrier when WMTP is enabled. 236 }; 237 238 //! \brief SHARED_LOCAL_MEMORY_SIZE 239 //! \details 240 //! This field indicates how much Shared Local Memory the thread group 241 //! requires. 242 enum SHARED_LOCAL_MEMORY_SIZE 243 { 244 SHARED_LOCAL_MEMORY_SIZE_ENCODES0KB = 0, //!< No SLM used 245 SHARED_LOCAL_MEMORY_SIZE_ENCODES1KB = 1, //!< No additional details 246 SHARED_LOCAL_MEMORY_SIZE_ENCODES2KB = 2, //!< No additional details 247 SHARED_LOCAL_MEMORY_SIZE_ENCODES4KB = 3, //!< No additional details 248 SHARED_LOCAL_MEMORY_SIZE_ENCODES8KB = 4, //!< No additional details 249 SHARED_LOCAL_MEMORY_SIZE_ENCODES16KB = 5, //!< No additional details 250 SHARED_LOCAL_MEMORY_SIZE_ENCODES32KB = 6, //!< No additional details 251 SHARED_LOCAL_MEMORY_SIZE_ENCODES64KB = 7, //!< No additional details 252 SHARED_LOCAL_MEMORY_SIZE_ENCODES24KB = 8, //!< No additional details 253 SHARED_LOCAL_MEMORY_SIZE_ENCODES48KB = 9, //!< No additional details 254 SHARED_LOCAL_MEMORY_SIZE_ENCODES96KB = 10, //!< No additional details 255 SHARED_LOCAL_MEMORY_SIZE_ENCODES128KB = 11, //!< No additional details 256 SHARED_LOCAL_MEMORY_SIZE_ENCODES192KB = 12, //!< No additional details 257 SHARED_LOCAL_MEMORY_SIZE_ENCODES256KB = 13, //!< No additional details 258 SHARED_LOCAL_MEMORY_SIZE_ENCODES384KB = 14, //!< No additional details 259 }; 260 261 enum ROUNDING_MODE 262 { 263 ROUNDING_MODE_RTNE = 0, //!< Round to Nearest Even 264 ROUNDING_MODE_RU = 1, //!< Round toward +Infinity 265 ROUNDING_MODE_RD = 2, //!< Round toward -Infinity 266 ROUNDING_MODE_RTZ = 3, //!< Round toward Zero 267 }; 268 269 //! \brief THREAD_GROUP_DISPATCH_SIZE 270 //! \details 271 //! Provides a mechanism for Software to tune the settings based on WLs 272 //! to evenly distribute the threads across the entire m/c. 273 //! The recommended settings is just a guidance and not a programming 274 //! requirement. 275 enum THREAD_GROUP_DISPATCH_SIZE 276 { 277 THREAD_GROUP_DISPATCH_SIZE_TGSIZE8 = 0, //!< The dispatch size is 8 thread groups. 278 THREAD_GROUP_DISPATCH_SIZE_TGSIZE4 = 1, //!< The dispatch size is 4 thread groups. 279 THREAD_GROUP_DISPATCH_SIZE_TGSIZE2 = 2, //!< The dispatch size is 2 thread groups. 280 }; 281 282 //! \brief NUMBER_OF_BARRIERS 283 //! \details 284 //! Specifies number of barriers in the threadgroup. 285 enum NUMBER_OF_BARRIERS 286 { 287 NUMBER_OF_BARRIERS_NONE = 0, //!< No additional details 288 NUMBER_OF_BARRIERS_B1 = 1, //!< No additional details 289 NUMBER_OF_BARRIERS_B2 = 2, //!< No additional details 290 NUMBER_OF_BARRIERS_B4 = 3, //!< No additional details 291 NUMBER_OF_BARRIERS_B8 = 4, //!< No additional details 292 NUMBER_OF_BARRIERS_B16 = 5, //!< No additional details 293 NUMBER_OF_BARRIERS_B24 = 6, //!< No additional details 294 NUMBER_OF_BARRIERS_B32 = 7, //!< No additional details 295 }; 296 297 //! \brief BTD_MODE 298 //! \details 299 //! If this field is valid, it means that the Compute pipeline is 300 //! dispatching BTD threads. 301 enum BTD_MODE 302 { 303 BTD_MODE_DISABLE = 0, //!< Normal thread dispatch 304 BTD_MODE_ENABLE = 1, //!< When walker dispatched compute kernels either perform messages to the Bindless Thread Dispatch (BTD) shared function or Ray Tracing HW shared function, this bit must be enabled.When this bit is enabled, the BTD stack IDs are passedin the compute kernelR1. See <a href="https:gfxspecs.intel.com/Predator/Home/Index/55404">GPGPU_R1_BTD</a>.When this bit is enabled, neither SLM nor barrier is available. 305 }; 306 307 //! \brief PREFERRED_SLM_SIZE_OVERRIDE 308 //! \details 309 //! This bit provides a mechanism to override thePreferred SLM size per 310 //! Subslice to maintain backward compatibility with old drivers. 311 //! 312 enum PREFERRED_SLM_SIZE_OVERRIDE 313 { 314 PREFERRED_SLM_SIZE_OVERRIDE_UNNAMED0 = 0, //!< The preferred SLM size is fixed at 128KB. The value defined in DW7 bits[3:0] of this command is ignored. 315 PREFERRED_SLM_SIZE_OVERRIDE_UNNAMED1 = 1, //!< The preferred SLM size from DW7 bits[3:0] of this commmand is used. 316 }; 317 318 //! \brief PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE 319 //! \details 320 //! For products where SLM and Subslice L1 cacheshares a common, 321 //! re-partitionable RAM, this field indicates the preferred SLM size per 322 //! Subslice for this dispatch. The SLM size programmed here should be >= 323 //! the per thread-group SLM size programmed in DW[5][20:16]. 324 //! The "Preferred SLM Size override" bit of this command must be set to 325 //! 1 for this programmed size to take effect. Otherwise, SLM partition size 326 //! is fixed at128KB per subslice. 327 enum PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE 328 { 329 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_0KB = 0, //!< Preferred SLM size is 0KB 330 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_16KB = 1, //!< Preferred SLM size is 16KB 331 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_32KB = 2, //!< Preferred SLM size is 32KB 332 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_64KB = 3, //!< Preferred SLM size is 64KB 333 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_96KB = 4, //!< Preferred SLM size is 96KB 334 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_128KB = 5, //!< Preferred SLM size is 128KB 335 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_160KB = 6, //!< Preferred SLM size is 160KB 336 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_192KB = 7, //!< Preferred SLM size is 192KB 337 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_256KB = 8, //!< Preferred SLM size is 256KB 338 PREFERRED_SLM_ALLOCATION_SIZE_PER_SUBSLICE_384KB = 9, //!< Preferred SLM size is 384KB 339 }; 340 341 //! \name Initializations 342 343 //! \brief Explicit member initialization function 344 INTERFACE_DESCRIPTOR_DATA_CMD(); 345 346 static const size_t dwSize = 8; 347 static const size_t byteSize = 32; 348 }; 349 350 //! 351 //! \brief BINDING_TABLE_STATE 352 //! \details 353 //! The binding table binds surfaces to logical resource indices used by 354 //! shaders and other compute engine kernels. It is stored as an array of up 355 //! to 256 elements, each of which contains one dword as defined here. The 356 //! start of each element is spaced one dword apart. The first element of 357 //! the binding table is aligned to a 64-byte boundary. Binding table 358 //! indexes beyond 256 will automatically be mapped to entry 0 by the HW, w/ 359 //! the exception of any messages which support the special indexes 240 360 //! through 255, inclusive. 361 //! 362 struct BINDING_TABLE_STATE_CMD 363 { 364 union 365 { 366 //!< DWORD 0 367 struct 368 { 369 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 370 uint32_t SurfaceStatePointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Surface State Pointer 371 }; 372 uint32_t Value; 373 } DW0; 374 375 //! \name Local enumerations 376 377 //! \name Initializations 378 379 //! \brief Explicit member initialization function 380 BINDING_TABLE_STATE_CMD(); 381 382 static const size_t dwSize = 1; 383 static const size_t byteSize = 4; 384 }; 385 386 //! 387 //! \brief RENDER_SURFACE_STATE 388 //! \details 389 //! This is the normal surface state used by all messages that use 390 //! SURFACE_STATE except those that use MEDIA_SURFACE_STATE. 391 //! 392 struct RENDER_SURFACE_STATE_CMD 393 { 394 union 395 { 396 struct 397 { 398 uint32_t CubeFaceEnablePositiveZ : __CODEGEN_BITFIELD( 0, 0) ; //!< Cube Face Enable - Positive Z 399 uint32_t CubeFaceEnableNegativeZ : __CODEGEN_BITFIELD( 1, 1) ; //!< Cube Face Enable - Negative Z 400 uint32_t CubeFaceEnablePositiveY : __CODEGEN_BITFIELD( 2, 2) ; //!< Cube Face Enable - Positive Y 401 uint32_t CubeFaceEnableNegativeY : __CODEGEN_BITFIELD( 3, 3) ; //!< Cube Face Enable - Negative Y 402 uint32_t CubeFaceEnablePositiveX : __CODEGEN_BITFIELD( 4, 4) ; //!< Cube Face Enable - Positive X 403 uint32_t CubeFaceEnableNegativeX : __CODEGEN_BITFIELD( 5, 5) ; //!< Cube Face Enable - Negative X 404 uint32_t MediaBoundaryPixelMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MEDIA_BOUNDARY_PIXEL_MODE 405 uint32_t RenderCacheReadWriteMode : __CODEGEN_BITFIELD( 8, 8) ; //!< RENDER_CACHE_READ_WRITE_MODE 406 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 407 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(10, 10) ; //!< Vertical Line Stride Offset 408 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(11, 11) ; //!< Vertical Line Stride 409 uint32_t TileMode : __CODEGEN_BITFIELD(12, 13) ; //!< TILE_MODE 410 uint32_t SurfaceHorizontalAlignment : __CODEGEN_BITFIELD(14, 15) ; //!< SURFACE_HORIZONTAL_ALIGNMENT 411 uint32_t SurfaceVerticalAlignment : __CODEGEN_BITFIELD(16, 17) ; //!< SURFACE_VERTICAL_ALIGNMENT 412 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(18, 26) ; //!< SURFACE_FORMAT 413 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 27) ; //!< Reserved 414 uint32_t SurfaceArray : __CODEGEN_BITFIELD(28, 28) ; //!< Surface Array 415 uint32_t SurfaceType : __CODEGEN_BITFIELD(29, 31) ; //!< SURFACE_TYPE 416 }; 417 uint32_t Value; 418 } DW0; 419 union 420 { 421 struct 422 { 423 uint32_t SurfaceQpitch : __CODEGEN_BITFIELD( 0, 14) ; //!< Surface QPitch 424 uint32_t SampleTapDiscardDisable : __CODEGEN_BITFIELD(15, 15) ; //!< SAMPLE_TAP_DISCARD_DISABLE 425 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 426 uint32_t CornerTexelMode : __CODEGEN_BITFIELD(18, 18) ; //!< CORNER_TEXEL_MODE 427 uint32_t BaseMipLevel : __CODEGEN_BITFIELD(19, 23) ; //!< Base Mip Level 428 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD(24, 30) ; //!< Memory Object Control State 429 uint32_t Reserved63 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 430 }; 431 uint32_t Value; 432 } DW1; 433 union 434 { 435 struct 436 { 437 uint32_t Width : __CODEGEN_BITFIELD( 0, 13) ; //!< Width 438 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 439 uint32_t Height : __CODEGEN_BITFIELD(16, 29) ; //!< Height 440 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 441 uint32_t DepthStencilResource : __CODEGEN_BITFIELD(31, 31) ; //!< Depth/Stencil Resource 442 }; 443 uint32_t Value; 444 } DW2; 445 union 446 { 447 struct 448 { 449 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 0, 17) ; //!< Surface Pitch 450 uint32_t Reserved115 : __CODEGEN_BITFIELD(18, 20) ; //!< Reserved 451 uint32_t Depth : __CODEGEN_BITFIELD(21, 31) ; //!< Depth 452 }; 453 uint32_t Value; 454 } DW3; 455 union 456 { 457 struct 458 { 459 uint32_t MultisamplePositionPaletteIndex : __CODEGEN_BITFIELD( 0, 2) ; //!< Multisample Position Palette Index 460 uint32_t NumberOfMultisamples : __CODEGEN_BITFIELD( 3, 5) ; //!< NUMBER_OF_MULTISAMPLES 461 uint32_t MultisampledSurfaceStorageFormat : __CODEGEN_BITFIELD( 6, 6) ; //!< MULTISAMPLED_SURFACE_STORAGE_FORMAT 462 uint32_t RenderTargetViewExtent : __CODEGEN_BITFIELD( 7, 17) ; //!< Render Target View Extent 463 uint32_t MinimumArrayElement : __CODEGEN_BITFIELD(18, 28) ; //!< Minimum Array Element 464 uint32_t RenderTargetAndSampleUnormRotation : __CODEGEN_BITFIELD(29, 30) ; //!< RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 465 uint32_t DecompressInL3 : __CODEGEN_BITFIELD(31, 31) ; //!< DECOMPRESS_IN_L3 466 }; 467 uint32_t Value; 468 } DW4; 469 union 470 { 471 struct 472 { 473 uint32_t MipCountLod : __CODEGEN_BITFIELD( 0, 3) ; //!< MIP Count / LOD 474 uint32_t SurfaceMinLod : __CODEGEN_BITFIELD( 4, 7) ; //!< Surface Min LOD 475 uint32_t MipTailStartLod : __CODEGEN_BITFIELD( 8, 11) ; //!< Mip Tail Start LOD 476 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 13) ; //!< Reserved 477 uint32_t CoherencyType : __CODEGEN_BITFIELD(14, 15) ; //!< COHERENCY_TYPE 478 uint32_t L1CacheControl : __CODEGEN_BITFIELD(16, 18) ; //!< L1 Cache Control 479 uint32_t Reserved179 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 480 uint32_t EwaDisableForCube : __CODEGEN_BITFIELD(20, 20) ; //!< EWA_DISABLE_FOR_CUBE 481 uint32_t YOffset : __CODEGEN_BITFIELD(21, 23) ; //!< Y Offset 482 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 483 uint32_t XOffset : __CODEGEN_BITFIELD(25, 31) ; //!< X Offset 484 }; 485 uint32_t Value; 486 } DW5; 487 union 488 { 489 struct 490 { 491 uint32_t AuxiliarySurfaceMode : __CODEGEN_BITFIELD( 0, 2) ; //!< AUXILIARY_SURFACE_MODE, ([Surface Format] != 'PLANAR') 492 uint32_t Reserved195 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved, ([Surface Format] != 'PLANAR') 493 } Obj0; 494 struct 495 { 496 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved, ([Surface Format] != 'PLANAR') 497 uint32_t AuxiliarySurfacePitch : __CODEGEN_BITFIELD( 3, 12) ; //!< Auxiliary Surface Pitch, ([Surface Format] != 'PLANAR') 498 uint32_t Reserved205 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, ([Surface Format] != 'PLANAR') 499 uint32_t AuxiliarySurfaceQpitch : __CODEGEN_BITFIELD(16, 30) ; //!< Auxiliary Surface QPitch, ([Surface Format] != 'PLANAR') 500 uint32_t Reserved223 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, ([Surface Format] != 'PLANAR') 501 } Obj1; 502 struct 503 { 504 uint32_t YOffsetForUOrUvPlane : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 505 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved, ([Surface Format] == 'PLANAR') 506 uint32_t XOffsetForUOrUvPlane : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 507 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD(30, 30) ; //!< HALF_PITCH_FOR_CHROMA, ([Surface Format] == 'PLANAR') 508 uint32_t SeparateUvPlaneEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Separate UV Plane Enable, ([Surface Format] == 'PLANAR') 509 } Obj2; 510 struct 511 { 512 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 14) ; //!< Reserved, ([Surface Format] == 'PLANAR') 513 uint32_t YuvInterpolationEnable : __CODEGEN_BITFIELD(15, 15) ; //!< YUV_INTERPOLATION_ENABLE, 514 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved, 515 } Obj3; 516 uint32_t Value; 517 } DW6; 518 union 519 { 520 struct 521 { 522 uint32_t ResourceMinLod : __CODEGEN_BITFIELD( 0, 11) ; //!< Resource Min LOD 523 uint32_t Reserved236 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 524 uint32_t ShaderChannelSelectAlpha : __CODEGEN_BITFIELD(16, 18) ; //!< SHADER_CHANNEL_SELECT_ALPHA 525 uint32_t ShaderChannelSelectBlue : __CODEGEN_BITFIELD(19, 21) ; //!< SHADER_CHANNEL_SELECT_BLUE 526 uint32_t ShaderChannelSelectGreen : __CODEGEN_BITFIELD(22, 24) ; //!< SHADER_CHANNEL_SELECT_GREEN 527 uint32_t ShaderChannelSelectRed : __CODEGEN_BITFIELD(25, 27) ; //!< SHADER_CHANNEL_SELECT_RED 528 uint32_t Reserved252 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 529 }; 530 uint32_t Value; 531 } DW7; 532 union 533 { 534 struct 535 { 536 uint64_t SurfaceBaseAddress ; //!< Surface Base Address 537 }; 538 uint32_t Value[2]; 539 } DW8_9; 540 union 541 { 542 struct 543 { 544 uint64_t Reserved320 : __CODEGEN_BITFIELD(0, 10) ; //!< CLEAR_VALUE_ADDRESS_ENABLE, 545 uint64_t ProceduralTexture : __CODEGEN_BITFIELD(11, 11) ; //!< Procedural Texture, 546 uint64_t Reserved332 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved, 547 uint64_t YOffsetForVPlane : __CODEGEN_BITFIELD(32, 45) ; //!< Y Offset for V Plane, ([Surface Format] == 'PLANAR') 548 uint64_t Reserved366 : __CODEGEN_BITFIELD(46, 63) ; //!< Reserved, ([Surface Format] == 'PLANAR') 549 } Obj0; 550 struct 551 { 552 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 47) ; //!< Reserved, ([Surface Format] == 'PLANAR') 553 uint64_t XOffsetForVPlane : __CODEGEN_BITFIELD(48, 61) ; //!< X Offset for V Plane, ([Surface Format] == 'PLANAR') 554 uint64_t Reserved382 : __CODEGEN_BITFIELD(62, 63) ; //!< Reserved, ([Surface Format] == 'PLANAR') 555 } Obj1; 556 struct 557 { 558 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved, ([Surface Format] == 'PLANAR') 559 uint64_t AuxiliarySurfaceBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Auxiliary Surface Base Address, ([Surface Format] != 'PLANAR') AND [Memory Compression Enable] == 0 560 } Obj2; 561 uint32_t Value[2]; 562 } DW10_11; 563 union 564 { 565 struct 566 { 567 uint32_t CompressionFormat : __CODEGEN_BITFIELD( 0, 3) ; //!< COMPRESSION_FORMAT 568 uint32_t Reserved388 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 569 }; 570 uint32_t Value; 571 } DW12; 572 union 573 { 574 struct 575 { 576 uint32_t Reserved416 : __CODEGEN_BITFIELD( 0, 30) ; //!< Reserved 577 uint32_t DisallowLowQualityFiltering : __CODEGEN_BITFIELD(31, 31) ; //!< Disallow low quality filtering 578 }; 579 uint32_t Value; 580 } DW13; 581 union 582 { 583 struct 584 { 585 uint32_t Reserved448 ; //!< Reserved 586 }; 587 uint32_t Value; 588 } DW14; 589 union 590 { 591 struct 592 { 593 uint32_t Reserved480 ; //!< Reserved 594 }; 595 uint32_t Value; 596 } DW15; 597 598 //! \name Local enumerations 599 600 //! \brief MEDIA_BOUNDARY_PIXEL_MODE 601 //! \details 602 //! 603 //! For 2D Non-Array Surfaces accessed via the Data Port 604 //! Media Block Read Message or Data Port Transpose Read message: 605 //! This field enables control of which rows are returned on vertical 606 //! out-of-bounds reads using the Data Port Media Block Read Message or Data 607 //! Port Transpose Read message. In the description below, frame mode refers 608 //! to Vertical Line Stride = 0, field mode is Vertical Line 609 //! Stride = 1 in which only the even or odd rows are addressable. The 610 //! frame refers to the entire surface, while the field refers only to the 611 //! even or odd rows within the surface. 612 //! 613 //! For Other Surfaces:Reserved : MBZ 614 //! 615 enum MEDIA_BOUNDARY_PIXEL_MODE 616 { 617 MEDIA_BOUNDARY_PIXEL_MODE_NORMALMODE = 0, //!< The row returned on an out-of-bound access is the closest row in the frame or field. Rows from the opposite field are never returned. 618 MEDIA_BOUNDARY_PIXEL_MODE_PROGRESSIVEFRAME = 2, //!< The row returned on an out-of-bound access is the closest row in the frame, even if in field mode. 619 MEDIA_BOUNDARY_PIXEL_MODE_INTERLACEDFRAME = 3, //!< In field mode, the row returned on an out-of-bound access is the closest row in the field. In frame mode, even out-of-bound rows return the nearest even row while odd out-of-bound rows return the nearest odd row. 620 }; 621 622 //! \brief RENDER_CACHE_READ_WRITE_MODE 623 //! \details 624 //! 625 //! For Surfaces accessed via the Data Port to Render 626 //! Cache:This field specifies the way Render Cache treats a write 627 //! request. If unset, Render Cache allocates a write-only cache line for a 628 //! write miss. If set, Render Cache allocates a read-write cache line for a 629 //! write miss. 630 //! 631 //! For Surfaces accessed via the Sampling Engine or Data 632 //! Port to Texture Cache or Data Cache:This field is reserved : 633 //! MBZ 634 enum RENDER_CACHE_READ_WRITE_MODE 635 { 636 RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLYCACHE = 0, //!< Allocating write-only cache for a write miss 637 RENDER_CACHE_READ_WRITE_MODE_READ_WRITECACHE = 1, //!< Allocating read-write cache for a write miss 638 }; 639 640 //! \brief TILE_MODE 641 //! \details 642 //! This field specifies the type of memory tiling (Linear, XMajor,Tile4, 643 //! Tile64) 644 enum TILE_MODE 645 { 646 TILE_MODE_LINEAR = 0, //!< Linear mode (no tiling) 647 TILE_MODE_TILE64 = 1, //!< Tile64 64KB tiling 648 TILE_MODE_XMAJOR = 2, //!< X major tiling 649 TILE_MODE_TILE4 = 3, //!< Tile4 4KB tiling 650 }; 651 652 //! \brief SURFACE_HORIZONTAL_ALIGNMENT 653 //! \details 654 //! This field specifies the horizontal alignment of MIPs within the 655 //! surface in bytesfor all surface formats except 24, 48 and 656 //! 96bpt (e.g. R8G8B8_UNORM). In the case of 24, 48 and 96bpt surfaces, 657 //! this field specifies the horizontal alignment of MIPs within the surface 658 //! in texels. Specifically, the left-edge of LOD2through 659 //! LOD14 will be horizontally aligned within the surface by the value in 660 //! this field. 661 //! This field is ignored for Tile64surface formats because horizontal 662 //! alignment is always to the start of the next tile in that case. 663 //! For block-compressed surfaces the Surface Horizontal Alignment field 664 //! is multiplied by the block width (p). 665 //! The value of i is calculated by the HALIGN value programmed 666 //! here divided by the Bpe (Bits per element)of the surface format. 667 //! For example, an HALIGN_64 on a 32Bpe surface would imply a Horizontal 668 //! Alignment Factor i=64/(Bpe/8) = 64/4=16 669 //! For 8-bit Packed YUV formats (e.g. YCRCB_NORMAL, YCRCB_SWAPUV, etc.), 670 //! the texel size is considered to be 32bpe and for 16-bit Packed YUV 671 //! formats (e.g. PAKCED_422_16) the bpe is assumed to be 64. So an HALIGN 672 //! of 64 would mean 64 Bytes, which corresponds to two texels for 8-bit 673 //! packed YUV. 674 //! See<a href="/Predator/Home/Index/44623">Surface Layout and 675 //! Tiling</a>for a full description of how i and p parameters are used to 676 //! determine horizontal and vertical offset to the start of a MIP. 677 enum SURFACE_HORIZONTAL_ALIGNMENT 678 { 679 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN16 = 0, //!< Horizontal alignment is 16bytes (16 texels for 24, 48 and 96 bpt surface formats).The Horizontal Alignment Factor i is dependent on the Bpp (bits per pixel) of the surface format. 680 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN32 = 1, //!< Horizontal Alignment is 32bytesThe Horizontal Alignment Factor i is dependent on the Bpp (bits per pixel) of the surface format. 681 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN64 = 2, //!< Horizontal Alignment is 64bytes.The Horizontal Alignment Factor i is dependent on the Bpp (bits per pixel) of the surface format. 682 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN128 = 3, //!< Horizontal Alignment is 128bytes.The Horizontal Alignment Factor i is dependent on the Bpp (bits per pixel) of the surface format. 683 }; 684 685 //! \brief SURFACE_VERTICAL_ALIGNMENT 686 //! \details 687 //! For Sampling Engine and Render Target Surfaces: This field 688 //! specifies the vertical alignment requirement in elements for the 689 //! surface. Refer to the "Memory Data Formats" chapter for details on how 690 //! this field changes the layout of the surface in memory. An 691 //! element is defined as a pixel in uncompressed surface formats, 692 //! and as a compression block in compressed surface formats. For 693 //! MSFMT_DEPTH_STENCIL type multisampled surfaces, an element is a sample. 694 enum SURFACE_VERTICAL_ALIGNMENT 695 { 696 SURFACE_VERTICAL_ALIGNMENT_VALIGN4 = 1, //!< Vertical alignment factor j = 4 697 SURFACE_VERTICAL_ALIGNMENT_VALIGN8 = 2, //!< Vertical alignment factor j = 8 698 SURFACE_VERTICAL_ALIGNMENT_VALIGN16 = 3, //!< Vertical alignment factor j = 16 699 }; 700 701 //! \brief SURFACE_FORMAT 702 //! \details 703 //! This field specifies the format of the surface or element within this 704 //! surface. This field is ignored for all data port messages other than the 705 //! render target message and streamed vertex buffer write message. Some 706 //! forms of the media block messages use the surface format. 707 enum SURFACE_FORMAT 708 { 709 SURFACE_FORMAT_R32G32B32A32FLOAT = 0, //!< No additional details 710 SURFACE_FORMAT_R32G32B32A32SINT = 1, //!< No additional details 711 SURFACE_FORMAT_R32G32B32A32UINT = 2, //!< No additional details 712 SURFACE_FORMAT_R32G32B32A32UNORM = 3, //!< No additional details 713 SURFACE_FORMAT_R32G32B32A32SNORM = 4, //!< No additional details 714 SURFACE_FORMAT_R64G64FLOAT = 5, //!< No additional details 715 SURFACE_FORMAT_R32G32B32X32FLOAT = 6, //!< No additional details 716 SURFACE_FORMAT_R32G32B32A32SSCALED = 7, //!< No additional details 717 SURFACE_FORMAT_R32G32B32A32USCALED = 8, //!< No additional details 718 SURFACE_FORMAT_R32G32B32A32SFIXED = 32, //!< No additional details 719 SURFACE_FORMAT_R64G64PASSTHRU = 33, //!< No additional details 720 SURFACE_FORMAT_R32G32B32FLOAT = 64, //!< No additional details 721 SURFACE_FORMAT_R32G32B32SINT = 65, //!< No additional details 722 SURFACE_FORMAT_R32G32B32UINT = 66, //!< No additional details 723 SURFACE_FORMAT_R32G32B32UNORM = 67, //!< No additional details 724 SURFACE_FORMAT_R32G32B32SNORM = 68, //!< No additional details 725 SURFACE_FORMAT_R32G32B32SSCALED = 69, //!< No additional details 726 SURFACE_FORMAT_R32G32B32USCALED = 70, //!< No additional details 727 SURFACE_FORMAT_R32G32B32SFIXED = 80, //!< No additional details 728 SURFACE_FORMAT_R16G16B16A16UNORM = 128, //!< No additional details 729 SURFACE_FORMAT_R16G16B16A16SNORM = 129, //!< No additional details 730 SURFACE_FORMAT_R16G16B16A16SINT = 130, //!< No additional details 731 SURFACE_FORMAT_R16G16B16A16UINT = 131, //!< No additional details 732 SURFACE_FORMAT_R16G16B16A16FLOAT = 132, //!< No additional details 733 SURFACE_FORMAT_R32G32FLOAT = 133, //!< No additional details 734 SURFACE_FORMAT_R32G32SINT = 134, //!< No additional details 735 SURFACE_FORMAT_R32G32UINT = 135, //!< No additional details 736 SURFACE_FORMAT_R32FLOATX8X24TYPELESS = 136, //!< No additional details 737 SURFACE_FORMAT_X32TYPELESSG8X24UINT = 137, //!< No additional details 738 SURFACE_FORMAT_L32A32FLOAT = 138, //!< No additional details 739 SURFACE_FORMAT_R32G32UNORM = 139, //!< No additional details 740 SURFACE_FORMAT_R32G32SNORM = 140, //!< No additional details 741 SURFACE_FORMAT_R64FLOAT = 141, //!< No additional details 742 SURFACE_FORMAT_R16G16B16X16UNORM = 142, //!< No additional details 743 SURFACE_FORMAT_R16G16B16X16FLOAT = 143, //!< No additional details 744 SURFACE_FORMAT_A32X32FLOAT = 144, //!< No additional details 745 SURFACE_FORMAT_L32X32FLOAT = 145, //!< No additional details 746 SURFACE_FORMAT_I32X32FLOAT = 146, //!< No additional details 747 SURFACE_FORMAT_R16G16B16A16SSCALED = 147, //!< No additional details 748 SURFACE_FORMAT_R16G16B16A16USCALED = 148, //!< No additional details 749 SURFACE_FORMAT_R32G32SSCALED = 149, //!< No additional details 750 SURFACE_FORMAT_R32G32USCALED = 150, //!< No additional details 751 SURFACE_FORMAT_R32G32SFIXED = 160, //!< No additional details 752 SURFACE_FORMAT_R64PASSTHRU = 161, //!< No additional details 753 SURFACE_FORMAT_B8G8R8A8UNORM = 192, //!< No additional details 754 SURFACE_FORMAT_B8G8R8A8UNORMSRGB = 193, //!< No additional details 755 SURFACE_FORMAT_R10G10B10A2UNORM = 194, //!< No additional details 756 SURFACE_FORMAT_R10G10B10A2UNORMSRGB = 195, //!< No additional details 757 SURFACE_FORMAT_R10G10B10A2UINT = 196, //!< No additional details 758 SURFACE_FORMAT_R10G10B10SNORMA2UNORM = 197, //!< No additional details 759 SURFACE_FORMAT_R8G8B8A8UNORM = 199, //!< No additional details 760 SURFACE_FORMAT_R8G8B8A8UNORMSRGB = 200, //!< No additional details 761 SURFACE_FORMAT_R8G8B8A8SNORM = 201, //!< No additional details 762 SURFACE_FORMAT_R8G8B8A8SINT = 202, //!< No additional details 763 SURFACE_FORMAT_R8G8B8A8UINT = 203, //!< No additional details 764 SURFACE_FORMAT_R16G16UNORM = 204, //!< No additional details 765 SURFACE_FORMAT_R16G16SNORM = 205, //!< No additional details 766 SURFACE_FORMAT_R16G16SINT = 206, //!< No additional details 767 SURFACE_FORMAT_R16G16UINT = 207, //!< No additional details 768 SURFACE_FORMAT_R16G16FLOAT = 208, //!< No additional details 769 SURFACE_FORMAT_B10G10R10A2UNORM = 209, //!< No additional details 770 SURFACE_FORMAT_B10G10R10A2UNORMSRGB = 210, //!< No additional details 771 SURFACE_FORMAT_R11G11B10FLOAT = 211, //!< No additional details 772 SURFACE_FORMAT_R10G10B10FLOATA2UNORM = 213, //!< No additional details 773 SURFACE_FORMAT_R32SINT = 214, //!< No additional details 774 SURFACE_FORMAT_R32UINT = 215, //!< No additional details 775 SURFACE_FORMAT_R32FLOAT = 216, //!< No additional details 776 SURFACE_FORMAT_R24UNORMX8TYPELESS = 217, //!< No additional details 777 SURFACE_FORMAT_X24TYPELESSG8UINT = 218, //!< No additional details 778 SURFACE_FORMAT_L32UNORM = 221, //!< No additional details 779 SURFACE_FORMAT_A32UNORM = 222, //!< No additional details 780 SURFACE_FORMAT_L16A16UNORM = 223, //!< No additional details 781 SURFACE_FORMAT_I24X8UNORM = 224, //!< No additional details 782 SURFACE_FORMAT_L24X8UNORM = 225, //!< No additional details 783 SURFACE_FORMAT_A24X8UNORM = 226, //!< No additional details 784 SURFACE_FORMAT_I32FLOAT = 227, //!< No additional details 785 SURFACE_FORMAT_L32FLOAT = 228, //!< No additional details 786 SURFACE_FORMAT_A32FLOAT = 229, //!< No additional details 787 SURFACE_FORMAT_X8B8UNORMG8R8SNORM = 230, //!< No additional details 788 SURFACE_FORMAT_A8X8UNORMG8R8SNORM = 231, //!< No additional details 789 SURFACE_FORMAT_B8X8UNORMG8R8SNORM = 232, //!< No additional details 790 SURFACE_FORMAT_B8G8R8X8UNORM = 233, //!< No additional details 791 SURFACE_FORMAT_B8G8R8X8UNORMSRGB = 234, //!< No additional details 792 SURFACE_FORMAT_R8G8B8X8UNORM = 235, //!< No additional details 793 SURFACE_FORMAT_R8G8B8X8UNORMSRGB = 236, //!< No additional details 794 SURFACE_FORMAT_R9G9B9E5SHAREDEXP = 237, //!< No additional details 795 SURFACE_FORMAT_B10G10R10X2UNORM = 238, //!< No additional details 796 SURFACE_FORMAT_L16A16FLOAT = 240, //!< No additional details 797 SURFACE_FORMAT_R32UNORM = 241, //!< No additional details 798 SURFACE_FORMAT_R32SNORM = 242, //!< No additional details 799 SURFACE_FORMAT_R10G10B10X2USCALED = 243, //!< No additional details 800 SURFACE_FORMAT_R8G8B8A8SSCALED = 244, //!< No additional details 801 SURFACE_FORMAT_R8G8B8A8USCALED = 245, //!< No additional details 802 SURFACE_FORMAT_R16G16SSCALED = 246, //!< No additional details 803 SURFACE_FORMAT_R16G16USCALED = 247, //!< No additional details 804 SURFACE_FORMAT_R32SSCALED = 248, //!< No additional details 805 SURFACE_FORMAT_R32USCALED = 249, //!< No additional details 806 SURFACE_FORMAT_B5G6R5UNORM = 256, //!< No additional details 807 SURFACE_FORMAT_B5G6R5UNORMSRGB = 257, //!< No additional details 808 SURFACE_FORMAT_B5G5R5A1UNORM = 258, //!< No additional details 809 SURFACE_FORMAT_B5G5R5A1UNORMSRGB = 259, //!< No additional details 810 SURFACE_FORMAT_B4G4R4A4UNORM = 260, //!< No additional details 811 SURFACE_FORMAT_B4G4R4A4UNORMSRGB = 261, //!< No additional details 812 SURFACE_FORMAT_R8G8UNORM = 262, //!< No additional details 813 SURFACE_FORMAT_R8G8SNORM = 263, //!< No additional details 814 SURFACE_FORMAT_R8G8SINT = 264, //!< No additional details 815 SURFACE_FORMAT_R8G8UINT = 265, //!< No additional details 816 SURFACE_FORMAT_R16UNORM = 266, //!< No additional details 817 SURFACE_FORMAT_R16SNORM = 267, //!< No additional details 818 SURFACE_FORMAT_R16SINT = 268, //!< No additional details 819 SURFACE_FORMAT_R16UINT = 269, //!< No additional details 820 SURFACE_FORMAT_R16FLOAT = 270, //!< No additional details 821 SURFACE_FORMAT_A8P8UNORMPALETTE0 = 271, //!< No additional details 822 SURFACE_FORMAT_A8P8UNORMPALETTE1 = 272, //!< No additional details 823 SURFACE_FORMAT_I16UNORM = 273, //!< No additional details 824 SURFACE_FORMAT_L16UNORM = 274, //!< No additional details 825 SURFACE_FORMAT_A16UNORM = 275, //!< No additional details 826 SURFACE_FORMAT_L8A8UNORM = 276, //!< No additional details 827 SURFACE_FORMAT_I16FLOAT = 277, //!< No additional details 828 SURFACE_FORMAT_L16FLOAT = 278, //!< No additional details 829 SURFACE_FORMAT_A16FLOAT = 279, //!< No additional details 830 SURFACE_FORMAT_L8A8UNORMSRGB = 280, //!< No additional details 831 SURFACE_FORMAT_R5G5SNORMB6UNORM = 281, //!< No additional details 832 SURFACE_FORMAT_B5G5R5X1UNORM = 282, //!< No additional details 833 SURFACE_FORMAT_B5G5R5X1UNORMSRGB = 283, //!< No additional details 834 SURFACE_FORMAT_R8G8SSCALED = 284, //!< No additional details 835 SURFACE_FORMAT_R8G8USCALED = 285, //!< No additional details 836 SURFACE_FORMAT_R16SSCALED = 286, //!< No additional details 837 SURFACE_FORMAT_R16USCALED = 287, //!< No additional details 838 SURFACE_FORMAT_P8A8UNORMPALETTE0 = 290, //!< No additional details 839 SURFACE_FORMAT_P8A8UNORMPALETTE1 = 291, //!< No additional details 840 SURFACE_FORMAT_A1B5G5R5UNORM = 292, //!< No additional details 841 SURFACE_FORMAT_A4B4G4R4UNORM = 293, //!< No additional details 842 SURFACE_FORMAT_L8A8UINT = 294, //!< No additional details 843 SURFACE_FORMAT_L8A8SINT = 295, //!< No additional details 844 SURFACE_FORMAT_R8UNORM = 320, //!< No additional details 845 SURFACE_FORMAT_R8SNORM = 321, //!< No additional details 846 SURFACE_FORMAT_R8SINT = 322, //!< No additional details 847 SURFACE_FORMAT_R8UINT = 323, //!< No additional details 848 SURFACE_FORMAT_A8UNORM = 324, //!< No additional details 849 SURFACE_FORMAT_I8UNORM = 325, //!< No additional details 850 SURFACE_FORMAT_L8UNORM = 326, //!< No additional details 851 SURFACE_FORMAT_P4A4UNORMPALETTE0 = 327, //!< No additional details 852 SURFACE_FORMAT_A4P4UNORMPALETTE0 = 328, //!< No additional details 853 SURFACE_FORMAT_R8SSCALED = 329, //!< No additional details 854 SURFACE_FORMAT_R8USCALED = 330, //!< No additional details 855 SURFACE_FORMAT_P8UNORMPALETTE0 = 331, //!< No additional details 856 SURFACE_FORMAT_L8UNORMSRGB = 332, //!< No additional details 857 SURFACE_FORMAT_P8UNORMPALETTE1 = 333, //!< No additional details 858 SURFACE_FORMAT_P4A4UNORMPALETTE1 = 334, //!< No additional details 859 SURFACE_FORMAT_A4P4UNORMPALETTE1 = 335, //!< No additional details 860 SURFACE_FORMAT_Y8UNORM = 336, //!< No additional details 861 SURFACE_FORMAT_L8UINT = 338, //!< No additional details 862 SURFACE_FORMAT_L8SINT = 339, //!< No additional details 863 SURFACE_FORMAT_I8UINT = 340, //!< No additional details 864 SURFACE_FORMAT_I8SINT = 341, //!< No additional details 865 SURFACE_FORMAT_DXT1RGBSRGB = 384, //!< No additional details 866 SURFACE_FORMAT_R1UNORM = 385, //!< SET0_LEGACY: Undefined behavior if used in any feature added for GEN11+. See Legacy sampler feature page for detalls 867 SURFACE_FORMAT_YCRCBNORMAL = 386, //!< No additional details 868 SURFACE_FORMAT_YCRCBSWAPUVY = 387, //!< No additional details 869 SURFACE_FORMAT_P2UNORMPALETTE0 = 388, //!< No additional details 870 SURFACE_FORMAT_P2UNORMPALETTE1 = 389, //!< No additional details 871 SURFACE_FORMAT_BC1UNORM = 390, //!< (DXT1) 872 SURFACE_FORMAT_BC2UNORM = 391, //!< (DXT2/3) 873 SURFACE_FORMAT_BC3UNORM = 392, //!< (DXT4/5) 874 SURFACE_FORMAT_BC4UNORM = 393, //!< No additional details 875 SURFACE_FORMAT_BC5UNORM = 394, //!< No additional details 876 SURFACE_FORMAT_BC1UNORMSRGB = 395, //!< (DXT1_SRGB) 877 SURFACE_FORMAT_BC2UNORMSRGB = 396, //!< (DXT2/3_SRGB) 878 SURFACE_FORMAT_BC3UNORMSRGB = 397, //!< (DXT4/5_SRGB) 879 SURFACE_FORMAT_MONO8 = 398, //!< SET0_LEGACY: Undefined behavior if used in any feature added for GEN11+. See Legacy sampler feature page for detalls 880 SURFACE_FORMAT_YCRCBSWAPUV = 399, //!< No additional details 881 SURFACE_FORMAT_YCRCBSWAPY = 400, //!< No additional details 882 SURFACE_FORMAT_DXT1RGB = 401, //!< No additional details 883 SURFACE_FORMAT_R8G8B8UNORM = 403, //!< No additional details 884 SURFACE_FORMAT_R8G8B8SNORM = 404, //!< No additional details 885 SURFACE_FORMAT_R8G8B8SSCALED = 405, //!< No additional details 886 SURFACE_FORMAT_R8G8B8USCALED = 406, //!< No additional details 887 SURFACE_FORMAT_R64G64B64A64FLOAT = 407, //!< No additional details 888 SURFACE_FORMAT_R64G64B64FLOAT = 408, //!< No additional details 889 SURFACE_FORMAT_BC4SNORM = 409, //!< No additional details 890 SURFACE_FORMAT_BC5SNORM = 410, //!< No additional details 891 SURFACE_FORMAT_R16G16B16FLOAT = 411, //!< No additional details 892 SURFACE_FORMAT_R16G16B16UNORM = 412, //!< No additional details 893 SURFACE_FORMAT_R16G16B16SNORM = 413, //!< No additional details 894 SURFACE_FORMAT_R16G16B16SSCALED = 414, //!< No additional details 895 SURFACE_FORMAT_R16G16B16USCALED = 415, //!< No additional details 896 SURFACE_FORMAT_BC6HSF16 = 417, //!< No additional details 897 SURFACE_FORMAT_BC7UNORM = 418, //!< No additional details 898 SURFACE_FORMAT_BC7UNORMSRGB = 419, //!< No additional details 899 SURFACE_FORMAT_BC6HUF16 = 420, //!< No additional details 900 SURFACE_FORMAT_PLANAR4208 = 421, //!< No additional details 901 SURFACE_FORMAT_PLANAR42016 = 422, //!< No additional details 902 SURFACE_FORMAT_R8G8B8UNORMSRGB = 424, //!< No additional details 903 SURFACE_FORMAT_ETC1RGB8 = 425, //!< No additional details 904 SURFACE_FORMAT_ETC2RGB8 = 426, //!< No additional details 905 SURFACE_FORMAT_EACR11 = 427, //!< No additional details 906 SURFACE_FORMAT_EACRG11 = 428, //!< No additional details 907 SURFACE_FORMAT_EACSIGNEDR11 = 429, //!< No additional details 908 SURFACE_FORMAT_EACSIGNEDRG11 = 430, //!< No additional details 909 SURFACE_FORMAT_ETC2SRGB8 = 431, //!< No additional details 910 SURFACE_FORMAT_R16G16B16UINT = 432, //!< No additional details 911 SURFACE_FORMAT_R16G16B16SINT = 433, //!< No additional details 912 SURFACE_FORMAT_R32SFIXED = 434, //!< No additional details 913 SURFACE_FORMAT_R10G10B10A2SNORM = 435, //!< No additional details 914 SURFACE_FORMAT_R10G10B10A2USCALED = 436, //!< No additional details 915 SURFACE_FORMAT_R10G10B10A2SSCALED = 437, //!< No additional details 916 SURFACE_FORMAT_R10G10B10A2SINT = 438, //!< No additional details 917 SURFACE_FORMAT_B10G10R10A2SNORM = 439, //!< No additional details 918 SURFACE_FORMAT_B10G10R10A2USCALED = 440, //!< No additional details 919 SURFACE_FORMAT_B10G10R10A2SSCALED = 441, //!< No additional details 920 SURFACE_FORMAT_B10G10R10A2UINT = 442, //!< No additional details 921 SURFACE_FORMAT_B10G10R10A2SINT = 443, //!< No additional details 922 SURFACE_FORMAT_R64G64B64A64PASSTHRU = 444, //!< No additional details 923 SURFACE_FORMAT_R64G64B64PASSTHRU = 445, //!< No additional details 924 SURFACE_FORMAT_ETC2RGB8PTA = 448, //!< No additional details 925 SURFACE_FORMAT_ETC2SRGB8PTA = 449, //!< No additional details 926 SURFACE_FORMAT_ETC2EACRGBA8 = 450, //!< No additional details 927 SURFACE_FORMAT_ETC2EACSRGB8A8 = 451, //!< No additional details 928 SURFACE_FORMAT_R8G8B8UINT = 456, //!< No additional details 929 SURFACE_FORMAT_R8G8B8SINT = 457, //!< No additional details 930 SURFACE_FORMAT_RAW = 511, //!< No additional details 931 }; 932 933 //! \brief SURFACE_TYPE 934 //! \details 935 //! This field defines the type of the surface. 936 enum SURFACE_TYPE 937 { 938 SURFACE_TYPE_SURFTYPE1D = 0, //!< Defines a 1-dimensional map or array of maps 939 SURFACE_TYPE_SURFTYPE2D = 1, //!< Defines a 2-dimensional map or array of maps 940 SURFACE_TYPE_SURFTYPE3D = 2, //!< Defines a 3-dimensional (volumetric) map 941 SURFACE_TYPE_SURFTYPECUBE = 3, //!< Defines a cube map or array of cube maps 942 SURFACE_TYPE_SURFTYPEBUFFER = 4, //!< Defines an element in a buffer 943 SURFACE_TYPE_SURFTYPERES5 = 5, //!< No additional details 944 SURFACE_TYPE_SURFTYPESCRATCH = 6, //!< Defines a structured buffer surface that is indexed by physical thread. 945 SURFACE_TYPE_SURFTYPENULL = 7, //!< Defines a null surface 946 }; 947 948 //! \brief SAMPLE_TAP_DISCARD_DISABLE 949 //! \details 950 //! This bit forces sample tap discard filter mode to be disabled for this 951 //! surface state. This bit must be set for surfaces which are no Alpha 952 //! Channel such as R8G8B8_UNORM. 953 enum SAMPLE_TAP_DISCARD_DISABLE 954 { 955 SAMPLE_TAP_DISCARD_DISABLE_DISABLE = 0, //!< When programmed to 0h, Sample Tap Discard filter mode is allowed and is not disabled by this bit. This bit is ignored if Sample Tap Discard is not enabled in the Sampler State. 956 SAMPLE_TAP_DISCARD_DISABLE_ENABLE = 1, //!< When programmed to 1h, Sample Tap Discard filter mode will be disabled even if enabled through Sampler State 957 }; 958 959 //! \brief CORNERTEXELMODE 960 //! \details 961 //! This field, when ENABLED, indicates when a surface is using corner 962 //! texel-mode for sampling. 963 //! Corner Texel Mode is ignored for Planar YUV/YCrCb surface 964 //! formats. 965 //! Corner Texel Mode is ignored for sample_8X8 and 966 //! sample_unorm messasge types. 967 //! Corner Texel Mode is not supported with Non-Normalized 968 //! Coordinates 969 //! 970 //! <!--StartFragment-->Does not support legacy sampler features 971 //! set0 See legacy sampler page for more details<!--EndFragment--> 972 enum CORNER_TEXEL_MODE 973 { 974 CORNER_TEXEL_MODE_DISABLE = 0, //!< When programmed to 0h, Corner Texel Mode is disabled. This means texel references are shifted a half-texel from the upper-right corner of the texture map which is the standard texel referencemode. 975 CORNER_TEXEL_MODE_ENABLE = 1, //!< When programmed to 1h, Corner Texel Mode is enabled. The location of a sampled texel on a texture map is shifted a half-texel to the upper-left, meaning texel (0,0) isin the exact upper-left corner of the surface. 976 }; 977 978 //! \brief NUMBEROFMULTISAMPLES 979 //! \details 980 //! This field indicates the number of multisamples on the surface. 981 enum NUMBER_OF_MULTISAMPLES 982 { 983 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT1 = 0, //!< No additional details 984 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT2 = 1, //!< No additional details 985 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT4 = 2, //!< No additional details 986 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT8 = 3, //!< No additional details 987 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT16 = 4, //!< No additional details 988 }; 989 990 //! \brief MULTISAMPLED_SURFACE_STORAGE_FORMAT 991 //! \details 992 //! This field indicates the storage format of the multisampled surface. 993 enum MULTISAMPLED_SURFACE_STORAGE_FORMAT 994 { 995 MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS = 0, //!< Multsampled surface was/is rendered as a render target 996 MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTHSTENCIL = 1, //!< Multisampled surface was rendered as a depth or stencil buffer 997 }; 998 999 //! \brief RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 1000 //! \details 1001 //! For Render Target Surfaces:This field specifies the rotation of 1002 //! this render target surface when being written to memory. 1003 enum RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 1004 { 1005 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG = 0, //!< No rotation (0 degrees) 1006 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_90DEG = 1, //!< Rotate by 90 degrees 1007 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_180DEG = 2, //!< Rotate by 180 degrees [for sample_unorm message] 1008 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_270DEG = 3, //!< Rotate by 270 degrees 1009 }; 1010 1011 enum DECOMPRESS_IN_L3 1012 { 1013 DECOMPRESS_IN_L3_DISABLE = 0, //!< When this field is set to 0h, the associated compressible surface, when accessed by sampler and data-port, can be compressed in L3. If the surface is not compressible, this bit field is ignored. 1014 DECOMPRESS_IN_L3_ENABLE = 1, //!< When this field is set to 1h, the associated compressible surface, when accessed by sampler and data-port, will be uncompressed in L3. If the surface is not compressible, this bit field is ignored. 1015 }; 1016 1017 //! \brief COHERENCY_TYPE 1018 //! \details 1019 //! Specifies the type of coherency maintained for this surface. 1020 enum COHERENCY_TYPE 1021 { 1022 COHERENCY_TYPE_SINGLE_GPUCOHERENT = 0, //!< Coherency is only maintained within a single GPU 1023 COHERENCY_TYPE_SYSTEMCOHERENT = 1, //!< Coherency is maintained across the system (CPU and all GPUs). 1024 COHERENCY_TYPE_MULTI_GPUCOHERENT = 2, //!< Coherency is maintained across all the GPUs but not with the CPU. 1025 }; 1026 1027 //! \brief EWA_DISABLE_FOR_CUBE 1028 //! \details 1029 //! Specifies if EWA mode for LOD quality improvement needs to be disabled 1030 //! for cube maps. 1031 enum EWA_DISABLE_FOR_CUBE 1032 { 1033 EWA_DISABLE_FOR_CUBE_ENABLE = 0, //!< EWA is enabled for cube maps 1034 EWA_DISABLE_FOR_CUBE_DISABLE = 1, //!< EWA is disabled for cube maps 1035 }; 1036 1037 //! \brief AUXILIARY_SURFACE_MODE 1038 //! \details 1039 //! Specifies what type of surface the Auxiliary surface is. The Auxiliary 1040 //! surface has its own base address and pitch, but otherwise shares or 1041 //! overrides other fields set for the primary surface, detailed in the 1042 //! programming notes below. 1043 enum AUXILIARY_SURFACE_MODE 1044 { 1045 AUXILIARY_SURFACE_MODE_AUXNONE = 0, //!< No Auxiliary surface is used 1046 AUXILIARY_SURFACE_MODE_AUXAPPEND = 1, //!< The Auxiliary surface is an append buffer 1047 AUXILIARY_SURFACE_MODE_AUXMCS = 2, //!< Auxiliary surface is Multisample Control Surface, used by sample compression. 1048 AUXILIARY_SURFACE_MODE_AUXAMFS = 3, //!< Auxiliary surface is AMFScontrol surface.Also known as SFT (Sampler Feedback Texture) 1049 }; 1050 1051 //! \brief YUV_INTERPOLATION_ENABLE 1052 //! \details 1053 //! This bit controls whether a Non-Planar YUV4:2:2surfaces use interpolated 1054 //! or replicated U and V channels for input to the Sampler filter. 1055 //! Programming to 1h causes interpolation of U and V channels. In this case 1056 //! the chrominance for odd pixels is computed by an interpolation between 1057 //! adjacent even pixels. Programming to 0h causes the chrominance to be 1058 //! copied from the pixel to the left. Note this no longer has any effect 1059 //! on planar sufaces. This bit must NOT be set for planar 1060 //! surfaces. 1061 enum YUV_INTERPOLATION_ENABLE 1062 { 1063 YUV_INTERPOLATION_ENABLE_DISABLE = 0, //!< Programming to 0h causes the sampler to replicate U and V channels. This will lead to lower quality in certain cases where the YUV surface is being filtered (e.g. linear). 1064 YUV_INTERPOLATION_ENABLE_ENABLE = 1, //!< Programming to 1h causes the sampler to interpolate the U and V channels between the horizontally neighboring pixels. This will improve image quality if the surface is being filtered. 1065 }; 1066 1067 //! \brief HALF_PITCH_FOR_CHROMA 1068 //! \details 1069 //! 1070 //! style="font-family: 1071 //! "Arial","sans-serif"; font-size: 10pt; 1072 //! mso-fareast-font-family: "Times New Roman"; mso-ansi-language: 1073 //! EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA;"> 1074 //! <font color="#000000">This bit enables support for 1075 //! half-pitch chroma planes for Planar YUV surfaces. It is ignored for 1076 //! Non-Planar surfaces. For planar surfaces it allows the chroma planes to 1077 //! be one-half the width of a the Y (Luma) plane.</font> 1078 //! 1079 //! style="font-family: 1080 //! "Arial","sans-serif"; font-size: 10pt; 1081 //! mso-fareast-font-family: "Times New Roman"; mso-ansi-language: 1082 //! EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA;"> 1083 //! <font color="#000000">For example, should be set to 0h for 1084 //! NV12 surfaces.</font> 1085 //! 1086 //! style="font-family: 1087 //! "Arial","sans-serif"; font-size: 10pt; 1088 //! mso-fareast-font-family: "Times New Roman"; mso-ansi-language: 1089 //! EN-US; mso-fareast-language: EN-US; mso-bidi-language: AR-SA;"> 1090 //! <font color="#000000">Must be set to 1h for YV12 1091 //! surfaces.</font> 1092 //! 1093 enum HALF_PITCH_FOR_CHROMA 1094 { 1095 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< <font color="#000000">Setting this bit to 0h (default) causes Chroma planes to be treated as full width (same as Y plane).</font> 1096 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< <font color="#000000">Setting this bit to 1h causes Chroma planes (U and V) to be treated as half the width of the Luma (Y) plane.</font> 1097 }; 1098 1099 //! \brief SHADER_CHANNEL_SELECT_ALPHA 1100 //! \details 1101 //! See Shader Channel Select Red for details. 1102 enum SHADER_CHANNEL_SELECT_ALPHA 1103 { 1104 SHADER_CHANNEL_SELECT_ALPHA_ZERO = 0, //!< No additional details 1105 SHADER_CHANNEL_SELECT_ALPHA_ONE = 1, //!< No additional details 1106 SHADER_CHANNEL_SELECT_ALPHA_RED = 4, //!< Shader channel is set to surface red channel 1107 SHADER_CHANNEL_SELECT_ALPHA_GREEN = 5, //!< Shader channel is set to surface green channel 1108 SHADER_CHANNEL_SELECT_ALPHA_BLUE = 6, //!< Shader channel is set to surface blue channel 1109 SHADER_CHANNEL_SELECT_ALPHA_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1110 }; 1111 1112 //! \brief SHADER_CHANNEL_SELECT_BLUE 1113 //! \details 1114 //! See Shader Channel Select Red for details. 1115 enum SHADER_CHANNEL_SELECT_BLUE 1116 { 1117 SHADER_CHANNEL_SELECT_BLUE_ZERO = 0, //!< No additional details 1118 SHADER_CHANNEL_SELECT_BLUE_ONE = 1, //!< No additional details 1119 SHADER_CHANNEL_SELECT_BLUE_RED = 4, //!< Shader channel is set to surface red channel 1120 SHADER_CHANNEL_SELECT_BLUE_GREEN = 5, //!< Shader channel is set to surface green channel 1121 SHADER_CHANNEL_SELECT_BLUE_BLUE = 6, //!< Shader channel is set to surface blue channel 1122 SHADER_CHANNEL_SELECT_BLUE_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1123 }; 1124 1125 //! \brief SHADER_CHANNEL_SELECT_GREEN 1126 //! \details 1127 //! See Shader Channel Select Red for details. 1128 enum SHADER_CHANNEL_SELECT_GREEN 1129 { 1130 SHADER_CHANNEL_SELECT_GREEN_ZERO = 0, //!< No additional details 1131 SHADER_CHANNEL_SELECT_GREEN_ONE = 1, //!< No additional details 1132 SHADER_CHANNEL_SELECT_GREEN_RED = 4, //!< Shader channel is set to surface red channel 1133 SHADER_CHANNEL_SELECT_GREEN_GREEN = 5, //!< Shader channel is set to surface green channel 1134 SHADER_CHANNEL_SELECT_GREEN_BLUE = 6, //!< Shader channel is set to surface blue channel 1135 SHADER_CHANNEL_SELECT_GREEN_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1136 }; 1137 1138 //! \brief SHADER_CHANNEL_SELECT_RED 1139 //! \details 1140 //! Specifies which surface channel is read or written in the Red shader 1141 //! channel. 1142 enum SHADER_CHANNEL_SELECT_RED 1143 { 1144 SHADER_CHANNEL_SELECT_RED_ZERO = 0, //!< No additional details 1145 SHADER_CHANNEL_SELECT_RED_ONE = 1, //!< No additional details 1146 SHADER_CHANNEL_SELECT_RED_RED = 4, //!< Shader channel is set to surface red channel 1147 SHADER_CHANNEL_SELECT_RED_GREEN = 5, //!< Shader channel is set to surface green channel 1148 SHADER_CHANNEL_SELECT_RED_BLUE = 6, //!< Shader channel is set to surface blue channel 1149 SHADER_CHANNEL_SELECT_RED_ALPHA = 7, //!< Shader channel is set to surface alpha channel 1150 }; 1151 1152 //! \brief COMPRESSIONFORMAT 1153 //! \details 1154 //! Specifies 4bit unified 3D/Media compression format 1155 enum COMPRESSION_FORMAT 1156 { 1157 COMPRESSION_FORMAT_CMFR8 = 0, //!< Single 8bit channel format 1158 COMPRESSION_FORMAT_CMFR8G8 = 1, //!< Two 8bit channel format 1159 COMPRESSION_FORMAT_CMFR8G8B8A8 = 2, //!< Four 8bit channel format 1160 COMPRESSION_FORMAT_CMFR10G10B10A2 = 3, //!< Three 10bit channels and One 2bit channel 1161 COMPRESSION_FORMAT_CMFR11G11B10 = 4, //!< Two 11bit channels and One 10bit channel 1162 COMPRESSION_FORMAT_CMFR16 = 5, //!< Single 16bit channel format 1163 COMPRESSION_FORMAT_CMFR16G16 = 6, //!< Two 16bit channel format 1164 COMPRESSION_FORMAT_CMFR16G16B16A16 = 7, //!< Four 16bit channels 1165 COMPRESSION_FORMAT_CMFR32 = 8, //!< Single 32bit channel 1166 COMPRESSION_FORMAT_CMFR32G32 = 9, //!< Two 32bit channels 1167 COMPRESSION_FORMAT_CMFR32G32B32A32 = 10, //!< Four 32bit channels 1168 COMPRESSION_FORMAT_CMFY16U16Y16V16 = 11, //!< Packed YUV 16/12/10 bit per channel 1169 COMPRESSION_FORMAT_CMFML8 = 15, //!< Machine Learning format / Generic data 1170 }; 1171 1172 //! \name Initializations 1173 1174 //! \brief Explicit member initialization function 1175 RENDER_SURFACE_STATE_CMD(); 1176 1177 static const size_t dwSize = 16; 1178 static const size_t byteSize = 64; 1179 }; 1180 1181 //! 1182 //! \brief MEDIA_SURFACE_STATE 1183 //! \details 1184 //! This is the SURFACE_STATE used by only deinterlace, sample_8x8, and VME 1185 //! messages. 1186 //! 1187 struct MEDIA_SURFACE_STATE_CMD 1188 { 1189 union 1190 { 1191 struct 1192 { 1193 uint32_t CompressionFormat : __CODEGEN_BITFIELD( 0, 3) ; //!< COMPRESSION_FORMAT 1194 uint32_t Reserved4 : __CODEGEN_BITFIELD( 4, 15) ; //!< Reserved 1195 uint32_t YOffset : __CODEGEN_BITFIELD(16, 19) ; //!< Y Offset 1196 uint32_t XOffset : __CODEGEN_BITFIELD(20, 26) ; //!< X Offset 1197 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 29) ; //!< Reserved 1198 uint32_t Rotation : __CODEGEN_BITFIELD(30, 31) ; //!< ROTATION 1199 }; 1200 uint32_t Value; 1201 } DW0; 1202 union 1203 { 1204 struct 1205 { 1206 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION 1207 uint32_t PictureStructure : __CODEGEN_BITFIELD( 2, 3) ; //!< PICTURE_STRUCTURE 1208 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1209 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1210 }; 1211 uint32_t Value; 1212 } DW1; 1213 union 1214 { 1215 struct 1216 { 1217 uint32_t TileMode : __CODEGEN_BITFIELD( 0, 1) ; //!< TILE_MODE 1218 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 1219 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 20) ; //!< Surface Pitch 1220 uint32_t AddressControl : __CODEGEN_BITFIELD(21, 21) ; //!< ADDRESS_CONTROL 1221 uint32_t CompressionAccumulationBufferEnable : __CODEGEN_BITFIELD(22, 22) ; //!< Compression Accumulation Buffer Enable 1222 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 1223 uint32_t CrVCbUPixelOffsetVDirectionMsb : __CODEGEN_BITFIELD(24, 24) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1224 uint32_t CrVCbUPixelOffsetUDirection : __CODEGEN_BITFIELD(25, 25) ; //!< CRVCBU_PIXEL_OFFSET_U_DIRECTION 1225 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(26, 26) ; //!< Interleave Chroma 1226 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 1227 }; 1228 uint32_t Value; 1229 } DW2; 1230 union 1231 { 1232 struct 1233 { 1234 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U(Cb) 1235 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1236 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U(Cb) 1237 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1238 }; 1239 uint32_t Value; 1240 } DW3; 1241 union 1242 { 1243 struct 1244 { 1245 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for V(Cr) 1246 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1247 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for V(Cr) 1248 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1249 }; 1250 uint32_t Value; 1251 } DW4; 1252 union 1253 { 1254 struct 1255 { 1256 uint32_t SurfaceMemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< SURFACE_MEMORY_OBJECT_CONTROL_STATE 1257 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 29) ; //!< Reserved 1258 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(30, 30) ; //!< Vertical Line Stride Offset 1259 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(31, 31) ; //!< Vertical Line Stride 1260 }; 1261 uint32_t Value; 1262 } DW5; 1263 union 1264 { 1265 struct 1266 { 1267 uint32_t SurfaceBaseAddress ; //!< Surface Base Address 1268 }; 1269 uint32_t Value; 1270 } DW6; 1271 union 1272 { 1273 struct 1274 { 1275 uint32_t SurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Surface Base Address High 1276 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1277 }; 1278 uint32_t Value; 1279 } DW7; 1280 1281 //! \name Local enumerations 1282 1283 //! \brief COMPRESSION_FORMAT 1284 //! \details 1285 //! Specifies Compression format 1286 enum COMPRESSION_FORMAT 1287 { 1288 COMPRESSION_FORMAT_CMFR8 = 0, //!< Single 8bit channel format 1289 COMPRESSION_FORMAT_CMFR8G8 = 1, //!< Two 8bit channel format 1290 COMPRESSION_FORMAT_CMFR8G8B8A8 = 2, //!< Four 8bit channel format 1291 COMPRESSION_FORMAT_CMFR10G10B10A2 = 3, //!< Three 10bit channels and One 2bit channel 1292 COMPRESSION_FORMAT_CMFR11G11B10 = 4, //!< Two 11bit channels and One 10bit channel 1293 COMPRESSION_FORMAT_CMFR16 = 5, //!< Single 16bit channel format 1294 COMPRESSION_FORMAT_CMFR16G16 = 6, //!< Two 16bit channel format 1295 COMPRESSION_FORMAT_CMFR16G16B16A16 = 7, //!< Four 16bit channels 1296 COMPRESSION_FORMAT_CMFR32 = 8, //!< Single 32bit channel 1297 COMPRESSION_FORMAT_CMFR32G32 = 9, //!< Two 32bit channels 1298 COMPRESSION_FORMAT_CMFR32G32B32A32 = 10, //!< Four 32bit channels 1299 COMPRESSION_FORMAT_CMFY16U16Y16V16 = 11, //!< Packed YUV 16/12/10 bit per channel 1300 COMPRESSION_FORMAT_CMFML8 = 15, //!< Machine Learning format / Generic data 1301 }; 1302 1303 //! \brief ROTATION 1304 //! \details 1305 //! Rotation is only supported only with AVS function messages and not with 1306 //! HDC direct write and 16x8 AVS messages. 1307 enum ROTATION 1308 { 1309 ROTATION_NOROTATIONOR0DEGREE = 0, //!< No additional details 1310 ROTATION_90DEGREEROTATION = 1, //!< No additional details 1311 ROTATION_180DEGREEROTATION = 2, //!< No additional details 1312 ROTATION_270DEGREEROTATION = 3, //!< No additional details 1313 }; 1314 1315 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION 1316 //! \details 1317 //! Specifies the distance to the U/V values with respect to the even 1318 //! numbered Y channels in the V direction 1319 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION 1320 { 1321 CRVCBU_PIXEL_OFFSET_V_DIRECTION_UNNAMED0 = 0, //!< No additional details 1322 }; 1323 1324 //! \brief PICTURE_STRUCTURE 1325 //! \details 1326 //! Specifies the encoding of the current picture. 1327 enum PICTURE_STRUCTURE 1328 { 1329 PICTURE_STRUCTURE_FRAMEPICTURE = 0, //!< No additional details 1330 PICTURE_STRUCTURE_TOPFIELDPICTURE = 1, //!< No additional details 1331 PICTURE_STRUCTURE_BOTTOMFIELDPICTURE = 2, //!< No additional details 1332 PICTURE_STRUCTURE_INVALID_NOTALLOWED = 3, //!< No additional details 1333 }; 1334 1335 //! \brief TILE_MODE 1336 //! \details 1337 //! This field specifies the type of memory tiling (Linear, WMajor, XMajor, 1338 //! or YMajor) employed to tile this surface. See Memory Interface Functions 1339 //! for details on memory tiling and restrictions. 1340 enum TILE_MODE 1341 { 1342 TILE_MODE_TILEMODELINEAR = 0, //!< Linear mode (no tiling) 1343 TILE_MODE_TILES_64K = 1, //!< For media surface state, Tile S (64K) is not allowed. 1344 TILE_MODE_TILEMODEXMAJOR = 2, //!< X major tiling 1345 TILE_MODE_TILEF = 3, //!< No additional details 1346 }; 1347 1348 enum ADDRESS_CONTROL 1349 { 1350 ADDRESS_CONTROL_CLAMP = 0, //!< Clamp 1351 ADDRESS_CONTROL_MIRROR = 1, //!< Mirror 1352 }; 1353 1354 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1355 //! \details 1356 //! Specifies the distance to the U/V values with respect to the even 1357 //! numbered Y channels in the V direction 1358 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1359 { 1360 CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB_UNNAMED0 = 0, //!< No additional details 1361 }; 1362 1363 //! \brief CRVCBU_PIXEL_OFFSET_U_DIRECTION 1364 //! \details 1365 //! Specifies the distance to the U/V values with respect to the even 1366 //! numbered Y channels in the U direction 1367 enum CRVCBU_PIXEL_OFFSET_U_DIRECTION 1368 { 1369 CRVCBU_PIXEL_OFFSET_U_DIRECTION_UNNAMED0 = 0, //!< No additional details 1370 }; 1371 1372 //! \brief SURFACE_FORMAT 1373 //! \details 1374 //! Specifies the format of the surface. All of the Y and G channels will 1375 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1. 1376 enum SURFACE_FORMAT 1377 { 1378 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 1379 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 1380 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 1381 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 1382 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 1383 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 only 1384 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 AVS only 1385 SURFACE_FORMAT_R8B8UNORM_CRCB = 10, //!< Sample_8x8 AVS only 1386 SURFACE_FORMAT_R8UNORM_CRCB = 11, //!< Sample_8x8 AVS only 1387 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 AVS only 1388 SURFACE_FORMAT_A8Y8U8V8UNORM = 13, //!< Sample_8x8 AVS only 1389 SURFACE_FORMAT_B8G8R8A8UNORM = 14, //!< Sample_8x8 AVS only 1390 SURFACE_FORMAT_R16G16B16A16 = 15, //!< Sample_8x8 AVS only 1391 SURFACE_FORMAT_PLANAR4228 = 18, //!< Sample_8x8 AVS only 1392 SURFACE_FORMAT_PLANAR42016 = 23, //!< Sample_8x8 AVS only 1393 SURFACE_FORMAT_R16B16UNORM_CRCB = 24, //!< Sample_8x8 AVS only 1394 SURFACE_FORMAT_R16UNORM_CRCB = 25, //!< Sample_8x8 AVS only 1395 SURFACE_FORMAT_Y16UNORM = 26, //!< Sample_8x8 AVS only 1396 }; 1397 1398 //! \brief SURFACE_MEMORY_OBJECT_CONTROL_STATE 1399 //! \details 1400 //! This 7-bit field is used in various state commands and indirect state 1401 //! objects to define cacheability and other attributes related to memory 1402 //! objects. 1403 enum SURFACE_MEMORY_OBJECT_CONTROL_STATE 1404 { 1405 SURFACE_MEMORY_OBJECT_CONTROL_STATE_DEFAULTVAUEDESC = 0, //!< No additional details 1406 }; 1407 1408 //! \name Initializations 1409 1410 //! \brief Explicit member initialization function 1411 MEDIA_SURFACE_STATE_CMD(); 1412 1413 static const size_t dwSize = 8; 1414 static const size_t byteSize = 32; 1415 }; 1416 1417 //! 1418 //! \brief SAMPLER_STATE 1419 //! \details 1420 //! This is the normal sampler state used by all messages that use 1421 //! SAMPLER_STATE except sample_8x8 and deinterlace. The sampler state is 1422 //! stored as an array of up to 16 elements, each of which contains the 1423 //! dwords described here. The start of each element is spaced 4 dwords 1424 //! apart. The first element of the sampler state array is aligned to a 1425 //! 32-byte boundary. 1426 //! 1427 struct SAMPLER_STATE_CMD 1428 { 1429 union 1430 { 1431 struct 1432 { 1433 uint32_t LodAlgorithm : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_ALGORITHM 1434 uint32_t TextureLodBias : __CODEGEN_BITFIELD( 1, 13) ; //!< Texture LOD Bias 1435 uint32_t MinModeFilter : __CODEGEN_BITFIELD(14, 16) ; //!< MIN_MODE_FILTER 1436 uint32_t MagModeFilter : __CODEGEN_BITFIELD(17, 19) ; //!< MAG_MODE_FILTER 1437 uint32_t MipModeFilter : __CODEGEN_BITFIELD(20, 21) ; //!< MIP_MODE_FILTER 1438 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 25) ; //!< Reserved 1439 uint32_t LowQualityCubeCornerModeEnable : __CODEGEN_BITFIELD(26, 26) ; //!< LOW_QUALITY_CUBE_CORNER_MODE_ENABLE 1440 uint32_t LodPreclampMode : __CODEGEN_BITFIELD(27, 28) ; //!< LOD_PRECLAMP_MODE 1441 uint32_t Reserved29 : __CODEGEN_BITFIELD(29, 29) ; //!< Reserved 1442 uint32_t CpsLodCompensationEnable : __CODEGEN_BITFIELD(30, 30) ; //!< CPS LOD Compensation Enable 1443 uint32_t SamplerDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Sampler Disable 1444 }; 1445 uint32_t Value; 1446 } DW0; 1447 union 1448 { 1449 struct 1450 { 1451 uint32_t CubeSurfaceControlMode : __CODEGEN_BITFIELD( 0, 0) ; //!< CUBE_SURFACE_CONTROL_MODE 1452 uint32_t ShadowFunction : __CODEGEN_BITFIELD( 1, 3) ; //!< SHADOW_FUNCTION 1453 uint32_t ChromakeyMode : __CODEGEN_BITFIELD( 4, 4) ; //!< CHROMAKEY_MODE 1454 uint32_t ChromakeyIndex : __CODEGEN_BITFIELD( 5, 6) ; //!< ChromaKey Index 1455 uint32_t ChromakeyEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< ChromaKey Enable 1456 uint32_t MaxLod : __CODEGEN_BITFIELD( 8, 19) ; //!< Max LOD 1457 uint32_t MinLod : __CODEGEN_BITFIELD(20, 31) ; //!< Min LOD 1458 }; 1459 uint32_t Value; 1460 } DW1; 1461 union 1462 { 1463 struct 1464 { 1465 uint32_t LodClampMagnificationMode : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_CLAMP_MAGNIFICATION_MODE 1466 uint32_t SrgbDecode : __CODEGEN_BITFIELD( 1, 1) ; //!< SRGB_DECODE 1467 uint32_t ReturnFilterWeightForNullTexels : __CODEGEN_BITFIELD( 2, 2) ; //!< RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1468 uint32_t ReturnFilterWeightForBorderTexels : __CODEGEN_BITFIELD( 3, 3) ; //!< RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1469 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 1470 uint32_t ForceGather4Behavior : __CODEGEN_BITFIELD( 5, 5) ; //!< Force gather4 Behavior 1471 uint32_t IndirectStatePointer : __CODEGEN_BITFIELD( 6, 23) ; //!< Indirect State Pointer 1472 uint32_t ExtendedIndirectStatePointer : __CODEGEN_BITFIELD(24, 31) ; //!< Extended Indirect State Pointer 1473 }; 1474 uint32_t Value; 1475 } DW2; 1476 union 1477 { 1478 struct 1479 { 1480 uint32_t TczAddressControlMode : __CODEGEN_BITFIELD( 0, 2) ; //!< TCZ_ADDRESS_CONTROL_MODE 1481 uint32_t TcyAddressControlMode : __CODEGEN_BITFIELD( 3, 5) ; //!< TCY_ADDRESS_CONTROL_MODE 1482 uint32_t TcxAddressControlMode : __CODEGEN_BITFIELD( 6, 8) ; //!< TCX_ADDRESS_CONTROL_MODE 1483 uint32_t ReductionTypeEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Reduction Type Enable 1484 uint32_t NonNormalizedCoordinateEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Non-normalized Coordinate Enable 1485 uint32_t MipLinearFilterQuality : __CODEGEN_BITFIELD(11, 12) ; //!< MIP_LINEAR_FILTER_QUALITY 1486 uint32_t RAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(13, 13) ; //!< R Address Min Filter Rounding Enable 1487 uint32_t RAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(14, 14) ; //!< R Address Mag Filter Rounding Enable 1488 uint32_t VAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(15, 15) ; //!< V Address Min Filter Rounding Enable 1489 uint32_t VAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(16, 16) ; //!< V Address Mag Filter Rounding Enable 1490 uint32_t UAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< U Address Min Filter Rounding Enable 1491 uint32_t UAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< U Address Mag Filter Rounding Enable 1492 uint32_t MaximumAnisotropy : __CODEGEN_BITFIELD(19, 21) ; //!< MAXIMUM_ANISOTROPY 1493 uint32_t ReductionType : __CODEGEN_BITFIELD(22, 23) ; //!< REDUCTION_TYPE 1494 uint32_t AllowLowQualityLodCalculation : __CODEGEN_BITFIELD(24, 24) ; //!< Allow low quality LOD calculation 1495 uint32_t Reserved121 : __CODEGEN_BITFIELD(25, 25) ; //!< Reserved 1496 uint32_t LowQualityFilter : __CODEGEN_BITFIELD(26, 26) ; //!< LOW_QUALITY_FILTER 1497 uint32_t Reserved123 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1498 }; 1499 uint32_t Value; 1500 } DW3; 1501 1502 //! \name Local enumerations 1503 1504 //! \brief LOD_ALGORITHM 1505 //! \details 1506 //! <!--StartFragment-->Controls which algorithm is used for LOD 1507 //! calculation. Generally, the EWA approximation algorithm results in 1508 //! higher image quality than the legacy algorithm. <!--EndFragment--> 1509 enum LOD_ALGORITHM 1510 { 1511 LOD_ALGORITHM_LEGACY = 0, //!< Use the legacy algorithm for anisotropic filtering 1512 LOD_ALGORITHM_EWAAPPROXIMATION = 1, //!< Use the new EWA approximation algorithm for anisotropic filtering 1513 }; 1514 1515 //! \brief MIN_MODE_FILTER 1516 //! \details 1517 //! This field determines how texels are sampled/filtered when a texture is 1518 //! being "minified" (shrunk). For volume maps, this filter mode selection 1519 //! also applies to the 3rd (inter-layer) dimension.See Mag Mode Filter 1520 enum MIN_MODE_FILTER 1521 { 1522 MIN_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1523 MIN_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1524 MIN_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1525 }; 1526 1527 //! \brief MAG_MODE_FILTER 1528 //! \details 1529 //! This field determines how texels are sampled/filtered when a texture is 1530 //! being "magnified" (enlarged). For volume maps, this filter mode 1531 //! selection also applies to the 3rd (inter-layer) dimension. 1532 enum MAG_MODE_FILTER 1533 { 1534 MAG_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1535 MAG_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1536 MAG_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1537 }; 1538 1539 //! \brief MIP_MODE_FILTER 1540 //! \details 1541 //! This field determines if and how mip map levels are chosen and/or 1542 //! combined when texture filtering. 1543 enum MIP_MODE_FILTER 1544 { 1545 MIP_MODE_FILTER_NONE = 0, //!< Disable mip mapping - force use of the mipmap level corresponding to Min LOD. 1546 MIP_MODE_FILTER_NEAREST = 1, //!< Nearest, Select the nearest mip map 1547 MIP_MODE_FILTER_LINEAR = 3, //!< Linearly interpolate between nearest mip maps (combined with linear min/mag filters this is analogous to "Trilinear" filtering). 1548 }; 1549 1550 //! \brief LOW_QUALITY_CUBE_CORNER_MODE_ENABLE 1551 //! \details 1552 //! This bit, when set to 1, forces sampler to use low-quality filtering 1553 //! for Cube Corners with texel replication which is not compatible with 1554 //! DirectX When cleared to 0 (default), the sampler will 1555 //! use a high-quality filtering for Cube Corners with 3-way texel 1556 //! averaging. 1557 enum LOW_QUALITY_CUBE_CORNER_MODE_ENABLE 1558 { 1559 LOW_QUALITY_CUBE_CORNER_MODE_ENABLE_DISABLE = 0, //!< Disables low-quality Cube Corner mode 1560 LOW_QUALITY_CUBE_CORNER_MODE_ENABLE_ENABLE = 1, //!< Enables low-quality Cube Corner mode 1561 }; 1562 1563 //! \brief LOD_PRECLAMP_MODE 1564 //! \details 1565 //! This field determines whether the computed LOD is clamped to 1566 //! [max,min] mip levelbefore the mag-vs-min determination is performed. 1567 enum LOD_PRECLAMP_MODE 1568 { 1569 LOD_PRECLAMP_MODE_NONE = 0, //!< LOD PreClamp disabled 1570 LOD_PRECLAMP_MODE_OGL = 2, //!< LOD PreClamp enabled (OGL mode) 1571 }; 1572 1573 //! \brief CUBE_SURFACE_CONTROL_MODE 1574 //! \details 1575 //! When sampling from a SURFTYPE_CUBE surface, this field controls whether 1576 //! the TC* Address Control Mode fields are interpreted as programmed or 1577 //! overridden to TEXCOORDMODE_CUBE. 1578 enum CUBE_SURFACE_CONTROL_MODE 1579 { 1580 CUBE_SURFACE_CONTROL_MODE_PROGRAMMED = 0, //!< No additional details 1581 CUBE_SURFACE_CONTROL_MODE_OVERRIDE = 1, //!< No additional details 1582 }; 1583 1584 //! \brief SHADOW_FUNCTION 1585 //! \details 1586 //! This field is used for shadow mapping support via the sample_c message 1587 //! type, and specifies the specific comparison operation to be used. The 1588 //! comparison is between the texture sample red channel (except for 1589 //! alpha-only formats which use the alpha channel), and the "ref" value 1590 //! provided in the input message. 1591 enum SHADOW_FUNCTION 1592 { 1593 SHADOW_FUNCTION_PREFILTEROPALWAYS = 0, //!< No additional details 1594 SHADOW_FUNCTION_PREFILTEROPNEVER = 1, //!< No additional details 1595 SHADOW_FUNCTION_PREFILTEROPLESS = 2, //!< No additional details 1596 SHADOW_FUNCTION_PREFILTEROPEQUAL = 3, //!< No additional details 1597 SHADOW_FUNCTION_PREFILTEROPLEQUAL = 4, //!< No additional details 1598 SHADOW_FUNCTION_PREFILTEROPGREATER = 5, //!< No additional details 1599 SHADOW_FUNCTION_PREFILTEROPNOTEQUAL = 6, //!< No additional details 1600 SHADOW_FUNCTION_PREFILTEROPGEQUAL = 7, //!< No additional details 1601 }; 1602 1603 //! \brief CHROMAKEY_MODE 1604 //! \details 1605 //! This field specifies the behavior of the device in the event of a 1606 //! ChromaKey match. This field is ignored if ChromaKey is disabled. 1607 enum CHROMAKEY_MODE 1608 { 1609 CHROMAKEY_MODE_KEYFILTERKILLONANYMATCH = 0, //!< In this mode, if any contributing texel matches the chroma key, the corresponding pixel mask bit for that pixel is cleared. The result of this operation is observable only if the Killed Pixel Mask Return flag is set on the input message. 1610 CHROMAKEY_MODE_KEYFILTERREPLACEBLACK = 1, //!< In this mode, each texel that matches the chroma key is replaced with (0,0,0,0) (black with alpha=0) prior to filtering. For YCrCb surface formats, the black value is A=0, R(Cr)=0x80, G(Y)=0x10, B(Cb)=0x80. This will tend to darken/fade edges of keyed regions. Note that the pixel pipeline must be programmed to use the resulting filtered texel value to gain the intended effect, e.g., handle the case of a totally keyed-out region (filtered texel alpha==0) through use of alpha test, etc. 1611 }; 1612 1613 //! \brief LOD_CLAMP_MAGNIFICATION_MODE 1614 //! \details 1615 //! This field allows the flexibility to control how LOD clamping is handled 1616 //! when in magnification mode. 1617 enum LOD_CLAMP_MAGNIFICATION_MODE 1618 { 1619 LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE = 0, //!< When in magnification mode, Sampler will clamp LOD as if the Mip Mode Filteris MIPFILTER_NONE. This is how OpenGL defines magnification, and therefore it isexpected that those drivers would not set this bit. 1620 LOD_CLAMP_MAGNIFICATION_MODE_MIPFILTER = 1, //!< When in magnification mode, Sampler will clamp LOD based on the value of Mip Mode Filter. 1621 }; 1622 1623 //! \brief SRGB_DECODE 1624 //! \details 1625 //! This bit controls whether the 3D sampler will decode an sRGB 1626 //! formatted surface into RGB prior to any filtering operation. 1627 //! When set, it does not convert to linear RGB (via a reverse gamma 1628 //! conversion). This bit is ignored for ASTC formats, which are always 1629 //! converted to linear RGB prior to filtering. 1630 enum SRGB_DECODE 1631 { 1632 SRGB_DECODE_DECODEEXT = 0, //!< When set to 0h, the 3D sampler will convert texels from an sRGB surface to linear RGB prior to filtering and/or returning the value. 1633 SRGB_DECODE_SKIPDECODEEXT = 1, //!< When set to 1h, the 3D sampler will not convert texels to linear RGB before filtering and returning results. 1634 }; 1635 1636 //! \brief RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1637 //! \details 1638 //! This bit, when set, causes samples to return filter_weight of all 1639 //! non-NULL texels in the Alpha channel; Red, Green, and Blue channels are 1640 //! contain the filter result with NULL texels excluded; A non-NULL texel is 1641 //! a texel which does not reference a Null Tile. For cases 1642 //! where Tiled_Resource_Mode is TR_NONE, the result will always be 1.0 1643 //! since no texels would be NULL. For cases where the 1644 //! surface format contains an Alpha channel, the result returned will be 1645 //! overridden to return the filter weight. For cases where 1646 //! the surface format does not contain Alpha, the result will still be 1647 //! returned in the Alpha Channel. 1648 enum RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1649 { 1650 RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_DISABLE = 0, //!< When programmed to 0h, filter weight will not be returned, and normal data will be returned on the Alpha channel. 1651 RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_ENABLE = 1, //!< When programmed to 1h, filter weight will be returned on the Alpha channel rather than the normal data expected on the Alpha channel. 1652 }; 1653 1654 //! \brief RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1655 //! \details 1656 //! This bit, when set, returns the filter_weight in the Alpha channel of 1657 //! all non-border texels. Red, Green, and Blue channels will contain the 1658 //! sample resultwith border texels excluded. For cases 1659 //! where the surface format contains an Alpha channel, the result returned 1660 //! will be ovewritten to return the filter weight. For 1661 //! cases where the surface format does not contain Alpha, the result will 1662 //! still be returned in the Alpha Channel. 1663 enum RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1664 { 1665 RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_DISABLE = 0, //!< When programmed to 0h, normal data will be returned on RGBA channels, including contribution from border color texels. 1666 RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_ENABLE = 1, //!< When programmed to 1h, RGB channels return filter data contributed from non-border color texels, and A channel returns filter weight of contributing texels. 1667 }; 1668 1669 //! \brief TCZ_ADDRESS_CONTROL_MODE 1670 //! \details 1671 //! Controls how the 3rd (TCZ) component of input texture coordinates are 1672 //! mapped to texture map addresses - specifically, how coordinates 1673 //! "outside" the texture are handled (wrap/clamp/mirror).See Address TCX 1674 //! Control Mode above for details 1675 enum TCZ_ADDRESS_CONTROL_MODE 1676 { 1677 TCZ_ADDRESS_CONTROL_MODE_WRAP = 0, //!< Map is repeated in the U direction 1678 TCZ_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< Map is mirrored in the U direction 1679 TCZ_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< Map is clamped to the edges of the accessed map 1680 TCZ_ADDRESS_CONTROL_MODE_CUBE = 3, //!< For cube-mapping, filtering in edges access adjacent map faces 1681 TCZ_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< Map is infinitely extended with the border color 1682 TCZ_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< Map is mirrored once about origin, then clamped 1683 TCZ_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< Map is infinitely extended with the average of the nearest edge texel and the border color 1684 TCZ_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< Map is mirrored one time in each direction, but the first pixel of the reflected image is skipped, and the reflected image is effectively 1 pixel less in that direction.May only be used on 2D surfaces./> 1685 }; 1686 1687 //! \brief TCY_ADDRESS_CONTROL_MODE 1688 //! \details 1689 //! Controls how the 2nd (TCY, aka V) component of input texture coordinates 1690 //! are mapped to texture map addresses - specifically, how coordinates 1691 //! "outside" the texture are handled (wrap/clamp/mirror). See Address TCX 1692 //! Control Mode above for details 1693 enum TCY_ADDRESS_CONTROL_MODE 1694 { 1695 TCY_ADDRESS_CONTROL_MODE_WRAP = 0, //!< Map is repeated in the U direction 1696 TCY_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< Map is mirrored in the U direction 1697 TCY_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< Map is clamped to the edges of the accessed map 1698 TCY_ADDRESS_CONTROL_MODE_CUBE = 3, //!< For cube-mapping, filtering in edges access adjacent map faces 1699 TCY_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< Map is infinitely extended with the border color 1700 TCY_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< Map is mirrored once about origin, then clamped 1701 TCY_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< Map is infinitely extended with the average of the nearest edge texel and the border color 1702 TCY_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< Map is mirrored one time in each direction, but the first pixel of the reflected image is skipped, and the reflected image is effectively 1 pixel less in that direction.May only be used on 2D surfaces./> 1703 }; 1704 1705 //! \brief TCX_ADDRESS_CONTROL_MODE 1706 //! \details 1707 //! Controls how the 1st (TCX, aka U) component of input texture coordinates 1708 //! are mapped to texture map addresses - specifically, how coordinates 1709 //! "outside" the texture are handled (wrap/clamp/mirror). The setting of 1710 //! this field is subject to being overridden by the Cube Surface Control 1711 //! Mode field when sampling from a SURFTYPE_CUBE surface. 1712 enum TCX_ADDRESS_CONTROL_MODE 1713 { 1714 TCX_ADDRESS_CONTROL_MODE_WRAP = 0, //!< Map is repeated in the U direction 1715 TCX_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< Map is mirrored in the U direction 1716 TCX_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< Map is clamped to the edges of the accessed map 1717 TCX_ADDRESS_CONTROL_MODE_CUBE = 3, //!< For cube-mapping, filtering in edges access adjacent map faces 1718 TCX_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< Map is infinitely extended with the border color 1719 TCX_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< Map is mirrored once about origin, then clamped 1720 TCX_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< Map is infinitely extended with the average of the nearest edge texel and the border color 1721 TCX_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< Map is mirrored one time in each direction, but the first pixel of the reflected image is skipped, and the reflected image is effectively 1 pixel less in that direction.May only be used on 2D surfaces./> 1722 }; 1723 1724 //! \brief MIP_LINEAR_FILTER_QUALITY 1725 //! \details 1726 //! This 2-bit field controls the rounding of LOD for MIP Linear 1727 //! Filtering modes (e.g. Trilinear, etc). 1728 enum MIP_LINEAR_FILTER_QUALITY 1729 { 1730 MIP_LINEAR_FILTER_QUALITY_FULLQUALITY = 0, //!< No rounding of LOD is done, the full 8-bit quality is used for filtering. 1731 MIP_LINEAR_FILTER_QUALITY_HIGHQUALITY = 1, //!< LOD values which are within 12.5% of an integer LOD value are rounded to that value prior to filtering and filtering effectively becomes the same as MIP Nearest. 1732 MIP_LINEAR_FILTER_QUALITY_MEDIUMQUALITY = 2, //!< LOD values which are within 16.67% of an integer LOD value are rounded to that value prior to filtering and filtering effectively becomes the same as MIP Nearest. 1733 MIP_LINEAR_FILTER_QUALITY_LOWQUALITY = 3, //!< LOD values which are within 25% of an integer LOD value are rounded to that value prior to filtering and filtering effectively becomes the same as MIP Nearest 1734 }; 1735 1736 //! \brief MAXIMUM_ANISOTROPY 1737 //! \details 1738 //! This field clamps the maximum value of the anisotropy ratio used by the 1739 //! MAPFILTER_ANISOTROPIC filter (Min or Mag Mode Filter). 1740 enum MAXIMUM_ANISOTROPY 1741 { 1742 MAXIMUM_ANISOTROPY_RATIO21 = 0, //!< At most a 2:1 aspect ratio filter is used 1743 MAXIMUM_ANISOTROPY_RATIO41 = 1, //!< At most a 4:1 aspect ratio filter is used 1744 MAXIMUM_ANISOTROPY_RATIO61 = 2, //!< At most a 6:1 aspect ratio filter is used 1745 MAXIMUM_ANISOTROPY_RATIO81 = 3, //!< At most a 8:1 aspect ratio filter is used 1746 MAXIMUM_ANISOTROPY_RATIO101 = 4, //!< At most a 10:1 aspect ratio filter is used 1747 MAXIMUM_ANISOTROPY_RATIO121 = 5, //!< At most a 12:1 aspect ratio filter is used 1748 MAXIMUM_ANISOTROPY_RATIO141 = 6, //!< At most a 14:1 aspect ratio filter is used 1749 MAXIMUM_ANISOTROPY_RATIO161 = 7, //!< At most a 16:1 aspect ratio filter is used 1750 }; 1751 1752 //! \brief REDUCTION_TYPE 1753 //! \details 1754 //! This field defines the type of reduction that will be performed on the 1755 //! texels in the footprint defined by the Min/Mag/Mip Filter Mode 1756 //! fields. This field is ignored if Reduction Type Enable is 1757 //! disabled. 1758 enum REDUCTION_TYPE 1759 { 1760 REDUCTION_TYPE_STDFILTER = 0, //!< standard filter 1761 REDUCTION_TYPE_COMPARISON = 1, //!< comparison followed by standard filter 1762 REDUCTION_TYPE_MINIMUM = 2, //!< minimum of footprint 1763 REDUCTION_TYPE_MAXIMUM = 3, //!< maximum of footprint 1764 }; 1765 1766 //! \brief LOW_QUALITY_FILTER 1767 //! \details 1768 //! style="box-sizing: border-box; color: rgb(35, 35, 35); font-family: 1769 //! Arial,sans-serif; font-size: 13.33px; font-style: normal; font-variant: 1770 //! normal; font-weight: 400; letter-spacing: normal; margin-bottom: 11px; 1771 //! margin-left: 0px; margin-right: 0px; margin-top: 0px; orphans: 2; 1772 //! text-align: left; text-decoration: none; text-indent: 0px; 1773 //! text-transform: none; -webkit-text-stroke-width: 0px; white-space: 1774 //! normal; word-spacing: 0px;">Setting this bit will enable low quality 1775 //! filter to save power. 1776 //! style="box-sizing: border-box; color: rgb(35, 35, 35); font-family: 1777 //! Arial,sans-serif; font-size: 13.33px; font-style: normal; font-variant: 1778 //! normal; font-weight: 400; letter-spacing: normal; margin-bottom: 11px; 1779 //! margin-left: 0px; margin-right: 0px; margin-top: 0px; orphans: 2; 1780 //! text-align: left; text-decoration: none; text-indent: 0px; 1781 //! text-transform: none; -webkit-text-stroke-width: 0px; white-space: 1782 //! normal; word-spacing: 0px;">* Will result in lower precision 1783 //! style="box-sizing: border-box; color: rgb(35, 35, 35); font-family: 1784 //! Arial,sans-serif; font-size: 13.33px; font-style: normal; font-variant: 1785 //! normal; font-weight: 400; letter-spacing: normal; margin-bottom: 11px; 1786 //! margin-left: 0px; margin-right: 0px; margin-top: 0px; orphans: 2; 1787 //! text-align: left; text-decoration: none; text-indent: 0px; 1788 //! text-transform: none; -webkit-text-stroke-width: 0px; white-space: 1789 //! normal; word-spacing: 0px;">* Only has an affect if the surface format 1790 //! is one of the currently supported formats. The list currently allows 1791 //! unorm8, unorm16 and float16 type formats. 1792 //! style="box-sizing: border-box; color: rgb(35, 35, 35); font-family: 1793 //! Arial,sans-serif; font-size: 13.33px; font-style: normal; font-variant: 1794 //! normal; font-weight: 400; letter-spacing: normal; margin-bottom: 11px; 1795 //! margin-left: 0px; margin-right: 0px; margin-top: 0px; orphans: 2; 1796 //! text-align: left; text-decoration: none; text-indent: 0px; 1797 //! text-transform: none; -webkit-text-stroke-width: 0px; white-space: 1798 //! normal; word-spacing: 0px;">* Has no affect if in anisotropic mode. 1799 enum LOW_QUALITY_FILTER 1800 { 1801 LOW_QUALITY_FILTER_DISABLE = 0, //!< When set to 0h, filter quality is high and there is no degradation in precision. Power will be higher for some surface formats. 1802 LOW_QUALITY_FILTER_ENABLE = 1, //!< When set to 1h, filter quality is lower and precision is reduced. Power will be lower for these surface formats. 1803 }; 1804 1805 //! \name Initializations 1806 1807 //! \brief Explicit member initialization function 1808 SAMPLER_STATE_CMD(); 1809 1810 static const size_t dwSize = 4; 1811 static const size_t byteSize = 16; 1812 }; 1813 1814 //! 1815 //! \brief SAMPLER_STATE_8x8_AVS_COEFFICIENTS 1816 //! \details 1817 //! ExistsIf = AVS && (Function_mode = 0) 1818 //! 1819 struct SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD 1820 { 1821 union 1822 { 1823 struct 1824 { 1825 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,0] 1826 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,0] 1827 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,1] 1828 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,1] 1829 }; 1830 uint32_t Value; 1831 } DW0; 1832 union 1833 { 1834 struct 1835 { 1836 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,2] 1837 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,2] 1838 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,3] 1839 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,3] 1840 }; 1841 uint32_t Value; 1842 } DW1; 1843 union 1844 { 1845 struct 1846 { 1847 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,4] 1848 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,4] 1849 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,5] 1850 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,5] 1851 }; 1852 uint32_t Value; 1853 } DW2; 1854 union 1855 { 1856 struct 1857 { 1858 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,6] 1859 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,6] 1860 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,7] 1861 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,7] 1862 }; 1863 uint32_t Value; 1864 } DW3; 1865 union 1866 { 1867 struct 1868 { 1869 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1870 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[n,2] 1871 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1X Filter Coefficient[n,3] 1872 }; 1873 uint32_t Value; 1874 } DW4; 1875 union 1876 { 1877 struct 1878 { 1879 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[n,4] 1880 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1X Filter Coefficient[n,5] 1881 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1882 }; 1883 uint32_t Value; 1884 } DW5; 1885 union 1886 { 1887 struct 1888 { 1889 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1890 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1Y Filter Coefficient[n,2] 1891 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[n,3] 1892 }; 1893 uint32_t Value; 1894 } DW6; 1895 union 1896 { 1897 struct 1898 { 1899 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1Y Filter Coefficient[n,4] 1900 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[n,5] 1901 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1902 }; 1903 uint32_t Value; 1904 } DW7; 1905 1906 //! \name Local enumerations 1907 1908 //! \name Initializations 1909 1910 //! \brief Explicit member initialization function 1911 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD(); 1912 1913 static const size_t dwSize = 8; 1914 static const size_t byteSize = 32; 1915 }; 1916 1917 //! 1918 //! \brief SAMPLER_STATE_8x8_AVS 1919 //! \details 1920 //! ExistsIf = AVS 1921 //! 1922 struct SAMPLER_STATE_8x8_AVS_CMD 1923 { 1924 uint32_t Reserved0[3]; //!< Reserved 1925 union 1926 { 1927 struct 1928 { 1929 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 27) ; //!< Reserved 1930 uint32_t Enable8TapFilter : __CODEGEN_BITFIELD(28, 29) ; //!< ENABLE_8_TAP_FILTER 1931 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1932 }; 1933 uint32_t Value; 1934 } DW3; 1935 union 1936 { 1937 struct 1938 { 1939 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 10) ; //!< Reserved 1940 uint32_t ShuffleOutputwritebackForSample8X8 : __CODEGEN_BITFIELD(11, 11) ; //!< SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 1941 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 1942 }; 1943 uint32_t Value; 1944 } DW4; 1945 uint32_t Reserved160[11]; //!< Reserved 1946 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient016[17]; //!< DW16..151, Filter Coefficient[0..16] 1947 union 1948 { 1949 struct 1950 { 1951 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 1952 uint32_t Reserved4867 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 1953 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 1954 uint32_t Reserved4871 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 1955 uint32_t MaxDerivative8Pixels : __CODEGEN_BITFIELD( 8, 15) ; //!< Max Derivative 8 Pixels 1956 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 1957 uint32_t DefaultSharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< DEFAULT_SHARPNESS_LEVEL 1958 }; 1959 uint32_t Value; 1960 } DW152; 1961 union 1962 { 1963 struct 1964 { 1965 uint32_t RgbAdaptive : __CODEGEN_BITFIELD( 0, 0) ; //!< RGB_ADAPTIVE 1966 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1967 uint32_t Reserved4898 : __CODEGEN_BITFIELD( 2, 20) ; //!< Reserved 1968 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD(21, 21) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 1969 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD(22, 22) ; //!< BYPASS_X_ADAPTIVE_FILTERING 1970 uint32_t Reserved4919 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 1971 }; 1972 uint32_t Value; 1973 } DW153; 1974 uint32_t Reserved4928[6]; //!< Reserved 1975 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient1731[15]; //!< DW160..279, Filter Coefficient[17..31] 1976 1977 //! \name Local enumerations 1978 1979 //! \brief ENABLE_8_TAP_FILTER 1980 //! \details 1981 //! 1982 //! Adaptive Filtering (Mode = 11) ExistsIf: 1983 //! 1984 //! /> R10G10B10A2_UNORM R8G8B8A8_UNORM (AYUV also) 1985 //! R8B8G8A8_UNORM B8G8R8A8_UNORM R16G16B16A16 1986 enum ENABLE_8_TAP_FILTER 1987 { 1988 ENABLE_8_TAP_FILTER_UNNAMED0 = 0, //!< 4-tap filter is only done on all channels. 1989 ENABLE_8_TAP_FILTER_UNNAMED1 = 1, //!< Enable 8-tap Adaptive filter on G-channel. 4-tap filter on other channels. 1990 ENABLE_8_TAP_FILTER_UNNAMED2 = 2, //!< 8-tap filter is done on all channels (UV-ch uses the Y-coefficients) 1991 ENABLE_8_TAP_FILTER_UNNAMED3 = 3, //!< Enable 8-tap Adaptive filter all channels (UV-ch uses the Y-coefficients). 1992 }; 1993 1994 enum SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 1995 { 1996 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED0 = 0, //!< Writeback same as Original Sample_8x8 1997 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED1 = 1, //!< Writeback of Sample_8x8 Is Modified to Suite Sample_Unorm 1998 }; 1999 2000 //! \brief DEFAULT_SHARPNESS_LEVEL 2001 //! \details 2002 //! When adaptive scaling is off, determines the balance between sharp and 2003 //! smooth scalers. 2004 enum DEFAULT_SHARPNESS_LEVEL 2005 { 2006 DEFAULT_SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 2007 DEFAULT_SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 2008 }; 2009 2010 //! \brief RGB_ADAPTIVE 2011 //! \details 2012 //! This should be always set to 0 for YUV input and can be enabled/disabled 2013 //! for RGB input.This should be enabled only if we enable 8-tap adaptive 2014 //! filter for RGB input. 2015 enum RGB_ADAPTIVE 2016 { 2017 RGB_ADAPTIVE_DISBLE = 0, //!< Disable the RGB Adaptive equation and use G-Ch directly for adaptive filter 2018 RGB_ADAPTIVE_ENABLE = 1, //!< Enable the RGB Adaptive filter using the equation (Y=(R+2G+B)>>2) 2019 }; 2020 2021 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2022 //! \details 2023 //! Only to be enabled if 8-tap Adaptive filter mode is on, eElse it should 2024 //! be disabled. 2025 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2026 { 2027 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISBLE = 0, //!< Disable Adaptive Filter on UV/RB Channels 2028 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLE = 1, //!< Enable Adaptive Filter on UV/RB Channels 2029 }; 2030 2031 //! \brief BYPASS_Y_ADAPTIVE_FILTERING 2032 //! \details 2033 //! When disabled, the Y direction will use Default Sharpness Level 2034 //! to blend between the smooth and sharp filters rather than the calculated 2035 //! value. 2036 enum BYPASS_Y_ADAPTIVE_FILTERING 2037 { 2038 BYPASS_Y_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable Y Adaptive Filtering 2039 BYPASS_Y_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable Y Adaptive Filtering 2040 }; 2041 2042 //! \brief BYPASS_X_ADAPTIVE_FILTERING 2043 //! \details 2044 //! When disabled, the X direction will use Default Sharpness Level 2045 //! to blend between the smooth and sharp filters rather than the calculated 2046 //! value. 2047 enum BYPASS_X_ADAPTIVE_FILTERING 2048 { 2049 BYPASS_X_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable X Adaptive Filtering 2050 BYPASS_X_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable X Adaptive Filtering 2051 }; 2052 2053 //! \name Initializations 2054 2055 //! \brief Explicit member initialization function 2056 SAMPLER_STATE_8x8_AVS_CMD(); 2057 2058 static const size_t dwSize = 280; 2059 static const size_t byteSize = 1120; 2060 }; 2061 2062 //! 2063 //! \brief SAMPLER_INDIRECT_STATE 2064 //! \details 2065 //! The format of the border color is R32G32B32A32_FLOAT, R32G32B32A32_SINT, 2066 //! or R32G32B32A32_UINT, depending on the surface format chosen. For 2067 //! surface formats with one or more channels missing, the value from the 2068 //! border color is not used for the missing channels, resulting in these 2069 //! channels resulting in the overall default value (0 for colors and 1 for 2070 //! alpha) regardless of whether border color is chosen. The surface formats 2071 //! with "L" and "I" have special behavior with respect to the border color. 2072 //! The border color value used for the replicated channels (RGB for "L" 2073 //! formats and RGBA for "I" formats) comes from theredchannel of border 2074 //! color. In these cases, the green and blue channels, and also alpha for 2075 //! "I", of the border color are ignored. 2076 //! 2077 //! The conditions under which this color is used depend on theSurface Type- 2078 //! 1D/2D/3D surfaces use the border color when the coordinates extend 2079 //! beyond the surface extent; cube surfaces use the border color for 2080 //! "empty" (disabled) faces. 2081 //! The border color itself is accessed through the texture cache hierarchy 2082 //! rather than the state cache hierarchy. Thus, if the border color is 2083 //! changed in memory, the texture cache must be invalidated and the state 2084 //! cache does not need to be invalidated. 2085 //! 2086 struct SAMPLER_INDIRECT_STATE_CMD 2087 { 2088 union 2089 { 2090 struct 2091 { 2092 uint32_t BorderColorRed ; //!< Border Color Red 2093 }; 2094 uint32_t Value; 2095 } DW0; 2096 union 2097 { 2098 struct 2099 { 2100 uint32_t BorderColorGreen ; //!< Border Color Green 2101 }; 2102 uint32_t Value; 2103 } DW1; 2104 union 2105 { 2106 struct 2107 { 2108 uint32_t BorderColorBlue ; //!< Border Color Blue 2109 }; 2110 uint32_t Value; 2111 } DW2; 2112 union 2113 { 2114 struct 2115 { 2116 uint32_t BorderColorAlpha ; //!< Border Color Alpha 2117 }; 2118 uint32_t Value; 2119 } DW3; 2120 uint32_t Reserved128[12]; //!< Reserved 2121 2122 //! \name Local enumerations 2123 2124 //! \name Initializations 2125 2126 //! \brief Explicit member initialization function 2127 SAMPLER_INDIRECT_STATE_CMD(); 2128 2129 static const size_t dwSize = 16; 2130 static const size_t byteSize = 64; 2131 }; 2132 MEDIA_CLASS_DEFINE_END(mhw_state_heap_xe2_hpg) 2133 }; 2134 2135 #pragma pack() 2136 2137 #endif // __MHW_STATE_HEAP_HWCMD_XE2_HPG_H__ 2138