1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_state_heap_hwcmd_g9_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g9_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_STATE_HEAP_HWCMD_G9_X_H__ 29 #define __MHW_STATE_HEAP_HWCMD_G9_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_state_heap_g9_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief INTERFACE_DESCRIPTOR_DATA 50 //! \details 51 //! 52 //! 53 struct INTERFACE_DESCRIPTOR_DATA_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 61 uint32_t KernelStartPointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Kernel Start Pointer 62 }; 63 uint32_t Value; 64 } DW0; 65 union 66 { 67 //!< DWORD 1 68 struct 69 { 70 uint32_t KernelStartPointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Kernel Start Pointer High 71 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 72 }; 73 uint32_t Value; 74 } DW1; 75 union 76 { 77 //!< DWORD 2 78 struct 79 { 80 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 81 uint32_t SoftwareExceptionEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Software Exception Enable 82 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 10) ; //!< Reserved 83 uint32_t MaskStackExceptionEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Mask Stack Exception Enable 84 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 12) ; //!< Reserved 85 uint32_t IllegalOpcodeExceptionEnable : __CODEGEN_BITFIELD(13, 13) ; //!< Illegal Opcode Exception Enable 86 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 87 uint32_t FloatingPointMode : __CODEGEN_BITFIELD(16, 16) ; //!< FLOATING_POINT_MODE 88 uint32_t ThreadPriority : __CODEGEN_BITFIELD(17, 17) ; //!< THREAD_PRIORITY 89 uint32_t SingleProgramFlow : __CODEGEN_BITFIELD(18, 18) ; //!< SINGLE_PROGRAM_FLOW 90 uint32_t DenormMode : __CODEGEN_BITFIELD(19, 19) ; //!< DENORM_MODE 91 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 92 }; 93 uint32_t Value; 94 } DW2; 95 union 96 { 97 //!< DWORD 3 98 struct 99 { 100 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 101 uint32_t SamplerCount : __CODEGEN_BITFIELD( 2, 4) ; //!< SAMPLER_COUNT 102 uint32_t SamplerStatePointer : __CODEGEN_BITFIELD( 5, 31) ; //!< Sampler State Pointer 103 }; 104 uint32_t Value; 105 } DW3; 106 union 107 { 108 //!< DWORD 4 109 struct 110 { 111 uint32_t BindingTableEntryCount : __CODEGEN_BITFIELD( 0, 4) ; //!< Binding Table Entry Count 112 uint32_t BindingTablePointer : __CODEGEN_BITFIELD( 5, 15) ; //!< Binding Table Pointer 113 uint32_t Reserved144 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 114 }; 115 uint32_t Value; 116 } DW4; 117 union 118 { 119 //!< DWORD 5 120 struct 121 { 122 uint32_t ConstantUrbEntryReadOffset : __CODEGEN_BITFIELD( 0, 15) ; //!< Constant URB Entry Read Offset 123 uint32_t ConstantIndirectUrbEntryReadLength : __CODEGEN_BITFIELD(16, 31) ; //!< Constant/Indirect URB Entry Read Length 124 }; 125 uint32_t Value; 126 } DW5; 127 union 128 { 129 //!< DWORD 6 130 struct 131 { 132 uint32_t NumberOfThreadsInGpgpuThreadGroup : __CODEGEN_BITFIELD( 0, 9) ; //!< Number of Threads in GPGPU Thread Group 133 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 14) ; //!< Reserved 134 uint32_t GlobalBarrierEnable : __CODEGEN_BITFIELD(15, 15) ; //!< Global Barrier Enable 135 uint32_t SharedLocalMemorySize : __CODEGEN_BITFIELD(16, 20) ; //!< SHARED_LOCAL_MEMORY_SIZE 136 uint32_t BarrierEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Barrier Enable 137 uint32_t RoundingMode : __CODEGEN_BITFIELD(22, 23) ; //!< ROUNDING_MODE 138 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 139 }; 140 uint32_t Value; 141 } DW6; 142 union 143 { 144 //!< DWORD 7 145 struct 146 { 147 uint32_t CrossThreadConstantDataReadLength : __CODEGEN_BITFIELD( 0, 7) ; //!< Cross-Thread Constant Data Read Length 148 uint32_t Reserved232 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 149 }; 150 uint32_t Value; 151 } DW7; 152 153 //! \name Local enumerations 154 155 //! \brief FLOATING_POINT_MODE 156 //! \details 157 //! Specifies the floating point mode used by the dispatched thread. 158 enum FLOATING_POINT_MODE 159 { 160 FLOATING_POINT_MODE_IEEE_754 = 0, //!< No additional details 161 FLOATING_POINT_MODE_ALTERNATE = 1, //!< No additional details 162 }; 163 164 //! \brief THREAD_PRIORITY 165 //! \details 166 //! Specifies the priority of the thread for dispatch. 167 enum THREAD_PRIORITY 168 { 169 THREAD_PRIORITY_NORMALPRIORITY = 0, //!< No additional details 170 THREAD_PRIORITY_HIGHPRIORITY = 1, //!< No additional details 171 }; 172 173 //! \brief SINGLE_PROGRAM_FLOW 174 //! \details 175 //! Specifies whether the kernel program has a single program flow (SIMDnxm 176 //! with m = 1) or multiple program flows (SIMDnxm with m > 1). 177 enum SINGLE_PROGRAM_FLOW 178 { 179 SINGLE_PROGRAM_FLOW_MULTIPLE = 0, //!< No additional details 180 SINGLE_PROGRAM_FLOW_SINGLE = 1, //!< No additional details 181 }; 182 183 //! \brief DENORM_MODE 184 //! \details 185 //! This field specifies how Float denormalized numbers are handles in the 186 //! dispatched thread. 187 enum DENORM_MODE 188 { 189 DENORM_MODE_FTZ = 0, //!< Float denorms will be flushed to zero when appearing as inputs; denorms will never come out of instructions. Double precision float and half precision float numbers are not flushed to zero. 190 DENORM_MODE_SETBYKERNEL = 1, //!< Denorms will be handled in by kernel. 191 }; 192 193 //! \brief SAMPLER_COUNT 194 //! \details 195 //! Specifies how many samplers (in multiples of 4) the kernel uses. Used 196 //! only for prefetching the associated sampler state entries. 197 //! <i>This field is ignored for child threads.</i> 198 //! <i>If this field is not zero, sampler state is prefetched for the 199 //! first instance of a root thread upon the startup of the media 200 //! pipeline.</i> 201 enum SAMPLER_COUNT 202 { 203 SAMPLER_COUNT_NOSAMPLERSUSED = 0, //!< No additional details 204 SAMPLER_COUNT_BETWEEN1AND4SAMPLERSUSED = 1, //!< No additional details 205 SAMPLER_COUNT_BETWEEN5AND8SAMPLERSUSED = 2, //!< No additional details 206 SAMPLER_COUNT_BETWEEN9AND12SAMPLERSUSED = 3, //!< No additional details 207 SAMPLER_COUNT_BETWEEN13AND16SAMPLERSUSED = 4, //!< No additional details 208 }; 209 210 //! \brief SHARED_LOCAL_MEMORY_SIZE 211 //! \details 212 //! This field indicates how much SharedLocalMemory the thread group 213 //! requires. The amount is specified in 4k blocks, but only powers of 2 are 214 //! allowed: 0, 4k, 8k, 16k, 32k and 64k per half-slice. 215 enum SHARED_LOCAL_MEMORY_SIZE 216 { 217 SHARED_LOCAL_MEMORY_SIZE_ENCODES0K = 0, //!< No SLM used 218 SHARED_LOCAL_MEMORY_SIZE_ENCODES1K = 1, //!< No additional details 219 SHARED_LOCAL_MEMORY_SIZE_ENCODES2K = 2, //!< No additional details 220 SHARED_LOCAL_MEMORY_SIZE_ENCODES4K = 3, //!< No additional details 221 SHARED_LOCAL_MEMORY_SIZE_ENCODES8K = 4, //!< No additional details 222 SHARED_LOCAL_MEMORY_SIZE_ENCODES16K = 5, //!< No additional details 223 SHARED_LOCAL_MEMORY_SIZE_ENCODES32K = 6, //!< No additional details 224 SHARED_LOCAL_MEMORY_SIZE_ENCODES64K = 7, //!< No additional details 225 }; 226 227 enum ROUNDING_MODE 228 { 229 ROUNDING_MODE_RTNE = 0, //!< Round to Nearest Even 230 ROUNDING_MODE_RU = 1, //!< Round toward +Infinity 231 ROUNDING_MODE_RD = 2, //!< Round toward -Infinity 232 ROUNDING_MODE_RTZ = 3, //!< Round toward Zero 233 }; 234 235 //! \name Initializations 236 237 //! \brief Explicit member initialization function 238 INTERFACE_DESCRIPTOR_DATA_CMD(); 239 240 static const size_t dwSize = 8; 241 static const size_t byteSize = 32; 242 }; 243 244 //! 245 //! \brief BINDING_TABLE_STATE 246 //! \details 247 //! The binding table binds surfaces to logical resource indices used by 248 //! shaders and other compute engine kernels. It is stored as an array of up 249 //! to 256 elements, each of which contains one dword as defined here. The 250 //! start of each element is spaced one dword apart. The first element of 251 //! the binding table is aligned to a 64-byte boundary. Binding table 252 //! indexes beyond 256 will automatically be mapped to entry 0 by the HW, w/ 253 //! the exception of any messages which support the special indexes 240 254 //! through 255, inclusive. 255 //! 256 struct BINDING_TABLE_STATE_CMD 257 { 258 union 259 { 260 //!< DWORD 0 261 struct 262 { 263 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 264 uint32_t SurfaceStatePointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Surface State Pointer 265 }; 266 uint32_t Value; 267 } DW0; 268 269 //! \name Local enumerations 270 271 //! \name Initializations 272 273 //! \brief Explicit member initialization function 274 BINDING_TABLE_STATE_CMD(); 275 276 static const size_t dwSize = 1; 277 static const size_t byteSize = 4; 278 }; 279 280 //! 281 //! \brief RENDER_SURFACE_STATE 282 //! \details 283 //! This is the normal surface state used by all messages that use 284 //! SURFACE_STATE except those that use MEDIA_SURFACE_STATE. 285 //! 286 struct RENDER_SURFACE_STATE_CMD 287 { 288 union 289 { 290 //!< DWORD 0 291 struct 292 { 293 uint32_t CubeFaceEnablePositiveZ : __CODEGEN_BITFIELD( 0, 0) ; //!< Cube Face Enable - Positive Z, [Surface Type] == 'SURFTYPE_CUBE' 294 uint32_t CubeFaceEnableNegativeZ : __CODEGEN_BITFIELD( 1, 1) ; //!< Cube Face Enable - Negative Z, [Surface Type] == 'SURFTYPE_CUBE' 295 uint32_t CubeFaceEnablePositiveY : __CODEGEN_BITFIELD( 2, 2) ; //!< Cube Face Enable - Positive Y, [Surface Type] == 'SURFTYPE_CUBE' 296 uint32_t CubeFaceEnableNegativeY : __CODEGEN_BITFIELD( 3, 3) ; //!< Cube Face Enable - Negative Y, [Surface Type] == 'SURFTYPE_CUBE' 297 uint32_t CubeFaceEnablePositiveX : __CODEGEN_BITFIELD( 4, 4) ; //!< Cube Face Enable - Positive X, [Surface Type] == 'SURFTYPE_CUBE' 298 uint32_t CubeFaceEnableNegativeX : __CODEGEN_BITFIELD( 5, 5) ; //!< Cube Face Enable - Negative X, [Surface Type] == 'SURFTYPE_CUBE' 299 uint32_t MediaBoundaryPixelMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MEDIA_BOUNDARY_PIXEL_MODE 300 uint32_t RenderCacheReadWriteMode : __CODEGEN_BITFIELD( 8, 8) ; //!< RENDER_CACHE_READ_WRITE_MODE 301 uint32_t SamplerL2OutOfOrderModeDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Sampler L2 Out of Order Mode Disable 302 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(10, 10) ; //!< Vertical Line Stride Offset 303 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(11, 11) ; //!< Vertical Line Stride 304 uint32_t TileMode : __CODEGEN_BITFIELD(12, 13) ; //!< TILE_MODE 305 uint32_t SurfaceHorizontalAlignment : __CODEGEN_BITFIELD(14, 15) ; //!< SURFACE_HORIZONTAL_ALIGNMENT 306 uint32_t SurfaceVerticalAlignment : __CODEGEN_BITFIELD(16, 17) ; //!< SURFACE_VERTICAL_ALIGNMENT 307 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(18, 26) ; //!< SURFACE_FORMAT 308 uint32_t AstcEnable : __CODEGEN_BITFIELD(27, 27) ; //!< ASTC_Enable 309 uint32_t SurfaceArray : __CODEGEN_BITFIELD(28, 28) ; //!< Surface Array 310 uint32_t SurfaceType : __CODEGEN_BITFIELD(29, 31) ; //!< SURFACE_TYPE 311 }; 312 uint32_t Value; 313 } DW0; 314 union 315 { 316 //!< DWORD 1 317 struct 318 { 319 uint32_t SurfaceQpitch : __CODEGEN_BITFIELD( 0, 14) ; //!< Surface QPitch 320 uint32_t Reserved47 : __CODEGEN_BITFIELD(15, 18) ; //!< Reserved 321 uint32_t BaseMipLevel : __CODEGEN_BITFIELD(19, 23) ; //!< Base Mip Level 322 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD(24, 30) ; //!< Memory Object Control State 323 uint32_t Reserved63 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 324 }; 325 uint32_t Value; 326 } DW1; 327 union 328 { 329 //!< DWORD 2 330 struct 331 { 332 uint32_t Width : __CODEGEN_BITFIELD( 0, 13) ; //!< Width 333 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 334 uint32_t Height : __CODEGEN_BITFIELD(16, 29) ; //!< Height 335 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 336 }; 337 uint32_t Value; 338 } DW2; 339 union 340 { 341 //!< DWORD 3 342 struct 343 { 344 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 0, 17) ; //!< Surface Pitch 345 uint32_t Reserved114 : __CODEGEN_BITFIELD(18, 20) ; //!< Reserved 346 uint32_t Depth : __CODEGEN_BITFIELD(21, 31) ; //!< Depth 347 }; 348 uint32_t Value; 349 } DW3; 350 union 351 { 352 //!< DWORD 4 353 struct 354 { 355 uint32_t MultisamplePositionPaletteIndex : __CODEGEN_BITFIELD( 0, 2) ; //!< Multisample Position Palette Index, [Surface Type] != 'SURFTYPE_STRBUF' 356 uint32_t NumberOfMultisamples : __CODEGEN_BITFIELD( 3, 5) ; //!< NUMBER_OF_MULTISAMPLES, [Surface Type] != 'SURFTYPE_STRBUF' 357 uint32_t MultisampledSurfaceStorageFormat : __CODEGEN_BITFIELD( 6, 6) ; //!< MULTISAMPLED_SURFACE_STORAGE_FORMAT, [Surface Type] != 'SURFTYPE_STRBUF' 358 uint32_t RenderTargetViewExtent : __CODEGEN_BITFIELD( 7, 17) ; //!< Render Target View Extent, [Surface Type] != 'SURFTYPE_STRBUF' 359 uint32_t MinimumArrayElement : __CODEGEN_BITFIELD(18, 28) ; //!< Minimum Array Element, [Surface Type] != 'SURFTYPE_STRBUF' 360 uint32_t RenderTargetAndSampleUnormRotation : __CODEGEN_BITFIELD(29, 30) ; //!< RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION, [Surface Type] != 'SURFTYPE_STRBUF' 361 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, [Surface Type] != 'SURFTYPE_STRBUF' 362 }; 363 uint32_t Value; 364 } DW4; 365 union 366 { 367 //!< DWORD 5 368 struct 369 { 370 uint32_t MipCountLod : __CODEGEN_BITFIELD( 0, 3) ; //!< MIP Count / LOD 371 uint32_t SurfaceMinLod : __CODEGEN_BITFIELD( 4, 7) ; //!< Surface Min LOD 372 uint32_t MipTailStartLod : __CODEGEN_BITFIELD( 8, 11) ; //!< Mip Tail Start LOD 373 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 13) ; //!< Reserved 374 uint32_t CoherencyType : __CODEGEN_BITFIELD(14, 14) ; //!< COHERENCY_TYPE 375 uint32_t Reserved175 : __CODEGEN_BITFIELD(15, 17) ; //!< Reserved 376 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(18, 19) ; //!< TILED_RESOURCE_MODE 377 uint32_t EwaDisableForCube : __CODEGEN_BITFIELD(20, 20) ; //!< EWA_DISABLE_FOR_CUBE 378 uint32_t YOffset : __CODEGEN_BITFIELD(21, 23) ; //!< Y Offset 379 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 380 uint32_t XOffset : __CODEGEN_BITFIELD(25, 31) ; //!< X Offset 381 }; 382 uint32_t Value; 383 } DW5; 384 union 385 { 386 //!< DWORD 6 387 struct 388 { 389 uint32_t AuxiliarySurfaceMode : __CODEGEN_BITFIELD( 0, 2) ; //!< AUXILIARY_SURFACE_MODE, ([Surface Format] != 'PLANAR') 390 uint32_t AuxiliarySurfacePitch : __CODEGEN_BITFIELD( 3, 11) ; //!< Auxiliary Surface Pitch, ([Surface Format] != 'PLANAR') 391 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved, ([Surface Format] != 'PLANAR') 392 uint32_t AuxiliarySurfaceQpitch : __CODEGEN_BITFIELD(16, 30) ; //!< Auxiliary Surface QPitch, ([Surface Format] != 'PLANAR') 393 uint32_t Reserved223 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, ([Surface Format] != 'PLANAR') 394 } Obj0; 395 struct 396 { 397 uint32_t YOffsetForUOrUvPlane : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 398 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved, ([Surface Format] == 'PLANAR') 399 uint32_t XOffsetForUOrUvPlane : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 400 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved, ([Surface Format] == 'PLANAR') 401 uint32_t SeparateUvPlaneEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Separate UV Plane Enable, ([Surface Format] == 'PLANAR') 402 } Obj1; 403 uint32_t Value; 404 } DW6; 405 union 406 { 407 //!< DWORD 7 408 struct 409 { 410 uint32_t ResourceMinLod : __CODEGEN_BITFIELD( 0, 11) ; //!< Resource Min LOD 411 uint32_t Reserved236 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 412 uint32_t ShaderChannelSelectAlpha : __CODEGEN_BITFIELD(16, 18) ; //!< SHADER_CHANNEL_SELECT_ALPHA 413 uint32_t ShaderChannelSelectBlue : __CODEGEN_BITFIELD(19, 21) ; //!< SHADER_CHANNEL_SELECT_BLUE 414 uint32_t ShaderChannelSelectGreen : __CODEGEN_BITFIELD(22, 24) ; //!< SHADER_CHANNEL_SELECT_GREEN 415 uint32_t ShaderChannelSelectRed : __CODEGEN_BITFIELD(25, 27) ; //!< SHADER_CHANNEL_SELECT_RED 416 uint32_t Reserved252 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 417 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(30, 30) ; //!< Memory Compression Enable 418 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD(31, 31) ; //!< MEMORY_COMPRESSION_MODE 419 }; 420 uint32_t Value; 421 } DW7; 422 union 423 { 424 //!< DWORD 8..9 425 struct 426 { 427 uint64_t SurfaceBaseAddress ; //!< Surface Base Address 428 }; 429 uint32_t Value[2]; 430 } DW8_9; 431 union 432 { 433 //!< DWORD 10..11 434 struct 435 { 436 uint64_t QuiltWidth : __CODEGEN_BITFIELD( 0, 4) ; //!< Quilt Width, 437 uint64_t QuiltHeight : __CODEGEN_BITFIELD( 5, 9) ; //!< Quilt Height, 438 uint64_t Reserved330 : __CODEGEN_BITFIELD(10, 63) ; //!< Reserved, 439 } Obj0; 440 struct 441 { 442 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved, 443 uint64_t AuxiliarySurfaceBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Auxiliary Surface Base Address, ([Surface Format] != 'PLANAR') AND [Memory Compression Enable] == 0 444 } Obj1; 445 struct 446 { 447 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 20) ; //!< Reserved, 448 uint64_t AuxiliaryTableIndexForMediaCompressedSurface : __CODEGEN_BITFIELD(21, 31) ; //!< Auxiliary Table Index for Media Compressed Surface, [Memory Compression Enable] ==1 449 uint64_t Reserved352 : __CODEGEN_BITFIELD(32, 63) ; //!< Reserved, [Memory Compression Enable] ==1 450 } Obj2; 451 struct 452 { 453 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved, [Memory Compression Enable] ==1 454 uint64_t YOffsetForVPlane : __CODEGEN_BITFIELD(32, 45) ; //!< Y Offset for V Plane, ([Surface Format] == 'PLANAR') 455 uint64_t Reserved366 : __CODEGEN_BITFIELD(46, 47) ; //!< Reserved, ([Surface Format] == 'PLANAR') 456 uint64_t XOffsetForVPlane : __CODEGEN_BITFIELD(48, 61) ; //!< X Offset for V Plane, ([Surface Format] == 'PLANAR') 457 uint64_t Reserved382 : __CODEGEN_BITFIELD(62, 63) ; //!< Reserved, ([Surface Format] == 'PLANAR') 458 } Obj3; 459 uint32_t Value[2]; 460 } DW10_11; 461 union 462 { 463 //!< DWORD 12 464 struct 465 { 466 uint32_t HierarchicalDepthClearValue ; //!< Hierarchical Depth Clear Value, [Auxiliary Surface Mode] == 'AUX_HIZ' 467 } Obj0; 468 struct 469 { 470 uint32_t RedClearColor ; //!< Red Clear Color, [Auxiliary Surface Mode] == 'AUX_CCS_D' OR [Auxiliary Surface Mode] == 'AUX_CCS_E' 471 } Obj1; 472 uint32_t Value; 473 } DW12; 474 union 475 { 476 //!< DWORD 13 477 struct 478 { 479 uint32_t GreenClearColor ; //!< Green Clear Color, [Auxiliary Surface Mode] == 'AUX_CCS_D' OR [Auxiliary Surface Mode] == 'AUX_CCS_E' 480 }; 481 uint32_t Value; 482 } DW13; 483 union 484 { 485 //!< DWORD 14 486 struct 487 { 488 uint32_t BlueClearColor ; //!< Blue Clear Color, [Auxiliary Surface Mode] == 'AUX_CCS_D' OR [Auxiliary Surface Mode] == 'AUX_CCS_E' 489 }; 490 uint32_t Value; 491 } DW14; 492 union 493 { 494 //!< DWORD 15 495 struct 496 { 497 uint32_t AlphaClearColor ; //!< Alpha Clear Color, [Auxiliary Surface Mode] == 'AUX_CCS_D' OR [Auxiliary Surface Mode] == 'AUX_CCS_E' 498 }; 499 uint32_t Value; 500 } DW15; 501 502 //! \name Local enumerations 503 504 //! \brief MEDIA_BOUNDARY_PIXEL_MODE 505 //! \details 506 //! <div id="GroupContent-248" class="GroupContent UseCKEdit"> 507 //! <p><b>For 2D Non-Array Surfaces accessed via the Data Port Media Block 508 //! Read Message or Data Port Transpose Read message:</b><br /> 509 //! This field enables control of which rows are returned on vertical 510 //! out-of-bounds reads using the Data Port Media Block Read Message or Data 511 //! Port Transpose Read message. In the description below, frame mode refers 512 //! to <b>Vertical Line Stride</b> = 0, field mode is <b>Vertical Line 513 //! Stride</b> = 1 in which only the even or odd rows are addressable. The 514 //! frame refers to the entire surface, while the field refers only to the 515 //! even or odd rows within the surface.</p> 516 //! <p><b>For Other Surfaces:</b><br /> 517 //! Reserved : MBZ</p></div> 518 enum MEDIA_BOUNDARY_PIXEL_MODE 519 { 520 MEDIA_BOUNDARY_PIXEL_MODE_NORMALMODE = 0, //!< The row returned on an out-of-bound access is the closest row in the frame or field. Rows from the opposite field are never returned. 521 MEDIA_BOUNDARY_PIXEL_MODE_PROGRESSIVEFRAME = 2, //!< The row returned on an out-of-bound access is the closest row in the frame, even if in field mode. 522 MEDIA_BOUNDARY_PIXEL_MODE_INTERLACEDFRAME = 3, //!< In field mode, the row returned on an out-of-bound access is the closest row in the field. In frame mode, even out-of-bound rows return the nearest even row while odd out-of-bound rows return the nearest odd row. 523 }; 524 525 //! \brief RENDER_CACHE_READ_WRITE_MODE 526 //! \details 527 //! <p><b>For Surfaces accessed via the Data Port to Render Cache:</b><br /> 528 //! This field specifies the way Render Cache treats a write request. If 529 //! unset, Render Cache allocates a write-only cache line for a write miss. 530 //! If set, Render Cache allocates a read-write cache line for a write 531 //! miss.</p> 532 //! <p><b>For Surfaces accessed via the Sampling Engine or Data Port to 533 //! Texture Cache or Data Cache:</b><br /> 534 //! This field is reserved : MBZ</p> 535 enum RENDER_CACHE_READ_WRITE_MODE 536 { 537 RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLYCACHE = 0, //!< Allocating write-only cache for a write miss 538 RENDER_CACHE_READ_WRITE_MODE_READ_WRITECACHE = 1, //!< Allocating read-write cache for a write miss 539 }; 540 541 //! \brief TILE_MODE 542 //! \details 543 //! This field specifies the type of memory tiling (Linear, WMajor, XMajor, 544 //! or YMajor) employed to tile this surface. See <em>Memory Interface 545 //! Functions</em> for details on memory tiling and restrictions. 546 enum TILE_MODE 547 { 548 TILE_MODE_LINEAR = 0, //!< Linear mode (no tiling) 549 TILE_MODE_WMAJOR = 1, //!< W major tiling 550 TILE_MODE_XMAJOR = 2, //!< X major tiling 551 TILE_MODE_YMAJOR = 3, //!< Y major tiling 552 }; 553 554 //! \brief SURFACE_HORIZONTAL_ALIGNMENT 555 //! \details 556 //! For Sampling Engine and Render Target Surfaces: This field specifies the 557 //! horizontal alignment requirement for the surface. 558 enum SURFACE_HORIZONTAL_ALIGNMENT 559 { 560 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN4 = 1, //!< Horizontal alignment factor j = 4 561 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN8 = 2, //!< Horizontal alignment factor j = 8 562 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN16 = 3, //!< Horizontal alignment factor j = 16 563 }; 564 565 //! \brief SURFACE_VERTICAL_ALIGNMENT 566 //! \details 567 //! <b>For Sampling Engine and Render Target Surfaces:</b> This field 568 //! specifies the vertical alignment requirement in elements for the 569 //! surface. Refer to the "Memory Data Formats" chapter for details on how 570 //! this field changes the layout of the surface in memory. An 571 //! <i>element</i> is defined as a pixel in uncompresed surface formats, and 572 //! as a compression block in compressed surface formats. For 573 //! MSFMT_DEPTH_STENCIL type multisampled surfaces, an element is a sample. 574 enum SURFACE_VERTICAL_ALIGNMENT 575 { 576 SURFACE_VERTICAL_ALIGNMENT_VALIGN4 = 1, //!< Vertical alignment factor j = 4 577 SURFACE_VERTICAL_ALIGNMENT_VALIGN8 = 2, //!< Vertical alignment factor j = 8 578 SURFACE_VERTICAL_ALIGNMENT_VALIGN16 = 3, //!< Vertical alignment factor j = 16 579 }; 580 581 //! \brief SURFACE_FORMAT 582 //! \details 583 //! This field specifies the format of the surface or element within this 584 //! surface. This field is ignored for all data port messages other than the 585 //! render target message and streamed vertex buffer write message. Some 586 //! forms of the media block messages use the surface format. 587 enum SURFACE_FORMAT 588 { 589 SURFACE_FORMAT_R32G32B32A32FLOAT = 0, //!< No additional details 590 SURFACE_FORMAT_R32G32B32A32SINT = 1, //!< No additional details 591 SURFACE_FORMAT_R32G32B32A32UINT = 2, //!< No additional details 592 SURFACE_FORMAT_R32G32B32A32UNORM = 3, //!< No additional details 593 SURFACE_FORMAT_R32G32B32A32SNORM = 4, //!< No additional details 594 SURFACE_FORMAT_R64G64FLOAT = 5, //!< No additional details 595 SURFACE_FORMAT_R32G32B32X32FLOAT = 6, //!< No additional details 596 SURFACE_FORMAT_R32G32B32A32SSCALED = 7, //!< No additional details 597 SURFACE_FORMAT_R32G32B32A32USCALED = 8, //!< No additional details 598 SURFACE_FORMAT_R32G32B32A32SFIXED = 32, //!< No additional details 599 SURFACE_FORMAT_R64G64PASSTHRU = 33, //!< No additional details 600 SURFACE_FORMAT_R32G32B32FLOAT = 64, //!< No additional details 601 SURFACE_FORMAT_R32G32B32SINT = 65, //!< No additional details 602 SURFACE_FORMAT_R32G32B32UINT = 66, //!< No additional details 603 SURFACE_FORMAT_R32G32B32UNORM = 67, //!< No additional details 604 SURFACE_FORMAT_R32G32B32SNORM = 68, //!< No additional details 605 SURFACE_FORMAT_R32G32B32SSCALED = 69, //!< No additional details 606 SURFACE_FORMAT_R32G32B32USCALED = 70, //!< No additional details 607 SURFACE_FORMAT_R32G32B32SFIXED = 80, //!< No additional details 608 SURFACE_FORMAT_R16G16B16A16UNORM = 128, //!< No additional details 609 SURFACE_FORMAT_R16G16B16A16SNORM = 129, //!< No additional details 610 SURFACE_FORMAT_R16G16B16A16SINT = 130, //!< No additional details 611 SURFACE_FORMAT_R16G16B16A16UINT = 131, //!< No additional details 612 SURFACE_FORMAT_R16G16B16A16FLOAT = 132, //!< No additional details 613 SURFACE_FORMAT_R32G32FLOAT = 133, //!< No additional details 614 SURFACE_FORMAT_R32G32SINT = 134, //!< No additional details 615 SURFACE_FORMAT_R32G32UINT = 135, //!< No additional details 616 SURFACE_FORMAT_R32FLOATX8X24TYPELESS = 136, //!< No additional details 617 SURFACE_FORMAT_X32TYPELESSG8X24UINT = 137, //!< No additional details 618 SURFACE_FORMAT_L32A32FLOAT = 138, //!< No additional details 619 SURFACE_FORMAT_R32G32UNORM = 139, //!< No additional details 620 SURFACE_FORMAT_R32G32SNORM = 140, //!< No additional details 621 SURFACE_FORMAT_R64FLOAT = 141, //!< No additional details 622 SURFACE_FORMAT_R16G16B16X16UNORM = 142, //!< No additional details 623 SURFACE_FORMAT_R16G16B16X16FLOAT = 143, //!< No additional details 624 SURFACE_FORMAT_A32X32FLOAT = 144, //!< No additional details 625 SURFACE_FORMAT_L32X32FLOAT = 145, //!< No additional details 626 SURFACE_FORMAT_I32X32FLOAT = 146, //!< No additional details 627 SURFACE_FORMAT_R16G16B16A16SSCALED = 147, //!< No additional details 628 SURFACE_FORMAT_R16G16B16A16USCALED = 148, //!< No additional details 629 SURFACE_FORMAT_R32G32SSCALED = 149, //!< No additional details 630 SURFACE_FORMAT_R32G32USCALED = 150, //!< No additional details 631 SURFACE_FORMAT_R32G32SFIXED = 160, //!< No additional details 632 SURFACE_FORMAT_R64PASSTHRU = 161, //!< No additional details 633 SURFACE_FORMAT_B8G8R8A8UNORM = 192, //!< No additional details 634 SURFACE_FORMAT_B8G8R8A8UNORMSRGB = 193, //!< No additional details 635 SURFACE_FORMAT_R10G10B10A2UNORM = 194, //!< No additional details 636 SURFACE_FORMAT_R10G10B10A2UNORMSRGB = 195, //!< No additional details 637 SURFACE_FORMAT_R10G10B10A2UINT = 196, //!< No additional details 638 SURFACE_FORMAT_R10G10B10SNORMA2UNORM = 197, //!< No additional details 639 SURFACE_FORMAT_R8G8B8A8UNORM = 199, //!< No additional details 640 SURFACE_FORMAT_R8G8B8A8UNORMSRGB = 200, //!< No additional details 641 SURFACE_FORMAT_R8G8B8A8SNORM = 201, //!< No additional details 642 SURFACE_FORMAT_R8G8B8A8SINT = 202, //!< No additional details 643 SURFACE_FORMAT_R8G8B8A8UINT = 203, //!< No additional details 644 SURFACE_FORMAT_R16G16UNORM = 204, //!< No additional details 645 SURFACE_FORMAT_R16G16SNORM = 205, //!< No additional details 646 SURFACE_FORMAT_R16G16SINT = 206, //!< No additional details 647 SURFACE_FORMAT_R16G16UINT = 207, //!< No additional details 648 SURFACE_FORMAT_R16G16FLOAT = 208, //!< No additional details 649 SURFACE_FORMAT_B10G10R10A2UNORM = 209, //!< No additional details 650 SURFACE_FORMAT_B10G10R10A2UNORMSRGB = 210, //!< No additional details 651 SURFACE_FORMAT_R11G11B10FLOAT = 211, //!< No additional details 652 SURFACE_FORMAT_R32SINT = 214, //!< No additional details 653 SURFACE_FORMAT_R32UINT = 215, //!< No additional details 654 SURFACE_FORMAT_R32FLOAT = 216, //!< No additional details 655 SURFACE_FORMAT_R24UNORMX8TYPELESS = 217, //!< No additional details 656 SURFACE_FORMAT_X24TYPELESSG8UINT = 218, //!< No additional details 657 SURFACE_FORMAT_L32UNORM = 221, //!< No additional details 658 SURFACE_FORMAT_A32UNORM = 222, //!< No additional details 659 SURFACE_FORMAT_L16A16UNORM = 223, //!< No additional details 660 SURFACE_FORMAT_I24X8UNORM = 224, //!< No additional details 661 SURFACE_FORMAT_L24X8UNORM = 225, //!< No additional details 662 SURFACE_FORMAT_A24X8UNORM = 226, //!< No additional details 663 SURFACE_FORMAT_I32FLOAT = 227, //!< No additional details 664 SURFACE_FORMAT_L32FLOAT = 228, //!< No additional details 665 SURFACE_FORMAT_A32FLOAT = 229, //!< No additional details 666 SURFACE_FORMAT_X8B8UNORMG8R8SNORM = 230, //!< No additional details 667 SURFACE_FORMAT_A8X8UNORMG8R8SNORM = 231, //!< No additional details 668 SURFACE_FORMAT_B8X8UNORMG8R8SNORM = 232, //!< No additional details 669 SURFACE_FORMAT_B8G8R8X8UNORM = 233, //!< No additional details 670 SURFACE_FORMAT_B8G8R8X8UNORMSRGB = 234, //!< No additional details 671 SURFACE_FORMAT_R8G8B8X8UNORM = 235, //!< No additional details 672 SURFACE_FORMAT_R8G8B8X8UNORMSRGB = 236, //!< No additional details 673 SURFACE_FORMAT_R9G9B9E5SHAREDEXP = 237, //!< No additional details 674 SURFACE_FORMAT_B10G10R10X2UNORM = 238, //!< No additional details 675 SURFACE_FORMAT_L16A16FLOAT = 240, //!< No additional details 676 SURFACE_FORMAT_R32UNORM = 241, //!< No additional details 677 SURFACE_FORMAT_R32SNORM = 242, //!< No additional details 678 SURFACE_FORMAT_R10G10B10X2USCALED = 243, //!< No additional details 679 SURFACE_FORMAT_R8G8B8A8SSCALED = 244, //!< No additional details 680 SURFACE_FORMAT_R8G8B8A8USCALED = 245, //!< No additional details 681 SURFACE_FORMAT_R16G16SSCALED = 246, //!< No additional details 682 SURFACE_FORMAT_R16G16USCALED = 247, //!< No additional details 683 SURFACE_FORMAT_R32SSCALED = 248, //!< No additional details 684 SURFACE_FORMAT_R32USCALED = 249, //!< No additional details 685 SURFACE_FORMAT_B5G6R5UNORM = 256, //!< No additional details 686 SURFACE_FORMAT_B5G6R5UNORMSRGB = 257, //!< No additional details 687 SURFACE_FORMAT_B5G5R5A1UNORM = 258, //!< No additional details 688 SURFACE_FORMAT_B5G5R5A1UNORMSRGB = 259, //!< No additional details 689 SURFACE_FORMAT_B4G4R4A4UNORM = 260, //!< No additional details 690 SURFACE_FORMAT_B4G4R4A4UNORMSRGB = 261, //!< No additional details 691 SURFACE_FORMAT_R8G8UNORM = 262, //!< No additional details 692 SURFACE_FORMAT_R8G8SNORM = 263, //!< No additional details 693 SURFACE_FORMAT_R8G8SINT = 264, //!< No additional details 694 SURFACE_FORMAT_R8G8UINT = 265, //!< No additional details 695 SURFACE_FORMAT_R16UNORM = 266, //!< No additional details 696 SURFACE_FORMAT_R16SNORM = 267, //!< No additional details 697 SURFACE_FORMAT_R16SINT = 268, //!< No additional details 698 SURFACE_FORMAT_R16UINT = 269, //!< No additional details 699 SURFACE_FORMAT_R16FLOAT = 270, //!< No additional details 700 SURFACE_FORMAT_A8P8UNORMPALETTE0 = 271, //!< No additional details 701 SURFACE_FORMAT_A8P8UNORMPALETTE1 = 272, //!< No additional details 702 SURFACE_FORMAT_I16UNORM = 273, //!< No additional details 703 SURFACE_FORMAT_L16UNORM = 274, //!< No additional details 704 SURFACE_FORMAT_A16UNORM = 275, //!< No additional details 705 SURFACE_FORMAT_L8A8UNORM = 276, //!< No additional details 706 SURFACE_FORMAT_I16FLOAT = 277, //!< No additional details 707 SURFACE_FORMAT_L16FLOAT = 278, //!< No additional details 708 SURFACE_FORMAT_A16FLOAT = 279, //!< No additional details 709 SURFACE_FORMAT_L8A8UNORMSRGB = 280, //!< No additional details 710 SURFACE_FORMAT_R5G5SNORMB6UNORM = 281, //!< No additional details 711 SURFACE_FORMAT_B5G5R5X1UNORM = 282, //!< No additional details 712 SURFACE_FORMAT_B5G5R5X1UNORMSRGB = 283, //!< No additional details 713 SURFACE_FORMAT_R8G8SSCALED = 284, //!< No additional details 714 SURFACE_FORMAT_R8G8USCALED = 285, //!< No additional details 715 SURFACE_FORMAT_R16SSCALED = 286, //!< No additional details 716 SURFACE_FORMAT_R16USCALED = 287, //!< No additional details 717 SURFACE_FORMAT_P8A8UNORMPALETTE0 = 290, //!< No additional details 718 SURFACE_FORMAT_P8A8UNORMPALETTE1 = 291, //!< No additional details 719 SURFACE_FORMAT_A1B5G5R5UNORM = 292, //!< No additional details 720 SURFACE_FORMAT_A4B4G4R4UNORM = 293, //!< No additional details 721 SURFACE_FORMAT_L8A8UINT = 294, //!< No additional details 722 SURFACE_FORMAT_L8A8SINT = 295, //!< No additional details 723 SURFACE_FORMAT_R8UNORM = 320, //!< No additional details 724 SURFACE_FORMAT_R8SNORM = 321, //!< No additional details 725 SURFACE_FORMAT_R8SINT = 322, //!< No additional details 726 SURFACE_FORMAT_R8UINT = 323, //!< No additional details 727 SURFACE_FORMAT_A8UNORM = 324, //!< No additional details 728 SURFACE_FORMAT_I8UNORM = 325, //!< No additional details 729 SURFACE_FORMAT_L8UNORM = 326, //!< No additional details 730 SURFACE_FORMAT_P4A4UNORMPALETTE0 = 327, //!< No additional details 731 SURFACE_FORMAT_A4P4UNORMPALETTE0 = 328, //!< No additional details 732 SURFACE_FORMAT_R8SSCALED = 329, //!< No additional details 733 SURFACE_FORMAT_R8USCALED = 330, //!< No additional details 734 SURFACE_FORMAT_P8UNORMPALETTE0 = 331, //!< No additional details 735 SURFACE_FORMAT_L8UNORMSRGB = 332, //!< No additional details 736 SURFACE_FORMAT_P8UNORMPALETTE1 = 333, //!< No additional details 737 SURFACE_FORMAT_P4A4UNORMPALETTE1 = 334, //!< No additional details 738 SURFACE_FORMAT_A4P4UNORMPALETTE1 = 335, //!< No additional details 739 SURFACE_FORMAT_Y8UNORM = 336, //!< No additional details 740 SURFACE_FORMAT_L8UINT = 338, //!< No additional details 741 SURFACE_FORMAT_L8SINT = 339, //!< No additional details 742 SURFACE_FORMAT_I8UINT = 340, //!< No additional details 743 SURFACE_FORMAT_I8SINT = 341, //!< No additional details 744 SURFACE_FORMAT_DXT1RGBSRGB = 384, //!< No additional details 745 SURFACE_FORMAT_R1UNORM = 385, //!< No additional details 746 SURFACE_FORMAT_YCRCBNORMAL = 386, //!< No additional details 747 SURFACE_FORMAT_YCRCBSWAPUVY = 387, //!< No additional details 748 SURFACE_FORMAT_P2UNORMPALETTE0 = 388, //!< No additional details 749 SURFACE_FORMAT_P2UNORMPALETTE1 = 389, //!< No additional details 750 SURFACE_FORMAT_BC1UNORM = 390, //!< No additional details 751 SURFACE_FORMAT_BC2UNORM = 391, //!< No additional details 752 SURFACE_FORMAT_BC3UNORM = 392, //!< No additional details 753 SURFACE_FORMAT_BC4UNORM = 393, //!< No additional details 754 SURFACE_FORMAT_BC5UNORM = 394, //!< No additional details 755 SURFACE_FORMAT_BC1UNORMSRGB = 395, //!< No additional details 756 SURFACE_FORMAT_BC2UNORMSRGB = 396, //!< No additional details 757 SURFACE_FORMAT_BC3UNORMSRGB = 397, //!< No additional details 758 SURFACE_FORMAT_MONO8 = 398, //!< No additional details 759 SURFACE_FORMAT_YCRCBSWAPUV = 399, //!< No additional details 760 SURFACE_FORMAT_YCRCBSWAPY = 400, //!< No additional details 761 SURFACE_FORMAT_DXT1RGB = 401, //!< No additional details 762 SURFACE_FORMAT_FXT1 = 402, //!< No additional details 763 SURFACE_FORMAT_R8G8B8UNORM = 403, //!< No additional details 764 SURFACE_FORMAT_R8G8B8SNORM = 404, //!< No additional details 765 SURFACE_FORMAT_R8G8B8SSCALED = 405, //!< No additional details 766 SURFACE_FORMAT_R8G8B8USCALED = 406, //!< No additional details 767 SURFACE_FORMAT_R64G64B64A64FLOAT = 407, //!< No additional details 768 SURFACE_FORMAT_R64G64B64FLOAT = 408, //!< No additional details 769 SURFACE_FORMAT_BC4SNORM = 409, //!< No additional details 770 SURFACE_FORMAT_BC5SNORM = 410, //!< No additional details 771 SURFACE_FORMAT_R16G16B16FLOAT = 411, //!< No additional details 772 SURFACE_FORMAT_R16G16B16UNORM = 412, //!< No additional details 773 SURFACE_FORMAT_R16G16B16SNORM = 413, //!< No additional details 774 SURFACE_FORMAT_R16G16B16SSCALED = 414, //!< No additional details 775 SURFACE_FORMAT_R16G16B16USCALED = 415, //!< No additional details 776 SURFACE_FORMAT_BC6HSF16 = 417, //!< No additional details 777 SURFACE_FORMAT_BC7UNORM = 418, //!< No additional details 778 SURFACE_FORMAT_BC7UNORMSRGB = 419, //!< No additional details 779 SURFACE_FORMAT_BC6HUF16 = 420, //!< No additional details 780 SURFACE_FORMAT_PLANAR4208 = 421, //!< No additional details 781 SURFACE_FORMAT_R8G8B8UNORMSRGB = 424, //!< No additional details 782 SURFACE_FORMAT_ETC1RGB8 = 425, //!< No additional details 783 SURFACE_FORMAT_ETC2RGB8 = 426, //!< No additional details 784 SURFACE_FORMAT_EACR11 = 427, //!< No additional details 785 SURFACE_FORMAT_EACRG11 = 428, //!< No additional details 786 SURFACE_FORMAT_EACSIGNEDR11 = 429, //!< No additional details 787 SURFACE_FORMAT_EACSIGNEDRG11 = 430, //!< No additional details 788 SURFACE_FORMAT_ETC2SRGB8 = 431, //!< No additional details 789 SURFACE_FORMAT_R16G16B16UINT = 432, //!< No additional details 790 SURFACE_FORMAT_R16G16B16SINT = 433, //!< No additional details 791 SURFACE_FORMAT_R32SFIXED = 434, //!< No additional details 792 SURFACE_FORMAT_R10G10B10A2SNORM = 435, //!< No additional details 793 SURFACE_FORMAT_R10G10B10A2USCALED = 436, //!< No additional details 794 SURFACE_FORMAT_R10G10B10A2SSCALED = 437, //!< No additional details 795 SURFACE_FORMAT_R10G10B10A2SINT = 438, //!< No additional details 796 SURFACE_FORMAT_B10G10R10A2SNORM = 439, //!< No additional details 797 SURFACE_FORMAT_B10G10R10A2USCALED = 440, //!< No additional details 798 SURFACE_FORMAT_B10G10R10A2SSCALED = 441, //!< No additional details 799 SURFACE_FORMAT_B10G10R10A2UINT = 442, //!< No additional details 800 SURFACE_FORMAT_B10G10R10A2SINT = 443, //!< No additional details 801 SURFACE_FORMAT_R64G64B64A64PASSTHRU = 444, //!< No additional details 802 SURFACE_FORMAT_R64G64B64PASSTHRU = 445, //!< No additional details 803 SURFACE_FORMAT_ETC2RGB8PTA = 448, //!< No additional details 804 SURFACE_FORMAT_ETC2SRGB8PTA = 449, //!< No additional details 805 SURFACE_FORMAT_ETC2EACRGBA8 = 450, //!< No additional details 806 SURFACE_FORMAT_ETC2EACSRGB8A8 = 451, //!< No additional details 807 SURFACE_FORMAT_R8G8B8UINT = 456, //!< No additional details 808 SURFACE_FORMAT_R8G8B8SINT = 457, //!< No additional details 809 SURFACE_FORMAT_RAW = 511, //!< No additional details 810 }; 811 812 //! \brief SURFACE_TYPE 813 //! \details 814 //! This field defines the type of the surface. 815 enum SURFACE_TYPE 816 { 817 SURFACE_TYPE_SURFTYPE1D = 0, //!< Defines a 1-dimensional map or array of maps 818 SURFACE_TYPE_SURFTYPE2D = 1, //!< Defines a 2-dimensional map or array of maps 819 SURFACE_TYPE_SURFTYPE3D = 2, //!< Defines a 3-dimensional (volumetric) map 820 SURFACE_TYPE_SURFTYPECUBE = 3, //!< Defines a cube map or array of cube maps 821 SURFACE_TYPE_SURFTYPEBUFFER = 4, //!< Defines an element in a buffer 822 SURFACE_TYPE_SURFTYPESTRBUF = 5, //!< Defines a structured buffer surface 823 SURFACE_TYPE_SURFTYPENULL = 7, //!< Defines a null surface 824 }; 825 826 //! \brief NUMBER_OF_MULTISAMPLES 827 //! \details 828 //! This field indicates the number of multisamples on the surface. 829 enum NUMBER_OF_MULTISAMPLES 830 { 831 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT1 = 0, //!< No additional details 832 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT2 = 1, //!< No additional details 833 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT4 = 2, //!< No additional details 834 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT8 = 3, //!< No additional details 835 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT16 = 4, //!< No additional details 836 }; 837 838 //! \brief MULTISAMPLED_SURFACE_STORAGE_FORMAT 839 //! \details 840 //! This field indicates the storage format of the multisampled surface. 841 enum MULTISAMPLED_SURFACE_STORAGE_FORMAT 842 { 843 MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS = 0, //!< Multisampled surface was/is rendered as a render target 844 MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTHSTENCIL = 1, //!< Multisampled surface was rendered as a depth or stencil buffer 845 }; 846 847 //! \brief RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 848 //! \details 849 //! <b>For Render Target Surfaces:</b> 850 //! This field specifies the rotation of this render target surface 851 //! when being written to memory. 852 enum RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 853 { 854 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG = 0, //!< No rotation (0 degrees) 855 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_90DEG = 1, //!< Rotate by 90 degrees 856 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_180DEG = 2, //!< Rotate by 180 degrees [for sample_unorm message] 857 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_270DEG = 3, //!< Rotate by 270 degrees 858 }; 859 860 //! \brief COHERENCY_TYPE 861 //! \details 862 //! Specifies the type of coherency maintained for this surface. 863 enum COHERENCY_TYPE 864 { 865 COHERENCY_TYPE_GPUCOHERENT = 0, //!< Surface memory is kept coherent with GPU threads using GPU read/write ordering rules. Surface memory is backed by system memory but is not kept coherent with CPU (LLC). 866 COHERENCY_TYPE_IACOHERENT = 1, //!< Surface memory is kept coherent with CPU (LLC). 867 }; 868 869 //! \brief TILED_RESOURCE_MODE 870 //! \details 871 //! <b>For Sampling Engine, Render Target, and Typed/Untyped Surfaces:</b> 872 //! This field specifies the tiled resource mode. 873 //! 874 //! <b>For other surfaces:</b> 875 //! This field is ignored. 876 enum TILED_RESOURCE_MODE 877 { 878 TILED_RESOURCE_MODE_NONE = 0, //!< No tiled resource 879 TILED_RESOURCE_MODE_4KB = 1, //!< 4KB tiled resources 880 TILED_RESOURCE_MODE_TILEYF = 1, //!< 4KB tiled resources 881 TILED_RESOURCE_MODE_64KB = 2, //!< 64KB tiled resources 882 TILED_RESOURCE_MODE_TILEYS = 2, //!< 64KB tiled resources 883 }; 884 885 //! \brief EWA_DISABLE_FOR_CUBE 886 //! \details 887 //! Specifies if EWA mode for LOD quality improvement needs to be disabled 888 //! for cube maps. 889 enum EWA_DISABLE_FOR_CUBE 890 { 891 EWA_DISABLE_FOR_CUBE_ENABLE = 0, //!< EWA is enabled for cube maps 892 EWA_DISABLE_FOR_CUBE_DISABLE = 1, //!< EWA is disabled for cube maps 893 }; 894 895 //! \brief AUXILIARY_SURFACE_MODE 896 //! \details 897 //! Specifies what type of surface the Auxiliary surface is. The Auxiliary 898 //! surface has its own base address and pitch, but otherwise shares or 899 //! overrides other fields set for the primary surface, detailed in the 900 //! programming notes below. 901 enum AUXILIARY_SURFACE_MODE 902 { 903 AUXILIARY_SURFACE_MODE_AUXNONE = 0, //!< No Auxiliary surface is used 904 AUXILIARY_SURFACE_MODE_AUXCCSD = 1, //!< The Auxiliary surface is a CCS (Color Control Surface) with compression disabled or an MCS with compression enabled, depending on Number of Multisamples. MCS (Multisample Control Surface) is a special type of CCS. 905 AUXILIARY_SURFACE_MODE_AUXAPPEND = 2, //!< The Auxiliary surface is an append buffer 906 AUXILIARY_SURFACE_MODE_AUXHIZ = 3, //!< The Auxiliary surface is a hierarchical depth buffer 907 AUXILIARY_SURFACE_MODE_AUXCCSE = 5, //!< The Auxiliary surface is a CCS with compression enabled or an MCS with compression enabled, depending on Number of Multisamples. 908 }; 909 910 //! \brief SHADER_CHANNEL_SELECT_ALPHA 911 //! \details 912 //! See <b>Shader Channel Select Red</b> for details. 913 enum SHADER_CHANNEL_SELECT_ALPHA 914 { 915 SHADER_CHANNEL_SELECT_ALPHA_ZERO = 0, //!< No additional details 916 SHADER_CHANNEL_SELECT_ALPHA_ONE = 1, //!< No additional details 917 SHADER_CHANNEL_SELECT_ALPHA_RED = 4, //!< No additional details 918 SHADER_CHANNEL_SELECT_ALPHA_GREEN = 5, //!< No additional details 919 SHADER_CHANNEL_SELECT_ALPHA_BLUE = 6, //!< No additional details 920 SHADER_CHANNEL_SELECT_ALPHA_ALPHA = 7, //!< No additional details 921 }; 922 923 //! \brief SHADER_CHANNEL_SELECT_BLUE 924 //! \details 925 //! See <b>Shader Channel Select Red</b> for details. 926 enum SHADER_CHANNEL_SELECT_BLUE 927 { 928 SHADER_CHANNEL_SELECT_BLUE_ZERO = 0, //!< No additional details 929 SHADER_CHANNEL_SELECT_BLUE_ONE = 1, //!< No additional details 930 SHADER_CHANNEL_SELECT_BLUE_RED = 4, //!< No additional details 931 SHADER_CHANNEL_SELECT_BLUE_GREEN = 5, //!< No additional details 932 SHADER_CHANNEL_SELECT_BLUE_BLUE = 6, //!< No additional details 933 SHADER_CHANNEL_SELECT_BLUE_ALPHA = 7, //!< No additional details 934 }; 935 936 //! \brief SHADER_CHANNEL_SELECT_GREEN 937 //! \details 938 //! See <b>Shader Channel Select Red</b> for details. 939 enum SHADER_CHANNEL_SELECT_GREEN 940 { 941 SHADER_CHANNEL_SELECT_GREEN_ZERO = 0, //!< No additional details 942 SHADER_CHANNEL_SELECT_GREEN_ONE = 1, //!< No additional details 943 SHADER_CHANNEL_SELECT_GREEN_RED = 4, //!< No additional details 944 SHADER_CHANNEL_SELECT_GREEN_GREEN = 5, //!< No additional details 945 SHADER_CHANNEL_SELECT_GREEN_BLUE = 6, //!< No additional details 946 SHADER_CHANNEL_SELECT_GREEN_ALPHA = 7, //!< No additional details 947 }; 948 949 //! \brief SHADER_CHANNEL_SELECT_RED 950 //! \details 951 //! Specifies which surface channel is read or written in the Red shader 952 //! channel. 953 enum SHADER_CHANNEL_SELECT_RED 954 { 955 SHADER_CHANNEL_SELECT_RED_ZERO = 0, //!< No additional details 956 SHADER_CHANNEL_SELECT_RED_ONE = 1, //!< No additional details 957 SHADER_CHANNEL_SELECT_RED_RED = 4, //!< No additional details 958 SHADER_CHANNEL_SELECT_RED_GREEN = 5, //!< No additional details 959 SHADER_CHANNEL_SELECT_RED_BLUE = 6, //!< No additional details 960 SHADER_CHANNEL_SELECT_RED_ALPHA = 7, //!< No additional details 961 }; 962 963 //! \brief MEMORY_COMPRESSION_MODE 964 //! \details 965 //! Distinguishes Vertical from Horizontal compression. 966 enum MEMORY_COMPRESSION_MODE 967 { 968 MEMORY_COMPRESSION_MODE_HORIZONTAL = 0, //!< No additional details 969 MEMORY_COMPRESSION_MODE_VERTICAL = 1, //!< No additional details 970 }; 971 972 //! \name Initializations 973 974 //! \brief Explicit member initialization function 975 RENDER_SURFACE_STATE_CMD(); 976 977 static const size_t dwSize = 16; 978 static const size_t byteSize = 64; 979 }; 980 981 //! 982 //! \brief MEDIA_SURFACE_STATE 983 //! \details 984 //! This is the SURFACE_STATE used by only deinterlace, sample_8x8, and VME 985 //! messages. 986 //! 987 struct MEDIA_SURFACE_STATE_CMD 988 { 989 union 990 { 991 //!< DWORD 0 992 struct 993 { 994 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 995 uint32_t YOffset : __CODEGEN_BITFIELD(16, 19) ; //!< Y Offset, [Surface Format] is one of Planar Formats 996 uint32_t XOffset : __CODEGEN_BITFIELD(20, 26) ; //!< X Offset, [Surface Format] is one of Planar Formats 997 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 29) ; //!< Reserved, [Surface Format] is one of Planar Formats 998 uint32_t Rotation : __CODEGEN_BITFIELD(30, 31) ; //!< ROTATION 999 }; 1000 uint32_t Value; 1001 } DW0; 1002 union 1003 { 1004 //!< DWORD 1 1005 struct 1006 { 1007 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION 1008 uint32_t PictureStructure : __CODEGEN_BITFIELD( 2, 3) ; //!< PICTURE_STRUCTURE 1009 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1010 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1011 }; 1012 uint32_t Value; 1013 } DW1; 1014 union 1015 { 1016 //!< DWORD 2 1017 struct 1018 { 1019 uint32_t TileMode : __CODEGEN_BITFIELD( 0, 1) ; //!< TILE_MODE 1020 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 1021 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 20) ; //!< Surface Pitch 1022 uint32_t AddressControl : __CODEGEN_BITFIELD(21, 21) ; //!< ADDRESS_CONTROL 1023 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(22, 22) ; //!< Memory Compression Enable 1024 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD(23, 23) ; //!< MEMORY_COMPRESSION_MODE 1025 uint32_t CrVCbUPixelOffsetVDirectionMsb : __CODEGEN_BITFIELD(24, 24) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1026 uint32_t CrVCbUPixelOffsetUDirection : __CODEGEN_BITFIELD(25, 25) ; //!< CRVCBU_PIXEL_OFFSET_U_DIRECTION 1027 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(26, 26) ; //!< Interleave Chroma 1028 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 1029 }; 1030 uint32_t Value; 1031 } DW2; 1032 union 1033 { 1034 //!< DWORD 3 1035 struct 1036 { 1037 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U(Cb) 1038 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1039 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U(Cb) 1040 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1041 }; 1042 uint32_t Value; 1043 } DW3; 1044 union 1045 { 1046 //!< DWORD 4 1047 struct 1048 { 1049 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for V(Cr) 1050 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1051 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for V(Cr) 1052 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1053 }; 1054 uint32_t Value; 1055 } DW4; 1056 union 1057 { 1058 //!< DWORD 5 1059 struct 1060 { 1061 uint32_t SurfaceMemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< SURFACE_MEMORY_OBJECT_CONTROL_STATE 1062 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 17) ; //!< Reserved 1063 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(18, 19) ; //!< TILED_RESOURCE_MODE 1064 uint32_t Reserved180 : __CODEGEN_BITFIELD(20, 29) ; //!< Reserved 1065 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(30, 30) ; //!< Vertical Line Stride Offset 1066 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(31, 31) ; //!< Vertical Line Stride 1067 }; 1068 uint32_t Value; 1069 } DW5; 1070 union 1071 { 1072 //!< DWORD 6 1073 struct 1074 { 1075 uint32_t SurfaceBaseAddress ; //!< Surface Base Address 1076 }; 1077 uint32_t Value; 1078 } DW6; 1079 union 1080 { 1081 //!< DWORD 7 1082 struct 1083 { 1084 uint32_t SurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Surface Base Address High 1085 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1086 }; 1087 uint32_t Value; 1088 } DW7; 1089 1090 //! \name Local enumerations 1091 1092 //! \brief ROTATION 1093 //! \details 1094 //! Rotation is only supported only with AVS function messages and not with 1095 //! HDC direct write and 16x8 AVS messages. 1096 enum ROTATION 1097 { 1098 ROTATION_NOROTATIONOR0DEGREE = 0, //!< No additional details 1099 ROTATION_90DEGREEROTATION = 1, //!< No additional details 1100 ROTATION_180DEGREEROTATION = 2, //!< No additional details 1101 ROTATION_270DEGREEROTATION = 3, //!< No additional details 1102 }; 1103 1104 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION 1105 //! \details 1106 //! Specifies the distance to the U/V values with respect to the even 1107 //! numbered Y channels in the V direction 1108 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION 1109 { 1110 CRVCBU_PIXEL_OFFSET_V_DIRECTION_UNNAMED0 = 0, //!< No additional details 1111 }; 1112 1113 //! \brief PICTURE_STRUCTURE 1114 //! \details 1115 //! Specifies the encoding of the current picture. 1116 enum PICTURE_STRUCTURE 1117 { 1118 PICTURE_STRUCTURE_FRAMEPICTURE = 0, //!< No additional details 1119 PICTURE_STRUCTURE_TOPFIELDPICTURE = 1, //!< No additional details 1120 PICTURE_STRUCTURE_BOTTOMFIELDPICTURE = 2, //!< No additional details 1121 PICTURE_STRUCTURE_INVALID_NOTALLOWED = 3, //!< No additional details 1122 }; 1123 1124 //! \brief TILE_MODE 1125 //! \details 1126 //! This field specifies the type of memory tiling (Linear, WMajor, XMajor, 1127 //! or YMajor) employed to tile this surface. See Memory Interface Functions 1128 //! for details on memory tiling and restrictions. 1129 enum TILE_MODE 1130 { 1131 TILE_MODE_TILEMODELINEAR = 0, //!< Linear mode (no tiling) 1132 TILE_MODE_TILEMODEXMAJOR = 2, //!< X major tiling 1133 TILE_MODE_TILEMODEYMAJOR = 3, //!< Y major tiling 1134 }; 1135 1136 enum ADDRESS_CONTROL 1137 { 1138 ADDRESS_CONTROL_CLAMP = 0, //!< Clamp 1139 ADDRESS_CONTROL_MIRROR = 1, //!< Mirror 1140 }; 1141 1142 //! \brief MEMORY_COMPRESSION_MODE 1143 //! \details 1144 //! Distinguishes Vertical from Horizontal compression. 1145 enum MEMORY_COMPRESSION_MODE 1146 { 1147 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 1148 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 1149 }; 1150 1151 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1152 //! \details 1153 //! Specifies the distance to the U/V values with respect to the even 1154 //! numbered Y channels in the V direction 1155 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1156 { 1157 CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB_UNNAMED0 = 0, //!< No additional details 1158 }; 1159 1160 //! \brief CRVCBU_PIXEL_OFFSET_U_DIRECTION 1161 //! \details 1162 //! Specifies the distance to the U/V values with respect to the even 1163 //! numbered Y channels in the U direction 1164 enum CRVCBU_PIXEL_OFFSET_U_DIRECTION 1165 { 1166 CRVCBU_PIXEL_OFFSET_U_DIRECTION_UNNAMED0 = 0, //!< No additional details 1167 }; 1168 1169 //! \brief SURFACE_FORMAT 1170 //! \details 1171 //! Specifies the format of the surface. All of the Y and G channels will 1172 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1. 1173 enum SURFACE_FORMAT 1174 { 1175 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 1176 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 1177 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 1178 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 1179 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 1180 SURFACE_FORMAT_Y8UNORMVA = 5, //!< Sample_8x8 only except AVS 1181 SURFACE_FORMAT_Y16SNORM = 6, //!< Sample_8x8 only except AVS 1182 SURFACE_FORMAT_Y16UNORMVA = 7, //!< Sample_8x8 only except AVS 1183 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 only 1184 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 AVS only 1185 SURFACE_FORMAT_R8B8UNORM_CRCB = 10, //!< Sample_8x8 AVS only 1186 SURFACE_FORMAT_R8UNORM_CRCB = 11, //!< Sample_8x8 AVS only 1187 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 AVS only 1188 SURFACE_FORMAT_A8Y8U8V8UNORM = 13, //!< Sample_8x8 AVS only 1189 SURFACE_FORMAT_B8G8R8A8UNORM = 14, //!< Sample_8x8 AVS only 1190 SURFACE_FORMAT_R16G16B16A16 = 15, //!< Sample_8x8 AVS only 1191 SURFACE_FORMAT_Y1UNORM = 16, //!< Sample_8x8 only for boolean surfaces (1bit/pixel) 1192 SURFACE_FORMAT_Y32UNORM = 17, //!< For Integral Image (32bpp) 1193 SURFACE_FORMAT_PLANAR4228 = 18, //!< Sample_8x8 AVS only 1194 }; 1195 1196 //! \brief SURFACE_MEMORY_OBJECT_CONTROL_STATE 1197 //! \details 1198 //! This 7-bit field is used in various state commands and indirect state 1199 //! objects to define cacheability and other attributes related to memory 1200 //! objects. 1201 enum SURFACE_MEMORY_OBJECT_CONTROL_STATE 1202 { 1203 SURFACE_MEMORY_OBJECT_CONTROL_STATE_DEFAULTVAUEDESC = 0, //!< No additional details 1204 }; 1205 1206 //! \brief TILED_RESOURCE_MODE 1207 //! \details 1208 //! <b>For Sampling Engine, Render Target, and Typed/Untyped Surfaces:</b> 1209 //! This field specifies the tiled resource mode. 1210 //! <b>For other surfaces:</b> 1211 //! This field is ignored. 1212 enum TILED_RESOURCE_MODE 1213 { 1214 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1215 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1216 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1217 }; 1218 1219 //! \name Initializations 1220 1221 //! \brief Explicit member initialization function 1222 MEDIA_SURFACE_STATE_CMD(); 1223 1224 static const size_t dwSize = 8; 1225 static const size_t byteSize = 32; 1226 }; 1227 1228 //! 1229 //! \brief SAMPLER_STATE 1230 //! \details 1231 //! This is the normal sampler state used by all messages that use 1232 //! SAMPLER_STATE except sample_8x8 and deinterlace. The sampler state is 1233 //! stored as an array of up to 16 elements, each of which contains the 1234 //! dwords described here. The start of each element is spaced 4 dwords 1235 //! apart. The first element of the sampler state array is aligned to a 1236 //! 32-byte boundary. 1237 //! 1238 struct SAMPLER_STATE_CMD 1239 { 1240 union 1241 { 1242 //!< DWORD 0 1243 struct 1244 { 1245 uint32_t LodAlgorithm : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_ALGORITHM 1246 uint32_t TextureLodBias : __CODEGEN_BITFIELD( 1, 13) ; //!< Texture LOD Bias 1247 uint32_t MinModeFilter : __CODEGEN_BITFIELD(14, 16) ; //!< MIN_MODE_FILTER 1248 uint32_t MagModeFilter : __CODEGEN_BITFIELD(17, 19) ; //!< MAG_MODE_FILTER 1249 uint32_t MipModeFilter : __CODEGEN_BITFIELD(20, 21) ; //!< MIP_MODE_FILTER 1250 uint32_t CoarseLodQualityMode : __CODEGEN_BITFIELD(22, 26) ; //!< COARSE_LOD_QUALITY_MODE 1251 uint32_t LodPreclampMode : __CODEGEN_BITFIELD(27, 28) ; //!< LOD_PRECLAMP_MODE 1252 uint32_t TextureBorderColorMode : __CODEGEN_BITFIELD(29, 29) ; //!< TEXTURE_BORDER_COLOR_MODE 1253 uint32_t Reserved30 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 1254 uint32_t SamplerDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Sampler Disable 1255 }; 1256 uint32_t Value; 1257 } DW0; 1258 union 1259 { 1260 //!< DWORD 1 1261 struct 1262 { 1263 uint32_t CubeSurfaceControlMode : __CODEGEN_BITFIELD( 0, 0) ; //!< CUBE_SURFACE_CONTROL_MODE 1264 uint32_t ShadowFunction : __CODEGEN_BITFIELD( 1, 3) ; //!< SHADOW_FUNCTION 1265 uint32_t ChromakeyMode : __CODEGEN_BITFIELD( 4, 4) ; //!< CHROMAKEY_MODE 1266 uint32_t ChromakeyIndex : __CODEGEN_BITFIELD( 5, 6) ; //!< ChromaKey Index 1267 uint32_t ChromakeyEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< ChromaKey Enable 1268 uint32_t MaxLod : __CODEGEN_BITFIELD( 8, 19) ; //!< Max LOD 1269 uint32_t MinLod : __CODEGEN_BITFIELD(20, 31) ; //!< Min LOD 1270 }; 1271 uint32_t Value; 1272 } DW1; 1273 union 1274 { 1275 //!< DWORD 2 1276 struct 1277 { 1278 uint32_t LodClampMagnificationMode : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_CLAMP_MAGNIFICATION_MODE 1279 uint32_t Reserved65 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 1280 uint32_t IndirectStatePointer : __CODEGEN_BITFIELD( 6, 23) ; //!< Indirect State Pointer 1281 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1282 }; 1283 uint32_t Value; 1284 } DW2; 1285 union 1286 { 1287 //!< DWORD 3 1288 struct 1289 { 1290 uint32_t TczAddressControlMode : __CODEGEN_BITFIELD( 0, 2) ; //!< TCZ_ADDRESS_CONTROL_MODE 1291 uint32_t TcyAddressControlMode : __CODEGEN_BITFIELD( 3, 5) ; //!< TCY_ADDRESS_CONTROL_MODE 1292 uint32_t TcxAddressControlMode : __CODEGEN_BITFIELD( 6, 8) ; //!< TCX_ADDRESS_CONTROL_MODE 1293 uint32_t ReductionTypeEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Reduction Type Enable 1294 uint32_t NonNormalizedCoordinateEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Non-normalized Coordinate Enable 1295 uint32_t TrilinearFilterQuality : __CODEGEN_BITFIELD(11, 12) ; //!< TRILINEAR_FILTER_QUALITY 1296 uint32_t RAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(13, 13) ; //!< R Address Min Filter Rounding Enable 1297 uint32_t RAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(14, 14) ; //!< R Address Mag Filter Rounding Enable 1298 uint32_t VAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(15, 15) ; //!< V Address Min Filter Rounding Enable 1299 uint32_t VAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(16, 16) ; //!< V Address Mag Filter Rounding Enable 1300 uint32_t UAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< U Address Min Filter Rounding Enable 1301 uint32_t UAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< U Address Mag Filter Rounding Enable 1302 uint32_t MaximumAnisotropy : __CODEGEN_BITFIELD(19, 21) ; //!< MAXIMUM_ANISOTROPY 1303 uint32_t ReductionType : __CODEGEN_BITFIELD(22, 23) ; //!< REDUCTION_TYPE 1304 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1305 }; 1306 uint32_t Value; 1307 } DW3; 1308 1309 //! \name Local enumerations 1310 1311 //! \brief LOD_ALGORITHM 1312 //! \details 1313 //! Controls which algorithm is used for LOD calculation. Generally, the EWA 1314 //! approximation algorithm results in higher image quality than the legacy 1315 //! algorithm. 1316 enum LOD_ALGORITHM 1317 { 1318 LOD_ALGORITHM_LEGACY = 0, //!< Use the legacy algorithm for anisotropic filtering 1319 LOD_ALGORITHM_EWAAPPROXIMATION = 1, //!< Use the new EWA approximation algorithm for anisotropic filtering 1320 }; 1321 1322 //! \brief MIN_MODE_FILTER 1323 //! \details 1324 //! This field determines how texels are sampled/filtered when a texture is 1325 //! being "minified" (shrunk). For volume maps, this filter mode selection 1326 //! also applies to the 3rd (inter-layer) dimension.See Mag Mode Filter 1327 enum MIN_MODE_FILTER 1328 { 1329 MIN_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1330 MIN_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1331 MIN_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1332 MIN_MODE_FILTER_MONO = 6, //!< Perform a monochrome convolution filter 1333 }; 1334 1335 //! \brief MAG_MODE_FILTER 1336 //! \details 1337 //! This field determines how texels are sampled/filtered when a texture is 1338 //! being "magnified" (enlarged). For volume maps, this filter mode 1339 //! selection also applies to the 3rd (inter-layer) dimension. 1340 enum MAG_MODE_FILTER 1341 { 1342 MAG_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1343 MAG_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1344 MAG_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1345 MAG_MODE_FILTER_MONO = 6, //!< Perform a monochrome convolution filter 1346 }; 1347 1348 //! \brief MIP_MODE_FILTER 1349 //! \details 1350 //! This field determines if and how mip map levels are chosen and/or 1351 //! combined when texture filtering. 1352 enum MIP_MODE_FILTER 1353 { 1354 MIP_MODE_FILTER_NONE = 0, //!< Disable mip mapping - force use of the mipmap level corresponding to Min LOD. 1355 MIP_MODE_FILTER_NEAREST = 1, //!< Nearest, Select the nearest mip map 1356 MIP_MODE_FILTER_LINEAR = 3, //!< Linearly interpolate between nearest mip maps (combined with linear min/mag filters this is analogous to "Trilinear" filtering). 1357 }; 1358 1359 //! \brief COARSE_LOD_QUALITY_MODE 1360 //! \details 1361 //! This field configures the coarse LOD image quality mode for the 1362 //! sample_d, sample_l, and sample_b messages in the sampling engine. In 1363 //! general, performance will increase and power consumption will decrease 1364 //! with each step of reduced quality (performance gain for sample_l and 1365 //! sample_b will be minimal). 1366 enum COARSE_LOD_QUALITY_MODE 1367 { 1368 COARSE_LOD_QUALITY_MODE_DISABLED = 0, //!< Full quality is enabled, matching prior products 1369 }; 1370 1371 //! \brief LOD_PRECLAMP_MODE 1372 //! \details 1373 //! <p>This field determines whether the computed LOD is clamped to 1374 //! [max,min] mip level 1375 //! before the mag-vs-min determination is performed.</p> 1376 enum LOD_PRECLAMP_MODE 1377 { 1378 LOD_PRECLAMP_MODE_NONE = 0, //!< LOD PreClamp disabled 1379 LOD_PRECLAMP_MODE_OGL = 2, //!< LOD PreClamp enabled (OGL mode) 1380 }; 1381 1382 //! \brief TEXTURE_BORDER_COLOR_MODE 1383 //! \details 1384 //! For some surface formats, the 32 bit border color is decoded differently 1385 //! based on the border color mode. In addition, the default value of 1386 //! channels not included in the surface may be affected by this field. 1387 //! Refer to the "Sampler Output Channel Mapping" table for the values of 1388 //! these channels, and for surface formats that may only support one of 1389 //! these modes. Also refer to the definition of SAMPLER_BORDER_COLOR_STATE 1390 //! for more details on the behavior of the two modes defined by this field. 1391 enum TEXTURE_BORDER_COLOR_MODE 1392 { 1393 TEXTURE_BORDER_COLOR_MODE_OGL = 0, //!< OGL mode for interpreting the border color 1394 TEXTURE_BORDER_COLOR_MODE_8BIT = 1, //!< Earlier mode for interpreting the border color as UNORM8. 1395 }; 1396 1397 //! \brief CUBE_SURFACE_CONTROL_MODE 1398 //! \details 1399 //! When sampling from a SURFTYPE_CUBE surface, this field controls whether 1400 //! the TC* Address Control Mode fields are interpreted as programmed or 1401 //! overridden to TEXCOORDMODE_CUBE. 1402 enum CUBE_SURFACE_CONTROL_MODE 1403 { 1404 CUBE_SURFACE_CONTROL_MODE_PROGRAMMED = 0, //!< No additional details 1405 CUBE_SURFACE_CONTROL_MODE_OVERRIDE = 1, //!< No additional details 1406 }; 1407 1408 //! \brief SHADOW_FUNCTION 1409 //! \details 1410 //! This field is used for shadow mapping support via the sample_c message 1411 //! type, and specifies the specific comparison operation to be used. The 1412 //! comparison is between the texture sample red channel (except for 1413 //! alpha-only formats which use the alpha channel), and the "ref" value 1414 //! provided in the input message. 1415 enum SHADOW_FUNCTION 1416 { 1417 SHADOW_FUNCTION_PREFILTEROPALWAYS = 0, //!< No additional details 1418 SHADOW_FUNCTION_PREFILTEROPNEVER = 1, //!< No additional details 1419 SHADOW_FUNCTION_PREFILTEROPLESS = 2, //!< No additional details 1420 SHADOW_FUNCTION_PREFILTEROPEQUAL = 3, //!< No additional details 1421 SHADOW_FUNCTION_PREFILTEROPLEQUAL = 4, //!< No additional details 1422 SHADOW_FUNCTION_PREFILTEROPGREATER = 5, //!< No additional details 1423 SHADOW_FUNCTION_PREFILTEROPNOTEQUAL = 6, //!< No additional details 1424 SHADOW_FUNCTION_PREFILTEROPGEQUAL = 7, //!< No additional details 1425 }; 1426 1427 //! \brief CHROMAKEY_MODE 1428 //! \details 1429 //! This field specifies the behavior of the device in the event of a 1430 //! ChromaKey match. This field is ignored if ChromaKey is disabled. 1431 enum CHROMAKEY_MODE 1432 { 1433 CHROMAKEY_MODE_KEYFILTERKILLONANYMATCH = 0, //!< In this mode, if any contributing texel matches the chroma key, the corresponding pixel mask bit for that pixel is cleared. The result of this operation is observable only if the Killed Pixel Mask Return flag is set on the input message. 1434 CHROMAKEY_MODE_KEYFILTERREPLACEBLACK = 1, //!< In this mode, each texel that matches the chroma key is replaced with (0,0,0,0) (black with alpha=0) prior to filtering. For YCrCb surface formats, the black value is A=0, R(Cr)=0x80, G(Y)=0x10, B(Cb)=0x80. This will tend to darken/fade edges of keyed regions. Note that the pixel pipeline must be programmed to use the resulting filtered texel value to gain the intended effect, e.g., handle the case of a totally keyed-out region (filtered texel alpha==0) through use of alpha test, etc. 1435 }; 1436 1437 //! \brief LOD_CLAMP_MAGNIFICATION_MODE 1438 //! \details 1439 //! This field allows the flexibility to control how LOD clamping is handled 1440 //! when in magnification mode. 1441 enum LOD_CLAMP_MAGNIFICATION_MODE 1442 { 1443 LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE = 0, //!< When in magnification mode, Sampler will clamp LOD as if the Mip Mode Filteris MIPFILTER_NONE. This is how OpenGL defines magnification, and therefore it isexpected that those drivers would not set this bit. 1444 LOD_CLAMP_MAGNIFICATION_MODE_MIPFILTER = 1, //!< When in magnification mode, Sampler will clamp LOD based on the value of Mip Mode Filter. 1445 }; 1446 1447 //! \brief TCZ_ADDRESS_CONTROL_MODE 1448 //! \details 1449 //! Controls how the 3rd (TCZ) component of input texture coordinates are 1450 //! mapped to texture map addresses - specifically, how coordinates 1451 //! "outside" the texture are handled (wrap/clamp/mirror).See Address TCX 1452 //! Control Mode above for details 1453 enum TCZ_ADDRESS_CONTROL_MODE 1454 { 1455 TCZ_ADDRESS_CONTROL_MODE_WRAP = 0, //!< No additional details 1456 TCZ_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< No additional details 1457 TCZ_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< No additional details 1458 TCZ_ADDRESS_CONTROL_MODE_CUBE = 3, //!< No additional details 1459 TCZ_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< No additional details 1460 TCZ_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< No additional details 1461 TCZ_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< No additional details 1462 }; 1463 1464 //! \brief TCY_ADDRESS_CONTROL_MODE 1465 //! \details 1466 //! Controls how the 2nd (TCY, aka V) component of input texture coordinates 1467 //! are mapped to texture map addresses - specifically, how coordinates 1468 //! "outside" the texture are handled (wrap/clamp/mirror). See Address TCX 1469 //! Control Mode above for details 1470 enum TCY_ADDRESS_CONTROL_MODE 1471 { 1472 TCY_ADDRESS_CONTROL_MODE_WRAP = 0, //!< No additional details 1473 TCY_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< No additional details 1474 TCY_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< No additional details 1475 TCY_ADDRESS_CONTROL_MODE_CUBE = 3, //!< No additional details 1476 TCY_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< No additional details 1477 TCY_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< No additional details 1478 TCY_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< No additional details 1479 }; 1480 1481 //! \brief TCX_ADDRESS_CONTROL_MODE 1482 //! \details 1483 //! Controls how the 1st (TCX, aka U) component of input texture coordinates 1484 //! are mapped to texture map addresses - specifically, how coordinates 1485 //! "outside" the texture are handled (wrap/clamp/mirror). The setting of 1486 //! this field is subject to being overridden by the Cube Surface Control 1487 //! Mode field when sampling from a SURFTYPE_CUBE surface. 1488 enum TCX_ADDRESS_CONTROL_MODE 1489 { 1490 TCX_ADDRESS_CONTROL_MODE_WRAP = 0, //!< No additional details 1491 TCX_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< No additional details 1492 TCX_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< No additional details 1493 TCX_ADDRESS_CONTROL_MODE_CUBE = 3, //!< No additional details 1494 TCX_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< No additional details 1495 TCX_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< No additional details 1496 TCX_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< No additional details 1497 }; 1498 1499 //! \brief TRILINEAR_FILTER_QUALITY 1500 //! \details 1501 //! Selects the quality level for the trilinear filter. 1502 enum TRILINEAR_FILTER_QUALITY 1503 { 1504 TRILINEAR_FILTER_QUALITY_FULL = 0, //!< Full Quality. Both mip maps are sampled under all circumstances. 1505 TRILINEAR_FILTER_QUALITY_TRIQUALHIGHMAGCLAMPMIPFILTER = 1, //!< High Quality. 1506 TRILINEAR_FILTER_QUALITY_MED = 2, //!< Medium Quality. 1507 TRILINEAR_FILTER_QUALITY_LOW = 3, //!< Low Quality. 1508 }; 1509 1510 //! \brief MAXIMUM_ANISOTROPY 1511 //! \details 1512 //! This field clamps the maximum value of the anisotropy ratio used by the 1513 //! MAPFILTER_ANISOTROPIC filter (Min or Mag Mode Filter). 1514 enum MAXIMUM_ANISOTROPY 1515 { 1516 MAXIMUM_ANISOTROPY_RATIO21 = 0, //!< At most a 2:1 aspect ratio filter is used 1517 MAXIMUM_ANISOTROPY_RATIO41 = 1, //!< At most a 4:1 aspect ratio filter is used 1518 MAXIMUM_ANISOTROPY_RATIO61 = 2, //!< At most a 6:1 aspect ratio filter is used 1519 MAXIMUM_ANISOTROPY_RATIO81 = 3, //!< At most a 8:1 aspect ratio filter is used 1520 MAXIMUM_ANISOTROPY_RATIO101 = 4, //!< At most a 10:1 aspect ratio filter is used 1521 MAXIMUM_ANISOTROPY_RATIO121 = 5, //!< At most a 12:1 aspect ratio filter is used 1522 MAXIMUM_ANISOTROPY_RATIO141 = 6, //!< At most a 14:1 aspect ratio filter is used 1523 MAXIMUM_ANISOTROPY_RATIO161 = 7, //!< At most a 16:1 aspect ratio filter is used 1524 }; 1525 1526 //! \brief REDUCTION_TYPE 1527 //! \details 1528 //! This field defines the type of reduction that will be performed on the 1529 //! texels in the footprint defined by the <b>Min/Mag/Mip Filter Mode</b> 1530 //! fields. This field is ignored if <b>Reduction Type Enable</b> is 1531 //! disabled. 1532 enum REDUCTION_TYPE 1533 { 1534 REDUCTION_TYPE_STDFILTER = 0, //!< standard filter 1535 REDUCTION_TYPE_COMPARISON = 1, //!< comparison followed by standard filter 1536 REDUCTION_TYPE_MINIMUM = 2, //!< minimum of footprint 1537 REDUCTION_TYPE_MAXIMUM = 3, //!< maximum of footprint 1538 }; 1539 1540 //! \name Initializations 1541 1542 //! \brief Explicit member initialization function 1543 SAMPLER_STATE_CMD(); 1544 1545 static const size_t dwSize = 4; 1546 static const size_t byteSize = 16; 1547 }; 1548 1549 //! 1550 //! \brief SAMPLER_STATE_8x8_AVS_COEFFICIENTS 1551 //! \details 1552 //! ExistsIf = AVS && (Function_mode = 0) 1553 //! 1554 struct SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD 1555 { 1556 union 1557 { 1558 //!< DWORD 0 1559 struct 1560 { 1561 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,0] 1562 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,0] 1563 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,1] 1564 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,1] 1565 }; 1566 uint32_t Value; 1567 } DW0; 1568 union 1569 { 1570 //!< DWORD 1 1571 struct 1572 { 1573 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,2] 1574 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,2] 1575 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,3] 1576 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,3] 1577 }; 1578 uint32_t Value; 1579 } DW1; 1580 union 1581 { 1582 //!< DWORD 2 1583 struct 1584 { 1585 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,4] 1586 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,4] 1587 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,5] 1588 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,5] 1589 }; 1590 uint32_t Value; 1591 } DW2; 1592 union 1593 { 1594 //!< DWORD 3 1595 struct 1596 { 1597 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,6] 1598 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,6] 1599 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,7] 1600 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,7] 1601 }; 1602 uint32_t Value; 1603 } DW3; 1604 union 1605 { 1606 //!< DWORD 4 1607 struct 1608 { 1609 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1610 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[n,2] 1611 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1X Filter Coefficient[n,3] 1612 }; 1613 uint32_t Value; 1614 } DW4; 1615 union 1616 { 1617 //!< DWORD 5 1618 struct 1619 { 1620 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[n,4] 1621 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1X Filter Coefficient[n,5] 1622 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1623 }; 1624 uint32_t Value; 1625 } DW5; 1626 union 1627 { 1628 //!< DWORD 6 1629 struct 1630 { 1631 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1632 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1Y Filter Coefficient[n,2] 1633 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[n,3] 1634 }; 1635 uint32_t Value; 1636 } DW6; 1637 union 1638 { 1639 //!< DWORD 7 1640 struct 1641 { 1642 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1Y Filter Coefficient[n,4] 1643 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[n,5] 1644 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1645 }; 1646 uint32_t Value; 1647 } DW7; 1648 1649 //! \name Local enumerations 1650 1651 //! \name Initializations 1652 1653 //! \brief Explicit member initialization function 1654 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD(); 1655 1656 static const size_t dwSize = 8; 1657 static const size_t byteSize = 32; 1658 }; 1659 1660 //! 1661 //! \brief SAMPLER_STATE_8x8_AVS 1662 //! \details 1663 //! ExistsIf = AVS && (Function_mode = 0) 1664 //! 1665 struct SAMPLER_STATE_8x8_AVS_CMD 1666 { 1667 union 1668 { 1669 //!< DWORD 0 1670 struct 1671 { 1672 uint32_t GainFactor : __CODEGEN_BITFIELD( 0, 5) ; //!< GAIN_FACTOR 1673 uint32_t WeakEdgeThreshold : __CODEGEN_BITFIELD( 6, 11) ; //!< WEAK_EDGE_THRESHOLD 1674 uint32_t StrongEdgeThreshold : __CODEGEN_BITFIELD(12, 17) ; //!< STRONG_EDGE_THRESHOLD 1675 uint32_t R3XCoefficient : __CODEGEN_BITFIELD(18, 22) ; //!< R3X_COEFFICIENT 1676 uint32_t R3CCoefficient : __CODEGEN_BITFIELD(23, 27) ; //!< R3C_COEFFICIENT 1677 uint32_t Reserved28 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1678 }; 1679 uint32_t Value; 1680 } DW0; 1681 union 1682 { 1683 //!< DWORD 1 1684 struct 1685 { 1686 uint32_t Reserved32 ; //!< Reserved 1687 }; 1688 uint32_t Value; 1689 } DW1; 1690 union 1691 { 1692 //!< DWORD 2 1693 struct 1694 { 1695 uint32_t GlobalNoiseEstimation : __CODEGEN_BITFIELD( 0, 7) ; //!< GLOBAL_NOISE_ESTIMATION 1696 uint32_t NonEdgeWeight : __CODEGEN_BITFIELD( 8, 10) ; //!< NON_EDGE_WEIGHT 1697 uint32_t RegularWeight : __CODEGEN_BITFIELD(11, 13) ; //!< REGULAR_WEIGHT 1698 uint32_t StrongEdgeWeight : __CODEGEN_BITFIELD(14, 16) ; //!< STRONG_EDGE_WEIGHT 1699 uint32_t R5XCoefficient : __CODEGEN_BITFIELD(17, 21) ; //!< R5X_COEFFICIENT 1700 uint32_t R5CxCoefficient : __CODEGEN_BITFIELD(22, 26) ; //!< R5CX_COEFFICIENT 1701 uint32_t R5CCoefficient : __CODEGEN_BITFIELD(27, 31) ; //!< R5C_COEFFICIENT 1702 }; 1703 uint32_t Value; 1704 } DW2; 1705 union 1706 { 1707 //!< DWORD 3 1708 struct 1709 { 1710 uint32_t SinAlpha : __CODEGEN_BITFIELD( 0, 7) ; //!< Sin(alpha) 1711 uint32_t CosAlpha : __CODEGEN_BITFIELD( 8, 15) ; //!< Cos(alpha) 1712 uint32_t SatMax : __CODEGEN_BITFIELD(16, 21) ; //!< SAT_MAX 1713 uint32_t HueMax : __CODEGEN_BITFIELD(22, 27) ; //!< HUE_MAX 1714 uint32_t Enable8TapFilter : __CODEGEN_BITFIELD(28, 29) ; //!< ENABLE_8_TAP_FILTER 1715 uint32_t Ief4SmoothEnable : __CODEGEN_BITFIELD(30, 30) ; //!< IEF4SMOOTH_ENABLE_ 1716 uint32_t SkinToneTunedIefEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SKIN_TONE_TUNED_IEF__ENABLE 1717 }; 1718 uint32_t Value; 1719 } DW3; 1720 union 1721 { 1722 //!< DWORD 4 1723 struct 1724 { 1725 uint32_t S3U : __CODEGEN_BITFIELD( 0, 10) ; //!< S3U 1726 uint32_t ShuffleOutputwritebackForSample8X8 : __CODEGEN_BITFIELD(11, 11) ; //!< SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 1727 uint32_t DiamondMargin : __CODEGEN_BITFIELD(12, 14) ; //!< DIAMOND_MARGIN 1728 uint32_t VyStdEnable : __CODEGEN_BITFIELD(15, 15) ; //!< VY_STD_Enable 1729 uint32_t UMid : __CODEGEN_BITFIELD(16, 23) ; //!< U_MID 1730 uint32_t VMid : __CODEGEN_BITFIELD(24, 31) ; //!< V_MID 1731 }; 1732 uint32_t Value; 1733 } DW4; 1734 union 1735 { 1736 //!< DWORD 5 1737 struct 1738 { 1739 uint32_t DiamondDv : __CODEGEN_BITFIELD( 0, 6) ; //!< DIAMOND_DV 1740 uint32_t DiamondTh : __CODEGEN_BITFIELD( 7, 12) ; //!< DIAMOND_TH 1741 uint32_t DiamondAlpha : __CODEGEN_BITFIELD(13, 20) ; //!< Diamond_alpha 1742 uint32_t HsMargin : __CODEGEN_BITFIELD(21, 23) ; //!< HS_MARGIN 1743 uint32_t DiamondDu : __CODEGEN_BITFIELD(24, 30) ; //!< DIAMOND_DU 1744 uint32_t Skindetailfactor : __CODEGEN_BITFIELD(31, 31) ; //!< SKINDETAILFACTOR_ 1745 }; 1746 uint32_t Value; 1747 } DW5; 1748 union 1749 { 1750 //!< DWORD 6 1751 struct 1752 { 1753 uint32_t YPoint1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y_POINT_1 1754 uint32_t YPoint2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y_POINT_2 1755 uint32_t YPoint3 : __CODEGEN_BITFIELD(16, 23) ; //!< Y_POINT_3 1756 uint32_t YPoint4 : __CODEGEN_BITFIELD(24, 31) ; //!< Y_POINT_4 1757 }; 1758 uint32_t Value; 1759 } DW6; 1760 union 1761 { 1762 //!< DWORD 7 1763 struct 1764 { 1765 uint32_t InvMarginVyl : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYL 1766 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1767 }; 1768 uint32_t Value; 1769 } DW7; 1770 union 1771 { 1772 //!< DWORD 8 1773 struct 1774 { 1775 uint32_t InvMarginVyu : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYU 1776 uint32_t P0L : __CODEGEN_BITFIELD(16, 23) ; //!< P0L 1777 uint32_t P1L : __CODEGEN_BITFIELD(24, 31) ; //!< P1L 1778 }; 1779 uint32_t Value; 1780 } DW8; 1781 union 1782 { 1783 //!< DWORD 9 1784 struct 1785 { 1786 uint32_t P2L : __CODEGEN_BITFIELD( 0, 7) ; //!< P2L 1787 uint32_t P3L : __CODEGEN_BITFIELD( 8, 15) ; //!< P3L 1788 uint32_t B0L : __CODEGEN_BITFIELD(16, 23) ; //!< B0L 1789 uint32_t B1L : __CODEGEN_BITFIELD(24, 31) ; //!< B1L 1790 }; 1791 uint32_t Value; 1792 } DW9; 1793 union 1794 { 1795 //!< DWORD 10 1796 struct 1797 { 1798 uint32_t B2L : __CODEGEN_BITFIELD( 0, 7) ; //!< B2L 1799 uint32_t B3L : __CODEGEN_BITFIELD( 8, 15) ; //!< B3L 1800 uint32_t S0L : __CODEGEN_BITFIELD(16, 26) ; //!< S0L 1801 uint32_t YSlope2 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope_2 1802 }; 1803 uint32_t Value; 1804 } DW10; 1805 union 1806 { 1807 //!< DWORD 11 1808 struct 1809 { 1810 uint32_t S1L : __CODEGEN_BITFIELD( 0, 10) ; //!< S1L 1811 uint32_t S2L : __CODEGEN_BITFIELD(11, 21) ; //!< S2L 1812 uint32_t Reserved374 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 1813 }; 1814 uint32_t Value; 1815 } DW11; 1816 union 1817 { 1818 //!< DWORD 12 1819 struct 1820 { 1821 uint32_t S3L : __CODEGEN_BITFIELD( 0, 10) ; //!< S3L 1822 uint32_t P0U : __CODEGEN_BITFIELD(11, 18) ; //!< P0U 1823 uint32_t P1U : __CODEGEN_BITFIELD(19, 26) ; //!< P1U 1824 uint32_t YSlope1 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope1 1825 }; 1826 uint32_t Value; 1827 } DW12; 1828 union 1829 { 1830 //!< DWORD 13 1831 struct 1832 { 1833 uint32_t P2U : __CODEGEN_BITFIELD( 0, 7) ; //!< P2U 1834 uint32_t P3U : __CODEGEN_BITFIELD( 8, 15) ; //!< P3U 1835 uint32_t B0U : __CODEGEN_BITFIELD(16, 23) ; //!< B0U 1836 uint32_t B1U : __CODEGEN_BITFIELD(24, 31) ; //!< B1U 1837 }; 1838 uint32_t Value; 1839 } DW13; 1840 union 1841 { 1842 //!< DWORD 14 1843 struct 1844 { 1845 uint32_t B2U : __CODEGEN_BITFIELD( 0, 7) ; //!< B2U 1846 uint32_t B3U : __CODEGEN_BITFIELD( 8, 15) ; //!< B3U 1847 uint32_t S0U : __CODEGEN_BITFIELD(16, 26) ; //!< S0U 1848 uint32_t Reserved475 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1849 }; 1850 uint32_t Value; 1851 } DW14; 1852 union 1853 { 1854 //!< DWORD 15 1855 struct 1856 { 1857 uint32_t S1U : __CODEGEN_BITFIELD( 0, 10) ; //!< S1U 1858 uint32_t S2U : __CODEGEN_BITFIELD(11, 21) ; //!< S2U 1859 uint32_t Reserved502 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 1860 }; 1861 uint32_t Value; 1862 } DW15; 1863 1864 mhw_state_heap_g9_X::SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient016[17]; //!< Filter Coefficient[0..16] 1865 1866 union 1867 { 1868 //!< DWORD 152 1869 struct 1870 { 1871 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 1872 uint32_t Reserved4867 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 1873 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 1874 uint32_t Reserved4871 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 1875 uint32_t MaxDerivative8Pixels : __CODEGEN_BITFIELD( 8, 15) ; //!< Max Derivative 8 Pixels 1876 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 1877 uint32_t DefaultSharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< DEFAULT_SHARPNESS_LEVEL 1878 }; 1879 uint32_t Value; 1880 } DW152; 1881 union 1882 { 1883 //!< DWORD 153 1884 struct 1885 { 1886 uint32_t RgbAdaptive : __CODEGEN_BITFIELD( 0, 0) ; //!< RGB_ADAPTIVE 1887 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1888 uint32_t Reserved4898 : __CODEGEN_BITFIELD( 2, 20) ; //!< Reserved 1889 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD(21, 21) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 1890 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD(22, 22) ; //!< BYPASS_X_ADAPTIVE_FILTERING 1891 uint32_t Reserved4919 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 1892 }; 1893 uint32_t Value; 1894 } DW153; 1895 1896 uint32_t Reserved4928[6]; //!< Reserved 1897 1898 mhw_state_heap_g9_X::SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient1731[15]; //!< Filter Coefficient[17..31] 1899 1900 //! \name Local enumerations 1901 1902 //! \brief GAIN_FACTOR 1903 //! \details 1904 //! User control sharpening strength 1905 enum GAIN_FACTOR 1906 { 1907 GAIN_FACTOR_UNNAMED44 = 44, //!< No additional details 1908 }; 1909 1910 //! \brief WEAK_EDGE_THRESHOLD 1911 //! \details 1912 //! If <b>Strong Edge Threshold</b> > EM > <b>Weak Edge Threshold</b>, 1913 //! the basic VSA detects a weak edge. 1914 enum WEAK_EDGE_THRESHOLD 1915 { 1916 WEAK_EDGE_THRESHOLD_UNNAMED1 = 1, //!< No additional details 1917 }; 1918 1919 //! \brief STRONG_EDGE_THRESHOLD 1920 //! \details 1921 //! If EM > <b>Strong Edge Threshold</b>, the basic VSA detects a strong 1922 //! edge. 1923 enum STRONG_EDGE_THRESHOLD 1924 { 1925 STRONG_EDGE_THRESHOLD_UNNAMED8 = 8, //!< No additional details 1926 }; 1927 1928 //! \brief R3X_COEFFICIENT 1929 //! \details 1930 //! IEF smoothing coefficient, see IEF map. 1931 enum R3X_COEFFICIENT 1932 { 1933 R3X_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 1934 }; 1935 1936 //! \brief R3C_COEFFICIENT 1937 //! \details 1938 //! IEF smoothing coefficient, see IEF map. 1939 enum R3C_COEFFICIENT 1940 { 1941 R3C_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 1942 }; 1943 1944 //! \brief GLOBAL_NOISE_ESTIMATION 1945 //! \details 1946 //! Global noise estimation of previous frame. 1947 enum GLOBAL_NOISE_ESTIMATION 1948 { 1949 GLOBAL_NOISE_ESTIMATION_UNNAMED255 = 255, //!< No additional details 1950 }; 1951 1952 //! \brief NON_EDGE_WEIGHT 1953 //! \details 1954 //! Sharpening strength when no edge is found in basic VSA. 1955 enum NON_EDGE_WEIGHT 1956 { 1957 NON_EDGE_WEIGHT_UNNAMED1 = 1, //!< No additional details 1958 }; 1959 1960 //! \brief REGULAR_WEIGHT 1961 //! \details 1962 //! Sharpening strength when a weak edge is found in basic VSA. 1963 enum REGULAR_WEIGHT 1964 { 1965 REGULAR_WEIGHT_UNNAMED2 = 2, //!< No additional details 1966 }; 1967 1968 //! \brief STRONG_EDGE_WEIGHT 1969 //! \details 1970 //! Sharpening strength when a strong edge is found in basic VSA. 1971 enum STRONG_EDGE_WEIGHT 1972 { 1973 STRONG_EDGE_WEIGHT_UNNAMED7 = 7, //!< No additional details 1974 }; 1975 1976 //! \brief R5X_COEFFICIENT 1977 //! \details 1978 //! IEF smoothing coefficient, see IEF map. 1979 enum R5X_COEFFICIENT 1980 { 1981 R5X_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 1982 }; 1983 1984 //! \brief R5CX_COEFFICIENT 1985 //! \details 1986 //! IEF smoothing coefficient, see IEF map. 1987 enum R5CX_COEFFICIENT 1988 { 1989 R5CX_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 1990 }; 1991 1992 //! \brief R5C_COEFFICIENT 1993 //! \details 1994 //! IEF smoothing coefficient, see IEF map. 1995 enum R5C_COEFFICIENT 1996 { 1997 R5C_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 1998 }; 1999 2000 //! \brief SAT_MAX 2001 //! \details 2002 //! Rectangle half length 2003 enum SAT_MAX 2004 { 2005 SAT_MAX_UNNAMED31 = 31, //!< No additional details 2006 }; 2007 2008 //! \brief HUE_MAX 2009 //! \details 2010 //! Rectangle half width. 2011 enum HUE_MAX 2012 { 2013 HUE_MAX_UNNAMED14 = 14, //!< No additional details 2014 }; 2015 2016 //! \brief ENABLE_8_TAP_FILTER 2017 //! \details 2018 //! <i><b>Adaptive Filtering (Mode = 11) ExistsIf:</b></i> 2019 //! <p></p> R10G10B10A2_UNORM R8G8B8A8_UNORM (AYUV also) R8B8G8A8_UNORM 2020 //! B8G8R8A8_UNORM R16G16B16A16 2021 enum ENABLE_8_TAP_FILTER 2022 { 2023 ENABLE_8_TAP_FILTER_UNNAMED0 = 0, //!< 4-tap filter is only done on all channels. 2024 ENABLE_8_TAP_FILTER_UNNAMED1 = 1, //!< Enable 8-tap Adaptive filter on G-channel. 4-tap filter on other channels. 2025 ENABLE_8_TAP_FILTER_UNNAMED2 = 2, //!< 8-tap filter is done on all channels (UV-ch uses the Y-coefficients) 2026 ENABLE_8_TAP_FILTER_UNNAMED3 = 3, //!< Enable 8-tap Adaptive filter all channels (UV-ch uses the Y-coefficients). 2027 }; 2028 2029 enum IEF4SMOOTH_ENABLE_ 2030 { 2031 IEF4SMOOTH_ENABLE_UNNAMED0 = 0, //!< IEF is operating as a content adaptive detail filter based on 5x5 region 2032 IEF4SMOOTH_ENABLE_UNNAMED1 = 1, //!< IEF is operating as a content adaptive smooth filter based on 3x3 region 2033 }; 2034 2035 //! \brief SKIN_TONE_TUNED_IEF__ENABLE 2036 //! \details 2037 //! Control bit to enable the skin tone tuned IEF. 2038 enum SKIN_TONE_TUNED_IEF__ENABLE 2039 { 2040 SKIN_TONE_TUNED_IEF_ENABLE_UNNAMED1 = 1, //!< No additional details 2041 }; 2042 2043 enum SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 2044 { 2045 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED0 = 0, //!< Writeback same as Original Sample_8x8 2046 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED1 = 1, //!< Writeback of Sample_8x8 Is Modified to Suite Sample_Unorm 2047 }; 2048 2049 enum DIAMOND_MARGIN 2050 { 2051 DIAMOND_MARGIN_UNNAMED4 = 4, //!< No additional details 2052 }; 2053 2054 //! \brief U_MID 2055 //! \details 2056 //! Rectangle middle-point U coordinate. 2057 enum U_MID 2058 { 2059 U_MID_UNNAMED110 = 110, //!< No additional details 2060 }; 2061 2062 //! \brief V_MID 2063 //! \details 2064 //! Rectangle middle-point V coordinate. 2065 enum V_MID 2066 { 2067 V_MID_UNNAMED154 = 154, //!< No additional details 2068 }; 2069 2070 //! \brief DIAMOND_DV 2071 //! \details 2072 //! Rhombus center shift in the hue-direction, relative to the rectangle 2073 //! center. 2074 enum DIAMOND_DV 2075 { 2076 DIAMOND_DV_UNNAMED0 = 0, //!< No additional details 2077 }; 2078 2079 //! \brief DIAMOND_TH 2080 //! \details 2081 //! Half length of the rhombus axis in the sat-direction. 2082 enum DIAMOND_TH 2083 { 2084 DIAMOND_TH_UNNAMED35 = 35, //!< No additional details 2085 }; 2086 2087 //! \brief HS_MARGIN 2088 //! \details 2089 //! Defines rectangle margin 2090 enum HS_MARGIN 2091 { 2092 HS_MARGIN_UNNAMED3 = 3, //!< No additional details 2093 }; 2094 2095 //! \brief DIAMOND_DU 2096 //! \details 2097 //! Rhombus center shift in the sat-direction, relative to the rectangle 2098 //! center. 2099 enum DIAMOND_DU 2100 { 2101 DIAMOND_DU_UNNAMED2 = 2, //!< No additional details 2102 }; 2103 2104 //! \brief SKINDETAILFACTOR_ 2105 //! \details 2106 //! This flag bit is in operation only when the control bit <b>Skin Tone 2107 //! TunedIEF_Enable</b> is on. 2108 enum SKINDETAILFACTOR_ 2109 { 2110 SKINDETAILFACTOR_UNNAMED0 = 0, //!< sign(SkinDetailFactor) is equal to -1, and the content of the detected skin tone area is detail revealed. 2111 SKINDETAILFACTOR_UNNAMED1 = 1, //!< sign(SkinDetailFactor) is equal to +1, and the content of the detected skin tone area is not detail revealed. 2112 }; 2113 2114 //! \brief Y_POINT_1 2115 //! \details 2116 //! First point of the Y piecewise linear membership function. 2117 enum Y_POINT_1 2118 { 2119 Y_POINT_1_UNNAMED46 = 46, //!< No additional details 2120 }; 2121 2122 //! \brief Y_POINT_2 2123 //! \details 2124 //! Second point of the Y piecewise linear membership function. 2125 enum Y_POINT_2 2126 { 2127 Y_POINT_2_UNNAMED47 = 47, //!< No additional details 2128 }; 2129 2130 //! \brief Y_POINT_3 2131 //! \details 2132 //! Third point of the Y piecewise linear membership function. 2133 enum Y_POINT_3 2134 { 2135 Y_POINT_3_UNNAMED254 = 254, //!< No additional details 2136 }; 2137 2138 //! \brief Y_POINT_4 2139 //! \details 2140 //! Fourth point of the Y piecewise linear membership function. 2141 enum Y_POINT_4 2142 { 2143 Y_POINT_4_UNNAMED255 = 255, //!< No additional details 2144 }; 2145 2146 //! \brief P0L 2147 //! \details 2148 //! Y Point 0 of the lower part of the detection PWLF. 2149 enum P0L 2150 { 2151 P0L_UNNAMED46 = 46, //!< No additional details 2152 }; 2153 2154 //! \brief P1L 2155 //! \details 2156 //! Y Point 1 of the lower part of the detection PWLF. 2157 enum P1L 2158 { 2159 P1L_UNNAMED216 = 216, //!< No additional details 2160 }; 2161 2162 //! \brief P2L 2163 //! \details 2164 //! Y Point 2 of the lower part of the detection PWLF. 2165 enum P2L 2166 { 2167 P2L_UNNAMED236 = 236, //!< No additional details 2168 }; 2169 2170 //! \brief P3L 2171 //! \details 2172 //! Y Point 3 of the lower part of the detection PWLF. 2173 enum P3L 2174 { 2175 P3L_UNNAMED236 = 236, //!< No additional details 2176 }; 2177 2178 //! \brief B0L 2179 //! \details 2180 //! V Bias 0 of the lower part of the detection PWLF. 2181 enum B0L 2182 { 2183 B0L_UNNAMED133 = 133, //!< No additional details 2184 }; 2185 2186 //! \brief B1L 2187 //! \details 2188 //! V Bias 1 of the lower part of the detection PWLF. 2189 enum B1L 2190 { 2191 B1L_UNNAMED130 = 130, //!< No additional details 2192 }; 2193 2194 enum B2L 2195 { 2196 B2L_UNNAMED130 = 130, //!< No additional details 2197 }; 2198 2199 //! \brief B3L 2200 //! \details 2201 //! V Bias 3 of the lower part of the detection PWLF. 2202 enum B3L 2203 { 2204 B3L_UNNAMED130 = 130, //!< No additional details 2205 }; 2206 2207 //! \brief P0U 2208 //! \details 2209 //! Y Point 0 of the upper part of the detection PWLF. 2210 enum P0U 2211 { 2212 P0U_UNNAMED46 = 46, //!< No additional details 2213 }; 2214 2215 //! \brief P1U 2216 //! \details 2217 //! Y Point 1 of the upper part of the detection PWLF. 2218 enum P1U 2219 { 2220 P1U_UNNAMED66 = 66, //!< No additional details 2221 }; 2222 2223 //! \brief P2U 2224 //! \details 2225 //! Y Point 2 of the upper part of the detection PWLF. 2226 enum P2U 2227 { 2228 P2U_UNNAMED150 = 150, //!< No additional details 2229 }; 2230 2231 //! \brief P3U 2232 //! \details 2233 //! Y Point 3 of the upper part of the detection PWLF. 2234 enum P3U 2235 { 2236 P3U_UNNAMED236 = 236, //!< No additional details 2237 }; 2238 2239 //! \brief B0U 2240 //! \details 2241 //! V Bias 0 of the upper part of the detection PWLF. 2242 enum B0U 2243 { 2244 B0U_UNNAMED143 = 143, //!< No additional details 2245 }; 2246 2247 //! \brief B1U 2248 //! \details 2249 //! V Bias 1 of the upper part of the detection PWLF. 2250 enum B1U 2251 { 2252 B1U_UNNAMED163 = 163, //!< No additional details 2253 }; 2254 2255 //! \brief B2U 2256 //! \details 2257 //! V Bias 2 of the upper part of the detection PWLF. 2258 enum B2U 2259 { 2260 B2U_UNNAMED200 = 200, //!< No additional details 2261 }; 2262 2263 //! \brief B3U 2264 //! \details 2265 //! V Bias 3 of the upper part of the detection PWLF. 2266 enum B3U 2267 { 2268 B3U_UNNAMED140 = 140, //!< No additional details 2269 }; 2270 2271 //! \brief DEFAULT_SHARPNESS_LEVEL 2272 //! \details 2273 //! When adaptive scaling is off, determines the balance between sharp and 2274 //! smooth scalers. 2275 enum DEFAULT_SHARPNESS_LEVEL 2276 { 2277 DEFAULT_SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 2278 DEFAULT_SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 2279 }; 2280 2281 //! \brief RGB_ADAPTIVE 2282 //! \details 2283 //! This should be always set to 0 for YUV input and can be enabled/disabled 2284 //! for RGB input. 2285 //! This should be enabled only if we enable 8-tap adaptive filter for 2286 //! RGB input. 2287 enum RGB_ADAPTIVE 2288 { 2289 RGB_ADAPTIVE_DISBLE = 0, //!< Disable the RGB Adaptive equation and use G-Ch directly for adaptive filter 2290 RGB_ADAPTIVE_ENABLE = 1, //!< Enable the RGB Adaptive filter using the equation (Y=(R+2G+B)>>2) 2291 }; 2292 2293 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2294 //! \details 2295 //! Only to be enabled if 8-tap Adaptive filter mode is on, eElse it should 2296 //! be disabled. 2297 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2298 { 2299 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISBLE = 0, //!< Disable Adaptive Filter on UV/RB Channels 2300 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLE = 1, //!< Enable Adaptive Filter on UV/RB Channels 2301 }; 2302 2303 //! \brief BYPASS_Y_ADAPTIVE_FILTERING 2304 //! \details 2305 //! When disabled, the Y direction will use <b>Default Sharpness Level</b> 2306 //! to blend between the smooth and sharp filters rather than the calculated 2307 //! value. 2308 enum BYPASS_Y_ADAPTIVE_FILTERING 2309 { 2310 BYPASS_Y_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable Y Adaptive Filtering 2311 BYPASS_Y_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable Y Adaptive Filtering 2312 }; 2313 2314 //! \brief BYPASS_X_ADAPTIVE_FILTERING 2315 //! \details 2316 //! When disabled, the X direction will use <b>Default Sharpness Level</b> 2317 //! to blend between the smooth and sharp filters rather than the calculated 2318 //! value. 2319 enum BYPASS_X_ADAPTIVE_FILTERING 2320 { 2321 BYPASS_X_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable X Adaptive Filtering 2322 BYPASS_X_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable X Adaptive Filtering 2323 }; 2324 2325 //! \name Initializations 2326 2327 //! \brief Explicit member initialization function 2328 SAMPLER_STATE_8x8_AVS_CMD(); 2329 2330 static const size_t dwSize = 280; 2331 static const size_t byteSize = 1120; 2332 }; 2333 2334 //! 2335 //! \brief SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS 2336 //! \details 2337 //! Function: 0001b ExistsIf: [Convolve] && [SKL_mode==0] && 2338 //! [(Kernel Size) =< (15x15)] 2339 //! 2340 //! Function: 1010b ExistsIf: "[1Pixel Convolution ] && [(Kernel 2341 //! Size) =< (15x15)] 2342 //! 2343 //! Function: 0001b ExistsIf: [Convolve] && [SKL_mode==1] && 2344 //! [(Kernel Size) > (15x15)] 2345 //! 2346 struct SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS_CMD 2347 { 2348 union 2349 { 2350 //!< DWORD 0 2351 struct 2352 { 2353 uint32_t FilterCoefficient00 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,0] 2354 uint32_t FilterCoefficient01 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,1] 2355 }; 2356 uint32_t Value; 2357 } DW0; 2358 union 2359 { 2360 //!< DWORD 1 2361 struct 2362 { 2363 uint32_t FilterCoefficient02 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,2] 2364 uint32_t FilterCoefficient03 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,3] 2365 }; 2366 uint32_t Value; 2367 } DW1; 2368 union 2369 { 2370 //!< DWORD 2 2371 struct 2372 { 2373 uint32_t FilterCoefficient04 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,4] 2374 uint32_t FilterCoefficient05 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,5] 2375 }; 2376 uint32_t Value; 2377 } DW2; 2378 union 2379 { 2380 //!< DWORD 3 2381 struct 2382 { 2383 uint32_t FilterCoefficient06 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,6] 2384 uint32_t FilterCoefficient07 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,7] 2385 }; 2386 uint32_t Value; 2387 } DW3; 2388 union 2389 { 2390 //!< DWORD 4 2391 struct 2392 { 2393 uint32_t FilterCoefficient08 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,8] 2394 uint32_t FilterCoefficient09 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,9] 2395 }; 2396 uint32_t Value; 2397 } DW4; 2398 union 2399 { 2400 //!< DWORD 5 2401 struct 2402 { 2403 uint32_t FilterCoefficient010 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,10] 2404 uint32_t FilterCoefficient011 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,11] 2405 }; 2406 uint32_t Value; 2407 } DW5; 2408 union 2409 { 2410 //!< DWORD 6 2411 struct 2412 { 2413 uint32_t FilterCoefficient012 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,12] 2414 uint32_t FilterCoefficient013 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,13] 2415 }; 2416 uint32_t Value; 2417 } DW6; 2418 union 2419 { 2420 //!< DWORD 7 2421 struct 2422 { 2423 uint32_t FilterCoefficient014 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,14] 2424 uint32_t FilterCoefficient015 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,15] 2425 }; 2426 uint32_t Value; 2427 } DW7; 2428 2429 //! \name Local enumerations 2430 2431 //! \name Initializations 2432 2433 //! \brief Explicit member initialization function 2434 SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS_CMD(); 2435 2436 static const size_t dwSize = 8; 2437 static const size_t byteSize = 32; 2438 }; 2439 2440 //! 2441 //! \brief SAMPLER_STATE_8x8_CONVOLVE 2442 //! \details 2443 //! Function: 0001b ExistsIf: [Convolve] && [SKL_mode==0] && 2444 //! [(Kernel Size) =< (15x15)] 2445 //! 2446 //! Function: 1010b ExistsIf: "[1Pixel Convolution ] && [(Kernel 2447 //! Size) =< (15x15)] 2448 //! 2449 //! Function: 0001b ExistsIf: [Convolve] && [SKL_mode==1] && 2450 //! [(Kernel Size) > (15x15)] 2451 //! 2452 struct SAMPLER_STATE_8x8_CONVOLVE_CMD 2453 { 2454 union 2455 { 2456 //!< DWORD 0 2457 struct 2458 { 2459 uint32_t Height : __CODEGEN_BITFIELD( 0, 3) ; //!< HEIGHT 2460 uint32_t Width : __CODEGEN_BITFIELD( 4, 7) ; //!< WIDTH 2461 uint32_t ScaleDownValue : __CODEGEN_BITFIELD( 8, 11) ; //!< Scale down value 2462 uint32_t SizeOfTheCoefficient : __CODEGEN_BITFIELD(12, 12) ; //!< SIZE_OF_THE_COEFFICIENT 2463 uint32_t Reserved13 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 2464 uint32_t MsbHeight : __CODEGEN_BITFIELD(16, 16) ; //!< MSB_HEIGHT 2465 uint32_t Reserved17 : __CODEGEN_BITFIELD(17, 19) ; //!< Reserved 2466 uint32_t MsbWidth : __CODEGEN_BITFIELD(20, 20) ; //!< MSB_WIDTH 2467 uint32_t Reserved21 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 2468 }; 2469 uint32_t Value; 2470 } DW0; 2471 2472 uint32_t Reserved32[15]; //!< Reserved 2473 2474 mhw_state_heap_g9_X::SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS_CMD FilterCoefficient300310[62]; //!< Filter Coefficient[30:0,31:0] 2475 2476 //! \name Local enumerations 2477 2478 enum SIZE_OF_THE_COEFFICIENT 2479 { 2480 SIZE_OF_THE_COEFFICIENT_8BIT = 0, //!< The lower 8 bits of the accumulator is forced to zero or ignored during the accumulation operation. 2481 SIZE_OF_THE_COEFFICIENT_16BIT = 1, //!< The lower 8 bits are also included for the operation. The final result of the accumulator is shifted before clamping the result as specified by the Scale down value.:Result[15:0] = Clamp(Accum[40:12] >> scale_down) 2482 }; 2483 2484 //! \brief MSB_HEIGHT 2485 //! \details 2486 //! It contains the MSB HEIGHT of the kernel and is used to extend the 2487 //! kernel width range to 31. 2488 //! Used along with bits[3:0] which represents the LSB for the kernel 2489 //! Height. 2490 enum MSB_HEIGHT 2491 { 2492 MSB_HEIGHT_NOCHANGE = 0, //!< No Change to the Filter Size 2493 MSB_HEIGHT_EXTENDED = 1, //!< Extends the filter size height upto 31. 2494 }; 2495 2496 //! \brief MSB_WIDTH 2497 //! \details 2498 //! It contains the MSB Width of the kernel and is used to extend the kernel 2499 //! width range to 31. 2500 //! Used along with bits[3:0] which represents the LSB for the kernel 2501 //! Height. 2502 enum MSB_WIDTH 2503 { 2504 MSB_WIDTH_NOCHANGE = 0, //!< No Change to the Filter Size 2505 MSB_WIDTH_EXTENDED = 1, //!< Extends the Filter Size Width upto 31. 2506 }; 2507 2508 //! \name Initializations 2509 2510 //! \brief Explicit member initialization function 2511 SAMPLER_STATE_8x8_CONVOLVE_CMD(); 2512 2513 static const size_t dwSize = 512; 2514 static const size_t byteSize = 2048; 2515 }; 2516 2517 //! 2518 //! \brief SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER 2519 //! \details 2520 //! The table is valid for the following funstions: 0100 - Erode && 2521 //! (Function_mode==0) 0101 - Dilate && (Function_mode==0) 0011 - 2522 //! MinMaxFilter && (Function_mode==0) 2523 //! 2524 //! Max kernel size is 15x15. For sizes less than 15x15 the coefficients not 2525 //! used should be zeroed out. 2526 //! 2527 struct SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER_CMD 2528 { 2529 union 2530 { 2531 //!< DWORD 0 2532 struct 2533 { 2534 uint32_t HeightOfTheKernel : __CODEGEN_BITFIELD( 0, 3) ; //!< Height Of The Kernel 2535 uint32_t WidthOfTheKernel : __CODEGEN_BITFIELD( 4, 7) ; //!< Width Of The Kernel 2536 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 2537 uint32_t BitMask16ForRow0150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row0 [15:0] 2538 }; 2539 uint32_t Value; 2540 } DW0; 2541 union 2542 { 2543 //!< DWORD 1 2544 struct 2545 { 2546 uint32_t BitMask16ForRow1150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row1 [15:0] 2547 uint32_t BitMask16ForRow2150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row2 [15:0] 2548 }; 2549 uint32_t Value; 2550 } DW1; 2551 union 2552 { 2553 //!< DWORD 2 2554 struct 2555 { 2556 uint32_t BitMask16ForRow3150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row3 [15:0] 2557 uint32_t BitMask16ForRow4150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row4 [15:0] 2558 }; 2559 uint32_t Value; 2560 } DW2; 2561 union 2562 { 2563 //!< DWORD 3 2564 struct 2565 { 2566 uint32_t BitMask16ForRow5150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row5 [15:0] 2567 uint32_t BitMask16ForRow6150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row6 [15:0] 2568 }; 2569 uint32_t Value; 2570 } DW3; 2571 union 2572 { 2573 //!< DWORD 4 2574 struct 2575 { 2576 uint32_t BitMask16ForRow7150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row7 [15:0] 2577 uint32_t BitMask16ForRow8150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row8 [15:0] 2578 }; 2579 uint32_t Value; 2580 } DW4; 2581 union 2582 { 2583 //!< DWORD 5 2584 struct 2585 { 2586 uint32_t BitMask16ForRow9150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row9 [15:0] 2587 uint32_t BitMask16ForRow10150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row10 [15:0] 2588 }; 2589 uint32_t Value; 2590 } DW5; 2591 union 2592 { 2593 //!< DWORD 6 2594 struct 2595 { 2596 uint32_t BitMask16ForRow11150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row11 [15:0] 2597 uint32_t BitMask16ForRow12150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row12 [15:0] 2598 }; 2599 uint32_t Value; 2600 } DW6; 2601 union 2602 { 2603 //!< DWORD 7 2604 struct 2605 { 2606 uint32_t BitMask16ForRow13150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row13 [15:0] 2607 uint32_t BitMask16ForRow14150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row14 [15:0] 2608 }; 2609 uint32_t Value; 2610 } DW7; 2611 2612 //! \name Local enumerations 2613 2614 //! \name Initializations 2615 2616 //! \brief Explicit member initialization function 2617 SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER_CMD(); 2618 2619 static const size_t dwSize = 8; 2620 static const size_t byteSize = 32; 2621 }; 2622 2623 //! 2624 //! \brief SAMPLER_INDIRECT_STATE 2625 //! \details 2626 //! Note: There are three variations of this structure, defined separately 2627 //! because their payloads have different lengths. Currently only 2628 //! SAMPLER_INDIRECT_STATE_BORDER_COLOR is fully defined. 2629 //! This structure is pointed to by Indirect State Pointer (SAMPLER_STATE). 2630 //! The interpretation of the border color depends on the Texture Border 2631 //! Color Mode field in SAMPLER_STATE as follows: 2632 //! 2633 //! In 8BIT mode, the border color is 8-bit UNORM format, regardless of the 2634 //! surface format chosen. For surface formats with one or more channels 2635 //! missing (i.e. R5G6R5_UNORM is missing the alpha channel), the value from 2636 //! the border color, if selected, will be used even for the missing 2637 //! channels. 2638 //! 2639 //! In OGL mode, the format of the border color is R32G32B32A32_FLOAT, 2640 //! R32G32B32A32_SINT, or R32G32B32A32_UINT, depending on the surface format 2641 //! chosen. For surface formats with one or more channels missing, the value 2642 //! from the border color is not used for the missing channels, resulting in 2643 //! these channels resulting in the overall default value (0 for colors and 2644 //! 1 for alpha) regardless of whether border color is chosen. The surface 2645 //! formats with "L" and "I" have special behavior with respect to the 2646 //! border color. The border color value used for the replicated channels 2647 //! (RGB for "L" formats and RGBA for "I" formats) comes from the red 2648 //! channel of border color. In these cases, the green and blue channels, 2649 //! and also alpha for "I", of the border color are ignored. 2650 //! 2651 //! 2652 //! 2653 //! 2654 //! 2655 //! The format of this state depends on the Texture Border Color Mode field. 2656 //! 2657 //! 8BIT mode is not supported for surfaces with more than 16 bits in any 2658 //! channel, other than 32-bit float formats which are supported. 2659 //! The conditions under which this color is used depend on the Surface 2660 //! Type - 1D/2D/3D surfaces use the border color when the coordinates 2661 //! extend beyond the surface extent; cube surfaces use the border color for 2662 //! "empty" (disabled) faces. 2663 //! The border color itself is accessed through the texture cache hierarchy 2664 //! rather than the state cache hierarchy. Thus, if the border color is 2665 //! changed in memory, the texture cache must be invalidated and the state 2666 //! cache does not need to be invalidated. 2667 //! MAPFILTER_MONO: The border color is ignored. Border color is fixed at 2668 //! a value of 0 by hardware. 2669 //! 2670 //! 2671 struct SAMPLER_INDIRECT_STATE_CMD 2672 { 2673 union 2674 { 2675 //!< DWORD 0 2676 struct 2677 { 2678 uint32_t BorderColorRed ; //!< Border Color Red, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2679 } Obj0; 2680 struct 2681 { 2682 uint32_t BorderColorRed : __CODEGEN_BITFIELD( 0, 7) ; //!< Border Color Red, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2683 uint32_t BorderColorGreen : __CODEGEN_BITFIELD( 8, 15) ; //!< Border Color Green, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2684 uint32_t BorderColorBlue : __CODEGEN_BITFIELD(16, 23) ; //!< Border Color Blue, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2685 uint32_t BorderColorAlpha : __CODEGEN_BITFIELD(24, 31) ; //!< Border Color Alpha, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2686 } Obj1; 2687 uint32_t Value; 2688 } DW0; 2689 union 2690 { 2691 //!< DWORD 1 2692 struct 2693 { 2694 uint32_t BorderColorGreen ; //!< Border Color Green, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2695 }; 2696 uint32_t Value; 2697 } DW1; 2698 union 2699 { 2700 //!< DWORD 2 2701 struct 2702 { 2703 uint32_t BorderColorBlue ; //!< Border Color Blue, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2704 }; 2705 uint32_t Value; 2706 } DW2; 2707 union 2708 { 2709 //!< DWORD 3 2710 struct 2711 { 2712 uint32_t BorderColorAlpha ; //!< Border Color Alpha, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2713 }; 2714 uint32_t Value; 2715 } DW3; 2716 2717 uint32_t Reserved128[12]; //!< Reserved 2718 2719 //! \name Local enumerations 2720 2721 //! \name Initializations 2722 2723 //! \brief Explicit member initialization function 2724 SAMPLER_INDIRECT_STATE_CMD(); 2725 2726 static const size_t dwSize = 16; 2727 static const size_t byteSize = 64; 2728 }; 2729 2730 }; 2731 2732 #pragma pack() 2733 2734 #endif // __MHW_STATE_HEAP_HWCMD_G9_X_H__ 2735