1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_state_heap_hwcmd_g8_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g8_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_STATE_HEAP_HWCMD_G8_X_H__ 29 #define __MHW_STATE_HEAP_HWCMD_G8_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_state_heap_g8_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief INTERFACE_DESCRIPTOR_DATA 50 //! \details 51 //! 52 //! 53 struct INTERFACE_DESCRIPTOR_DATA_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 61 uint32_t KernelStartPointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Kernel Start Pointer 62 }; 63 uint32_t Value; 64 } DW0; 65 union 66 { 67 //!< DWORD 1 68 struct 69 { 70 uint32_t KernelStartPointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Kernel Start Pointer High 71 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 72 }; 73 uint32_t Value; 74 } DW1; 75 union 76 { 77 //!< DWORD 2 78 struct 79 { 80 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 81 uint32_t SoftwareExceptionEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Software Exception Enable 82 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 10) ; //!< Reserved 83 uint32_t MaskStackExceptionEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Mask Stack Exception Enable 84 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 12) ; //!< Reserved 85 uint32_t IllegalOpcodeExceptionEnable : __CODEGEN_BITFIELD(13, 13) ; //!< Illegal Opcode Exception Enable 86 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 87 uint32_t FloatingPointMode : __CODEGEN_BITFIELD(16, 16) ; //!< FLOATING_POINT_MODE 88 uint32_t ThreadPriority : __CODEGEN_BITFIELD(17, 17) ; //!< THREAD_PRIORITY 89 uint32_t SingleProgramFlow : __CODEGEN_BITFIELD(18, 18) ; //!< SINGLE_PROGRAM_FLOW 90 uint32_t DenormMode : __CODEGEN_BITFIELD(19, 19) ; //!< DENORM_MODE 91 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 31) ; //!< Reserved 92 }; 93 uint32_t Value; 94 } DW2; 95 union 96 { 97 //!< DWORD 3 98 struct 99 { 100 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 101 uint32_t SamplerCount : __CODEGEN_BITFIELD( 2, 4) ; //!< SAMPLER_COUNT 102 uint32_t SamplerStatePointer : __CODEGEN_BITFIELD( 5, 31) ; //!< Sampler State Pointer 103 }; 104 uint32_t Value; 105 } DW3; 106 union 107 { 108 //!< DWORD 4 109 struct 110 { 111 uint32_t BindingTableEntryCount : __CODEGEN_BITFIELD( 0, 4) ; //!< Binding Table Entry Count 112 uint32_t BindingTablePointer : __CODEGEN_BITFIELD( 5, 15) ; //!< Binding Table Pointer 113 uint32_t Reserved144 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 114 }; 115 uint32_t Value; 116 } DW4; 117 union 118 { 119 //!< DWORD 5 120 struct 121 { 122 uint32_t ConstantUrbEntryReadOffset : __CODEGEN_BITFIELD( 0, 15) ; //!< Constant URB Entry Read Offset 123 uint32_t ConstantIndirectUrbEntryReadLength : __CODEGEN_BITFIELD(16, 31) ; //!< Constant/Indirect URB Entry Read Length 124 }; 125 uint32_t Value; 126 } DW5; 127 union 128 { 129 //!< DWORD 6 130 struct 131 { 132 uint32_t NumberOfThreadsInGpgpuThreadGroup : __CODEGEN_BITFIELD( 0, 9) ; //!< Number of Threads in GPGPU Thread Group 133 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 134 uint32_t SharedLocalMemorySize : __CODEGEN_BITFIELD(16, 20) ; //!< SHARED_LOCAL_MEMORY_SIZE 135 uint32_t BarrierEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Barrier Enable 136 uint32_t RoundingMode : __CODEGEN_BITFIELD(22, 23) ; //!< ROUNDING_MODE 137 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 138 }; 139 uint32_t Value; 140 } DW6; 141 union 142 { 143 //!< DWORD 7 144 struct 145 { 146 uint32_t CrossThreadConstantDataReadLength : __CODEGEN_BITFIELD( 0, 7) ; //!< Cross-Thread Constant Data Read Length 147 uint32_t Reserved232 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 148 }; 149 uint32_t Value; 150 } DW7; 151 152 //! \name Local enumerations 153 154 //! \brief FLOATING_POINT_MODE 155 //! \details 156 //! Specifies the floating point mode used by the dispatched thread. 157 enum FLOATING_POINT_MODE 158 { 159 FLOATING_POINT_MODE_IEEE_754 = 0, //!< No additional details 160 FLOATING_POINT_MODE_ALTERNATE = 1, //!< No additional details 161 }; 162 163 //! \brief THREAD_PRIORITY 164 //! \details 165 //! Specifies the priority of the thread for dispatch. 166 enum THREAD_PRIORITY 167 { 168 THREAD_PRIORITY_NORMALPRIORITY = 0, //!< No additional details 169 THREAD_PRIORITY_HIGHPRIORITY = 1, //!< No additional details 170 }; 171 172 //! \brief SINGLE_PROGRAM_FLOW 173 //! \details 174 //! Specifies whether the kernel program has a single program flow (SIMDnxm 175 //! with m = 1) or multiple program flows (SIMDnxm with m > 1). 176 enum SINGLE_PROGRAM_FLOW 177 { 178 SINGLE_PROGRAM_FLOW_MULTIPLE = 0, //!< No additional details 179 SINGLE_PROGRAM_FLOW_SINGLE = 1, //!< No additional details 180 }; 181 182 //! \brief DENORM_MODE 183 //! \details 184 //! This field specifies how Float denormalized numbers are handles in the 185 //! dispatched thread. 186 enum DENORM_MODE 187 { 188 DENORM_MODE_FTZ = 0, //!< Float denorms will be flushed to zero when appearing as inputs; denorms will never come out of instructions. Double precision float and half precision float numbers are not flushed to zero. 189 DENORM_MODE_SETBYKERNEL = 1, //!< Denorms will be handled in by kernel. 190 }; 191 192 //! \brief SAMPLER_COUNT 193 //! \details 194 //! Specifies how many samplers (in multiples of 4) the kernel uses. Used 195 //! only for prefetching the associated sampler state entries. 196 //! <i>This field is ignored for child threads.</i> 197 //! <i>If this field is not zero, sampler state is prefetched for the 198 //! first instance of a root thread upon the startup of the media 199 //! pipeline.</i> 200 enum SAMPLER_COUNT 201 { 202 SAMPLER_COUNT_NOSAMPLERSUSED = 0, //!< No additional details 203 SAMPLER_COUNT_BETWEEN1AND4SAMPLERSUSED = 1, //!< No additional details 204 SAMPLER_COUNT_BETWEEN5AND8SAMPLERSUSED = 2, //!< No additional details 205 SAMPLER_COUNT_BETWEEN9AND12SAMPLERSUSED = 3, //!< No additional details 206 SAMPLER_COUNT_BETWEEN13AND16SAMPLERSUSED = 4, //!< No additional details 207 }; 208 209 //! \brief SHARED_LOCAL_MEMORY_SIZE 210 //! \details 211 //! This field indicates how much sharedlocalmemory the thread group 212 //! requires. The amount is specified in 4k blocks, but only powers of 2 213 //! are allowed: 0, 4k, 8k, 16k, 32k and 64k per half-slice. 214 enum SHARED_LOCAL_MEMORY_SIZE 215 { 216 SHARED_LOCAL_MEMORY_SIZE_ENCODES0K = 0, //!< No additional details 217 SHARED_LOCAL_MEMORY_SIZE_ENCODES4K = 1, //!< No additional details 218 SHARED_LOCAL_MEMORY_SIZE_ENCODES8K = 2, //!< No additional details 219 SHARED_LOCAL_MEMORY_SIZE_ENCODES16K = 4, //!< No additional details 220 SHARED_LOCAL_MEMORY_SIZE_ENCODES32K = 8, //!< No additional details 221 SHARED_LOCAL_MEMORY_SIZE_ENCODES64K = 16, //!< No additional details 222 }; 223 224 enum ROUNDING_MODE 225 { 226 ROUNDING_MODE_RTNE = 0, //!< Round to Nearest Even 227 ROUNDING_MODE_RU = 1, //!< Round toward +Infinity 228 ROUNDING_MODE_RD = 2, //!< Round toward -Infinity 229 ROUNDING_MODE_RTZ = 3, //!< Round toward Zero 230 }; 231 232 //! \name Initializations 233 234 //! \brief Explicit member initialization function 235 INTERFACE_DESCRIPTOR_DATA_CMD(); 236 237 static const size_t dwSize = 8; 238 static const size_t byteSize = 32; 239 }; 240 241 //! 242 //! \brief BINDING_TABLE_STATE 243 //! \details 244 //! The binding table binds surfaces to logical resource indices used by 245 //! shaders and other compute engine kernels. It is stored as an array of up 246 //! to 256 elements, each of which contains one dword as defined here. The 247 //! start of each element is spaced one dword apart. The first element of 248 //! the binding table is aligned to a 64-byte boundary. Binding table 249 //! indexes beyond 256 will automatically be mapped to entry 0 by the HW, w/ 250 //! the exception of any messages which support the special indexes 240 251 //! through 255, inclusive. 252 //! 253 struct BINDING_TABLE_STATE_CMD 254 { 255 union 256 { 257 //!< DWORD 0 258 struct 259 { 260 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 261 uint32_t SurfaceStatePointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Surface State Pointer 262 }; 263 uint32_t Value; 264 } DW0; 265 266 //! \name Local enumerations 267 268 //! \name Initializations 269 270 //! \brief Explicit member initialization function 271 BINDING_TABLE_STATE_CMD(); 272 273 static const size_t dwSize = 1; 274 static const size_t byteSize = 4; 275 }; 276 277 //! 278 //! \brief RENDER_SURFACE_STATE 279 //! \details 280 //! This is the normal surface state used by all messages that use 281 //! SURFACE_STATE except those that use MEDIA_SURFACE_STATE. 282 //! 283 struct RENDER_SURFACE_STATE_CMD 284 { 285 union 286 { 287 //!< DWORD 0 288 struct 289 { 290 uint32_t CubeFaceEnablePositiveZ : __CODEGEN_BITFIELD( 0, 0) ; //!< Cube Face Enable - Positive Z, [Surface Type] == 'SURFTYPE_CUBE' 291 uint32_t CubeFaceEnableNegativeZ : __CODEGEN_BITFIELD( 1, 1) ; //!< Cube Face Enable - Negative Z, [Surface Type] == 'SURFTYPE_CUBE' 292 uint32_t CubeFaceEnablePositiveY : __CODEGEN_BITFIELD( 2, 2) ; //!< Cube Face Enable - Positive Y, [Surface Type] == 'SURFTYPE_CUBE' 293 uint32_t CubeFaceEnableNegativeY : __CODEGEN_BITFIELD( 3, 3) ; //!< Cube Face Enable - Negative Y, [Surface Type] == 'SURFTYPE_CUBE' 294 uint32_t CubeFaceEnablePositiveX : __CODEGEN_BITFIELD( 4, 4) ; //!< Cube Face Enable - Positive X, [Surface Type] == 'SURFTYPE_CUBE' 295 uint32_t CubeFaceEnableNegativeX : __CODEGEN_BITFIELD( 5, 5) ; //!< Cube Face Enable - Negative X, [Surface Type] == 'SURFTYPE_CUBE' 296 uint32_t MediaBoundaryPixelMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MEDIA_BOUNDARY_PIXEL_MODE 297 uint32_t RenderCacheReadWriteMode : __CODEGEN_BITFIELD( 8, 8) ; //!< RENDER_CACHE_READ_WRITE_MODE 298 uint32_t SamplerL2OutOfOrderModeDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Sampler L2 Out of Order Mode Disable 299 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(10, 10) ; //!< Vertical Line Stride Offset 300 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(11, 11) ; //!< Vertical Line Stride 301 uint32_t TileMode : __CODEGEN_BITFIELD(12, 13) ; //!< TILE_MODE 302 uint32_t SurfaceHorizontalAlignment : __CODEGEN_BITFIELD(14, 15) ; //!< SURFACE_HORIZONTAL_ALIGNMENT 303 uint32_t SurfaceVerticalAlignment : __CODEGEN_BITFIELD(16, 17) ; //!< SURFACE_VERTICAL_ALIGNMENT 304 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(18, 26) ; //!< SURFACE_FORMAT 305 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 27) ; //!< Reserved 306 uint32_t SurfaceArray : __CODEGEN_BITFIELD(28, 28) ; //!< Surface Array 307 uint32_t SurfaceType : __CODEGEN_BITFIELD(29, 31) ; //!< SURFACE_TYPE 308 }; 309 uint32_t Value; 310 } DW0; 311 union 312 { 313 //!< DWORD 1 314 struct 315 { 316 uint32_t SurfaceQpitch : __CODEGEN_BITFIELD( 0, 14) ; //!< Surface QPitch 317 uint32_t Reserved47 : __CODEGEN_BITFIELD(15, 18) ; //!< Reserved 318 uint32_t BaseMipLevel : __CODEGEN_BITFIELD(19, 23) ; //!< Base Mip Level 319 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD(24, 30) ; //!< Memory Object Control State 320 uint32_t Reserved63 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 321 }; 322 uint32_t Value; 323 } DW1; 324 union 325 { 326 //!< DWORD 2 327 struct 328 { 329 uint32_t Width : __CODEGEN_BITFIELD( 0, 13) ; //!< Width 330 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 331 uint32_t Height : __CODEGEN_BITFIELD(16, 29) ; //!< Height 332 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 333 }; 334 uint32_t Value; 335 } DW2; 336 union 337 { 338 //!< DWORD 3 339 struct 340 { 341 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 0, 17) ; //!< Surface Pitch 342 uint32_t Reserved114 : __CODEGEN_BITFIELD(18, 20) ; //!< Reserved 343 uint32_t Depth : __CODEGEN_BITFIELD(21, 31) ; //!< Depth 344 }; 345 uint32_t Value; 346 } DW3; 347 union 348 { 349 //!< DWORD 4 350 struct 351 { 352 uint32_t MultisamplePositionPaletteIndex : __CODEGEN_BITFIELD( 0, 2) ; //!< Multisample Position Palette Index, [Surface Type] != 'SURFTYPE_STRBUF' 353 uint32_t NumberOfMultisamples : __CODEGEN_BITFIELD( 3, 5) ; //!< NUMBER_OF_MULTISAMPLES, [Surface Type] != 'SURFTYPE_STRBUF' 354 uint32_t MultisampledSurfaceStorageFormat : __CODEGEN_BITFIELD( 6, 6) ; //!< MULTISAMPLED_SURFACE_STORAGE_FORMAT, [Surface Type] != 'SURFTYPE_STRBUF' 355 uint32_t RenderTargetViewExtent : __CODEGEN_BITFIELD( 7, 17) ; //!< Render Target View Extent, [Surface Type] != 'SURFTYPE_STRBUF' 356 uint32_t MinimumArrayElement : __CODEGEN_BITFIELD(18, 28) ; //!< Minimum Array Element, [Surface Type] != 'SURFTYPE_STRBUF' 357 uint32_t RenderTargetAndSampleUnormRotation : __CODEGEN_BITFIELD(29, 30) ; //!< RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION, [Surface Type] != 'SURFTYPE_STRBUF' 358 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, [Surface Type] != 'SURFTYPE_STRBUF' 359 }; 360 uint32_t Value; 361 } DW4; 362 union 363 { 364 //!< DWORD 5 365 struct 366 { 367 uint32_t MipCountLod : __CODEGEN_BITFIELD( 0, 3) ; //!< MIP Count / LOD, 368 uint32_t SurfaceMinLod : __CODEGEN_BITFIELD( 4, 7) ; //!< Surface Min LOD, 369 uint32_t Reserved168 : __CODEGEN_BITFIELD( 8, 13) ; //!< Reserved, 370 uint32_t CoherencyType : __CODEGEN_BITFIELD(14, 14) ; //!< COHERENCY_TYPE, 371 uint32_t Reserved175 : __CODEGEN_BITFIELD(15, 19) ; //!< Reserved, 372 uint32_t EwaDisableForCube : __CODEGEN_BITFIELD(20, 20) ; //!< EWA_DISABLE_FOR_CUBE, 373 uint32_t YOffset : __CODEGEN_BITFIELD(21, 23) ; //!< Y Offset, 374 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved, 375 uint32_t XOffset : __CODEGEN_BITFIELD(25, 31) ; //!< X Offset, 376 }; 377 uint32_t Value; 378 } DW5; 379 union 380 { 381 //!< DWORD 6 382 struct 383 { 384 uint32_t YOffsetForUOrUvPlane : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 385 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved, ([Surface Format] == 'PLANAR') 386 uint32_t XOffsetForUOrUvPlane : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 387 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved, ([Surface Format] == 'PLANAR') 388 uint32_t SeparateUvPlaneEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Separate UV Plane Enable, ([Surface Format] == 'PLANAR') 389 } Obj0; 390 struct 391 { 392 uint32_t AuxiliarySurfaceMode : __CODEGEN_BITFIELD( 0, 2) ; //!< AUXILIARY_SURFACE_MODE, ([Surface Format] != 'PLANAR') 393 uint32_t AuxiliarySurfacePitch : __CODEGEN_BITFIELD( 3, 11) ; //!< Auxiliary Surface Pitch, ([Surface Format] != 'PLANAR') 394 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved, ([Surface Format] != 'PLANAR') 395 uint32_t AuxiliarySurfaceQpitch : __CODEGEN_BITFIELD(16, 30) ; //!< Auxiliary Surface QPitch, ([Surface Format] != 'PLANAR') 396 uint32_t Reserved223 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, ([Surface Format] != 'PLANAR') 397 } Obj1; 398 uint32_t Value; 399 } DW6; 400 union 401 { 402 //!< DWORD 7 403 struct 404 { 405 uint32_t ResourceMinLod : __CODEGEN_BITFIELD( 0, 11) ; //!< Resource Min LOD 406 uint32_t Reserved236 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 407 uint32_t ShaderChannelSelectAlpha : __CODEGEN_BITFIELD(16, 18) ; //!< SHADER_CHANNEL_SELECT_ALPHA 408 uint32_t ShaderChannelSelectBlue : __CODEGEN_BITFIELD(19, 21) ; //!< SHADER_CHANNEL_SELECT_BLUE 409 uint32_t ShaderChannelSelectGreen : __CODEGEN_BITFIELD(22, 24) ; //!< SHADER_CHANNEL_SELECT_GREEN 410 uint32_t ShaderChannelSelectRed : __CODEGEN_BITFIELD(25, 27) ; //!< SHADER_CHANNEL_SELECT_RED 411 uint32_t AlphaClearColor : __CODEGEN_BITFIELD(28, 28) ; //!< ALPHA_CLEAR_COLOR 412 uint32_t BlueClearColor : __CODEGEN_BITFIELD(29, 29) ; //!< BLUE_CLEAR_COLOR 413 uint32_t GreenClearColor : __CODEGEN_BITFIELD(30, 30) ; //!< GREEN_CLEAR_COLOR 414 uint32_t RedClearColor : __CODEGEN_BITFIELD(31, 31) ; //!< RED_CLEAR_COLOR 415 }; 416 uint32_t Value; 417 } DW7; 418 union 419 { 420 //!< DWORD 8..9 421 struct 422 { 423 uint64_t SurfaceBaseAddress ; //!< Surface Base Address 424 }; 425 uint32_t Value[2]; 426 } DW8_9; 427 union 428 { 429 //!< DWORD 10..11 430 struct 431 { 432 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved, 433 uint64_t AuxiliarySurfaceBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Auxiliary Surface Base Address, ([Surface Format] != 'PLANAR') AND [Memory Compression Enable] == 0 434 } Obj0; 435 struct 436 { 437 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 20) ; //!< Reserved, 438 uint64_t AuxiliaryTableIndexForMediaCompressedSurface : __CODEGEN_BITFIELD(21, 31) ; //!< Auxiliary Table Index for Media Compressed Surface, [Memory Compression Enable] ==1 439 uint64_t Reserved352 : __CODEGEN_BITFIELD(32, 63) ; //!< Reserved, [Memory Compression Enable] ==1 440 } Obj1; 441 struct 442 { 443 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved, [Memory Compression Enable] ==1 444 uint64_t YOffsetForVPlane : __CODEGEN_BITFIELD(32, 45) ; //!< Y Offset for V Plane, ([Surface Format] == 'PLANAR') 445 uint64_t Reserved366 : __CODEGEN_BITFIELD(46, 47) ; //!< Reserved, ([Surface Format] == 'PLANAR') 446 uint64_t XOffsetForVPlane : __CODEGEN_BITFIELD(48, 61) ; //!< X Offset for V Plane, ([Surface Format] == 'PLANAR') 447 uint64_t Reserved382 : __CODEGEN_BITFIELD(62, 63) ; //!< Reserved, ([Surface Format] == 'PLANAR') 448 } Obj2; 449 uint32_t Value[2]; 450 } DW10_11; 451 union 452 { 453 //!< DWORD 12 454 struct 455 { 456 uint32_t Reserved384 ; //!< Reserved 457 }; 458 uint32_t Value; 459 } DW12; 460 union 461 { 462 //!< DWORD 13 463 struct 464 { 465 uint32_t Reserved416 ; //!< Reserved 466 }; 467 uint32_t Value; 468 } DW13; 469 union 470 { 471 //!< DWORD 14 472 struct 473 { 474 uint32_t Reserved448 ; //!< Reserved 475 }; 476 uint32_t Value; 477 } DW14; 478 union 479 { 480 //!< DWORD 15 481 struct 482 { 483 uint32_t Reserved480 ; //!< Reserved 484 }; 485 uint32_t Value; 486 } DW15; 487 488 //! \name Local enumerations 489 490 //! \brief MEDIA_BOUNDARY_PIXEL_MODE 491 //! \details 492 //! <div id="GroupContent-248" class="GroupContent UseCKEdit"> 493 //! <p><b>For 2D Non-Array Surfaces accessed via the Data Port Media Block 494 //! Read Message or Data Port Transpose Read message:</b><br /> 495 //! This field enables control of which rows are returned on vertical 496 //! out-of-bounds reads using the Data Port Media Block Read Message or Data 497 //! Port Transpose Read message. In the description below, frame mode refers 498 //! to <b>Vertical Line Stride</b> = 0, field mode is <b>Vertical Line 499 //! Stride</b> = 1 in which only the even or odd rows are addressable. The 500 //! frame refers to the entire surface, while the field refers only to the 501 //! even or odd rows within the surface.</p> 502 //! <p><b>For Other Surfaces:</b><br /> 503 //! Reserved : MBZ</p></div> 504 enum MEDIA_BOUNDARY_PIXEL_MODE 505 { 506 MEDIA_BOUNDARY_PIXEL_MODE_NORMALMODE = 0, //!< The row returned on an out-of-bound access is the closest row in the frame or field. Rows from the opposite field are never returned. 507 MEDIA_BOUNDARY_PIXEL_MODE_PROGRESSIVEFRAME = 2, //!< The row returned on an out-of-bound access is the closest row in the frame, even if in field mode. 508 MEDIA_BOUNDARY_PIXEL_MODE_INTERLACEDFRAME = 3, //!< In field mode, the row returned on an out-of-bound access is the closest row in the field. In frame mode, even out-of-bound rows return the nearest even row while odd out-of-bound rows return the nearest odd row. 509 }; 510 511 //! \brief RENDER_CACHE_READ_WRITE_MODE 512 //! \details 513 //! <p><b>For Surfaces accessed via the Data Port to Render Cache:</b><br /> 514 //! This field specifies the way Render Cache treats a write request. If 515 //! unset, Render Cache allocates a write-only cache line for a write miss. 516 //! If set, Render Cache allocates a read-write cache line for a write 517 //! miss.</p> 518 //! <p><b>For Surfaces accessed via the Sampling Engine or Data Port to 519 //! Texture Cache or Data Cache:</b><br /> 520 //! This field is reserved : MBZ</p> 521 enum RENDER_CACHE_READ_WRITE_MODE 522 { 523 RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLYCACHE = 0, //!< Allocating write-only cache for a write miss 524 RENDER_CACHE_READ_WRITE_MODE_READ_WRITECACHE = 1, //!< Allocating read-write cache for a write miss 525 }; 526 527 //! \brief TILE_MODE 528 //! \details 529 //! This field specifies the type of memory tiling (Linear, WMajor, XMajor, 530 //! or YMajor) employed to tile this surface. See <em>Memory Interface 531 //! Functions</em> for details on memory tiling and restrictions. 532 enum TILE_MODE 533 { 534 TILE_MODE_LINEAR = 0, //!< Linear mode (no tiling) 535 TILE_MODE_WMAJOR = 1, //!< W major tiling 536 TILE_MODE_XMAJOR = 2, //!< X major tiling 537 TILE_MODE_YMAJOR = 3, //!< Y major tiling 538 }; 539 540 //! \brief SURFACE_HORIZONTAL_ALIGNMENT 541 //! \details 542 //! For Sampling Engine and Render Target Surfaces: This field specifies the 543 //! horizontal alignment requirement for the surface. 544 enum SURFACE_HORIZONTAL_ALIGNMENT 545 { 546 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN4 = 1, //!< Horizontal alignment factor j = 4 547 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN8 = 2, //!< Horizontal alignment factor j = 8 548 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN16 = 3, //!< Horizontal alignment factor j = 16 549 }; 550 551 //! \brief SURFACE_VERTICAL_ALIGNMENT 552 //! \details 553 //! <b>For Sampling Engine and Render Target Surfaces:</b> This field 554 //! specifies the vertical alignment requirement in elements for the 555 //! surface. Refer to the "Memory Data Formats" chapter for details on how 556 //! this field changes the layout of the surface in memory. An 557 //! <i>element</i> is defined as a pixel in uncompresed surface formats, and 558 //! as a compression block in compressed surface formats. For 559 //! MSFMT_DEPTH_STENCIL type multisampled surfaces, an element is a sample. 560 enum SURFACE_VERTICAL_ALIGNMENT 561 { 562 SURFACE_VERTICAL_ALIGNMENT_VALIGN4 = 1, //!< Vertical alignment factor j = 4 563 SURFACE_VERTICAL_ALIGNMENT_VALIGN8 = 2, //!< Vertical alignment factor j = 8 564 SURFACE_VERTICAL_ALIGNMENT_VALIGN16 = 3, //!< Vertical alignment factor j = 16 565 }; 566 567 //! \brief SURFACE_FORMAT 568 //! \details 569 //! This field specifies the format of the surface or element within this 570 //! surface. This field is ignored for all data port messages other than the 571 //! render target message and streamed vertex buffer write message. Some 572 //! forms of the media block messages use the surface format. 573 enum SURFACE_FORMAT 574 { 575 SURFACE_FORMAT_R32G32B32A32FLOAT = 0, //!< No additional details 576 SURFACE_FORMAT_R32G32B32A32SINT = 1, //!< No additional details 577 SURFACE_FORMAT_R32G32B32A32UINT = 2, //!< No additional details 578 SURFACE_FORMAT_R32G32B32A32UNORM = 3, //!< No additional details 579 SURFACE_FORMAT_R32G32B32A32SNORM = 4, //!< No additional details 580 SURFACE_FORMAT_R64G64FLOAT = 5, //!< No additional details 581 SURFACE_FORMAT_R32G32B32X32FLOAT = 6, //!< No additional details 582 SURFACE_FORMAT_R32G32B32A32SSCALED = 7, //!< No additional details 583 SURFACE_FORMAT_R32G32B32A32USCALED = 8, //!< No additional details 584 SURFACE_FORMAT_R32G32B32A32SFIXED = 32, //!< No additional details 585 SURFACE_FORMAT_R64G64PASSTHRU = 33, //!< No additional details 586 SURFACE_FORMAT_R32G32B32FLOAT = 64, //!< No additional details 587 SURFACE_FORMAT_R32G32B32SINT = 65, //!< No additional details 588 SURFACE_FORMAT_R32G32B32UINT = 66, //!< No additional details 589 SURFACE_FORMAT_R32G32B32UNORM = 67, //!< No additional details 590 SURFACE_FORMAT_R32G32B32SNORM = 68, //!< No additional details 591 SURFACE_FORMAT_R32G32B32SSCALED = 69, //!< No additional details 592 SURFACE_FORMAT_R32G32B32USCALED = 70, //!< No additional details 593 SURFACE_FORMAT_R32G32B32SFIXED = 80, //!< No additional details 594 SURFACE_FORMAT_R16G16B16A16UNORM = 128, //!< No additional details 595 SURFACE_FORMAT_R16G16B16A16SNORM = 129, //!< No additional details 596 SURFACE_FORMAT_R16G16B16A16SINT = 130, //!< No additional details 597 SURFACE_FORMAT_R16G16B16A16UINT = 131, //!< No additional details 598 SURFACE_FORMAT_R16G16B16A16FLOAT = 132, //!< No additional details 599 SURFACE_FORMAT_R32G32FLOAT = 133, //!< No additional details 600 SURFACE_FORMAT_R32G32SINT = 134, //!< No additional details 601 SURFACE_FORMAT_R32G32UINT = 135, //!< No additional details 602 SURFACE_FORMAT_R32FLOATX8X24TYPELESS = 136, //!< No additional details 603 SURFACE_FORMAT_X32TYPELESSG8X24UINT = 137, //!< No additional details 604 SURFACE_FORMAT_L32A32FLOAT = 138, //!< No additional details 605 SURFACE_FORMAT_R32G32UNORM = 139, //!< No additional details 606 SURFACE_FORMAT_R32G32SNORM = 140, //!< No additional details 607 SURFACE_FORMAT_R64FLOAT = 141, //!< No additional details 608 SURFACE_FORMAT_R16G16B16X16UNORM = 142, //!< No additional details 609 SURFACE_FORMAT_R16G16B16X16FLOAT = 143, //!< No additional details 610 SURFACE_FORMAT_A32X32FLOAT = 144, //!< No additional details 611 SURFACE_FORMAT_L32X32FLOAT = 145, //!< No additional details 612 SURFACE_FORMAT_I32X32FLOAT = 146, //!< No additional details 613 SURFACE_FORMAT_R16G16B16A16SSCALED = 147, //!< No additional details 614 SURFACE_FORMAT_R16G16B16A16USCALED = 148, //!< No additional details 615 SURFACE_FORMAT_R32G32SSCALED = 149, //!< No additional details 616 SURFACE_FORMAT_R32G32USCALED = 150, //!< No additional details 617 SURFACE_FORMAT_R32G32SFIXED = 160, //!< No additional details 618 SURFACE_FORMAT_R64PASSTHRU = 161, //!< No additional details 619 SURFACE_FORMAT_B8G8R8A8UNORM = 192, //!< No additional details 620 SURFACE_FORMAT_B8G8R8A8UNORMSRGB = 193, //!< No additional details 621 SURFACE_FORMAT_R10G10B10A2UNORM = 194, //!< No additional details 622 SURFACE_FORMAT_R10G10B10A2UNORMSRGB = 195, //!< No additional details 623 SURFACE_FORMAT_R10G10B10A2UINT = 196, //!< No additional details 624 SURFACE_FORMAT_R10G10B10SNORMA2UNORM = 197, //!< No additional details 625 SURFACE_FORMAT_R8G8B8A8UNORM = 199, //!< No additional details 626 SURFACE_FORMAT_R8G8B8A8UNORMSRGB = 200, //!< No additional details 627 SURFACE_FORMAT_R8G8B8A8SNORM = 201, //!< No additional details 628 SURFACE_FORMAT_R8G8B8A8SINT = 202, //!< No additional details 629 SURFACE_FORMAT_R8G8B8A8UINT = 203, //!< No additional details 630 SURFACE_FORMAT_R16G16UNORM = 204, //!< No additional details 631 SURFACE_FORMAT_R16G16SNORM = 205, //!< No additional details 632 SURFACE_FORMAT_R16G16SINT = 206, //!< No additional details 633 SURFACE_FORMAT_R16G16UINT = 207, //!< No additional details 634 SURFACE_FORMAT_R16G16FLOAT = 208, //!< No additional details 635 SURFACE_FORMAT_B10G10R10A2UNORM = 209, //!< No additional details 636 SURFACE_FORMAT_B10G10R10A2UNORMSRGB = 210, //!< No additional details 637 SURFACE_FORMAT_R11G11B10FLOAT = 211, //!< No additional details 638 SURFACE_FORMAT_R32SINT = 214, //!< No additional details 639 SURFACE_FORMAT_R32UINT = 215, //!< No additional details 640 SURFACE_FORMAT_R32FLOAT = 216, //!< No additional details 641 SURFACE_FORMAT_R24UNORMX8TYPELESS = 217, //!< No additional details 642 SURFACE_FORMAT_X24TYPELESSG8UINT = 218, //!< No additional details 643 SURFACE_FORMAT_L32UNORM = 221, //!< No additional details 644 SURFACE_FORMAT_A32UNORM = 222, //!< No additional details 645 SURFACE_FORMAT_L16A16UNORM = 223, //!< No additional details 646 SURFACE_FORMAT_I24X8UNORM = 224, //!< No additional details 647 SURFACE_FORMAT_L24X8UNORM = 225, //!< No additional details 648 SURFACE_FORMAT_A24X8UNORM = 226, //!< No additional details 649 SURFACE_FORMAT_I32FLOAT = 227, //!< No additional details 650 SURFACE_FORMAT_L32FLOAT = 228, //!< No additional details 651 SURFACE_FORMAT_A32FLOAT = 229, //!< No additional details 652 SURFACE_FORMAT_X8B8UNORMG8R8SNORM = 230, //!< No additional details 653 SURFACE_FORMAT_A8X8UNORMG8R8SNORM = 231, //!< No additional details 654 SURFACE_FORMAT_B8X8UNORMG8R8SNORM = 232, //!< No additional details 655 SURFACE_FORMAT_B8G8R8X8UNORM = 233, //!< No additional details 656 SURFACE_FORMAT_B8G8R8X8UNORMSRGB = 234, //!< No additional details 657 SURFACE_FORMAT_R8G8B8X8UNORM = 235, //!< No additional details 658 SURFACE_FORMAT_R8G8B8X8UNORMSRGB = 236, //!< No additional details 659 SURFACE_FORMAT_R9G9B9E5SHAREDEXP = 237, //!< No additional details 660 SURFACE_FORMAT_B10G10R10X2UNORM = 238, //!< No additional details 661 SURFACE_FORMAT_L16A16FLOAT = 240, //!< No additional details 662 SURFACE_FORMAT_R32UNORM = 241, //!< No additional details 663 SURFACE_FORMAT_R32SNORM = 242, //!< No additional details 664 SURFACE_FORMAT_R10G10B10X2USCALED = 243, //!< No additional details 665 SURFACE_FORMAT_R8G8B8A8SSCALED = 244, //!< No additional details 666 SURFACE_FORMAT_R8G8B8A8USCALED = 245, //!< No additional details 667 SURFACE_FORMAT_R16G16SSCALED = 246, //!< No additional details 668 SURFACE_FORMAT_R16G16USCALED = 247, //!< No additional details 669 SURFACE_FORMAT_R32SSCALED = 248, //!< No additional details 670 SURFACE_FORMAT_R32USCALED = 249, //!< No additional details 671 SURFACE_FORMAT_B5G6R5UNORM = 256, //!< No additional details 672 SURFACE_FORMAT_B5G6R5UNORMSRGB = 257, //!< No additional details 673 SURFACE_FORMAT_B5G5R5A1UNORM = 258, //!< No additional details 674 SURFACE_FORMAT_B5G5R5A1UNORMSRGB = 259, //!< No additional details 675 SURFACE_FORMAT_B4G4R4A4UNORM = 260, //!< No additional details 676 SURFACE_FORMAT_B4G4R4A4UNORMSRGB = 261, //!< No additional details 677 SURFACE_FORMAT_R8G8UNORM = 262, //!< No additional details 678 SURFACE_FORMAT_R8G8SNORM = 263, //!< No additional details 679 SURFACE_FORMAT_R8G8SINT = 264, //!< No additional details 680 SURFACE_FORMAT_R8G8UINT = 265, //!< No additional details 681 SURFACE_FORMAT_R16UNORM = 266, //!< No additional details 682 SURFACE_FORMAT_R16SNORM = 267, //!< No additional details 683 SURFACE_FORMAT_R16SINT = 268, //!< No additional details 684 SURFACE_FORMAT_R16UINT = 269, //!< No additional details 685 SURFACE_FORMAT_R16FLOAT = 270, //!< No additional details 686 SURFACE_FORMAT_A8P8UNORMPALETTE0 = 271, //!< No additional details 687 SURFACE_FORMAT_A8P8UNORMPALETTE1 = 272, //!< No additional details 688 SURFACE_FORMAT_I16UNORM = 273, //!< No additional details 689 SURFACE_FORMAT_L16UNORM = 274, //!< No additional details 690 SURFACE_FORMAT_A16UNORM = 275, //!< No additional details 691 SURFACE_FORMAT_L8A8UNORM = 276, //!< No additional details 692 SURFACE_FORMAT_I16FLOAT = 277, //!< No additional details 693 SURFACE_FORMAT_L16FLOAT = 278, //!< No additional details 694 SURFACE_FORMAT_A16FLOAT = 279, //!< No additional details 695 SURFACE_FORMAT_L8A8UNORMSRGB = 280, //!< No additional details 696 SURFACE_FORMAT_R5G5SNORMB6UNORM = 281, //!< No additional details 697 SURFACE_FORMAT_B5G5R5X1UNORM = 282, //!< No additional details 698 SURFACE_FORMAT_B5G5R5X1UNORMSRGB = 283, //!< No additional details 699 SURFACE_FORMAT_R8G8SSCALED = 284, //!< No additional details 700 SURFACE_FORMAT_R8G8USCALED = 285, //!< No additional details 701 SURFACE_FORMAT_R16SSCALED = 286, //!< No additional details 702 SURFACE_FORMAT_R16USCALED = 287, //!< No additional details 703 SURFACE_FORMAT_P8A8UNORMPALETTE0 = 290, //!< No additional details 704 SURFACE_FORMAT_P8A8UNORMPALETTE1 = 291, //!< No additional details 705 SURFACE_FORMAT_A1B5G5R5UNORM = 292, //!< No additional details 706 SURFACE_FORMAT_A4B4G4R4UNORM = 293, //!< No additional details 707 SURFACE_FORMAT_L8A8UINT = 294, //!< No additional details 708 SURFACE_FORMAT_L8A8SINT = 295, //!< No additional details 709 SURFACE_FORMAT_R8UNORM = 320, //!< No additional details 710 SURFACE_FORMAT_R8SNORM = 321, //!< No additional details 711 SURFACE_FORMAT_R8SINT = 322, //!< No additional details 712 SURFACE_FORMAT_R8UINT = 323, //!< No additional details 713 SURFACE_FORMAT_A8UNORM = 324, //!< No additional details 714 SURFACE_FORMAT_I8UNORM = 325, //!< No additional details 715 SURFACE_FORMAT_L8UNORM = 326, //!< No additional details 716 SURFACE_FORMAT_P4A4UNORMPALETTE0 = 327, //!< No additional details 717 SURFACE_FORMAT_A4P4UNORMPALETTE0 = 328, //!< No additional details 718 SURFACE_FORMAT_R8SSCALED = 329, //!< No additional details 719 SURFACE_FORMAT_R8USCALED = 330, //!< No additional details 720 SURFACE_FORMAT_P8UNORMPALETTE0 = 331, //!< No additional details 721 SURFACE_FORMAT_L8UNORMSRGB = 332, //!< No additional details 722 SURFACE_FORMAT_P8UNORMPALETTE1 = 333, //!< No additional details 723 SURFACE_FORMAT_P4A4UNORMPALETTE1 = 334, //!< No additional details 724 SURFACE_FORMAT_A4P4UNORMPALETTE1 = 335, //!< No additional details 725 SURFACE_FORMAT_Y8UNORM = 336, //!< No additional details 726 SURFACE_FORMAT_L8UINT = 338, //!< No additional details 727 SURFACE_FORMAT_L8SINT = 339, //!< No additional details 728 SURFACE_FORMAT_I8UINT = 340, //!< No additional details 729 SURFACE_FORMAT_I8SINT = 341, //!< No additional details 730 SURFACE_FORMAT_DXT1RGBSRGB = 384, //!< No additional details 731 SURFACE_FORMAT_R1UNORM = 385, //!< No additional details 732 SURFACE_FORMAT_YCRCBNORMAL = 386, //!< No additional details 733 SURFACE_FORMAT_YCRCBSWAPUVY = 387, //!< No additional details 734 SURFACE_FORMAT_P2UNORMPALETTE0 = 388, //!< No additional details 735 SURFACE_FORMAT_P2UNORMPALETTE1 = 389, //!< No additional details 736 SURFACE_FORMAT_BC1UNORM = 390, //!< No additional details 737 SURFACE_FORMAT_BC2UNORM = 391, //!< No additional details 738 SURFACE_FORMAT_BC3UNORM = 392, //!< No additional details 739 SURFACE_FORMAT_BC4UNORM = 393, //!< No additional details 740 SURFACE_FORMAT_BC5UNORM = 394, //!< No additional details 741 SURFACE_FORMAT_BC1UNORMSRGB = 395, //!< No additional details 742 SURFACE_FORMAT_BC2UNORMSRGB = 396, //!< No additional details 743 SURFACE_FORMAT_BC3UNORMSRGB = 397, //!< No additional details 744 SURFACE_FORMAT_MONO8 = 398, //!< No additional details 745 SURFACE_FORMAT_YCRCBSWAPUV = 399, //!< No additional details 746 SURFACE_FORMAT_YCRCBSWAPY = 400, //!< No additional details 747 SURFACE_FORMAT_DXT1RGB = 401, //!< No additional details 748 SURFACE_FORMAT_FXT1 = 402, //!< No additional details 749 SURFACE_FORMAT_R8G8B8UNORM = 403, //!< No additional details 750 SURFACE_FORMAT_R8G8B8SNORM = 404, //!< No additional details 751 SURFACE_FORMAT_R8G8B8SSCALED = 405, //!< No additional details 752 SURFACE_FORMAT_R8G8B8USCALED = 406, //!< No additional details 753 SURFACE_FORMAT_R64G64B64A64FLOAT = 407, //!< No additional details 754 SURFACE_FORMAT_R64G64B64FLOAT = 408, //!< No additional details 755 SURFACE_FORMAT_BC4SNORM = 409, //!< No additional details 756 SURFACE_FORMAT_BC5SNORM = 410, //!< No additional details 757 SURFACE_FORMAT_R16G16B16FLOAT = 411, //!< No additional details 758 SURFACE_FORMAT_R16G16B16UNORM = 412, //!< No additional details 759 SURFACE_FORMAT_R16G16B16SNORM = 413, //!< No additional details 760 SURFACE_FORMAT_R16G16B16SSCALED = 414, //!< No additional details 761 SURFACE_FORMAT_R16G16B16USCALED = 415, //!< No additional details 762 SURFACE_FORMAT_BC6HSF16 = 417, //!< No additional details 763 SURFACE_FORMAT_BC7UNORM = 418, //!< No additional details 764 SURFACE_FORMAT_BC7UNORMSRGB = 419, //!< No additional details 765 SURFACE_FORMAT_BC6HUF16 = 420, //!< No additional details 766 SURFACE_FORMAT_PLANAR4208 = 421, //!< No additional details 767 SURFACE_FORMAT_R8G8B8UNORMSRGB = 424, //!< No additional details 768 SURFACE_FORMAT_ETC1RGB8 = 425, //!< No additional details 769 SURFACE_FORMAT_ETC2RGB8 = 426, //!< No additional details 770 SURFACE_FORMAT_EACR11 = 427, //!< No additional details 771 SURFACE_FORMAT_EACRG11 = 428, //!< No additional details 772 SURFACE_FORMAT_EACSIGNEDR11 = 429, //!< No additional details 773 SURFACE_FORMAT_EACSIGNEDRG11 = 430, //!< No additional details 774 SURFACE_FORMAT_ETC2SRGB8 = 431, //!< No additional details 775 SURFACE_FORMAT_R16G16B16UINT = 432, //!< No additional details 776 SURFACE_FORMAT_R16G16B16SINT = 433, //!< No additional details 777 SURFACE_FORMAT_R32SFIXED = 434, //!< No additional details 778 SURFACE_FORMAT_R10G10B10A2SNORM = 435, //!< No additional details 779 SURFACE_FORMAT_R10G10B10A2USCALED = 436, //!< No additional details 780 SURFACE_FORMAT_R10G10B10A2SSCALED = 437, //!< No additional details 781 SURFACE_FORMAT_R10G10B10A2SINT = 438, //!< No additional details 782 SURFACE_FORMAT_B10G10R10A2SNORM = 439, //!< No additional details 783 SURFACE_FORMAT_B10G10R10A2USCALED = 440, //!< No additional details 784 SURFACE_FORMAT_B10G10R10A2SSCALED = 441, //!< No additional details 785 SURFACE_FORMAT_B10G10R10A2UINT = 442, //!< No additional details 786 SURFACE_FORMAT_B10G10R10A2SINT = 443, //!< No additional details 787 SURFACE_FORMAT_R64G64B64A64PASSTHRU = 444, //!< No additional details 788 SURFACE_FORMAT_R64G64B64PASSTHRU = 445, //!< No additional details 789 SURFACE_FORMAT_ETC2RGB8PTA = 448, //!< No additional details 790 SURFACE_FORMAT_ETC2SRGB8PTA = 449, //!< No additional details 791 SURFACE_FORMAT_ETC2EACRGBA8 = 450, //!< No additional details 792 SURFACE_FORMAT_ETC2EACSRGB8A8 = 451, //!< No additional details 793 SURFACE_FORMAT_R8G8B8UINT = 456, //!< No additional details 794 SURFACE_FORMAT_R8G8B8SINT = 457, //!< No additional details 795 SURFACE_FORMAT_RAW = 511, //!< No additional details 796 }; 797 798 //! \brief SURFACE_TYPE 799 //! \details 800 //! This field defines the type of the surface. 801 enum SURFACE_TYPE 802 { 803 SURFACE_TYPE_SURFTYPE1D = 0, //!< Defines a 1-dimensional map or array of maps 804 SURFACE_TYPE_SURFTYPE2D = 1, //!< Defines a 2-dimensional map or array of maps 805 SURFACE_TYPE_SURFTYPE3D = 2, //!< Defines a 3-dimensional (volumetric) map 806 SURFACE_TYPE_SURFTYPECUBE = 3, //!< Defines a cube map or array of cube maps 807 SURFACE_TYPE_SURFTYPEBUFFER = 4, //!< Defines an element in a buffer 808 SURFACE_TYPE_SURFTYPESTRBUF = 5, //!< Defines a structured buffer surface 809 SURFACE_TYPE_SURFTYPENULL = 7, //!< Defines a null surface 810 }; 811 812 //! \brief NUMBER_OF_MULTISAMPLES 813 //! \details 814 //! This field indicates the number of multisamples on the surface. 815 enum NUMBER_OF_MULTISAMPLES 816 { 817 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT1 = 0, //!< No additional details 818 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT2 = 1, //!< No additional details 819 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT4 = 2, //!< No additional details 820 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT8 = 3, //!< No additional details 821 }; 822 823 //! \brief MULTISAMPLED_SURFACE_STORAGE_FORMAT 824 //! \details 825 //! This field indicates the storage format of the multisampled surface. 826 enum MULTISAMPLED_SURFACE_STORAGE_FORMAT 827 { 828 MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS = 0, //!< Multisampled surface was/is rendered as a render target 829 MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTHSTENCIL = 1, //!< Multisampled surface was rendered as a depth or stencil buffer 830 }; 831 832 //! \brief RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 833 //! \details 834 //! <b>For Render Target Surfaces:</b> 835 //! This field specifies the rotation of this render target surface 836 //! when being written to memory. 837 enum RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 838 { 839 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG = 0, //!< No rotation (0 degrees) 840 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_90DEG = 1, //!< Rotate by 90 degrees 841 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_270DEG = 3, //!< Rotate by 270 degrees 842 }; 843 844 //! \brief COHERENCY_TYPE 845 //! \details 846 //! Specifies the type of coherency maintained for this surface. 847 enum COHERENCY_TYPE 848 { 849 COHERENCY_TYPE_GPUCOHERENT = 0, //!< Surface memory is kept coherent with GPU threads using GPU read/write ordering rules. Surface memory is backed by system memory but is not kept coherent with CPU (LLC). 850 COHERENCY_TYPE_IACOHERENT = 1, //!< Surface memory is kept coherent with CPU (LLC). 851 }; 852 853 //! \brief EWA_DISABLE_FOR_CUBE 854 //! \details 855 //! Specifies if EWA mode for LOD quality improvement needs to be disabled 856 //! for cube maps. 857 enum EWA_DISABLE_FOR_CUBE 858 { 859 EWA_DISABLE_FOR_CUBE_ENABLE = 0, //!< EWA is enabled for cube maps 860 EWA_DISABLE_FOR_CUBE_DISABLE = 1, //!< EWA is disabled for cube maps 861 }; 862 863 //! \brief AUXILIARY_SURFACE_MODE 864 //! \details 865 //! Specifies what type of surface the Auxiliary surface is. The Auxiliary 866 //! surface has its own base address and pitch, but otherwise shares or 867 //! overrides other fields set for the primary surface, detailed in the 868 //! programming notes below. 869 enum AUXILIARY_SURFACE_MODE 870 { 871 AUXILIARY_SURFACE_MODE_AUXNONE = 0, //!< No Auxiliary surface is used 872 AUXILIARY_SURFACE_MODE_AUXMCS = 1, //!< The Auxiliary surfaces is an MCS (Multisample Control Surface) 873 AUXILIARY_SURFACE_MODE_AUXAPPEND = 2, //!< The Auxiliary surface is an append buffer 874 AUXILIARY_SURFACE_MODE_AUXHIZ = 3, //!< The Auxiliary surface is a hierarchical depth buffer 875 }; 876 877 //! \brief SHADER_CHANNEL_SELECT_ALPHA 878 //! \details 879 //! See <b>Shader Channel Select Red</b> for details. 880 enum SHADER_CHANNEL_SELECT_ALPHA 881 { 882 SHADER_CHANNEL_SELECT_ALPHA_ZERO = 0, //!< No additional details 883 SHADER_CHANNEL_SELECT_ALPHA_ONE = 1, //!< No additional details 884 SHADER_CHANNEL_SELECT_ALPHA_RED = 4, //!< No additional details 885 SHADER_CHANNEL_SELECT_ALPHA_GREEN = 5, //!< No additional details 886 SHADER_CHANNEL_SELECT_ALPHA_BLUE = 6, //!< No additional details 887 SHADER_CHANNEL_SELECT_ALPHA_ALPHA = 7, //!< No additional details 888 }; 889 890 //! \brief SHADER_CHANNEL_SELECT_BLUE 891 //! \details 892 //! See <b>Shader Channel Select Red</b> for details. 893 enum SHADER_CHANNEL_SELECT_BLUE 894 { 895 SHADER_CHANNEL_SELECT_BLUE_ZERO = 0, //!< No additional details 896 SHADER_CHANNEL_SELECT_BLUE_ONE = 1, //!< No additional details 897 SHADER_CHANNEL_SELECT_BLUE_RED = 4, //!< No additional details 898 SHADER_CHANNEL_SELECT_BLUE_GREEN = 5, //!< No additional details 899 SHADER_CHANNEL_SELECT_BLUE_BLUE = 6, //!< No additional details 900 SHADER_CHANNEL_SELECT_BLUE_ALPHA = 7, //!< No additional details 901 }; 902 903 //! \brief SHADER_CHANNEL_SELECT_GREEN 904 //! \details 905 //! See <b>Shader Channel Select Red</b> for details. 906 enum SHADER_CHANNEL_SELECT_GREEN 907 { 908 SHADER_CHANNEL_SELECT_GREEN_ZERO = 0, //!< No additional details 909 SHADER_CHANNEL_SELECT_GREEN_ONE = 1, //!< No additional details 910 SHADER_CHANNEL_SELECT_GREEN_RED = 4, //!< No additional details 911 SHADER_CHANNEL_SELECT_GREEN_GREEN = 5, //!< No additional details 912 SHADER_CHANNEL_SELECT_GREEN_BLUE = 6, //!< No additional details 913 SHADER_CHANNEL_SELECT_GREEN_ALPHA = 7, //!< No additional details 914 }; 915 916 //! \brief SHADER_CHANNEL_SELECT_RED 917 //! \details 918 //! Specifies which surface channel is read or written in the Red shader 919 //! channel. 920 enum SHADER_CHANNEL_SELECT_RED 921 { 922 SHADER_CHANNEL_SELECT_RED_ZERO = 0, //!< No additional details 923 SHADER_CHANNEL_SELECT_RED_ONE = 1, //!< No additional details 924 SHADER_CHANNEL_SELECT_RED_RED = 4, //!< No additional details 925 SHADER_CHANNEL_SELECT_RED_GREEN = 5, //!< No additional details 926 SHADER_CHANNEL_SELECT_RED_BLUE = 6, //!< No additional details 927 SHADER_CHANNEL_SELECT_RED_ALPHA = 7, //!< No additional details 928 }; 929 930 //! \brief ALPHA_CLEAR_COLOR 931 //! \details 932 //! <p><b>For Sampling Engine Multisampled Surfaces and Render 933 //! Targets:</b><br /> 934 //! Specifies the clear value for the alpha channel. 935 //! </p> 936 //! <p><b>For Other Surfaces:</b><br /> 937 //! This field is ignored. 938 //! </p> 939 enum ALPHA_CLEAR_COLOR 940 { 941 ALPHA_CLEAR_COLOR_CCZERO = 0, //!< No additional details 942 ALPHA_CLEAR_COLOR_CCONE = 1, //!< No additional details 943 }; 944 945 //! \brief BLUE_CLEAR_COLOR 946 //! \details 947 //! <p><b>For Sampling Engine Multisampled Surfaces and Render 948 //! Targets:</b><br /> 949 //! Specifies the clear value for the blue channel. 950 //! </p> 951 //! <p><b>For Other Surfaces:</b><br /> 952 //! This field is ignored. 953 //! </p> 954 enum BLUE_CLEAR_COLOR 955 { 956 BLUE_CLEAR_COLOR_CCZERO = 0, //!< No additional details 957 BLUE_CLEAR_COLOR_CCONE = 1, //!< No additional details 958 }; 959 960 //! \brief GREEN_CLEAR_COLOR 961 //! \details 962 //! <p><b>For Sampling Engine Multisampled Surfaces and Render 963 //! Targets:</b><br /> 964 //! Specifies the clear value for the green channel. 965 //! </p> 966 //! <p><b>For Other Surfaces:</b><br /> 967 //! This field is ignored. 968 //! </p> 969 enum GREEN_CLEAR_COLOR 970 { 971 GREEN_CLEAR_COLOR_CCZERO = 0, //!< No additional details 972 GREEN_CLEAR_COLOR_CCONE = 1, //!< No additional details 973 }; 974 975 //! \brief RED_CLEAR_COLOR 976 //! \details 977 //! <p><b>For Sampling Engine Multisampled Surfaces and Render 978 //! Targets:</b><br /> 979 //! Specifies the clear value for the red channel.</p> 980 //! <p><b>For Other Surfaces:</b><br /> 981 //! This field is ignored. 982 //! </p> 983 enum RED_CLEAR_COLOR 984 { 985 RED_CLEAR_COLOR_CCZERO = 0, //!< No additional details 986 RED_CLEAR_COLOR_CCONE = 1, //!< No additional details 987 }; 988 989 //! \name Initializations 990 991 //! \brief Explicit member initialization function 992 RENDER_SURFACE_STATE_CMD(); 993 994 static const size_t dwSize = 15; 995 static const size_t byteSize = 60; 996 }; 997 998 //! 999 //! \brief MEDIA_SURFACE_STATE 1000 //! \details 1001 //! This is the SURFACE_STATE used by only deinterlace, sample_8x8, and VME 1002 //! messages. 1003 //! 1004 struct MEDIA_SURFACE_STATE_CMD 1005 { 1006 union 1007 { 1008 //!< DWORD 0 1009 struct 1010 { 1011 uint32_t Reserved0 ; //!< Reserved 1012 }; 1013 uint32_t Value; 1014 } DW0; 1015 union 1016 { 1017 //!< DWORD 1 1018 struct 1019 { 1020 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION 1021 uint32_t PictureStructure : __CODEGEN_BITFIELD( 2, 3) ; //!< PICTURE_STRUCTURE 1022 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1023 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1024 }; 1025 uint32_t Value; 1026 } DW1; 1027 union 1028 { 1029 //!< DWORD 2 1030 struct 1031 { 1032 uint32_t TileMode : __CODEGEN_BITFIELD( 0, 1) ; //!< TILE_MODE 1033 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 1034 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 20) ; //!< Surface Pitch 1035 uint32_t AddressControl : __CODEGEN_BITFIELD(21, 21) ; //!< ADDRESS_CONTROL 1036 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 25) ; //!< Reserved 1037 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(26, 26) ; //!< Interleave Chroma 1038 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 1039 }; 1040 uint32_t Value; 1041 } DW2; 1042 union 1043 { 1044 //!< DWORD 3 1045 struct 1046 { 1047 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U(Cb) 1048 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1049 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U(Cb) 1050 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1051 }; 1052 uint32_t Value; 1053 } DW3; 1054 union 1055 { 1056 //!< DWORD 4 1057 struct 1058 { 1059 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for V(Cr) 1060 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1061 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for V(Cr) 1062 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1063 }; 1064 uint32_t Value; 1065 } DW4; 1066 union 1067 { 1068 //!< DWORD 5 1069 struct 1070 { 1071 uint32_t SurfaceMemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< SURFACE_MEMORY_OBJECT_CONTROL_STATE 1072 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 29) ; //!< Reserved 1073 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(30, 30) ; //!< Vertical Line Stride Offset 1074 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(31, 31) ; //!< Vertical Line Stride 1075 }; 1076 uint32_t Value; 1077 } DW5; 1078 union 1079 { 1080 //!< DWORD 6 1081 struct 1082 { 1083 uint32_t SurfaceBaseAddress ; //!< Surface Base Address 1084 }; 1085 uint32_t Value; 1086 } DW6; 1087 union 1088 { 1089 //!< DWORD 7 1090 struct 1091 { 1092 uint32_t SurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Surface Base Address High 1093 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1094 }; 1095 uint32_t Value; 1096 } DW7; 1097 1098 //! \name Local enumerations 1099 1100 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION 1101 //! \details 1102 //! Specifies the distance to the U/V values with respect to the even 1103 //! numbered Y channels in the V direction 1104 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION 1105 { 1106 CRVCBU_PIXEL_OFFSET_V_DIRECTION_UNNAMED0 = 0, //!< No additional details 1107 }; 1108 1109 //! \brief PICTURE_STRUCTURE 1110 //! \details 1111 //! Specifies the encoding of the current picture. 1112 enum PICTURE_STRUCTURE 1113 { 1114 PICTURE_STRUCTURE_FRAMEPICTURE = 0, //!< No additional details 1115 PICTURE_STRUCTURE_TOPFIELDPICTURE = 1, //!< No additional details 1116 PICTURE_STRUCTURE_BOTTOMFIELDPICTURE = 2, //!< No additional details 1117 PICTURE_STRUCTURE_INVALID_NOTALLOWED = 3, //!< No additional details 1118 }; 1119 1120 //! \brief TILE_MODE 1121 //! \details 1122 //! This field specifies the type of memory tiling (Linear, WMajor, XMajor, 1123 //! or YMajor) employed to tile this surface. See Memory Interface Functions 1124 //! for details on memory tiling and restrictions. 1125 enum TILE_MODE 1126 { 1127 TILE_MODE_TILEMODELINEAR = 0, //!< Linear mode (no tiling) 1128 TILE_MODE_TILEMODEXMAJOR = 2, //!< X major tiling 1129 TILE_MODE_TILEMODEYMAJOR = 3, //!< Y major tiling 1130 }; 1131 1132 enum ADDRESS_CONTROL 1133 { 1134 ADDRESS_CONTROL_CLAMP = 0, //!< Clamp 1135 ADDRESS_CONTROL_MIRROR = 1, //!< Mirror 1136 }; 1137 1138 //! \brief SURFACE_FORMAT 1139 //! \details 1140 //! Specifies the format of the surface. All of the Y and G channels will 1141 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1. 1142 enum SURFACE_FORMAT 1143 { 1144 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 1145 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 1146 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 1147 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 1148 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 1149 SURFACE_FORMAT_Y8UNORMVA = 5, //!< Sample_8x8 only except AVS 1150 SURFACE_FORMAT_Y16SNORM = 6, //!< Sample_8x8 only except AVS 1151 SURFACE_FORMAT_Y16UNORMVA = 7, //!< Sample_8x8 only except AVS 1152 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 only 1153 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 AVS only 1154 SURFACE_FORMAT_R8B8UNORM_CRCB = 10, //!< Sample_8x8 AVS only 1155 SURFACE_FORMAT_R8UNORM_CRCB = 11, //!< Sample_8x8 AVS only 1156 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 AVS only 1157 SURFACE_FORMAT_A8Y8U8V8UNORM = 13, //!< Sample_8x8 AVS only 1158 SURFACE_FORMAT_B8G8R8A8UNORM = 14, //!< Sample_8x8 AVS only 1159 SURFACE_FORMAT_R16G16B16A16 = 15, //!< Sample_8x8 AVS only 1160 SURFACE_FORMAT_Y1UNORM = 16, //!< Sample_8x8 only for boolean surfaces (1bit/pixel) 1161 SURFACE_FORMAT_Y32UNORM = 17, //!< For Integral Image (32bpp) 1162 }; 1163 1164 //! \brief SURFACE_MEMORY_OBJECT_CONTROL_STATE 1165 //! \details 1166 //! This 7-bit field is used in various state commands and indirect state 1167 //! objects to define cacheability and other attributes related to memory 1168 //! objects. 1169 enum SURFACE_MEMORY_OBJECT_CONTROL_STATE 1170 { 1171 SURFACE_MEMORY_OBJECT_CONTROL_STATE_DEFAULTVAUEDESC = 0, //!< No additional details 1172 }; 1173 1174 //! \name Initializations 1175 1176 //! \brief Explicit member initialization function 1177 MEDIA_SURFACE_STATE_CMD(); 1178 1179 static const size_t dwSize = 8; 1180 static const size_t byteSize = 32; 1181 }; 1182 1183 //! 1184 //! \brief SAMPLER_STATE 1185 //! \details 1186 //! This is the normal sampler state used by all messages that use 1187 //! SAMPLER_STATE except sample_8x8 and deinterlace. The sampler state is 1188 //! stored as an array of up to 16 elements, each of which contains the 1189 //! dwords described here. The start of each element is spaced 4 dwords 1190 //! apart. The first element of the sampler state array is aligned to a 1191 //! 32-byte boundary. 1192 //! 1193 struct SAMPLER_STATE_CMD 1194 { 1195 union 1196 { 1197 //!< DWORD 0 1198 struct 1199 { 1200 uint32_t LodAlgorithm : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_ALGORITHM 1201 uint32_t TextureLodBias : __CODEGEN_BITFIELD( 1, 13) ; //!< Texture LOD Bias 1202 uint32_t MinModeFilter : __CODEGEN_BITFIELD(14, 16) ; //!< MIN_MODE_FILTER 1203 uint32_t MagModeFilter : __CODEGEN_BITFIELD(17, 19) ; //!< MAG_MODE_FILTER 1204 uint32_t MipModeFilter : __CODEGEN_BITFIELD(20, 21) ; //!< MIP_MODE_FILTER 1205 uint32_t BaseMipLevel : __CODEGEN_BITFIELD(22, 26) ; //!< Base Mip Level 1206 uint32_t LodPreclampMode : __CODEGEN_BITFIELD(27, 28) ; //!< LOD_PRECLAMP_MODE 1207 uint32_t TextureBorderColorMode : __CODEGEN_BITFIELD(29, 29) ; //!< TEXTURE_BORDER_COLOR_MODE 1208 uint32_t Reserved30 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 1209 uint32_t SamplerDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Sampler Disable 1210 }; 1211 uint32_t Value; 1212 } DW0; 1213 union 1214 { 1215 //!< DWORD 1 1216 struct 1217 { 1218 uint32_t CubeSurfaceControlMode : __CODEGEN_BITFIELD( 0, 0) ; //!< CUBE_SURFACE_CONTROL_MODE 1219 uint32_t ShadowFunction : __CODEGEN_BITFIELD( 1, 3) ; //!< SHADOW_FUNCTION 1220 uint32_t ChromakeyMode : __CODEGEN_BITFIELD( 4, 4) ; //!< CHROMAKEY_MODE 1221 uint32_t ChromakeyIndex : __CODEGEN_BITFIELD( 5, 6) ; //!< ChromaKey Index 1222 uint32_t ChromakeyEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< ChromaKey Enable 1223 uint32_t MaxLod : __CODEGEN_BITFIELD( 8, 19) ; //!< Max LOD 1224 uint32_t MinLod : __CODEGEN_BITFIELD(20, 31) ; //!< Min LOD 1225 }; 1226 uint32_t Value; 1227 } DW1; 1228 union 1229 { 1230 //!< DWORD 2 1231 struct 1232 { 1233 uint32_t LodClampMagnificationMode : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_CLAMP_MAGNIFICATION_MODE 1234 uint32_t Reserved65 : __CODEGEN_BITFIELD( 1, 5) ; //!< Reserved 1235 uint32_t IndirectStatePointer : __CODEGEN_BITFIELD( 6, 23) ; //!< Indirect State Pointer 1236 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1237 }; 1238 uint32_t Value; 1239 } DW2; 1240 union 1241 { 1242 //!< DWORD 3 1243 struct 1244 { 1245 uint32_t TczAddressControlMode : __CODEGEN_BITFIELD( 0, 2) ; //!< TCZ_ADDRESS_CONTROL_MODE 1246 uint32_t TcyAddressControlMode : __CODEGEN_BITFIELD( 3, 5) ; //!< TCY_ADDRESS_CONTROL_MODE 1247 uint32_t TcxAddressControlMode : __CODEGEN_BITFIELD( 6, 8) ; //!< TCX_ADDRESS_CONTROL_MODE 1248 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1249 uint32_t NonNormalizedCoordinateEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Non-normalized Coordinate Enable 1250 uint32_t TrilinearFilterQuality : __CODEGEN_BITFIELD(11, 12) ; //!< TRILINEAR_FILTER_QUALITY 1251 uint32_t RAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(13, 13) ; //!< R Address Min Filter Rounding Enable 1252 uint32_t RAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(14, 14) ; //!< R Address Mag Filter Rounding Enable 1253 uint32_t VAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(15, 15) ; //!< V Address Min Filter Rounding Enable 1254 uint32_t VAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(16, 16) ; //!< V Address Mag Filter Rounding Enable 1255 uint32_t UAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< U Address Min Filter Rounding Enable 1256 uint32_t UAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< U Address Mag Filter Rounding Enable 1257 uint32_t MaximumAnisotropy : __CODEGEN_BITFIELD(19, 21) ; //!< MAXIMUM_ANISOTROPY 1258 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 1259 }; 1260 uint32_t Value; 1261 } DW3; 1262 1263 //! \name Local enumerations 1264 1265 //! \brief LOD_ALGORITHM 1266 //! \details 1267 //! Controls which algorithm is used for LOD calculation. Generally, the EWA 1268 //! approximation algorithm results in higher image quality than the legacy 1269 //! algorithm. 1270 enum LOD_ALGORITHM 1271 { 1272 LOD_ALGORITHM_LEGACY = 0, //!< Use the legacy algorithm for anisotropic filtering 1273 LOD_ALGORITHM_EWAAPPROXIMATION = 1, //!< Use the new EWA approximation algorithm for anisotropic filtering 1274 }; 1275 1276 //! \brief MIN_MODE_FILTER 1277 //! \details 1278 //! This field determines how texels are sampled/filtered when a texture is 1279 //! being "minified" (shrunk). For volume maps, this filter mode selection 1280 //! also applies to the 3rd (inter-layer) dimension.See Mag Mode Filter 1281 enum MIN_MODE_FILTER 1282 { 1283 MIN_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1284 MIN_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1285 MIN_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1286 MIN_MODE_FILTER_MONO = 6, //!< Perform a monochrome convolution filter 1287 }; 1288 1289 //! \brief MAG_MODE_FILTER 1290 //! \details 1291 //! This field determines how texels are sampled/filtered when a texture is 1292 //! being "magnified" (enlarged). For volume maps, this filter mode 1293 //! selection also applies to the 3rd (inter-layer) dimension. 1294 enum MAG_MODE_FILTER 1295 { 1296 MAG_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1297 MAG_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1298 MAG_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1299 MAG_MODE_FILTER_MONO = 6, //!< Perform a monochrome convolution filter 1300 }; 1301 1302 //! \brief MIP_MODE_FILTER 1303 //! \details 1304 //! This field determines if and how mip map levels are chosen and/or 1305 //! combined when texture filtering. 1306 enum MIP_MODE_FILTER 1307 { 1308 MIP_MODE_FILTER_NONE = 0, //!< Disable mip mapping - force use of the mipmap level corresponding to Min LOD. 1309 MIP_MODE_FILTER_NEAREST = 1, //!< Nearest, Select the nearest mip map 1310 MIP_MODE_FILTER_LINEAR = 3, //!< Linearly interpolate between nearest mip maps (combined with linear min/mag filters this is analogous to "Trilinear" filtering). 1311 }; 1312 1313 //! \brief LOD_PRECLAMP_MODE 1314 //! \details 1315 //! <p>This field determines whether the computed LOD is clamped to 1316 //! [max,min] mip level 1317 //! before the mag-vs-min determination is performed.</p> 1318 enum LOD_PRECLAMP_MODE 1319 { 1320 LOD_PRECLAMP_MODE_NONE = 0, //!< LOD PreClamp disabled 1321 LOD_PRECLAMP_MODE_OGL = 2, //!< LOD PreClamp enabled (OGL mode) 1322 }; 1323 1324 //! \brief TEXTURE_BORDER_COLOR_MODE 1325 //! \details 1326 //! For some surface formats, the 32 bit border color is decoded differently 1327 //! based on the border color mode. In addition, the default value of 1328 //! channels not included in the surface may be affected by this field. 1329 //! Refer to the "Sampler Output Channel Mapping" table for the values of 1330 //! these channels, and for surface formats that may only support one of 1331 //! these modes. Also refer to the definition of SAMPLER_BORDER_COLOR_STATE 1332 //! for more details on the behavior of the two modes defined by this field. 1333 enum TEXTURE_BORDER_COLOR_MODE 1334 { 1335 TEXTURE_BORDER_COLOR_MODE_OGL = 0, //!< OGL mode for interpreting the border color 1336 TEXTURE_BORDER_COLOR_MODE_8BIT = 1, //!< Earlier mode for interpreting the border color as UNORM8. 1337 }; 1338 1339 //! \brief CUBE_SURFACE_CONTROL_MODE 1340 //! \details 1341 //! When sampling from a SURFTYPE_CUBE surface, this field controls whether 1342 //! the TC* Address Control Mode fields are interpreted as programmed or 1343 //! overridden to TEXCOORDMODE_CUBE. 1344 enum CUBE_SURFACE_CONTROL_MODE 1345 { 1346 CUBE_SURFACE_CONTROL_MODE_PROGRAMMED = 0, //!< No additional details 1347 CUBE_SURFACE_CONTROL_MODE_OVERRIDE = 1, //!< No additional details 1348 }; 1349 1350 //! \brief SHADOW_FUNCTION 1351 //! \details 1352 //! This field is used for shadow mapping support via the sample_c message 1353 //! type, and specifies the specific comparison operation to be used. The 1354 //! comparison is between the texture sample red channel (except for 1355 //! alpha-only formats which use the alpha channel), and the "ref" value 1356 //! provided in the input message. 1357 enum SHADOW_FUNCTION 1358 { 1359 SHADOW_FUNCTION_PREFILTEROPALWAYS = 0, //!< No additional details 1360 SHADOW_FUNCTION_PREFILTEROPNEVER = 1, //!< No additional details 1361 SHADOW_FUNCTION_PREFILTEROPLESS = 2, //!< No additional details 1362 SHADOW_FUNCTION_PREFILTEROPEQUAL = 3, //!< No additional details 1363 SHADOW_FUNCTION_PREFILTEROPLEQUAL = 4, //!< No additional details 1364 SHADOW_FUNCTION_PREFILTEROPGREATER = 5, //!< No additional details 1365 SHADOW_FUNCTION_PREFILTEROPNOTEQUAL = 6, //!< No additional details 1366 SHADOW_FUNCTION_PREFILTEROPGEQUAL = 7, //!< No additional details 1367 }; 1368 1369 //! \brief CHROMAKEY_MODE 1370 //! \details 1371 //! This field specifies the behavior of the device in the event of a 1372 //! ChromaKey match. This field is ignored if ChromaKey is disabled. 1373 enum CHROMAKEY_MODE 1374 { 1375 CHROMAKEY_MODE_KEYFILTERKILLONANYMATCH = 0, //!< In this mode, if any contributing texel matches the chroma key, the corresponding pixel mask bit for that pixel is cleared. The result of this operation is observable only if the Killed Pixel Mask Return flag is set on the input message. 1376 CHROMAKEY_MODE_KEYFILTERREPLACEBLACK = 1, //!< In this mode, each texel that matches the chroma key is replaced with (0,0,0,0) (black with alpha=0) prior to filtering. For YCrCb surface formats, the black value is A=0, R(Cr)=0x80, G(Y)=0x10, B(Cb)=0x80. This will tend to darken/fade edges of keyed regions. Note that the pixel pipeline must be programmed to use the resulting filtered texel value to gain the intended effect, e.g., handle the case of a totally keyed-out region (filtered texel alpha==0) through use of alpha test, etc. 1377 }; 1378 1379 //! \brief LOD_CLAMP_MAGNIFICATION_MODE 1380 //! \details 1381 //! This field allows the flexibility to control how LOD clamping is handled 1382 //! when in magnification mode. 1383 enum LOD_CLAMP_MAGNIFICATION_MODE 1384 { 1385 LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE = 0, //!< When in magnification mode, Sampler will clamp LOD as if the Mip Mode Filteris MIPFILTER_NONE. This is how OpenGL defines magnification, and therefore it isexpected that those drivers would not set this bit. 1386 LOD_CLAMP_MAGNIFICATION_MODE_MIPFILTER = 1, //!< When in magnification mode, Sampler will clamp LOD based on the value of Mip Mode Filter. 1387 }; 1388 1389 //! \brief TCZ_ADDRESS_CONTROL_MODE 1390 //! \details 1391 //! Controls how the 3rd (TCZ) component of input texture coordinates are 1392 //! mapped to texture map addresses - specifically, how coordinates 1393 //! "outside" the texture are handled (wrap/clamp/mirror).See Address TCX 1394 //! Control Mode above for details 1395 enum TCZ_ADDRESS_CONTROL_MODE 1396 { 1397 TCZ_ADDRESS_CONTROL_MODE_WRAP = 0, //!< No additional details 1398 TCZ_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< No additional details 1399 TCZ_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< No additional details 1400 TCZ_ADDRESS_CONTROL_MODE_CUBE = 3, //!< No additional details 1401 TCZ_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< No additional details 1402 TCZ_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< No additional details 1403 TCZ_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< No additional details 1404 }; 1405 1406 //! \brief TCY_ADDRESS_CONTROL_MODE 1407 //! \details 1408 //! Controls how the 2nd (TCY, aka V) component of input texture coordinates 1409 //! are mapped to texture map addresses - specifically, how coordinates 1410 //! "outside" the texture are handled (wrap/clamp/mirror). See Address TCX 1411 //! Control Mode above for details 1412 enum TCY_ADDRESS_CONTROL_MODE 1413 { 1414 TCY_ADDRESS_CONTROL_MODE_WRAP = 0, //!< No additional details 1415 TCY_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< No additional details 1416 TCY_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< No additional details 1417 TCY_ADDRESS_CONTROL_MODE_CUBE = 3, //!< No additional details 1418 TCY_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< No additional details 1419 TCY_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< No additional details 1420 TCY_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< No additional details 1421 }; 1422 1423 //! \brief TCX_ADDRESS_CONTROL_MODE 1424 //! \details 1425 //! Controls how the 1st (TCX, aka U) component of input texture coordinates 1426 //! are mapped to texture map addresses - specifically, how coordinates 1427 //! "outside" the texture are handled (wrap/clamp/mirror). The setting of 1428 //! this field is subject to being overridden by the Cube Surface Control 1429 //! Mode field when sampling from a SURFTYPE_CUBE surface. 1430 enum TCX_ADDRESS_CONTROL_MODE 1431 { 1432 TCX_ADDRESS_CONTROL_MODE_WRAP = 0, //!< No additional details 1433 TCX_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< No additional details 1434 TCX_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< No additional details 1435 TCX_ADDRESS_CONTROL_MODE_CUBE = 3, //!< No additional details 1436 TCX_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< No additional details 1437 TCX_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< No additional details 1438 TCX_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< No additional details 1439 }; 1440 1441 //! \brief TRILINEAR_FILTER_QUALITY 1442 //! \details 1443 //! Selects the quality level for the trilinear filter. 1444 enum TRILINEAR_FILTER_QUALITY 1445 { 1446 TRILINEAR_FILTER_QUALITY_FULL = 0, //!< Full Quality. Both mip maps are sampled under all circumstances. 1447 TRILINEAR_FILTER_QUALITY_TRIQUALHIGHMAGCLAMPMIPFILTER = 1, //!< High Quality. 1448 TRILINEAR_FILTER_QUALITY_MED = 2, //!< Medium Quality. 1449 TRILINEAR_FILTER_QUALITY_LOW = 3, //!< Low Quality. 1450 }; 1451 1452 //! \brief MAXIMUM_ANISOTROPY 1453 //! \details 1454 //! This field clamps the maximum value of the anisotropy ratio used by the 1455 //! MAPFILTER_ANISOTROPIC filter (Min or Mag Mode Filter). 1456 enum MAXIMUM_ANISOTROPY 1457 { 1458 MAXIMUM_ANISOTROPY_RATIO21 = 0, //!< At most a 2:1 aspect ratio filter is used 1459 MAXIMUM_ANISOTROPY_RATIO41 = 1, //!< At most a 4:1 aspect ratio filter is used 1460 MAXIMUM_ANISOTROPY_RATIO61 = 2, //!< At most a 6:1 aspect ratio filter is used 1461 MAXIMUM_ANISOTROPY_RATIO81 = 3, //!< At most a 8:1 aspect ratio filter is used 1462 MAXIMUM_ANISOTROPY_RATIO101 = 4, //!< At most a 10:1 aspect ratio filter is used 1463 MAXIMUM_ANISOTROPY_RATIO121 = 5, //!< At most a 12:1 aspect ratio filter is used 1464 MAXIMUM_ANISOTROPY_RATIO141 = 6, //!< At most a 14:1 aspect ratio filter is used 1465 MAXIMUM_ANISOTROPY_RATIO161 = 7, //!< At most a 16:1 aspect ratio filter is used 1466 }; 1467 1468 //! \name Initializations 1469 1470 //! \brief Explicit member initialization function 1471 SAMPLER_STATE_CMD(); 1472 1473 static const size_t dwSize = 4; 1474 static const size_t byteSize = 16; 1475 }; 1476 1477 //! 1478 //! \brief SAMPLER_STATE_8x8_AVS_COEFFICIENTS 1479 //! \details 1480 //! ExistsIf = AVS 1481 //! 1482 struct SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD 1483 { 1484 union 1485 { 1486 //!< DWORD 0 1487 struct 1488 { 1489 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,0] 1490 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,0] 1491 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,1] 1492 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,1] 1493 }; 1494 uint32_t Value; 1495 } DW0; 1496 union 1497 { 1498 //!< DWORD 1 1499 struct 1500 { 1501 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,2] 1502 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,2] 1503 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,3] 1504 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,3] 1505 }; 1506 uint32_t Value; 1507 } DW1; 1508 union 1509 { 1510 //!< DWORD 2 1511 struct 1512 { 1513 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,4] 1514 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,4] 1515 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,5] 1516 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,5] 1517 }; 1518 uint32_t Value; 1519 } DW2; 1520 union 1521 { 1522 //!< DWORD 3 1523 struct 1524 { 1525 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,6] 1526 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,6] 1527 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,7] 1528 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,7] 1529 }; 1530 uint32_t Value; 1531 } DW3; 1532 union 1533 { 1534 //!< DWORD 4 1535 struct 1536 { 1537 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1538 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[n,2] 1539 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1X Filter Coefficient[n,3] 1540 }; 1541 uint32_t Value; 1542 } DW4; 1543 union 1544 { 1545 //!< DWORD 5 1546 struct 1547 { 1548 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[n,4] 1549 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1X Filter Coefficient[n,5] 1550 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1551 }; 1552 uint32_t Value; 1553 } DW5; 1554 union 1555 { 1556 //!< DWORD 6 1557 struct 1558 { 1559 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1560 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1Y Filter Coefficient[n,2] 1561 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[n,3] 1562 }; 1563 uint32_t Value; 1564 } DW6; 1565 union 1566 { 1567 //!< DWORD 7 1568 struct 1569 { 1570 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1Y Filter Coefficient[n,4] 1571 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[n,5] 1572 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1573 }; 1574 uint32_t Value; 1575 } DW7; 1576 1577 //! \name Local enumerations 1578 1579 //! \name Initializations 1580 1581 //! \brief Explicit member initialization function 1582 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD(); 1583 1584 static const size_t dwSize = 8; 1585 static const size_t byteSize = 32; 1586 }; 1587 1588 //! 1589 //! \brief SAMPLER_STATE_8x8_AVS 1590 //! \details 1591 //! ExistsIf = AVS 1592 //! 1593 struct SAMPLER_STATE_8x8_AVS_CMD 1594 { 1595 union 1596 { 1597 //!< DWORD 0 1598 struct 1599 { 1600 uint32_t GainFactor : __CODEGEN_BITFIELD( 0, 5) ; //!< GAIN_FACTOR 1601 uint32_t WeakEdgeThreshold : __CODEGEN_BITFIELD( 6, 11) ; //!< WEAK_EDGE_THRESHOLD 1602 uint32_t StrongEdgeThreshold : __CODEGEN_BITFIELD(12, 17) ; //!< STRONG_EDGE_THRESHOLD 1603 uint32_t R3XCoefficient : __CODEGEN_BITFIELD(18, 22) ; //!< R3X_COEFFICIENT 1604 uint32_t R3CCoefficient : __CODEGEN_BITFIELD(23, 27) ; //!< R3C_COEFFICIENT 1605 uint32_t Reserved28 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1606 }; 1607 uint32_t Value; 1608 } DW0; 1609 union 1610 { 1611 //!< DWORD 1 1612 struct 1613 { 1614 uint32_t Reserved32 ; //!< Reserved 1615 }; 1616 uint32_t Value; 1617 } DW1; 1618 union 1619 { 1620 //!< DWORD 2 1621 struct 1622 { 1623 uint32_t GlobalNoiseEstimation : __CODEGEN_BITFIELD( 0, 7) ; //!< GLOBAL_NOISE_ESTIMATION 1624 uint32_t NonEdgeWeight : __CODEGEN_BITFIELD( 8, 10) ; //!< NON_EDGE_WEIGHT 1625 uint32_t RegularWeight : __CODEGEN_BITFIELD(11, 13) ; //!< REGULAR_WEIGHT 1626 uint32_t StrongEdgeWeight : __CODEGEN_BITFIELD(14, 16) ; //!< STRONG_EDGE_WEIGHT 1627 uint32_t R5XCoefficient : __CODEGEN_BITFIELD(17, 21) ; //!< R5X_COEFFICIENT 1628 uint32_t R5CxCoefficient : __CODEGEN_BITFIELD(22, 26) ; //!< R5CX_COEFFICIENT 1629 uint32_t R5CCoefficient : __CODEGEN_BITFIELD(27, 31) ; //!< R5C_COEFFICIENT 1630 }; 1631 uint32_t Value; 1632 } DW2; 1633 union 1634 { 1635 //!< DWORD 3 1636 struct 1637 { 1638 uint32_t SinAlpha : __CODEGEN_BITFIELD( 0, 7) ; //!< Sin(alpha) 1639 uint32_t CosAlpha : __CODEGEN_BITFIELD( 8, 15) ; //!< Cos(alpha) 1640 uint32_t SatMax : __CODEGEN_BITFIELD(16, 21) ; //!< SAT_MAX 1641 uint32_t HueMax : __CODEGEN_BITFIELD(22, 27) ; //!< HUE_MAX 1642 uint32_t Enable8TapFilter : __CODEGEN_BITFIELD(28, 29) ; //!< ENABLE_8_TAP_FILTER 1643 uint32_t Ief4SmoothEnable : __CODEGEN_BITFIELD(30, 30) ; //!< IEF4SMOOTH_ENABLE_ 1644 uint32_t SkinToneTunedIefEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SKIN_TONE_TUNED_IEF__ENABLE 1645 }; 1646 uint32_t Value; 1647 } DW3; 1648 union 1649 { 1650 //!< DWORD 4 1651 struct 1652 { 1653 uint32_t S3U : __CODEGEN_BITFIELD( 0, 10) ; //!< S3U 1654 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1655 uint32_t DiamondMargin : __CODEGEN_BITFIELD(12, 14) ; //!< DIAMOND_MARGIN 1656 uint32_t VyStdEnable : __CODEGEN_BITFIELD(15, 15) ; //!< VY_STD_Enable 1657 uint32_t UMid : __CODEGEN_BITFIELD(16, 23) ; //!< U_MID 1658 uint32_t VMid : __CODEGEN_BITFIELD(24, 31) ; //!< V_MID 1659 }; 1660 uint32_t Value; 1661 } DW4; 1662 union 1663 { 1664 //!< DWORD 5 1665 struct 1666 { 1667 uint32_t DiamondDv : __CODEGEN_BITFIELD( 0, 6) ; //!< DIAMOND_DV 1668 uint32_t DiamondTh : __CODEGEN_BITFIELD( 7, 12) ; //!< DIAMOND_TH 1669 uint32_t DiamondAlpha : __CODEGEN_BITFIELD(13, 20) ; //!< Diamond_alpha 1670 uint32_t HsMargin : __CODEGEN_BITFIELD(21, 23) ; //!< HS_MARGIN 1671 uint32_t DiamondDu : __CODEGEN_BITFIELD(24, 30) ; //!< DIAMOND_DU 1672 uint32_t Skindetailfactor : __CODEGEN_BITFIELD(31, 31) ; //!< SKINDETAILFACTOR_ 1673 }; 1674 uint32_t Value; 1675 } DW5; 1676 union 1677 { 1678 //!< DWORD 6 1679 struct 1680 { 1681 uint32_t YPoint1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y_POINT_1 1682 uint32_t YPoint2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y_POINT_2 1683 uint32_t YPoint3 : __CODEGEN_BITFIELD(16, 23) ; //!< Y_POINT_3 1684 uint32_t YPoint4 : __CODEGEN_BITFIELD(24, 31) ; //!< Y_POINT_4 1685 }; 1686 uint32_t Value; 1687 } DW6; 1688 union 1689 { 1690 //!< DWORD 7 1691 struct 1692 { 1693 uint32_t InvMarginVyl : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYL 1694 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1695 }; 1696 uint32_t Value; 1697 } DW7; 1698 union 1699 { 1700 //!< DWORD 8 1701 struct 1702 { 1703 uint32_t InvMarginVyu : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYU 1704 uint32_t P0L : __CODEGEN_BITFIELD(16, 23) ; //!< P0L 1705 uint32_t P1L : __CODEGEN_BITFIELD(24, 31) ; //!< P1L 1706 }; 1707 uint32_t Value; 1708 } DW8; 1709 union 1710 { 1711 //!< DWORD 9 1712 struct 1713 { 1714 uint32_t P2L : __CODEGEN_BITFIELD( 0, 7) ; //!< P2L 1715 uint32_t P3L : __CODEGEN_BITFIELD( 8, 15) ; //!< P3L 1716 uint32_t B0L : __CODEGEN_BITFIELD(16, 23) ; //!< B0L 1717 uint32_t B1L : __CODEGEN_BITFIELD(24, 31) ; //!< B1L 1718 }; 1719 uint32_t Value; 1720 } DW9; 1721 union 1722 { 1723 //!< DWORD 10 1724 struct 1725 { 1726 uint32_t B2L : __CODEGEN_BITFIELD( 0, 7) ; //!< B2L 1727 uint32_t B3L : __CODEGEN_BITFIELD( 8, 15) ; //!< B3L 1728 uint32_t S0L : __CODEGEN_BITFIELD(16, 26) ; //!< S0L 1729 uint32_t YSlope2 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope_2 1730 }; 1731 uint32_t Value; 1732 } DW10; 1733 union 1734 { 1735 //!< DWORD 11 1736 struct 1737 { 1738 uint32_t S1L : __CODEGEN_BITFIELD( 0, 10) ; //!< S1L 1739 uint32_t S2L : __CODEGEN_BITFIELD(11, 21) ; //!< S2L 1740 uint32_t Reserved374 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 1741 }; 1742 uint32_t Value; 1743 } DW11; 1744 union 1745 { 1746 //!< DWORD 12 1747 struct 1748 { 1749 uint32_t S3L : __CODEGEN_BITFIELD( 0, 10) ; //!< S3L 1750 uint32_t P0U : __CODEGEN_BITFIELD(11, 18) ; //!< P0U 1751 uint32_t P1U : __CODEGEN_BITFIELD(19, 26) ; //!< P1U 1752 uint32_t YSlope1 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope1 1753 }; 1754 uint32_t Value; 1755 } DW12; 1756 union 1757 { 1758 //!< DWORD 13 1759 struct 1760 { 1761 uint32_t P2U : __CODEGEN_BITFIELD( 0, 7) ; //!< P2U 1762 uint32_t P3U : __CODEGEN_BITFIELD( 8, 15) ; //!< P3U 1763 uint32_t B0U : __CODEGEN_BITFIELD(16, 23) ; //!< B0U 1764 uint32_t B1U : __CODEGEN_BITFIELD(24, 31) ; //!< B1U 1765 }; 1766 uint32_t Value; 1767 } DW13; 1768 union 1769 { 1770 //!< DWORD 14 1771 struct 1772 { 1773 uint32_t B2U : __CODEGEN_BITFIELD( 0, 7) ; //!< B2U 1774 uint32_t B3U : __CODEGEN_BITFIELD( 8, 15) ; //!< B3U 1775 uint32_t S0U : __CODEGEN_BITFIELD(16, 26) ; //!< S0U 1776 uint32_t Reserved475 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1777 }; 1778 uint32_t Value; 1779 } DW14; 1780 union 1781 { 1782 //!< DWORD 15 1783 struct 1784 { 1785 uint32_t S1U : __CODEGEN_BITFIELD( 0, 10) ; //!< S1U 1786 uint32_t S2U : __CODEGEN_BITFIELD(11, 21) ; //!< S2U 1787 uint32_t Reserved502 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 1788 }; 1789 uint32_t Value; 1790 } DW15; 1791 1792 mhw_state_heap_g8_X::SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient016[17]; //!< Filter Coefficient[0..16] 1793 1794 union 1795 { 1796 //!< DWORD 152 1797 struct 1798 { 1799 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 1800 uint32_t Reserved4867 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 1801 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 1802 uint32_t Reserved4871 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 1803 uint32_t MaxDerivative8Pixels : __CODEGEN_BITFIELD( 8, 15) ; //!< Max Derivative 8 Pixels 1804 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 1805 uint32_t DefaultSharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< DEFAULT_SHARPNESS_LEVEL 1806 }; 1807 uint32_t Value; 1808 } DW152; 1809 union 1810 { 1811 //!< DWORD 153 1812 struct 1813 { 1814 uint32_t RgbAdaptive : __CODEGEN_BITFIELD( 0, 0) ; //!< RGB_ADAPTIVE 1815 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1816 uint32_t Reserved4898 : __CODEGEN_BITFIELD( 2, 20) ; //!< Reserved 1817 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD(21, 21) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 1818 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD(22, 22) ; //!< BYPASS_X_ADAPTIVE_FILTERING 1819 uint32_t Reserved4919 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 1820 }; 1821 uint32_t Value; 1822 } DW153; 1823 1824 //! \name Local enumerations 1825 1826 //! \brief GAIN_FACTOR 1827 //! \details 1828 //! User control sharpening strength 1829 enum GAIN_FACTOR 1830 { 1831 GAIN_FACTOR_UNNAMED44 = 44, //!< No additional details 1832 }; 1833 1834 //! \brief WEAK_EDGE_THRESHOLD 1835 //! \details 1836 //! If <b>Strong Edge Threshold</b> > EM > <b>Weak Edge Threshold</b>, 1837 //! the basic VSA detects a weak edge. 1838 enum WEAK_EDGE_THRESHOLD 1839 { 1840 WEAK_EDGE_THRESHOLD_UNNAMED1 = 1, //!< No additional details 1841 }; 1842 1843 //! \brief STRONG_EDGE_THRESHOLD 1844 //! \details 1845 //! If EM > <b>Strong Edge Threshold</b>, the basic VSA detects a strong 1846 //! edge. 1847 enum STRONG_EDGE_THRESHOLD 1848 { 1849 STRONG_EDGE_THRESHOLD_UNNAMED8 = 8, //!< No additional details 1850 }; 1851 1852 //! \brief R3X_COEFFICIENT 1853 //! \details 1854 //! IEF smoothing coefficient, see IEF map. 1855 enum R3X_COEFFICIENT 1856 { 1857 R3X_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 1858 }; 1859 1860 //! \brief R3C_COEFFICIENT 1861 //! \details 1862 //! IEF smoothing coefficient, see IEF map. 1863 enum R3C_COEFFICIENT 1864 { 1865 R3C_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 1866 }; 1867 1868 //! \brief GLOBAL_NOISE_ESTIMATION 1869 //! \details 1870 //! Global noise estimation of previous frame. 1871 enum GLOBAL_NOISE_ESTIMATION 1872 { 1873 GLOBAL_NOISE_ESTIMATION_UNNAMED255 = 255, //!< No additional details 1874 }; 1875 1876 //! \brief NON_EDGE_WEIGHT 1877 //! \details 1878 //! Sharpening strength when no edge is found in basic VSA. 1879 enum NON_EDGE_WEIGHT 1880 { 1881 NON_EDGE_WEIGHT_UNNAMED1 = 1, //!< No additional details 1882 }; 1883 1884 //! \brief REGULAR_WEIGHT 1885 //! \details 1886 //! Sharpening strength when a weak edge is found in basic VSA. 1887 enum REGULAR_WEIGHT 1888 { 1889 REGULAR_WEIGHT_UNNAMED2 = 2, //!< No additional details 1890 }; 1891 1892 //! \brief STRONG_EDGE_WEIGHT 1893 //! \details 1894 //! Sharpening strength when a strong edge is found in basic VSA. 1895 enum STRONG_EDGE_WEIGHT 1896 { 1897 STRONG_EDGE_WEIGHT_UNNAMED7 = 7, //!< No additional details 1898 }; 1899 1900 //! \brief R5X_COEFFICIENT 1901 //! \details 1902 //! IEF smoothing coefficient, see IEF map. 1903 enum R5X_COEFFICIENT 1904 { 1905 R5X_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 1906 }; 1907 1908 //! \brief R5CX_COEFFICIENT 1909 //! \details 1910 //! IEF smoothing coefficient, see IEF map. 1911 enum R5CX_COEFFICIENT 1912 { 1913 R5CX_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 1914 }; 1915 1916 //! \brief R5C_COEFFICIENT 1917 //! \details 1918 //! IEF smoothing coefficient, see IEF map. 1919 enum R5C_COEFFICIENT 1920 { 1921 R5C_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 1922 }; 1923 1924 //! \brief SAT_MAX 1925 //! \details 1926 //! Rectangle half length 1927 enum SAT_MAX 1928 { 1929 SAT_MAX_UNNAMED31 = 31, //!< No additional details 1930 }; 1931 1932 //! \brief HUE_MAX 1933 //! \details 1934 //! Rectangle half width. 1935 enum HUE_MAX 1936 { 1937 HUE_MAX_UNNAMED14 = 14, //!< No additional details 1938 }; 1939 1940 //! \brief ENABLE_8_TAP_FILTER 1941 //! \details 1942 //! <i><b>Adaptive Filtering (Mode = 11) ExistsIf:</b></i> 1943 //! <p></p> R10G10B10A2_UNORM R8G8B8A8_UNORM (AYUV also) R8B8G8A8_UNORM 1944 //! B8G8R8A8_UNORM R16G16B16A16 1945 enum ENABLE_8_TAP_FILTER 1946 { 1947 ENABLE_8_TAP_FILTER_UNNAMED0 = 0, //!< 4-tap filter is only done on all channels. 1948 ENABLE_8_TAP_FILTER_UNNAMED1 = 1, //!< Enable 8-tap Adaptive filter on G-channel. 4-tap filter on other channels. 1949 ENABLE_8_TAP_FILTER_UNNAMED2 = 2, //!< 8-tap filter is done on all channels (UV-ch uses the Y-coefficients) 1950 ENABLE_8_TAP_FILTER_UNNAMED3 = 3, //!< Enable 8-tap Adaptive filter all channels (UV-ch uses the Y-coefficients). 1951 }; 1952 1953 enum IEF4SMOOTH_ENABLE_ 1954 { 1955 IEF4SMOOTH_ENABLE_UNNAMED0 = 0, //!< IEF is operating as a content adaptive detail filter based on 5x5 region 1956 IEF4SMOOTH_ENABLE_UNNAMED1 = 1, //!< IEF is operating as a content adaptive smooth filter based on 3x3 region 1957 }; 1958 1959 //! \brief SKIN_TONE_TUNED_IEF__ENABLE 1960 //! \details 1961 //! Control bit to enable the skin tone tuned IEF. 1962 enum SKIN_TONE_TUNED_IEF__ENABLE 1963 { 1964 SKIN_TONE_TUNED_IEF_ENABLE_UNNAMED1 = 1, //!< No additional details 1965 }; 1966 1967 enum DIAMOND_MARGIN 1968 { 1969 DIAMOND_MARGIN_UNNAMED4 = 4, //!< No additional details 1970 }; 1971 1972 //! \brief U_MID 1973 //! \details 1974 //! Rectangle middle-point U coordinate. 1975 enum U_MID 1976 { 1977 U_MID_UNNAMED110 = 110, //!< No additional details 1978 }; 1979 1980 //! \brief V_MID 1981 //! \details 1982 //! Rectangle middle-point V coordinate. 1983 enum V_MID 1984 { 1985 V_MID_UNNAMED154 = 154, //!< No additional details 1986 }; 1987 1988 //! \brief DIAMOND_DV 1989 //! \details 1990 //! Rhombus center shift in the hue-direction, relative to the rectangle 1991 //! center. 1992 enum DIAMOND_DV 1993 { 1994 DIAMOND_DV_UNNAMED0 = 0, //!< No additional details 1995 }; 1996 1997 //! \brief DIAMOND_TH 1998 //! \details 1999 //! Half length of the rhombus axis in the sat-direction. 2000 enum DIAMOND_TH 2001 { 2002 DIAMOND_TH_UNNAMED35 = 35, //!< No additional details 2003 }; 2004 2005 //! \brief HS_MARGIN 2006 //! \details 2007 //! Defines rectangle margin 2008 enum HS_MARGIN 2009 { 2010 HS_MARGIN_UNNAMED3 = 3, //!< No additional details 2011 }; 2012 2013 //! \brief DIAMOND_DU 2014 //! \details 2015 //! Rhombus center shift in the sat-direction, relative to the rectangle 2016 //! center. 2017 enum DIAMOND_DU 2018 { 2019 DIAMOND_DU_UNNAMED2 = 2, //!< No additional details 2020 }; 2021 2022 //! \brief SKINDETAILFACTOR_ 2023 //! \details 2024 //! This flag bit is in operation only when the control bit <b>Skin Tone 2025 //! TunedIEF_Enable</b> is on. 2026 enum SKINDETAILFACTOR_ 2027 { 2028 SKINDETAILFACTOR_UNNAMED0 = 0, //!< sign(SkinDetailFactor) is equal to -1, and the content of the detected skin tone area is detail revealed. 2029 SKINDETAILFACTOR_UNNAMED1 = 1, //!< sign(SkinDetailFactor) is equal to +1, and the content of the detected skin tone area is not detail revealed. 2030 }; 2031 2032 //! \brief Y_POINT_1 2033 //! \details 2034 //! First point of the Y piecewise linear membership function. 2035 enum Y_POINT_1 2036 { 2037 Y_POINT_1_UNNAMED46 = 46, //!< No additional details 2038 }; 2039 2040 //! \brief Y_POINT_2 2041 //! \details 2042 //! Second point of the Y piecewise linear membership function. 2043 enum Y_POINT_2 2044 { 2045 Y_POINT_2_UNNAMED47 = 47, //!< No additional details 2046 }; 2047 2048 //! \brief Y_POINT_3 2049 //! \details 2050 //! Third point of the Y piecewise linear membership function. 2051 enum Y_POINT_3 2052 { 2053 Y_POINT_3_UNNAMED254 = 254, //!< No additional details 2054 }; 2055 2056 //! \brief Y_POINT_4 2057 //! \details 2058 //! Fourth point of the Y piecewise linear membership function. 2059 enum Y_POINT_4 2060 { 2061 Y_POINT_4_UNNAMED255 = 255, //!< No additional details 2062 }; 2063 2064 //! \brief P0L 2065 //! \details 2066 //! Y Point 0 of the lower part of the detection PWLF. 2067 enum P0L 2068 { 2069 P0L_UNNAMED46 = 46, //!< No additional details 2070 }; 2071 2072 //! \brief P1L 2073 //! \details 2074 //! Y Point 1 of the lower part of the detection PWLF. 2075 enum P1L 2076 { 2077 P1L_UNNAMED216 = 216, //!< No additional details 2078 }; 2079 2080 //! \brief P2L 2081 //! \details 2082 //! Y Point 2 of the lower part of the detection PWLF. 2083 enum P2L 2084 { 2085 P2L_UNNAMED236 = 236, //!< No additional details 2086 }; 2087 2088 //! \brief P3L 2089 //! \details 2090 //! Y Point 3 of the lower part of the detection PWLF. 2091 enum P3L 2092 { 2093 P3L_UNNAMED236 = 236, //!< No additional details 2094 }; 2095 2096 //! \brief B0L 2097 //! \details 2098 //! V Bias 0 of the lower part of the detection PWLF. 2099 enum B0L 2100 { 2101 B0L_UNNAMED133 = 133, //!< No additional details 2102 }; 2103 2104 //! \brief B1L 2105 //! \details 2106 //! V Bias 1 of the lower part of the detection PWLF. 2107 enum B1L 2108 { 2109 B1L_UNNAMED130 = 130, //!< No additional details 2110 }; 2111 2112 enum B2L 2113 { 2114 B2L_UNNAMED130 = 130, //!< No additional details 2115 }; 2116 2117 //! \brief B3L 2118 //! \details 2119 //! V Bias 3 of the lower part of the detection PWLF. 2120 enum B3L 2121 { 2122 B3L_UNNAMED130 = 130, //!< No additional details 2123 }; 2124 2125 //! \brief P0U 2126 //! \details 2127 //! Y Point 0 of the upper part of the detection PWLF. 2128 enum P0U 2129 { 2130 P0U_UNNAMED46 = 46, //!< No additional details 2131 }; 2132 2133 //! \brief P1U 2134 //! \details 2135 //! Y Point 1 of the upper part of the detection PWLF. 2136 enum P1U 2137 { 2138 P1U_UNNAMED66 = 66, //!< No additional details 2139 }; 2140 2141 //! \brief P2U 2142 //! \details 2143 //! Y Point 2 of the upper part of the detection PWLF. 2144 enum P2U 2145 { 2146 P2U_UNNAMED150 = 150, //!< No additional details 2147 }; 2148 2149 //! \brief P3U 2150 //! \details 2151 //! Y Point 3 of the upper part of the detection PWLF. 2152 enum P3U 2153 { 2154 P3U_UNNAMED236 = 236, //!< No additional details 2155 }; 2156 2157 //! \brief B0U 2158 //! \details 2159 //! V Bias 0 of the upper part of the detection PWLF. 2160 enum B0U 2161 { 2162 B0U_UNNAMED143 = 143, //!< No additional details 2163 }; 2164 2165 //! \brief B1U 2166 //! \details 2167 //! V Bias 1 of the upper part of the detection PWLF. 2168 enum B1U 2169 { 2170 B1U_UNNAMED163 = 163, //!< No additional details 2171 }; 2172 2173 //! \brief B2U 2174 //! \details 2175 //! V Bias 2 of the upper part of the detection PWLF. 2176 enum B2U 2177 { 2178 B2U_UNNAMED200 = 200, //!< No additional details 2179 }; 2180 2181 //! \brief B3U 2182 //! \details 2183 //! V Bias 3 of the upper part of the detection PWLF. 2184 enum B3U 2185 { 2186 B3U_UNNAMED140 = 140, //!< No additional details 2187 }; 2188 2189 //! \brief DEFAULT_SHARPNESS_LEVEL 2190 //! \details 2191 //! When adaptive scaling is off, determines the balance between sharp and 2192 //! smooth scalers. 2193 enum DEFAULT_SHARPNESS_LEVEL 2194 { 2195 DEFAULT_SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 2196 DEFAULT_SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 2197 }; 2198 2199 //! \brief RGB_ADAPTIVE 2200 //! \details 2201 //! This should be always set to 0 for YUV input and can be enabled/disabled 2202 //! for RGB input. 2203 //! This should be enabled only if we enable 8-tap adaptive filter for 2204 //! RGB input. 2205 enum RGB_ADAPTIVE 2206 { 2207 RGB_ADAPTIVE_DISBLE = 0, //!< Disable the RGB Adaptive equation and use G-Ch directly for adaptive filter 2208 RGB_ADAPTIVE_ENABLE = 1, //!< Enable the RGB Adaptive filter using the equation (Y=(R+2G+B)>>2) 2209 }; 2210 2211 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2212 //! \details 2213 //! Only to be enabled if 8-tap Adaptive filter mode is on, eElse it should 2214 //! be disabled. 2215 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2216 { 2217 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISBLE = 0, //!< Disable Adaptive Filter on UV/RB Channels 2218 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLE = 1, //!< Enable Adaptive Filter on UV/RB Channels 2219 }; 2220 2221 //! \brief BYPASS_Y_ADAPTIVE_FILTERING 2222 //! \details 2223 //! When disabled, the Y direction will use <b>Default Sharpness Level</b> 2224 //! to blend between the smooth and sharp filters rather than the calculated 2225 //! value. 2226 enum BYPASS_Y_ADAPTIVE_FILTERING 2227 { 2228 BYPASS_Y_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable Y Adaptive Filtering 2229 BYPASS_Y_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable Y Adaptive Filtering 2230 }; 2231 2232 //! \brief BYPASS_X_ADAPTIVE_FILTERING 2233 //! \details 2234 //! When disabled, the X direction will use <b>Default Sharpness Level</b> 2235 //! to blend between the smooth and sharp filters rather than the calculated 2236 //! value. 2237 enum BYPASS_X_ADAPTIVE_FILTERING 2238 { 2239 BYPASS_X_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable X Adaptive Filtering 2240 BYPASS_X_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable X Adaptive Filtering 2241 }; 2242 2243 //! \name Initializations 2244 2245 //! \brief Explicit member initialization function 2246 SAMPLER_STATE_8x8_AVS_CMD(); 2247 2248 static const size_t dwSize = 154; 2249 static const size_t byteSize = 616; 2250 }; 2251 2252 //! 2253 //! \brief SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS 2254 //! \details 2255 //! Function: 0001b ExistsIf: [Convolve] && [(Kernel Size) =< 2256 //! (15x15)] 2257 //! 2258 struct SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS_CMD 2259 { 2260 union 2261 { 2262 //!< DWORD 0 2263 struct 2264 { 2265 uint32_t FilterCoefficient00 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,0] 2266 uint32_t FilterCoefficient01 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,1] 2267 }; 2268 uint32_t Value; 2269 } DW0; 2270 union 2271 { 2272 //!< DWORD 1 2273 struct 2274 { 2275 uint32_t FilterCoefficient02 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,2] 2276 uint32_t FilterCoefficient03 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,3] 2277 }; 2278 uint32_t Value; 2279 } DW1; 2280 union 2281 { 2282 //!< DWORD 2 2283 struct 2284 { 2285 uint32_t FilterCoefficient04 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,4] 2286 uint32_t FilterCoefficient05 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,5] 2287 }; 2288 uint32_t Value; 2289 } DW2; 2290 union 2291 { 2292 //!< DWORD 3 2293 struct 2294 { 2295 uint32_t FilterCoefficient06 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,6] 2296 uint32_t FilterCoefficient07 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,7] 2297 }; 2298 uint32_t Value; 2299 } DW3; 2300 union 2301 { 2302 //!< DWORD 4 2303 struct 2304 { 2305 uint32_t FilterCoefficient08 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,8] 2306 uint32_t FilterCoefficient09 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,9] 2307 }; 2308 uint32_t Value; 2309 } DW4; 2310 union 2311 { 2312 //!< DWORD 5 2313 struct 2314 { 2315 uint32_t FilterCoefficient010 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,10] 2316 uint32_t FilterCoefficient011 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,11] 2317 }; 2318 uint32_t Value; 2319 } DW5; 2320 union 2321 { 2322 //!< DWORD 6 2323 struct 2324 { 2325 uint32_t FilterCoefficient012 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,12] 2326 uint32_t FilterCoefficient013 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,13] 2327 }; 2328 uint32_t Value; 2329 } DW6; 2330 union 2331 { 2332 //!< DWORD 7 2333 struct 2334 { 2335 uint32_t FilterCoefficient014 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,14] 2336 uint32_t FilterCoefficient015 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,15] 2337 }; 2338 uint32_t Value; 2339 } DW7; 2340 2341 //! \name Local enumerations 2342 2343 //! \name Initializations 2344 2345 //! \brief Explicit member initialization function 2346 SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS_CMD(); 2347 2348 static const size_t dwSize = 8; 2349 static const size_t byteSize = 32; 2350 }; 2351 2352 //! 2353 //! \brief SAMPLER_STATE_8x8_CONVOLVE 2354 //! \details 2355 //! Function: 0001b ExistsIf: [Convolve] && [(Kernel Size) =< 2356 //! (15x15)] 2357 //! 2358 struct SAMPLER_STATE_8x8_CONVOLVE_CMD 2359 { 2360 union 2361 { 2362 //!< DWORD 0 2363 struct 2364 { 2365 uint32_t Height : __CODEGEN_BITFIELD( 0, 3) ; //!< HEIGHT 2366 uint32_t Width : __CODEGEN_BITFIELD( 4, 7) ; //!< WIDTH 2367 uint32_t ScaleDownValue : __CODEGEN_BITFIELD( 8, 11) ; //!< Scale down value 2368 uint32_t SizeOfTheCoefficient : __CODEGEN_BITFIELD(12, 12) ; //!< SIZE_OF_THE_COEFFICIENT 2369 uint32_t Reserved13 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 2370 }; 2371 uint32_t Value; 2372 } DW0; 2373 2374 uint32_t Reserved32[15]; //!< Reserved 2375 2376 mhw_state_heap_g8_X::SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS_CMD FilterCoefficient150150[16]; //!< Filter Coefficient[15:0,15:0] 2377 2378 uint32_t Reserved4608[368]; //!< Reserved 2379 2380 //! \name Local enumerations 2381 2382 enum SIZE_OF_THE_COEFFICIENT 2383 { 2384 SIZE_OF_THE_COEFFICIENT_8BIT = 0, //!< The lower 8 bits of the accumulator is forced to zero or ignored during the accumulation operation. 2385 SIZE_OF_THE_COEFFICIENT_16BIT = 1, //!< The lower 8 bits are also included for the operation. The final result of the accumulator is shifted before clamping the result as specified by the Scale down value.:Result[15:0] = Clamp(Accum[40:12] >> scale_down) 2386 }; 2387 2388 //! \name Initializations 2389 2390 //! \brief Explicit member initialization function 2391 SAMPLER_STATE_8x8_CONVOLVE_CMD(); 2392 2393 static const size_t dwSize = 512; 2394 static const size_t byteSize = 2048; 2395 }; 2396 2397 //! 2398 //! \brief SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER 2399 //! \details 2400 //! The table is valid for the following funstions: 0100 - Erode 0101 - 2401 //! Dilate 0011 - MinMaxFilter 2402 //! 2403 //! Max kernel size is 15x15. For sizes less than 15x15 the coefficients not 2404 //! used should be zeroed out. 2405 //! 2406 struct SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER_CMD 2407 { 2408 union 2409 { 2410 //!< DWORD 0 2411 struct 2412 { 2413 uint32_t HeightOfTheKernel : __CODEGEN_BITFIELD( 0, 3) ; //!< Height Of The Kernel 2414 uint32_t WidthOfTheKernel : __CODEGEN_BITFIELD( 4, 7) ; //!< Width Of The Kernel 2415 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 2416 uint32_t BitMask16ForRow0150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row0 [15:0] 2417 }; 2418 uint32_t Value; 2419 } DW0; 2420 union 2421 { 2422 //!< DWORD 1 2423 struct 2424 { 2425 uint32_t BitMask16ForRow1150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row1 [15:0] 2426 uint32_t BitMask16ForRow2150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row2 [15:0] 2427 }; 2428 uint32_t Value; 2429 } DW1; 2430 union 2431 { 2432 //!< DWORD 2 2433 struct 2434 { 2435 uint32_t BitMask16ForRow3150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row3 [15:0] 2436 uint32_t BitMask16ForRow4150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row4 [15:0] 2437 }; 2438 uint32_t Value; 2439 } DW2; 2440 union 2441 { 2442 //!< DWORD 3 2443 struct 2444 { 2445 uint32_t BitMask16ForRow5150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row5 [15:0] 2446 uint32_t BitMask16ForRow6150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row6 [15:0] 2447 }; 2448 uint32_t Value; 2449 } DW3; 2450 union 2451 { 2452 //!< DWORD 4 2453 struct 2454 { 2455 uint32_t BitMask16ForRow7150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row7 [15:0] 2456 uint32_t BitMask16ForRow8150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row8 [15:0] 2457 }; 2458 uint32_t Value; 2459 } DW4; 2460 union 2461 { 2462 //!< DWORD 5 2463 struct 2464 { 2465 uint32_t BitMask16ForRow9150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row9 [15:0] 2466 uint32_t BitMask16ForRow10150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row10 [15:0] 2467 }; 2468 uint32_t Value; 2469 } DW5; 2470 union 2471 { 2472 //!< DWORD 6 2473 struct 2474 { 2475 uint32_t BitMask16ForRow11150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row11 [15:0] 2476 uint32_t BitMask16ForRow12150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row12 [15:0] 2477 }; 2478 uint32_t Value; 2479 } DW6; 2480 union 2481 { 2482 //!< DWORD 7 2483 struct 2484 { 2485 uint32_t BitMask16ForRow13150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row13 [15:0] 2486 uint32_t BitMask16ForRow14150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row14 [15:0] 2487 }; 2488 uint32_t Value; 2489 } DW7; 2490 2491 //! \name Local enumerations 2492 2493 //! \name Initializations 2494 2495 //! \brief Explicit member initialization function 2496 SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER_CMD(); 2497 2498 static const size_t dwSize = 8; 2499 static const size_t byteSize = 32; 2500 }; 2501 2502 //! 2503 //! \brief SAMPLER_INDIRECT_STATE 2504 //! \details 2505 //! Note: There are three variations of this structure, defined separately 2506 //! because their payloads have different lengths. Currently only 2507 //! SAMPLER_INDIRECT_STATE_BORDER_COLOR is fully defined. 2508 //! This structure is pointed to by Indirect State Pointer (SAMPLER_STATE). 2509 //! The interpretation of the border color depends on the Texture Border 2510 //! Color Mode field in SAMPLER_STATE as follows: 2511 //! 2512 //! In 8BIT mode, the border color is 8-bit UNORM format, regardless of the 2513 //! surface format chosen. For surface formats with one or more channels 2514 //! missing (i.e. R5G6R5_UNORM is missing the alpha channel), the value from 2515 //! the border color, if selected, will be used even for the missing 2516 //! channels. 2517 //! 2518 //! In OGL mode, the format of the border color is R32G32B32A32_FLOAT, 2519 //! R32G32B32A32_SINT, or R32G32B32A32_UINT, depending on the surface format 2520 //! chosen. For surface formats with one or more channels missing, the value 2521 //! from the border color is not used for the missing channels, resulting in 2522 //! these channels resulting in the overall default value (0 for colors and 2523 //! 1 for alpha) regardless of whether border color is chosen. The surface 2524 //! formats with "L" and "I" have special behavior with respect to the 2525 //! border color. The border color value used for the replicated channels 2526 //! (RGB for "L" formats and RGBA for "I" formats) comes from the red 2527 //! channel of border color. In these cases, the green and blue channels, 2528 //! and also alpha for "I", of the border color are ignored. 2529 //! 2530 //! 2531 //! 2532 //! 2533 //! 2534 //! The format of this state depends on the Texture Border Color Mode field. 2535 //! 2536 //! 8BIT mode is not supported for surfaces with more than 16 bits in any 2537 //! channel, other than 32-bit float formats which are supported. 2538 //! The conditions under which this color is used depend on the Surface 2539 //! Type - 1D/2D/3D surfaces use the border color when the coordinates 2540 //! extend beyond the surface extent; cube surfaces use the border color for 2541 //! "empty" (disabled) faces. 2542 //! The border color itself is accessed through the texture cache hierarchy 2543 //! rather than the state cache hierarchy. Thus, if the border color is 2544 //! changed in memory, the texture cache must be invalidated and the state 2545 //! cache does not need to be invalidated. 2546 //! MAPFILTER_MONO: The border color is ignored. Border color is fixed at 2547 //! a value of 0 by hardware. 2548 //! 2549 //! 2550 struct SAMPLER_INDIRECT_STATE_CMD 2551 { 2552 union 2553 { 2554 //!< DWORD 0 2555 struct 2556 { 2557 uint32_t BorderColorRed ; //!< Border Color Red, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2558 } Obj0; 2559 struct 2560 { 2561 uint32_t BorderColorRed : __CODEGEN_BITFIELD( 0, 7) ; //!< Border Color Red, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2562 uint32_t BorderColorGreen : __CODEGEN_BITFIELD( 8, 15) ; //!< Border Color Green, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2563 uint32_t BorderColorBlue : __CODEGEN_BITFIELD(16, 23) ; //!< Border Color Blue, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2564 uint32_t BorderColorAlpha : __CODEGEN_BITFIELD(24, 31) ; //!< Border Color Alpha, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2565 } Obj1; 2566 uint32_t Value; 2567 } DW0; 2568 union 2569 { 2570 //!< DWORD 1 2571 struct 2572 { 2573 uint32_t BorderColorGreen ; //!< Border Color Green, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2574 }; 2575 uint32_t Value; 2576 } DW1; 2577 union 2578 { 2579 //!< DWORD 2 2580 struct 2581 { 2582 uint32_t BorderColorBlue ; //!< Border Color Blue, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2583 }; 2584 uint32_t Value; 2585 } DW2; 2586 union 2587 { 2588 //!< DWORD 3 2589 struct 2590 { 2591 uint32_t BorderColorAlpha ; //!< Border Color Alpha, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2592 }; 2593 uint32_t Value; 2594 } DW3; 2595 2596 uint32_t Reserved128[12]; //!< Reserved 2597 2598 //! \name Local enumerations 2599 2600 //! \name Initializations 2601 2602 //! \brief Explicit member initialization function 2603 SAMPLER_INDIRECT_STATE_CMD(); 2604 2605 static const size_t dwSize = 16; 2606 static const size_t byteSize = 64; 2607 }; 2608 2609 }; 2610 2611 #pragma pack() 2612 2613 #endif // __MHW_STATE_HEAP_HWCMD_G8_X_H__ 2614