1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_state_heap_hwcmd_g11_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g11_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_STATE_HEAP_HWCMD_G11_X_H__ 29 #define __MHW_STATE_HEAP_HWCMD_G11_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_state_heap_g11_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief INTERFACE_DESCRIPTOR_DATA 50 //! \details 51 //! 52 //! 53 struct INTERFACE_DESCRIPTOR_DATA_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 61 uint32_t KernelStartPointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Kernel Start Pointer 62 }; 63 uint32_t Value; 64 } DW0; 65 union 66 { 67 //!< DWORD 1 68 struct 69 { 70 uint32_t KernelStartPointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Kernel Start Pointer High 71 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 72 }; 73 uint32_t Value; 74 } DW1; 75 union 76 { 77 //!< DWORD 2 78 struct 79 { 80 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 81 uint32_t SoftwareExceptionEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Software Exception Enable 82 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 10) ; //!< Reserved 83 uint32_t MaskStackExceptionEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Mask Stack Exception Enable 84 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 12) ; //!< Reserved 85 uint32_t IllegalOpcodeExceptionEnable : __CODEGEN_BITFIELD(13, 13) ; //!< Illegal Opcode Exception Enable 86 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 87 uint32_t FloatingPointMode : __CODEGEN_BITFIELD(16, 16) ; //!< FLOATING_POINT_MODE 88 uint32_t ThreadPriority : __CODEGEN_BITFIELD(17, 17) ; //!< THREAD_PRIORITY 89 uint32_t SingleProgramFlow : __CODEGEN_BITFIELD(18, 18) ; //!< SINGLE_PROGRAM_FLOW 90 uint32_t DenormMode : __CODEGEN_BITFIELD(19, 19) ; //!< DENORM_MODE 91 uint32_t ThreadPreemptionDisable : __CODEGEN_BITFIELD(20, 20) ; //!< THREAD_PREEMPTION_DISABLE 92 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 93 }; 94 uint32_t Value; 95 } DW2; 96 union 97 { 98 //!< DWORD 3 99 struct 100 { 101 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 102 uint32_t SamplerCount : __CODEGEN_BITFIELD( 2, 4) ; //!< SAMPLER_COUNT 103 uint32_t SamplerStatePointer : __CODEGEN_BITFIELD( 5, 31) ; //!< Sampler State Pointer 104 }; 105 uint32_t Value; 106 } DW3; 107 union 108 { 109 //!< DWORD 4 110 struct 111 { 112 uint32_t BindingTableEntryCount : __CODEGEN_BITFIELD( 0, 4) ; //!< Binding Table Entry Count 113 uint32_t BindingTablePointer : __CODEGEN_BITFIELD( 5, 15) ; //!< Binding Table Pointer 114 uint32_t Reserved144 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 115 }; 116 uint32_t Value; 117 } DW4; 118 union 119 { 120 //!< DWORD 5 121 struct 122 { 123 uint32_t ConstantUrbEntryReadOffset : __CODEGEN_BITFIELD( 0, 15) ; //!< Constant URB Entry Read Offset 124 uint32_t ConstantIndirectUrbEntryReadLength : __CODEGEN_BITFIELD(16, 31) ; //!< Constant/Indirect URB Entry Read Length 125 }; 126 uint32_t Value; 127 } DW5; 128 union 129 { 130 //!< DWORD 6 131 struct 132 { 133 uint32_t NumberOfThreadsInGpgpuThreadGroup : __CODEGEN_BITFIELD( 0, 9) ; //!< Number of Threads in GPGPU Thread Group 134 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 135 uint32_t SharedLocalMemorySize : __CODEGEN_BITFIELD(16, 20) ; //!< SHARED_LOCAL_MEMORY_SIZE 136 uint32_t BarrierEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Barrier Enable 137 uint32_t RoundingMode : __CODEGEN_BITFIELD(22, 23) ; //!< ROUNDING_MODE 138 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 139 }; 140 uint32_t Value; 141 } DW6; 142 union 143 { 144 //!< DWORD 7 145 struct 146 { 147 uint32_t CrossThreadConstantDataReadLength : __CODEGEN_BITFIELD( 0, 7) ; //!< Cross-Thread Constant Data Read Length 148 uint32_t Reserved232 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 149 }; 150 uint32_t Value; 151 } DW7; 152 153 //! \name Local enumerations 154 155 //! \brief FLOATING_POINT_MODE 156 //! \details 157 //! Specifies the floating point mode used by the dispatched thread. 158 enum FLOATING_POINT_MODE 159 { 160 FLOATING_POINT_MODE_IEEE_754 = 0, //!< No additional details 161 FLOATING_POINT_MODE_ALTERNATE = 1, //!< No additional details 162 }; 163 164 //! \brief THREAD_PRIORITY 165 //! \details 166 //! Specifies the priority of the thread for dispatch. 167 enum THREAD_PRIORITY 168 { 169 THREAD_PRIORITY_NORMALPRIORITY = 0, //!< No additional details 170 THREAD_PRIORITY_HIGHPRIORITY = 1, //!< No additional details 171 }; 172 173 //! \brief SINGLE_PROGRAM_FLOW 174 //! \details 175 //! Specifies whether the kernel program has a single program flow (SIMDnxm 176 //! with m = 1) or multiple program flows (SIMDnxm with m > 1). 177 enum SINGLE_PROGRAM_FLOW 178 { 179 SINGLE_PROGRAM_FLOW_MULTIPLE = 0, //!< No additional details 180 SINGLE_PROGRAM_FLOW_SINGLE = 1, //!< No additional details 181 }; 182 183 //! \brief DENORM_MODE 184 //! \details 185 //! This field specifies how Float denormalized numbers are handles in the 186 //! dispatched thread. 187 enum DENORM_MODE 188 { 189 DENORM_MODE_FTZ = 0, //!< Float denorms will be flushed to zero when appearing as inputs; denorms will never come out of instructions. Double precision float and half precision float numbers are not flushed to zero. 190 DENORM_MODE_SETBYKERNEL = 1, //!< Denorms will be handled in by kernel. 191 }; 192 193 //! \brief THREAD_PREEMPTION_DISABLE 194 //! \details 195 //! <p>This field specifies whether, when dispatched, the thread is 196 //! allowed to stop in middle on receiving mid-thread pre-emption 197 //! request.</p> 198 enum THREAD_PREEMPTION_DISABLE 199 { 200 THREAD_PREEMPTION_DISABLE_DISABLE = 0, //!< Thread is pre-empted on receiving pre-emption indication. 201 THREAD_PREEMPTION_DISABLE_ENABLE = 1, //!< Thread is preempted only in case of page-fault. 202 }; 203 204 //! \brief SAMPLER_COUNT 205 //! \details 206 //! Specifies how many samplers (in multiples of 4) the kernel uses. Used 207 //! only for prefetching the associated sampler state entries. 208 //! <i>This field is ignored for child threads.</i> 209 //! <i>If this field is not zero, sampler state is prefetched for the 210 //! first instance of a root thread upon the startup of the media 211 //! pipeline.</i> 212 enum SAMPLER_COUNT 213 { 214 SAMPLER_COUNT_NOSAMPLERSUSED = 0, //!< No additional details 215 SAMPLER_COUNT_BETWEEN1AND4SAMPLERSUSED = 1, //!< No additional details 216 SAMPLER_COUNT_BETWEEN5AND8SAMPLERSUSED = 2, //!< No additional details 217 SAMPLER_COUNT_BETWEEN9AND12SAMPLERSUSED = 3, //!< No additional details 218 SAMPLER_COUNT_BETWEEN13AND16SAMPLERSUSED = 4, //!< No additional details 219 }; 220 221 //! \brief SHARED_LOCAL_MEMORY_SIZE 222 //! \details 223 //! This field indicates how much SharedLocalMemory the thread group 224 //! requires. The amount is specified in 4k blocks, but only powers of 2 are 225 //! allowed: 0, 4k, 8k, 16k, 32k and 64k per half-slice. 226 enum SHARED_LOCAL_MEMORY_SIZE 227 { 228 SHARED_LOCAL_MEMORY_SIZE_ENCODES0K = 0, //!< No SLM used 229 SHARED_LOCAL_MEMORY_SIZE_ENCODES1K = 1, //!< No additional details 230 SHARED_LOCAL_MEMORY_SIZE_ENCODES2K = 2, //!< No additional details 231 SHARED_LOCAL_MEMORY_SIZE_ENCODES4K = 3, //!< No additional details 232 SHARED_LOCAL_MEMORY_SIZE_ENCODES8K = 4, //!< No additional details 233 SHARED_LOCAL_MEMORY_SIZE_ENCODES16K = 5, //!< No additional details 234 SHARED_LOCAL_MEMORY_SIZE_ENCODES32K = 6, //!< No additional details 235 SHARED_LOCAL_MEMORY_SIZE_ENCODES64K = 7, //!< No additional details 236 }; 237 238 enum ROUNDING_MODE 239 { 240 ROUNDING_MODE_RTNE = 0, //!< Round to Nearest Even 241 ROUNDING_MODE_RU = 1, //!< Round toward +Infinity 242 ROUNDING_MODE_RD = 2, //!< Round toward -Infinity 243 ROUNDING_MODE_RTZ = 3, //!< Round toward Zero 244 }; 245 246 //! \name Initializations 247 248 //! \brief Explicit member initialization function 249 INTERFACE_DESCRIPTOR_DATA_CMD(); 250 251 static const size_t dwSize = 8; 252 static const size_t byteSize = 32; 253 }; 254 255 //! 256 //! \brief BINDING_TABLE_STATE 257 //! \details 258 //! The binding table binds surfaces to logical resource indices used by 259 //! shaders and other compute engine kernels. It is stored as an array of up 260 //! to 256 elements, each of which contains one dword as defined here. The 261 //! start of each element is spaced one dword apart. The first element of 262 //! the binding table is aligned to a 64-byte boundary. Binding table 263 //! indexes beyond 256 will automatically be mapped to entry 0 by the HW, w/ 264 //! the exception of any messages which support the special indexes 240 265 //! through 255, inclusive. 266 //! 267 struct BINDING_TABLE_STATE_CMD 268 { 269 union 270 { 271 //!< DWORD 0 272 struct 273 { 274 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 275 uint32_t SurfaceStatePointer : __CODEGEN_BITFIELD( 6, 31) ; //!< Surface State Pointer 276 }; 277 uint32_t Value; 278 } DW0; 279 280 //! \name Local enumerations 281 282 //! \name Initializations 283 284 //! \brief Explicit member initialization function 285 BINDING_TABLE_STATE_CMD(); 286 287 static const size_t dwSize = 1; 288 static const size_t byteSize = 4; 289 }; 290 291 //! 292 //! \brief RENDER_SURFACE_STATE 293 //! \details 294 //! This is the normal surface state used by all messages that use 295 //! SURFACE_STATE except those that use MEDIA_SURFACE_STATE. 296 //! 297 struct RENDER_SURFACE_STATE_CMD 298 { 299 union 300 { 301 //!< DWORD 0 302 struct 303 { 304 uint32_t CubeFaceEnablePositiveZ : __CODEGEN_BITFIELD( 0, 0) ; //!< Cube Face Enable - Positive Z, [Surface Type] == 'SURFTYPE_CUBE' 305 uint32_t CubeFaceEnableNegativeZ : __CODEGEN_BITFIELD( 1, 1) ; //!< Cube Face Enable - Negative Z, [Surface Type] == 'SURFTYPE_CUBE' 306 uint32_t CubeFaceEnablePositiveY : __CODEGEN_BITFIELD( 2, 2) ; //!< Cube Face Enable - Positive Y, [Surface Type] == 'SURFTYPE_CUBE' 307 uint32_t CubeFaceEnableNegativeY : __CODEGEN_BITFIELD( 3, 3) ; //!< Cube Face Enable - Negative Y, [Surface Type] == 'SURFTYPE_CUBE' 308 uint32_t CubeFaceEnablePositiveX : __CODEGEN_BITFIELD( 4, 4) ; //!< Cube Face Enable - Positive X, [Surface Type] == 'SURFTYPE_CUBE' 309 uint32_t CubeFaceEnableNegativeX : __CODEGEN_BITFIELD( 5, 5) ; //!< Cube Face Enable - Negative X, [Surface Type] == 'SURFTYPE_CUBE' 310 uint32_t MediaBoundaryPixelMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MEDIA_BOUNDARY_PIXEL_MODE 311 uint32_t RenderCacheReadWriteMode : __CODEGEN_BITFIELD( 8, 8) ; //!< RENDER_CACHE_READ_WRITE_MODE 312 uint32_t SamplerL2OutOfOrderModeDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Sampler L2 Out of Order Mode Disable 313 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(10, 10) ; //!< Vertical Line Stride Offset 314 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(11, 11) ; //!< Vertical Line Stride 315 uint32_t TileMode : __CODEGEN_BITFIELD(12, 13) ; //!< TILE_MODE 316 uint32_t SurfaceHorizontalAlignment : __CODEGEN_BITFIELD(14, 15) ; //!< SURFACE_HORIZONTAL_ALIGNMENT 317 uint32_t SurfaceVerticalAlignment : __CODEGEN_BITFIELD(16, 17) ; //!< SURFACE_VERTICAL_ALIGNMENT 318 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(18, 26) ; //!< SURFACE_FORMAT 319 uint32_t AstcEnable : __CODEGEN_BITFIELD(27, 27) ; //!< ASTC_Enable 320 uint32_t SurfaceArray : __CODEGEN_BITFIELD(28, 28) ; //!< Surface Array 321 uint32_t SurfaceType : __CODEGEN_BITFIELD(29, 31) ; //!< SURFACE_TYPE 322 }; 323 uint32_t Value; 324 } DW0; 325 union 326 { 327 //!< DWORD 1 328 struct 329 { 330 uint32_t SurfaceQpitch : __CODEGEN_BITFIELD( 0, 14) ; //!< Surface QPitch 331 uint32_t SampleTapDiscardDisable : __CODEGEN_BITFIELD(15, 15) ; //!< SAMPLE_TAP_DISCARD_DISABLE 332 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 333 uint32_t CornerTexelMode : __CODEGEN_BITFIELD(18, 18) ; //!< CORNER_TEXEL_MODE 334 uint32_t BaseMipLevel : __CODEGEN_BITFIELD(19, 23) ; //!< Base Mip Level 335 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD(24, 30) ; //!< Memory Object Control State 336 uint32_t EnableUnormPathInColorPipe : __CODEGEN_BITFIELD(31, 31) ; //!< ENABLE_UNORM_PATH_IN_COLOR_PIPE 337 }; 338 uint32_t Value; 339 } DW1; 340 union 341 { 342 //!< DWORD 2 343 struct 344 { 345 uint32_t Width : __CODEGEN_BITFIELD( 0, 13) ; //!< Width 346 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 347 uint32_t Height : __CODEGEN_BITFIELD(16, 29) ; //!< Height 348 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 349 }; 350 uint32_t Value; 351 } DW2; 352 union 353 { 354 //!< DWORD 3 355 struct 356 { 357 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 0, 17) ; //!< Surface Pitch 358 uint32_t Reserved114 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 359 uint32_t StandardTilingModeExtensions : __CODEGEN_BITFIELD(19, 19) ; //!< STANDARD_TILING_MODE_EXTENSIONS 360 uint32_t TileAddressMappingMode : __CODEGEN_BITFIELD(20, 20) ; //!< TILE_ADDRESS_MAPPING_MODE 361 uint32_t Depth : __CODEGEN_BITFIELD(21, 31) ; //!< Depth 362 }; 363 uint32_t Value; 364 } DW3; 365 union 366 { 367 //!< DWORD 4 368 struct 369 { 370 uint32_t MultisamplePositionPaletteIndex : __CODEGEN_BITFIELD( 0, 2) ; //!< Multisample Position Palette Index, [Surface Type] != 'SURFTYPE_STRBUF' 371 uint32_t NumberOfMultisamples : __CODEGEN_BITFIELD( 3, 5) ; //!< NUMBER_OF_MULTISAMPLES, [Surface Type] != 'SURFTYPE_STRBUF' 372 uint32_t MultisampledSurfaceStorageFormat : __CODEGEN_BITFIELD( 6, 6) ; //!< MULTISAMPLED_SURFACE_STORAGE_FORMAT, [Surface Type] != 'SURFTYPE_STRBUF' 373 uint32_t RenderTargetViewExtent : __CODEGEN_BITFIELD( 7, 17) ; //!< Render Target View Extent, [Surface Type] != 'SURFTYPE_STRBUF' 374 uint32_t MinimumArrayElement : __CODEGEN_BITFIELD(18, 28) ; //!< Minimum Array Element, [Surface Type] != 'SURFTYPE_STRBUF' 375 uint32_t RenderTargetAndSampleUnormRotation : __CODEGEN_BITFIELD(29, 30) ; //!< RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION, [Surface Type] != 'SURFTYPE_STRBUF' 376 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, [Surface Type] != 'SURFTYPE_STRBUF' 377 }; 378 uint32_t Value; 379 } DW4; 380 union 381 { 382 //!< DWORD 5 383 struct 384 { 385 uint32_t MipCountLod : __CODEGEN_BITFIELD( 0, 3) ; //!< MIP Count / LOD 386 uint32_t SurfaceMinLod : __CODEGEN_BITFIELD( 4, 7) ; //!< Surface Min LOD 387 uint32_t MipTailStartLod : __CODEGEN_BITFIELD( 8, 11) ; //!< Mip Tail Start LOD 388 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 13) ; //!< Reserved 389 uint32_t CoherencyType : __CODEGEN_BITFIELD(14, 14) ; //!< COHERENCY_TYPE 390 uint32_t Reserved175 : __CODEGEN_BITFIELD(15, 17) ; //!< Reserved 391 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(18, 19) ; //!< TILED_RESOURCE_MODE 392 uint32_t EwaDisableForCube : __CODEGEN_BITFIELD(20, 20) ; //!< EWA_DISABLE_FOR_CUBE 393 uint32_t YOffset : __CODEGEN_BITFIELD(21, 23) ; //!< Y Offset 394 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 395 uint32_t XOffset : __CODEGEN_BITFIELD(25, 31) ; //!< X Offset 396 }; 397 uint32_t Value; 398 } DW5; 399 union 400 { 401 //!< DWORD 6 402 struct 403 { 404 uint32_t YOffsetForUOrUvPlane : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 405 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved, ([Surface Format] == 'PLANAR') 406 uint32_t XOffsetForUOrUvPlane : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U or UV Plane, ([Surface Format] == 'PLANAR') 407 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD(30, 30) ; //!< HALF_PITCH_FOR_CHROMA, ([Surface Format] == 'PLANAR') 408 uint32_t SeparateUvPlaneEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Separate UV Plane Enable, ([Surface Format] == 'PLANAR') 409 } Obj0; 410 struct 411 { 412 uint32_t AuxiliarySurfaceMode : __CODEGEN_BITFIELD( 0, 2) ; //!< AUXILIARY_SURFACE_MODE, ([Surface Format] != 'PLANAR') 413 uint32_t AuxiliarySurfacePitch : __CODEGEN_BITFIELD( 3, 11) ; //!< Auxiliary Surface Pitch, ([Surface Format] != 'PLANAR') 414 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved, ([Surface Format] != 'PLANAR') 415 uint32_t AuxiliarySurfaceQpitch : __CODEGEN_BITFIELD(16, 30) ; //!< Auxiliary Surface QPitch, ([Surface Format] != 'PLANAR') 416 uint32_t Reserved223 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, ([Surface Format] != 'PLANAR') 417 } Obj1; 418 struct 419 { 420 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 14) ; //!< Reserved, ([Surface Format] != 'PLANAR') 421 uint32_t YuvInterpolationEnable : __CODEGEN_BITFIELD(15, 15) ; //!< YUV_INTERPOLATION_ENABLE, 422 uint32_t Reserved208 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved, 423 } Obj2; 424 uint32_t Value; 425 } DW6; 426 union 427 { 428 //!< DWORD 7 429 struct 430 { 431 uint32_t ResourceMinLod : __CODEGEN_BITFIELD( 0, 11) ; //!< Resource Min LOD 432 uint32_t Reserved236 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 433 uint32_t ShaderChannelSelectAlpha : __CODEGEN_BITFIELD(16, 18) ; //!< SHADER_CHANNEL_SELECT_ALPHA 434 uint32_t ShaderChannelSelectBlue : __CODEGEN_BITFIELD(19, 21) ; //!< SHADER_CHANNEL_SELECT_BLUE 435 uint32_t ShaderChannelSelectGreen : __CODEGEN_BITFIELD(22, 24) ; //!< SHADER_CHANNEL_SELECT_GREEN 436 uint32_t ShaderChannelSelectRed : __CODEGEN_BITFIELD(25, 27) ; //!< SHADER_CHANNEL_SELECT_RED 437 uint32_t Reserved252 : __CODEGEN_BITFIELD(28, 29) ; //!< Reserved 438 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(30, 30) ; //!< Memory Compression Enable 439 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD(31, 31) ; //!< MEMORY_COMPRESSION_MODE 440 }; 441 uint32_t Value; 442 } DW7; 443 union 444 { 445 //!< DWORD 8..9 446 struct 447 { 448 uint64_t SurfaceBaseAddress ; //!< Surface Base Address 449 }; 450 uint32_t Value[2]; 451 } DW8_9; 452 union 453 { 454 //!< DWORD 10..11 455 struct 456 { 457 uint64_t QuiltWidth : __CODEGEN_BITFIELD( 0, 4) ; //!< Quilt Width, 458 uint64_t QuiltHeight : __CODEGEN_BITFIELD( 5, 9) ; //!< Quilt Height, 459 uint64_t ClearValueAddressEnable : __CODEGEN_BITFIELD(10, 10) ; //!< CLEAR_VALUE_ADDRESS_ENABLE, 460 uint64_t Reserved331 : __CODEGEN_BITFIELD(11, 63) ; //!< Reserved, 461 } Obj0; 462 struct 463 { 464 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved, 465 uint64_t AuxiliarySurfaceBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Auxiliary Surface Base Address, ([Surface Format] != 'PLANAR') AND [Memory Compression Enable] == 0 466 } Obj1; 467 struct 468 { 469 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 20) ; //!< Reserved, 470 uint64_t AuxiliaryTableIndexForMediaCompressedSurface : __CODEGEN_BITFIELD(21, 31) ; //!< Auxiliary Table Index for Media Compressed Surface, [Memory Compression Enable] ==1 471 uint64_t Reserved352 : __CODEGEN_BITFIELD(32, 63) ; //!< Reserved, [Memory Compression Enable] ==1 472 } Obj2; 473 struct 474 { 475 uint64_t Reserved320 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved, [Memory Compression Enable] ==1 476 uint64_t YOffsetForVPlane : __CODEGEN_BITFIELD(32, 45) ; //!< Y Offset for V Plane, ([Surface Format] == 'PLANAR') 477 uint64_t Reserved366 : __CODEGEN_BITFIELD(46, 47) ; //!< Reserved, ([Surface Format] == 'PLANAR') 478 uint64_t XOffsetForVPlane : __CODEGEN_BITFIELD(48, 61) ; //!< X Offset for V Plane, ([Surface Format] == 'PLANAR') 479 uint64_t Reserved382 : __CODEGEN_BITFIELD(62, 63) ; //!< Reserved, ([Surface Format] == 'PLANAR') 480 } Obj3; 481 uint32_t Value[2]; 482 } DW10_11; 483 union 484 { 485 //!< DWORD 12 486 struct 487 { 488 uint32_t RedClearColor ; //!< Red Clear Color 489 }; 490 uint32_t Value; 491 } DW12; 492 union 493 { 494 //!< DWORD 13 495 struct 496 { 497 uint32_t ClearDepthAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Clear Depth Address High, ([Auxiliary Surface Mode] == 'AUX_HIZ') AND ([Clear Value Address Enable] == 'Enable') 498 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved, ([Auxiliary Surface Mode] == 'AUX_HIZ') AND ([Clear Value Address Enable] == 'Enable') 499 } Obj0; 500 struct 501 { 502 uint32_t ClearColorAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Clear Color Address High, (([Auxiliary Surface Mode] == 'AUX_CCS_D' OR [Auxiliary Surface Mode] == 'AUX_CCS_E') AND [Clear Value Address Enable] == 'Enable') 503 uint32_t Reserved432 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved, (([Auxiliary Surface Mode] == 'AUX_CCS_D' OR [Auxiliary Surface Mode] == 'AUX_CCS_E') AND [Clear Value Address Enable] == 'Enable') 504 } Obj1; 505 struct 506 { 507 uint32_t GreenClearColor ; //!< Green Clear Color, (([Auxiliary Surface Mode] == 'AUX_CCS_D' OR [Auxiliary Surface Mode] == 'AUX_CCS_E') AND [Clear Value Address Enable] == 'Disable') 508 } Obj2; 509 uint32_t Value; 510 } DW13; 511 union 512 { 513 //!< DWORD 14 514 struct 515 { 516 uint32_t BlueClearColor ; //!< Blue Clear Color, (([Auxiliary Surface Mode] == 'AUX_CCS_D' OR [Auxiliary Surface Mode] == 'AUX_CCS_E') AND [Clear Value Address Enable] == 'Disable') 517 }; 518 uint32_t Value; 519 } DW14; 520 union 521 { 522 //!< DWORD 15 523 struct 524 { 525 uint32_t AlphaClearColor ; //!< Alpha Clear Color, (([Auxiliary Surface Mode] == 'AUX_CCS_D' OR [Auxiliary Surface Mode] == 'AUX_CCS_E') AND [Clear Value Address Enable] == 'Disable') 526 }; 527 uint32_t Value; 528 } DW15; 529 530 //! \name Local enumerations 531 532 //! \brief MEDIA_BOUNDARY_PIXEL_MODE 533 //! \details 534 //! <div id="GroupContent-248" class="GroupContent UseCKEdit"> 535 //! <p><b>For 2D Non-Array Surfaces accessed via the Data Port Media Block 536 //! Read Message or Data Port Transpose Read message:</b><br /> 537 //! This field enables control of which rows are returned on vertical 538 //! out-of-bounds reads using the Data Port Media Block Read Message or Data 539 //! Port Transpose Read message. In the description below, frame mode refers 540 //! to <b>Vertical Line Stride</b> = 0, field mode is <b>Vertical Line 541 //! Stride</b> = 1 in which only the even or odd rows are addressable. The 542 //! frame refers to the entire surface, while the field refers only to the 543 //! even or odd rows within the surface.</p> 544 //! <p><b>For Other Surfaces:</b><br /> 545 //! Reserved : MBZ</p></div> 546 enum MEDIA_BOUNDARY_PIXEL_MODE 547 { 548 MEDIA_BOUNDARY_PIXEL_MODE_NORMALMODE = 0, //!< The row returned on an out-of-bound access is the closest row in the frame or field. Rows from the opposite field are never returned. 549 MEDIA_BOUNDARY_PIXEL_MODE_PROGRESSIVEFRAME = 2, //!< The row returned on an out-of-bound access is the closest row in the frame, even if in field mode. 550 MEDIA_BOUNDARY_PIXEL_MODE_INTERLACEDFRAME = 3, //!< In field mode, the row returned on an out-of-bound access is the closest row in the field. In frame mode, even out-of-bound rows return the nearest even row while odd out-of-bound rows return the nearest odd row. 551 }; 552 553 //! \brief RENDER_CACHE_READ_WRITE_MODE 554 //! \details 555 //! <p><b>For Surfaces accessed via the Data Port to Render Cache:</b><br /> 556 //! This field specifies the way Render Cache treats a write request. If 557 //! unset, Render Cache allocates a write-only cache line for a write miss. 558 //! If set, Render Cache allocates a read-write cache line for a write 559 //! miss.</p> 560 //! <p><b>For Surfaces accessed via the Sampling Engine or Data Port to 561 //! Texture Cache or Data Cache:</b><br /> 562 //! This field is reserved : MBZ</p> 563 enum RENDER_CACHE_READ_WRITE_MODE 564 { 565 RENDER_CACHE_READ_WRITE_MODE_WRITE_ONLYCACHE = 0, //!< Allocating write-only cache for a write miss 566 RENDER_CACHE_READ_WRITE_MODE_READ_WRITECACHE = 1, //!< Allocating read-write cache for a write miss 567 }; 568 569 //! \brief TILE_MODE 570 //! \details 571 //! This field specifies the type of memory tiling (Linear, WMajor, XMajor, 572 //! or YMajor) employed to tile this surface. See <em>Memory Interface 573 //! Functions</em> for details on memory tiling and restrictions. 574 enum TILE_MODE 575 { 576 TILE_MODE_LINEAR = 0, //!< Linear mode (no tiling) 577 TILE_MODE_WMAJOR = 1, //!< W major tiling 578 TILE_MODE_XMAJOR = 2, //!< X major tiling 579 TILE_MODE_YMAJOR = 3, //!< Y major tiling 580 }; 581 582 //! \brief SURFACE_HORIZONTAL_ALIGNMENT 583 //! \details 584 //! For Sampling Engine and Render Target Surfaces: This field specifies the 585 //! horizontal alignment requirement for the surface. 586 enum SURFACE_HORIZONTAL_ALIGNMENT 587 { 588 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN4 = 1, //!< Horizontal alignment factor j = 4 589 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN8 = 2, //!< Horizontal alignment factor j = 8 590 SURFACE_HORIZONTAL_ALIGNMENT_HALIGN16 = 3, //!< Horizontal alignment factor j = 16 591 }; 592 593 //! \brief SURFACE_VERTICAL_ALIGNMENT 594 //! \details 595 //! <b>For Sampling Engine and Render Target Surfaces:</b> This field 596 //! specifies the vertical alignment requirement in elements for the 597 //! surface. Refer to the "Memory Data Formats" chapter for details on how 598 //! this field changes the layout of the surface in memory. An 599 //! <i>element</i> is defined as a pixel in uncompresed surface formats, and 600 //! as a compression block in compressed surface formats. For 601 //! MSFMT_DEPTH_STENCIL type multisampled surfaces, an element is a sample. 602 enum SURFACE_VERTICAL_ALIGNMENT 603 { 604 SURFACE_VERTICAL_ALIGNMENT_VALIGN4 = 1, //!< Vertical alignment factor j = 4 605 SURFACE_VERTICAL_ALIGNMENT_VALIGN8 = 2, //!< Vertical alignment factor j = 8 606 SURFACE_VERTICAL_ALIGNMENT_VALIGN16 = 3, //!< Vertical alignment factor j = 16 607 }; 608 609 //! \brief SURFACE_FORMAT 610 //! \details 611 //! This field specifies the format of the surface or element within this 612 //! surface. This field is ignored for all data port messages other than the 613 //! render target message and streamed vertex buffer write message. Some 614 //! forms of the media block messages use the surface format. 615 enum SURFACE_FORMAT 616 { 617 SURFACE_FORMAT_R32G32B32A32FLOAT = 0, //!< No additional details 618 SURFACE_FORMAT_R32G32B32A32SINT = 1, //!< No additional details 619 SURFACE_FORMAT_R32G32B32A32UINT = 2, //!< No additional details 620 SURFACE_FORMAT_R32G32B32A32UNORM = 3, //!< No additional details 621 SURFACE_FORMAT_R32G32B32A32SNORM = 4, //!< No additional details 622 SURFACE_FORMAT_R64G64FLOAT = 5, //!< No additional details 623 SURFACE_FORMAT_R32G32B32X32FLOAT = 6, //!< No additional details 624 SURFACE_FORMAT_R32G32B32A32SSCALED = 7, //!< No additional details 625 SURFACE_FORMAT_R32G32B32A32USCALED = 8, //!< No additional details 626 SURFACE_FORMAT_R32G32B32A32SFIXED = 32, //!< No additional details 627 SURFACE_FORMAT_R64G64PASSTHRU = 33, //!< No additional details 628 SURFACE_FORMAT_R32G32B32FLOAT = 64, //!< No additional details 629 SURFACE_FORMAT_R32G32B32SINT = 65, //!< No additional details 630 SURFACE_FORMAT_R32G32B32UINT = 66, //!< No additional details 631 SURFACE_FORMAT_R32G32B32UNORM = 67, //!< No additional details 632 SURFACE_FORMAT_R32G32B32SNORM = 68, //!< No additional details 633 SURFACE_FORMAT_R32G32B32SSCALED = 69, //!< No additional details 634 SURFACE_FORMAT_R32G32B32USCALED = 70, //!< No additional details 635 SURFACE_FORMAT_R32G32B32SFIXED = 80, //!< No additional details 636 SURFACE_FORMAT_R16G16B16A16UNORM = 128, //!< No additional details 637 SURFACE_FORMAT_R16G16B16A16SNORM = 129, //!< No additional details 638 SURFACE_FORMAT_R16G16B16A16SINT = 130, //!< No additional details 639 SURFACE_FORMAT_R16G16B16A16UINT = 131, //!< No additional details 640 SURFACE_FORMAT_R16G16B16A16FLOAT = 132, //!< No additional details 641 SURFACE_FORMAT_R32G32FLOAT = 133, //!< No additional details 642 SURFACE_FORMAT_R32G32SINT = 134, //!< No additional details 643 SURFACE_FORMAT_R32G32UINT = 135, //!< No additional details 644 SURFACE_FORMAT_R32FLOATX8X24TYPELESS = 136, //!< No additional details 645 SURFACE_FORMAT_X32TYPELESSG8X24UINT = 137, //!< No additional details 646 SURFACE_FORMAT_L32A32FLOAT = 138, //!< No additional details 647 SURFACE_FORMAT_R32G32UNORM = 139, //!< No additional details 648 SURFACE_FORMAT_R32G32SNORM = 140, //!< No additional details 649 SURFACE_FORMAT_R64FLOAT = 141, //!< No additional details 650 SURFACE_FORMAT_R16G16B16X16UNORM = 142, //!< No additional details 651 SURFACE_FORMAT_R16G16B16X16FLOAT = 143, //!< No additional details 652 SURFACE_FORMAT_A32X32FLOAT = 144, //!< No additional details 653 SURFACE_FORMAT_L32X32FLOAT = 145, //!< No additional details 654 SURFACE_FORMAT_I32X32FLOAT = 146, //!< No additional details 655 SURFACE_FORMAT_R16G16B16A16SSCALED = 147, //!< No additional details 656 SURFACE_FORMAT_R16G16B16A16USCALED = 148, //!< No additional details 657 SURFACE_FORMAT_R32G32SSCALED = 149, //!< No additional details 658 SURFACE_FORMAT_R32G32USCALED = 150, //!< No additional details 659 SURFACE_FORMAT_R32G32SFIXED = 160, //!< No additional details 660 SURFACE_FORMAT_R64PASSTHRU = 161, //!< No additional details 661 SURFACE_FORMAT_B8G8R8A8UNORM = 192, //!< No additional details 662 SURFACE_FORMAT_B8G8R8A8UNORMSRGB = 193, //!< No additional details 663 SURFACE_FORMAT_R10G10B10A2UNORM = 194, //!< No additional details 664 SURFACE_FORMAT_R10G10B10A2UNORMSRGB = 195, //!< No additional details 665 SURFACE_FORMAT_R10G10B10A2UINT = 196, //!< No additional details 666 SURFACE_FORMAT_R10G10B10SNORMA2UNORM = 197, //!< No additional details 667 SURFACE_FORMAT_R8G8B8A8UNORM = 199, //!< No additional details 668 SURFACE_FORMAT_R8G8B8A8UNORMSRGB = 200, //!< No additional details 669 SURFACE_FORMAT_R8G8B8A8SNORM = 201, //!< No additional details 670 SURFACE_FORMAT_R8G8B8A8SINT = 202, //!< No additional details 671 SURFACE_FORMAT_R8G8B8A8UINT = 203, //!< No additional details 672 SURFACE_FORMAT_R16G16UNORM = 204, //!< No additional details 673 SURFACE_FORMAT_R16G16SNORM = 205, //!< No additional details 674 SURFACE_FORMAT_R16G16SINT = 206, //!< No additional details 675 SURFACE_FORMAT_R16G16UINT = 207, //!< No additional details 676 SURFACE_FORMAT_R16G16FLOAT = 208, //!< No additional details 677 SURFACE_FORMAT_B10G10R10A2UNORM = 209, //!< No additional details 678 SURFACE_FORMAT_B10G10R10A2UNORMSRGB = 210, //!< No additional details 679 SURFACE_FORMAT_R11G11B10FLOAT = 211, //!< No additional details 680 SURFACE_FORMAT_R32SINT = 214, //!< No additional details 681 SURFACE_FORMAT_R32UINT = 215, //!< No additional details 682 SURFACE_FORMAT_R32FLOAT = 216, //!< No additional details 683 SURFACE_FORMAT_R24UNORMX8TYPELESS = 217, //!< No additional details 684 SURFACE_FORMAT_X24TYPELESSG8UINT = 218, //!< No additional details 685 SURFACE_FORMAT_L32UNORM = 221, //!< No additional details 686 SURFACE_FORMAT_A32UNORM = 222, //!< No additional details 687 SURFACE_FORMAT_L16A16UNORM = 223, //!< No additional details 688 SURFACE_FORMAT_I24X8UNORM = 224, //!< No additional details 689 SURFACE_FORMAT_L24X8UNORM = 225, //!< No additional details 690 SURFACE_FORMAT_A24X8UNORM = 226, //!< No additional details 691 SURFACE_FORMAT_I32FLOAT = 227, //!< No additional details 692 SURFACE_FORMAT_L32FLOAT = 228, //!< No additional details 693 SURFACE_FORMAT_A32FLOAT = 229, //!< No additional details 694 SURFACE_FORMAT_X8B8UNORMG8R8SNORM = 230, //!< No additional details 695 SURFACE_FORMAT_A8X8UNORMG8R8SNORM = 231, //!< No additional details 696 SURFACE_FORMAT_B8X8UNORMG8R8SNORM = 232, //!< No additional details 697 SURFACE_FORMAT_B8G8R8X8UNORM = 233, //!< No additional details 698 SURFACE_FORMAT_B8G8R8X8UNORMSRGB = 234, //!< No additional details 699 SURFACE_FORMAT_R8G8B8X8UNORM = 235, //!< No additional details 700 SURFACE_FORMAT_R8G8B8X8UNORMSRGB = 236, //!< No additional details 701 SURFACE_FORMAT_R9G9B9E5SHAREDEXP = 237, //!< No additional details 702 SURFACE_FORMAT_B10G10R10X2UNORM = 238, //!< No additional details 703 SURFACE_FORMAT_L16A16FLOAT = 240, //!< No additional details 704 SURFACE_FORMAT_R32UNORM = 241, //!< No additional details 705 SURFACE_FORMAT_R32SNORM = 242, //!< No additional details 706 SURFACE_FORMAT_R10G10B10X2USCALED = 243, //!< No additional details 707 SURFACE_FORMAT_R8G8B8A8SSCALED = 244, //!< No additional details 708 SURFACE_FORMAT_R8G8B8A8USCALED = 245, //!< No additional details 709 SURFACE_FORMAT_R16G16SSCALED = 246, //!< No additional details 710 SURFACE_FORMAT_R16G16USCALED = 247, //!< No additional details 711 SURFACE_FORMAT_R32SSCALED = 248, //!< No additional details 712 SURFACE_FORMAT_R32USCALED = 249, //!< No additional details 713 SURFACE_FORMAT_B5G6R5UNORM = 256, //!< No additional details 714 SURFACE_FORMAT_B5G6R5UNORMSRGB = 257, //!< No additional details 715 SURFACE_FORMAT_B5G5R5A1UNORM = 258, //!< No additional details 716 SURFACE_FORMAT_B5G5R5A1UNORMSRGB = 259, //!< No additional details 717 SURFACE_FORMAT_B4G4R4A4UNORM = 260, //!< No additional details 718 SURFACE_FORMAT_B4G4R4A4UNORMSRGB = 261, //!< No additional details 719 SURFACE_FORMAT_R8G8UNORM = 262, //!< No additional details 720 SURFACE_FORMAT_R8G8SNORM = 263, //!< No additional details 721 SURFACE_FORMAT_R8G8SINT = 264, //!< No additional details 722 SURFACE_FORMAT_R8G8UINT = 265, //!< No additional details 723 SURFACE_FORMAT_R16UNORM = 266, //!< No additional details 724 SURFACE_FORMAT_R16SNORM = 267, //!< No additional details 725 SURFACE_FORMAT_R16SINT = 268, //!< No additional details 726 SURFACE_FORMAT_R16UINT = 269, //!< No additional details 727 SURFACE_FORMAT_R16FLOAT = 270, //!< No additional details 728 SURFACE_FORMAT_A8P8UNORMPALETTE0 = 271, //!< No additional details 729 SURFACE_FORMAT_A8P8UNORMPALETTE1 = 272, //!< No additional details 730 SURFACE_FORMAT_I16UNORM = 273, //!< No additional details 731 SURFACE_FORMAT_L16UNORM = 274, //!< No additional details 732 SURFACE_FORMAT_A16UNORM = 275, //!< No additional details 733 SURFACE_FORMAT_L8A8UNORM = 276, //!< No additional details 734 SURFACE_FORMAT_I16FLOAT = 277, //!< No additional details 735 SURFACE_FORMAT_L16FLOAT = 278, //!< No additional details 736 SURFACE_FORMAT_A16FLOAT = 279, //!< No additional details 737 SURFACE_FORMAT_L8A8UNORMSRGB = 280, //!< No additional details 738 SURFACE_FORMAT_R5G5SNORMB6UNORM = 281, //!< No additional details 739 SURFACE_FORMAT_B5G5R5X1UNORM = 282, //!< No additional details 740 SURFACE_FORMAT_B5G5R5X1UNORMSRGB = 283, //!< No additional details 741 SURFACE_FORMAT_R8G8SSCALED = 284, //!< No additional details 742 SURFACE_FORMAT_R8G8USCALED = 285, //!< No additional details 743 SURFACE_FORMAT_R16SSCALED = 286, //!< No additional details 744 SURFACE_FORMAT_R16USCALED = 287, //!< No additional details 745 SURFACE_FORMAT_P8A8UNORMPALETTE0 = 290, //!< No additional details 746 SURFACE_FORMAT_P8A8UNORMPALETTE1 = 291, //!< No additional details 747 SURFACE_FORMAT_A1B5G5R5UNORM = 292, //!< No additional details 748 SURFACE_FORMAT_A4B4G4R4UNORM = 293, //!< No additional details 749 SURFACE_FORMAT_L8A8UINT = 294, //!< No additional details 750 SURFACE_FORMAT_L8A8SINT = 295, //!< No additional details 751 SURFACE_FORMAT_R8UNORM = 320, //!< No additional details 752 SURFACE_FORMAT_R8SNORM = 321, //!< No additional details 753 SURFACE_FORMAT_R8SINT = 322, //!< No additional details 754 SURFACE_FORMAT_R8UINT = 323, //!< No additional details 755 SURFACE_FORMAT_A8UNORM = 324, //!< No additional details 756 SURFACE_FORMAT_I8UNORM = 325, //!< No additional details 757 SURFACE_FORMAT_L8UNORM = 326, //!< No additional details 758 SURFACE_FORMAT_P4A4UNORMPALETTE0 = 327, //!< No additional details 759 SURFACE_FORMAT_A4P4UNORMPALETTE0 = 328, //!< No additional details 760 SURFACE_FORMAT_R8SSCALED = 329, //!< No additional details 761 SURFACE_FORMAT_R8USCALED = 330, //!< No additional details 762 SURFACE_FORMAT_P8UNORMPALETTE0 = 331, //!< No additional details 763 SURFACE_FORMAT_L8UNORMSRGB = 332, //!< No additional details 764 SURFACE_FORMAT_P8UNORMPALETTE1 = 333, //!< No additional details 765 SURFACE_FORMAT_P4A4UNORMPALETTE1 = 334, //!< No additional details 766 SURFACE_FORMAT_A4P4UNORMPALETTE1 = 335, //!< No additional details 767 SURFACE_FORMAT_Y8UNORM = 336, //!< No additional details 768 SURFACE_FORMAT_L8UINT = 338, //!< No additional details 769 SURFACE_FORMAT_L8SINT = 339, //!< No additional details 770 SURFACE_FORMAT_I8UINT = 340, //!< No additional details 771 SURFACE_FORMAT_I8SINT = 341, //!< No additional details 772 SURFACE_FORMAT_DXT1RGBSRGB = 384, //!< No additional details 773 SURFACE_FORMAT_R1UNORM = 385, //!< No additional details 774 SURFACE_FORMAT_YCRCBNORMAL = 386, //!< No additional details 775 SURFACE_FORMAT_YCRCBSWAPUVY = 387, //!< No additional details 776 SURFACE_FORMAT_P2UNORMPALETTE0 = 388, //!< No additional details 777 SURFACE_FORMAT_P2UNORMPALETTE1 = 389, //!< No additional details 778 SURFACE_FORMAT_BC1UNORM = 390, //!< No additional details 779 SURFACE_FORMAT_BC2UNORM = 391, //!< No additional details 780 SURFACE_FORMAT_BC3UNORM = 392, //!< No additional details 781 SURFACE_FORMAT_BC4UNORM = 393, //!< No additional details 782 SURFACE_FORMAT_BC5UNORM = 394, //!< No additional details 783 SURFACE_FORMAT_BC1UNORMSRGB = 395, //!< No additional details 784 SURFACE_FORMAT_BC2UNORMSRGB = 396, //!< No additional details 785 SURFACE_FORMAT_BC3UNORMSRGB = 397, //!< No additional details 786 SURFACE_FORMAT_MONO8 = 398, //!< No additional details 787 SURFACE_FORMAT_YCRCBSWAPUV = 399, //!< No additional details 788 SURFACE_FORMAT_YCRCBSWAPY = 400, //!< No additional details 789 SURFACE_FORMAT_DXT1RGB = 401, //!< No additional details 790 SURFACE_FORMAT_FXT1 = 402, //!< No additional details 791 SURFACE_FORMAT_R8G8B8UNORM = 403, //!< No additional details 792 SURFACE_FORMAT_R8G8B8SNORM = 404, //!< No additional details 793 SURFACE_FORMAT_R8G8B8SSCALED = 405, //!< No additional details 794 SURFACE_FORMAT_R8G8B8USCALED = 406, //!< No additional details 795 SURFACE_FORMAT_R64G64B64A64FLOAT = 407, //!< No additional details 796 SURFACE_FORMAT_R64G64B64FLOAT = 408, //!< No additional details 797 SURFACE_FORMAT_BC4SNORM = 409, //!< No additional details 798 SURFACE_FORMAT_BC5SNORM = 410, //!< No additional details 799 SURFACE_FORMAT_R16G16B16FLOAT = 411, //!< No additional details 800 SURFACE_FORMAT_R16G16B16UNORM = 412, //!< No additional details 801 SURFACE_FORMAT_R16G16B16SNORM = 413, //!< No additional details 802 SURFACE_FORMAT_R16G16B16SSCALED = 414, //!< No additional details 803 SURFACE_FORMAT_R16G16B16USCALED = 415, //!< No additional details 804 SURFACE_FORMAT_BC6HSF16 = 417, //!< No additional details 805 SURFACE_FORMAT_BC7UNORM = 418, //!< No additional details 806 SURFACE_FORMAT_BC7UNORMSRGB = 419, //!< No additional details 807 SURFACE_FORMAT_BC6HUF16 = 420, //!< No additional details 808 SURFACE_FORMAT_PLANAR4208 = 421, //!< No additional details 809 SURFACE_FORMAT_PLANAR42016 = 422, //!< No additional details 810 SURFACE_FORMAT_R8G8B8UNORMSRGB = 424, //!< No additional details 811 SURFACE_FORMAT_ETC1RGB8 = 425, //!< No additional details 812 SURFACE_FORMAT_ETC2RGB8 = 426, //!< No additional details 813 SURFACE_FORMAT_EACR11 = 427, //!< No additional details 814 SURFACE_FORMAT_EACRG11 = 428, //!< No additional details 815 SURFACE_FORMAT_EACSIGNEDR11 = 429, //!< No additional details 816 SURFACE_FORMAT_EACSIGNEDRG11 = 430, //!< No additional details 817 SURFACE_FORMAT_ETC2SRGB8 = 431, //!< No additional details 818 SURFACE_FORMAT_R16G16B16UINT = 432, //!< No additional details 819 SURFACE_FORMAT_R16G16B16SINT = 433, //!< No additional details 820 SURFACE_FORMAT_R32SFIXED = 434, //!< No additional details 821 SURFACE_FORMAT_R10G10B10A2SNORM = 435, //!< No additional details 822 SURFACE_FORMAT_R10G10B10A2USCALED = 436, //!< No additional details 823 SURFACE_FORMAT_R10G10B10A2SSCALED = 437, //!< No additional details 824 SURFACE_FORMAT_R10G10B10A2SINT = 438, //!< No additional details 825 SURFACE_FORMAT_B10G10R10A2SNORM = 439, //!< No additional details 826 SURFACE_FORMAT_B10G10R10A2USCALED = 440, //!< No additional details 827 SURFACE_FORMAT_B10G10R10A2SSCALED = 441, //!< No additional details 828 SURFACE_FORMAT_B10G10R10A2UINT = 442, //!< No additional details 829 SURFACE_FORMAT_B10G10R10A2SINT = 443, //!< No additional details 830 SURFACE_FORMAT_R64G64B64A64PASSTHRU = 444, //!< No additional details 831 SURFACE_FORMAT_R64G64B64PASSTHRU = 445, //!< No additional details 832 SURFACE_FORMAT_ETC2RGB8PTA = 448, //!< No additional details 833 SURFACE_FORMAT_ETC2SRGB8PTA = 449, //!< No additional details 834 SURFACE_FORMAT_ETC2EACRGBA8 = 450, //!< No additional details 835 SURFACE_FORMAT_ETC2EACSRGB8A8 = 451, //!< No additional details 836 SURFACE_FORMAT_R8G8B8UINT = 456, //!< No additional details 837 SURFACE_FORMAT_R8G8B8SINT = 457, //!< No additional details 838 SURFACE_FORMAT_RAW = 511, //!< No additional details 839 }; 840 841 //! \brief SURFACE_TYPE 842 //! \details 843 //! This field defines the type of the surface. 844 enum SURFACE_TYPE 845 { 846 SURFACE_TYPE_SURFTYPE1D = 0, //!< Defines a 1-dimensional map or array of maps 847 SURFACE_TYPE_SURFTYPE2D = 1, //!< Defines a 2-dimensional map or array of maps 848 SURFACE_TYPE_SURFTYPE3D = 2, //!< Defines a 3-dimensional (volumetric) map 849 SURFACE_TYPE_SURFTYPECUBE = 3, //!< Defines a cube map or array of cube maps 850 SURFACE_TYPE_SURFTYPEBUFFER = 4, //!< Defines an element in a buffer 851 SURFACE_TYPE_SURFTYPESTRBUF = 5, //!< Defines a structured buffer surface 852 SURFACE_TYPE_SURFTYPENULL = 7, //!< Defines a null surface 853 }; 854 855 //! \brief SAMPLE_TAP_DISCARD_DISABLE 856 //! \details 857 //! This bit forces sample tap discard filter mode to be disabled for this 858 //! surface state. This bit must be set for surfaces which are no Alpha 859 //! Channel such as R8G8B8_UNORM. 860 enum SAMPLE_TAP_DISCARD_DISABLE 861 { 862 SAMPLE_TAP_DISCARD_DISABLE_DISABLE = 0, //!< When programmed to 0h, Sample Tap Discard filter mode is allowed and is not disabled by this bit. This bit is ignored if Sample Tap Discard is not enabled in the Sampler State. 863 SAMPLE_TAP_DISCARD_DISABLE_ENABLE = 1, //!< When programmed to 1h, Sample Tap Discard filter mode will be disabled even if enabled through Sampler State 864 }; 865 866 //! \brief CORNER_TEXEL_MODE 867 //! \details 868 //! <p>This field, when ENABLED, indicates when a surface is using corner 869 //! texel-mode for sampling.</p> 870 //! <p>Corner Texel Mode is ignored for Planar YUV/YCrCb surface 871 //! formats.</p> 872 //! <p>Corner Texel Mode is ignored for sample_8X8 and sample_unorm messasge 873 //! types.</p> 874 //! <p>Does not support legacy sampler features set0 See legacy sampler page 875 //! for more details</p> 876 enum CORNER_TEXEL_MODE 877 { 878 CORNER_TEXEL_MODE_DISABLE = 0, //!< When programmed to 0h, Corner Texel Mode is disabled. This means texel coordinate references use standard texel reference mode, with respect to the center of the texel. 879 CORNER_TEXEL_MODE_ENABLE = 1, //!< When programmed to 1h, Corner Texel Mode is enabled. Texel coordinate references are with respect to the upper left corner of a texel. 880 }; 881 882 //! \brief ENABLE_UNORM_PATH_IN_COLOR_PIPE 883 //! \details 884 //! Enables Unorm Path (fixed Point Conversion of floating point for fill 885 //! and blend in DAPRSS) in color Pipe. 886 enum ENABLE_UNORM_PATH_IN_COLOR_PIPE 887 { 888 ENABLE_UNORM_PATH_IN_COLOR_PIPE_UNNAMED0 = 0, //!< Disables Unorm path in Color Pipe. 889 ENABLE_UNORM_PATH_IN_COLOR_PIPE_UNNAMED1 = 1, //!< Enables Unorm Path in Color Pipe. 890 }; 891 892 //! \brief STANDARD_TILING_MODE_EXTENSIONS 893 //! \details 894 //! <p>It changes in the MIP Tail Packing. When enabled (programmed to 1h), 895 //! MIP Tail packing for Volumetric and 1D are changed as defined in the 896 //! Surface Layout and Tiling</b><br /> 897 //! <p></p> 898 enum STANDARD_TILING_MODE_EXTENSIONS 899 { 900 STANDARD_TILING_MODE_EXTENSIONS_DISABLE = 0, //!< When programmed to 0h, the Gen11 extensions to support Standard Tiling are disabled. Behavior reverts to Gen10 and Gen9 Miptail packing. 901 STANDARD_TILING_MODE_EXTENSIONS_ENABLE = 1, //!< When programmed to 1h, the Gen11 changes to support Standard Tiling Extensions are enabled. See the Surface Layout and Tiling section for details. 902 }; 903 904 //! \brief TILE_ADDRESS_MAPPING_MODE 905 //! \details 906 //! This field is used to select between Gen9 Tile Address Mapping mode and 907 //! Gen10 for TileYs and TileYf. 908 enum TILE_ADDRESS_MAPPING_MODE 909 { 910 TILE_ADDRESS_MAPPING_MODE_GEN9 = 0, //!< Gen9 Tile Address Mapping ModeThou shalt program the bit to 0h. Thou shalt NOT program the bit to 1h. Thou shalt not program the bit to 2h. 3h is right out. The number of the programming shall be 0h and 0h shall be the number of the programming. Fractional numbers, being evil in our site (and impossible) must also not be used. Great disappointment and functional woes shall be seen if this bit is not programmed to 0h. 911 TILE_ADDRESS_MAPPING_MODE_GEN10 = 1, //!< Gen10+ Tile Address Mapping Mode (for Standard Tiling).<!--StartFragment-->Thou shalt not program the bit to 1h. Thou shalt program the bit to 0h. Thou shalt not program the bit to 2h. 3h is right out. The number of the programming shall be 0h and 0h shall be the number of the programming. Fractional numbers, being evil in our site (and impossible) must also not be used. Great disappointment and functional woes shall be seen if this bit is not programmed to 0h.<!--EndFragment--> 912 }; 913 914 //! \brief NUMBER_OF_MULTISAMPLES 915 //! \details 916 //! This field indicates the number of multisamples on the surface. 917 enum NUMBER_OF_MULTISAMPLES 918 { 919 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT1 = 0, //!< No additional details 920 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT2 = 1, //!< No additional details 921 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT4 = 2, //!< No additional details 922 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT8 = 3, //!< No additional details 923 NUMBER_OF_MULTISAMPLES_MULTISAMPLECOUNT16 = 4, //!< No additional details 924 }; 925 926 //! \brief MULTISAMPLED_SURFACE_STORAGE_FORMAT 927 //! \details 928 //! This field indicates the storage format of the multisampled surface. 929 enum MULTISAMPLED_SURFACE_STORAGE_FORMAT 930 { 931 MULTISAMPLED_SURFACE_STORAGE_FORMAT_MSS = 0, //!< Multisampled surface was/is rendered as a render target 932 MULTISAMPLED_SURFACE_STORAGE_FORMAT_DEPTHSTENCIL = 1, //!< Multisampled surface was rendered as a depth or stencil buffer 933 }; 934 935 //! \brief RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 936 //! \details 937 //! <b>For Render Target Surfaces:</b> 938 //! This field specifies the rotation of this render target surface 939 //! when being written to memory. 940 enum RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION 941 { 942 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_0DEG = 0, //!< No rotation (0 degrees) 943 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_90DEG = 1, //!< Rotate by 90 degrees 944 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_180DEG = 2, //!< Rotate by 180 degrees [for sample_unorm message] 945 RENDER_TARGET_AND_SAMPLE_UNORM_ROTATION_270DEG = 3, //!< Rotate by 270 degrees 946 }; 947 948 //! \brief COHERENCY_TYPE 949 //! \details 950 //! Specifies the type of coherency maintained for this surface. 951 enum COHERENCY_TYPE 952 { 953 COHERENCY_TYPE_GPUCOHERENT = 0, //!< Surface memory is kept coherent with GPU threads using GPU read/write ordering rules. Surface memory is backed by system memory but is not kept coherent with CPU (LLC). 954 COHERENCY_TYPE_IACOHERENT = 1, //!< Surface memory is kept coherent with CPU (LLC). 955 }; 956 957 //! \brief TILED_RESOURCE_MODE 958 //! \details 959 //! <b>For Sampling Engine, Render Target, and Typed/Untyped Surfaces:</b> 960 //! This field specifies the tiled resource mode. 961 //! 962 //! <b>For other surfaces:</b> 963 //! This field is ignored. 964 enum TILED_RESOURCE_MODE 965 { 966 TILED_RESOURCE_MODE_NONE = 0, //!< No tiled resource 967 TILED_RESOURCE_MODE_4KB = 1, //!< 4KB tiled resources 968 TILED_RESOURCE_MODE_TILEYF = 1, //!< 4KB tiled resources 969 TILED_RESOURCE_MODE_64KB = 2, //!< 64KB tiled resources 970 TILED_RESOURCE_MODE_TILEYS = 2, //!< 64KB tiled resources 971 }; 972 973 //! \brief EWA_DISABLE_FOR_CUBE 974 //! \details 975 //! Specifies if EWA mode for LOD quality improvement needs to be disabled 976 //! for cube maps. 977 enum EWA_DISABLE_FOR_CUBE 978 { 979 EWA_DISABLE_FOR_CUBE_ENABLE = 0, //!< EWA is enabled for cube maps 980 EWA_DISABLE_FOR_CUBE_DISABLE = 1, //!< EWA is disabled for cube maps 981 }; 982 983 //! \brief AUXILIARY_SURFACE_MODE 984 //! \details 985 //! Specifies what type of surface the Auxiliary surface is. The Auxiliary 986 //! surface has its own base address and pitch, but otherwise shares or 987 //! overrides other fields set for the primary surface, detailed in the 988 //! programming notes below. 989 enum AUXILIARY_SURFACE_MODE 990 { 991 AUXILIARY_SURFACE_MODE_AUXNONE = 0, //!< No Auxiliary surface is used 992 AUXILIARY_SURFACE_MODE_AUXCCSD = 1, //!< The Auxiliary surface is a CCS (Color Control Surface) with compression disabled or an MCS with compression enabled, depending on Number of Multisamples. MCS (Multisample Control Surface) is a special type of CCS. 993 AUXILIARY_SURFACE_MODE_AUXAPPEND = 2, //!< The Auxiliary surface is an append buffer 994 AUXILIARY_SURFACE_MODE_AUXHIZ = 3, //!< The Auxiliary surface is a hierarchical depth buffer 995 AUXILIARY_SURFACE_MODE_AUXCCSE = 5, //!< The Auxiliary surface is a CCS with compression enabled or an MCS with compression enabled, depending on Number of Multisamples. 996 }; 997 998 //! \brief YUV_INTERPOLATION_ENABLE 999 //! \details 1000 //! This bit controls whether a Non-Planar YUV4:2:2 and Planar YUV4:2:0 1001 //! surface use interpolated or replicated U and V channels for input to the 1002 //! Sampler filter. Programming to 1h causes interpolation of U and V 1003 //! channels. In this case the chrominance for odd pixels is computed by an 1004 //! interpolation between adjacent even pixels. Programming to 0h causes the 1005 //! chrominance to be copied from the pixel to the left. 1006 enum YUV_INTERPOLATION_ENABLE 1007 { 1008 YUV_INTERPOLATION_ENABLE_DISABLE = 0, //!< Programming to 0h causes the sampler to replicate U and V channels. This will lead to lower quality in certain cases where the YUV surface is being filtered (e.g. linear). 1009 YUV_INTERPOLATION_ENABLE_ENABLE = 1, //!< Programming to 1h causes the sampler to interpolate the U and V channels between the horizonally neighboring pixels. This will improvie image quality if the surface is being filtered. 1010 }; 1011 1012 //! \brief HALF_PITCH_FOR_CHROMA 1013 //! \details 1014 //! <p><span style="font-family: "Arial","sans-serif"; 1015 //! font-size: 10pt; mso-fareast-font-family: "Times New Roman"; 1016 //! mso-ansi-language: EN-US; mso-fareast-language: EN-US; 1017 //! mso-bidi-language: AR-SA;"><font color="#000000">This bit enables 1018 //! support for half-pitch chroma planes for Planar YUV surfaces. It is 1019 //! ignored for Non-Planar surfaces. For planar surfaces it allows the 1020 //! chroma planes to be one-half the width of a the Y (Luma) 1021 //! plane.</font></span></p> 1022 //! <p><span style="font-family: "Arial","sans-serif"; 1023 //! font-size: 10pt; mso-fareast-font-family: "Times New Roman"; 1024 //! mso-ansi-language: EN-US; mso-fareast-language: EN-US; 1025 //! mso-bidi-language: AR-SA;"><font color="#000000">For example, should be 1026 //! set to 0h for NV12 surfaces.</font></span></p> 1027 //! <p><span style="font-family: "Arial","sans-serif"; 1028 //! font-size: 10pt; mso-fareast-font-family: "Times New Roman"; 1029 //! mso-ansi-language: EN-US; mso-fareast-language: EN-US; 1030 //! mso-bidi-language: AR-SA;"><font color="#000000">Must be set to 1h for 1031 //! YV12 surfaces.</font></span></p> 1032 enum HALF_PITCH_FOR_CHROMA 1033 { 1034 HALF_PITCH_FOR_CHROMA_DISABLE = 0, //!< <font color="#000000">Setting this bit to 0h (default) causes Chroma planes to be treated as full width (same as Y plane).</font> 1035 HALF_PITCH_FOR_CHROMA_ENABLE = 1, //!< <font color="#000000">Setting this bit to 1h causes Chroma planes (U and V) to be treated as half the width of the Luma (Y) plane.</font> 1036 }; 1037 1038 //! \brief SHADER_CHANNEL_SELECT_ALPHA 1039 //! \details 1040 //! See <b>Shader Channel Select Red</b> for details. 1041 enum SHADER_CHANNEL_SELECT_ALPHA 1042 { 1043 SHADER_CHANNEL_SELECT_ALPHA_ZERO = 0, //!< No additional details 1044 SHADER_CHANNEL_SELECT_ALPHA_ONE = 1, //!< No additional details 1045 SHADER_CHANNEL_SELECT_ALPHA_RED = 4, //!< No additional details 1046 SHADER_CHANNEL_SELECT_ALPHA_GREEN = 5, //!< No additional details 1047 SHADER_CHANNEL_SELECT_ALPHA_BLUE = 6, //!< No additional details 1048 SHADER_CHANNEL_SELECT_ALPHA_ALPHA = 7, //!< No additional details 1049 }; 1050 1051 //! \brief SHADER_CHANNEL_SELECT_BLUE 1052 //! \details 1053 //! See <b>Shader Channel Select Red</b> for details. 1054 enum SHADER_CHANNEL_SELECT_BLUE 1055 { 1056 SHADER_CHANNEL_SELECT_BLUE_ZERO = 0, //!< No additional details 1057 SHADER_CHANNEL_SELECT_BLUE_ONE = 1, //!< No additional details 1058 SHADER_CHANNEL_SELECT_BLUE_RED = 4, //!< No additional details 1059 SHADER_CHANNEL_SELECT_BLUE_GREEN = 5, //!< No additional details 1060 SHADER_CHANNEL_SELECT_BLUE_BLUE = 6, //!< No additional details 1061 SHADER_CHANNEL_SELECT_BLUE_ALPHA = 7, //!< No additional details 1062 }; 1063 1064 //! \brief SHADER_CHANNEL_SELECT_GREEN 1065 //! \details 1066 //! See <b>Shader Channel Select Red</b> for details. 1067 enum SHADER_CHANNEL_SELECT_GREEN 1068 { 1069 SHADER_CHANNEL_SELECT_GREEN_ZERO = 0, //!< No additional details 1070 SHADER_CHANNEL_SELECT_GREEN_ONE = 1, //!< No additional details 1071 SHADER_CHANNEL_SELECT_GREEN_RED = 4, //!< No additional details 1072 SHADER_CHANNEL_SELECT_GREEN_GREEN = 5, //!< No additional details 1073 SHADER_CHANNEL_SELECT_GREEN_BLUE = 6, //!< No additional details 1074 SHADER_CHANNEL_SELECT_GREEN_ALPHA = 7, //!< No additional details 1075 }; 1076 1077 //! \brief SHADER_CHANNEL_SELECT_RED 1078 //! \details 1079 //! Specifies which surface channel is read or written in the Red shader 1080 //! channel. 1081 enum SHADER_CHANNEL_SELECT_RED 1082 { 1083 SHADER_CHANNEL_SELECT_RED_ZERO = 0, //!< No additional details 1084 SHADER_CHANNEL_SELECT_RED_ONE = 1, //!< No additional details 1085 SHADER_CHANNEL_SELECT_RED_RED = 4, //!< No additional details 1086 SHADER_CHANNEL_SELECT_RED_GREEN = 5, //!< No additional details 1087 SHADER_CHANNEL_SELECT_RED_BLUE = 6, //!< No additional details 1088 SHADER_CHANNEL_SELECT_RED_ALPHA = 7, //!< No additional details 1089 }; 1090 1091 //! \brief MEMORY_COMPRESSION_MODE 1092 //! \details 1093 //! Distinguishes Vertical from Horizontal compression. 1094 enum MEMORY_COMPRESSION_MODE 1095 { 1096 MEMORY_COMPRESSION_MODE_HORIZONTAL = 0, //!< No additional details 1097 MEMORY_COMPRESSION_MODE_VERTICAL = 1, //!< No additional details 1098 }; 1099 1100 //! \brief CLEAR_VALUE_ADDRESS_ENABLE 1101 //! \details 1102 //! This field enables HW Managed Clear Value Layout for the Surface State. 1103 //! If this bit is enabled, Clear Value Address is present instead of 1104 //! explicit clear values. 1105 enum CLEAR_VALUE_ADDRESS_ENABLE 1106 { 1107 CLEAR_VALUE_ADDRESS_ENABLE_DISABLE = 0, //!< Clear values are present in the surface state explicitly. 1108 CLEAR_VALUE_ADDRESS_ENABLE_ENABLE = 1, //!< Clear value Address is present instead of explicit clear values. 1109 }; 1110 1111 //! \name Initializations 1112 1113 //! \brief Explicit member initialization function 1114 RENDER_SURFACE_STATE_CMD(); 1115 1116 static const size_t dwSize = 16; 1117 static const size_t byteSize = 64; 1118 }; 1119 1120 //! 1121 //! \brief MEDIA_SURFACE_STATE 1122 //! \details 1123 //! This is the SURFACE_STATE used by only deinterlace, sample_8x8, and VME 1124 //! messages. 1125 //! 1126 struct MEDIA_SURFACE_STATE_CMD 1127 { 1128 union 1129 { 1130 //!< DWORD 0 1131 struct 1132 { 1133 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1134 uint32_t YOffset : __CODEGEN_BITFIELD(16, 19) ; //!< Y Offset, [Surface Format] is one of Planar Formats 1135 uint32_t XOffset : __CODEGEN_BITFIELD(20, 26) ; //!< X Offset, [Surface Format] is one of Planar Formats 1136 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 29) ; //!< Reserved, [Surface Format] is one of Planar Formats 1137 uint32_t Rotation : __CODEGEN_BITFIELD(30, 31) ; //!< ROTATION 1138 }; 1139 uint32_t Value; 1140 } DW0; 1141 union 1142 { 1143 //!< DWORD 1 1144 struct 1145 { 1146 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION 1147 uint32_t PictureStructure : __CODEGEN_BITFIELD( 2, 3) ; //!< PICTURE_STRUCTURE 1148 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 1149 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 1150 }; 1151 uint32_t Value; 1152 } DW1; 1153 union 1154 { 1155 //!< DWORD 2 1156 struct 1157 { 1158 uint32_t TileMode : __CODEGEN_BITFIELD( 0, 1) ; //!< TILE_MODE 1159 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 1160 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 20) ; //!< Surface Pitch 1161 uint32_t AddressControl : __CODEGEN_BITFIELD(21, 21) ; //!< ADDRESS_CONTROL 1162 uint32_t MemoryCompressionEnable : __CODEGEN_BITFIELD(22, 22) ; //!< Memory Compression Enable 1163 uint32_t MemoryCompressionMode : __CODEGEN_BITFIELD(23, 23) ; //!< MEMORY_COMPRESSION_MODE 1164 uint32_t CrVCbUPixelOffsetVDirectionMsb : __CODEGEN_BITFIELD(24, 24) ; //!< CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1165 uint32_t CrVCbUPixelOffsetUDirection : __CODEGEN_BITFIELD(25, 25) ; //!< CRVCBU_PIXEL_OFFSET_U_DIRECTION 1166 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(26, 26) ; //!< Interleave Chroma 1167 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 1168 }; 1169 uint32_t Value; 1170 } DW2; 1171 union 1172 { 1173 //!< DWORD 3 1174 struct 1175 { 1176 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 13) ; //!< Y Offset for U(Cb) 1177 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1178 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for U(Cb) 1179 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1180 }; 1181 uint32_t Value; 1182 } DW3; 1183 union 1184 { 1185 //!< DWORD 4 1186 struct 1187 { 1188 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for V(Cr) 1189 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1190 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 29) ; //!< X Offset for V(Cr) 1191 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1192 }; 1193 uint32_t Value; 1194 } DW4; 1195 union 1196 { 1197 //!< DWORD 5 1198 struct 1199 { 1200 uint32_t SurfaceMemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< SURFACE_MEMORY_OBJECT_CONTROL_STATE 1201 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 17) ; //!< Reserved 1202 uint32_t TiledResourceMode : __CODEGEN_BITFIELD(18, 19) ; //!< TILED_RESOURCE_MODE 1203 uint32_t Depth : __CODEGEN_BITFIELD(20, 23) ; //!< Depth 1204 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 29) ; //!< Reserved 1205 uint32_t VerticalLineStrideOffset : __CODEGEN_BITFIELD(30, 30) ; //!< Vertical Line Stride Offset 1206 uint32_t VerticalLineStride : __CODEGEN_BITFIELD(31, 31) ; //!< Vertical Line Stride 1207 }; 1208 uint32_t Value; 1209 } DW5; 1210 union 1211 { 1212 //!< DWORD 6 1213 struct 1214 { 1215 uint32_t SurfaceBaseAddress ; //!< Surface Base Address 1216 }; 1217 uint32_t Value; 1218 } DW6; 1219 union 1220 { 1221 //!< DWORD 7 1222 struct 1223 { 1224 uint32_t SurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Surface Base Address High 1225 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1226 }; 1227 uint32_t Value; 1228 } DW7; 1229 1230 //! \name Local enumerations 1231 1232 //! \brief ROTATION 1233 //! \details 1234 //! Rotation is only supported only with AVS function messages and not with 1235 //! HDC direct write and 16x8 AVS messages. 1236 enum ROTATION 1237 { 1238 ROTATION_NOROTATIONOR0DEGREE = 0, //!< No additional details 1239 ROTATION_90DEGREEROTATION = 1, //!< No additional details 1240 ROTATION_180DEGREEROTATION = 2, //!< No additional details 1241 ROTATION_270DEGREEROTATION = 3, //!< No additional details 1242 }; 1243 1244 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION 1245 //! \details 1246 //! Specifies the distance to the U/V values with respect to the even 1247 //! numbered Y channels in the V direction 1248 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION 1249 { 1250 CRVCBU_PIXEL_OFFSET_V_DIRECTION_UNNAMED0 = 0, //!< No additional details 1251 }; 1252 1253 //! \brief PICTURE_STRUCTURE 1254 //! \details 1255 //! Specifies the encoding of the current picture. 1256 enum PICTURE_STRUCTURE 1257 { 1258 PICTURE_STRUCTURE_FRAMEPICTURE = 0, //!< No additional details 1259 PICTURE_STRUCTURE_TOPFIELDPICTURE = 1, //!< No additional details 1260 PICTURE_STRUCTURE_BOTTOMFIELDPICTURE = 2, //!< No additional details 1261 PICTURE_STRUCTURE_INVALID_NOTALLOWED = 3, //!< No additional details 1262 }; 1263 1264 //! \brief TILE_MODE 1265 //! \details 1266 //! This field specifies the type of memory tiling (Linear, WMajor, XMajor, 1267 //! or YMajor) employed to tile this surface. See Memory Interface Functions 1268 //! for details on memory tiling and restrictions. 1269 enum TILE_MODE 1270 { 1271 TILE_MODE_TILEMODELINEAR = 0, //!< Linear mode (no tiling) 1272 TILE_MODE_TILEMODEXMAJOR = 2, //!< X major tiling 1273 TILE_MODE_TILEMODEYMAJOR = 3, //!< Y major tiling 1274 }; 1275 1276 enum ADDRESS_CONTROL 1277 { 1278 ADDRESS_CONTROL_CLAMP = 0, //!< Clamp 1279 ADDRESS_CONTROL_MIRROR = 1, //!< Mirror 1280 }; 1281 1282 //! \brief MEMORY_COMPRESSION_MODE 1283 //! \details 1284 //! Distinguishes Vertical from Horizontal compression. 1285 enum MEMORY_COMPRESSION_MODE 1286 { 1287 MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 1288 MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 1289 }; 1290 1291 //! \brief CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1292 //! \details 1293 //! Specifies the distance to the U/V values with respect to the even 1294 //! numbered Y channels in the V direction 1295 enum CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB 1296 { 1297 CRVCBU_PIXEL_OFFSET_V_DIRECTION_MSB_UNNAMED0 = 0, //!< No additional details 1298 }; 1299 1300 //! \brief CRVCBU_PIXEL_OFFSET_U_DIRECTION 1301 //! \details 1302 //! Specifies the distance to the U/V values with respect to the even 1303 //! numbered Y channels in the U direction 1304 enum CRVCBU_PIXEL_OFFSET_U_DIRECTION 1305 { 1306 CRVCBU_PIXEL_OFFSET_U_DIRECTION_UNNAMED0 = 0, //!< No additional details 1307 }; 1308 1309 //! \brief SURFACE_FORMAT 1310 //! \details 1311 //! Specifies the format of the surface. All of the Y and G channels will 1312 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1. 1313 enum SURFACE_FORMAT 1314 { 1315 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 1316 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 1317 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 1318 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 1319 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 1320 SURFACE_FORMAT_Y8UNORMVA = 5, //!< Sample_8x8 only except AVS 1321 SURFACE_FORMAT_Y16SNORM = 6, //!< Sample_8x8 only except AVS 1322 SURFACE_FORMAT_Y16UNORMVA = 7, //!< Sample_8x8 only except AVS 1323 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 only 1324 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 AVS only 1325 SURFACE_FORMAT_R8B8UNORM_CRCB = 10, //!< Sample_8x8 AVS only 1326 SURFACE_FORMAT_R8UNORM_CRCB = 11, //!< Sample_8x8 AVS only 1327 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 AVS only 1328 SURFACE_FORMAT_A8Y8U8V8UNORM = 13, //!< Sample_8x8 AVS only 1329 SURFACE_FORMAT_B8G8R8A8UNORM = 14, //!< Sample_8x8 AVS only 1330 SURFACE_FORMAT_R16G16B16A16 = 15, //!< Sample_8x8 AVS only 1331 SURFACE_FORMAT_Y1UNORM = 16, //!< Sample_8x8 only for boolean surfaces (1bit/pixel) 1332 SURFACE_FORMAT_Y32UNORM = 17, //!< For Integral Image (32bpp) 1333 SURFACE_FORMAT_PLANAR4228 = 18, //!< Sample_8x8 AVS only 1334 SURFACE_FORMAT_FMSTRBUFY1 = 19, //!< Structure Buffer 1bit/element Sample_8x8 only feature matching 1335 SURFACE_FORMAT_FMSTRBUFY8 = 20, //!< Structure Buffer 8bit/element Sample_8x8 only feature matching 1336 SURFACE_FORMAT_FMSTRBUFY16 = 21, //!< Structure Buffer 16bit/element Sample_8x8 only feature matching 1337 SURFACE_FORMAT_FMSTRBUFY32 = 22, //!< Used for Index Table only. 32bit per entry. 1338 SURFACE_FORMAT_PLANAR42016 = 23, //!< Sample_8x8 AVS only 1339 SURFACE_FORMAT_R16B16UNORM_CRCB = 24, //!< Sample_8x8 AVS only 1340 SURFACE_FORMAT_R16UNORM_CRCB = 25, //!< Sample_8x8 AVS only 1341 SURFACE_FORMAT_Y16UNORM = 26, //!< Sample_8x8 AVS only 1342 }; 1343 1344 //! \brief SURFACE_MEMORY_OBJECT_CONTROL_STATE 1345 //! \details 1346 //! This 7-bit field is used in various state commands and indirect state 1347 //! objects to define cacheability and other attributes related to memory 1348 //! objects. 1349 enum SURFACE_MEMORY_OBJECT_CONTROL_STATE 1350 { 1351 SURFACE_MEMORY_OBJECT_CONTROL_STATE_DEFAULTVAUEDESC = 0, //!< No additional details 1352 }; 1353 1354 //! \brief TILED_RESOURCE_MODE 1355 //! \details 1356 //! <b>For Sampling Engine, Render Target, and Typed/Untyped Surfaces:</b> 1357 //! This field specifies the tiled resource mode. 1358 //! <b>For other surfaces:</b> 1359 //! This field is ignored. 1360 enum TILED_RESOURCE_MODE 1361 { 1362 TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1363 TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1364 TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1365 }; 1366 1367 //! \name Initializations 1368 1369 //! \brief Explicit member initialization function 1370 MEDIA_SURFACE_STATE_CMD(); 1371 1372 static const size_t dwSize = 8; 1373 static const size_t byteSize = 32; 1374 }; 1375 1376 //! 1377 //! \brief SAMPLER_STATE 1378 //! \details 1379 //! This is the normal sampler state used by all messages that use 1380 //! SAMPLER_STATE except sample_8x8 and deinterlace. The sampler state is 1381 //! stored as an array of up to 16 elements, each of which contains the 1382 //! dwords described here. The start of each element is spaced 4 dwords 1383 //! apart. The first element of the sampler state array is aligned to a 1384 //! 32-byte boundary. 1385 //! 1386 struct SAMPLER_STATE_CMD 1387 { 1388 union 1389 { 1390 //!< DWORD 0 1391 struct 1392 { 1393 uint32_t LodAlgorithm : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_ALGORITHM 1394 uint32_t TextureLodBias : __CODEGEN_BITFIELD( 1, 13) ; //!< Texture LOD Bias 1395 uint32_t MinModeFilter : __CODEGEN_BITFIELD(14, 16) ; //!< MIN_MODE_FILTER 1396 uint32_t MagModeFilter : __CODEGEN_BITFIELD(17, 19) ; //!< MAG_MODE_FILTER 1397 uint32_t MipModeFilter : __CODEGEN_BITFIELD(20, 21) ; //!< MIP_MODE_FILTER 1398 uint32_t CoarseLodQualityMode : __CODEGEN_BITFIELD(22, 26) ; //!< COARSE_LOD_QUALITY_MODE 1399 uint32_t LodPreclampMode : __CODEGEN_BITFIELD(27, 28) ; //!< LOD_PRECLAMP_MODE 1400 uint32_t TextureBorderColorMode : __CODEGEN_BITFIELD(29, 29) ; //!< TEXTURE_BORDER_COLOR_MODE 1401 uint32_t CpsLodCompensationEnable : __CODEGEN_BITFIELD(30, 30) ; //!< CPS LOD Compensation Enable 1402 uint32_t SamplerDisable : __CODEGEN_BITFIELD(31, 31) ; //!< Sampler Disable 1403 }; 1404 uint32_t Value; 1405 } DW0; 1406 union 1407 { 1408 //!< DWORD 1 1409 struct 1410 { 1411 uint32_t CubeSurfaceControlMode : __CODEGEN_BITFIELD( 0, 0) ; //!< CUBE_SURFACE_CONTROL_MODE 1412 uint32_t ShadowFunction : __CODEGEN_BITFIELD( 1, 3) ; //!< SHADOW_FUNCTION 1413 uint32_t ChromakeyMode : __CODEGEN_BITFIELD( 4, 4) ; //!< CHROMAKEY_MODE 1414 uint32_t ChromakeyIndex : __CODEGEN_BITFIELD( 5, 6) ; //!< ChromaKey Index 1415 uint32_t ChromakeyEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< ChromaKey Enable 1416 uint32_t MaxLod : __CODEGEN_BITFIELD( 8, 19) ; //!< Max LOD 1417 uint32_t MinLod : __CODEGEN_BITFIELD(20, 31) ; //!< Min LOD 1418 }; 1419 uint32_t Value; 1420 } DW1; 1421 union 1422 { 1423 //!< DWORD 2 1424 struct 1425 { 1426 uint32_t LodClampMagnificationMode : __CODEGEN_BITFIELD( 0, 0) ; //!< LOD_CLAMP_MAGNIFICATION_MODE 1427 uint32_t SrgbDecode : __CODEGEN_BITFIELD( 1, 1) ; //!< SRGB_DECODE 1428 uint32_t ReturnFilterWeightForNullTexels : __CODEGEN_BITFIELD( 2, 2) ; //!< RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1429 uint32_t ReturnFilterWeightForBorderTexels : __CODEGEN_BITFIELD( 3, 3) ; //!< RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1430 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 5) ; //!< Reserved 1431 uint32_t IndirectStatePointer : __CODEGEN_BITFIELD( 6, 23) ; //!< Indirect State Pointer 1432 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1433 }; 1434 uint32_t Value; 1435 } DW2; 1436 union 1437 { 1438 //!< DWORD 3 1439 struct 1440 { 1441 uint32_t TczAddressControlMode : __CODEGEN_BITFIELD( 0, 2) ; //!< TCZ_ADDRESS_CONTROL_MODE 1442 uint32_t TcyAddressControlMode : __CODEGEN_BITFIELD( 3, 5) ; //!< TCY_ADDRESS_CONTROL_MODE 1443 uint32_t TcxAddressControlMode : __CODEGEN_BITFIELD( 6, 8) ; //!< TCX_ADDRESS_CONTROL_MODE 1444 uint32_t ReductionTypeEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Reduction Type Enable 1445 uint32_t NonNormalizedCoordinateEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Non-normalized Coordinate Enable 1446 uint32_t TrilinearFilterQuality : __CODEGEN_BITFIELD(11, 12) ; //!< TRILINEAR_FILTER_QUALITY 1447 uint32_t RAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(13, 13) ; //!< R Address Min Filter Rounding Enable 1448 uint32_t RAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(14, 14) ; //!< R Address Mag Filter Rounding Enable 1449 uint32_t VAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(15, 15) ; //!< V Address Min Filter Rounding Enable 1450 uint32_t VAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(16, 16) ; //!< V Address Mag Filter Rounding Enable 1451 uint32_t UAddressMinFilterRoundingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< U Address Min Filter Rounding Enable 1452 uint32_t UAddressMagFilterRoundingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< U Address Mag Filter Rounding Enable 1453 uint32_t MaximumAnisotropy : __CODEGEN_BITFIELD(19, 21) ; //!< MAXIMUM_ANISOTROPY 1454 uint32_t ReductionType : __CODEGEN_BITFIELD(22, 23) ; //!< REDUCTION_TYPE 1455 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1456 }; 1457 uint32_t Value; 1458 } DW3; 1459 1460 //! \name Local enumerations 1461 1462 //! \brief LOD_ALGORITHM 1463 //! \details 1464 //! Controls which algorithm is used for LOD calculation. Generally, the EWA 1465 //! approximation algorithm results in higher image quality than the legacy 1466 //! algorithm. 1467 enum LOD_ALGORITHM 1468 { 1469 LOD_ALGORITHM_LEGACY = 0, //!< Use the legacy algorithm for anisotropic filtering 1470 LOD_ALGORITHM_EWAAPPROXIMATION = 1, //!< Use the new EWA approximation algorithm for anisotropic filtering 1471 }; 1472 1473 //! \brief MIN_MODE_FILTER 1474 //! \details 1475 //! This field determines how texels are sampled/filtered when a texture is 1476 //! being "minified" (shrunk). For volume maps, this filter mode selection 1477 //! also applies to the 3rd (inter-layer) dimension.See Mag Mode Filter 1478 enum MIN_MODE_FILTER 1479 { 1480 MIN_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1481 MIN_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1482 MIN_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1483 MIN_MODE_FILTER_MONO = 6, //!< Perform a monochrome convolution filter 1484 }; 1485 1486 //! \brief MAG_MODE_FILTER 1487 //! \details 1488 //! This field determines how texels are sampled/filtered when a texture is 1489 //! being "magnified" (enlarged). For volume maps, this filter mode 1490 //! selection also applies to the 3rd (inter-layer) dimension. 1491 enum MAG_MODE_FILTER 1492 { 1493 MAG_MODE_FILTER_NEAREST = 0, //!< Sample the nearest texel 1494 MAG_MODE_FILTER_LINEAR = 1, //!< Bilinearly filter the 4 nearest texels 1495 MAG_MODE_FILTER_ANISOTROPIC = 2, //!< Perform an "anisotropic" filter on the chosen mip level 1496 MAG_MODE_FILTER_MONO = 6, //!< Perform a monochrome convolution filter 1497 }; 1498 1499 //! \brief MIP_MODE_FILTER 1500 //! \details 1501 //! This field determines if and how mip map levels are chosen and/or 1502 //! combined when texture filtering. 1503 enum MIP_MODE_FILTER 1504 { 1505 MIP_MODE_FILTER_NONE = 0, //!< Disable mip mapping - force use of the mipmap level corresponding to Min LOD. 1506 MIP_MODE_FILTER_NEAREST = 1, //!< Nearest, Select the nearest mip map 1507 MIP_MODE_FILTER_LINEAR = 3, //!< Linearly interpolate between nearest mip maps (combined with linear min/mag filters this is analogous to "Trilinear" filtering). 1508 }; 1509 1510 //! \brief COARSE_LOD_QUALITY_MODE 1511 //! \details 1512 //! This field configures the coarse LOD image quality mode for the 1513 //! sample_d, sample_l, and sample_b messages in the sampling engine. In 1514 //! general, performance will increase and power consumption will decrease 1515 //! with each step of reduced quality (performance gain for sample_l and 1516 //! sample_b will be minimal). 1517 enum COARSE_LOD_QUALITY_MODE 1518 { 1519 COARSE_LOD_QUALITY_MODE_DISABLED = 0, //!< Full quality is enabled, matching prior products 1520 }; 1521 1522 //! \brief LOD_PRECLAMP_MODE 1523 //! \details 1524 //! <p>This field determines whether the computed LOD is clamped to 1525 //! [max,min] mip level 1526 //! before the mag-vs-min determination is performed.</p> 1527 enum LOD_PRECLAMP_MODE 1528 { 1529 LOD_PRECLAMP_MODE_NONE = 0, //!< LOD PreClamp disabled 1530 LOD_PRECLAMP_MODE_OGL = 2, //!< LOD PreClamp enabled (OGL mode) 1531 }; 1532 1533 //! \brief TEXTURE_BORDER_COLOR_MODE 1534 //! \details 1535 //! For some surface formats, the 32 bit border color is decoded differently 1536 //! based on the border color mode. In addition, the default value of 1537 //! channels not included in the surface may be affected by this field. 1538 //! Refer to the "Sampler Output Channel Mapping" table for the values of 1539 //! these channels, and for surface formats that may only support one of 1540 //! these modes. Also refer to the definition of SAMPLER_BORDER_COLOR_STATE 1541 //! for more details on the behavior of the two modes defined by this field. 1542 enum TEXTURE_BORDER_COLOR_MODE 1543 { 1544 TEXTURE_BORDER_COLOR_MODE_OGL = 0, //!< OGL mode for interpreting the border color 1545 TEXTURE_BORDER_COLOR_MODE_8BIT = 1, //!< 8 bit and earlier mode for interpreting the border color 1546 }; 1547 1548 //! \brief CUBE_SURFACE_CONTROL_MODE 1549 //! \details 1550 //! When sampling from a SURFTYPE_CUBE surface, this field controls whether 1551 //! the TC* Address Control Mode fields are interpreted as programmed or 1552 //! overridden to TEXCOORDMODE_CUBE. 1553 enum CUBE_SURFACE_CONTROL_MODE 1554 { 1555 CUBE_SURFACE_CONTROL_MODE_PROGRAMMED = 0, //!< No additional details 1556 CUBE_SURFACE_CONTROL_MODE_OVERRIDE = 1, //!< No additional details 1557 }; 1558 1559 //! \brief SHADOW_FUNCTION 1560 //! \details 1561 //! This field is used for shadow mapping support via the sample_c message 1562 //! type, and specifies the specific comparison operation to be used. The 1563 //! comparison is between the texture sample red channel (except for 1564 //! alpha-only formats which use the alpha channel), and the "ref" value 1565 //! provided in the input message. 1566 enum SHADOW_FUNCTION 1567 { 1568 SHADOW_FUNCTION_PREFILTEROPALWAYS = 0, //!< No additional details 1569 SHADOW_FUNCTION_PREFILTEROPNEVER = 1, //!< No additional details 1570 SHADOW_FUNCTION_PREFILTEROPLESS = 2, //!< No additional details 1571 SHADOW_FUNCTION_PREFILTEROPEQUAL = 3, //!< No additional details 1572 SHADOW_FUNCTION_PREFILTEROPLEQUAL = 4, //!< No additional details 1573 SHADOW_FUNCTION_PREFILTEROPGREATER = 5, //!< No additional details 1574 SHADOW_FUNCTION_PREFILTEROPNOTEQUAL = 6, //!< No additional details 1575 SHADOW_FUNCTION_PREFILTEROPGEQUAL = 7, //!< No additional details 1576 }; 1577 1578 //! \brief CHROMAKEY_MODE 1579 //! \details 1580 //! This field specifies the behavior of the device in the event of a 1581 //! ChromaKey match. This field is ignored if ChromaKey is disabled. 1582 enum CHROMAKEY_MODE 1583 { 1584 CHROMAKEY_MODE_KEYFILTERKILLONANYMATCH = 0, //!< In this mode, if any contributing texel matches the chroma key, the corresponding pixel mask bit for that pixel is cleared. The result of this operation is observable only if the Killed Pixel Mask Return flag is set on the input message. 1585 CHROMAKEY_MODE_KEYFILTERREPLACEBLACK = 1, //!< In this mode, each texel that matches the chroma key is replaced with (0,0,0,0) (black with alpha=0) prior to filtering. For YCrCb surface formats, the black value is A=0, R(Cr)=0x80, G(Y)=0x10, B(Cb)=0x80. This will tend to darken/fade edges of keyed regions. Note that the pixel pipeline must be programmed to use the resulting filtered texel value to gain the intended effect, e.g., handle the case of a totally keyed-out region (filtered texel alpha==0) through use of alpha test, etc. 1586 }; 1587 1588 //! \brief LOD_CLAMP_MAGNIFICATION_MODE 1589 //! \details 1590 //! This field allows the flexibility to control how LOD clamping is handled 1591 //! when in magnification mode. 1592 enum LOD_CLAMP_MAGNIFICATION_MODE 1593 { 1594 LOD_CLAMP_MAGNIFICATION_MODE_MIPNONE = 0, //!< When in magnification mode, Sampler will clamp LOD as if the Mip Mode Filteris MIPFILTER_NONE. This is how OpenGL defines magnification, and therefore it isexpected that those drivers would not set this bit. 1595 LOD_CLAMP_MAGNIFICATION_MODE_MIPFILTER = 1, //!< When in magnification mode, Sampler will clamp LOD based on the value of Mip Mode Filter. 1596 }; 1597 1598 //! \brief SRGB_DECODE 1599 //! \details 1600 //! <p>This bit controls whether the 3D sampler will decode an sRGB 1601 //! formatted surface into RGB prior to any filtering operation.</p> 1602 //! <p>When set, it does not convert to linear RGB (via a reverse gamma 1603 //! conversion). This bit is ignored for ASTC formats, which are always 1604 //! converted to linear RGB prior to filtering.</p> 1605 enum SRGB_DECODE 1606 { 1607 SRGB_DECODE_DECODEEXT = 0, //!< When set to 0h, the 3D sampler will convert texels from an sRGB surface to linear RGB prior to filtering and/or returning the value. 1608 SRGB_DECODE_SKIPDECODEEXT = 1, //!< When set to 1h, the 3D sampler will not convert texels to linear RGB before filtering and returning results. 1609 }; 1610 1611 //! \brief RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1612 //! \details 1613 //! <p>This bit, when set, causes samples to return filter_weight of all 1614 //! non-NULL texels in the Alpha channel; Red, Green, and Blue channels are 1615 //! contain the filter result with NULL texels excluded; A non-NULL texel is 1616 //! a texel which does not reference a Null Tile.</p> 1617 //! <p>For cases where Tiled_Resource_Mode is TR_NONE, the result will 1618 //! always be 1.0 since no texels would be NULL.</p> 1619 //! <p>For cases where the surface format contains an Alpha channel, the 1620 //! result returned will be overridden to return the filter weight.</p> 1621 //! <p>For cases where the surface format does not contain Alpha, the result 1622 //! will still be returned in the Alpha Channel.</p> 1623 enum RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS 1624 { 1625 RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_DISABLE = 0, //!< When programmed to 0h, filter weight will not be returned, and normal data will be returned on the Alpha channel. 1626 RETURN_FILTER_WEIGHT_FOR_NULL_TEXELS_ENABLE = 1, //!< When programmed to 1h, filter weight will be returned on the Alpha channel rather than the normal data expected on the Alpha channel. 1627 }; 1628 1629 //! \brief RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1630 //! \details 1631 //! <p>This bit, when set, returns the filter_weight in the Alpha channel of 1632 //! all non-border texels. Red, Green, and Blue channels will contain the 1633 //! sample result with border texels excluded.</p> 1634 //! <p>For cases where the surface format contains an Alpha channel, the 1635 //! result returned will be ovewritten to return the filter weight.</p> 1636 //! <p>For cases where the surface format does not contain Alpha, the result 1637 //! will still be returned in the Alpha Channel.</p> 1638 enum RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS 1639 { 1640 RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_DISABLE = 0, //!< When programmed to 0h, normal data will be returned on RGBA channels, including contribution from border color texels. 1641 RETURN_FILTER_WEIGHT_FOR_BORDER_TEXELS_ENABLE = 1, //!< When programmed to 1h, RGB channels return filter data contributed from non-border color texels, and A channel returns filter weight of contributing texels. 1642 }; 1643 1644 //! \brief TCZ_ADDRESS_CONTROL_MODE 1645 //! \details 1646 //! Controls how the 3rd (TCZ) component of input texture coordinates are 1647 //! mapped to texture map addresses - specifically, how coordinates 1648 //! "outside" the texture are handled (wrap/clamp/mirror).See Address TCX 1649 //! Control Mode above for details 1650 enum TCZ_ADDRESS_CONTROL_MODE 1651 { 1652 TCZ_ADDRESS_CONTROL_MODE_WRAP = 0, //!< No additional details 1653 TCZ_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< No additional details 1654 TCZ_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< No additional details 1655 TCZ_ADDRESS_CONTROL_MODE_CUBE = 3, //!< No additional details 1656 TCZ_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< No additional details 1657 TCZ_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< No additional details 1658 TCZ_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< No additional details 1659 TCZ_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< No additional details 1660 }; 1661 1662 //! \brief TCY_ADDRESS_CONTROL_MODE 1663 //! \details 1664 //! Controls how the 2nd (TCY, aka V) component of input texture coordinates 1665 //! are mapped to texture map addresses - specifically, how coordinates 1666 //! "outside" the texture are handled (wrap/clamp/mirror). See Address TCX 1667 //! Control Mode above for details 1668 enum TCY_ADDRESS_CONTROL_MODE 1669 { 1670 TCY_ADDRESS_CONTROL_MODE_WRAP = 0, //!< No additional details 1671 TCY_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< No additional details 1672 TCY_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< No additional details 1673 TCY_ADDRESS_CONTROL_MODE_CUBE = 3, //!< No additional details 1674 TCY_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< No additional details 1675 TCY_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< No additional details 1676 TCY_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< No additional details 1677 TCY_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< No additional details 1678 }; 1679 1680 //! \brief TCX_ADDRESS_CONTROL_MODE 1681 //! \details 1682 //! Controls how the 1st (TCX, aka U) component of input texture coordinates 1683 //! are mapped to texture map addresses - specifically, how coordinates 1684 //! "outside" the texture are handled (wrap/clamp/mirror). The setting of 1685 //! this field is subject to being overridden by the Cube Surface Control 1686 //! Mode field when sampling from a SURFTYPE_CUBE surface. 1687 enum TCX_ADDRESS_CONTROL_MODE 1688 { 1689 TCX_ADDRESS_CONTROL_MODE_WRAP = 0, //!< No additional details 1690 TCX_ADDRESS_CONTROL_MODE_MIRROR = 1, //!< No additional details 1691 TCX_ADDRESS_CONTROL_MODE_CLAMP = 2, //!< No additional details 1692 TCX_ADDRESS_CONTROL_MODE_CUBE = 3, //!< No additional details 1693 TCX_ADDRESS_CONTROL_MODE_CLAMPBORDER = 4, //!< No additional details 1694 TCX_ADDRESS_CONTROL_MODE_MIRRORONCE = 5, //!< No additional details 1695 TCX_ADDRESS_CONTROL_MODE_HALFBORDER = 6, //!< No additional details 1696 TCX_ADDRESS_CONTROL_MODE_MIRROR101 = 7, //!< No additional details 1697 }; 1698 1699 //! \brief TRILINEAR_FILTER_QUALITY 1700 //! \details 1701 //! Selects the quality level for the trilinear filter. 1702 enum TRILINEAR_FILTER_QUALITY 1703 { 1704 TRILINEAR_FILTER_QUALITY_FULL = 0, //!< Full Quality. Both mip maps are sampled under all circumstances. 1705 TRILINEAR_FILTER_QUALITY_TRIQUALHIGHMAGCLAMPMIPFILTER = 1, //!< If [Trilinear Filter Quality Mode Gen11] High Quality. Same as full quality. <!--StartFragment-->Same as full quality. When in magnification mode, Sampler will clamp LOD based on the value of Mip Mode Filter.<!--EndFragment-->If [Trilinear Filter Quality Mode] LOD values which are within 12.5% of an integer LOD value are rounded to that value prior to filtering and filtering effectively becomes the same as MIP Nearest. 1706 TRILINEAR_FILTER_QUALITY_MED = 2, //!< If [Trilinear Filter Quality Mode Gen11] Medium Quality. If the contribution of one mip map is less than 25%, only the other mip map contributes.If [Trilinear Filter Quality Mode] LOD values which are within 16.67% of an integer LOD value are rounded to that value prior to filtering and filtering effectively becomes the same as MIP Nearest. 1707 TRILINEAR_FILTER_QUALITY_LOW = 3, //!< If [Trilinear Filter Quality Mode Gen11] Low Quality. If the contribution of one mip map is less than 37.5%, only the other mip map contributes.If [Trilinear Filter Quality Mode] Should not be used. 1708 }; 1709 1710 //! \brief MAXIMUM_ANISOTROPY 1711 //! \details 1712 //! This field clamps the maximum value of the anisotropy ratio used by the 1713 //! MAPFILTER_ANISOTROPIC filter (Min or Mag Mode Filter). 1714 enum MAXIMUM_ANISOTROPY 1715 { 1716 MAXIMUM_ANISOTROPY_RATIO21 = 0, //!< At most a 2:1 aspect ratio filter is used 1717 MAXIMUM_ANISOTROPY_RATIO41 = 1, //!< At most a 4:1 aspect ratio filter is used 1718 MAXIMUM_ANISOTROPY_RATIO61 = 2, //!< At most a 6:1 aspect ratio filter is used 1719 MAXIMUM_ANISOTROPY_RATIO81 = 3, //!< At most a 8:1 aspect ratio filter is used 1720 MAXIMUM_ANISOTROPY_RATIO101 = 4, //!< At most a 10:1 aspect ratio filter is used 1721 MAXIMUM_ANISOTROPY_RATIO121 = 5, //!< At most a 12:1 aspect ratio filter is used 1722 MAXIMUM_ANISOTROPY_RATIO141 = 6, //!< At most a 14:1 aspect ratio filter is used 1723 MAXIMUM_ANISOTROPY_RATIO161 = 7, //!< At most a 16:1 aspect ratio filter is used 1724 }; 1725 1726 //! \brief REDUCTION_TYPE 1727 //! \details 1728 //! This field defines the type of reduction that will be performed on the 1729 //! texels in the footprint defined by the <b>Min/Mag/Mip Filter Mode</b> 1730 //! fields. This field is ignored if <b>Reduction Type Enable</b> is 1731 //! disabled. 1732 enum REDUCTION_TYPE 1733 { 1734 REDUCTION_TYPE_STDFILTER = 0, //!< standard filter 1735 REDUCTION_TYPE_COMPARISON = 1, //!< comparison followed by standard filter 1736 REDUCTION_TYPE_MINIMUM = 2, //!< minimum of footprint 1737 REDUCTION_TYPE_MAXIMUM = 3, //!< maximum of footprint 1738 }; 1739 1740 //! \name Initializations 1741 1742 //! \brief Explicit member initialization function 1743 SAMPLER_STATE_CMD(); 1744 1745 static const size_t dwSize = 4; 1746 static const size_t byteSize = 16; 1747 }; 1748 1749 //! 1750 //! \brief SAMPLER_STATE_8x8_AVS_COEFFICIENTS 1751 //! \details 1752 //! ExistsIf = AVS && (Function_mode = 0) 1753 //! 1754 struct SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD 1755 { 1756 union 1757 { 1758 //!< DWORD 0 1759 struct 1760 { 1761 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,0] 1762 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,0] 1763 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,1] 1764 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,1] 1765 }; 1766 uint32_t Value; 1767 } DW0; 1768 union 1769 { 1770 //!< DWORD 1 1771 struct 1772 { 1773 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,2] 1774 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,2] 1775 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,3] 1776 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,3] 1777 }; 1778 uint32_t Value; 1779 } DW1; 1780 union 1781 { 1782 //!< DWORD 2 1783 struct 1784 { 1785 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,4] 1786 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,4] 1787 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,5] 1788 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,5] 1789 }; 1790 uint32_t Value; 1791 } DW2; 1792 union 1793 { 1794 //!< DWORD 3 1795 struct 1796 { 1797 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[n,6] 1798 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[n,6] 1799 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[n,7] 1800 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[n,7] 1801 }; 1802 uint32_t Value; 1803 } DW3; 1804 union 1805 { 1806 //!< DWORD 4 1807 struct 1808 { 1809 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1810 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[n,2] 1811 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1X Filter Coefficient[n,3] 1812 }; 1813 uint32_t Value; 1814 } DW4; 1815 union 1816 { 1817 //!< DWORD 5 1818 struct 1819 { 1820 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[n,4] 1821 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1X Filter Coefficient[n,5] 1822 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1823 }; 1824 uint32_t Value; 1825 } DW5; 1826 union 1827 { 1828 //!< DWORD 6 1829 struct 1830 { 1831 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 1832 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1Y Filter Coefficient[n,2] 1833 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[n,3] 1834 }; 1835 uint32_t Value; 1836 } DW6; 1837 union 1838 { 1839 //!< DWORD 7 1840 struct 1841 { 1842 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1Y Filter Coefficient[n,4] 1843 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[n,5] 1844 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1845 }; 1846 uint32_t Value; 1847 } DW7; 1848 1849 //! \name Local enumerations 1850 1851 //! \name Initializations 1852 1853 //! \brief Explicit member initialization function 1854 SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD(); 1855 1856 static const size_t dwSize = 8; 1857 static const size_t byteSize = 32; 1858 }; 1859 1860 //! 1861 //! \brief SAMPLER_STATE_8x8_AVS 1862 //! \details 1863 //! ExistsIf = AVS && (Function_mode = 0) 1864 //! 1865 struct SAMPLER_STATE_8x8_AVS_CMD 1866 { 1867 union 1868 { 1869 //!< DWORD 0 1870 struct 1871 { 1872 uint32_t GainFactor : __CODEGEN_BITFIELD( 0, 5) ; //!< GAIN_FACTOR 1873 uint32_t WeakEdgeThreshold : __CODEGEN_BITFIELD( 6, 11) ; //!< WEAK_EDGE_THRESHOLD 1874 uint32_t StrongEdgeThreshold : __CODEGEN_BITFIELD(12, 17) ; //!< STRONG_EDGE_THRESHOLD 1875 uint32_t R3XCoefficient : __CODEGEN_BITFIELD(18, 22) ; //!< R3X_COEFFICIENT 1876 uint32_t R3CCoefficient : __CODEGEN_BITFIELD(23, 27) ; //!< R3C_COEFFICIENT 1877 uint32_t Reserved28 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1878 }; 1879 uint32_t Value; 1880 } DW0; 1881 union 1882 { 1883 //!< DWORD 1 1884 struct 1885 { 1886 uint32_t Reserved32 ; //!< Reserved 1887 }; 1888 uint32_t Value; 1889 } DW1; 1890 union 1891 { 1892 //!< DWORD 2 1893 struct 1894 { 1895 uint32_t GlobalNoiseEstimation : __CODEGEN_BITFIELD( 0, 7) ; //!< GLOBAL_NOISE_ESTIMATION 1896 uint32_t NonEdgeWeight : __CODEGEN_BITFIELD( 8, 10) ; //!< NON_EDGE_WEIGHT 1897 uint32_t RegularWeight : __CODEGEN_BITFIELD(11, 13) ; //!< REGULAR_WEIGHT 1898 uint32_t StrongEdgeWeight : __CODEGEN_BITFIELD(14, 16) ; //!< STRONG_EDGE_WEIGHT 1899 uint32_t R5XCoefficient : __CODEGEN_BITFIELD(17, 21) ; //!< R5X_COEFFICIENT 1900 uint32_t R5CxCoefficient : __CODEGEN_BITFIELD(22, 26) ; //!< R5CX_COEFFICIENT 1901 uint32_t R5CCoefficient : __CODEGEN_BITFIELD(27, 31) ; //!< R5C_COEFFICIENT 1902 }; 1903 uint32_t Value; 1904 } DW2; 1905 union 1906 { 1907 //!< DWORD 3 1908 struct 1909 { 1910 uint32_t SinAlpha : __CODEGEN_BITFIELD( 0, 7) ; //!< Sin(alpha) 1911 uint32_t CosAlpha : __CODEGEN_BITFIELD( 8, 15) ; //!< Cos(alpha) 1912 uint32_t SatMax : __CODEGEN_BITFIELD(16, 21) ; //!< SAT_MAX 1913 uint32_t HueMax : __CODEGEN_BITFIELD(22, 27) ; //!< HUE_MAX 1914 uint32_t Enable8TapFilter : __CODEGEN_BITFIELD(28, 29) ; //!< ENABLE_8_TAP_FILTER 1915 uint32_t Ief4SmoothEnable : __CODEGEN_BITFIELD(30, 30) ; //!< IEF4SMOOTH_ENABLE_ 1916 uint32_t SkinToneTunedIefEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SKIN_TONE_TUNED_IEF__ENABLE 1917 }; 1918 uint32_t Value; 1919 } DW3; 1920 union 1921 { 1922 //!< DWORD 4 1923 struct 1924 { 1925 uint32_t S3U : __CODEGEN_BITFIELD( 0, 10) ; //!< S3U 1926 uint32_t ShuffleOutputwritebackForSample8X8 : __CODEGEN_BITFIELD(11, 11) ; //!< SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 1927 uint32_t DiamondMargin : __CODEGEN_BITFIELD(12, 14) ; //!< DIAMOND_MARGIN 1928 uint32_t VyStdEnable : __CODEGEN_BITFIELD(15, 15) ; //!< VY_STD_Enable 1929 uint32_t UMid : __CODEGEN_BITFIELD(16, 23) ; //!< U_MID 1930 uint32_t VMid : __CODEGEN_BITFIELD(24, 31) ; //!< V_MID 1931 }; 1932 uint32_t Value; 1933 } DW4; 1934 union 1935 { 1936 //!< DWORD 5 1937 struct 1938 { 1939 uint32_t DiamondDv : __CODEGEN_BITFIELD( 0, 6) ; //!< DIAMOND_DV 1940 uint32_t DiamondTh : __CODEGEN_BITFIELD( 7, 12) ; //!< DIAMOND_TH 1941 uint32_t DiamondAlpha : __CODEGEN_BITFIELD(13, 20) ; //!< Diamond_alpha 1942 uint32_t HsMargin : __CODEGEN_BITFIELD(21, 23) ; //!< HS_MARGIN 1943 uint32_t DiamondDu : __CODEGEN_BITFIELD(24, 30) ; //!< DIAMOND_DU 1944 uint32_t Skindetailfactor : __CODEGEN_BITFIELD(31, 31) ; //!< SKINDETAILFACTOR_ 1945 }; 1946 uint32_t Value; 1947 } DW5; 1948 union 1949 { 1950 //!< DWORD 6 1951 struct 1952 { 1953 uint32_t YPoint1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y_POINT_1 1954 uint32_t YPoint2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y_POINT_2 1955 uint32_t YPoint3 : __CODEGEN_BITFIELD(16, 23) ; //!< Y_POINT_3 1956 uint32_t YPoint4 : __CODEGEN_BITFIELD(24, 31) ; //!< Y_POINT_4 1957 }; 1958 uint32_t Value; 1959 } DW6; 1960 union 1961 { 1962 //!< DWORD 7 1963 struct 1964 { 1965 uint32_t InvMarginVyl : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYL 1966 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1967 }; 1968 uint32_t Value; 1969 } DW7; 1970 union 1971 { 1972 //!< DWORD 8 1973 struct 1974 { 1975 uint32_t InvMarginVyu : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYU 1976 uint32_t P0L : __CODEGEN_BITFIELD(16, 23) ; //!< P0L 1977 uint32_t P1L : __CODEGEN_BITFIELD(24, 31) ; //!< P1L 1978 }; 1979 uint32_t Value; 1980 } DW8; 1981 union 1982 { 1983 //!< DWORD 9 1984 struct 1985 { 1986 uint32_t P2L : __CODEGEN_BITFIELD( 0, 7) ; //!< P2L 1987 uint32_t P3L : __CODEGEN_BITFIELD( 8, 15) ; //!< P3L 1988 uint32_t B0L : __CODEGEN_BITFIELD(16, 23) ; //!< B0L 1989 uint32_t B1L : __CODEGEN_BITFIELD(24, 31) ; //!< B1L 1990 }; 1991 uint32_t Value; 1992 } DW9; 1993 union 1994 { 1995 //!< DWORD 10 1996 struct 1997 { 1998 uint32_t B2L : __CODEGEN_BITFIELD( 0, 7) ; //!< B2L 1999 uint32_t B3L : __CODEGEN_BITFIELD( 8, 15) ; //!< B3L 2000 uint32_t S0L : __CODEGEN_BITFIELD(16, 26) ; //!< S0L 2001 uint32_t YSlope2 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope_2 2002 }; 2003 uint32_t Value; 2004 } DW10; 2005 union 2006 { 2007 //!< DWORD 11 2008 struct 2009 { 2010 uint32_t S1L : __CODEGEN_BITFIELD( 0, 10) ; //!< S1L 2011 uint32_t S2L : __CODEGEN_BITFIELD(11, 21) ; //!< S2L 2012 uint32_t Reserved374 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 2013 }; 2014 uint32_t Value; 2015 } DW11; 2016 union 2017 { 2018 //!< DWORD 12 2019 struct 2020 { 2021 uint32_t S3L : __CODEGEN_BITFIELD( 0, 10) ; //!< S3L 2022 uint32_t P0U : __CODEGEN_BITFIELD(11, 18) ; //!< P0U 2023 uint32_t P1U : __CODEGEN_BITFIELD(19, 26) ; //!< P1U 2024 uint32_t YSlope1 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope1 2025 }; 2026 uint32_t Value; 2027 } DW12; 2028 union 2029 { 2030 //!< DWORD 13 2031 struct 2032 { 2033 uint32_t P2U : __CODEGEN_BITFIELD( 0, 7) ; //!< P2U 2034 uint32_t P3U : __CODEGEN_BITFIELD( 8, 15) ; //!< P3U 2035 uint32_t B0U : __CODEGEN_BITFIELD(16, 23) ; //!< B0U 2036 uint32_t B1U : __CODEGEN_BITFIELD(24, 31) ; //!< B1U 2037 }; 2038 uint32_t Value; 2039 } DW13; 2040 union 2041 { 2042 //!< DWORD 14 2043 struct 2044 { 2045 uint32_t B2U : __CODEGEN_BITFIELD( 0, 7) ; //!< B2U 2046 uint32_t B3U : __CODEGEN_BITFIELD( 8, 15) ; //!< B3U 2047 uint32_t S0U : __CODEGEN_BITFIELD(16, 26) ; //!< S0U 2048 uint32_t Reserved475 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 2049 }; 2050 uint32_t Value; 2051 } DW14; 2052 union 2053 { 2054 //!< DWORD 15 2055 struct 2056 { 2057 uint32_t S1U : __CODEGEN_BITFIELD( 0, 10) ; //!< S1U 2058 uint32_t S2U : __CODEGEN_BITFIELD(11, 21) ; //!< S2U 2059 uint32_t Reserved502 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 2060 }; 2061 uint32_t Value; 2062 } DW15; 2063 2064 mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient016[17]; //!< Filter Coefficient[0..16] 2065 2066 union 2067 { 2068 //!< DWORD 152 2069 struct 2070 { 2071 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 2072 uint32_t Reserved4867 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 2073 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 2074 uint32_t Reserved4871 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 2075 uint32_t MaxDerivative8Pixels : __CODEGEN_BITFIELD( 8, 15) ; //!< Max Derivative 8 Pixels 2076 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 2077 uint32_t DefaultSharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< DEFAULT_SHARPNESS_LEVEL 2078 }; 2079 uint32_t Value; 2080 } DW152; 2081 union 2082 { 2083 //!< DWORD 153 2084 struct 2085 { 2086 uint32_t RgbAdaptive : __CODEGEN_BITFIELD( 0, 0) ; //!< RGB_ADAPTIVE 2087 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2088 uint32_t Reserved4898 : __CODEGEN_BITFIELD( 2, 20) ; //!< Reserved 2089 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD(21, 21) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 2090 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD(22, 22) ; //!< BYPASS_X_ADAPTIVE_FILTERING 2091 uint32_t Reserved4919 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 2092 }; 2093 uint32_t Value; 2094 } DW153; 2095 2096 uint32_t Reserved4928[6]; //!< Reserved 2097 2098 2099 mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD FilterCoefficient1731[15]; //!< Filter Coefficient[17..31] 2100 2101 2102 //! \name Local enumerations 2103 2104 //! \brief GAIN_FACTOR 2105 //! \details 2106 //! User control sharpening strength 2107 enum GAIN_FACTOR 2108 { 2109 GAIN_FACTOR_UNNAMED44 = 44, //!< No additional details 2110 }; 2111 2112 //! \brief WEAK_EDGE_THRESHOLD 2113 //! \details 2114 //! If <b>Strong Edge Threshold</b> > EM > <b>Weak Edge Threshold</b>, 2115 //! the basic VSA detects a weak edge. 2116 enum WEAK_EDGE_THRESHOLD 2117 { 2118 WEAK_EDGE_THRESHOLD_UNNAMED1 = 1, //!< No additional details 2119 }; 2120 2121 //! \brief STRONG_EDGE_THRESHOLD 2122 //! \details 2123 //! If EM > <b>Strong Edge Threshold</b>, the basic VSA detects a strong 2124 //! edge. 2125 enum STRONG_EDGE_THRESHOLD 2126 { 2127 STRONG_EDGE_THRESHOLD_UNNAMED8 = 8, //!< No additional details 2128 }; 2129 2130 //! \brief R3X_COEFFICIENT 2131 //! \details 2132 //! IEF smoothing coefficient, see IEF map. 2133 enum R3X_COEFFICIENT 2134 { 2135 R3X_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 2136 }; 2137 2138 //! \brief R3C_COEFFICIENT 2139 //! \details 2140 //! IEF smoothing coefficient, see IEF map. 2141 enum R3C_COEFFICIENT 2142 { 2143 R3C_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 2144 }; 2145 2146 //! \brief GLOBAL_NOISE_ESTIMATION 2147 //! \details 2148 //! Global noise estimation of previous frame. 2149 enum GLOBAL_NOISE_ESTIMATION 2150 { 2151 GLOBAL_NOISE_ESTIMATION_UNNAMED255 = 255, //!< No additional details 2152 }; 2153 2154 //! \brief NON_EDGE_WEIGHT 2155 //! \details 2156 //! Sharpening strength when no edge is found in basic VSA. 2157 enum NON_EDGE_WEIGHT 2158 { 2159 NON_EDGE_WEIGHT_UNNAMED1 = 1, //!< No additional details 2160 }; 2161 2162 //! \brief REGULAR_WEIGHT 2163 //! \details 2164 //! Sharpening strength when a weak edge is found in basic VSA. 2165 enum REGULAR_WEIGHT 2166 { 2167 REGULAR_WEIGHT_UNNAMED2 = 2, //!< No additional details 2168 }; 2169 2170 //! \brief STRONG_EDGE_WEIGHT 2171 //! \details 2172 //! Sharpening strength when a strong edge is found in basic VSA. 2173 enum STRONG_EDGE_WEIGHT 2174 { 2175 STRONG_EDGE_WEIGHT_UNNAMED7 = 7, //!< No additional details 2176 }; 2177 2178 //! \brief R5X_COEFFICIENT 2179 //! \details 2180 //! IEF smoothing coefficient, see IEF map. 2181 enum R5X_COEFFICIENT 2182 { 2183 R5X_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 2184 }; 2185 2186 //! \brief R5CX_COEFFICIENT 2187 //! \details 2188 //! IEF smoothing coefficient, see IEF map. 2189 enum R5CX_COEFFICIENT 2190 { 2191 R5CX_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 2192 }; 2193 2194 //! \brief R5C_COEFFICIENT 2195 //! \details 2196 //! IEF smoothing coefficient, see IEF map. 2197 enum R5C_COEFFICIENT 2198 { 2199 R5C_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 2200 }; 2201 2202 //! \brief SAT_MAX 2203 //! \details 2204 //! Rectangle half length 2205 enum SAT_MAX 2206 { 2207 SAT_MAX_UNNAMED31 = 31, //!< No additional details 2208 }; 2209 2210 //! \brief HUE_MAX 2211 //! \details 2212 //! Rectangle half width. 2213 enum HUE_MAX 2214 { 2215 HUE_MAX_UNNAMED14 = 14, //!< No additional details 2216 }; 2217 2218 //! \brief ENABLE_8_TAP_FILTER 2219 //! \details 2220 //! <i><b>Adaptive Filtering (Mode = 11) ExistsIf:</b></i> 2221 //! <p></p> R10G10B10A2_UNORM R8G8B8A8_UNORM (AYUV also) R8B8G8A8_UNORM 2222 //! B8G8R8A8_UNORM R16G16B16A16 2223 enum ENABLE_8_TAP_FILTER 2224 { 2225 ENABLE_8_TAP_FILTER_UNNAMED0 = 0, //!< 4-tap filter is only done on all channels. 2226 ENABLE_8_TAP_FILTER_UNNAMED1 = 1, //!< Enable 8-tap Adaptive filter on G-channel. 4-tap filter on other channels. 2227 ENABLE_8_TAP_FILTER_UNNAMED2 = 2, //!< 8-tap filter is done on all channels (UV-ch uses the Y-coefficients) 2228 ENABLE_8_TAP_FILTER_UNNAMED3 = 3, //!< Enable 8-tap Adaptive filter all channels (UV-ch uses the Y-coefficients). 2229 }; 2230 2231 enum IEF4SMOOTH_ENABLE_ 2232 { 2233 IEF4SMOOTH_ENABLE_UNNAMED0 = 0, //!< IEF is operating as a content adaptive detail filter based on 5x5 region 2234 IEF4SMOOTH_ENABLE_UNNAMED1 = 1, //!< IEF is operating as a content adaptive smooth filter based on 3x3 region 2235 }; 2236 2237 //! \brief SKIN_TONE_TUNED_IEF__ENABLE 2238 //! \details 2239 //! Control bit to enable the skin tone tuned IEF. 2240 enum SKIN_TONE_TUNED_IEF__ENABLE 2241 { 2242 SKIN_TONE_TUNED_IEF_ENABLE_UNNAMED1 = 1, //!< No additional details 2243 }; 2244 2245 enum SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8 2246 { 2247 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED0 = 0, //!< Writeback same as Original Sample_8x8 2248 SHUFFLE_OUTPUTWRITEBACK_FOR_SAMPLE_8X8_UNNAMED1 = 1, //!< Writeback of Sample_8x8 Is Modified to Suite Sample_Unorm 2249 }; 2250 2251 enum DIAMOND_MARGIN 2252 { 2253 DIAMOND_MARGIN_UNNAMED4 = 4, //!< No additional details 2254 }; 2255 2256 //! \brief U_MID 2257 //! \details 2258 //! Rectangle middle-point U coordinate. 2259 enum U_MID 2260 { 2261 U_MID_UNNAMED110 = 110, //!< No additional details 2262 }; 2263 2264 //! \brief V_MID 2265 //! \details 2266 //! Rectangle middle-point V coordinate. 2267 enum V_MID 2268 { 2269 V_MID_UNNAMED154 = 154, //!< No additional details 2270 }; 2271 2272 //! \brief DIAMOND_DV 2273 //! \details 2274 //! Rhombus center shift in the hue-direction, relative to the rectangle 2275 //! center. 2276 enum DIAMOND_DV 2277 { 2278 DIAMOND_DV_UNNAMED0 = 0, //!< No additional details 2279 }; 2280 2281 //! \brief DIAMOND_TH 2282 //! \details 2283 //! Half length of the rhombus axis in the sat-direction. 2284 enum DIAMOND_TH 2285 { 2286 DIAMOND_TH_UNNAMED35 = 35, //!< No additional details 2287 }; 2288 2289 //! \brief HS_MARGIN 2290 //! \details 2291 //! Defines rectangle margin 2292 enum HS_MARGIN 2293 { 2294 HS_MARGIN_UNNAMED3 = 3, //!< No additional details 2295 }; 2296 2297 //! \brief DIAMOND_DU 2298 //! \details 2299 //! Rhombus center shift in the sat-direction, relative to the rectangle 2300 //! center. 2301 enum DIAMOND_DU 2302 { 2303 DIAMOND_DU_UNNAMED2 = 2, //!< No additional details 2304 }; 2305 2306 //! \brief SKINDETAILFACTOR_ 2307 //! \details 2308 //! This flag bit is in operation only when the control bit <b>Skin Tone 2309 //! TunedIEF_Enable</b> is on. 2310 enum SKINDETAILFACTOR_ 2311 { 2312 SKINDETAILFACTOR_UNNAMED0 = 0, //!< sign(SkinDetailFactor) is equal to -1, and the content of the detected skin tone area is detail revealed. 2313 SKINDETAILFACTOR_UNNAMED1 = 1, //!< sign(SkinDetailFactor) is equal to +1, and the content of the detected skin tone area is not detail revealed. 2314 }; 2315 2316 //! \brief Y_POINT_1 2317 //! \details 2318 //! First point of the Y piecewise linear membership function. 2319 enum Y_POINT_1 2320 { 2321 Y_POINT_1_UNNAMED46 = 46, //!< No additional details 2322 }; 2323 2324 //! \brief Y_POINT_2 2325 //! \details 2326 //! Second point of the Y piecewise linear membership function. 2327 enum Y_POINT_2 2328 { 2329 Y_POINT_2_UNNAMED47 = 47, //!< No additional details 2330 }; 2331 2332 //! \brief Y_POINT_3 2333 //! \details 2334 //! Third point of the Y piecewise linear membership function. 2335 enum Y_POINT_3 2336 { 2337 Y_POINT_3_UNNAMED254 = 254, //!< No additional details 2338 }; 2339 2340 //! \brief Y_POINT_4 2341 //! \details 2342 //! Fourth point of the Y piecewise linear membership function. 2343 enum Y_POINT_4 2344 { 2345 Y_POINT_4_UNNAMED255 = 255, //!< No additional details 2346 }; 2347 2348 //! \brief P0L 2349 //! \details 2350 //! Y Point 0 of the lower part of the detection PWLF. 2351 enum P0L 2352 { 2353 P0L_UNNAMED46 = 46, //!< No additional details 2354 }; 2355 2356 //! \brief P1L 2357 //! \details 2358 //! Y Point 1 of the lower part of the detection PWLF. 2359 enum P1L 2360 { 2361 P1L_UNNAMED216 = 216, //!< No additional details 2362 }; 2363 2364 //! \brief P2L 2365 //! \details 2366 //! Y Point 2 of the lower part of the detection PWLF. 2367 enum P2L 2368 { 2369 P2L_UNNAMED236 = 236, //!< No additional details 2370 }; 2371 2372 //! \brief P3L 2373 //! \details 2374 //! Y Point 3 of the lower part of the detection PWLF. 2375 enum P3L 2376 { 2377 P3L_UNNAMED236 = 236, //!< No additional details 2378 }; 2379 2380 //! \brief B0L 2381 //! \details 2382 //! V Bias 0 of the lower part of the detection PWLF. 2383 enum B0L 2384 { 2385 B0L_UNNAMED133 = 133, //!< No additional details 2386 }; 2387 2388 //! \brief B1L 2389 //! \details 2390 //! V Bias 1 of the lower part of the detection PWLF. 2391 enum B1L 2392 { 2393 B1L_UNNAMED130 = 130, //!< No additional details 2394 }; 2395 2396 enum B2L 2397 { 2398 B2L_UNNAMED130 = 130, //!< No additional details 2399 }; 2400 2401 //! \brief B3L 2402 //! \details 2403 //! V Bias 3 of the lower part of the detection PWLF. 2404 enum B3L 2405 { 2406 B3L_UNNAMED130 = 130, //!< No additional details 2407 }; 2408 2409 //! \brief P0U 2410 //! \details 2411 //! Y Point 0 of the upper part of the detection PWLF. 2412 enum P0U 2413 { 2414 P0U_UNNAMED46 = 46, //!< No additional details 2415 }; 2416 2417 //! \brief P1U 2418 //! \details 2419 //! Y Point 1 of the upper part of the detection PWLF. 2420 enum P1U 2421 { 2422 P1U_UNNAMED66 = 66, //!< No additional details 2423 }; 2424 2425 //! \brief P2U 2426 //! \details 2427 //! Y Point 2 of the upper part of the detection PWLF. 2428 enum P2U 2429 { 2430 P2U_UNNAMED150 = 150, //!< No additional details 2431 }; 2432 2433 //! \brief P3U 2434 //! \details 2435 //! Y Point 3 of the upper part of the detection PWLF. 2436 enum P3U 2437 { 2438 P3U_UNNAMED236 = 236, //!< No additional details 2439 }; 2440 2441 //! \brief B0U 2442 //! \details 2443 //! V Bias 0 of the upper part of the detection PWLF. 2444 enum B0U 2445 { 2446 B0U_UNNAMED143 = 143, //!< No additional details 2447 }; 2448 2449 //! \brief B1U 2450 //! \details 2451 //! V Bias 1 of the upper part of the detection PWLF. 2452 enum B1U 2453 { 2454 B1U_UNNAMED163 = 163, //!< No additional details 2455 }; 2456 2457 //! \brief B2U 2458 //! \details 2459 //! V Bias 2 of the upper part of the detection PWLF. 2460 enum B2U 2461 { 2462 B2U_UNNAMED200 = 200, //!< No additional details 2463 }; 2464 2465 //! \brief B3U 2466 //! \details 2467 //! V Bias 3 of the upper part of the detection PWLF. 2468 enum B3U 2469 { 2470 B3U_UNNAMED140 = 140, //!< No additional details 2471 }; 2472 2473 //! \brief DEFAULT_SHARPNESS_LEVEL 2474 //! \details 2475 //! When adaptive scaling is off, determines the balance between sharp and 2476 //! smooth scalers. 2477 enum DEFAULT_SHARPNESS_LEVEL 2478 { 2479 DEFAULT_SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 2480 DEFAULT_SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 2481 }; 2482 2483 //! \brief RGB_ADAPTIVE 2484 //! \details 2485 //! This should be always set to 0 for YUV input and can be enabled/disabled 2486 //! for RGB input. 2487 //! This should be enabled only if we enable 8-tap adaptive filter for 2488 //! RGB input. 2489 enum RGB_ADAPTIVE 2490 { 2491 RGB_ADAPTIVE_DISBLE = 0, //!< Disable the RGB Adaptive equation and use G-Ch directly for adaptive filter 2492 RGB_ADAPTIVE_ENABLE = 1, //!< Enable the RGB Adaptive filter using the equation (Y=(R+2G+B)>>2) 2493 }; 2494 2495 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2496 //! \details 2497 //! Only to be enabled if 8-tap Adaptive filter mode is on, eElse it should 2498 //! be disabled. 2499 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2500 { 2501 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISBLE = 0, //!< Disable Adaptive Filter on UV/RB Channels 2502 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLE = 1, //!< Enable Adaptive Filter on UV/RB Channels 2503 }; 2504 2505 //! \brief BYPASS_Y_ADAPTIVE_FILTERING 2506 //! \details 2507 //! When disabled, the Y direction will use <b>Default Sharpness Level</b> 2508 //! to blend between the smooth and sharp filters rather than the calculated 2509 //! value. 2510 enum BYPASS_Y_ADAPTIVE_FILTERING 2511 { 2512 BYPASS_Y_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable Y Adaptive Filtering 2513 BYPASS_Y_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable Y Adaptive Filtering 2514 }; 2515 2516 //! \brief BYPASS_X_ADAPTIVE_FILTERING 2517 //! \details 2518 //! When disabled, the X direction will use <b>Default Sharpness Level</b> 2519 //! to blend between the smooth and sharp filters rather than the calculated 2520 //! value. 2521 enum BYPASS_X_ADAPTIVE_FILTERING 2522 { 2523 BYPASS_X_ADAPTIVE_FILTERING_ENABLE = 0, //!< Enable X Adaptive Filtering 2524 BYPASS_X_ADAPTIVE_FILTERING_DISBLE = 1, //!< Disable X Adaptive Filtering 2525 }; 2526 2527 //! \name Initializations 2528 2529 //! \brief Explicit member initialization function 2530 SAMPLER_STATE_8x8_AVS_CMD(); 2531 2532 static const size_t dwSize = 280; 2533 static const size_t byteSize = 1120; 2534 }; 2535 2536 //! 2537 //! \brief SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS 2538 //! \details 2539 //! Function: 0001b ExistsIf: [Convolve] && [SKL_mode==0] && 2540 //! [(Kernel Size) =< (15x15)] 2541 //! 2542 //! Function: 1010b ExistsIf: "[1Pixel Convolution ] && [(Kernel 2543 //! Size) =< (15x15)] 2544 //! 2545 //! Function: 0001b ExistsIf: [Convolve] && [SKL_mode==1] && 2546 //! [(Kernel Size) > (15x15)] 2547 //! 2548 struct SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS_CMD 2549 { 2550 union 2551 { 2552 //!< DWORD 0 2553 struct 2554 { 2555 uint32_t FilterCoefficient00 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,0] 2556 uint32_t FilterCoefficient01 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,1] 2557 }; 2558 uint32_t Value; 2559 } DW0; 2560 union 2561 { 2562 //!< DWORD 1 2563 struct 2564 { 2565 uint32_t FilterCoefficient02 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,2] 2566 uint32_t FilterCoefficient03 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,3] 2567 }; 2568 uint32_t Value; 2569 } DW1; 2570 union 2571 { 2572 //!< DWORD 2 2573 struct 2574 { 2575 uint32_t FilterCoefficient04 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,4] 2576 uint32_t FilterCoefficient05 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,5] 2577 }; 2578 uint32_t Value; 2579 } DW2; 2580 union 2581 { 2582 //!< DWORD 3 2583 struct 2584 { 2585 uint32_t FilterCoefficient06 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,6] 2586 uint32_t FilterCoefficient07 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,7] 2587 }; 2588 uint32_t Value; 2589 } DW3; 2590 union 2591 { 2592 //!< DWORD 4 2593 struct 2594 { 2595 uint32_t FilterCoefficient08 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,8] 2596 uint32_t FilterCoefficient09 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,9] 2597 }; 2598 uint32_t Value; 2599 } DW4; 2600 union 2601 { 2602 //!< DWORD 5 2603 struct 2604 { 2605 uint32_t FilterCoefficient010 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,10] 2606 uint32_t FilterCoefficient011 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,11] 2607 }; 2608 uint32_t Value; 2609 } DW5; 2610 union 2611 { 2612 //!< DWORD 6 2613 struct 2614 { 2615 uint32_t FilterCoefficient012 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,12] 2616 uint32_t FilterCoefficient013 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,13] 2617 }; 2618 uint32_t Value; 2619 } DW6; 2620 union 2621 { 2622 //!< DWORD 7 2623 struct 2624 { 2625 uint32_t FilterCoefficient014 : __CODEGEN_BITFIELD( 0, 15) ; //!< Filter Coefficient[0,14] 2626 uint32_t FilterCoefficient015 : __CODEGEN_BITFIELD(16, 31) ; //!< Filter Coefficient[0,15] 2627 }; 2628 uint32_t Value; 2629 } DW7; 2630 2631 //! \name Local enumerations 2632 2633 //! \name Initializations 2634 2635 //! \brief Explicit member initialization function 2636 SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS_CMD(); 2637 2638 static const size_t dwSize = 8; 2639 static const size_t byteSize = 32; 2640 }; 2641 2642 //! 2643 //! \brief SAMPLER_STATE_8x8_CONVOLVE 2644 //! \details 2645 //! Function: 0001b ExistsIf: [Convolve] && [SKL_mode==0] && 2646 //! [(Kernel Size) =< (15x15)] 2647 //! 2648 //! Function: 1010b ExistsIf: "[1Pixel Convolution ] && [(Kernel 2649 //! Size) =< (15x15)] 2650 //! 2651 //! Function: 0001b ExistsIf: [Convolve] && [SKL_mode==1] && 2652 //! [(Kernel Size) > (15x15)] 2653 //! 2654 struct SAMPLER_STATE_8x8_CONVOLVE_CMD 2655 { 2656 union 2657 { 2658 //!< DWORD 0 2659 struct 2660 { 2661 uint32_t Height : __CODEGEN_BITFIELD( 0, 3) ; //!< HEIGHT 2662 uint32_t Width : __CODEGEN_BITFIELD( 4, 7) ; //!< WIDTH 2663 uint32_t ScaleDownValue : __CODEGEN_BITFIELD( 8, 11) ; //!< Scale down value 2664 uint32_t SizeOfTheCoefficient : __CODEGEN_BITFIELD(12, 12) ; //!< SIZE_OF_THE_COEFFICIENT 2665 uint32_t Reserved13 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 2666 uint32_t MsbHeight : __CODEGEN_BITFIELD(16, 16) ; //!< MSB_HEIGHT 2667 uint32_t Reserved17 : __CODEGEN_BITFIELD(17, 19) ; //!< Reserved 2668 uint32_t MsbWidth : __CODEGEN_BITFIELD(20, 20) ; //!< MSB_WIDTH 2669 uint32_t Reserved21 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 2670 }; 2671 uint32_t Value; 2672 } DW0; 2673 2674 uint32_t Reserved32[15]; //!< Reserved 2675 2676 2677 mhw_state_heap_g11_X::SAMPLER_STATE_8x8_CONVOLVE_COEFFICIENTS_CMD FilterCoefficient300310[62]; //!< Filter Coefficient[30:0,31:0] 2678 2679 2680 //! \name Local enumerations 2681 2682 enum SIZE_OF_THE_COEFFICIENT 2683 { 2684 SIZE_OF_THE_COEFFICIENT_8BIT = 0, //!< The lower 8 bits of the accumulator is forced to zero or ignored during the accumulation operation. 2685 SIZE_OF_THE_COEFFICIENT_16BIT = 1, //!< The lower 8 bits are also included for the operation. The final result of the accumulator is shifted before clamping the result as specified by the Scale down value.:Result[15:0] = Clamp(Accum[40:12] >> scale_down) 2686 }; 2687 2688 //! \brief MSB_HEIGHT 2689 //! \details 2690 //! It contains the MSB HEIGHT of the kernel and is used to extend the 2691 //! kernel width range to 31. 2692 //! Used along with bits[3:0] which represents the LSB for the kernel 2693 //! Height. 2694 enum MSB_HEIGHT 2695 { 2696 MSB_HEIGHT_NOCHANGE = 0, //!< No Change to the Filter Size 2697 MSB_HEIGHT_EXTENDED = 1, //!< Extends the filter size height upto 31. 2698 }; 2699 2700 //! \brief MSB_WIDTH 2701 //! \details 2702 //! It contains the MSB Width of the kernel and is used to extend the kernel 2703 //! width range to 31. 2704 //! Used along with bits[3:0] which represents the LSB for the kernel 2705 //! Height. 2706 enum MSB_WIDTH 2707 { 2708 MSB_WIDTH_NOCHANGE = 0, //!< No Change to the Filter Size 2709 MSB_WIDTH_EXTENDED = 1, //!< Extends the Filter Size Width upto 31. 2710 }; 2711 2712 //! \name Initializations 2713 2714 //! \brief Explicit member initialization function 2715 SAMPLER_STATE_8x8_CONVOLVE_CMD(); 2716 2717 static const size_t dwSize = 512; 2718 static const size_t byteSize = 2048; 2719 }; 2720 2721 //! 2722 //! \brief SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER 2723 //! \details 2724 //! The table is valid for the following funstions: 0100 - Erode 0101 - 2725 //! Dilate 0011 - MinMaxFilter 2726 //! 2727 //! The table is valid for the following funstions: 0100 - Erode && 2728 //! (Function_mode==0) 0101 - Dilate && (Function_mode==0) 0011 - 2729 //! MinMaxFilter && (Function_mode==0) 2730 //! 2731 //! Max kernel size is 15x15. For sizes less than 15x15 the coefficients not 2732 //! used should be zeroed out. 2733 //! 2734 struct SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER_CMD 2735 { 2736 union 2737 { 2738 //!< DWORD 0 2739 struct 2740 { 2741 uint32_t HeightOfTheKernel : __CODEGEN_BITFIELD( 0, 3) ; //!< Height Of The Kernel 2742 uint32_t WidthOfTheKernel : __CODEGEN_BITFIELD( 4, 7) ; //!< Width Of The Kernel 2743 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 2744 uint32_t BitMask16ForRow0150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row0 [15:0] 2745 }; 2746 uint32_t Value; 2747 } DW0; 2748 union 2749 { 2750 //!< DWORD 1 2751 struct 2752 { 2753 uint32_t BitMask16ForRow1150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row1 [15:0] 2754 uint32_t BitMask16ForRow2150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row2 [15:0] 2755 }; 2756 uint32_t Value; 2757 } DW1; 2758 union 2759 { 2760 //!< DWORD 2 2761 struct 2762 { 2763 uint32_t BitMask16ForRow3150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row3 [15:0] 2764 uint32_t BitMask16ForRow4150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row4 [15:0] 2765 }; 2766 uint32_t Value; 2767 } DW2; 2768 union 2769 { 2770 //!< DWORD 3 2771 struct 2772 { 2773 uint32_t BitMask16ForRow5150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row5 [15:0] 2774 uint32_t BitMask16ForRow6150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row6 [15:0] 2775 }; 2776 uint32_t Value; 2777 } DW3; 2778 union 2779 { 2780 //!< DWORD 4 2781 struct 2782 { 2783 uint32_t BitMask16ForRow7150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row7 [15:0] 2784 uint32_t BitMask16ForRow8150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row8 [15:0] 2785 }; 2786 uint32_t Value; 2787 } DW4; 2788 union 2789 { 2790 //!< DWORD 5 2791 struct 2792 { 2793 uint32_t BitMask16ForRow9150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row9 [15:0] 2794 uint32_t BitMask16ForRow10150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row10 [15:0] 2795 }; 2796 uint32_t Value; 2797 } DW5; 2798 union 2799 { 2800 //!< DWORD 6 2801 struct 2802 { 2803 uint32_t BitMask16ForRow11150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row11 [15:0] 2804 uint32_t BitMask16ForRow12150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row12 [15:0] 2805 }; 2806 uint32_t Value; 2807 } DW6; 2808 union 2809 { 2810 //!< DWORD 7 2811 struct 2812 { 2813 uint32_t BitMask16ForRow13150 : __CODEGEN_BITFIELD( 0, 15) ; //!< 16bit Mask for Row13 [15:0] 2814 uint32_t BitMask16ForRow14150 : __CODEGEN_BITFIELD(16, 31) ; //!< 16bit Mask for Row14 [15:0] 2815 }; 2816 uint32_t Value; 2817 } DW7; 2818 2819 //! \name Local enumerations 2820 2821 //! \name Initializations 2822 2823 //! \brief Explicit member initialization function 2824 SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER_CMD(); 2825 2826 static const size_t dwSize = 8; 2827 static const size_t byteSize = 32; 2828 }; 2829 2830 //! 2831 //! \brief SAMPLER_INDIRECT_STATE 2832 //! \details 2833 //! Note: There are three variations of this structure, defined separately 2834 //! because their payloads have different lengths. Currently only 2835 //! SAMPLER_INDIRECT_STATE_BORDER_COLOR is fully defined. 2836 //! This structure is pointed to by Indirect State Pointer (SAMPLER_STATE). 2837 //! The interpretation of the border color depends on the Texture Border 2838 //! Color Mode field in SAMPLER_STATE as follows: 2839 //! 2840 //! In 8 bit mode, the border color is 8-bit UNORM format, regardless of the 2841 //! surface format chosen. For surface formats with one or more channels 2842 //! missing (i.e. R5G6R5_UNORM is missing the alpha channel), the value from 2843 //! the border color, if selected, will be used even for the missing 2844 //! channels. 2845 //! 2846 //! In OGL mode, the format of the border color is R32G32B32A32_FLOAT, 2847 //! R32G32B32A32_SINT, or R32G32B32A32_UINT, depending on the surface format 2848 //! chosen. For surface formats with one or more channels missing, the value 2849 //! from the border color is not used for the missing channels, resulting in 2850 //! these channels resulting in the overall default value (0 for colors and 2851 //! 1 for alpha) regardless of whether border color is chosen. The surface 2852 //! formats with "L" and "I" have special behavior with respect to the 2853 //! border color. The border color value used for the replicated channels 2854 //! (RGB for "L" formats and RGBA for "I" formats) comes from the red 2855 //! channel of border color. In these cases, the green and blue channels, 2856 //! and also alpha for "I", of the border color are ignored. 2857 //! 2858 //! 2859 //! 2860 //! 2861 //! 2862 //! The format of this state depends on the Texture Border Color Mode field. 2863 //! 2864 //! 8 bit mode is not supported for surfaces with more than 16 bits in any 2865 //! channel, other than 32-bit float formats which are supported. 2866 //! The conditions under which this color is used depend on the Surface 2867 //! Type - 1D/2D/3D surfaces use the border color when the coordinates 2868 //! extend beyond the surface extent; cube surfaces use the border color for 2869 //! "empty" (disabled) faces. 2870 //! The border color itself is accessed through the texture cache hierarchy 2871 //! rather than the state cache hierarchy. Thus, if the border color is 2872 //! changed in memory, the texture cache must be invalidated and the state 2873 //! cache does not need to be invalidated. 2874 //! MAPFILTER_MONO: The border color is ignored. Border color is fixed at 2875 //! a value of 0 by hardware. 2876 //! 2877 //! 2878 struct SAMPLER_INDIRECT_STATE_CMD 2879 { 2880 union 2881 { 2882 //!< DWORD 0 2883 struct 2884 { 2885 uint32_t BorderColorRed ; //!< Border Color Red, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2886 } Obj0; 2887 struct 2888 { 2889 uint32_t BorderColorRed : __CODEGEN_BITFIELD( 0, 7) ; //!< Border Color Red, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2890 uint32_t BorderColorGreen : __CODEGEN_BITFIELD( 8, 15) ; //!< Border Color Green, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2891 uint32_t BorderColorBlue : __CODEGEN_BITFIELD(16, 23) ; //!< Border Color Blue, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2892 uint32_t BorderColorAlpha : __CODEGEN_BITFIELD(24, 31) ; //!< Border Color Alpha, Structure[SAMPLER_STATE][Texture Border Color Mode] == '8BIT' 2893 } Obj1; 2894 uint32_t Value; 2895 } DW0; 2896 union 2897 { 2898 //!< DWORD 1 2899 struct 2900 { 2901 uint32_t BorderColorGreen ; //!< Border Color Green, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2902 }; 2903 uint32_t Value; 2904 } DW1; 2905 union 2906 { 2907 //!< DWORD 2 2908 struct 2909 { 2910 uint32_t BorderColorBlue ; //!< Border Color Blue, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2911 }; 2912 uint32_t Value; 2913 } DW2; 2914 union 2915 { 2916 //!< DWORD 3 2917 struct 2918 { 2919 uint32_t BorderColorAlpha ; //!< Border Color Alpha, Structure[SAMPLER_STATE][Texture Border Color Mode] == 'OGL' 2920 }; 2921 uint32_t Value; 2922 } DW3; 2923 2924 uint32_t Reserved128[12]; //!< Reserved 2925 2926 2927 //! \name Local enumerations 2928 2929 //! \name Initializations 2930 2931 //! \brief Explicit member initialization function 2932 SAMPLER_INDIRECT_STATE_CMD(); 2933 2934 static const size_t dwSize = 16; 2935 static const size_t byteSize = 64; 2936 }; 2937 2938 }; 2939 2940 #pragma pack() 2941 2942 #endif // __MHW_STATE_HEAP_HWCMD_G11_X_H__ 2943