1 /*
2 * Copyright (c) 2015-2019, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_state_heap_g12.c
24 //! \brief This modules implements HW interface layer to be used on all platforms on
25 //! all operating systems/DDIs, across MHW components.
26 //!
27 #include "mhw_state_heap_g12.h"
28 #include "mhw_cp_interface.h"
29 #include "mhw_render_hwcmd_g12_X.h"
30
MHW_STATE_HEAP_INTERFACE_G12_X(PMOS_INTERFACE pInputOSInterface,int8_t bDynamicMode)31 MHW_STATE_HEAP_INTERFACE_G12_X::MHW_STATE_HEAP_INTERFACE_G12_X(
32 PMOS_INTERFACE pInputOSInterface, int8_t bDynamicMode):
33 MHW_STATE_HEAP_INTERFACE_GENERIC(pInputOSInterface, bDynamicMode)
34 {
35 m_wBtIdxAlignment = m_mhwNumBindingTableEntryOffset;
36 m_wIdAlignment = (1 << m_mhwGenericOffsetShift);
37 m_wCurbeAlignment = (1 << m_mhwGenericOffsetShift);
38
39 m_dwSizeSurfaceState = MOS_ALIGN_CEIL(mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::byteSize, MHW_SURFACE_STATE_ALIGN);
40 m_dwSizeSurfaceStateAdv = MOS_ALIGN_CEIL(mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD::byteSize, MHW_SURFACE_STATE_ALIGN);
41 m_dwMaxSurfaceStateSize = MOS_MAX(m_dwSizeSurfaceState, m_dwSizeSurfaceStateAdv);
42 m_wSizeOfInterfaceDescriptor = mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD::byteSize;
43 m_wSizeOfCmdInterfaceDescriptorData = MOS_ALIGN_CEIL(m_wSizeOfInterfaceDescriptor, m_wIdAlignment);
44 m_wSizeOfCmdSamplerState = mhw_state_heap_g12_X::SAMPLER_STATE_CMD::byteSize;
45
46 InitHwSizes();
47 }
48
~MHW_STATE_HEAP_INTERFACE_G12_X()49 MHW_STATE_HEAP_INTERFACE_G12_X::~MHW_STATE_HEAP_INTERFACE_G12_X()
50 {
51 MHW_FUNCTION_ENTER;
52 }
53
InitHwSizes()54 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::InitHwSizes()
55 {
56 m_HwSizes.dwSizeMediaObjectHeaderCmd = mhw_render_g12_X::MEDIA_OBJECT_CMD::byteSize;
57 m_HwSizes.dwSizeSurfaceState = MOS_ALIGN_CEIL(mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::byteSize, MHW_SURFACE_STATE_ALIGN);
58 m_HwSizes.dwSizeSurfaceStateAvs = MOS_ALIGN_CEIL(mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD::byteSize, MHW_SURFACE_STATE_ALIGN);
59 m_HwSizes.dwMaxSizeSurfaceState = MOS_MAX(m_HwSizes.dwSizeSurfaceState, m_HwSizes.dwSizeSurfaceStateAvs);
60 m_HwSizes.dwSizeBindingTableState = mhw_state_heap_g12_X::BINDING_TABLE_STATE_CMD::byteSize;
61 m_HwSizes.dwSizeSamplerState = mhw_state_heap_g12_X::SAMPLER_STATE_CMD::byteSize;
62 m_HwSizes.dwSizeSamplerIndirectState = mhw_state_heap_g12_X::SAMPLER_INDIRECT_STATE_CMD::byteSize;
63 m_HwSizes.dwSizeSamplerStateVA = 0;
64 m_HwSizes.dwSizeSamplerStateVAConvolve = 0;
65 m_HwSizes.dwSizeSamplerStateTable8x8 = mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_CMD::byteSize - 16 * sizeof(uint32_t); // match old definitions to table size
66 m_HwSizes.dwSizeSampler8x8Table =
67 MOS_ALIGN_CEIL(m_HwSizes.dwSizeSamplerStateTable8x8, MHW_SAMPLER_STATE_ALIGN);
68 m_HwSizes.dwSizeSamplerStateAvs =
69 MOS_ALIGN_CEIL(mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_CMD::byteSize, MHW_SAMPLER_STATE_AVS_ALIGN_MEDIA);
70 m_HwSizes.dwSizeInterfaceDescriptor = mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD::byteSize;
71 m_HwSizes.dwSizeMediaWalkerBlock = 16;
72
73 return MOS_STATUS_SUCCESS;
74 }
75
SetInterfaceDescriptorEntry(PMHW_ID_ENTRY_PARAMS pParams)76 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::SetInterfaceDescriptorEntry(
77 PMHW_ID_ENTRY_PARAMS pParams)
78 {
79 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
80
81 MHW_FUNCTION_ENTER;
82
83 //------------------------------------
84 MHW_MI_CHK_NULL(pParams);
85 //------------------------------------
86
87 // Ensures that the Media ID base is correct
88 MHW_ASSERT(MOS_IS_ALIGNED(pParams->dwMediaIdOffset, m_wIdAlignment));
89
90 uint8_t *pStateHeapBase;
91 if (pParams->pGeneralStateHeap)
92 {
93 pStateHeapBase = (uint8_t*)pParams->pGeneralStateHeap->pvLockedHeap;
94 }
95 else
96 {
97 pStateHeapBase = (uint8_t*)(GetDSHPointer()->pvLockedHeap);
98 }
99
100 mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD *pInterfaceDescriptor;
101 pInterfaceDescriptor = (mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD *)
102 (pStateHeapBase + // State Heap Base
103 pParams->dwMediaIdOffset + // Offset to first Media ID
104 pParams->iMediaId * m_wSizeOfInterfaceDescriptor); // Offset to current ID
105 *pInterfaceDescriptor = mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD();
106
107 pInterfaceDescriptor->DW0.KernelStartPointer = pParams->dwKernelOffset >> MHW_KERNEL_OFFSET_SHIFT;
108 pInterfaceDescriptor->DW3.SamplerStatePointer = pParams->dwSamplerOffset >> MHW_SAMPLER_SHIFT;
109 pInterfaceDescriptor->DW3.SamplerCount = pParams->dwSamplerCount;
110 pInterfaceDescriptor->DW4.BindingTablePointer = MOS_ROUNDUP_SHIFT(pParams->dwBindingTableOffset, MHW_BINDING_TABLE_ID_SHIFT);
111 pInterfaceDescriptor->DW5.ConstantUrbEntryReadOffset = pParams->iCurbeOffset >> MHW_CURBE_SHIFT;
112 pInterfaceDescriptor->DW5.ConstantIndirectUrbEntryReadLength = MOS_ROUNDUP_SHIFT(pParams->iCurbeLength, MHW_CURBE_SHIFT);
113 pInterfaceDescriptor->DW6.BarrierEnable = pParams->bBarrierEnable;
114 pInterfaceDescriptor->DW6.NumberOfThreadsInGpgpuThreadGroup = pParams->dwNumberofThreadsInGPGPUGroup;
115 pInterfaceDescriptor->DW6.SharedLocalMemorySize = pParams->dwSharedLocalMemorySize;
116 pInterfaceDescriptor->DW7.CrossThreadConstantDataReadLength = pParams->iCrsThdConDataRdLn >> MHW_THRD_CON_DATA_RD_SHIFT;
117
118 return eStatus;
119 }
120
AddInterfaceDescriptorData(PMHW_ID_ENTRY_PARAMS pParams)121 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::AddInterfaceDescriptorData(
122 PMHW_ID_ENTRY_PARAMS pParams)
123 {
124 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
125
126 MHW_FUNCTION_ENTER;
127
128 //------------------------------------
129 MHW_MI_CHK_NULL(pParams);
130 //------------------------------------
131
132 // Ensures that the Media ID base is correct
133 MHW_ASSERT(MOS_IS_ALIGNED(pParams->dwMediaIdOffset, m_wIdAlignment));
134
135 uint32_t offset = pParams->dwMediaIdOffset + pParams->iMediaId * m_wSizeOfInterfaceDescriptor;
136 mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD *pInterfaceDescriptor;
137 pInterfaceDescriptor = (mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD *)MOS_AllocMemory(sizeof(mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD));
138 MHW_MI_CHK_NULL(pInterfaceDescriptor);
139 *pInterfaceDescriptor = mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD();
140
141 pInterfaceDescriptor->DW0.KernelStartPointer = pParams->dwKernelOffset >> MHW_KERNEL_OFFSET_SHIFT;
142 pInterfaceDescriptor->DW3.SamplerStatePointer = pParams->dwSamplerOffset >> MHW_SAMPLER_SHIFT;
143 pInterfaceDescriptor->DW3.SamplerCount = pParams->dwSamplerCount;
144 pInterfaceDescriptor->DW4.BindingTablePointer = MOS_ROUNDUP_SHIFT(pParams->dwBindingTableOffset, MHW_BINDING_TABLE_ID_SHIFT);
145 pInterfaceDescriptor->DW5.ConstantUrbEntryReadOffset = pParams->iCurbeOffset >> MHW_CURBE_SHIFT;
146 pInterfaceDescriptor->DW5.ConstantIndirectUrbEntryReadLength = MOS_ROUNDUP_SHIFT(pParams->iCurbeLength, MHW_CURBE_SHIFT);
147 pInterfaceDescriptor->DW6.BarrierEnable = pParams->bBarrierEnable;
148 pInterfaceDescriptor->DW6.NumberOfThreadsInGpgpuThreadGroup = pParams->dwNumberofThreadsInGPGPUGroup;
149 pInterfaceDescriptor->DW6.SharedLocalMemorySize = pParams->dwSharedLocalMemorySize;
150 pInterfaceDescriptor->DW7.CrossThreadConstantDataReadLength = pParams->iCrsThdConDataRdLn >> MHW_THRD_CON_DATA_RD_SHIFT;
151
152 // need to subtract memory block's offset in current state heap for AddData API
153 offset -= pParams->memoryBlock->GetOffset();
154 eStatus = pParams->memoryBlock->AddData(pInterfaceDescriptor, offset,
155 sizeof(mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD));
156
157 MOS_SafeFreeMemory(pInterfaceDescriptor);
158 MHW_MI_CHK_STATUS(eStatus);
159 return eStatus;
160 }
SetSurfaceStateEntry(PMHW_SURFACE_STATE_PARAMS pParams)161 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::SetSurfaceStateEntry(
162 PMHW_SURFACE_STATE_PARAMS pParams)
163 {
164
165 if (!pParams)
166 {
167 MHW_ASSERTMESSAGE("Invalid parameter\n");
168 return MOS_STATUS_INVALID_PARAMETER;
169 }
170
171 uint32_t TileMode = (pParams->bTiledSurface) ? ((pParams->bTileWalk == 0) ? 2 /*x-tile*/: 3 /*y-tile*/) : 0; /*linear*/
172
173 // for Gen11 Adv surface state
174 if (pParams->bUseAdvState)
175 {
176 // Obtain the Pointer to the Surface state from SSH Buffer
177 mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD* pSurfaceStateAdv =
178 (mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD*) pParams->pSurfaceState;
179 MHW_MI_CHK_NULL(pSurfaceStateAdv);
180 // Initialize Surface State
181 *pSurfaceStateAdv = mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD();
182
183 pSurfaceStateAdv->DW0.Rotation = pParams->RotationMode;
184 pSurfaceStateAdv->DW0.XOffset = pParams->iXOffset >> 2;
185 pSurfaceStateAdv->DW0.YOffset = pParams->iYOffset >> 2;
186 pSurfaceStateAdv->DW1.Width = pParams->dwWidth - 1;
187 pSurfaceStateAdv->DW1.Height = pParams->dwHeight - 1;
188 pSurfaceStateAdv->DW1.CrVCbUPixelOffsetVDirection = pParams->UVPixelOffsetVDirection & 3;
189 pSurfaceStateAdv->DW2.CrVCbUPixelOffsetVDirectionMsb = pParams->UVPixelOffsetVDirection >> 2;
190 pSurfaceStateAdv->DW2.CrVCbUPixelOffsetUDirection = pParams->UVPixelOffsetUDirection;
191 pSurfaceStateAdv->DW2.SurfaceFormat = pParams->dwFormat;
192 pSurfaceStateAdv->DW2.InterleaveChroma = pParams->bInterleaveChroma;
193 pSurfaceStateAdv->DW2.SurfacePitch = pParams->dwPitch - 1;
194 pSurfaceStateAdv->DW2.HalfPitchForChroma = pParams->bHalfPitchChroma;
195 pSurfaceStateAdv->DW2.TileMode = TileMode;
196 pSurfaceStateAdv->DW2.MemoryCompressionEnable =
197 (pParams->MmcState == MOS_MEMCOMP_RC || pParams->MmcState == MOS_MEMCOMP_MC) ? 1 : 0;
198 pSurfaceStateAdv->DW2.MemoryCompressionType =
199 (pParams->MmcState == MOS_MEMCOMP_RC) ? 1 : 0;
200 pSurfaceStateAdv->DW3.XOffsetForUCb = pParams->dwXOffsetForU;
201 pSurfaceStateAdv->DW3.YOffsetForUCb = pParams->dwYOffsetForU;
202 pSurfaceStateAdv->DW4.XOffsetForVCr = pParams->dwXOffsetForV;
203 pSurfaceStateAdv->DW4.YOffsetForVCr = pParams->dwYOffsetForV;
204 pSurfaceStateAdv->DW5.VerticalLineStride = pParams->bVerticalLineStride;
205 pSurfaceStateAdv->DW5.VerticalLineStrideOffset = pParams->bVerticalLineStrideOffset;
206 pSurfaceStateAdv->DW5.SurfaceMemoryObjectControlState = pParams->dwCacheabilityControl;
207
208 // Return offset and pointer for patching
209 pParams->pdwCmd = (uint32_t *)&(pSurfaceStateAdv->DW6.Value);
210 pParams->dwLocationInCmd = 6;
211 }
212 else // not AVS
213 {
214 // Obtain the Pointer to the Surface state from SSH Buffer
215 mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD* pSurfaceState =
216 (mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD*) pParams->pSurfaceState;
217 MHW_MI_CHK_NULL(pSurfaceState);
218
219 // Initialize Surface State
220 *pSurfaceState = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD();
221
222 pSurfaceState->DW0.SurfaceType = pParams->SurfaceType3D;
223 pSurfaceState->DW0.SurfaceFormat = pParams->dwFormat;
224 pSurfaceState->DW0.TileMode = TileMode;
225 pSurfaceState->DW0.VerticalLineStride = pParams->bVerticalLineStride;
226 pSurfaceState->DW0.VerticalLineStrideOffset = pParams->bVerticalLineStrideOffset;
227 pSurfaceState->DW0.SurfaceHorizontalAlignment = 1;
228 pSurfaceState->DW0.SurfaceVerticalAlignment = 1;
229
230 pSurfaceState->DW1.MemoryObjectControlState = pParams->dwCacheabilityControl;
231 if (GFX3DSTATE_SURFACETYPE_BUFFER == pParams->SurfaceType3D
232 || GFX3DSTATE_SURFACETYPE_SCRATCH == pParams->SurfaceType3D)
233 { // Buffer resources - use original width/height/pitch/depth
234 pSurfaceState->DW2.Width = pParams->dwWidth;
235 pSurfaceState->DW2.Height = pParams->dwHeight;
236 pSurfaceState->DW3.SurfacePitch = pParams->dwPitch;
237 pSurfaceState->DW3.Depth = pParams->dwDepth;
238 }
239 else
240 {
241 pSurfaceState->DW1.SurfaceQpitch = pParams->dwQPitch >> 2;
242 pSurfaceState->DW2.Width = pParams->dwWidth - 1;
243 pSurfaceState->DW2.Height = pParams->dwHeight - 1;
244 pSurfaceState->DW3.SurfacePitch = pParams->dwPitch - 1;
245 pSurfaceState->DW3.Depth = pParams->dwDepth - 1;
246 }
247 pSurfaceState->DW4.RenderTargetAndSampleUnormRotation = pParams->RotationMode;
248 pSurfaceState->DW5.XOffset = pParams->iXOffset >> 2;
249 pSurfaceState->DW5.YOffset = pParams->iYOffset >> 2;
250 pSurfaceState->DW6.Obj2.SeparateUvPlaneEnable = pParams->bSeperateUVPlane;
251 pSurfaceState->DW6.Obj2.HalfPitchForChroma = pParams->bHalfPitchChroma;
252 pSurfaceState->DW6.Obj2.XOffsetForUOrUvPlane = pParams->dwXOffsetForU;
253 pSurfaceState->DW6.Obj2.YOffsetForUOrUvPlane = pParams->dwYOffsetForU;
254
255 // R8B8G8A8 is designed to represent media AYUV format.
256 // But from Gen10+ 3D sampler doesn't support R8B8G8A8 format any more.
257 // Use R8G8B8A8 + Channel Select to fake it.
258 if (pParams->dwFormat == MHW_GFX3DSTATE_SURFACEFORMAT_R8B8G8A8_UNORM)
259 {
260 pSurfaceState->DW0.SurfaceFormat = MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_UNORM;
261 pSurfaceState->DW7.ShaderChannelSelectAlpha = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_ALPHA_ALPHA;
262 pSurfaceState->DW7.ShaderChannelSelectBlue = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_GREEN_GREEN;
263 pSurfaceState->DW7.ShaderChannelSelectGreen = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_BLUE_BLUE;
264 pSurfaceState->DW7.ShaderChannelSelectRed = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_RED_RED;
265 }
266 else
267 {
268 pSurfaceState->DW7.ShaderChannelSelectAlpha = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_ALPHA_ALPHA;
269 pSurfaceState->DW7.ShaderChannelSelectBlue = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_BLUE_BLUE;
270 pSurfaceState->DW7.ShaderChannelSelectGreen = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_GREEN_GREEN;
271 pSurfaceState->DW7.ShaderChannelSelectRed = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_RED_RED;
272 }
273
274 if (pParams->MmcState == MOS_MEMCOMP_MC)
275 {
276 // Media Compresseion Enable on Current surface
277 pSurfaceState->DW7.MemoryCompressionEnable = 1;
278 pSurfaceState->DW7.MemoryCompressionMode = 0;
279 pSurfaceState->DW4.DecompressInL3 = 1;
280 }
281 else if(pParams->MmcState == MOS_MEMCOMP_RC)
282 {
283 // Render Compression Enable on Current Surface
284 pSurfaceState->DW6.Obj0.AuxiliarySurfaceMode = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::AUXILIARY_SURFACE_MODE_AUXCCSE;
285 pSurfaceState->DW7.MemoryCompressionEnable = 0;
286 pSurfaceState->DW7.MemoryCompressionMode = 0;
287 pSurfaceState->DW4.DecompressInL3 = 1;
288 }
289
290 pSurfaceState->DW8_9.SurfaceBaseAddress = 0;
291 pSurfaceState->DW10_11.Obj1.XOffsetForVPlane = pParams->dwXOffsetForV;
292 pSurfaceState->DW10_11.Obj0.YOffsetForVPlane = pParams->dwYOffsetForV;
293
294 // Return offset and pointer for patching
295 pParams->pdwCmd = (uint32_t *)&(pSurfaceState->DW8_9.SurfaceBaseAddress);
296 pParams->dwLocationInCmd = 8;
297 }
298
299 return MOS_STATUS_SUCCESS;
300 }
301
SetSurfaceState(PMHW_KERNEL_STATE pKernelState,PMOS_COMMAND_BUFFER pCmdBuffer,uint32_t dwNumSurfaceStatesToSet,PMHW_RCS_SURFACE_PARAMS pParams)302 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::SetSurfaceState(
303 PMHW_KERNEL_STATE pKernelState,
304 PMOS_COMMAND_BUFFER pCmdBuffer,
305 uint32_t dwNumSurfaceStatesToSet,
306 PMHW_RCS_SURFACE_PARAMS pParams)
307 {
308 PMOS_INTERFACE pOsInterface;
309 uint8_t *pIndirectState = nullptr;
310 MHW_RESOURCE_PARAMS ResourceParams;
311 uint32_t uiIndirectStateOffset = 0, uiIndirectStateSize = 0;
312 PMHW_STATE_HEAP pStateHeap;
313 uint32_t dwSurfaceType = GFX3DSTATE_SURFACETYPE_NULL; // GFX3DSTATE_SURFACETYPE
314 uint32_t i; // Plane Index
315 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
316
317 MHW_FUNCTION_ENTER;
318
319 MHW_MI_CHK_NULL(pParams);
320 MHW_MI_CHK_NULL(pParams->psSurface);
321 MOS_UNUSED(dwNumSurfaceStatesToSet);
322
323 if (pParams->dwNumPlanes >= MHW_MAX_SURFACE_PLANES)
324 {
325 MHW_ASSERTMESSAGE("Invalid plane number provided");
326 eStatus = MOS_STATUS_INVALID_PARAMETER;
327 return eStatus;
328 }
329
330 pOsInterface = m_pOsInterface;
331 pStateHeap = &m_SurfaceStateHeap;
332
333 MHW_MI_CHK_NULL(pOsInterface);
334 MHW_MI_CHK_STATUS(pOsInterface->pfnGetIndirectStatePointer(pOsInterface, &pIndirectState));
335 MHW_MI_CHK_STATUS(pOsInterface->pfnGetIndirectState(pOsInterface, &uiIndirectStateOffset, &uiIndirectStateSize));
336
337 MOS_ZeroMemory(&ResourceParams, sizeof(ResourceParams));
338 ResourceParams.dwLsbNum = 0; // MHW_STATE_HEAP_SURFACE_STATE_SHIFT
339
340 for ( i = 0; i < pParams->dwNumPlanes; i++)
341 {
342 MHW_ASSERT_INVALID_BINDING_TABLE_IDX(pParams->dwBindingTableOffset[i]);
343 MHW_MI_CHK_NULL(pKernelState);
344 uint32_t u32SurfaceOffsetInSsh =
345 pKernelState->dwSshOffset + pKernelState->dwBindingTableSize + // offset within SSH to start of surfaces for this kernel
346 (m_HwSizes.dwMaxSizeSurfaceState * pParams->dwBindingTableOffset[i]); // offset to the current surface
347 if (u32SurfaceOffsetInSsh + m_HwSizes.dwMaxSizeSurfaceState > uiIndirectStateOffset)
348 {
349 MHW_ASSERTMESSAGE("Location requested for surface state is outside the bounds of SSH");
350 return MOS_STATUS_INVALID_PARAMETER;
351 }
352 uint8_t *pLocationOfSurfaceInSsh = (uint8_t*)
353 (pIndirectState + u32SurfaceOffsetInSsh);
354
355 if (pParams->bUseAdvState)
356 {
357 mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD *pCmd =
358 (mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD*)pLocationOfSurfaceInSsh;
359 MHW_MI_CHK_NULL(pCmd);
360 mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD CmdInit;
361
362 CmdInit.DW1.Width = (pParams->dwWidthToUse[i] == 0) ?
363 pParams->psSurface->dwWidth - 1 : pParams->dwWidthToUse[i] - 1;
364 CmdInit.DW1.Height = (pParams->dwHeightToUse[i] == 0) ?
365 pParams->psSurface->dwHeight - 1: pParams->dwHeightToUse[i] - 1;
366 CmdInit.DW1.CrVCbUPixelOffsetVDirection = pParams->Direction;
367
368 CmdInit.DW2.SurfacePitch = pParams->psSurface->dwPitch - 1;
369 CmdInit.DW2.SurfaceFormat = pParams->ForceSurfaceFormat[i];
370 CmdInit.DW2.InterleaveChroma = pParams->bInterleaveChroma;
371
372 if (IS_Y_MAJOR_TILE_FORMAT(pParams->psSurface->TileType))
373 {
374 CmdInit.DW2.TileMode = mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD::TILE_MODE_TILEMODEYMAJOR;
375 }
376 else if (pParams->psSurface->TileType == MOS_TILE_LINEAR)
377 {
378 CmdInit.DW2.TileMode = mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD::TILE_MODE_TILEMODELINEAR;
379 }
380 else if (pParams->psSurface->TileType == MOS_TILE_X)
381 {
382 CmdInit.DW2.TileMode = mhw_state_heap_g12_X::MEDIA_SURFACE_STATE_CMD::TILE_MODE_TILEMODEXMAJOR;
383 }
384
385 CmdInit.DW2.MemoryCompressionEnable =
386 (pParams->psSurface->MmcState == MOS_MEMCOMP_RC || pParams->psSurface->MmcState == MOS_MEMCOMP_MC) ? 1 : 0;
387 CmdInit.DW2.MemoryCompressionType =
388 (pParams->psSurface->MmcState == MOS_MEMCOMP_RC) ? 1 : 0;
389
390 CmdInit.DW5.SurfaceMemoryObjectControlState = pParams->dwCacheabilityControl;
391
392 CmdInit.DW5.TiledResourceMode = Mhw_ConvertToTRMode(pParams->psSurface->TileType);
393
394 if (i == MHW_U_PLANE) // AVS U plane
395 {
396 // Lockoffset is the offset from base address of Y plane to the origin of U/V plane.
397 // So, We can get XOffsetforU by Lockoffset % pSurface->dwPitch, and get YOffsetForU by Lockoffset / pSurface->dwPitch
398 /*pCmd->DW0.XOffset = pParams->psSurface->UPlaneOffset.iXOffset >> 2;
399 pCmd->DW0.YOffset = pParams->psSurface->UPlaneOffset.iYOffset >> 2;
400
401 pCmd->DW3.XOffsetforU = ((uint32_t)pParams->psSurface->UPlaneOffset.iLockSurfaceOffset % pSurface->dwPitch);
402 pCmd->DW3.YOffsetforU = ((uint32_t)pParams->psSurface->UPlaneOffset.iLockSurfaceOffset / pSurface->dwPitch);*/
403
404 // Currently CodecHal/VPHAL are not using the same PlaneOffsets, need to modify CodecHal to match VPHAL
405 CmdInit.DW3.YOffsetForUCb = pParams->psSurface->UPlaneOffset.iYOffset;
406 }
407 else if (i == MHW_V_PLANE) // AVS V plane
408 {
409 CmdInit.DW0.XOffset = pParams->psSurface->VPlaneOffset.iXOffset >> 2;
410 CmdInit.DW0.YOffset = pParams->psSurface->VPlaneOffset.iYOffset >> 2;
411
412 //pCmd->DW4.XOffsetforV = ((uint32_t)pParams->psSurface->UPlaneOffset.iLockSurfaceOffset % pSurface->dwPitch);
413 //pCmd->DW4.YOffsetforV = ((uint32_t)pParams->psSurface->VPlaneOffset.iLockSurfaceOffset / pSurface->dwPitch);
414 }
415 else // AVS/DNDI Y plane
416 {
417 CmdInit.DW3.XOffsetForUCb = pParams->dwXOffset[MHW_U_PLANE];
418 CmdInit.DW3.YOffsetForUCb = pParams->dwYOffset[MHW_U_PLANE];
419 CmdInit.DW4.XOffsetForVCr = pParams->dwXOffset[MHW_V_PLANE];
420 CmdInit.DW4.YOffsetForVCr = pParams->dwYOffset[MHW_V_PLANE];
421 }
422
423 // temporary code for Codec, need to remove in the future
424 CmdInit.DW3.YOffsetForUCb = pParams->psSurface->UPlaneOffset.iYOffset;
425 *pCmd = CmdInit;
426
427 ResourceParams.presResource = &pParams->psSurface->OsResource;
428 ResourceParams.dwOffset =
429 pParams->psSurface->dwOffset + pParams->dwBaseAddrOffset[i];
430 ResourceParams.pdwCmd = &(pCmd->DW6.Value);
431 ResourceParams.dwLocationInCmd = 6;
432 ResourceParams.bIsWritable = pParams->bIsWritable;
433 ResourceParams.dwOffsetInSSH =
434 uiIndirectStateOffset +
435 pKernelState->dwSshOffset +
436 pKernelState->dwBindingTableSize +
437 (pParams->dwBindingTableOffset[i] * m_dwMaxSurfaceStateSize);
438 ResourceParams.HwCommandType = MOS_SURFACE_STATE_ADV;
439
440 MHW_MI_CHK_STATUS(m_pfnAddResourceToCmd(
441 pOsInterface,
442 pCmdBuffer,
443 &ResourceParams));
444 }
445 else // 1D, 2D Surface
446 {
447 mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD *pCmd =
448 (mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD*)pLocationOfSurfaceInSsh;
449
450 mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD CmdInit;
451 CmdInit = *pCmd;
452 // Add additional defaults specific to media
453 CmdInit.DW0.SurfaceHorizontalAlignment = 1;
454 CmdInit.DW0.SurfaceVerticalAlignment = 1;
455 CmdInit.DW1.EnableUnormPathInColorPipe = CmdInit.ENABLE_UNORM_PATH_IN_COLOR_PIPE_DISABLE;
456 CmdInit.DW7.ShaderChannelSelectAlpha = CmdInit.SHADER_CHANNEL_SELECT_ALPHA_ALPHA;
457 CmdInit.DW7.ShaderChannelSelectBlue = CmdInit.SHADER_CHANNEL_SELECT_BLUE_BLUE;
458 CmdInit.DW7.ShaderChannelSelectGreen = CmdInit.SHADER_CHANNEL_SELECT_GREEN_GREEN;
459 CmdInit.DW7.ShaderChannelSelectRed = CmdInit.SHADER_CHANNEL_SELECT_RED_RED;
460
461 MHW_MI_CHK_STATUS(Mhw_SurfaceFormatToType(
462 pParams->ForceSurfaceFormat[i],
463 pParams->psSurface,
464 &dwSurfaceType));
465
466 // Force surface type to be 2D for this case since its a requirement for the Gen11 HEVC Kernel
467 if (i == MHW_Y_PLANE && pParams->ForceSurfaceFormat[i] == MHW_GFX3DSTATE_SURFACEFORMAT_R32_UINT && pParams->dwSurfaceType == GFX3DSTATE_SURFACETYPE_2D)
468 dwSurfaceType = GFX3DSTATE_SURFACETYPE_2D;
469 CmdInit.DW0.SurfaceType = dwSurfaceType;
470 CmdInit.DW0.VerticalLineStride = pParams->bVertLineStride;
471 CmdInit.DW0.VerticalLineStrideOffset = pParams->bVertLineStrideOffs;
472 CmdInit.DW0.MediaBoundaryPixelMode = pParams->MediaBoundaryPixelMode;
473 CmdInit.DW0.SurfaceFormat = pParams->ForceSurfaceFormat[i];
474
475 if (IS_Y_MAJOR_TILE_FORMAT(pParams->psSurface->TileType))
476 {
477 CmdInit.DW0.TileMode = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::TILE_MODE_YMAJOR;
478 }
479 else if (pParams->psSurface->TileType == MOS_TILE_LINEAR)
480 {
481 CmdInit.DW0.TileMode = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::TILE_MODE_LINEAR;
482 }
483 else if (pParams->psSurface->TileType == MOS_TILE_X)
484 {
485 CmdInit.DW0.TileMode = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::TILE_MODE_XMAJOR;
486 }
487
488 CmdInit.DW1.MemoryObjectControlState = pParams->dwCacheabilityControl;
489
490 CmdInit.DW2.Width = (pParams->dwWidthToUse[i] == 0) ?
491 pParams->psSurface->dwWidth : pParams->dwWidthToUse[i];
492 CmdInit.DW2.Height = (pParams->dwHeightToUse[i] == 0) ?
493 pParams->psSurface->dwHeight : pParams->dwHeightToUse[i];
494 CmdInit.DW3.SurfacePitch = (pParams->dwPitchToUse[i] == 0) ?
495 pParams->psSurface->dwPitch : pParams->dwPitchToUse[i];
496 if (pParams->psSurface->MmcState == MOS_MEMCOMP_MC)
497 {
498 CmdInit.DW7.MemoryCompressionEnable = 1;
499 CmdInit.DW7.MemoryCompressionMode = 0;
500 CmdInit.DW4.DecompressInL3 = 1;
501 }
502 else if(pParams->psSurface->MmcState == MOS_MEMCOMP_RC)
503 {
504 CmdInit.DW4.DecompressInL3 = 1;
505 CmdInit.DW7.MemoryCompressionEnable = 0;
506 CmdInit.DW7.MemoryCompressionMode = 0;
507 // Render Compression Enable on Current Surface
508 CmdInit.DW6.Obj0.AuxiliarySurfaceMode = mhw_state_heap_g12_X::RENDER_SURFACE_STATE_CMD::AUXILIARY_SURFACE_MODE_AUXCCSE;
509 # if !EMUL
510 *pCmd = CmdInit;
511 MOS_ZeroMemory(&ResourceParams, sizeof(ResourceParams));
512 ResourceParams.presResource = &pParams->psSurface->OsResource;
513 ResourceParams.dwOffset = pParams->psSurface->dwOffset + pParams->dwBaseAddrOffset[i]
514 + (uint32_t)pParams->psSurface->OsResource.pGmmResInfo->GetUnifiedAuxSurfaceOffset(GMM_AUX_CCS);
515 ResourceParams.pdwCmd = (pCmd->DW10_11.Value);
516 ResourceParams.dwLocationInCmd = 10;
517 ResourceParams.bIsWritable = pParams->bIsWritable;
518
519 ResourceParams.HwCommandType = MOS_SURFACE_STATE;
520
521 MHW_MI_CHK_STATUS(m_pfnAddResourceToCmd(
522 pOsInterface,
523 pCmdBuffer,
524 &ResourceParams));
525
526 MOS_ZeroMemory(&ResourceParams, sizeof(ResourceParams));
527 ResourceParams.presResource = &pParams->psSurface->OsResource;
528 ResourceParams.dwOffset = pParams->psSurface->dwOffset + pParams->dwBaseAddrOffset[i]
529 + (uint32_t)pParams->psSurface->OsResource.pGmmResInfo->GetUnifiedAuxSurfaceOffset(GMM_AUX_CC);
530 ResourceParams.pdwCmd = &(pCmd->DW12.Value);
531 ResourceParams.dwLocationInCmd = 12;
532 ResourceParams.bIsWritable = pParams->bIsWritable;
533
534 ResourceParams.HwCommandType = MOS_SURFACE_STATE;
535
536 MHW_MI_CHK_STATUS(m_pfnAddResourceToCmd(
537 pOsInterface,
538 pCmdBuffer,
539 &ResourceParams));
540 CmdInit = *pCmd;
541 # endif
542 }
543 else
544 {
545 CmdInit.DW7.MemoryCompressionEnable = 0;
546 CmdInit.DW7.MemoryCompressionMode = 0;
547 CmdInit.DW4.DecompressInL3 = 0;
548 }
549
550 CmdInit.DW3.SurfacePitch--; // both for 1D & 2D surface
551 // need to sync up with VP & CM for depth setup
552 CmdInit.DW3.Depth = pParams->psSurface->dwDepth;
553
554 if (dwSurfaceType == GFX3DSTATE_SURFACETYPE_BUFFER)
555 {
556 if (CmdInit.DW0.TileMode)
557 {
558 MHW_ASSERTMESSAGE("1D surfaces should not be tiled!");
559 eStatus = MOS_STATUS_INVALID_PARAMETER;
560 return eStatus;
561 }
562 }
563 else // 2D Surface
564 {
565 CmdInit.DW2.Width--;
566 CmdInit.DW2.Height--;
567 CmdInit.DW3.Depth--;
568 CmdInit.DW5.XOffset = pParams->dwXOffset[i] >> 2;
569 CmdInit.DW5.YOffset = pParams->dwYOffset[i] >> 2;
570 CmdInit.DW5.TiledResourceMode = Mhw_ConvertToTRMode(pParams->psSurface->TileType);
571 }
572 *pCmd = CmdInit;
573
574 MOS_ZeroMemory(&ResourceParams, sizeof(ResourceParams));
575 ResourceParams.presResource = &pParams->psSurface->OsResource;
576 ResourceParams.dwOffset =
577 pParams->psSurface->dwOffset + pParams->dwBaseAddrOffset[i];
578 ResourceParams.pdwCmd = (pCmd->DW8_9.Value);
579 ResourceParams.dwLocationInCmd = 8;
580 ResourceParams.bIsWritable = pParams->bIsWritable;
581
582 ResourceParams.dwOffsetInSSH =
583 uiIndirectStateOffset +
584 pKernelState->dwSshOffset +
585 pKernelState->dwBindingTableSize +
586 (pParams->dwBindingTableOffset[i] * m_dwMaxSurfaceStateSize);
587 ResourceParams.HwCommandType = MOS_SURFACE_STATE;
588
589 MHW_MI_CHK_STATUS(m_pfnAddResourceToCmd(
590 pOsInterface,
591 pCmdBuffer,
592 &ResourceParams));
593 }
594 }
595
596 return eStatus;
597 }
598
SetSamplerState(void * pSampler,PMHW_SAMPLER_STATE_PARAM pParam)599 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::SetSamplerState(
600 void *pSampler,
601 PMHW_SAMPLER_STATE_PARAM pParam)
602 {
603 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
604
605 MHW_FUNCTION_ENTER;
606
607 MHW_MI_CHK_NULL(pParam);
608
609 if (pParam->pKernelState)
610 {
611 PMHW_KERNEL_STATE pKernelState;
612 uint32_t dwCurrSampler;
613 uint32_t dwNumSampler;
614
615 mhw_state_heap_g12_X::SAMPLER_STATE_CMD Cmd;
616 Cmd.DW0.MinModeFilter = Cmd.MIN_MODE_FILTER_LINEAR;
617 Cmd.DW0.MagModeFilter = Cmd.MAG_MODE_FILTER_LINEAR;
618 Cmd.DW0.TextureBorderColorMode = Cmd.TEXTURE_BORDER_COLOR_MODE_8BIT;
619 Cmd.DW1.ShadowFunction = Cmd.SHADOW_FUNCTION_PREFILTEROPNEVER;
620 Cmd.DW3.TczAddressControlMode = Cmd.TCZ_ADDRESS_CONTROL_MODE_CLAMP;
621 Cmd.DW3.TcyAddressControlMode = Cmd.TCY_ADDRESS_CONTROL_MODE_CLAMP;
622 Cmd.DW3.TcxAddressControlMode = Cmd.TCX_ADDRESS_CONTROL_MODE_CLAMP;
623 Cmd.DW3.RAddressMinFilterRoundingEnable = true;
624 Cmd.DW3.RAddressMagFilterRoundingEnable = true;
625 Cmd.DW3.VAddressMinFilterRoundingEnable = true;
626 Cmd.DW3.VAddressMagFilterRoundingEnable = true;
627 Cmd.DW3.UAddressMinFilterRoundingEnable = true;
628 Cmd.DW3.UAddressMagFilterRoundingEnable = true;
629 Cmd.DW0.SamplerDisable = false;
630
631 dwNumSampler = pParam->pKernelState->KernelParams.iSamplerCount;
632
633 for (dwCurrSampler = 0; dwCurrSampler < dwNumSampler; dwCurrSampler++)
634 {
635 if (pParam[dwCurrSampler].bInUse)
636 {
637 pKernelState = pParam[dwCurrSampler].pKernelState;
638
639 MHW_MI_CHK_NULL(pKernelState);
640
641 MHW_MI_CHK_STATUS(pKernelState->m_dshRegion.AddData(
642 &Cmd,
643 pKernelState->dwSamplerOffset + dwCurrSampler * Cmd.byteSize,
644 sizeof(Cmd)));
645 }
646 }
647 }
648 else if (pParam->bInUse)
649 {
650 MHW_MI_CHK_NULL(pSampler);
651
652 if (pParam->SamplerType == MHW_SAMPLER_TYPE_3D)
653 {
654 mhw_state_heap_g12_X::SAMPLER_STATE_CMD *pUnormSampler =
655 (mhw_state_heap_g12_X::SAMPLER_STATE_CMD*)pSampler;
656
657 mhw_state_heap_g12_X::SAMPLER_STATE_CMD UnormSamplerInit;
658
659 // Add additional defaults specific to media
660 UnormSamplerInit.DW0.MinModeFilter = UnormSamplerInit.MIN_MODE_FILTER_LINEAR;
661 UnormSamplerInit.DW0.MagModeFilter = UnormSamplerInit.MAG_MODE_FILTER_LINEAR;
662 UnormSamplerInit.DW0.TextureBorderColorMode = UnormSamplerInit.TEXTURE_BORDER_COLOR_MODE_8BIT;
663 UnormSamplerInit.DW0.SamplerDisable = false;
664 UnormSamplerInit.DW1.ShadowFunction = UnormSamplerInit.SHADOW_FUNCTION_PREFILTEROPNEVER;
665 UnormSamplerInit.DW3.TczAddressControlMode = UnormSamplerInit.TCZ_ADDRESS_CONTROL_MODE_CLAMP;
666 UnormSamplerInit.DW3.TcyAddressControlMode = UnormSamplerInit.TCY_ADDRESS_CONTROL_MODE_CLAMP;
667 UnormSamplerInit.DW3.TcxAddressControlMode = UnormSamplerInit.TCX_ADDRESS_CONTROL_MODE_CLAMP;
668 UnormSamplerInit.DW3.RAddressMinFilterRoundingEnable = true;
669 UnormSamplerInit.DW3.RAddressMagFilterRoundingEnable = true;
670 UnormSamplerInit.DW3.VAddressMinFilterRoundingEnable = true;
671 UnormSamplerInit.DW3.VAddressMagFilterRoundingEnable = true;
672 UnormSamplerInit.DW3.UAddressMinFilterRoundingEnable = true;
673 UnormSamplerInit.DW3.UAddressMagFilterRoundingEnable = true;
674
675 *pUnormSampler = UnormSamplerInit;
676
677 if (pParam->Unorm.SamplerFilterMode == MHW_SAMPLER_FILTER_NEAREST)
678 {
679 pUnormSampler->DW0.MinModeFilter = pUnormSampler->MIN_MODE_FILTER_NEAREST;
680 pUnormSampler->DW0.MagModeFilter = pUnormSampler->MAG_MODE_FILTER_NEAREST;
681 }
682 else if (pParam->Unorm.SamplerFilterMode == MHW_SAMPLER_FILTER_BILINEAR)
683 {
684 pUnormSampler->DW0.MinModeFilter = pUnormSampler->MIN_MODE_FILTER_LINEAR;
685 pUnormSampler->DW0.MagModeFilter = pUnormSampler->MAG_MODE_FILTER_LINEAR;
686 }
687 else
688 {
689 pUnormSampler->DW0.MinModeFilter = pParam->Unorm.MinFilter;
690 pUnormSampler->DW0.MagModeFilter = pParam->Unorm.MagFilter;
691 }
692
693 pUnormSampler->DW3.TcxAddressControlMode = pParam->Unorm.AddressU;
694 pUnormSampler->DW3.TcyAddressControlMode = pParam->Unorm.AddressV;
695 pUnormSampler->DW3.TczAddressControlMode = pParam->Unorm.AddressW;
696
697 if (pParam->Unorm.bBorderColorIsValid)
698 {
699 mhw_state_heap_g12_X::SAMPLER_INDIRECT_STATE_CMD *pUnormSamplerBorderColor =
700 (mhw_state_heap_g12_X::SAMPLER_INDIRECT_STATE_CMD*)pParam->Unorm.pIndirectState;
701
702 mhw_state_heap_g12_X::SAMPLER_INDIRECT_STATE_CMD UnormSamplerBorderColorInit;
703 *pUnormSamplerBorderColor = UnormSamplerBorderColorInit;
704
705 // Since the structure is a union between float, uint, and int, can use any to set the state DW
706 pUnormSamplerBorderColor->DW0.Obj0.BorderColorRed = pParam->Unorm.BorderColorRedU;
707 pUnormSamplerBorderColor->DW1.BorderColorGreen = pParam->Unorm.BorderColorGreenU;
708 pUnormSamplerBorderColor->DW2.BorderColorBlue = pParam->Unorm.BorderColorBlueU;
709 pUnormSamplerBorderColor->DW3.BorderColorAlpha = pParam->Unorm.BorderColorAlphaU;
710
711 pUnormSampler->DW2.IndirectStatePointer = pParam->Unorm.IndirectStateOffset >> MHW_SAMPLER_INDIRECT_SHIFT;
712 }
713
714 if (pParam->Unorm.bChromaKeyEnable)
715 {
716 pUnormSampler->DW1.ChromakeyEnable = true;
717 pUnormSampler->DW1.ChromakeyIndex = pParam->Unorm.ChromaKeyIndex;
718 pUnormSampler->DW1.ChromakeyMode = pParam->Unorm.ChromaKeyMode;
719 }
720
721 }
722
723 else if (pParam->SamplerType == MHW_SAMPLER_TYPE_AVS)
724 {
725 mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_CMD *pSamplerState8x8 =
726 (mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_CMD*)pSampler;
727
728 mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_CMD SamplerState8x8Init;
729 // Add additional defaults specific to media
730 SamplerState8x8Init.DW4.ShuffleOutputwritebackForSample8X8 = 1;
731
732 *pSamplerState8x8 = SamplerState8x8Init;
733
734 if (pParam->Avs.bEnableAVS)
735 {
736 pSamplerState8x8->DW3.Enable8TapFilter = pParam->Avs.EightTapAFEnable;
737
738 // For HDC Direct Write, set Writeback same as Original Sample_8x8
739 if (pParam->Avs.bHdcDwEnable || pParam->Avs.bWritebackStandard)
740 {
741 pSamplerState8x8->DW4.ShuffleOutputwritebackForSample8X8 = 0;
742 }
743
744 if (pParam->Avs.pMhwSamplerAvsTableParam)
745 {
746 MHW_MI_CHK_STATUS(LoadSamplerAvsTable(pSamplerState8x8, pParam->Avs.pMhwSamplerAvsTableParam));
747 }
748 else
749 {
750 MHW_ASSERTMESSAGE("Invalid sampler params for avs 8x8 table \n");
751 return MOS_STATUS_INVALID_PARAMETER;
752 }
753 }
754 }
755 else
756 {
757 MHW_ASSERTMESSAGE("Invalid sampler type '%d'", pParam->SamplerType);
758 return MOS_STATUS_INVALID_PARAMETER;
759 }
760 }
761
762 return eStatus;
763 }
764
AddSamplerStateData(uint32_t samplerOffset,MemoryBlock * memoryBlock,PMHW_SAMPLER_STATE_PARAM pParam)765 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::AddSamplerStateData(
766 uint32_t samplerOffset,
767 MemoryBlock *memoryBlock,
768 PMHW_SAMPLER_STATE_PARAM pParam)
769 {
770 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
771
772 MHW_MI_CHK_NULL(memoryBlock);
773 MHW_MI_CHK_NULL(pParam);
774
775 if (pParam->SamplerType == MHW_SAMPLER_TYPE_3D)
776 {
777 mhw_state_heap_g12_X::SAMPLER_STATE_CMD unormSampler;
778 mhw_state_heap_g12_X::SAMPLER_INDIRECT_STATE_CMD indirectState;
779
780 pParam->Unorm.pIndirectState = &indirectState;
781
782 MHW_MI_CHK_STATUS(SetSamplerState(&unormSampler, pParam));
783
784 // Add indirect state to heap if necessary
785 if (pParam->Unorm.bBorderColorIsValid)
786 {
787 // adjust unormSampler->DW2.IndirectStatePointer
788 // to include memoryBlock's offset from base of state heap
789 unormSampler.DW2.IndirectStatePointer =
790 (pParam->Unorm.IndirectStateOffset + memoryBlock->GetOffset())
791 >> MHW_SAMPLER_INDIRECT_SHIFT;
792
793 MHW_MI_CHK_STATUS(memoryBlock->AddData(
794 &indirectState,
795 pParam->Unorm.IndirectStateOffset,
796 sizeof(mhw_state_heap_g12_X::SAMPLER_INDIRECT_STATE_CMD)));
797 }
798
799 // Add sampler state data to heap
800 MHW_MI_CHK_STATUS(memoryBlock->AddData(
801 &unormSampler,
802 samplerOffset,
803 sizeof(mhw_state_heap_g12_X::SAMPLER_STATE_CMD)));
804 }
805 else if (pParam->SamplerType == MHW_SAMPLER_TYPE_AVS)
806 {
807 mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_CMD samplerState8x8;
808
809 MHW_MI_CHK_STATUS(SetSamplerState(&samplerState8x8, pParam));
810
811 // Add sampler data to heap
812 MHW_MI_CHK_STATUS(memoryBlock->AddData(
813 &samplerState8x8,
814 samplerOffset,
815 sizeof(mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_CMD)));
816 }
817 else
818 {
819 MHW_ASSERTMESSAGE("Invalid sampler type '%d'", pParam->SamplerType);
820 eStatus = MOS_STATUS_INVALID_PARAMETER;
821 }
822
823 return eStatus;
824 }
InitSamplerStates(void * pSamplerStates,int32_t iSamplers)825 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::InitSamplerStates(
826 void *pSamplerStates,
827 int32_t iSamplers)
828 {
829 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
830
831 MHW_FUNCTION_ENTER;
832
833 MHW_MI_CHK_NULL(pSamplerStates);
834
835 mhw_state_heap_g12_X::SAMPLER_STATE_CMD SamplerStateInit;
836 // Add additional defaults specific to media
837 SamplerStateInit.DW0.MinModeFilter = SamplerStateInit.MIN_MODE_FILTER_LINEAR;
838 SamplerStateInit.DW0.MagModeFilter = SamplerStateInit.MAG_MODE_FILTER_LINEAR;
839 SamplerStateInit.DW0.TextureBorderColorMode = SamplerStateInit.TEXTURE_BORDER_COLOR_MODE_8BIT;
840 SamplerStateInit.DW0.SamplerDisable = true;
841 SamplerStateInit.DW1.ShadowFunction = SamplerStateInit.SHADOW_FUNCTION_PREFILTEROPNEVER;
842 SamplerStateInit.DW3.TczAddressControlMode = SamplerStateInit.TCZ_ADDRESS_CONTROL_MODE_CLAMP;
843 SamplerStateInit.DW3.TcyAddressControlMode = SamplerStateInit.TCY_ADDRESS_CONTROL_MODE_CLAMP;
844 SamplerStateInit.DW3.TcxAddressControlMode = SamplerStateInit.TCX_ADDRESS_CONTROL_MODE_CLAMP;
845 SamplerStateInit.DW3.RAddressMinFilterRoundingEnable = true;
846 SamplerStateInit.DW3.RAddressMagFilterRoundingEnable = true;
847 SamplerStateInit.DW3.VAddressMinFilterRoundingEnable = true;
848 SamplerStateInit.DW3.VAddressMagFilterRoundingEnable = true;
849 SamplerStateInit.DW3.UAddressMinFilterRoundingEnable = true;
850 SamplerStateInit.DW3.UAddressMagFilterRoundingEnable = true;
851
852 // Initialize Media Sampler States
853 uint8_t *pu8SamplerState = (uint8_t*)pSamplerStates;
854
855 for (; iSamplers > 0; iSamplers--)
856 {
857 MOS_SecureMemcpy(pu8SamplerState, SamplerStateInit.byteSize, &SamplerStateInit, SamplerStateInit.byteSize);
858 pu8SamplerState += SamplerStateInit.byteSize;
859 }
860
861 return eStatus;
862 }
863
864 //!
865 //! \brief Load Sampler 8X8 State Table for Gen9
866 //! \details Load Sampler 8x8 State Table
867 //! \param [in] void *pTable
868 //! Pointer to 8x8 table in GSH to load
869 //! \param [in] PMHW_SAMPLER_AVS_TABLE_PARAM pMhwSamplerAvsTableParam
870 //! Pointer to 8x8 sampler state params
871 //! \return MOS_STATUS
872 //!
LoadSamplerAvsTable(void * pvTable,PMHW_SAMPLER_AVS_TABLE_PARAM pMhwSamplerAvsTableParam)873 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::LoadSamplerAvsTable(
874 void *pvTable,
875 PMHW_SAMPLER_AVS_TABLE_PARAM pMhwSamplerAvsTableParam)
876 {
877 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
878
879 MHW_FUNCTION_ENTER;
880
881 MHW_MI_CHK_NULL(pvTable);
882 MHW_MI_CHK_NULL(pMhwSamplerAvsTableParam);
883
884 mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_CMD *pSampler8x8Avs =
885 (mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_CMD*)pvTable;
886
887 // DW0 ~ DW15 are for sampler state and programmed in other function, so no need to setup for it here.
888
889 uint32_t u32ConvolveTableNum =
890 sizeof(pSampler8x8Avs->FilterCoefficient016) / sizeof(pSampler8x8Avs->FilterCoefficient016[0]);
891
892 // DW16 ~ DW151 setting for table coefficients (DW0 ~ DW7) * 17
893 for (uint32_t u32CoeffTableIdx = 0; u32CoeffTableIdx < u32ConvolveTableNum; u32CoeffTableIdx++)
894 {
895 PMHW_AVS_COEFFICIENT_PARAM pCoeffParam = &pMhwSamplerAvsTableParam->paMhwAvsCoeffParam[u32CoeffTableIdx];
896 mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD *pCoeffTable =
897 &pSampler8x8Avs->FilterCoefficient016[u32CoeffTableIdx];
898 MHW_MI_CHK_NULL(pCoeffParam);
899 MHW_MI_CHK_NULL(pCoeffTable);
900
901 pCoeffTable->DW0.Table0XFilterCoefficientN0 = pCoeffParam->ZeroXFilterCoefficient[0];
902 pCoeffTable->DW0.Table0YFilterCoefficientN0 = pCoeffParam->ZeroYFilterCoefficient[0];
903 pCoeffTable->DW0.Table0XFilterCoefficientN1 = pCoeffParam->ZeroXFilterCoefficient[1];
904 pCoeffTable->DW0.Table0YFilterCoefficientN1 = pCoeffParam->ZeroYFilterCoefficient[1];
905
906 pCoeffTable->DW1.Table0XFilterCoefficientN2 = pCoeffParam->ZeroXFilterCoefficient[2];
907 pCoeffTable->DW1.Table0YFilterCoefficientN2 = pCoeffParam->ZeroYFilterCoefficient[2];
908 pCoeffTable->DW1.Table0XFilterCoefficientN3 = pCoeffParam->ZeroXFilterCoefficient[3];
909 pCoeffTable->DW1.Table0YFilterCoefficientN3 = pCoeffParam->ZeroYFilterCoefficient[3];
910
911 pCoeffTable->DW2.Table0XFilterCoefficientN4 = pCoeffParam->ZeroXFilterCoefficient[4];
912 pCoeffTable->DW2.Table0YFilterCoefficientN4 = pCoeffParam->ZeroYFilterCoefficient[4];
913 pCoeffTable->DW2.Table0XFilterCoefficientN5 = pCoeffParam->ZeroXFilterCoefficient[5];
914 pCoeffTable->DW2.Table0YFilterCoefficientN5 = pCoeffParam->ZeroYFilterCoefficient[5];
915
916 pCoeffTable->DW3.Table0XFilterCoefficientN6 = pCoeffParam->ZeroXFilterCoefficient[6];
917 pCoeffTable->DW3.Table0YFilterCoefficientN6 = pCoeffParam->ZeroYFilterCoefficient[6];
918 pCoeffTable->DW3.Table0XFilterCoefficientN7 = pCoeffParam->ZeroXFilterCoefficient[7];
919 pCoeffTable->DW3.Table0YFilterCoefficientN7 = pCoeffParam->ZeroYFilterCoefficient[7];
920
921 pCoeffTable->DW4.Table1XFilterCoefficientN2 = pCoeffParam->OneXFilterCoefficient[0];
922 pCoeffTable->DW4.Table1XFilterCoefficientN3 = pCoeffParam->OneXFilterCoefficient[1];
923 pCoeffTable->DW5.Table1XFilterCoefficientN4 = pCoeffParam->OneXFilterCoefficient[2];
924 pCoeffTable->DW5.Table1XFilterCoefficientN5 = pCoeffParam->OneXFilterCoefficient[3];
925
926 pCoeffTable->DW6.Table1YFilterCoefficientN2 = pCoeffParam->OneYFilterCoefficient[0];
927 pCoeffTable->DW6.Table1YFilterCoefficientN3 = pCoeffParam->OneYFilterCoefficient[1];
928 pCoeffTable->DW7.Table1YFilterCoefficientN4 = pCoeffParam->OneYFilterCoefficient[2];
929 pCoeffTable->DW7.Table1YFilterCoefficientN5 = pCoeffParam->OneYFilterCoefficient[3];
930 }
931
932 // DW152 ~ DW153 setting for table control
933 pSampler8x8Avs->DW152.TransitionAreaWith8Pixels = pMhwSamplerAvsTableParam->byteTransitionArea8Pixels; // 3-bits
934 pSampler8x8Avs->DW152.TransitionAreaWith4Pixels = pMhwSamplerAvsTableParam->byteTransitionArea4Pixels; // 3-bits
935 pSampler8x8Avs->DW152.MaxDerivative8Pixels = pMhwSamplerAvsTableParam->byteMaxDerivative8Pixels;
936 pSampler8x8Avs->DW152.MaxDerivative4Pixels = pMhwSamplerAvsTableParam->byteMaxDerivative4Pixels;
937 pSampler8x8Avs->DW152.DefaultSharpnessLevel = pMhwSamplerAvsTableParam->byteDefaultSharpnessLevel;
938
939 pSampler8x8Avs->DW153.RgbAdaptive = pMhwSamplerAvsTableParam->bEnableRGBAdaptive;
940 pSampler8x8Avs->DW153.AdaptiveFilterForAllChannels = pMhwSamplerAvsTableParam->bAdaptiveFilterAllChannels;
941 pSampler8x8Avs->DW153.BypassYAdaptiveFiltering = pMhwSamplerAvsTableParam->bBypassYAdaptiveFiltering;
942 pSampler8x8Avs->DW153.BypassXAdaptiveFiltering = pMhwSamplerAvsTableParam->bBypassXAdaptiveFiltering;
943
944 u32ConvolveTableNum =
945 sizeof(pSampler8x8Avs->FilterCoefficient1731) / sizeof(pSampler8x8Avs->FilterCoefficient1731[0]);
946 // DW160 ~ DW279 setting for extra table coefficients (DW0 ~ DW7) * 15
947 for (uint32_t u32CoeffTableIdx = 0; u32CoeffTableIdx < u32ConvolveTableNum; u32CoeffTableIdx++)
948 {
949 PMHW_AVS_COEFFICIENT_PARAM pCoeffParamExtra = &pMhwSamplerAvsTableParam->paMhwAvsCoeffParamExtra[u32CoeffTableIdx];
950 mhw_state_heap_g12_X::SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD *pCoeffTableExtra =
951 &pSampler8x8Avs->FilterCoefficient1731[u32CoeffTableIdx];
952 MHW_MI_CHK_NULL(pCoeffParamExtra);
953 MHW_MI_CHK_NULL(pCoeffTableExtra);
954
955 pCoeffTableExtra->DW0.Table0XFilterCoefficientN0 = pCoeffParamExtra->ZeroXFilterCoefficient[0];
956 pCoeffTableExtra->DW0.Table0YFilterCoefficientN0 = pCoeffParamExtra->ZeroYFilterCoefficient[0];
957 pCoeffTableExtra->DW0.Table0XFilterCoefficientN1 = pCoeffParamExtra->ZeroXFilterCoefficient[1];
958 pCoeffTableExtra->DW0.Table0YFilterCoefficientN1 = pCoeffParamExtra->ZeroYFilterCoefficient[1];
959
960 pCoeffTableExtra->DW1.Table0XFilterCoefficientN2 = pCoeffParamExtra->ZeroXFilterCoefficient[2];
961 pCoeffTableExtra->DW1.Table0YFilterCoefficientN2 = pCoeffParamExtra->ZeroYFilterCoefficient[2];
962 pCoeffTableExtra->DW1.Table0XFilterCoefficientN3 = pCoeffParamExtra->ZeroXFilterCoefficient[3];
963 pCoeffTableExtra->DW1.Table0YFilterCoefficientN3 = pCoeffParamExtra->ZeroYFilterCoefficient[3];
964
965 pCoeffTableExtra->DW2.Table0XFilterCoefficientN4 = pCoeffParamExtra->ZeroXFilterCoefficient[4];
966 pCoeffTableExtra->DW2.Table0YFilterCoefficientN4 = pCoeffParamExtra->ZeroYFilterCoefficient[4];
967 pCoeffTableExtra->DW2.Table0XFilterCoefficientN5 = pCoeffParamExtra->ZeroXFilterCoefficient[5];
968 pCoeffTableExtra->DW2.Table0YFilterCoefficientN5 = pCoeffParamExtra->ZeroYFilterCoefficient[5];
969
970 pCoeffTableExtra->DW3.Table0XFilterCoefficientN6 = pCoeffParamExtra->ZeroXFilterCoefficient[6];
971 pCoeffTableExtra->DW3.Table0YFilterCoefficientN6 = pCoeffParamExtra->ZeroYFilterCoefficient[6];
972 pCoeffTableExtra->DW3.Table0XFilterCoefficientN7 = pCoeffParamExtra->ZeroXFilterCoefficient[7];
973 pCoeffTableExtra->DW3.Table0YFilterCoefficientN7 = pCoeffParamExtra->ZeroYFilterCoefficient[7];
974
975 pCoeffTableExtra->DW4.Table1XFilterCoefficientN2 = pCoeffParamExtra->OneXFilterCoefficient[0];
976 pCoeffTableExtra->DW4.Table1XFilterCoefficientN3 = pCoeffParamExtra->OneXFilterCoefficient[1];
977 pCoeffTableExtra->DW5.Table1XFilterCoefficientN4 = pCoeffParamExtra->OneXFilterCoefficient[2];
978 pCoeffTableExtra->DW5.Table1XFilterCoefficientN5 = pCoeffParamExtra->OneXFilterCoefficient[3];
979
980 pCoeffTableExtra->DW6.Table1YFilterCoefficientN2 = pCoeffParamExtra->OneYFilterCoefficient[0];
981 pCoeffTableExtra->DW6.Table1YFilterCoefficientN3 = pCoeffParamExtra->OneYFilterCoefficient[1];
982 pCoeffTableExtra->DW7.Table1YFilterCoefficientN4 = pCoeffParamExtra->OneYFilterCoefficient[2];
983 pCoeffTableExtra->DW7.Table1YFilterCoefficientN5 = pCoeffParamExtra->OneYFilterCoefficient[3];
984 }
985
986 return eStatus;
987 }
988
SetInterfaceDescriptor(uint32_t dwNumIdsToSet,PMHW_INTERFACE_DESCRIPTOR_PARAMS pParams)989 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G12_X::SetInterfaceDescriptor(
990 uint32_t dwNumIdsToSet,
991 PMHW_INTERFACE_DESCRIPTOR_PARAMS pParams)
992 {
993 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
994
995 MHW_FUNCTION_ENTER;
996 MHW_MI_CHK_NULL(pParams);
997
998 for (uint32_t dwCurrId = 0; dwCurrId < dwNumIdsToSet; dwCurrId++)
999 {
1000 PMHW_KERNEL_STATE pKernelState = pParams[dwCurrId].pKernelState;
1001
1002 MHW_MI_CHK_NULL(pKernelState);
1003
1004 mhw_state_heap_g12_X::INTERFACE_DESCRIPTOR_DATA_CMD cmd;
1005
1006 cmd.DW0.KernelStartPointer =
1007 (pKernelState->m_ishRegion.GetOffset() +
1008 pKernelState->dwKernelBinaryOffset +
1009 pParams[dwCurrId].dwKernelStartOffset) >>
1010 MHW_KERNEL_OFFSET_SHIFT;
1011 cmd.DW3.SamplerStatePointer =
1012 (pKernelState->m_dshRegion.GetOffset() +
1013 pKernelState->dwSamplerOffset +
1014 pParams[dwCurrId].dwSamplerOffset) >>
1015 MHW_SAMPLER_SHIFT;
1016 cmd.DW3.SamplerCount = (pKernelState->KernelParams.iSamplerCount - 1) / 4 + 1;
1017 cmd.DW4.BindingTablePointer = MOS_ROUNDUP_SHIFT(
1018 (pKernelState->dwSshOffset +
1019 pParams[dwCurrId].dwBtOffset),
1020 MHW_BINDING_TABLE_ID_SHIFT);
1021 cmd.DW5.ConstantIndirectUrbEntryReadLength = MOS_ROUNDUP_SHIFT(
1022 pParams->pKernelState->KernelParams.iCurbeLength,
1023 MHW_CURBE_SHIFT);
1024 cmd.DW6.NumberOfThreadsInGpgpuThreadGroup = 1;
1025
1026 uint32_t idOffsetInIdSpace =
1027 pKernelState->dwIdOffset +
1028 (pParams[dwCurrId].dwIdIdx * m_wSizeOfCmdInterfaceDescriptorData);
1029 MHW_MI_CHK_STATUS(pKernelState->m_dshRegion.AddData(
1030 &cmd,
1031 idOffsetInIdSpace,
1032 cmd.byteSize));
1033 }
1034 return eStatus;
1035 }
1036