1 /*
2 * Copyright (c) 2014-2018, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_state_heap_g11.c
24 //! \brief This modules implements HW interface layer to be used on all platforms on all operating systems/DDIs, across MHW components.
25 //!
26 #include "mhw_state_heap_g11.h"
27 #include "mhw_cp_interface.h"
28 #include "mhw_render_hwcmd_g11_X.h"
29
MHW_STATE_HEAP_INTERFACE_G11_X(PMOS_INTERFACE pInputOSInterface,int8_t bDynamicMode)30 MHW_STATE_HEAP_INTERFACE_G11_X::MHW_STATE_HEAP_INTERFACE_G11_X(
31 PMOS_INTERFACE pInputOSInterface, int8_t bDynamicMode):
32 MHW_STATE_HEAP_INTERFACE_GENERIC(pInputOSInterface, bDynamicMode)
33 {
34 m_wBtIdxAlignment = m_mhwNumBindingTableEntryOffset;
35 m_wIdAlignment = (1 << m_mhwGenericOffsetShift);
36 m_wCurbeAlignment = (1 << m_mhwGenericOffsetShift);
37
38 m_dwSizeSurfaceState = MOS_ALIGN_CEIL(mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::byteSize, MHW_SURFACE_STATE_ALIGN);
39 m_dwSizeSurfaceStateAdv = MOS_ALIGN_CEIL(mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD::byteSize, MHW_SURFACE_STATE_ALIGN);
40 m_dwMaxSurfaceStateSize = MOS_MAX(m_dwSizeSurfaceState, m_dwSizeSurfaceStateAdv);
41 m_wSizeOfInterfaceDescriptor = mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD::byteSize;
42 m_wSizeOfCmdInterfaceDescriptorData = MOS_ALIGN_CEIL(m_wSizeOfInterfaceDescriptor, m_wIdAlignment);
43 m_wSizeOfCmdSamplerState = mhw_state_heap_g11_X::SAMPLER_STATE_CMD::byteSize;
44
45 InitHwSizes();
46 }
47
~MHW_STATE_HEAP_INTERFACE_G11_X()48 MHW_STATE_HEAP_INTERFACE_G11_X::~MHW_STATE_HEAP_INTERFACE_G11_X()
49 {
50 MHW_FUNCTION_ENTER;
51 }
52
InitHwSizes()53 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::InitHwSizes()
54 {
55 m_HwSizes.dwSizeMediaObjectHeaderCmd = mhw_render_g11_X::MEDIA_OBJECT_CMD::byteSize;
56 m_HwSizes.dwSizeSurfaceState = MOS_ALIGN_CEIL(mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::byteSize, MHW_SURFACE_STATE_ALIGN);
57 m_HwSizes.dwSizeSurfaceStateAvs = MOS_ALIGN_CEIL(mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD::byteSize, MHW_SURFACE_STATE_ALIGN);
58 m_HwSizes.dwMaxSizeSurfaceState = MOS_MAX(m_HwSizes.dwSizeSurfaceState, m_HwSizes.dwSizeSurfaceStateAvs);
59 m_HwSizes.dwSizeBindingTableState = mhw_state_heap_g11_X::BINDING_TABLE_STATE_CMD::byteSize;
60 m_HwSizes.dwSizeSamplerState = mhw_state_heap_g11_X::SAMPLER_STATE_CMD::byteSize;
61 m_HwSizes.dwSizeSamplerIndirectState = mhw_state_heap_g11_X::SAMPLER_INDIRECT_STATE_CMD::byteSize;
62 m_HwSizes.dwSizeSamplerStateVA = mhw_state_heap_g11_X::SAMPLER_STATE_8x8_ERODE_DILATE_MINMAXFILTER_CMD::byteSize; // MinMaxFilter, Erode, Dilate functions
63 m_HwSizes.dwSizeSamplerStateVAConvolve = mhw_state_heap_g11_X::SAMPLER_STATE_8x8_CONVOLVE_CMD::byteSize;
64 m_HwSizes.dwSizeSamplerStateTable8x8 = mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_CMD::byteSize - 16 * sizeof(uint32_t); // match old definitions to table size
65 m_HwSizes.dwSizeSampler8x8Table =
66 MOS_ALIGN_CEIL(m_HwSizes.dwSizeSamplerStateTable8x8, MHW_SAMPLER_STATE_ALIGN);
67 m_HwSizes.dwSizeSamplerStateAvs =
68 MOS_ALIGN_CEIL(mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_CMD::byteSize, MHW_SAMPLER_STATE_AVS_ALIGN_MEDIA);
69 m_HwSizes.dwSizeInterfaceDescriptor = mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD::byteSize;
70 m_HwSizes.dwSizeMediaWalkerBlock = 16;
71
72 return MOS_STATUS_SUCCESS;
73 }
74
SetInterfaceDescriptorEntry(PMHW_ID_ENTRY_PARAMS pParams)75 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::SetInterfaceDescriptorEntry(
76 PMHW_ID_ENTRY_PARAMS pParams)
77 {
78 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
79
80 MHW_FUNCTION_ENTER;
81
82 //------------------------------------
83 MHW_MI_CHK_NULL(pParams);
84 //------------------------------------
85
86 // Ensures that the Media ID base is correct
87 MHW_ASSERT(MOS_IS_ALIGNED(pParams->dwMediaIdOffset, m_wIdAlignment));
88
89 uint8_t *pStateHeapBase;
90 if (pParams->pGeneralStateHeap)
91 {
92 pStateHeapBase = (uint8_t*)pParams->pGeneralStateHeap->pvLockedHeap;
93 }
94 else
95 {
96 pStateHeapBase = (uint8_t*)(GetDSHPointer()->pvLockedHeap);
97 }
98
99 mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD *pInterfaceDescriptor;
100 pInterfaceDescriptor = (mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD *)
101 (pStateHeapBase + // State Heap Base
102 pParams->dwMediaIdOffset + // Offset to first Media ID
103 pParams->iMediaId * m_wSizeOfInterfaceDescriptor); // Offset to current ID
104 MHW_MI_CHK_NULL(pInterfaceDescriptor);
105 *pInterfaceDescriptor = mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD();
106
107 pInterfaceDescriptor->DW0.KernelStartPointer = pParams->dwKernelOffset >> MHW_KERNEL_OFFSET_SHIFT;
108 pInterfaceDescriptor->DW3.SamplerStatePointer = pParams->dwSamplerOffset >> MHW_SAMPLER_SHIFT;
109 pInterfaceDescriptor->DW3.SamplerCount = pParams->dwSamplerCount;
110 pInterfaceDescriptor->DW4.BindingTablePointer = MOS_ROUNDUP_SHIFT(pParams->dwBindingTableOffset, MHW_BINDING_TABLE_ID_SHIFT);
111 pInterfaceDescriptor->DW5.ConstantUrbEntryReadOffset = pParams->iCurbeOffset >> MHW_CURBE_SHIFT;
112 pInterfaceDescriptor->DW5.ConstantIndirectUrbEntryReadLength = MOS_ROUNDUP_SHIFT(pParams->iCurbeLength, MHW_CURBE_SHIFT);
113 pInterfaceDescriptor->DW6.BarrierEnable = pParams->bBarrierEnable;
114 pInterfaceDescriptor->DW6.NumberOfThreadsInGpgpuThreadGroup = pParams->dwNumberofThreadsInGPGPUGroup;
115 pInterfaceDescriptor->DW6.SharedLocalMemorySize = pParams->dwSharedLocalMemorySize;
116 pInterfaceDescriptor->DW7.CrossThreadConstantDataReadLength = pParams->iCrsThdConDataRdLn >> MHW_THRD_CON_DATA_RD_SHIFT;
117
118 return eStatus;
119 }
120
AddInterfaceDescriptorData(PMHW_ID_ENTRY_PARAMS pParams)121 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::AddInterfaceDescriptorData(
122 PMHW_ID_ENTRY_PARAMS pParams)
123 {
124 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
125
126 MHW_FUNCTION_ENTER;
127
128 //------------------------------------
129 MHW_MI_CHK_NULL(pParams);
130 //------------------------------------
131
132 // Ensures that the Media ID base is correct
133 MHW_ASSERT(MOS_IS_ALIGNED(pParams->dwMediaIdOffset, m_wIdAlignment));
134
135 uint32_t offset = pParams->dwMediaIdOffset + pParams->iMediaId * m_wSizeOfInterfaceDescriptor;
136
137 mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD *pInterfaceDescriptor;
138 pInterfaceDescriptor = (mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD *)MOS_AllocMemory(sizeof(mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD));
139 MHW_MI_CHK_NULL(pInterfaceDescriptor);
140 *pInterfaceDescriptor = mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD();
141
142 pInterfaceDescriptor->DW0.KernelStartPointer = pParams->dwKernelOffset >> MHW_KERNEL_OFFSET_SHIFT;
143 pInterfaceDescriptor->DW3.SamplerStatePointer = pParams->dwSamplerOffset >> MHW_SAMPLER_SHIFT;
144 pInterfaceDescriptor->DW3.SamplerCount = pParams->dwSamplerCount;
145 pInterfaceDescriptor->DW4.BindingTablePointer = MOS_ROUNDUP_SHIFT(pParams->dwBindingTableOffset, MHW_BINDING_TABLE_ID_SHIFT);
146 pInterfaceDescriptor->DW5.ConstantUrbEntryReadOffset = pParams->iCurbeOffset >> MHW_CURBE_SHIFT;
147 pInterfaceDescriptor->DW5.ConstantIndirectUrbEntryReadLength = MOS_ROUNDUP_SHIFT(pParams->iCurbeLength, MHW_CURBE_SHIFT);
148 pInterfaceDescriptor->DW6.BarrierEnable = pParams->bBarrierEnable;
149 pInterfaceDescriptor->DW6.NumberOfThreadsInGpgpuThreadGroup = pParams->dwNumberofThreadsInGPGPUGroup;
150 pInterfaceDescriptor->DW6.SharedLocalMemorySize = pParams->dwSharedLocalMemorySize;
151 pInterfaceDescriptor->DW7.CrossThreadConstantDataReadLength = pParams->iCrsThdConDataRdLn >> MHW_THRD_CON_DATA_RD_SHIFT;
152
153 // need to subtract memory block's offset in current state heap for AddData API
154 offset -= pParams->memoryBlock->GetOffset();
155 pParams->memoryBlock->AddData(pInterfaceDescriptor, offset,
156 sizeof(mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD));
157
158 MOS_SafeFreeMemory(pInterfaceDescriptor);
159
160 return eStatus;
161 }
162
SetSurfaceStateEntry(PMHW_SURFACE_STATE_PARAMS pParams)163 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::SetSurfaceStateEntry(
164 PMHW_SURFACE_STATE_PARAMS pParams)
165 {
166
167 if (!pParams || !m_pOsInterface)
168 {
169 MHW_ASSERTMESSAGE("Invalid parameter\n");
170 return MOS_STATUS_INVALID_PARAMETER;
171 }
172
173 uint32_t TileMode = (pParams->bTiledSurface) ? ((pParams->bTileWalk == 0) ? 2 /*x-tile*/: 3 /*y-tile*/) : 0; /*linear*/
174
175 // for Gen11 Adv surface state
176 if (pParams->bUseAdvState)
177 {
178 // Obtain the Pointer to the Surface state from SSH Buffer
179 mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD* pSurfaceStateAdv =
180 (mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD*) pParams->pSurfaceState;
181 MHW_MI_CHK_NULL(pSurfaceStateAdv);
182 // Initialize Surface State
183 *pSurfaceStateAdv = mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD();
184
185 pSurfaceStateAdv->DW0.Rotation = pParams->RotationMode;
186 pSurfaceStateAdv->DW0.XOffset = pParams->iXOffset >> 2;
187 pSurfaceStateAdv->DW0.YOffset = pParams->iYOffset >> 2;
188 pSurfaceStateAdv->DW1.Width = pParams->dwWidth - 1;
189 pSurfaceStateAdv->DW1.Height = pParams->dwHeight - 1;
190 pSurfaceStateAdv->DW1.CrVCbUPixelOffsetVDirection = pParams->UVPixelOffsetVDirection & 3;
191 pSurfaceStateAdv->DW2.CrVCbUPixelOffsetVDirectionMsb = pParams->UVPixelOffsetVDirection >> 2;
192 pSurfaceStateAdv->DW2.CrVCbUPixelOffsetUDirection = pParams->UVPixelOffsetUDirection;
193 pSurfaceStateAdv->DW2.SurfaceFormat = pParams->dwFormat;
194 pSurfaceStateAdv->DW2.InterleaveChroma = pParams->bInterleaveChroma;
195 pSurfaceStateAdv->DW2.SurfacePitch = pParams->dwPitch - 1;
196 pSurfaceStateAdv->DW2.HalfPitchForChroma = pParams->bHalfPitchChroma;
197 pSurfaceStateAdv->DW2.TileMode = TileMode;
198 pSurfaceStateAdv->DW2.MemoryCompressionEnable = pParams->bCompressionEnabled;
199 pSurfaceStateAdv->DW2.MemoryCompressionMode = pParams->bCompressionMode;
200 pSurfaceStateAdv->DW3.XOffsetForUCb = pParams->dwXOffsetForU;
201 pSurfaceStateAdv->DW3.YOffsetForUCb = pParams->dwYOffsetForU;
202 pSurfaceStateAdv->DW4.XOffsetForVCr = pParams->dwXOffsetForV;
203 pSurfaceStateAdv->DW4.YOffsetForVCr = pParams->dwYOffsetForV;
204 pSurfaceStateAdv->DW5.VerticalLineStride = pParams->bVerticalLineStride;
205 pSurfaceStateAdv->DW5.VerticalLineStrideOffset = pParams->bVerticalLineStrideOffset;
206 pSurfaceStateAdv->DW5.SurfaceMemoryObjectControlState = pParams->dwCacheabilityControl;
207
208 // Return offset and pointer for patching
209 pParams->pdwCmd = (uint32_t *)&(pSurfaceStateAdv->DW6.Value);
210 pParams->dwLocationInCmd = 6;
211
212 if (m_pOsInterface->bPitchAndUVPatchingNeeded)
213 {
214 pSurfaceStateAdv->DW2.SurfacePitch = 0;
215 pSurfaceStateAdv->DW3.YOffsetForUCb = 0;
216 }
217 }
218 else // not AVS
219 {
220 // Obtain the Pointer to the Surface state from SSH Buffer
221 mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD* pSurfaceState =
222 (mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD*) pParams->pSurfaceState;
223 MHW_MI_CHK_NULL(pSurfaceState);
224
225 // Initialize Surface State
226 *pSurfaceState = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD();
227
228 pSurfaceState->DW0.SurfaceType = pParams->SurfaceType3D;
229 pSurfaceState->DW0.SurfaceFormat = pParams->dwFormat;
230 pSurfaceState->DW0.TileMode = TileMode;
231 pSurfaceState->DW0.VerticalLineStride = pParams->bVerticalLineStride;
232 pSurfaceState->DW0.VerticalLineStrideOffset = pParams->bVerticalLineStrideOffset;
233 pSurfaceState->DW0.SurfaceHorizontalAlignment = 1;
234 pSurfaceState->DW0.SurfaceVerticalAlignment = 1;
235
236 pSurfaceState->DW1.MemoryObjectControlState = pParams->dwCacheabilityControl;
237 if (pParams->SurfaceType3D == GFX3DSTATE_SURFACETYPE_BUFFER)
238 { // Buffer resources - use original width/height/pitch/depth
239 pSurfaceState->DW2.Width = pParams->dwWidth;
240 pSurfaceState->DW2.Height = pParams->dwHeight;
241 pSurfaceState->DW3.SurfacePitch = pParams->dwPitch;
242 pSurfaceState->DW3.Depth = pParams->dwDepth;
243 }
244 else
245 {
246 pSurfaceState->DW1.SurfaceQpitch = pParams->dwQPitch >> 2;
247 pSurfaceState->DW2.Width = pParams->dwWidth - 1;
248 pSurfaceState->DW2.Height = pParams->dwHeight - 1;
249 pSurfaceState->DW3.SurfacePitch = pParams->dwPitch - 1;
250 pSurfaceState->DW3.Depth = pParams->dwDepth - 1;
251 }
252 pSurfaceState->DW4.RenderTargetAndSampleUnormRotation = pParams->RotationMode;
253 pSurfaceState->DW5.XOffset = pParams->iXOffset >> 2;
254 pSurfaceState->DW5.YOffset = pParams->iYOffset >> 2;
255 pSurfaceState->DW6.Obj0.SeparateUvPlaneEnable = pParams->bSeperateUVPlane;
256 pSurfaceState->DW6.Obj0.HalfPitchForChroma = pParams->bHalfPitchChroma;
257 pSurfaceState->DW6.Obj0.XOffsetForUOrUvPlane = pParams->dwXOffsetForU;
258 pSurfaceState->DW6.Obj0.YOffsetForUOrUvPlane = pParams->dwYOffsetForU;
259
260 // R8B8G8A8 is designed to represent media AYUV format.
261 // But from Gen10+ 3D sampler doesn't support R8B8G8A8 format any more.
262 // Use R8G8B8A8 + Channel Select to fake it.
263 if (pParams->dwFormat == MHW_GFX3DSTATE_SURFACEFORMAT_R8B8G8A8_UNORM)
264 {
265 pSurfaceState->DW0.SurfaceFormat = MHW_GFX3DSTATE_SURFACEFORMAT_R8G8B8A8_UNORM;
266 pSurfaceState->DW7.ShaderChannelSelectAlpha = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_ALPHA_ALPHA;
267 pSurfaceState->DW7.ShaderChannelSelectBlue = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_GREEN_GREEN;
268 pSurfaceState->DW7.ShaderChannelSelectGreen = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_BLUE_BLUE;
269 pSurfaceState->DW7.ShaderChannelSelectRed = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_RED_RED;
270 }
271 else
272 {
273 pSurfaceState->DW7.ShaderChannelSelectAlpha = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_ALPHA_ALPHA;
274 pSurfaceState->DW7.ShaderChannelSelectBlue = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_BLUE_BLUE;
275 pSurfaceState->DW7.ShaderChannelSelectGreen = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_GREEN_GREEN;
276 pSurfaceState->DW7.ShaderChannelSelectRed = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::SHADER_CHANNEL_SELECT_RED_RED;
277 }
278
279 pSurfaceState->DW7.MemoryCompressionEnable = pParams->bCompressionEnabled;
280 pSurfaceState->DW7.MemoryCompressionMode = pParams->bCompressionMode;
281 pSurfaceState->DW8_9.SurfaceBaseAddress = 0;
282 pSurfaceState->DW10_11.Obj3.XOffsetForVPlane = pParams->dwXOffsetForV;
283 pSurfaceState->DW10_11.Obj3.YOffsetForVPlane = pParams->dwYOffsetForV;
284
285 // Return offset and pointer for patching
286 pParams->pdwCmd = (uint32_t *)&(pSurfaceState->DW8_9.SurfaceBaseAddress);
287 pParams->dwLocationInCmd = 8;
288 if (m_pOsInterface->bPitchAndUVPatchingNeeded)
289 {
290 if (pParams->SurfaceType3D != GFX3DSTATE_SURFACETYPE_BUFFER)
291 {
292 pSurfaceState->DW3.SurfacePitch = 0;
293 }
294
295 pSurfaceState->DW6.Obj0.YOffsetForUOrUvPlane = 0;
296 }
297 }
298
299 return MOS_STATUS_SUCCESS;
300 }
301
SetSurfaceState(PMHW_KERNEL_STATE pKernelState,PMOS_COMMAND_BUFFER pCmdBuffer,uint32_t dwNumSurfaceStatesToSet,PMHW_RCS_SURFACE_PARAMS pParams)302 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::SetSurfaceState(
303 PMHW_KERNEL_STATE pKernelState,
304 PMOS_COMMAND_BUFFER pCmdBuffer,
305 uint32_t dwNumSurfaceStatesToSet,
306 PMHW_RCS_SURFACE_PARAMS pParams)
307 {
308 PMOS_INTERFACE pOsInterface;
309 uint8_t *pIndirectState = nullptr;
310 MHW_RESOURCE_PARAMS ResourceParams;
311 uint32_t uiIndirectStateOffset = 0, uiIndirectStateSize = 0;
312 PMHW_STATE_HEAP pStateHeap;
313 uint32_t dwSurfaceType = GFX3DSTATE_SURFACETYPE_NULL; // GFX3DSTATE_SURFACETYPE
314 uint32_t i; // Plane Index
315 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
316
317 MHW_FUNCTION_ENTER;
318
319 MHW_MI_CHK_NULL(pParams);
320 MHW_MI_CHK_NULL(pParams->psSurface);
321 MOS_UNUSED(dwNumSurfaceStatesToSet);
322
323 if (pParams->dwNumPlanes >= MHW_MAX_SURFACE_PLANES)
324 {
325 MHW_ASSERTMESSAGE("Invalid plane number provided");
326 eStatus = MOS_STATUS_INVALID_PARAMETER;
327 return eStatus;
328 }
329
330 pOsInterface = m_pOsInterface;
331 pStateHeap = &m_SurfaceStateHeap;
332
333 MHW_MI_CHK_NULL(pOsInterface);
334 MHW_MI_CHK_STATUS(pOsInterface->pfnGetIndirectStatePointer(pOsInterface, &pIndirectState));
335 MHW_MI_CHK_STATUS(pOsInterface->pfnGetIndirectState(pOsInterface, &uiIndirectStateOffset, &uiIndirectStateSize));
336
337 MOS_ZeroMemory(&ResourceParams, sizeof(ResourceParams));
338 ResourceParams.dwLsbNum = 0; // MHW_STATE_HEAP_SURFACE_STATE_SHIFT
339
340 for ( i = 0; i < pParams->dwNumPlanes; i++)
341 {
342 MHW_ASSERT_INVALID_BINDING_TABLE_IDX(pParams->dwBindingTableOffset[i]);
343 MHW_MI_CHK_NULL(pKernelState);
344 uint32_t u32SurfaceOffsetInSsh =
345 pKernelState->dwSshOffset + pKernelState->dwBindingTableSize + // offset within SSH to start of surfaces for this kernel
346 (m_HwSizes.dwMaxSizeSurfaceState * pParams->dwBindingTableOffset[i]); // offset to the current surface
347 if (u32SurfaceOffsetInSsh + m_HwSizes.dwMaxSizeSurfaceState > uiIndirectStateOffset)
348 {
349 MHW_ASSERTMESSAGE("Location requested for surface state is outside the bounds of SSH");
350 return MOS_STATUS_INVALID_PARAMETER;
351 }
352 uint8_t *pLocationOfSurfaceInSsh = (uint8_t*)
353 (pIndirectState + u32SurfaceOffsetInSsh);
354
355 if (pParams->bUseAdvState)
356 {
357 mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD *pCmd =
358 (mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD*)pLocationOfSurfaceInSsh;
359 MHW_MI_CHK_NULL(pCmd);
360 *pCmd = mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD();
361
362 pCmd->DW1.Width = (pParams->dwWidthToUse[i] == 0) ?
363 pParams->psSurface->dwWidth - 1 : pParams->dwWidthToUse[i] - 1;
364 pCmd->DW1.Height = (pParams->dwHeightToUse[i] == 0) ?
365 pParams->psSurface->dwHeight - 1: pParams->dwHeightToUse[i] - 1;
366 pCmd->DW1.CrVCbUPixelOffsetVDirection = pParams->Direction;
367
368 if(!(pOsInterface->bPitchAndUVPatchingNeeded))
369 pCmd->DW2.SurfacePitch = pParams->psSurface->dwPitch - 1;
370 pCmd->DW2.SurfaceFormat = pParams->ForceSurfaceFormat[i];
371 pCmd->DW2.InterleaveChroma = pParams->bInterleaveChroma;
372
373 if (IS_Y_MAJOR_TILE_FORMAT(pParams->psSurface->TileType))
374 {
375 pCmd->DW2.TileMode = mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD::TILE_MODE_TILEMODEYMAJOR;
376 }
377 else if (pParams->psSurface->TileType == MOS_TILE_LINEAR)
378 {
379 pCmd->DW2.TileMode = mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD::TILE_MODE_TILEMODELINEAR;
380 }
381 else if (pParams->psSurface->TileType == MOS_TILE_X)
382 {
383 pCmd->DW2.TileMode = mhw_state_heap_g11_X::MEDIA_SURFACE_STATE_CMD::TILE_MODE_TILEMODEXMAJOR;
384 }
385
386 if(pParams->psSurface->bCompressible)
387 {
388 MHW_MI_CHK_STATUS(pOsInterface->pfnGetMemoryCompressionMode(pOsInterface, &pParams->psSurface->OsResource, (PMOS_MEMCOMP_STATE) &pParams->psSurface->CompressionMode));
389
390 pCmd->DW2.MemoryCompressionEnable =
391 (pParams->psSurface->CompressionMode == MOS_MMC_DISABLED) ? 0 : 1;
392 pCmd->DW2.MemoryCompressionMode =
393 (pParams->psSurface->CompressionMode == MOS_MMC_VERTICAL) ? 1 : 0;
394 }
395
396 if(pOsInterface->bPitchAndUVPatchingNeeded)
397 {
398 MHW_RESOURCE_PARAMS ResourceParams;
399 MOS_ZeroMemory(&ResourceParams, sizeof(ResourceParams));
400 ResourceParams.presResource = &pParams->psSurface->OsResource;
401 ResourceParams.HwCommandType = MOS_SURFACE_STATE_ADV;
402 ResourceParams.patchType = MOS_PATCH_TYPE_PITCH;
403 ResourceParams.bIsWritable = pParams->bIsWritable;
404 ResourceParams.shiftDirection = 0;
405 ResourceParams.shiftAmount = 3;
406 ResourceParams.pdwCmd = &(pCmd->DW2.Value);
407 ResourceParams.dwLocationInCmd = 2; //DW2
408 ResourceParams.dwOffsetInSSH =
409 uiIndirectStateOffset +
410 pKernelState->dwSshOffset +
411 pKernelState->dwBindingTableSize +
412 (pParams->dwBindingTableOffset[i] * m_dwMaxSurfaceStateSize);
413
414 MHW_MI_CHK_STATUS(m_pfnAddResourceToCmd(pOsInterface,
415 pCmdBuffer,
416 &ResourceParams));
417 }
418
419 pCmd->DW5.SurfaceMemoryObjectControlState = pParams->dwCacheabilityControl;
420
421 pCmd->DW5.TiledResourceMode = Mhw_ConvertToTRMode(pParams->psSurface->TileType);
422
423 if (i == MHW_U_PLANE) // AVS U plane
424 {
425 // Lockoffset is the offset from base address of Y plane to the origin of U/V plane.
426 // So, We can get XOffsetforU by Lockoffset % pSurface->dwPitch, and get YOffsetForU by Lockoffset / pSurface->dwPitch
427 /*pCmd->DW0.XOffset = pParams->psSurface->UPlaneOffset.iXOffset >> 2;
428 pCmd->DW0.YOffset = pParams->psSurface->UPlaneOffset.iYOffset >> 2;
429
430 pCmd->DW3.XOffsetforU = ((uint32_t)pParams->psSurface->UPlaneOffset.iLockSurfaceOffset % pSurface->dwPitch);
431 pCmd->DW3.YOffsetforU = ((uint32_t)pParams->psSurface->UPlaneOffset.iLockSurfaceOffset / pSurface->dwPitch);*/
432
433 if((pOsInterface->bPitchAndUVPatchingNeeded))
434 {
435 // Send UV offset token
436 MHW_RESOURCE_PARAMS ResourceParams;
437
438 MOS_ZeroMemory(&ResourceParams, sizeof(ResourceParams));
439 ResourceParams.presResource = &pParams->psSurface->OsResource;
440 ResourceParams.HwCommandType = MOS_SURFACE_STATE_ADV;
441 ResourceParams.patchType = MOS_PATCH_TYPE_UV_Y_OFFSET;
442 ResourceParams.bIsWritable = pParams->bIsWritable;
443 ResourceParams.shiftDirection = 0;
444 ResourceParams.shiftAmount = 0;
445 ResourceParams.pdwCmd = &(pCmd->DW3.Value);
446
447 ResourceParams.dwLocationInCmd = 3; //DW3
448 ResourceParams.dwOffsetInSSH =
449 uiIndirectStateOffset +
450 pKernelState->dwSshOffset +
451 pKernelState->dwBindingTableSize +
452 (pParams->dwBindingTableOffset[i] * m_dwMaxSurfaceStateSize);
453
454
455 MHW_MI_CHK_STATUS(m_pfnAddResourceToCmd(pOsInterface,
456 pCmdBuffer,
457 &ResourceParams));
458 }
459 else
460 pCmd->DW3.YOffsetForUCb = pParams->psSurface->UPlaneOffset.iYOffset;
461 }
462 else if (i == MHW_V_PLANE) // AVS V plane
463 {
464 pCmd->DW0.XOffset = pParams->psSurface->VPlaneOffset.iXOffset >> 2;
465 pCmd->DW0.YOffset = pParams->psSurface->VPlaneOffset.iYOffset >> 2;
466
467 //pCmd->DW4.XOffsetforV = ((uint32_t)pParams->psSurface->UPlaneOffset.iLockSurfaceOffset % pSurface->dwPitch);
468 //pCmd->DW4.YOffsetforV = ((uint32_t)pParams->psSurface->VPlaneOffset.iLockSurfaceOffset / pSurface->dwPitch);
469 }
470 else // AVS/DNDI Y plane
471 {
472 pCmd->DW3.XOffsetForUCb = pParams->dwXOffset[MHW_U_PLANE];
473 pCmd->DW3.YOffsetForUCb = pParams->dwYOffset[MHW_U_PLANE];
474 pCmd->DW4.XOffsetForVCr = pParams->dwXOffset[MHW_V_PLANE];
475 pCmd->DW4.YOffsetForVCr = pParams->dwYOffset[MHW_V_PLANE];
476 }
477
478 if (!pOsInterface->bPitchAndUVPatchingNeeded )
479 pCmd->DW3.YOffsetForUCb = pParams->psSurface->UPlaneOffset.iYOffset;
480
481 ResourceParams.presResource = &pParams->psSurface->OsResource;
482 ResourceParams.dwOffset =
483 pParams->psSurface->dwOffset + pParams->dwBaseAddrOffset[i];
484 ResourceParams.pdwCmd = &(pCmd->DW6.Value);
485 ResourceParams.dwLocationInCmd = 6;
486 ResourceParams.bIsWritable = pParams->bIsWritable;
487 ResourceParams.dwOffsetInSSH =
488 uiIndirectStateOffset +
489 pKernelState->dwSshOffset +
490 pKernelState->dwBindingTableSize +
491 (pParams->dwBindingTableOffset[i] * m_dwMaxSurfaceStateSize);
492 ResourceParams.HwCommandType = MOS_SURFACE_STATE_ADV;
493
494 MHW_MI_CHK_STATUS(m_pfnAddResourceToCmd(
495 pOsInterface,
496 pCmdBuffer,
497 &ResourceParams));
498 }
499 else // 1D, 2D Surface
500 {
501 mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD *pCmd =
502 (mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD*)pLocationOfSurfaceInSsh;
503
504 mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD CmdInit;
505 // Add additional defaults specific to media
506 CmdInit.DW0.SurfaceHorizontalAlignment = 1;
507 CmdInit.DW0.SurfaceVerticalAlignment = 1;
508 CmdInit.DW1.EnableUnormPathInColorPipe = CmdInit.ENABLE_UNORM_PATH_IN_COLOR_PIPE_UNNAMED0;
509 CmdInit.DW7.ShaderChannelSelectAlpha = CmdInit.SHADER_CHANNEL_SELECT_ALPHA_ALPHA;
510 CmdInit.DW7.ShaderChannelSelectBlue = CmdInit.SHADER_CHANNEL_SELECT_BLUE_BLUE;
511 CmdInit.DW7.ShaderChannelSelectGreen = CmdInit.SHADER_CHANNEL_SELECT_GREEN_GREEN;
512 CmdInit.DW7.ShaderChannelSelectRed = CmdInit.SHADER_CHANNEL_SELECT_RED_RED;
513 *pCmd = CmdInit;
514
515 MHW_MI_CHK_STATUS(Mhw_SurfaceFormatToType(
516 pParams->ForceSurfaceFormat[i],
517 pParams->psSurface,
518 &dwSurfaceType));
519
520 // Force surface type to be 2D for this case since its a requirement for the Gen11 HEVC Kernel
521 if (i == MHW_Y_PLANE && pParams->ForceSurfaceFormat[i] == MHW_GFX3DSTATE_SURFACEFORMAT_R32_UINT && pParams->dwSurfaceType == GFX3DSTATE_SURFACETYPE_2D)
522 dwSurfaceType = GFX3DSTATE_SURFACETYPE_2D;
523
524 pCmd->DW0.SurfaceType = dwSurfaceType;
525 pCmd->DW0.VerticalLineStride = pParams->bVertLineStride;
526 pCmd->DW0.VerticalLineStrideOffset = pParams->bVertLineStrideOffs;
527 pCmd->DW0.MediaBoundaryPixelMode = pParams->MediaBoundaryPixelMode;
528 pCmd->DW0.SurfaceFormat = pParams->ForceSurfaceFormat[i];
529
530 if (IS_Y_MAJOR_TILE_FORMAT(pParams->psSurface->TileType))
531 {
532 pCmd->DW0.TileMode = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::TILE_MODE_YMAJOR;
533 }
534 else if (pParams->psSurface->TileType == MOS_TILE_LINEAR)
535 {
536 pCmd->DW0.TileMode = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::TILE_MODE_LINEAR;
537 }
538 else if (pParams->psSurface->TileType == MOS_TILE_X)
539 {
540 pCmd->DW0.TileMode = mhw_state_heap_g11_X::RENDER_SURFACE_STATE_CMD::TILE_MODE_XMAJOR;
541 }
542
543 pCmd->DW1.MemoryObjectControlState = pParams->dwCacheabilityControl;
544
545 pCmd->DW2.Width = (pParams->dwWidthToUse[i] == 0) ?
546 pParams->psSurface->dwWidth : pParams->dwWidthToUse[i];
547 pCmd->DW2.Height = (pParams->dwHeightToUse[i] == 0) ?
548 pParams->psSurface->dwHeight : pParams->dwHeightToUse[i];
549 pCmd->DW3.SurfacePitch = (pParams->dwPitchToUse[i] == 0) ?
550 pParams->psSurface->dwPitch : pParams->dwPitchToUse[i];
551
552 if(pParams->psSurface->bCompressible)
553 {
554 MHW_MI_CHK_STATUS(pOsInterface->pfnGetMemoryCompressionMode(pOsInterface, &pParams->psSurface->OsResource, (PMOS_MEMCOMP_STATE) &pParams->psSurface->CompressionMode));
555
556 pCmd->DW7.MemoryCompressionEnable =
557 (pParams->psSurface->CompressionMode == MOS_MMC_DISABLED) ? 0 : 1;
558 pCmd->DW7.MemoryCompressionMode =
559 (pParams->psSurface->CompressionMode == MOS_MMC_VERTICAL) ? 1 : 0;
560 }
561
562 pCmd->DW3.SurfacePitch--; // both for 1D & 2D surface
563 pCmd->DW3.Depth = pParams->psSurface->dwDepth;
564
565 if (dwSurfaceType == GFX3DSTATE_SURFACETYPE_BUFFER)
566 {
567 if (pCmd->DW0.TileMode)
568 {
569 MHW_ASSERTMESSAGE("1D surfaces should not be tiled!");
570 eStatus = MOS_STATUS_INVALID_PARAMETER;
571 return eStatus;
572 }
573 }
574 else // 2D Surface
575 {
576 pCmd->DW2.Width--;
577 pCmd->DW2.Height--;
578 pCmd->DW3.Depth--;
579 pCmd->DW5.XOffset = pParams->dwXOffset[i] >> 2;
580 pCmd->DW5.YOffset = pParams->dwYOffset[i] >> 2;
581 pCmd->DW5.TiledResourceMode = Mhw_ConvertToTRMode(pParams->psSurface->TileType);
582
583 if(pOsInterface->bPitchAndUVPatchingNeeded)
584 {
585 pCmd->DW3.SurfacePitch = 0;
586 if(dwSurfaceType != GFX3DSTATE_SURFACETYPE_BUFFER)
587 {
588 MHW_RESOURCE_PARAMS ResourceParams;
589 MOS_ZeroMemory(&ResourceParams, sizeof(ResourceParams));
590 ResourceParams.presResource = &pParams->psSurface->OsResource;
591 ResourceParams.HwCommandType = MOS_SURFACE_STATE;
592 ResourceParams.patchType = MOS_PATCH_TYPE_PITCH;
593 ResourceParams.bIsWritable = pParams->bIsWritable;
594 ResourceParams.shiftDirection = 0;
595 ResourceParams.shiftAmount = 0;
596 ResourceParams.pdwCmd = &(pCmd->DW3.Value);
597 ResourceParams.dwOffsetInSSH = uiIndirectStateOffset +
598 pKernelState->dwSshOffset +
599 pKernelState->dwBindingTableSize +
600 (pParams->dwBindingTableOffset[i] * m_dwMaxSurfaceStateSize);
601 ResourceParams.dwLocationInCmd = 3 ; //DW3
602 MHW_MI_CHK_STATUS(m_pfnAddResourceToCmd(pOsInterface,
603 pCmdBuffer,
604 &ResourceParams));
605 }
606 }
607 }
608
609 ResourceParams.presResource = &pParams->psSurface->OsResource;
610 ResourceParams.dwOffset =
611 pParams->psSurface->dwOffset + pParams->dwBaseAddrOffset[i];
612
613 if(pOsInterface->bPitchAndUVPatchingNeeded)
614 {
615 if(i == MHW_Y_PLANE)
616 {
617 ResourceParams.patchType = MOS_PATCH_TYPE_BASE_ADDRESS; //Patch Y address
618 }
619 else
620 {
621 ResourceParams.patchType = MOS_PATCH_TYPE_UV_BASE_ADDRESS; //Patch UV Base address
622 ResourceParams.dwOffset = 0;
623 }
624 }
625 ResourceParams.pdwCmd = (pCmd->DW8_9.Value);
626 ResourceParams.dwLocationInCmd = 8;
627 ResourceParams.bIsWritable = pParams->bIsWritable;
628
629 ResourceParams.dwOffsetInSSH =
630 uiIndirectStateOffset +
631 pKernelState->dwSshOffset +
632 pKernelState->dwBindingTableSize +
633 (pParams->dwBindingTableOffset[i] * m_dwMaxSurfaceStateSize);
634 ResourceParams.HwCommandType = MOS_SURFACE_STATE;
635
636 MHW_MI_CHK_STATUS(m_pfnAddResourceToCmd(
637 pOsInterface,
638 pCmdBuffer,
639 &ResourceParams));
640 }
641 }
642
643 return eStatus;
644 }
645
SetSamplerState(void * pSampler,PMHW_SAMPLER_STATE_PARAM pParam)646 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::SetSamplerState(
647 void *pSampler,
648 PMHW_SAMPLER_STATE_PARAM pParam)
649 {
650 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
651
652 MHW_FUNCTION_ENTER;
653
654 MHW_MI_CHK_NULL(pParam);
655
656 if (pParam->pKernelState)
657 {
658 PMHW_KERNEL_STATE pKernelState;
659 uint32_t dwCurrSampler;
660 uint32_t dwNumSampler;
661
662 mhw_state_heap_g11_X::SAMPLER_STATE_CMD Cmd;
663 Cmd.DW0.MinModeFilter = Cmd.MIN_MODE_FILTER_LINEAR;
664 Cmd.DW0.MagModeFilter = Cmd.MAG_MODE_FILTER_LINEAR;
665 Cmd.DW0.TextureBorderColorMode = Cmd.TEXTURE_BORDER_COLOR_MODE_8BIT;
666 Cmd.DW1.ShadowFunction = Cmd.SHADOW_FUNCTION_PREFILTEROPNEVER;
667 Cmd.DW3.TczAddressControlMode = Cmd.TCZ_ADDRESS_CONTROL_MODE_CLAMP;
668 Cmd.DW3.TcyAddressControlMode = Cmd.TCY_ADDRESS_CONTROL_MODE_CLAMP;
669 Cmd.DW3.TcxAddressControlMode = Cmd.TCX_ADDRESS_CONTROL_MODE_CLAMP;
670 Cmd.DW3.RAddressMinFilterRoundingEnable = true;
671 Cmd.DW3.RAddressMagFilterRoundingEnable = true;
672 Cmd.DW3.VAddressMinFilterRoundingEnable = true;
673 Cmd.DW3.VAddressMagFilterRoundingEnable = true;
674 Cmd.DW3.UAddressMinFilterRoundingEnable = true;
675 Cmd.DW3.UAddressMagFilterRoundingEnable = true;
676 Cmd.DW0.SamplerDisable = false;
677
678 dwNumSampler = pParam->pKernelState->KernelParams.iSamplerCount;
679
680 for (dwCurrSampler = 0; dwCurrSampler < dwNumSampler; dwCurrSampler++)
681 {
682 if (pParam[dwCurrSampler].bInUse)
683 {
684 pKernelState = pParam[dwCurrSampler].pKernelState;
685
686 MHW_MI_CHK_NULL(pKernelState);
687
688 MHW_MI_CHK_STATUS(pKernelState->m_dshRegion.AddData(
689 &Cmd,
690 pKernelState->dwSamplerOffset + dwCurrSampler * Cmd.byteSize,
691 sizeof(Cmd)));
692 }
693 }
694 }
695 else if (pParam->bInUse)
696 {
697 MHW_MI_CHK_NULL(pSampler);
698
699 if (pParam->SamplerType == MHW_SAMPLER_TYPE_3D)
700 {
701 mhw_state_heap_g11_X::SAMPLER_STATE_CMD *pUnormSampler =
702 (mhw_state_heap_g11_X::SAMPLER_STATE_CMD*)pSampler;
703
704 mhw_state_heap_g11_X::SAMPLER_STATE_CMD UnormSamplerInit;
705
706 // Add additional defaults specific to media
707 UnormSamplerInit.DW0.MinModeFilter = UnormSamplerInit.MIN_MODE_FILTER_LINEAR;
708 UnormSamplerInit.DW0.MagModeFilter = UnormSamplerInit.MAG_MODE_FILTER_LINEAR;
709 UnormSamplerInit.DW0.TextureBorderColorMode = UnormSamplerInit.TEXTURE_BORDER_COLOR_MODE_8BIT;
710 UnormSamplerInit.DW0.SamplerDisable = false;
711 UnormSamplerInit.DW1.ShadowFunction = UnormSamplerInit.SHADOW_FUNCTION_PREFILTEROPNEVER;
712 UnormSamplerInit.DW3.TczAddressControlMode = UnormSamplerInit.TCZ_ADDRESS_CONTROL_MODE_CLAMP;
713 UnormSamplerInit.DW3.TcyAddressControlMode = UnormSamplerInit.TCY_ADDRESS_CONTROL_MODE_CLAMP;
714 UnormSamplerInit.DW3.TcxAddressControlMode = UnormSamplerInit.TCX_ADDRESS_CONTROL_MODE_CLAMP;
715 UnormSamplerInit.DW3.RAddressMinFilterRoundingEnable = true;
716 UnormSamplerInit.DW3.RAddressMagFilterRoundingEnable = true;
717 UnormSamplerInit.DW3.VAddressMinFilterRoundingEnable = true;
718 UnormSamplerInit.DW3.VAddressMagFilterRoundingEnable = true;
719 UnormSamplerInit.DW3.UAddressMinFilterRoundingEnable = true;
720 UnormSamplerInit.DW3.UAddressMagFilterRoundingEnable = true;
721
722 *pUnormSampler = UnormSamplerInit;
723
724 if (pParam->Unorm.SamplerFilterMode == MHW_SAMPLER_FILTER_NEAREST)
725 {
726 pUnormSampler->DW0.MinModeFilter = pUnormSampler->MIN_MODE_FILTER_NEAREST;
727 pUnormSampler->DW0.MagModeFilter = pUnormSampler->MAG_MODE_FILTER_NEAREST;
728 }
729 else if (pParam->Unorm.SamplerFilterMode == MHW_SAMPLER_FILTER_BILINEAR)
730 {
731 pUnormSampler->DW0.MinModeFilter = pUnormSampler->MIN_MODE_FILTER_LINEAR;
732 pUnormSampler->DW0.MagModeFilter = pUnormSampler->MAG_MODE_FILTER_LINEAR;
733 }
734 else
735 {
736 pUnormSampler->DW0.MinModeFilter = pParam->Unorm.MinFilter;
737 pUnormSampler->DW0.MagModeFilter = pParam->Unorm.MagFilter;
738 }
739
740 pUnormSampler->DW3.TcxAddressControlMode = pParam->Unorm.AddressU;
741 pUnormSampler->DW3.TcyAddressControlMode = pParam->Unorm.AddressV;
742 pUnormSampler->DW3.TczAddressControlMode = pParam->Unorm.AddressW;
743
744 if (pParam->Unorm.bBorderColorIsValid)
745 {
746 mhw_state_heap_g11_X::SAMPLER_INDIRECT_STATE_CMD *pUnormSamplerBorderColor =
747 (mhw_state_heap_g11_X::SAMPLER_INDIRECT_STATE_CMD*)pParam->Unorm.pIndirectState;
748
749 mhw_state_heap_g11_X::SAMPLER_INDIRECT_STATE_CMD UnormSamplerBorderColorInit;
750 *pUnormSamplerBorderColor = UnormSamplerBorderColorInit;
751
752 // Since the structure is a union between float, uint, and int, can use any to set the state DW
753 pUnormSamplerBorderColor->DW0.Obj0.BorderColorRed = pParam->Unorm.BorderColorRedU;
754 pUnormSamplerBorderColor->DW1.BorderColorGreen = pParam->Unorm.BorderColorGreenU;
755 pUnormSamplerBorderColor->DW2.BorderColorBlue = pParam->Unorm.BorderColorBlueU;
756 pUnormSamplerBorderColor->DW3.BorderColorAlpha = pParam->Unorm.BorderColorAlphaU;
757
758 pUnormSampler->DW2.IndirectStatePointer = pParam->Unorm.IndirectStateOffset >> MHW_SAMPLER_INDIRECT_SHIFT;
759 }
760
761 if (pParam->Unorm.bChromaKeyEnable)
762 {
763 pUnormSampler->DW1.ChromakeyEnable = true;
764 pUnormSampler->DW1.ChromakeyIndex = pParam->Unorm.ChromaKeyIndex;
765 pUnormSampler->DW1.ChromakeyMode = pParam->Unorm.ChromaKeyMode;
766 }
767 }
768
769 else if (pParam->SamplerType == MHW_SAMPLER_TYPE_AVS)
770 {
771 mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_CMD *pSamplerState8x8 =
772 (mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_CMD*)pSampler;
773
774 mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_CMD SamplerState8x8Init;
775 // Add additional defaults specific to media
776 SamplerState8x8Init.DW0.GainFactor = 0;
777 SamplerState8x8Init.DW0.R3XCoefficient = 0;
778 SamplerState8x8Init.DW0.R3CCoefficient = 0;
779 SamplerState8x8Init.DW2.GlobalNoiseEstimation = 0;
780 SamplerState8x8Init.DW2.R5XCoefficient = 0;
781 SamplerState8x8Init.DW2.R5CxCoefficient = 0;
782 SamplerState8x8Init.DW2.R5XCoefficient = 0;
783 SamplerState8x8Init.DW3.SinAlpha = 101;
784 SamplerState8x8Init.DW3.CosAlpha = 79;
785 SamplerState8x8Init.DW4.ShuffleOutputwritebackForSample8X8 = 1;
786 SamplerState8x8Init.DW5.DiamondAlpha = 100;
787 SamplerState8x8Init.DW5.DiamondDu = 0;
788 SamplerState8x8Init.DW7.InvMarginVyl = 3300;
789 SamplerState8x8Init.DW8.InvMarginVyu = 1600;
790 SamplerState8x8Init.DW10.S0L = MOS_BITFIELD_VALUE((uint32_t)-5, 11);
791 SamplerState8x8Init.DW10.YSlope2 = 31;
792 SamplerState8x8Init.DW12.YSlope1 = 31;
793 SamplerState8x8Init.DW14.S0U = 256;
794 SamplerState8x8Init.DW15.S1U = 113;
795 SamplerState8x8Init.DW15.S2U = MOS_BITFIELD_VALUE((uint32_t)-179, 11);
796
797 *pSamplerState8x8 = SamplerState8x8Init;
798
799 // Set STE Params
800 pSamplerState8x8->DW3.SkinToneTunedIefEnable = pParam->Avs.bEnableSTDE;
801 if (pParam->Avs.bEnableSTDE)
802 {
803 pSamplerState8x8->DW5.Skindetailfactor = pParam->Avs.bSkinDetailFactor;
804 pSamplerState8x8->DW4.VyStdEnable = true;
805 }
806
807 if (pParam->Avs.bEnableIEF && pParam->Avs.wIEFFactor > 0)
808 {
809 pSamplerState8x8->DW0.GainFactor = pParam->Avs.wIEFFactor;
810 pSamplerState8x8->DW0.R3XCoefficient = pParam->Avs.wR3xCoefficient;
811 pSamplerState8x8->DW0.R3CCoefficient = pParam->Avs.wR3cCoefficient;
812 pSamplerState8x8->DW2.R5XCoefficient = pParam->Avs.wR5xCoefficient;
813 pSamplerState8x8->DW2.R5CxCoefficient = pParam->Avs.wR5cxCoefficient;
814 pSamplerState8x8->DW2.R5CCoefficient = pParam->Avs.wR5cCoefficient;
815 }
816
817 if (pParam->Avs.bEnableAVS)
818 {
819 pSamplerState8x8->DW0.GainFactor = pParam->Avs.GainFactor;
820 pSamplerState8x8->DW0.StrongEdgeThreshold = pParam->Avs.StrongEdgeThr;
821 pSamplerState8x8->DW0.WeakEdgeThreshold = pParam->Avs.WeakEdgeThr;
822 pSamplerState8x8->DW2.GlobalNoiseEstimation = pParam->Avs.GlobalNoiseEstm;
823 pSamplerState8x8->DW2.StrongEdgeWeight = pParam->Avs.StrongEdgeWght;
824 pSamplerState8x8->DW2.RegularWeight = pParam->Avs.RegularWght;
825 pSamplerState8x8->DW2.NonEdgeWeight = pParam->Avs.NonEdgeWght;
826 pSamplerState8x8->DW3.Enable8TapFilter = pParam->Avs.EightTapAFEnable;
827
828 // Set 8-Tap Adaptive Filter
829 if (pParam->Avs.b8TapAdaptiveEnable)
830 {
831 pSamplerState8x8->DW3.Enable8TapFilter = MHW_SAMPLER_FILTER_8_TAP_ADATIVE;
832 }
833 else if (pParam->Avs.b8TapLumaForYUV444)
834 {
835 pSamplerState8x8->DW3.Enable8TapFilter = MHW_SAMPLER_FILTER_8_4_TAP;
836 }
837
838 //pSamplerState8x8->DW3.IEFBypass = pParam->pAVSParam.BypassIEF; This should be done through Kernel Gen8+
839 pSamplerState8x8->DW0.R3XCoefficient = pParam->Avs.wR3xCoefficient;
840 pSamplerState8x8->DW0.R3CCoefficient = pParam->Avs.wR3cCoefficient;
841 pSamplerState8x8->DW2.R5XCoefficient = pParam->Avs.wR5xCoefficient;
842 pSamplerState8x8->DW2.R5CxCoefficient = pParam->Avs.wR5cxCoefficient;
843 pSamplerState8x8->DW2.R5CCoefficient = pParam->Avs.wR5cCoefficient;
844
845 if (pParam->Avs.AdditionalOverridesUsed)
846 {
847 pSamplerState8x8->DW10.YSlope2 = pParam->Avs.YSlope2;
848 pSamplerState8x8->DW10.S0L = pParam->Avs.S0L;
849 pSamplerState8x8->DW12.YSlope1 = pParam->Avs.YSlope1;
850 pSamplerState8x8->DW15.S2U = pParam->Avs.S2U;
851 pSamplerState8x8->DW15.S1U = pParam->Avs.S1U;
852 }
853
854 // For HDC Direct Write, set Writeback same as Original Sample_8x8
855 if (pParam->Avs.bHdcDwEnable || pParam->Avs.bWritebackStandard)
856 {
857 pSamplerState8x8->DW4.ShuffleOutputwritebackForSample8X8 = 0;
858 }
859
860 if (pParam->Avs.pMhwSamplerAvsTableParam)
861 {
862 MHW_MI_CHK_STATUS(LoadSamplerAvsTable(pSamplerState8x8, pParam->Avs.pMhwSamplerAvsTableParam));
863 }
864 else
865 {
866 MHW_ASSERTMESSAGE("Invalid sampler params for avs 8x8 table \n");
867 return MOS_STATUS_INVALID_PARAMETER;
868 }
869 }
870 }
871 else
872 {
873 MHW_ASSERTMESSAGE("Invalid sampler type '%d'", pParam->SamplerType);
874 return MOS_STATUS_INVALID_PARAMETER;
875 }
876 }
877
878 return eStatus;
879 }
880
AddSamplerStateData(uint32_t samplerOffset,MemoryBlock * memoryBlock,PMHW_SAMPLER_STATE_PARAM pParam)881 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::AddSamplerStateData(
882 uint32_t samplerOffset,
883 MemoryBlock *memoryBlock,
884 PMHW_SAMPLER_STATE_PARAM pParam)
885 {
886
887 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
888
889 MHW_MI_CHK_NULL(memoryBlock);
890 MHW_MI_CHK_NULL(pParam);
891
892 if (pParam->SamplerType == MHW_SAMPLER_TYPE_3D)
893 {
894 mhw_state_heap_g11_X::SAMPLER_STATE_CMD unormSampler;
895 mhw_state_heap_g11_X::SAMPLER_INDIRECT_STATE_CMD indirectState;
896
897 pParam->Unorm.pIndirectState = &indirectState;
898
899 MHW_MI_CHK_STATUS(SetSamplerState(&unormSampler, pParam));
900
901 // Add indirect state to heap if necessary
902 if (pParam->Unorm.bBorderColorIsValid)
903 {
904 // adjust unormSampler->DW2.IndirectStatePointer
905 // to include memoryBlock's offset from base of state heap
906 unormSampler.DW2.IndirectStatePointer =
907 (pParam->Unorm.IndirectStateOffset + memoryBlock->GetOffset())
908 >> MHW_SAMPLER_INDIRECT_SHIFT;
909
910 MHW_MI_CHK_STATUS(memoryBlock->AddData(
911 &indirectState,
912 pParam->Unorm.IndirectStateOffset,
913 sizeof(mhw_state_heap_g11_X::SAMPLER_INDIRECT_STATE_CMD)));
914 }
915
916 // Add sampler state data to heap
917 MHW_MI_CHK_STATUS(memoryBlock->AddData(
918 &unormSampler,
919 samplerOffset,
920 sizeof(mhw_state_heap_g11_X::SAMPLER_STATE_CMD)));
921 }
922 else if (pParam->SamplerType == MHW_SAMPLER_TYPE_AVS)
923 {
924 mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_CMD samplerState8x8;
925
926 MHW_MI_CHK_STATUS(SetSamplerState(&samplerState8x8, pParam));
927
928 // Add sampler data to heap
929 MHW_MI_CHK_STATUS(memoryBlock->AddData(
930 &samplerState8x8,
931 samplerOffset,
932 sizeof(mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_CMD)));
933 }
934 else
935 {
936 MHW_ASSERTMESSAGE("Invalid sampler type '%d'", pParam->SamplerType);
937 eStatus = MOS_STATUS_INVALID_PARAMETER;
938 }
939
940 return eStatus;
941 }
942
InitSamplerStates(void * pSamplerStates,int32_t iSamplers)943 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::InitSamplerStates(
944 void *pSamplerStates,
945 int32_t iSamplers)
946 {
947 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
948
949 MHW_FUNCTION_ENTER;
950
951 MHW_MI_CHK_NULL(pSamplerStates);
952
953 mhw_state_heap_g11_X::SAMPLER_STATE_CMD SamplerStateInit;
954 // Add additional defaults specific to media
955 SamplerStateInit.DW0.MinModeFilter = SamplerStateInit.MIN_MODE_FILTER_LINEAR;
956 SamplerStateInit.DW0.MagModeFilter = SamplerStateInit.MAG_MODE_FILTER_LINEAR;
957 SamplerStateInit.DW0.TextureBorderColorMode = SamplerStateInit.TEXTURE_BORDER_COLOR_MODE_8BIT;
958 SamplerStateInit.DW0.SamplerDisable = true;
959 SamplerStateInit.DW1.ShadowFunction = SamplerStateInit.SHADOW_FUNCTION_PREFILTEROPNEVER;
960 SamplerStateInit.DW3.TczAddressControlMode = SamplerStateInit.TCZ_ADDRESS_CONTROL_MODE_CLAMP;
961 SamplerStateInit.DW3.TcyAddressControlMode = SamplerStateInit.TCY_ADDRESS_CONTROL_MODE_CLAMP;
962 SamplerStateInit.DW3.TcxAddressControlMode = SamplerStateInit.TCX_ADDRESS_CONTROL_MODE_CLAMP;
963 SamplerStateInit.DW3.RAddressMinFilterRoundingEnable = true;
964 SamplerStateInit.DW3.RAddressMagFilterRoundingEnable = true;
965 SamplerStateInit.DW3.VAddressMinFilterRoundingEnable = true;
966 SamplerStateInit.DW3.VAddressMagFilterRoundingEnable = true;
967 SamplerStateInit.DW3.UAddressMinFilterRoundingEnable = true;
968 SamplerStateInit.DW3.UAddressMagFilterRoundingEnable = true;
969
970 // Initialize Media Sampler States
971 uint8_t *pu8SamplerState = (uint8_t*)pSamplerStates;
972
973 for (; iSamplers > 0; iSamplers--)
974 {
975 MOS_SecureMemcpy(pu8SamplerState, SamplerStateInit.byteSize, &SamplerStateInit, SamplerStateInit.byteSize);
976 pu8SamplerState += SamplerStateInit.byteSize;
977 }
978
979 return eStatus;
980 }
981
982 //!
983 //! \brief Load Sampler 8X8 State Table for Gen9
984 //! \details Load Sampler 8x8 State Table
985 //! \param [in] void *pTable
986 //! Pointer to 8x8 table in GSH to load
987 //! \param [in] PMHW_SAMPLER_AVS_TABLE_PARAM pMhwSamplerAvsTableParam
988 //! Pointer to 8x8 sampler state params
989 //! \return MOS_STATUS
990 //!
LoadSamplerAvsTable(void * pvTable,PMHW_SAMPLER_AVS_TABLE_PARAM pMhwSamplerAvsTableParam)991 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::LoadSamplerAvsTable(
992 void *pvTable,
993 PMHW_SAMPLER_AVS_TABLE_PARAM pMhwSamplerAvsTableParam)
994 {
995 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
996
997 MHW_FUNCTION_ENTER;
998
999 MHW_MI_CHK_NULL(pvTable);
1000 MHW_MI_CHK_NULL(pMhwSamplerAvsTableParam);
1001
1002 mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_CMD *pSampler8x8Avs =
1003 (mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_CMD*)pvTable;
1004
1005 // DW0 ~ DW15 are for sampler state and programmed in other function, so no need to setup for it here.
1006
1007 uint32_t u32ConvolveTableNum =
1008 sizeof(pSampler8x8Avs->FilterCoefficient016) / sizeof(pSampler8x8Avs->FilterCoefficient016[0]);
1009
1010 // DW16 ~ DW151 setting for table coefficients (DW0 ~ DW7) * 17
1011 for (uint32_t u32CoeffTableIdx = 0; u32CoeffTableIdx < u32ConvolveTableNum; u32CoeffTableIdx++)
1012 {
1013 PMHW_AVS_COEFFICIENT_PARAM pCoeffParam = &pMhwSamplerAvsTableParam->paMhwAvsCoeffParam[u32CoeffTableIdx];
1014 mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD *pCoeffTable =
1015 &pSampler8x8Avs->FilterCoefficient016[u32CoeffTableIdx];
1016 MHW_MI_CHK_NULL(pCoeffParam);
1017 MHW_MI_CHK_NULL(pCoeffTable);
1018
1019 pCoeffTable->DW0.Table0XFilterCoefficientN0 = pCoeffParam->ZeroXFilterCoefficient[0];
1020 pCoeffTable->DW0.Table0YFilterCoefficientN0 = pCoeffParam->ZeroYFilterCoefficient[0];
1021 pCoeffTable->DW0.Table0XFilterCoefficientN1 = pCoeffParam->ZeroXFilterCoefficient[1];
1022 pCoeffTable->DW0.Table0YFilterCoefficientN1 = pCoeffParam->ZeroYFilterCoefficient[1];
1023
1024 pCoeffTable->DW1.Table0XFilterCoefficientN2 = pCoeffParam->ZeroXFilterCoefficient[2];
1025 pCoeffTable->DW1.Table0YFilterCoefficientN2 = pCoeffParam->ZeroYFilterCoefficient[2];
1026 pCoeffTable->DW1.Table0XFilterCoefficientN3 = pCoeffParam->ZeroXFilterCoefficient[3];
1027 pCoeffTable->DW1.Table0YFilterCoefficientN3 = pCoeffParam->ZeroYFilterCoefficient[3];
1028
1029 pCoeffTable->DW2.Table0XFilterCoefficientN4 = pCoeffParam->ZeroXFilterCoefficient[4];
1030 pCoeffTable->DW2.Table0YFilterCoefficientN4 = pCoeffParam->ZeroYFilterCoefficient[4];
1031 pCoeffTable->DW2.Table0XFilterCoefficientN5 = pCoeffParam->ZeroXFilterCoefficient[5];
1032 pCoeffTable->DW2.Table0YFilterCoefficientN5 = pCoeffParam->ZeroYFilterCoefficient[5];
1033
1034 pCoeffTable->DW3.Table0XFilterCoefficientN6 = pCoeffParam->ZeroXFilterCoefficient[6];
1035 pCoeffTable->DW3.Table0YFilterCoefficientN6 = pCoeffParam->ZeroYFilterCoefficient[6];
1036 pCoeffTable->DW3.Table0XFilterCoefficientN7 = pCoeffParam->ZeroXFilterCoefficient[7];
1037 pCoeffTable->DW3.Table0YFilterCoefficientN7 = pCoeffParam->ZeroYFilterCoefficient[7];
1038
1039 pCoeffTable->DW4.Table1XFilterCoefficientN2 = pCoeffParam->OneXFilterCoefficient[0];
1040 pCoeffTable->DW4.Table1XFilterCoefficientN3 = pCoeffParam->OneXFilterCoefficient[1];
1041 pCoeffTable->DW5.Table1XFilterCoefficientN4 = pCoeffParam->OneXFilterCoefficient[2];
1042 pCoeffTable->DW5.Table1XFilterCoefficientN5 = pCoeffParam->OneXFilterCoefficient[3];
1043
1044 pCoeffTable->DW6.Table1YFilterCoefficientN2 = pCoeffParam->OneYFilterCoefficient[0];
1045 pCoeffTable->DW6.Table1YFilterCoefficientN3 = pCoeffParam->OneYFilterCoefficient[1];
1046 pCoeffTable->DW7.Table1YFilterCoefficientN4 = pCoeffParam->OneYFilterCoefficient[2];
1047 pCoeffTable->DW7.Table1YFilterCoefficientN5 = pCoeffParam->OneYFilterCoefficient[3];
1048 }
1049
1050 // DW152 ~ DW153 setting for table control
1051 pSampler8x8Avs->DW152.TransitionAreaWith8Pixels = pMhwSamplerAvsTableParam->byteTransitionArea8Pixels; // 3-bits
1052 pSampler8x8Avs->DW152.TransitionAreaWith4Pixels = pMhwSamplerAvsTableParam->byteTransitionArea4Pixels; // 3-bits
1053 pSampler8x8Avs->DW152.MaxDerivative8Pixels = pMhwSamplerAvsTableParam->byteMaxDerivative8Pixels;
1054 pSampler8x8Avs->DW152.MaxDerivative4Pixels = pMhwSamplerAvsTableParam->byteMaxDerivative4Pixels;
1055 pSampler8x8Avs->DW152.DefaultSharpnessLevel = pMhwSamplerAvsTableParam->byteDefaultSharpnessLevel;
1056
1057 pSampler8x8Avs->DW153.RgbAdaptive = pMhwSamplerAvsTableParam->bEnableRGBAdaptive;
1058 pSampler8x8Avs->DW153.AdaptiveFilterForAllChannels = pMhwSamplerAvsTableParam->bAdaptiveFilterAllChannels;
1059 pSampler8x8Avs->DW153.BypassYAdaptiveFiltering = pMhwSamplerAvsTableParam->bBypassYAdaptiveFiltering;
1060 pSampler8x8Avs->DW153.BypassXAdaptiveFiltering = pMhwSamplerAvsTableParam->bBypassXAdaptiveFiltering;
1061
1062 u32ConvolveTableNum =
1063 sizeof(pSampler8x8Avs->FilterCoefficient1731) / sizeof(pSampler8x8Avs->FilterCoefficient1731[0]);
1064 // DW160 ~ DW279 setting for extra table coefficients (DW0 ~ DW7) * 15
1065 for (uint32_t u32CoeffTableIdx = 0; u32CoeffTableIdx < u32ConvolveTableNum; u32CoeffTableIdx++)
1066 {
1067 PMHW_AVS_COEFFICIENT_PARAM pCoeffParamExtra = &pMhwSamplerAvsTableParam->paMhwAvsCoeffParamExtra[u32CoeffTableIdx];
1068 mhw_state_heap_g11_X::SAMPLER_STATE_8x8_AVS_COEFFICIENTS_CMD *pCoeffTableExtra =
1069 &pSampler8x8Avs->FilterCoefficient1731[u32CoeffTableIdx];
1070 MHW_MI_CHK_NULL(pCoeffParamExtra);
1071 MHW_MI_CHK_NULL(pCoeffTableExtra);
1072
1073 pCoeffTableExtra->DW0.Table0XFilterCoefficientN0 = pCoeffParamExtra->ZeroXFilterCoefficient[0];
1074 pCoeffTableExtra->DW0.Table0YFilterCoefficientN0 = pCoeffParamExtra->ZeroYFilterCoefficient[0];
1075 pCoeffTableExtra->DW0.Table0XFilterCoefficientN1 = pCoeffParamExtra->ZeroXFilterCoefficient[1];
1076 pCoeffTableExtra->DW0.Table0YFilterCoefficientN1 = pCoeffParamExtra->ZeroYFilterCoefficient[1];
1077
1078 pCoeffTableExtra->DW1.Table0XFilterCoefficientN2 = pCoeffParamExtra->ZeroXFilterCoefficient[2];
1079 pCoeffTableExtra->DW1.Table0YFilterCoefficientN2 = pCoeffParamExtra->ZeroYFilterCoefficient[2];
1080 pCoeffTableExtra->DW1.Table0XFilterCoefficientN3 = pCoeffParamExtra->ZeroXFilterCoefficient[3];
1081 pCoeffTableExtra->DW1.Table0YFilterCoefficientN3 = pCoeffParamExtra->ZeroYFilterCoefficient[3];
1082
1083 pCoeffTableExtra->DW2.Table0XFilterCoefficientN4 = pCoeffParamExtra->ZeroXFilterCoefficient[4];
1084 pCoeffTableExtra->DW2.Table0YFilterCoefficientN4 = pCoeffParamExtra->ZeroYFilterCoefficient[4];
1085 pCoeffTableExtra->DW2.Table0XFilterCoefficientN5 = pCoeffParamExtra->ZeroXFilterCoefficient[5];
1086 pCoeffTableExtra->DW2.Table0YFilterCoefficientN5 = pCoeffParamExtra->ZeroYFilterCoefficient[5];
1087
1088 pCoeffTableExtra->DW3.Table0XFilterCoefficientN6 = pCoeffParamExtra->ZeroXFilterCoefficient[6];
1089 pCoeffTableExtra->DW3.Table0YFilterCoefficientN6 = pCoeffParamExtra->ZeroYFilterCoefficient[6];
1090 pCoeffTableExtra->DW3.Table0XFilterCoefficientN7 = pCoeffParamExtra->ZeroXFilterCoefficient[7];
1091 pCoeffTableExtra->DW3.Table0YFilterCoefficientN7 = pCoeffParamExtra->ZeroYFilterCoefficient[7];
1092
1093 pCoeffTableExtra->DW4.Table1XFilterCoefficientN2 = pCoeffParamExtra->OneXFilterCoefficient[0];
1094 pCoeffTableExtra->DW4.Table1XFilterCoefficientN3 = pCoeffParamExtra->OneXFilterCoefficient[1];
1095 pCoeffTableExtra->DW5.Table1XFilterCoefficientN4 = pCoeffParamExtra->OneXFilterCoefficient[2];
1096 pCoeffTableExtra->DW5.Table1XFilterCoefficientN5 = pCoeffParamExtra->OneXFilterCoefficient[3];
1097
1098 pCoeffTableExtra->DW6.Table1YFilterCoefficientN2 = pCoeffParamExtra->OneYFilterCoefficient[0];
1099 pCoeffTableExtra->DW6.Table1YFilterCoefficientN3 = pCoeffParamExtra->OneYFilterCoefficient[1];
1100 pCoeffTableExtra->DW7.Table1YFilterCoefficientN4 = pCoeffParamExtra->OneYFilterCoefficient[2];
1101 pCoeffTableExtra->DW7.Table1YFilterCoefficientN5 = pCoeffParamExtra->OneYFilterCoefficient[3];
1102 }
1103
1104 return eStatus;
1105 }
1106
SetInterfaceDescriptor(uint32_t dwNumIdsToSet,PMHW_INTERFACE_DESCRIPTOR_PARAMS pParams)1107 MOS_STATUS MHW_STATE_HEAP_INTERFACE_G11_X::SetInterfaceDescriptor(
1108 uint32_t dwNumIdsToSet,
1109 PMHW_INTERFACE_DESCRIPTOR_PARAMS pParams)
1110 {
1111 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
1112
1113 MHW_FUNCTION_ENTER;
1114
1115 MHW_MI_CHK_NULL(pParams);
1116 for (uint32_t dwCurrId = 0; dwCurrId < dwNumIdsToSet; dwCurrId++)
1117 {
1118 PMHW_KERNEL_STATE pKernelState = pParams[dwCurrId].pKernelState;
1119
1120 MHW_MI_CHK_NULL(pKernelState);
1121
1122 mhw_state_heap_g11_X::INTERFACE_DESCRIPTOR_DATA_CMD cmd;
1123
1124 cmd.DW0.KernelStartPointer =
1125 (pKernelState->m_ishRegion.GetOffset() +
1126 pKernelState->dwKernelBinaryOffset +
1127 pParams[dwCurrId].dwKernelStartOffset) >>
1128 MHW_KERNEL_OFFSET_SHIFT;
1129 cmd.DW3.SamplerStatePointer =
1130 (pKernelState->m_dshRegion.GetOffset() +
1131 pKernelState->dwSamplerOffset +
1132 pParams[dwCurrId].dwSamplerOffset) >>
1133 MHW_SAMPLER_SHIFT;
1134 cmd.DW3.SamplerCount = (pKernelState->KernelParams.iSamplerCount - 1) / 4 + 1;
1135 cmd.DW4.BindingTablePointer = MOS_ROUNDUP_SHIFT(
1136 (pKernelState->dwSshOffset +
1137 pParams[dwCurrId].dwBtOffset),
1138 MHW_BINDING_TABLE_ID_SHIFT);
1139 cmd.DW5.ConstantIndirectUrbEntryReadLength = MOS_ROUNDUP_SHIFT(
1140 pParams->pKernelState->KernelParams.iCurbeLength,
1141 MHW_CURBE_SHIFT);
1142 cmd.DW6.NumberOfThreadsInGpgpuThreadGroup = 1;
1143
1144 uint32_t idOffsetInIdSpace =
1145 pKernelState->dwIdOffset +
1146 (pParams[dwCurrId].dwIdIdx * m_wSizeOfCmdInterfaceDescriptorData);
1147 MHW_MI_CHK_STATUS(pKernelState->m_dshRegion.AddData(
1148 &cmd,
1149 idOffsetInIdSpace,
1150 cmd.byteSize));
1151 }
1152 return eStatus;
1153 }
1154