1 2 /* 3 * Copyright (c) 2024, Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 //! 25 //! \file mhw_sfc_hwcmd_xe2_hpm_next.h 26 //! \brief Auto-generated constructors for MHW and states. 27 //! \details This file may not be included outside of Xe2_HPM as other components 28 //! should use MHW interface to interact with MHW commands and states. 29 //! 30 31 #ifndef __MHW_SFC_HWCMD_XE2_HPM_NEXT_H__ 32 #define __MHW_SFC_HWCMD_XE2_HPM_NEXT_H__ 33 34 #pragma once 35 #pragma pack(1) 36 37 #include <cstdint> 38 #include <cstddef> 39 #include "media_class_trace.h" 40 41 namespace mhw 42 { 43 namespace sfc 44 { 45 namespace xe2_hpm_next 46 { 47 class Cmd 48 { 49 public: 50 // Internal Macros 51 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 52 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 53 #define __CODEGEN_OP_LENGTH_BIAS 2 54 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 55 GetOpLength(uint32_t uiLength)56 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 57 58 //! 59 //! \brief SFC_AVS_STATE 60 //! \details 61 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 62 //! each frame once the lock request is granted. 63 //! 64 struct SFC_AVS_STATE_CMD 65 { 66 union 67 { 68 struct 69 { 70 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 71 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 72 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 73 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 74 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 75 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 76 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 77 }; 78 uint32_t Value; 79 } DW0; 80 union 81 { 82 struct 83 { 84 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 85 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 86 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 87 uint32_t Reserved39 : __CODEGEN_BITFIELD( 7, 23) ; //!< Reserved 88 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< SHARPNESS_LEVEL 89 }; 90 uint32_t Value; 91 } DW1; 92 union 93 { 94 struct 95 { 96 uint32_t MaxDerivativePoint8 : __CODEGEN_BITFIELD( 0, 7) ; //!< MAX Derivative Point 8 97 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 98 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 99 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 100 }; 101 uint32_t Value; 102 } DW2; 103 union 104 { 105 struct 106 { 107 uint32_t InputVerticalSitingSpecifiesTheVerticalSitingOfTheInput : __CODEGEN_BITFIELD( 0, 3) ; //!< INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 108 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 109 uint32_t InputHorizontalSitingValueSpecifiesTheHorizontalSitingOfTheInput : __CODEGEN_BITFIELD( 8, 12) ; //!< Input Horizontal Siting Value - Specifies the horizontal siting of the input 110 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 111 }; 112 uint32_t Value; 113 } DW3; 114 115 //! \name Local enumerations 116 117 enum SUBOPCODEB 118 { 119 SUBOPCODEB_SFCAVSSTATE = 2, //!< No additional details 120 }; 121 122 enum SUBOPCODEA 123 { 124 SUBOPCODEA_COMMON = 0, //!< No additional details 125 }; 126 127 enum MEDIA_COMMAND_OPCODE 128 { 129 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 130 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Modegen 131 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 132 }; 133 134 enum PIPELINE 135 { 136 PIPELINE_MEDIA = 2, //!< No additional details 137 }; 138 139 enum COMMAND_TYPE 140 { 141 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 142 }; 143 144 //! \brief SHARPNESS_LEVEL 145 //! \details 146 //! When adaptive scaling is off, determines the balance between sharp and 147 //! smooth scalers. 148 enum SHARPNESS_LEVEL 149 { 150 SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 151 SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 152 }; 153 154 //! \brief INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 155 //! \details 156 //! For 444 and 422 format, vertical chroma siting should be programmed to 157 //! zero. 158 enum INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 159 { 160 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_0 = 0, //!< No additional details 161 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_18 = 1, //!< No additional details 162 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_28 = 2, //!< No additional details 163 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_38 = 3, //!< No additional details 164 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_48 = 4, //!< No additional details 165 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_58 = 5, //!< No additional details 166 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_68 = 6, //!< No additional details 167 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_78 = 7, //!< No additional details 168 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_88 = 8, //!< No additional details 169 }; 170 171 //! \name Initializations 172 173 //! \brief Explicit member initialization function 174 SFC_AVS_STATE_CMD(); 175 176 static const size_t dwSize = 4; 177 static const size_t byteSize = 16; 178 }; 179 180 //! 181 //! \brief SFC_IEF_STATE 182 //! \details 183 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 184 //! each frame once the lock request is granted. 185 //! 186 struct SFC_IEF_STATE_CMD 187 { 188 union 189 { 190 struct 191 { 192 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 193 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 194 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 195 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 196 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 197 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 198 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 199 }; 200 uint32_t Value; 201 } DW0; 202 union 203 { 204 struct 205 { 206 uint32_t GainFactor : __CODEGEN_BITFIELD( 0, 5) ; //!< GAIN_FACTOR 207 uint32_t WeakEdgeThreshold : __CODEGEN_BITFIELD( 6, 11) ; //!< WEAK_EDGE_THRESHOLD 208 uint32_t StrongEdgeThreshold : __CODEGEN_BITFIELD(12, 17) ; //!< STRONG_EDGE_THRESHOLD 209 uint32_t R3XCoefficient : __CODEGEN_BITFIELD(18, 22) ; //!< R3X_COEFFICIENT 210 uint32_t R3CCoefficient : __CODEGEN_BITFIELD(23, 27) ; //!< R3C_COEFFICIENT 211 uint32_t Reserved60 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 212 }; 213 uint32_t Value; 214 } DW1; 215 union 216 { 217 struct 218 { 219 uint32_t GlobalNoiseEstimation : __CODEGEN_BITFIELD( 0, 7) ; //!< GLOBAL_NOISE_ESTIMATION 220 uint32_t NonEdgeWeight : __CODEGEN_BITFIELD( 8, 10) ; //!< NON_EDGE_WEIGHT 221 uint32_t RegularWeight : __CODEGEN_BITFIELD(11, 13) ; //!< REGULAR_WEIGHT 222 uint32_t StrongEdgeWeight : __CODEGEN_BITFIELD(14, 16) ; //!< STRONG_EDGE_WEIGHT 223 uint32_t R5XCoefficient : __CODEGEN_BITFIELD(17, 21) ; //!< R5X_COEFFICIENT 224 uint32_t R5CxCoefficient : __CODEGEN_BITFIELD(22, 26) ; //!< R5CX_COEFFICIENT 225 uint32_t R5CCoefficient : __CODEGEN_BITFIELD(27, 31) ; //!< R5C_COEFFICIENT 226 }; 227 uint32_t Value; 228 } DW2; 229 union 230 { 231 struct 232 { 233 uint32_t StdSinAlpha : __CODEGEN_BITFIELD( 0, 7) ; //!< STD Sin(alpha) 234 uint32_t StdCosAlpha : __CODEGEN_BITFIELD( 8, 15) ; //!< STD Cos(alpha) 235 uint32_t SatMax : __CODEGEN_BITFIELD(16, 21) ; //!< SAT_MAX 236 uint32_t HueMax : __CODEGEN_BITFIELD(22, 27) ; //!< HUE_MAX 237 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 238 }; 239 uint32_t Value; 240 } DW3; 241 union 242 { 243 struct 244 { 245 uint32_t S3U : __CODEGEN_BITFIELD( 0, 10) ; //!< S3U 246 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 247 uint32_t DiamondMargin : __CODEGEN_BITFIELD(12, 14) ; //!< DIAMOND_MARGIN 248 uint32_t VyStdEnable : __CODEGEN_BITFIELD(15, 15) ; //!< VY_STD_Enable 249 uint32_t UMid : __CODEGEN_BITFIELD(16, 23) ; //!< U_MID 250 uint32_t VMid : __CODEGEN_BITFIELD(24, 31) ; //!< V_MID 251 }; 252 uint32_t Value; 253 } DW4; 254 union 255 { 256 struct 257 { 258 uint32_t DiamondDv : __CODEGEN_BITFIELD( 0, 6) ; //!< DIAMOND_DV 259 uint32_t DiamondTh : __CODEGEN_BITFIELD( 7, 12) ; //!< DIAMOND_TH 260 uint32_t DiamondAlpha : __CODEGEN_BITFIELD(13, 20) ; //!< Diamond_alpha 261 uint32_t HsMargin : __CODEGEN_BITFIELD(21, 23) ; //!< HS_MARGIN 262 uint32_t DiamondDu : __CODEGEN_BITFIELD(24, 30) ; //!< DIAMOND_DU 263 uint32_t SkinDetailFactor : __CODEGEN_BITFIELD(31, 31) ; //!< SKIN_DETAIL_FACTOR 264 }; 265 uint32_t Value; 266 } DW5; 267 union 268 { 269 struct 270 { 271 uint32_t YPoint1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y_POINT_1 272 uint32_t YPoint2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y_POINT_2 273 uint32_t YPoint3 : __CODEGEN_BITFIELD(16, 23) ; //!< Y_POINT_3 274 uint32_t YPoint4 : __CODEGEN_BITFIELD(24, 31) ; //!< Y_POINT_4 275 }; 276 uint32_t Value; 277 } DW6; 278 union 279 { 280 struct 281 { 282 uint32_t InvMarginVyl : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYL 283 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 284 }; 285 uint32_t Value; 286 } DW7; 287 union 288 { 289 struct 290 { 291 uint32_t InvMarginVyu : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYU 292 uint32_t P0L : __CODEGEN_BITFIELD(16, 23) ; //!< P0L 293 uint32_t P1L : __CODEGEN_BITFIELD(24, 31) ; //!< P1L 294 }; 295 uint32_t Value; 296 } DW8; 297 union 298 { 299 struct 300 { 301 uint32_t P2L : __CODEGEN_BITFIELD( 0, 7) ; //!< P2L 302 uint32_t P3L : __CODEGEN_BITFIELD( 8, 15) ; //!< P3L 303 uint32_t B0L : __CODEGEN_BITFIELD(16, 23) ; //!< B0L 304 uint32_t B1L : __CODEGEN_BITFIELD(24, 31) ; //!< B1L 305 }; 306 uint32_t Value; 307 } DW9; 308 union 309 { 310 struct 311 { 312 uint32_t B2L : __CODEGEN_BITFIELD( 0, 7) ; //!< B2L 313 uint32_t B3L : __CODEGEN_BITFIELD( 8, 15) ; //!< B3L 314 uint32_t S0L : __CODEGEN_BITFIELD(16, 26) ; //!< S0L 315 uint32_t YSlope2 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope_2 316 }; 317 uint32_t Value; 318 } DW10; 319 union 320 { 321 struct 322 { 323 uint32_t S1L : __CODEGEN_BITFIELD( 0, 10) ; //!< S1L 324 uint32_t S2L : __CODEGEN_BITFIELD(11, 21) ; //!< S2L 325 uint32_t Reserved374 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 326 }; 327 uint32_t Value; 328 } DW11; 329 union 330 { 331 struct 332 { 333 uint32_t S3L : __CODEGEN_BITFIELD( 0, 10) ; //!< S3L 334 uint32_t P0U : __CODEGEN_BITFIELD(11, 18) ; //!< P0U 335 uint32_t P1U : __CODEGEN_BITFIELD(19, 26) ; //!< P1U 336 uint32_t YSlope1 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope1 337 }; 338 uint32_t Value; 339 } DW12; 340 union 341 { 342 struct 343 { 344 uint32_t P2U : __CODEGEN_BITFIELD( 0, 7) ; //!< P2U 345 uint32_t P3U : __CODEGEN_BITFIELD( 8, 15) ; //!< P3U 346 uint32_t B0U : __CODEGEN_BITFIELD(16, 23) ; //!< B0U 347 uint32_t B1U : __CODEGEN_BITFIELD(24, 31) ; //!< B1U 348 }; 349 uint32_t Value; 350 } DW13; 351 union 352 { 353 struct 354 { 355 uint32_t B2U : __CODEGEN_BITFIELD( 0, 7) ; //!< B2U 356 uint32_t B3U : __CODEGEN_BITFIELD( 8, 15) ; //!< B3U 357 uint32_t S0U : __CODEGEN_BITFIELD(16, 26) ; //!< S0U 358 uint32_t Reserved475 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 359 }; 360 uint32_t Value; 361 } DW14; 362 union 363 { 364 struct 365 { 366 uint32_t S1U : __CODEGEN_BITFIELD( 0, 10) ; //!< S1U 367 uint32_t S2U : __CODEGEN_BITFIELD(11, 21) ; //!< S2U 368 uint32_t Reserved502 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 369 }; 370 uint32_t Value; 371 } DW15; 372 union 373 { 374 struct 375 { 376 uint32_t TransformEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Transform Enable 377 uint32_t YuvChannelSwap : __CODEGEN_BITFIELD( 1, 1) ; //!< YUV Channel Swap 378 uint32_t Reserved514 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 379 uint32_t C0 : __CODEGEN_BITFIELD( 3, 15) ; //!< C0 380 uint32_t C1 : __CODEGEN_BITFIELD(16, 28) ; //!< C1 381 uint32_t Reserved541 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 382 }; 383 uint32_t Value; 384 } DW16; 385 union 386 { 387 struct 388 { 389 uint32_t C2 : __CODEGEN_BITFIELD( 0, 12) ; //!< C2 390 uint32_t C3 : __CODEGEN_BITFIELD(13, 25) ; //!< C3 391 uint32_t Reserved570 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 392 }; 393 uint32_t Value; 394 } DW17; 395 union 396 { 397 struct 398 { 399 uint32_t C4 : __CODEGEN_BITFIELD( 0, 12) ; //!< C4 400 uint32_t C5 : __CODEGEN_BITFIELD(13, 25) ; //!< C5 401 uint32_t Reserved602 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 402 }; 403 uint32_t Value; 404 } DW18; 405 union 406 { 407 struct 408 { 409 uint32_t C6 : __CODEGEN_BITFIELD( 0, 12) ; //!< C6 410 uint32_t C7 : __CODEGEN_BITFIELD(13, 25) ; //!< C7 411 uint32_t Reserved634 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 412 }; 413 uint32_t Value; 414 } DW19; 415 union 416 { 417 struct 418 { 419 uint32_t C8 : __CODEGEN_BITFIELD( 0, 12) ; //!< C8 420 uint32_t Reserved653 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 421 }; 422 uint32_t Value; 423 } DW20; 424 union 425 { 426 struct 427 { 428 uint32_t OffsetIn1 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_1 429 uint32_t OffsetOut1 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_1 430 uint32_t Reserved694 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 431 }; 432 uint32_t Value; 433 } DW21; 434 union 435 { 436 struct 437 { 438 uint32_t OffsetIn2 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_2 439 uint32_t OffsetOut2 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_2 440 uint32_t Reserved726 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 441 }; 442 uint32_t Value; 443 } DW22; 444 union 445 { 446 struct 447 { 448 uint32_t OffsetIn3 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_3 449 uint32_t OffsetOut3 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_3 450 uint32_t Reserved758 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 451 }; 452 uint32_t Value; 453 } DW23; 454 455 //! \name Local enumerations 456 457 enum SUBOPCODEB 458 { 459 SUBOPCODEB_SFCIEFSTATE = 3, //!< No additional details 460 }; 461 462 enum SUBOPCODEA 463 { 464 SUBOPCODEA_COMMON = 0, //!< No additional details 465 }; 466 467 enum MEDIA_COMMAND_OPCODE 468 { 469 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 470 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 471 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 472 }; 473 474 enum PIPELINE 475 { 476 PIPELINE_MEDIA = 2, //!< No additional details 477 }; 478 479 enum COMMAND_TYPE 480 { 481 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 482 }; 483 484 //! \brief GAIN_FACTOR 485 //! \details 486 //! User control sharpening strength. 487 enum GAIN_FACTOR 488 { 489 GAIN_FACTOR_UNNAMED44 = 44, //!< No additional details 490 }; 491 492 //! \brief WEAK_EDGE_THRESHOLD 493 //! \details 494 //! If Strong Edge Threshold > EM > Weak Edge Threshold the basic VSA 495 //! detects a weak edge. 496 enum WEAK_EDGE_THRESHOLD 497 { 498 WEAK_EDGE_THRESHOLD_UNNAMED1 = 1, //!< No additional details 499 }; 500 501 //! \brief STRONG_EDGE_THRESHOLD 502 //! \details 503 //! If EM > Strong Edge Threshold the basic VSA detects a strong edge. 504 enum STRONG_EDGE_THRESHOLD 505 { 506 STRONG_EDGE_THRESHOLD_UNNAMED8 = 8, //!< No additional details 507 }; 508 509 //! \brief R3X_COEFFICIENT 510 //! \details 511 //! IEF smoothing coefficient, see IEF map. 512 enum R3X_COEFFICIENT 513 { 514 R3X_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 515 }; 516 517 //! \brief R3C_COEFFICIENT 518 //! \details 519 //! IEF smoothing coefficient, see IEF map. 520 enum R3C_COEFFICIENT 521 { 522 R3C_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 523 }; 524 525 //! \brief GLOBAL_NOISE_ESTIMATION 526 //! \details 527 //! Global noise estimation of previous frame. 528 enum GLOBAL_NOISE_ESTIMATION 529 { 530 GLOBAL_NOISE_ESTIMATION_UNNAMED255 = 255, //!< No additional details 531 }; 532 533 //! \brief NON_EDGE_WEIGHT 534 //! \details 535 //! . Sharpening strength when NO EDGE is found in basic VSA. 536 enum NON_EDGE_WEIGHT 537 { 538 NON_EDGE_WEIGHT_UNNAMED1 = 1, //!< No additional details 539 }; 540 541 //! \brief REGULAR_WEIGHT 542 //! \details 543 //! Sharpening strength when a WEAK edge is found in basic VSA. 544 enum REGULAR_WEIGHT 545 { 546 REGULAR_WEIGHT_UNNAMED2 = 2, //!< No additional details 547 }; 548 549 //! \brief STRONG_EDGE_WEIGHT 550 //! \details 551 //! Sharpening strength when a STRONG edge is found in basic VSA. 552 enum STRONG_EDGE_WEIGHT 553 { 554 STRONG_EDGE_WEIGHT_UNNAMED7 = 7, //!< No additional details 555 }; 556 557 //! \brief R5X_COEFFICIENT 558 //! \details 559 //! IEF smoothing coefficient, see IEF map. 560 enum R5X_COEFFICIENT 561 { 562 R5X_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 563 }; 564 565 //! \brief R5CX_COEFFICIENT 566 //! \details 567 //! IEF smoothing coefficient, see IEF map. 568 enum R5CX_COEFFICIENT 569 { 570 R5CX_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 571 }; 572 573 //! \brief R5C_COEFFICIENT 574 //! \details 575 //! IEF smoothing coefficient, see IEF map. 576 enum R5C_COEFFICIENT 577 { 578 R5C_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 579 }; 580 581 //! \brief SAT_MAX 582 //! \details 583 //! Rectangle half length. 584 enum SAT_MAX 585 { 586 SAT_MAX_UNNAMED31 = 31, //!< No additional details 587 }; 588 589 //! \brief HUE_MAX 590 //! \details 591 //! Rectangle half width. 592 enum HUE_MAX 593 { 594 HUE_MAX_UNNAMED14 = 14, //!< No additional details 595 }; 596 597 enum DIAMOND_MARGIN 598 { 599 DIAMOND_MARGIN_UNNAMED4 = 4, //!< No additional details 600 }; 601 602 //! \brief U_MID 603 //! \details 604 //! Rectangle middle-point U coordinate. 605 enum U_MID 606 { 607 U_MID_UNNAMED110 = 110, //!< No additional details 608 }; 609 610 //! \brief V_MID 611 //! \details 612 //! Rectangle middle-point V coordinate. 613 enum V_MID 614 { 615 V_MID_UNNAMED154 = 154, //!< No additional details 616 }; 617 618 //! \brief DIAMOND_DV 619 //! \details 620 //! Rhombus center shift in the hue-direction, relative to the rectangle 621 //! center. 622 enum DIAMOND_DV 623 { 624 DIAMOND_DV_UNNAMED0 = 0, //!< No additional details 625 }; 626 627 //! \brief DIAMOND_TH 628 //! \details 629 //! Half length of the rhombus axis in the sat-direction. 630 enum DIAMOND_TH 631 { 632 DIAMOND_TH_UNNAMED35 = 35, //!< No additional details 633 }; 634 635 //! \brief HS_MARGIN 636 //! \details 637 //! Defines rectangle margin. 638 enum HS_MARGIN 639 { 640 HS_MARGIN_UNNAMED3 = 3, //!< No additional details 641 }; 642 643 //! \brief DIAMOND_DU 644 //! \details 645 //! Rhombus center shift in the sat-direction, relative to the rectangle 646 //! center. 647 enum DIAMOND_DU 648 { 649 DIAMOND_DU_UNNAMED0 = 0, //!< No additional details 650 }; 651 652 //! \brief SKIN_DETAIL_FACTOR 653 //! \details 654 //! This flag bit is in operation only when one of the following conditions 655 //! exists:when the control bit SkinToneTunedIEF_Enable is 656 //! on. 657 //! When SkinDetailFactor is equal to 0, 658 //! sign(SkinDetailFactor) is equal to +1, and the content of the 659 //! detected skin tone area is detail revealed.</Li>When 660 //! SkinDetailFactor is equal to 1, sign(SkinDetailFactor) is 661 //! equal to -1, and the content of the detected skin tone area is not 662 //! detail revealed. 663 664 enum SKIN_DETAIL_FACTOR 665 { 666 SKIN_DETAIL_FACTOR_DETAILREVEALED = 0, //!< No additional details 667 SKIN_DETAIL_FACTOR_NOTDETAILREVEALED = 1, //!< No additional details 668 }; 669 670 //! \brief Y_POINT_1 671 //! \details 672 //! First point of the Y piecewise linear membership function. 673 enum Y_POINT_1 674 { 675 Y_POINT_1_UNNAMED46 = 46, //!< No additional details 676 }; 677 678 //! \brief Y_POINT_2 679 //! \details 680 //! Second point of the Y piecewise linear membership function. 681 enum Y_POINT_2 682 { 683 Y_POINT_2_UNNAMED47 = 47, //!< No additional details 684 }; 685 686 //! \brief Y_POINT_3 687 //! \details 688 //! Third point of the Y piecewise linear membership function. 689 enum Y_POINT_3 690 { 691 Y_POINT_3_UNNAMED254 = 254, //!< No additional details 692 }; 693 694 //! \brief Y_POINT_4 695 //! \details 696 //! Fourth point of the Y piecewise linear membership function. 697 enum Y_POINT_4 698 { 699 Y_POINT_4_UNNAMED255 = 255, //!< No additional details 700 }; 701 702 //! \brief P0L 703 //! \details 704 //! Y Point 0 of the lower part of the detection PWLF. 705 enum P0L 706 { 707 P0L_UNNAMED46 = 46, //!< No additional details 708 }; 709 710 //! \brief P1L 711 //! \details 712 //! Y Point 1 of the lower part of the detection PWLF. 713 enum P1L 714 { 715 P1L_UNNAMED216 = 216, //!< No additional details 716 }; 717 718 //! \brief P2L 719 //! \details 720 //! Y Point 2 of the lower part of the detection PWLF. 721 enum P2L 722 { 723 P2L_UNNAMED236 = 236, //!< No additional details 724 }; 725 726 //! \brief P3L 727 //! \details 728 //! Y Point 3 of the lower part of the detection PWLF. 729 enum P3L 730 { 731 P3L_UNNAMED236 = 236, //!< No additional details 732 }; 733 734 //! \brief B0L 735 //! \details 736 //! V Bias 0 of the lower part of the detection PWLF. 737 enum B0L 738 { 739 B0L_UNNAMED133 = 133, //!< No additional details 740 }; 741 742 //! \brief B1L 743 //! \details 744 //! V Bias 1 of the lower part of the detection PWLF. 745 enum B1L 746 { 747 B1L_UNNAMED130 = 130, //!< No additional details 748 }; 749 750 //! \brief B2L 751 //! \details 752 //! V Bias 2 of the lower part of the detection PWLF. 753 enum B2L 754 { 755 B2L_UNNAMED130 = 130, //!< No additional details 756 }; 757 758 //! \brief B3L 759 //! \details 760 //! V Bias 3 of the lower part of the detection PWLF. 761 enum B3L 762 { 763 B3L_UNNAMED130 = 130, //!< No additional details 764 }; 765 766 //! \brief P0U 767 //! \details 768 //! Y Point 0 of the upper part of the detection PWLF. 769 enum P0U 770 { 771 P0U_UNNAMED46 = 46, //!< No additional details 772 }; 773 774 //! \brief P1U 775 //! \details 776 //! Y Point 1 of the upper part of the detection PWLF. 777 enum P1U 778 { 779 P1U_UNNAMED66 = 66, //!< No additional details 780 }; 781 782 //! \brief P2U 783 //! \details 784 //! Y Point 2 of the upper part of the detection PWLF. 785 enum P2U 786 { 787 P2U_UNNAMED150 = 150, //!< No additional details 788 }; 789 790 //! \brief P3U 791 //! \details 792 //! Y Point 3 of the upper part of the detection PWLF. 793 enum P3U 794 { 795 P3U_UNNAMED236 = 236, //!< No additional details 796 }; 797 798 //! \brief B0U 799 //! \details 800 //! V Bias 0 of the upper part of the detection PWLF. 801 enum B0U 802 { 803 B0U_UNNAMED143 = 143, //!< No additional details 804 }; 805 806 //! \brief B1U 807 //! \details 808 //! V Bias 1 of the upper part of the detection PWLF. 809 enum B1U 810 { 811 B1U_UNNAMED163 = 163, //!< No additional details 812 }; 813 814 //! \brief B2U 815 //! \details 816 //! V Bias 2 of the upper part of the detection PWLF. 817 enum B2U 818 { 819 B2U_UNNAMED200 = 200, //!< No additional details 820 }; 821 822 //! \brief B3U 823 //! \details 824 //! V Bias 3 of the upper part of the detection PWLF. 825 enum B3U 826 { 827 B3U_UNNAMED140 = 140, //!< No additional details 828 }; 829 830 //! \brief C0 831 //! \details 832 //! Transform coefficient 833 enum C0 834 { 835 C0_UNNAMED1024 = 1024, //!< No additional details 836 }; 837 838 //! \brief C1 839 //! \details 840 //! Transform coefficient 841 enum C1 842 { 843 C1_UNNAMED0 = 0, //!< No additional details 844 }; 845 846 //! \brief C2 847 //! \details 848 //! Transform coefficient 849 enum C2 850 { 851 C2_UNNAMED0 = 0, //!< No additional details 852 }; 853 854 //! \brief C3 855 //! \details 856 //! Transform coefficient 857 enum C3 858 { 859 C3_UNNAMED0 = 0, //!< No additional details 860 }; 861 862 //! \brief C4 863 //! \details 864 //! Transform coefficient 865 enum C4 866 { 867 C4_UNNAMED1024 = 1024, //!< No additional details 868 }; 869 870 //! \brief C5 871 //! \details 872 //! Transform coefficient 873 enum C5 874 { 875 C5_UNNAMED0 = 0, //!< No additional details 876 }; 877 878 //! \brief C6 879 //! \details 880 //! Transform coefficient 881 enum C6 882 { 883 C6_UNNAMED0 = 0, //!< No additional details 884 }; 885 886 //! \brief C7 887 //! \details 888 //! Transform coefficient 889 enum C7 890 { 891 C7_UNNAMED0 = 0, //!< No additional details 892 }; 893 894 //! \brief C8 895 //! \details 896 //! Transform coefficient 897 enum C8 898 { 899 C8_UNNAMED1024 = 1024, //!< No additional details 900 }; 901 902 //! \brief OFFSET_IN_1 903 //! \details 904 //! Offset in for Y/R. 905 enum OFFSET_IN_1 906 { 907 OFFSET_IN_1_UNNAMED0 = 0, //!< No additional details 908 }; 909 910 //! \brief OFFSET_OUT_1 911 //! \details 912 //! Offset out for Y/R. 913 enum OFFSET_OUT_1 914 { 915 OFFSET_OUT_1_UNNAMED0 = 0, //!< No additional details 916 }; 917 918 //! \brief OFFSET_IN_2 919 //! \details 920 //! Offset in for U/G. 921 enum OFFSET_IN_2 922 { 923 OFFSET_IN_2_UNNAMED0 = 0, //!< No additional details 924 }; 925 926 //! \brief OFFSET_OUT_2 927 //! \details 928 //! Offset out for U/G. 929 enum OFFSET_OUT_2 930 { 931 OFFSET_OUT_2_UNNAMED0 = 0, //!< No additional details 932 }; 933 934 //! \brief OFFSET_IN_3 935 //! \details 936 //! Offset in for V/B. 937 enum OFFSET_IN_3 938 { 939 OFFSET_IN_3_UNNAMED0 = 0, //!< No additional details 940 }; 941 942 //! \brief OFFSET_OUT_3 943 //! \details 944 //! Offset out for V/B. 945 enum OFFSET_OUT_3 946 { 947 OFFSET_OUT_3_UNNAMED0 = 0, //!< No additional details 948 }; 949 950 //! \name Initializations 951 952 //! \brief Explicit member initialization function 953 SFC_IEF_STATE_CMD(); 954 955 static const size_t dwSize = 24; 956 static const size_t byteSize = 96; 957 }; 958 959 //! 960 //! \brief SFC_FRAME_START 961 //! \details 962 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 963 //! each frame once the lock request is granted. 964 //! 965 struct SFC_FRAME_START_CMD 966 { 967 union 968 { 969 struct 970 { 971 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 972 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 973 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 974 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 975 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 976 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 977 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 978 }; 979 uint32_t Value; 980 } DW0; 981 union 982 { 983 struct 984 { 985 uint32_t Reserved32 ; //!< Reserved 986 }; 987 uint32_t Value; 988 } DW1; 989 990 //! \name Local enumerations 991 992 enum SUBOPCODEB 993 { 994 SUBOPCODEB_SFCFRAMESTART = 4, //!< No additional details 995 }; 996 997 enum SUBOPCODEA 998 { 999 SUBOPCODEA_COMMON = 0, //!< No additional details 1000 }; 1001 1002 enum MEDIA_COMMAND_OPCODE 1003 { 1004 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 1005 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 1006 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 1007 }; 1008 1009 enum PIPELINE 1010 { 1011 PIPELINE_MEDIA = 2, //!< No additional details 1012 }; 1013 1014 enum COMMAND_TYPE 1015 { 1016 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1017 }; 1018 1019 //! \name Initializations 1020 1021 //! \brief Explicit member initialization function 1022 SFC_FRAME_START_CMD(); 1023 1024 static const size_t dwSize = 2; 1025 static const size_t byteSize = 8; 1026 }; 1027 1028 //! 1029 //! \brief SFC_LOCK 1030 //! \details 1031 //! This command is used for VD/VE box to communicate with SFC before the 1032 //! start of any SFC workload. VD/VE uses this command to make sure that it 1033 //! has the ownership of SFC pipe before running workload with SFC since SFC 1034 //! is shared between VD/VE on a frame level. For VD(MFX)-SFC workload, 1035 //! only decoder mode is allowed. Encoder mode cannot use SFC. 1036 //! 1037 //! For VD(HCP)-SFC workload, only decoder mode is allowed. Encoder mode 1038 //! cannot use SFC 1039 //! 1040 struct SFC_LOCK_CMD 1041 { 1042 union 1043 { 1044 struct 1045 { 1046 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1047 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1048 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1049 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1050 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1051 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1052 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1053 }; 1054 uint32_t Value; 1055 } DW0; 1056 union 1057 { 1058 struct 1059 { 1060 uint32_t VeSfcPipeSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< VE-SFC Pipe Select 1061 uint32_t PreScaledOutputSurfaceOutputEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Pre-Scaled Output Surface Output Enable 1062 uint32_t SfcDisable : __CODEGEN_BITFIELD( 2, 2) ; //!< SFC_disable 1063 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved 1064 }; 1065 uint32_t Value; 1066 } DW1; 1067 1068 //! \name Local enumerations 1069 1070 enum SUBOPCODEB 1071 { 1072 SUBOPCODEB_SFCLOCK = 0, //!< No additional details 1073 }; 1074 1075 enum SUBOPCODEA 1076 { 1077 SUBOPCODEA_COMMON = 0, //!< No additional details 1078 }; 1079 1080 enum MEDIA_COMMAND_OPCODE 1081 { 1082 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 1083 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode. For VD(MFX)+SFC mode, only decoder mode is allowed. Encoder mode cannot use SFC 1084 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 1085 }; 1086 1087 enum PIPELINE 1088 { 1089 PIPELINE_MEDIA = 2, //!< No additional details 1090 }; 1091 1092 enum COMMAND_TYPE 1093 { 1094 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1095 }; 1096 1097 //! \name Initializations 1098 1099 //! \brief Explicit member initialization function 1100 SFC_LOCK_CMD(); 1101 1102 static const size_t dwSize = 2; 1103 static const size_t byteSize = 8; 1104 }; 1105 1106 //! 1107 //! \brief SFC_STATE 1108 //! \details 1109 //! This command is sent from VDBOX/HCP/VEBOX to SFC pipeline at the start 1110 //! of each frame once the lock request is granted. 1111 //! 1112 struct SFC_STATE_CMD 1113 { 1114 union 1115 { 1116 struct 1117 { 1118 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1119 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1120 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1121 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1122 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1123 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1124 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1125 }; 1126 uint32_t Value; 1127 } DW0; 1128 union 1129 { 1130 struct 1131 { 1132 uint32_t SfcPipeMode : __CODEGEN_BITFIELD( 0, 3) ; //!< SFC_PIPE_MODE 1133 uint32_t SfcInputChromaSubSampling : __CODEGEN_BITFIELD( 4, 7) ; //!< SFC_INPUT_CHROMA_SUB_SAMPLING 1134 uint32_t VdVeInputOrderingMode : __CODEGEN_BITFIELD( 8, 10) ; //!< VDVE_INPUT_ORDERING_MODE 1135 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1136 uint32_t SfcEngineMode : __CODEGEN_BITFIELD(12, 13) ; //!< SFC_ENGINE_MODE 1137 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 17) ; //!< Reserved 1138 uint32_t InputFrameDataFormat : __CODEGEN_BITFIELD(18, 19) ; //!< INPUT_FRAME_DATA_FORMAT 1139 uint32_t OutputFrameDataFormat : __CODEGEN_BITFIELD(20, 21) ; //!< OUTPUT_FRAME_DATA_FORMAT 1140 uint32_t TopBottomField : __CODEGEN_BITFIELD(22, 22) ; //!< Top/Bottom field 1141 uint32_t TopBottomFieldFirst : __CODEGEN_BITFIELD(23, 23) ; //!< Top/Bottom field first 1142 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1143 }; 1144 uint32_t Value; 1145 } DW1; 1146 union 1147 { 1148 struct 1149 { 1150 uint32_t InputFrameResolutionWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Input Frame Resolution Width 1151 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1152 uint32_t InputFrameResolutionHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Input Frame Resolution Height 1153 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1154 }; 1155 uint32_t Value; 1156 } DW2; 1157 union 1158 { 1159 struct 1160 { 1161 uint32_t OutputSurfaceFormatType : __CODEGEN_BITFIELD( 0, 3) ; //!< OUTPUT_SURFACE_FORMAT_TYPE 1162 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 1163 uint32_t ChannelSwapEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< Channel_Swap Enable 1164 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1165 uint32_t OutputChromaDownsamplingCoSitingPositionVerticalDirection : __CODEGEN_BITFIELD( 8, 11) ; //!< OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 1166 uint32_t OutputChromaDownsamplingCoSitingPositionHorizontalDirection : __CODEGEN_BITFIELD(12, 15) ; //!< OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 1167 uint32_t InputColorSpace0Yuv1Rgb : __CODEGEN_BITFIELD(16, 16) ; //!< INPUT_COLOR_SPACE_0_YUV1_RGB 1168 uint32_t DitherEnable : __CODEGEN_BITFIELD(17, 17) ; //!< Dither Enable 1169 uint32_t OutputCompressionFormat : __CODEGEN_BITFIELD(18, 22) ; //!< OUTPUT_COMPRESSION_FORMAT 1170 uint32_t RgbPlanarMemoryFormatEnable : __CODEGEN_BITFIELD(23, 23) ; //!< RGB planar memory format enable 1171 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1172 }; 1173 uint32_t Value; 1174 } DW3; 1175 union 1176 { 1177 struct 1178 { 1179 uint32_t IefEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< IEF_ENABLE 1180 uint32_t SkinToneTunedIefEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Skin Tone Tuned IEF_Enable 1181 uint32_t Ief4SmoothEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< IEF4SMOOTH_ENABLE_ 1182 uint32_t Enable8TapForChromaChannelsFiltering : __CODEGEN_BITFIELD( 3, 3) ; //!< Enable 8 tap for Chroma channels filtering 1183 uint32_t AvsFilterMode : __CODEGEN_BITFIELD( 4, 5) ; //!< AVS_FILTER_MODE 1184 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 6, 6) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1185 uint32_t AvsScalingEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< AVS_SCALING_ENABLE 1186 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD( 8, 8) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 1187 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD( 9, 9) ; //!< BYPASS_X_ADAPTIVE_FILTERING 1188 uint32_t RgbAdaptive : __CODEGEN_BITFIELD(10, 10) ; //!< RGB Adaptive 1189 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1190 uint32_t ChromaUpsamplingEnable : __CODEGEN_BITFIELD(12, 12) ; //!< Chroma Upsampling Enable 1191 uint32_t MirrorType : __CODEGEN_BITFIELD(13, 13) ; //!< MIRROR_TYPE 1192 uint32_t MirrorMode : __CODEGEN_BITFIELD(14, 14) ; //!< MIRROR_MODE 1193 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1194 uint32_t RotationMode : __CODEGEN_BITFIELD(16, 17) ; //!< ROTATION_MODE 1195 uint32_t ColorFillEnable : __CODEGEN_BITFIELD(18, 18) ; //!< Color Fill Enable 1196 uint32_t CscEnable : __CODEGEN_BITFIELD(19, 19) ; //!< CSC Enable 1197 uint32_t Bitdepth : __CODEGEN_BITFIELD(20, 21) ; //!< BITDEPTH 1198 uint32_t TileType : __CODEGEN_BITFIELD(22, 22) ; //!< Tile Type 1199 uint32_t HistogramStreamout : __CODEGEN_BITFIELD(23, 23) ; //!< Histogram Streamout 1200 uint32_t Reserved152 : __CODEGEN_BITFIELD(24, 30) ; //!< Reserved 1201 uint32_t SfdChickenBit : __CODEGEN_BITFIELD(31, 31) ; //!< SFD chicken bit 1202 }; 1203 uint32_t Value; 1204 } DW4; 1205 union 1206 { 1207 struct 1208 { 1209 uint32_t SourceRegionWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Source Region Width 1210 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1211 uint32_t SourceRegionHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Source Region Height 1212 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1213 }; 1214 uint32_t Value; 1215 } DW5; 1216 union 1217 { 1218 struct 1219 { 1220 uint32_t SourceRegionHorizontalOffset : __CODEGEN_BITFIELD( 0, 13) ; //!< Source Region Horizontal Offset 1221 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1222 uint32_t SourceRegionVerticalOffset : __CODEGEN_BITFIELD(16, 29) ; //!< Source Region Vertical Offset 1223 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1224 }; 1225 uint32_t Value; 1226 } DW6; 1227 union 1228 { 1229 struct 1230 { 1231 uint32_t OutputFrameWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Output Frame Width 1232 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1233 uint32_t OutputFrameHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Output Frame Height 1234 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1235 }; 1236 uint32_t Value; 1237 } DW7; 1238 union 1239 { 1240 struct 1241 { 1242 uint32_t ScaledRegionSizeWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Scaled Region Size Width 1243 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1244 uint32_t ScaledRegionSizeHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Scaled Region Size Height 1245 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1246 }; 1247 uint32_t Value; 1248 } DW8; 1249 union 1250 { 1251 struct 1252 { 1253 uint32_t ScaledRegionHorizontalOffset : __CODEGEN_BITFIELD( 0, 14) ; //!< Scaled Region Horizontal Offset 1254 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1255 uint32_t ScaledRegionVerticalOffset : __CODEGEN_BITFIELD(16, 30) ; //!< Scaled Region Vertical Offset 1256 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1257 }; 1258 uint32_t Value; 1259 } DW9; 1260 union 1261 { 1262 struct 1263 { 1264 uint32_t GrayBarPixelUG : __CODEGEN_BITFIELD( 0, 9) ; //!< Gray Bar Pixel - U/G 1265 uint32_t Reserved330 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1266 uint32_t GrayBarPixelYR : __CODEGEN_BITFIELD(16, 25) ; //!< Gray Bar Pixel - Y/R 1267 uint32_t Reserved346 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1268 }; 1269 uint32_t Value; 1270 } DW10; 1271 union 1272 { 1273 struct 1274 { 1275 uint32_t GrayBarPixelA : __CODEGEN_BITFIELD( 0, 9) ; //!< Gray Bar Pixel - A 1276 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1277 uint32_t GrayBarPixelVB : __CODEGEN_BITFIELD(16, 25) ; //!< Gray Bar Pixel - V/B 1278 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1279 }; 1280 uint32_t Value; 1281 } DW11; 1282 union 1283 { 1284 struct 1285 { 1286 uint32_t UvDefaultValueForUChannelForMonoInputSupport : __CODEGEN_BITFIELD( 0, 9) ; //!< UV Default value for U channel (For Mono Input Support) 1287 uint32_t Reserved394 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1288 uint32_t UvDefaultValueForVChannelForMonoInputSupport : __CODEGEN_BITFIELD(16, 25) ; //!< UV Default value for V channel (For Mono Input Support) 1289 uint32_t Reserved410 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1290 }; 1291 uint32_t Value; 1292 } DW12; 1293 union 1294 { 1295 struct 1296 { 1297 uint32_t AlphaDefaultValue : __CODEGEN_BITFIELD( 0, 9) ; //!< Alpha Default Value 1298 uint32_t Reserved426 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 1299 }; 1300 uint32_t Value; 1301 } DW13; 1302 union 1303 { 1304 struct 1305 { 1306 uint32_t Reserved448 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1307 uint32_t ScalingFactorHeight : __CODEGEN_BITFIELD( 5, 27) ; //!< Scaling Factor Height 1308 uint32_t Reserved476 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1309 }; 1310 uint32_t Value; 1311 } DW14; 1312 union 1313 { 1314 struct 1315 { 1316 uint32_t Reserved480 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1317 uint32_t ScaleFactorWidth : __CODEGEN_BITFIELD( 5, 27) ; //!< Scale Factor Width 1318 uint32_t Reserved508 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1319 }; 1320 uint32_t Value; 1321 } DW15; 1322 union 1323 { 1324 struct 1325 { 1326 uint32_t Reserved512 ; //!< Reserved 1327 }; 1328 uint32_t Value; 1329 } DW16; 1330 union 1331 { 1332 struct 1333 { 1334 uint32_t Reserved544 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1335 uint32_t OutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Output Frame Surface Base Address 1336 }; 1337 uint32_t Value; 1338 } DW17; 1339 union 1340 { 1341 struct 1342 { 1343 uint32_t OutputFrameSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Frame Surface Base Address High 1344 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1345 }; 1346 uint32_t Value; 1347 } DW18; 1348 union 1349 { 1350 struct 1351 { 1352 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1353 uint32_t OutputFrameSurfaceBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Output Frame Surface Base Address - Index to Memory Object Control State (MOCS) Tables 1354 uint32_t OutputFrameSurfaceBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Output Frame Surface Base Address - Arbitration Priority Control 1355 uint32_t OutputFrameSurfaceBaseAddressCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Output Frame Surface Base Address - Compression Accumulation Buffer Enable 1356 uint32_t Reserved618 : __CODEGEN_BITFIELD(10, 11) ; //!< Reserved 1357 uint32_t OutputFrameSurfaceBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1358 uint32_t Reserved621 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1359 }; 1360 uint32_t Value; 1361 } DW19; 1362 union 1363 { 1364 struct 1365 { 1366 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1367 uint32_t AvsLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< AVS Line Buffer Surface Base Address 1368 }; 1369 uint32_t Value; 1370 } DW20; 1371 union 1372 { 1373 struct 1374 { 1375 uint32_t AvsLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< AVS Line Buffer Surface Base Address High 1376 uint32_t Reserved688 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1377 }; 1378 uint32_t Value; 1379 } DW21; 1380 union 1381 { 1382 struct 1383 { 1384 uint32_t Reserved704 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1385 uint32_t AvsLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< AVS Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1386 uint32_t AvsLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< AVS Line Buffer Base Address - Arbitration Priority Control 1387 uint32_t AvsLineBufferBaseAddressCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< AVS Line Buffer Base Address - Compression Accumulation Buffer Enable 1388 uint32_t AvsLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1389 uint32_t Reserved715 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1390 uint32_t AvsLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1391 uint32_t Reserved717 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1392 }; 1393 uint32_t Value; 1394 } DW22; 1395 union 1396 { 1397 struct 1398 { 1399 uint32_t Reserved736 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1400 uint32_t IefLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< IEF Line Buffer Surface Base Address 1401 }; 1402 uint32_t Value; 1403 } DW23; 1404 union 1405 { 1406 struct 1407 { 1408 uint32_t IefLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< IEF Line Buffer Surface Base Address High 1409 uint32_t Reserved784 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1410 }; 1411 uint32_t Value; 1412 } DW24; 1413 union 1414 { 1415 struct 1416 { 1417 uint32_t Reserved800 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1418 uint32_t IefLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< IEF Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1419 uint32_t IefLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< IEF Line Buffer Base Address - Arbitration Priority Control 1420 uint32_t IefLineBufferBaseAddressCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< IEF Line Buffer Base Address - Compression Accumulation Buffer Enable 1421 uint32_t IefLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1422 uint32_t Reserved811 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1423 uint32_t IefLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1424 uint32_t Reserved813 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1425 }; 1426 uint32_t Value; 1427 } DW25; 1428 union 1429 { 1430 struct 1431 { 1432 uint32_t Reserved832 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1433 uint32_t SfdLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< SFD Line Buffer Surface Base Address 1434 }; 1435 uint32_t Value; 1436 } DW26; 1437 union 1438 { 1439 struct 1440 { 1441 uint32_t SfdLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SFD Line Buffer Surface Base Address High 1442 uint32_t Reserved880 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1443 }; 1444 uint32_t Value; 1445 } DW27; 1446 union 1447 { 1448 struct 1449 { 1450 uint32_t Reserved896 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1451 uint32_t SfdLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SFD Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1452 uint32_t SfdLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SFD Line Buffer Base Address - Arbitration Priority Control 1453 uint32_t SfdLineBufferBaseAddressCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SFD Line Buffer Base Address - Compression Accumulation Buffer Enable 1454 uint32_t SfdLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1455 uint32_t Reserved907 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1456 uint32_t SfdLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1457 uint32_t Reserved909 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1458 }; 1459 uint32_t Value; 1460 } DW28; 1461 union 1462 { 1463 struct 1464 { 1465 uint32_t TiledMode : __CODEGEN_BITFIELD( 0, 1) ; //!< TILED_MODE 1466 uint32_t OutputSurfaceHalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Output Surface Half Pitch For Chroma 1467 uint32_t OutputSurfacePitch : __CODEGEN_BITFIELD( 3, 21) ; //!< Output Surface Pitch 1468 uint32_t Reserved950 : __CODEGEN_BITFIELD(22, 26) ; //!< Reserved 1469 uint32_t OutputSurfaceInterleaveChromaEnable : __CODEGEN_BITFIELD(27, 27) ; //!< Output Surface Interleave Chroma Enable 1470 uint32_t OutputSurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< Output Surface Format 1471 }; 1472 uint32_t Value; 1473 } DW29; 1474 union 1475 { 1476 struct 1477 { 1478 uint32_t OutputSurfaceYOffsetForU : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Surface Y Offset For U 1479 uint32_t OutputSurfaceXOffsetForU : __CODEGEN_BITFIELD(16, 31) ; //!< Output Surface X Offset For U 1480 }; 1481 uint32_t Value; 1482 } DW30; 1483 union 1484 { 1485 struct 1486 { 1487 uint32_t OutputSurfaceYOffsetForV : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Surface Y Offset For V 1488 uint32_t OutputSurfaceXOffsetForV : __CODEGEN_BITFIELD(16, 31) ; //!< Output Surface X Offset For V 1489 }; 1490 uint32_t Value; 1491 } DW31; 1492 union 1493 { 1494 struct 1495 { 1496 uint32_t Reserved1024 ; //!< Reserved 1497 }; 1498 uint32_t Value; 1499 } DW32; 1500 union 1501 { 1502 struct 1503 { 1504 uint32_t Av1TileColumnNumber : __CODEGEN_BITFIELD( 0, 7) ; //!< AV1 Tile column number 1505 uint32_t Av1TileRowNumber : __CODEGEN_BITFIELD( 8, 15) ; //!< AV1 Tile row number 1506 uint32_t Reserved1072 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1507 }; 1508 uint32_t Value; 1509 } DW33; 1510 union 1511 { 1512 struct 1513 { 1514 uint32_t Sourcestartx : __CODEGEN_BITFIELD( 0, 13) ; //!< SourceStartX 1515 uint32_t Reserved1102 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1516 uint32_t Sourceendx : __CODEGEN_BITFIELD(16, 29) ; //!< SourceEndX 1517 uint32_t Reserved1118 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1518 }; 1519 uint32_t Value; 1520 } DW34; 1521 union 1522 { 1523 struct 1524 { 1525 uint32_t Destinationstartx : __CODEGEN_BITFIELD( 0, 13) ; //!< DestinationStartX 1526 uint32_t Reserved1134 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1527 uint32_t Destinationendx : __CODEGEN_BITFIELD(16, 29) ; //!< DestinationEndX 1528 uint32_t Reserved1150 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1529 }; 1530 uint32_t Value; 1531 } DW35; 1532 union 1533 { 1534 struct 1535 { 1536 uint32_t Reserved1152 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1537 uint32_t Xphaseshift : __CODEGEN_BITFIELD( 5, 28) ; //!< Xphaseshift 1538 uint32_t Reserved1181 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1539 }; 1540 uint32_t Value; 1541 } DW36; 1542 union 1543 { 1544 struct 1545 { 1546 uint32_t Reserved1184 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1547 uint32_t Yphaseshift : __CODEGEN_BITFIELD( 5, 28) ; //!< Yphaseshift 1548 uint32_t Reserved1213 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1549 }; 1550 uint32_t Value; 1551 } DW37; 1552 union 1553 { 1554 struct 1555 { 1556 uint32_t Reserved1216 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1557 uint32_t AvsLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< AVS Line Tile Buffer Surface Base Address 1558 }; 1559 uint32_t Value; 1560 } DW38; 1561 union 1562 { 1563 struct 1564 { 1565 uint32_t AvsLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< AVS Line Tile Buffer Surface Base Address High 1566 uint32_t Reserved1264 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1567 }; 1568 uint32_t Value; 1569 } DW39; 1570 union 1571 { 1572 struct 1573 { 1574 uint32_t Reserved1280 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1575 uint32_t AvsLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< AVS Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1576 uint32_t AvsLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< AVS Line Tile Buffer Base Address - Arbitration Priority Control 1577 uint32_t AvsLineBufferBaseAddressCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< AVS Line Buffer Base Address - Compression Accumulation Buffer Enable 1578 uint32_t AvsLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1579 uint32_t Reserved1291 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1580 uint32_t AvsLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1581 uint32_t Reserved1293 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1582 }; 1583 uint32_t Value; 1584 } DW40; 1585 union 1586 { 1587 struct 1588 { 1589 uint32_t Reserved1312 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1590 uint32_t IefLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< IEF Line Tile Buffer Surface Base Address 1591 }; 1592 uint32_t Value; 1593 } DW41; 1594 union 1595 { 1596 struct 1597 { 1598 uint32_t IefLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< IEF Line Tile Buffer Surface Base Address High 1599 uint32_t Reserved1360 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1600 }; 1601 uint32_t Value; 1602 } DW42; 1603 union 1604 { 1605 struct 1606 { 1607 uint32_t Reserved1376 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1608 uint32_t IefLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< IEF Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1609 uint32_t IefLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< IEF Line Tile Buffer Base Address - Arbitration Priority Control 1610 uint32_t IefLineBufferBaseAddressCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< IEF Line Buffer Base Address - Compression Accumulation Buffer Enable 1611 uint32_t IefLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1612 uint32_t Reserved1387 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1613 uint32_t IefLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1614 uint32_t Reserved1389 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1615 }; 1616 uint32_t Value; 1617 } DW43; 1618 union 1619 { 1620 struct 1621 { 1622 uint32_t Reserved1408 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1623 uint32_t SfdLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< SFD Line Tile Buffer Surface Base Address 1624 }; 1625 uint32_t Value; 1626 } DW44; 1627 union 1628 { 1629 struct 1630 { 1631 uint32_t SfdLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SFD Line Tile Buffer Surface Base Address High 1632 uint32_t Reserved1456 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1633 }; 1634 uint32_t Value; 1635 } DW45; 1636 union 1637 { 1638 struct 1639 { 1640 uint32_t Reserved1472 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1641 uint32_t SfdLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SFD Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1642 uint32_t SfdLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SFD Line Tile Buffer Base Address - Arbitration Priority Control 1643 uint32_t SfdLineBufferBaseAddressCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SFD Line Buffer Base Address - Compression Accumulation Buffer Enable 1644 uint32_t SfdLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 1645 uint32_t Reserved1483 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1646 uint32_t SfdLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1647 uint32_t Reserved1485 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1648 }; 1649 uint32_t Value; 1650 } DW46; 1651 union 1652 { 1653 struct 1654 { 1655 uint32_t Reserved1504 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1656 uint32_t HistogramSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Histogram Surface Base Address 1657 }; 1658 uint32_t Value; 1659 } DW47; 1660 union 1661 { 1662 struct 1663 { 1664 uint32_t HistogramSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Histogram Surface Base Address High 1665 uint32_t Reserved1552 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1666 }; 1667 uint32_t Value; 1668 } DW48; 1669 union 1670 { 1671 struct 1672 { 1673 uint32_t Reserved1568 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1674 uint32_t HisgotramBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Hisgotram Base Address - Index to Memory Object Control State (MOCS) Tables 1675 uint32_t HistogramBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Histogram Base Address - Arbitration Priority Control 1676 uint32_t HistogramBaseAddressCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Histogram Base Address - Compression Accumulation Buffer Enable 1677 uint32_t HistogramBaseAddressMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 1678 uint32_t Reserved1579 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1679 uint32_t HistogramBaseAddressCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< HISTOGRAM_BASE_ADDRESS_CACHE_SELECT 1680 uint32_t Reserved1581 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 1681 }; 1682 uint32_t Value; 1683 } DW49; 1684 union 1685 { 1686 struct 1687 { 1688 uint32_t DitheringLutDelta12 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 12 1689 uint32_t Reserved1603 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1690 uint32_t DitheringLutDelta13 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 13 1691 uint32_t Reserved1611 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1692 uint32_t DitheringLutDelta14 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 14 1693 uint32_t Reserved1619 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1694 uint32_t DitheringLutDelta15 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 15 1695 uint32_t Reserved1627 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1696 }; 1697 uint32_t Value; 1698 } DW50; 1699 union 1700 { 1701 struct 1702 { 1703 uint32_t DitheringLutDelta8 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 8 1704 uint32_t Reserved1635 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1705 uint32_t DitheringLutDelta9 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 9 1706 uint32_t Reserved1643 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1707 uint32_t DitheringLutDelta10 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 10 1708 uint32_t Reserved1651 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1709 uint32_t DitheringLutDelta11 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 11 1710 uint32_t Reserved1659 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1711 }; 1712 uint32_t Value; 1713 } DW51; 1714 union 1715 { 1716 struct 1717 { 1718 uint32_t DitheringLutDelta4 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 4 1719 uint32_t Reserved1667 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1720 uint32_t DitheringLutDelta5 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 5 1721 uint32_t Reserved1675 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1722 uint32_t DitheringLutDelta6 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 6 1723 uint32_t Reserved1683 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1724 uint32_t DitheringLutDelta7 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 7 1725 uint32_t Reserved1691 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1726 }; 1727 uint32_t Value; 1728 } DW52; 1729 union 1730 { 1731 struct 1732 { 1733 uint32_t DitheringLutDelta0 : __CODEGEN_BITFIELD( 0, 2) ; //!< Dithering LUT delta 0 1734 uint32_t Reserved1699 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 1735 uint32_t DitheringLutDelta1 : __CODEGEN_BITFIELD( 8, 10) ; //!< Dithering LUT delta 1 1736 uint32_t Reserved1707 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1737 uint32_t DitheringLutDelta2 : __CODEGEN_BITFIELD(16, 18) ; //!< Dithering LUT delta 2 1738 uint32_t Reserved1715 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved 1739 uint32_t DitheringLutDelta3 : __CODEGEN_BITFIELD(24, 26) ; //!< Dithering LUT delta 3 1740 uint32_t Reserved1723 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1741 }; 1742 uint32_t Value; 1743 } DW53; 1744 union 1745 { 1746 struct 1747 { 1748 uint32_t BottomFieldVerticalScalingOffset : __CODEGEN_BITFIELD( 0, 23) ; //!< Bottom field vertical scaling offset 1749 uint32_t Reserved1752 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1750 }; 1751 uint32_t Value; 1752 } DW54; 1753 union 1754 { 1755 struct 1756 { 1757 uint32_t Reserved1760 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1758 uint32_t BottomFieldBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Bottom field base address 1759 }; 1760 uint32_t Value; 1761 } DW55; 1762 union 1763 { 1764 struct 1765 { 1766 uint32_t BottomFieldBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Bottom field base address high 1767 uint32_t Reserved1808 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1768 }; 1769 uint32_t Value; 1770 } DW56; 1771 union 1772 { 1773 struct 1774 { 1775 uint32_t Reserved1824 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1776 uint32_t BottomFieldSurfaceBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Bottom field Surface Base Address - Index to Memory Object Control State (MOCS) Tables 1777 uint32_t BottomFieldSurfaceBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Bottom field Surface Base Address - Arbitration Priority Control 1778 uint32_t BottomFieldBaseAddressCompressionAccumulationBufferEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Bottom field Base Address - Compression Accumulation Buffer Enable 1779 uint32_t BottomFiledSurfaceBaseAddressMemoryCompressionType : __CODEGEN_BITFIELD(10, 10) ; //!< BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 1780 uint32_t Reserved1835 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 1781 }; 1782 uint32_t Value; 1783 } DW57; 1784 union 1785 { 1786 struct 1787 { 1788 uint32_t BottomFieldSurfaceTileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< BOTTOM_FIELD_SURFACE_TILE_WALK 1789 uint32_t BottomFieldSurfaceTiled : __CODEGEN_BITFIELD( 1, 1) ; //!< BOTTOM_FIELD_SURFACE_TILED 1790 uint32_t BottomFieldSurfaceHalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Bottom field Surface Half Pitch For Chroma 1791 uint32_t BottomFieldSurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Bottom field Surface Pitch 1792 uint32_t Reserved1878 : __CODEGEN_BITFIELD(22, 26) ; //!< Reserved 1793 uint32_t BottomFieldSurfaceInterleaveChromaEnable : __CODEGEN_BITFIELD(27, 27) ; //!< Bottom field Surface Interleave Chroma Enable 1794 uint32_t Reserved1884 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1795 }; 1796 uint32_t Value; 1797 } DW58; 1798 union 1799 { 1800 struct 1801 { 1802 uint32_t BottomFieldSurfaceYOffsetForU : __CODEGEN_BITFIELD( 0, 15) ; //!< Bottom field Surface Y Offset For U 1803 uint32_t BottomFieldSurfaceXOffsetForU : __CODEGEN_BITFIELD(16, 31) ; //!< Bottom field Surface X Offset For U 1804 }; 1805 uint32_t Value; 1806 } DW59; 1807 union 1808 { 1809 struct 1810 { 1811 uint32_t BottomFieldSurfaceYOffsetForV : __CODEGEN_BITFIELD( 0, 15) ; //!< Bottom field Surface Y Offset For V 1812 uint32_t BottomFieldSurfaceXOffsetForV : __CODEGEN_BITFIELD(16, 31) ; //!< Bottom field Surface X Offset For V 1813 }; 1814 uint32_t Value; 1815 } DW60; 1816 //! \name Local enumerations 1817 1818 enum SUBOPCODEB 1819 { 1820 SUBOPCODEB_SFCSTATE = 1, //!< No additional details 1821 }; 1822 1823 enum SUBOPCODEA 1824 { 1825 SUBOPCODEA_COMMON = 0, //!< No additional details 1826 }; 1827 1828 enum MEDIA_COMMAND_OPCODE 1829 { 1830 MEDIA_COMMAND_OPCODE_MEDIAHCPSFCMODE = 9, //!< No additional details 1831 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< No additional details 1832 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 1833 }; 1834 1835 enum PIPELINE 1836 { 1837 PIPELINE_MEDIA = 2, //!< No additional details 1838 }; 1839 1840 enum COMMAND_TYPE 1841 { 1842 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1843 }; 1844 1845 //! \name Local enumerations 1846 1847 //! \brief SFC_PIPE_MODE 1848 //! \details 1849 //! Note: for SFC Pipe mode set to VE-to-SFC AVS mode. IECP pipeline mode 1850 //! MUST be enabled. However, each sub-IECP feature can be turned on/off 1851 //! independently. 1852 enum SFC_PIPE_MODE 1853 { 1854 SFC_PIPE_MODE_UNNAMED0 = 0, //!< VD-to-SFC AVS 1855 SFC_PIPE_MODE_UNNAMED1 = 1, //!< VE-to-SFC AVS + IEF + Rotation 1856 SFC_PIPE_MODE_UNNAMED2 = 2, //!< HCP-to-SFC AVS 1857 SFC_PIPE_MODE_UNNAMED3 = 3, //!< Reserved 1858 SFC_PIPE_MODE_UNNAMED4 = 4, //!< VE-to-SFC Integral Image 1859 SFC_PIPE_MODE_UNNAMED5 = 5, //!< VD/AV1-to_SFC AVS 1860 }; 1861 1862 //! \brief SFC_INPUT_CHROMA_SUB_SAMPLING 1863 //! \details 1864 //! This field shall be programmed according to video modes used in VDBOX. 1865 //! NOTE: SFC supports progressive input and output only (Interlaced/MBAFF 1866 //! is not supported).<table border="1"><tbody><tr><td>Video 1867 //! Mode</td><td>Surface Format</td><td>SFC Input Chroma 1868 //! Sub-Sampling</td><td>VD/VE Input Ordering Mode</td></tr><tr><td>VC1 w/o 1869 //! LF and w/o OS Note: VC1 LF applies for either ILDB</td><td>420 1870 //! (NV12)</td><td>1</td><td>0</td></tr><tr><td>VC1 w/ LF or w/ OS or w/ 1871 //! both Note: VC1 LF applies for either ILDB</td><td /><td>INVALID with 1872 //! SFC</td><td>INVALID with SFC</td></tr><tr><td>AVC w/o 1873 //! LF</td><td>Monochrome</td><td>0</td><td>0</td></tr><tr><td>AVC w/o 1874 //! LF</td><td>420 (NV12)</td><td>1</td><td>0</td></tr><tr><td>AVC with 1875 //! LF</td><td>Monochrome</td><td>0</td><td>1</td></tr><tr><td>AVC/VP8 with 1876 //! LF</td><td>420 (NV12)</td><td>1</td><td>1</td></tr><tr><td>VP8 w/o 1877 //! LF</td><td>420 (NV12)</td><td>1</td><td>4</td></tr><tr><td>JPEG (YUV 1878 //! Interleaved)</td><td>Monochrome</td><td>0</td><td>2</td></tr><tr><td>JPEG 1879 //! (YUV Interleaved)</td><td>420</td><td>1</td><td>3</td></tr><tr><td>JPEG 1880 //! (YUV 1881 //! Interleaved)</td><td>422H_2Y</td><td>2</td><td>2</td></tr><tr><td>JPEG 1882 //! (YUV 1883 //! Interleaved)</td><td>422H_4Y</td><td>2</td><td>3</td></tr><tr><td>JPEG 1884 //! (YUV 1885 //! Interleaved)</td><td>444</td><td>4</td><td>2</td></tr></tbody></table>This 1886 //! field shall be programmed according to Image enhancement modes used in 1887 //! VEBOX.<table border="1"><tbody><tr><td>VEBOX MODE</td><td>Surface 1888 //! Format</td><td>SFC Input Chroma Sub Sampling</td><td>VD/VE Input 1889 //! Ordering Mode</td></tr><tr><td>Legacy DN/DI/IECP 1890 //! features</td><td>Monochrome</td><td>0</td><td>0</td></tr><tr><td>Legacy 1891 //! DN/DI/IECP features</td><td>420 1892 //! (NV12)</td><td>1</td><td>0</td></tr><tr><td>Legacy DN/DI/IECP 1893 //! features</td><td>422H</td><td>2</td><td>0</td></tr><tr><td>Legacy 1894 //! DN/DI/IECP 1895 //! features</td><td>444</td><td>4</td><td>0</td></tr><tr><td>Capture/Camera 1896 //! pipe 1897 //! enabled(Demosaic)</td><td>Monochrome</td><td>0</td><td>1</td></tr><tr><td>Capture/Camera 1898 //! pipe enabled(Demosaic)</td><td>420 1899 //! (NV12)</td><td>1</td><td>1</td></tr><tr><td>Capture/Camera pipe 1900 //! enabled(Demosaic)</td><td>422H</td><td>2</td><td>1</td></tr><tr><td>Capture/Camera 1901 //! pipe 1902 //! enabled(Demosaic)</td><td>444</td><td>4</td><td>1</td></tr></tbody></table> 1903 enum SFC_INPUT_CHROMA_SUB_SAMPLING 1904 { 1905 SFC_INPUT_CHROMA_SUB_SAMPLING_400 = 0, //!< SFC to insert UV channels 1906 SFC_INPUT_CHROMA_SUB_SAMPLING_420 = 1, //!< No additional details 1907 SFC_INPUT_CHROMA_SUB_SAMPLING_422HORIZONATAL = 2, //!< VD: 2:1:1 1908 SFC_INPUT_CHROMA_SUB_SAMPLING_444PROGRESSIVEINTERLEAVED = 4, //!< No additional details 1909 SFC_INPUT_CHROMA_SUB_SAMPLING_411 = 5, //!< No additional details 1910 }; 1911 1912 //! \brief VDVE_INPUT_ORDERING_MODE 1913 //! \details 1914 //! VD mode: (SFC pipe mode set as "0") 1915 //! VE mode: (pipe mode set as "1 and 4") 1916 //! For 1917 //! values for each mode, please refer to the table below: 1918 enum VDVE_INPUT_ORDERING_MODE 1919 { 1920 VDVE_INPUT_ORDERING_MODE_UNNAMED0 = 0, //!< AV1 64x64 NonIBC (shifted) [Shifted by 8 pixels) 1921 VDVE_INPUT_ORDERING_MODE_UNNAMED1 = 1, //!< AV1 128x128 NonIBC (shifted)[Shifted by 8 pixels) 1922 VDVE_INPUT_ORDERING_MODE_UNNAMED2 = 2, //!< AV1 64x64 IBC (unshifted) 1923 VDVE_INPUT_ORDERING_MODE_UNNAMED3 = 3, //!< AV1 128x128 IBC (unshifted) 1924 VDVE_INPUT_ORDERING_MODE_UNNAMED4 = 4, //!< 16x16 block VP8 row-scan order - no shift 1925 }; 1926 1927 //! \brief SFC_ENGINE_MODE 1928 //! \details 1929 //! If SFC Pipe Mode is HCP-to-SFC and VE-to-SFC modes .Programmer need 1930 //! to ensure SFC Engine Mode bits programmed is the same as 1931 //! HCP_PIPE_MODE_SELECT command, Multi-Engine Modebits. For VE-SFC mode, 1932 //! this field has to be programmed according to the position of the 1933 //! split 1934 //! This Field is ignored for other SFC Pipe Mode. 1935 enum SFC_ENGINE_MODE 1936 { 1937 SFC_ENGINE_MODE_SINGLESFC = 0, //!< Single SFC mode. 1938 SFC_ENGINE_MODE_LEFTMOSTSFC = 1, //!< Left Most SFC in scalability/split-frame mode. 1939 SFC_ENGINE_MODE_RIGHTMOSTSFC = 2, //!< Right Most SFC in scalability/split-frame mode. 1940 SFC_ENGINE_MODE_MIDDLESFC = 3, //!< Middle SFC in scalability/split-frame mode. 1941 }; 1942 1943 //! \brief INPUT_FRAME_DATA_FORMAT 1944 //! \details 1945 //! This field specifies the format of Input frame according the 1946 //! following table. 1947 enum INPUT_FRAME_DATA_FORMAT 1948 { 1949 INPUT_FRAME_DATA_FORMAT_PROGRESSIVE = 0, //!< Progressive - Frame has progressive data.Valid in VD+SFC, VE+SFC and HCP+SFC engine modes. 1950 INPUT_FRAME_DATA_FORMAT_INTERLEAVED = 1, //!< Interleaved - Frame has top and bottom field data interleaved.Top and Bottom field are interleaved. Valid only in VE+SFC mode. 1951 INPUT_FRAME_DATA_FORMAT_FIELDMODE = 2, //!< Field mode - Frame has interlaced data where top field and bottom field are processed a separate frame.Valid in VD+SFC, VE+SFC and HCP+SFC engine modes. 1952 }; 1953 1954 //! \brief OUTPUT_FRAME_DATA_FORMAT 1955 //! \details 1956 //! This field specifies the format of Output Frame according the 1957 //! following table. 1958 enum OUTPUT_FRAME_DATA_FORMAT 1959 { 1960 OUTPUT_FRAME_DATA_FORMAT_PROGRESSIVE = 0, //!< Progressive - Frame has progressive data. 1961 OUTPUT_FRAME_DATA_FORMAT_INTERLEAVED = 1, //!< Interleaved - Frame has top and bottom field data interleaved. 1962 OUTPUT_FRAME_DATA_FORMAT_FIELDMODE = 2, //!< Field mode - Frame has interlaced data where top field and bottom field are processed as a separate frame. 1963 }; 1964 1965 //! \brief OUTPUT_SURFACE_FORMAT_TYPE 1966 //! \details 1967 //! SFC output surface format type. 1968 enum OUTPUT_SURFACE_FORMAT_TYPE 1969 { 1970 OUTPUT_SURFACE_FORMAT_TYPE_AYUV = 0, //!< AYUV 4:4:4 (8:8:8:8 MSB-A:Y:U:V) 1971 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R8 = 1, //!< RGBA8 4:4:4:4 (8:8:8:8 MSB-A:B:G:R) 1972 OUTPUT_SURFACE_FORMAT_TYPE_A2R10G10B10 = 2, //!< RGBA10 10:10:10:2 (2:10:10:10 MSB-A:R:G:B) 1973 OUTPUT_SURFACE_FORMAT_TYPE_R5G6B5 = 3, //!< RGB 5:6:5 (5:6:5 MSB-R:G:B) 1974 OUTPUT_SURFACE_FORMAT_TYPE_NV12 = 4, //!< Planar NV12 4:2:0 8-bit 1975 OUTPUT_SURFACE_FORMAT_TYPE_YUYV = 5, //!< Packed YUYV 4:2:2 8-bit 1976 OUTPUT_SURFACE_FORMAT_TYPE_UYVY = 6, //!< Packed UYVY 4:2:2 8-bit 1977 OUTPUT_SURFACE_FORMAT_TYPE_INTEGRAL_32 = 7, //!< Packed integral Image 32-bit 1978 OUTPUT_SURFACE_FORMAT_TYPE_INTEGRAL_64 = 8, //!< Packed integral Image 64-bit 1979 OUTPUT_SURFACE_FORMAT_TYPE_P016 = 9, //!< P016 format 1980 OUTPUT_SURFACE_FORMAT_TYPE_Y216 = 10, //!< Y210 / Y216 FormatBitDepth = 0 => Y210BitDepth = 1 => Y216 1981 OUTPUT_SURFACE_FORMAT_TYPE_Y416 = 11, //!< Y410 / Y416 FormatBitDepth = 0 => Y410BitDepth = 1 => Y416 1982 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R83 = 13, //!< Y8_NORM 1983 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R84 = 14, //!< Y16_NORM 1984 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R85 = 15, //!< R16G16B16A16 1985 }; 1986 1987 //! \brief OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 1988 //! \details 1989 //! This field specifies the fractional position of the bilinear filter for 1990 //! chroma downsampling. In the Y-axis. 1991 enum OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 1992 { 1993 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_08_LEFTFULLPIXEL = 0, //!< 0 (fraction_in_integer) 1994 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_18 = 1, //!< 1 (fraction_in_integer) 1995 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_14_28 = 2, //!< 2 (fraction_in_integer) 1996 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_38 = 3, //!< 3 (fraction_in_integer) 1997 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_12_48 = 4, //!< 4 (fraction_in_integer) 1998 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_58 = 5, //!< 5 (fraction_in_integer) 1999 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_34_68 = 6, //!< 6 (fraction_in_integer) 2000 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_78 = 7, //!< 7 (fraction_in_integer) 2001 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_88 = 8, //!< No additional details 2002 }; 2003 2004 //! \brief OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 2005 //! \details 2006 //! This field specifies the fractional position of the bilinear filter for 2007 //! chroma downsampling. In the X-axis. 2008 enum OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 2009 { 2010 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_08_LEFTFULLPIXEL = 0, //!< 0 (fraction_in_integer) 2011 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_18 = 1, //!< 1 (fraction_in_integer) 2012 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_14_28 = 2, //!< 2 (fraction_in_integer) 2013 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_38 = 3, //!< 3 (fraction_in_integer) 2014 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_12_48 = 4, //!< 4 (fraction_in_integer) 2015 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_58 = 5, //!< 5 (fraction_in_integer) 2016 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_34_68 = 6, //!< 6 (fraction_in_integer) 2017 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_78 = 7, //!< 7 (fraction_in_integer) 2018 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_88 = 8, //!< No additional details 2019 }; 2020 2021 //! \brief INPUT_COLOR_SPACE_0_YUV1_RGB 2022 //! \details 2023 //! THis specifies the color space of the input format. RGB is valid only 2024 //! with the VE-SFC mode. 2025 enum INPUT_COLOR_SPACE_0_YUV1_RGB 2026 { 2027 INPUT_COLOR_SPACE_0_YUV1_RGB_YUVCOLORSPACE = 0, //!< No additional details 2028 INPUT_COLOR_SPACE_0_YUV1_RGB_RGBCOLORSPACE = 1, //!< No additional details 2029 }; 2030 2031 //! \brief OUTPUT_COMPRESSION_FORMAT 2032 //! \details 2033 //! Specifies the 5-bit compression format. 2034 enum OUTPUT_COMPRESSION_FORMAT 2035 { 2036 OUTPUT_COMPRESSION_FORMAT_CMFR8 = 0, //!< Single 8bit channel format 2037 OUTPUT_COMPRESSION_FORMAT_CMFR8G8 = 1, //!< Two 8bit channel format 2038 OUTPUT_COMPRESSION_FORMAT_CMFR8G8B8A8 = 2, //!< Four 8bit channel format 2039 OUTPUT_COMPRESSION_FORMAT_CMFR10G10B10A2 = 3, //!< Three 10bit channels and One 2bit channel 2040 OUTPUT_COMPRESSION_FORMAT_CMFR11G11B10 = 4, //!< Two 11bit channels and One 10bit channel 2041 OUTPUT_COMPRESSION_FORMAT_CMFR16 = 5, //!< Single 16bit channel format 2042 OUTPUT_COMPRESSION_FORMAT_CMFR16G16 = 6, //!< Two 16bit channel format 2043 OUTPUT_COMPRESSION_FORMAT_CMFR16G16B16A16 = 7, //!< Four 16bit channels 2044 OUTPUT_COMPRESSION_FORMAT_CMFR32 = 8, //!< Single 32bit channel 2045 OUTPUT_COMPRESSION_FORMAT_CMFR32G32 = 9, //!< Two 32bit channels 2046 OUTPUT_COMPRESSION_FORMAT_CMFR32G32B32A32 = 10, //!< Four 32bit channels 2047 OUTPUT_COMPRESSION_FORMAT_CMFY16U16Y16V16 = 11, //!< Packed YUV 16/12/10 bit per channel 2048 OUTPUT_COMPRESSION_FORMAT_CMFML8 = 15, //!< Machine Learning format / Generic data 2049 }; 2050 2051 //! \brief IEF_ENABLE 2052 //! \details 2053 //! Restriction : For Integral Image Mode and VD Mode, this field is 2054 //! Reserved and MBZ. 2055 enum IEF_ENABLE 2056 { 2057 IEF_ENABLE_DISABLE = 0, //!< IEF Filter is Disabled 2058 IEF_ENABLE_ENABLE = 1, //!< IEF Filter is Enabled 2059 }; 2060 2061 //! \brief IEF4SMOOTH_ENABLE_ 2062 //! \details 2063 //! Restriction : For Integral Image Mode, this field is Reserved and MBZ. 2064 enum IEF4SMOOTH_ENABLE_ 2065 { 2066 IEF4SMOOTH_ENABLE_UNNAMED0 = 0, //!< IEF is operating as a content adaptive detail filter based on 5x5 region. 2067 IEF4SMOOTH_ENABLE_UNNAMED1 = 1, //!< IEF is operating as a content adaptive smooth filter based on 3x3 region 2068 }; 2069 2070 //! \brief AVS_FILTER_MODE 2071 //! \details 2072 //! In VD-to-SFC mode, value of 1 is not allowed. 2073 enum AVS_FILTER_MODE 2074 { 2075 AVS_FILTER_MODE_5X5POLY_PHASEFILTERBILINEAR_ADAPTIVE = 0, //!< No additional details 2076 AVS_FILTER_MODE_8X8POLY_PHASEFILTERBILINEAR_ADAPTIVE = 1, //!< No additional details 2077 AVS_FILTER_MODE_BILINEARFILTERONLY = 2, //!< No additional details 2078 }; 2079 2080 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2081 //! \details 2082 //! The field can be enabled if 8-tap Adaptive filter mode is on. Else it 2083 //! should be disabled. 2084 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2085 { 2086 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISABLEADAPTIVEFILTERONUVRBCHANNELS = 0, //!< No additional details 2087 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLEADAPTIVEFILTERONUVRBCHANNELS = 1, //!< 8-tap Adaptive Filter Mode is on 2088 }; 2089 2090 enum AVS_SCALING_ENABLE 2091 { 2092 AVS_SCALING_ENABLE_DISABLE = 0, //!< The scaling factor is ignored and a scaling ratio of 1:1 is assumed. 2093 AVS_SCALING_ENABLE_ENABLE = 1, //!< No additional details 2094 }; 2095 2096 enum BYPASS_Y_ADAPTIVE_FILTERING 2097 { 2098 BYPASS_Y_ADAPTIVE_FILTERING_ENABLEYADAPTIVEFILTERING = 0, //!< No additional details 2099 BYPASS_Y_ADAPTIVE_FILTERING_DISABLEYADAPTIVEFILTERING = 1, //!< The Y direction will use Default Sharpness Level to blend between the smooth and sharp filters rather than the calculated value. 2100 }; 2101 2102 enum BYPASS_X_ADAPTIVE_FILTERING 2103 { 2104 BYPASS_X_ADAPTIVE_FILTERING_ENABLEXADAPTIVEFILTERING = 0, //!< No additional details 2105 BYPASS_X_ADAPTIVE_FILTERING_DISABLEXADAPTIVEFILTERING = 1, //!< The X direction will use Default Sharpness Level to blend between the smooth and sharp filters rather than the calculated value. 2106 }; 2107 2108 //! \brief MIRROR_TYPE 2109 //! \details 2110 //! 0 : Horizontal flip 1 : Vertical flip 2111 enum MIRROR_TYPE 2112 { 2113 MIRROR_TYPE_HORIZONTALFLIP = 0, //!< No additional details 2114 MIRROR_TYPE_VERTICALFLIP = 1, //!< No additional details 2115 }; 2116 2117 //! \brief MIRROR_MODE 2118 //! \details 2119 //! 0 : Mirror Mode disabled 1 : Mirror Mode enabled 2120 enum MIRROR_MODE 2121 { 2122 MIRROR_MODE_MIRRORMODEDISABLED = 0, //!< No additional details 2123 MIRROR_MODE_MIRRORMODEENABLED = 1, //!< No additional details 2124 }; 2125 2126 //! \brief ROTATION_MODE 2127 //! \details 2128 //! SFC rotation (90, 180 and 270) should be set only on VEBox input mode 2129 //! and SFC output set to TileY.Restriction: For Integral Image 2130 //! Mode, this field is Reserved and MBZ. 2131 //! For VDBox Mode, this field 2132 //! is Reserved and MBZ. 2133 //! For linear or TileX SFC output, this field 2134 //! is Reserved and MBZ. 2135 2136 enum ROTATION_MODE 2137 { 2138 ROTATION_MODE_0_DEGREES = 0, //!< No additional details 2139 ROTATION_MODE_90CLOCKWISE = 1, //!< No additional details 2140 ROTATION_MODE_180CLOCKWISE = 2, //!< No additional details 2141 ROTATION_MODE_270CLOCKWISE = 3, //!< No additional details 2142 }; 2143 2144 //! \brief BITDEPTH 2145 //! \details 2146 //! This field is valid only for output formats P016/Y216/Y416. This field 2147 //! is used to specify how many of the LSB bits have valid data. 2148 enum BITDEPTH 2149 { 2150 BITDEPTH_10BITFORMAT = 0, //!< Higher 10 bits are valid and lower 6 bits are 0 2151 }; 2152 2153 //! \brief OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2154 //! \details 2155 //! This must be set to 0 2156 enum OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2157 { 2158 OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_DISABLE = 0, //!< This field must be programmed to 0 2159 }; 2160 2161 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2162 //! \details 2163 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2164 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2165 //! vertical from horizontal compression. Please refer to vol1a? 2166 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2167 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2168 //! chapter - section style="color: rgb(35, 35, 35); 2169 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2170 //! line-height: normal;">?media Memory Compression for more details. 2171 enum AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2172 { 2173 AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< Memory compression is not supported for this surface. ?This bit just defaults to 0 2174 }; 2175 2176 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2177 //! \details 2178 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2179 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2180 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2181 //! or to LLC. 2182 enum AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2183 { 2184 AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2185 }; 2186 2187 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2188 //! \details 2189 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2190 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2191 //! vertical from horizontal compression. 2192 enum IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2193 { 2194 IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2195 }; 2196 2197 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2198 //! \details 2199 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2200 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2201 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2202 //! or to LLC. 2203 enum IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2204 { 2205 IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2206 }; 2207 2208 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2209 //! \details 2210 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2211 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2212 //! vertical from horizontal compression. Please refer to vol1a 2213 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2214 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2215 //! chapter - section style="color: rgb(35, 35, 35); 2216 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2217 //! line-height: normal;"> media Memory Compression for more details. 2218 enum SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2219 { 2220 SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2221 }; 2222 2223 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2224 //! \details 2225 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2226 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2227 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2228 //! or to LLC. 2229 enum SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2230 { 2231 SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2232 SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_MEDIASTORAGE = 1, //!< style="margin:0in 0in 8pt"> Data will first cache in Media Storage 2233 }; 2234 2235 //! \brief TILED_MODE 2236 //! \details 2237 //! Indicates the Tile Mode for the Surface. 2238 enum TILED_MODE 2239 { 2240 TILED_MODE_LINEAR = 0, //!< No additional details 2241 TILED_MODE_TILES_64K = 1, //!< No additional details 2242 TILED_MODE_XMAJOR = 2, //!< No additional details 2243 TILED_MODE_TILEF = 3, //!< No additional details 2244 }; 2245 2246 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2247 //! \details 2248 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2249 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2250 //! vertical from horizontal compression. Please refer to vol1a 2251 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2252 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2253 //! chapter - section style="color: rgb(35, 35, 35); 2254 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2255 //! line-height: normal;"> media Memory Compression for more details. 2256 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2257 { 2258 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2259 }; 2260 2261 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2262 //! \details 2263 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2264 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2265 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2266 //! or to LLC. 2267 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2268 { 2269 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2270 }; 2271 2272 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2273 //! \details 2274 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2275 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2276 //! vertical from horizontal compression. Please refer to vol1a 2277 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2278 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2279 //! chapter - section style="color: rgb(35, 35, 35); 2280 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2281 //! line-height: normal;"> media Memory Compression for more details. 2282 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2283 { 2284 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2285 }; 2286 2287 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2288 //! \details 2289 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2290 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2291 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2292 //! or to LLC. 2293 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2294 { 2295 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2296 }; 2297 2298 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2299 //! \details 2300 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2301 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2302 //! vertical from horizontal compression. Please refer to vol1a 2303 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2304 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2305 //! chapter - section style="color: rgb(35, 35, 35); 2306 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2307 //! line-height: normal;"> media Memory Compression for more details. 2308 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE 2309 { 2310 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2311 }; 2312 2313 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2314 //! \details 2315 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2316 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2317 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2318 //! or to LLC. 2319 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2320 { 2321 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2322 }; 2323 2324 //! \brief HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2325 //! \details 2326 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2327 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes Media 2328 //! or 3D compression. style="color: rgb(35, 35, 35); 2329 //! font-family: Arial, sans-serif; font-size: 13.3333330154419px; 2330 //! line-height: normal;">Memory Data Formats chapter - section 2331 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2332 //! font-size: 13.3333330154419px; line-height: normal;"> media Memory 2333 //! Compression for more details. 2334 enum HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2335 { 2336 HISTOGRAM_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE_UNNAMED0 = 0, //!< No additional details 2337 }; 2338 2339 //! \brief HISTOGRAM_BASE_ADDRESS_CACHE_SELECT 2340 //! \details 2341 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2342 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2343 //! if the Histogram need to be cached in LLC or not. 2344 enum HISTOGRAM_BASE_ADDRESS_CACHE_SELECT 2345 { 2346 HISTOGRAM_BASE_ADDRESS_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2347 }; 2348 2349 //! \brief BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2350 //! \details 2351 //! This field is applicable only when memory compression is enabled 2352 enum BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE 2353 { 2354 BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE_MEDIACOMPRESSIONENABLED = 0, //!< No additional details 2355 BOTTOM_FILED_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_TYPE_RENDERCOMPRESSIONENABLED = 1, //!< No additional details 2356 }; 2357 2358 //! \brief BOTTOM_FIELD_SURFACE_TILE_WALK 2359 //! \details 2360 //! This field specifies the type of memory tiling (XMajor or YMajor) 2361 //! employed to tile this surface. See Memory Interface Functions for 2362 //! details on memory tiling and restrictions. 2363 enum BOTTOM_FIELD_SURFACE_TILE_WALK 2364 { 2365 BOTTOM_FIELD_SURFACE_TILE_WALK_TILEWALKXMAJOR = 0, //!< No additional details 2366 BOTTOM_FIELD_SURFACE_TILE_WALK_TILEWALKYMAJOR = 1, //!< No additional details 2367 }; 2368 2369 //! \brief BOTTOM_FIELD_SURFACE_TILED 2370 //! \details 2371 //! This field specifies whether the surface is tiled. 2372 enum BOTTOM_FIELD_SURFACE_TILED 2373 { 2374 BOTTOM_FIELD_SURFACE_TILED_FALSE = 0, //!< Linear 2375 BOTTOM_FIELD_SURFACE_TILED_TRUE = 1, //!< Tiled 2376 }; 2377 2378 //! \name Initializations 2379 2380 //! \brief Explicit member initialization function 2381 SFC_STATE_CMD(); 2382 2383 static const size_t dwSize = 61; 2384 static const size_t byteSize = 244; 2385 }; 2386 2387 //! 2388 //! \brief SFC_AVS_LUMA_Coeff_Table 2389 //! \details 2390 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 2391 //! each frame once the lock request is granted. 2392 //! 2393 struct SFC_AVS_LUMA_Coeff_Table_CMD 2394 { 2395 union 2396 { 2397 struct 2398 { 2399 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2400 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2401 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2402 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 2403 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 2404 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2405 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2406 }; 2407 uint32_t Value; 2408 } DW0; 2409 union 2410 { 2411 struct 2412 { 2413 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],0] 2414 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],0] 2415 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],1] 2416 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],1] 2417 }; 2418 uint32_t Value; 2419 } DW1; 2420 union 2421 { 2422 struct 2423 { 2424 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],2] 2425 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],2] 2426 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],3] 2427 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],3] 2428 }; 2429 uint32_t Value; 2430 } DW2; 2431 union 2432 { 2433 struct 2434 { 2435 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],4] 2436 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],4] 2437 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],5] 2438 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],5] 2439 }; 2440 uint32_t Value; 2441 } DW3; 2442 union 2443 { 2444 struct 2445 { 2446 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],6] 2447 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],6] 2448 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],7] 2449 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],7] 2450 }; 2451 uint32_t Value; 2452 } DW4; 2453 uint32_t FilterCoefficients[124]; //!< Filter Coefficients 2454 2455 //! \name Local enumerations 2456 2457 enum SUBOPCODEB 2458 { 2459 SUBOPCODEB_SFCAVSLUMACOEFFTABLE = 5, //!< No additional details 2460 }; 2461 2462 enum SUBOPCODEA 2463 { 2464 SUBOPCODEA_COMMON = 0, //!< No additional details 2465 }; 2466 2467 enum MEDIA_COMMAND_OPCODE 2468 { 2469 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 2470 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 2471 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 2472 }; 2473 2474 enum PIPELINE 2475 { 2476 PIPELINE_MEDIA = 2, //!< No additional details 2477 }; 2478 2479 enum COMMAND_TYPE 2480 { 2481 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2482 }; 2483 2484 //! \name Initializations 2485 2486 //! \brief Explicit member initialization function 2487 SFC_AVS_LUMA_Coeff_Table_CMD(); 2488 2489 static const size_t dwSize = 129; 2490 static const size_t byteSize = 516; 2491 }; 2492 2493 //! 2494 //! \brief SFC_AVS_CHROMA_Coeff_Table 2495 //! \details 2496 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 2497 //! each frame once the lock request is granted. 2498 //! 2499 struct SFC_AVS_CHROMA_Coeff_Table_CMD 2500 { 2501 union 2502 { 2503 struct 2504 { 2505 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2506 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2507 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2508 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 2509 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 2510 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2511 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2512 }; 2513 uint32_t Value; 2514 } DW0; 2515 union 2516 { 2517 struct 2518 { 2519 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[[n],2] 2520 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[[n],2] 2521 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[[n],3] 2522 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[[n],3] 2523 }; 2524 uint32_t Value; 2525 } DW1; 2526 union 2527 { 2528 struct 2529 { 2530 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[[n],4] 2531 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[[n],4] 2532 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[[n],5] 2533 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[[n],5] 2534 }; 2535 uint32_t Value; 2536 } DW2; 2537 uint32_t FilterCoefficients[62]; //!< Filter Coefficients 2538 2539 //! \name Local enumerations 2540 2541 enum SUBOPCODEB 2542 { 2543 SUBOPCODEB_SFCAVSCHROMACOEFFTABLE = 6, //!< No additional details 2544 }; 2545 2546 enum SUBOPCODEA 2547 { 2548 SUBOPCODEA_COMMON = 0, //!< No additional details 2549 }; 2550 2551 enum MEDIA_COMMAND_OPCODE 2552 { 2553 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 2554 MEDIA_COMMAND_OPCODE_MEDIAMISC = 10, //!< Media MFX/VEBOX+SFC Mode 2555 MEDIA_COMMAND_OPCODE_MEDIAAVPSFCMODE = 0xD, //!< No additional details 2556 }; 2557 2558 enum PIPELINE 2559 { 2560 PIPELINE_MEDIA = 2, //!< No additional details 2561 }; 2562 2563 enum COMMAND_TYPE 2564 { 2565 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2566 }; 2567 2568 //! \name Initializations 2569 2570 //! \brief Explicit member initialization function 2571 SFC_AVS_CHROMA_Coeff_Table_CMD(); 2572 2573 static const size_t dwSize = 65; 2574 static const size_t byteSize = 260; 2575 }; 2576 MEDIA_CLASS_DEFINE_END(mhw__sfc__xe2_hpm_next__Cmd) 2577 }; 2578 } // namespace xe2_hpm_next 2579 } // namespace sfc 2580 } // namespace mhw 2581 2582 #pragma pack() 2583 2584 #endif // __MHW_SFC_HWCMD_XE2_HPM_H__ 2585