1 /* 2 * Copyright (c) 2024, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_render_xe2_hpg_next_impl.h 24 //! \brief MHW Render interface common base for Xe2_HPG 25 //! \details 26 //! 27 28 #ifndef __MHW_RENDER_XE2_HPG_NEXT_IMPL_H__ 29 #define __MHW_RENDER_XE2_HPG_NEXT_IMPL_H__ 30 31 #include "mhw_render_impl.h" 32 #include "mhw_render_hwcmd_xe2_hpg_next.h" 33 #include "mhw_render_itf.h" 34 #include "mhw_impl.h" 35 36 namespace mhw 37 { 38 namespace render 39 { 40 namespace xe2_hpg_next 41 { 42 class Impl : public render::Impl<mhw::render::xe2_hpg_next::Cmd> 43 { 44 public: Impl(PMOS_INTERFACE osItf)45 Impl(PMOS_INTERFACE osItf) : base_t(osItf) 46 { 47 MHW_FUNCTION_ENTER; 48 49 InitMmioRegisters(); 50 }; 51 InitMmioRegisters()52 MOS_STATUS InitMmioRegisters() override 53 { 54 MHW_FUNCTION_ENTER; 55 MHW_MI_MMIOREGISTERS *mmioRegisters = &m_mmioRegisters; 56 mmioRegisters->generalPurposeRegister0LoOffset = CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET; 57 mmioRegisters->generalPurposeRegister0HiOffset = CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET; 58 mmioRegisters->generalPurposeRegister4LoOffset = CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET; 59 mmioRegisters->generalPurposeRegister4HiOffset = CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET; 60 mmioRegisters->generalPurposeRegister11LoOffset = CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET; 61 mmioRegisters->generalPurposeRegister11HiOffset = CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET; 62 mmioRegisters->generalPurposeRegister12LoOffset = CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET; 63 mmioRegisters->generalPurposeRegister12HiOffset = CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET; 64 65 return MOS_STATUS_SUCCESS; 66 } 67 EnableL3Caching(mhw::render::MHW_RENDER_ENGINE_L3_CACHE_SETTINGS * cacheSettings)68 MOS_STATUS EnableL3Caching(mhw::render::MHW_RENDER_ENGINE_L3_CACHE_SETTINGS *cacheSettings) override 69 { 70 MHW_FUNCTION_ENTER; 71 // L3 Caching enabled by default 72 m_l3CacheConfig.bL3CachingEnabled = true; 73 m_l3CacheConfig.dwRcsL3CacheAllocReg_Register = M_MMIO_RCS_L3ALLOCREG; 74 m_l3CacheConfig.dwRcsL3CacheTcCntlReg_Register = M_MMIO_RCS_TCCNTLREG; 75 m_l3CacheConfig.dwCcs0L3CacheAllocReg_Register = M_MMIO_CCS0_L3ALLOCREG; 76 m_l3CacheConfig.dwCcs0L3CacheTcCntlReg_Register = M_MMIO_CCS0_TCCNTLREG; 77 if (cacheSettings) 78 { 79 MHW_RENDER_ENGINE_L3_CACHE_SETTINGS *cacheSettingsHpg = (MHW_RENDER_ENGINE_L3_CACHE_SETTINGS *)cacheSettings; 80 m_l3CacheConfig.dwL3CacheAllocReg_Setting = cacheSettingsHpg->dwAllocReg; 81 m_l3CacheConfig.dwL3CacheTcCntlReg_Setting = cacheSettingsHpg->dwTcCntlReg; 82 // update default settings is needed from CM HAL call 83 if (cacheSettingsHpg->bUpdateDefault) 84 { 85 m_l3CacheAllocRegisterValueDefault = cacheSettingsHpg->dwAllocReg; 86 m_l3CacheTcCntlRegisterValueDefault = cacheSettingsHpg->dwTcCntlReg; 87 } 88 } 89 else // Use the default setting if regkey is not set 90 { 91 // different default settings after CM HAL call 92 m_l3CacheConfig.dwL3CacheAllocReg_Setting = m_l3CacheAllocRegisterValueDefault; 93 m_l3CacheConfig.dwL3CacheTcCntlReg_Setting = m_l3CacheTcCntlRegisterValueDefault; 94 } 95 96 return MOS_STATUS_SUCCESS; 97 } 98 SetL3Cache(PMOS_COMMAND_BUFFER cmdBuffer,std::shared_ptr<mhw::mi::Itf> miItf)99 MOS_STATUS SetL3Cache(PMOS_COMMAND_BUFFER cmdBuffer, std::shared_ptr<mhw::mi::Itf> miItf) override 100 { 101 MHW_FUNCTION_ENTER; 102 MOS_STATUS eStatus = MOS_STATUS_SUCCESS; 103 104 MHW_MI_CHK_NULL(cmdBuffer); 105 MHW_MI_CHK_NULL(miItf); 106 107 if (m_l3CacheConfig.bL3CachingEnabled) 108 { 109 //L3CacheAllocReg_Setting and L3CacheTcCntlReg_Setting 110 if ((m_l3CacheConfig.dwL3CacheAllocReg_Setting != 0) || (m_l3CacheConfig.dwL3CacheTcCntlReg_Setting != 0)) 111 { 112 //update L3 AllocReg setting for RCS; CCS L3 AllocReg setting will be dulicated from RCS 113 auto& l3CachePar = miItf->MHW_GETPAR_F(MI_LOAD_REGISTER_IMM)(); 114 l3CachePar = {}; 115 l3CachePar.dwRegister = m_l3CacheConfig.dwRcsL3CacheAllocReg_Register; 116 l3CachePar.dwData = m_l3CacheConfig.dwL3CacheAllocReg_Setting; 117 MHW_MI_CHK_STATUS(miItf->MHW_ADDCMD_F(MI_LOAD_REGISTER_IMM)(cmdBuffer)); 118 119 //update L3 TcCntlReg setting for RCS; CCS L3 TcCntlReg setting will be dulicated from RCS 120 auto& rcsL3CacheTcCntlPar = miItf->MHW_GETPAR_F(MI_LOAD_REGISTER_IMM)(); 121 rcsL3CacheTcCntlPar = {}; 122 rcsL3CacheTcCntlPar.dwRegister = m_l3CacheConfig.dwRcsL3CacheTcCntlReg_Register; 123 rcsL3CacheTcCntlPar.dwData = m_l3CacheConfig.dwL3CacheTcCntlReg_Setting; 124 MHW_MI_CHK_STATUS(miItf->MHW_ADDCMD_F(MI_LOAD_REGISTER_IMM)(cmdBuffer)); 125 } 126 } 127 128 return eStatus; 129 } 130 _MHW_SETCMD_OVERRIDE_DECL(_3DSTATE_CHROMA_KEY)131 _MHW_SETCMD_OVERRIDE_DECL(_3DSTATE_CHROMA_KEY) 132 { 133 _MHW_SETCMD_CALLBASE(_3DSTATE_CHROMA_KEY); 134 135 cmd.DW1.ChromakeyTableIndex = params.dwIndex; 136 cmd.DW2.ChromakeyLowValue = params.dwLow; 137 cmd.DW3.ChromakeyHighValue = params.dwHigh; 138 139 return MOS_STATUS_SUCCESS; 140 } 141 _MHW_SETCMD_OVERRIDE_DECL(PIPELINE_SELECT)142 _MHW_SETCMD_OVERRIDE_DECL(PIPELINE_SELECT) 143 { 144 _MHW_SETCMD_CALLBASE(PIPELINE_SELECT); 145 cmd.DW0.MaskBits = 0x13; 146 return MOS_STATUS_SUCCESS; 147 } 148 _MHW_SETCMD_OVERRIDE_DECL(STATE_COMPUTE_MODE)149 _MHW_SETCMD_OVERRIDE_DECL(STATE_COMPUTE_MODE) 150 { 151 _MHW_SETCMD_CALLBASE(STATE_COMPUTE_MODE); 152 cmd.DW1.Mask1 = 0xFFFF; 153 cmd.DW1.LargeGrfMode = 0; 154 cmd.DW1.EuThreadSchedulingModeOverride = params.forceEuThreadSchedulingMode; 155 156 return MOS_STATUS_SUCCESS; 157 } 158 _MHW_SETCMD_OVERRIDE_DECL(CFE_STATE)159 _MHW_SETCMD_OVERRIDE_DECL(CFE_STATE) 160 { 161 _MHW_SETCMD_CALLBASE(CFE_STATE); 162 163 cmd.DW3.MaximumNumberOfThreads = params.dwMaximumNumberofThreads; 164 cmd.DW1.ScratchSpaceBuffer = params.ScratchSpaceBuffer; 165 166 return MOS_STATUS_SUCCESS; 167 } 168 _MHW_SETCMD_OVERRIDE_DECL(COMPUTE_WALKER)169 _MHW_SETCMD_OVERRIDE_DECL(COMPUTE_WALKER) 170 { 171 _MHW_SETCMD_CALLBASE(COMPUTE_WALKER); 172 173 cmd.DW2.IndirectDataLength = params.IndirectDataLength; 174 cmd.DW3.IndirectDataStartAddress = params.IndirectDataStartAddress >> MHW_COMPUTE_INDIRECT_SHIFT; 175 176 cmd.DW4.SIMDSize = 2; 177 cmd.DW4.MessageSIMD = Cmd::COMPUTE_WALKER_CMD::MESSAGE_SIMD_SIMT32; 178 cmd.DW5.ExecutionMask = 0xffffffff; 179 cmd.DW6.LocalXMaximum = params.ThreadWidth - 1; 180 cmd.DW6.LocalYMaximum = params.ThreadHeight - 1; 181 cmd.DW6.LocalZMaximum = params.ThreadDepth - 1; 182 183 cmd.DW7.ThreadGroupIDXDimension = params.GroupWidth; 184 cmd.DW8.ThreadGroupIDYDimension = params.GroupHeight; 185 cmd.DW9.ThreadGroupIDZDimension = params.GroupDepth; 186 cmd.DW10.ThreadGroupIDStartingX = params.GroupStartingX; 187 cmd.DW11.ThreadGroupIDStartingY = params.GroupStartingY; 188 cmd.DW12.ThreadGroupIDStartingZ = params.GroupStartingZ; 189 190 cmd.InterfaceDescriptor.DW0.KernelStartPointer = params.dwKernelOffset >> MHW_KERNEL_OFFSET_SHIFT; 191 cmd.InterfaceDescriptor.DW3.SamplerCount = params.dwSamplerCount; 192 cmd.InterfaceDescriptor.DW3.SamplerStatePointer = params.dwSamplerOffset >> MHW_SAMPLER_SHIFT; 193 cmd.InterfaceDescriptor.DW4.BindingTablePointer = MOS_ROUNDUP_SHIFT(params.dwBindingTableOffset, MHW_BINDING_TABLE_ID_SHIFT); 194 cmd.InterfaceDescriptor.DW5.NumberOfThreadsInGpgpuThreadGroup = params.dwNumberofThreadsInGPGPUGroup; 195 cmd.InterfaceDescriptor.DW5.SharedLocalMemorySize = params.dwSharedLocalMemorySize; 196 197 cmd.InterfaceDescriptor.DW7.PreferredSlmAllocationSizePerSubslice = params.preferredSlmAllocationSize; 198 199 // when Barriers is not 0, the EU fusion will close. 200 // Assigns barrier count. 201 if (params.bBarrierEnable) 202 { // Bits [28:30] represent the number of barriers on DG2. 203 cmd.InterfaceDescriptor.DW5.NumberOfBarriers = 1; 204 } 205 206 cmd.DW4.EmitInlineParameter = params.isEmitInlineParameter; 207 MOS_SecureMemcpy(cmd.InlineData.Value, sizeof(cmd.InlineData.Value), params.inlineData, params.inlineDataLength); 208 209 cmd.DW4.GenerateLocalId = params.isGenerateLocalId; 210 cmd.DW4.EmitLocal = params.emitLocal; 211 212 return MOS_STATUS_SUCCESS; 213 } 214 215 protected: 216 using base_t = render::Impl<mhw::render::xe2_hpg_next::Cmd>; 217 uint32_t m_l3CacheTcCntlRegisterValueDefault = 0x80000080; 218 uint32_t m_l3CacheAllocRegisterValueDefault = 0xD0000020; 219 MEDIA_CLASS_DEFINE_END(mhw__render__xe2_hpg_next__Impl) 220 }; 221 222 } // namespace xe2_hpg_next 223 } // namespace render 224 } // namespace mhw 225 226 #endif // __MHW_RENDER_XE_HPG_IMPL_H__