1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_render_hwcmd_g11_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g11_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_RENDER_HWCMD_G11_X_H__ 29 #define __MHW_RENDER_HWCMD_G11_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_render_g11_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MEDIA_OBJECT 50 //! \details 51 //! 52 //! 53 struct MEDIA_OBJECT_CMD 54 { 55 union 56 { 57 //!< DWORD 0 58 struct 59 { 60 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 14) ; //!< DWORD_LENGTH 61 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 62 uint32_t MediaCommandSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< MEDIA_COMMAND_SUB_OPCODE 63 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 64 uint32_t MediaCommandPipeline : __CODEGEN_BITFIELD(27, 28) ; //!< MEDIA_COMMAND_PIPELINE 65 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 66 }; 67 uint32_t Value; 68 } DW0; 69 union 70 { 71 //!< DWORD 1 72 struct 73 { 74 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 75 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 76 }; 77 uint32_t Value; 78 } DW1; 79 union 80 { 81 //!< DWORD 2 82 struct 83 { 84 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 85 uint32_t SubsliceDestinationSelect : __CODEGEN_BITFIELD(17, 18) ; //!< SUBSLICE_DESTINATION_SELECT 86 uint32_t SliceDestinationSelect : __CODEGEN_BITFIELD(19, 20) ; //!< SLICE_DESTINATION_SELECT 87 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 88 uint32_t ForceDestination : __CODEGEN_BITFIELD(22, 22) ; //!< Force Destination 89 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 90 uint32_t ThreadSynchronization : __CODEGEN_BITFIELD(24, 24) ; //!< THREAD_SYNCHRONIZATION 91 uint32_t SliceDestinationSelectMsbs : __CODEGEN_BITFIELD(25, 26) ; //!< Slice Destination Select MSBs 92 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 93 }; 94 uint32_t Value; 95 } DW2; 96 union 97 { 98 //!< DWORD 3 99 struct 100 { 101 uint32_t IndirectDataStartAddress ; //!< Indirect Data Start Address 102 }; 103 uint32_t Value; 104 } DW3; 105 union 106 { 107 //!< DWORD 4 108 struct 109 { 110 uint32_t XPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< X Position 111 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 112 uint32_t YPosition : __CODEGEN_BITFIELD(16, 24) ; //!< Y Position 113 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 114 }; 115 uint32_t Value; 116 } DW4; 117 union 118 { 119 //!< DWORD 5 120 struct 121 { 122 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 123 uint32_t BlockColor : __CODEGEN_BITFIELD(16, 23) ; //!< Block Color 124 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 125 }; 126 uint32_t Value; 127 } DW5; 128 129 //! \name Local enumerations 130 131 enum MEDIA_COMMAND_SUB_OPCODE 132 { 133 MEDIA_COMMAND_SUB_OPCODE_MEDIAOBJECTSUBOP = 0, //!< No additional details 134 }; 135 136 enum MEDIA_COMMAND_OPCODE 137 { 138 MEDIA_COMMAND_OPCODE_MEDIAOBJECT = 1, //!< No additional details 139 }; 140 141 enum MEDIA_COMMAND_PIPELINE 142 { 143 MEDIA_COMMAND_PIPELINE_MEDIA = 2, //!< No additional details 144 }; 145 146 enum COMMAND_TYPE 147 { 148 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 149 }; 150 151 //! \brief SUBSLICE_DESTINATION_SELECT 152 //! \details 153 //! This field selects the SubSlice that this thread must be sent to. 154 //! Ignored if <b>Force Destination</b> = 0 155 enum SUBSLICE_DESTINATION_SELECT 156 { 157 SUBSLICE_DESTINATION_SELECT_SUBSLICE0 = 0, //!< No additional details 158 SUBSLICE_DESTINATION_SELECT_SUBSLICE1 = 1, //!< No additional details 159 SUBSLICE_DESTINATION_SELECT_SUBSLICE2 = 2, //!< No additional details 160 SUBSLICE_DESTINATION_SELECT_SUBSLICE3 = 3, //!< No additional details 161 }; 162 163 //! \brief SLICE_DESTINATION_SELECT 164 //! \details 165 //! This bit along with the subslice destination select determines the slice 166 //! that this thread must be sent to. Ignored if <b>Force Destination</b> = 167 //! 0, or if product only has 1 slice. 168 enum SLICE_DESTINATION_SELECT 169 { 170 SLICE_DESTINATION_SELECT_SLICE0 = 0, //!< No additional details 171 SLICE_DESTINATION_SELECT_SLICE1 = 1, //!< Cannot be used in products without a Slice 1. 172 SLICE_DESTINATION_SELECT_SLICE2 = 2, //!< Cannot be used in products without a Slice 2. 173 }; 174 175 //! \brief THREAD_SYNCHRONIZATION 176 //! \details 177 //! This field when set indicates that the dispatch of the thread originated 178 //! from this command is based on the "spawn root thread" message. 179 enum THREAD_SYNCHRONIZATION 180 { 181 THREAD_SYNCHRONIZATION_NOTHREADSYNCHRONIZATION = 0, //!< No additional details 182 THREAD_SYNCHRONIZATION_THREADDISPATCHISSYNCHRONIZEDBYTHESPAWNROOTTHREADMESSAGE = 1, //!< No additional details 183 }; 184 185 //! \name Initializations 186 187 //! \brief Explicit member initialization function 188 MEDIA_OBJECT_CMD(); 189 190 static const size_t dwSize = 6; 191 static const size_t byteSize = 24; 192 }; 193 194 //! 195 //! \brief PIPELINE_SELECT 196 //! \details 197 //! The PIPELINE_SELECT command is used to specify which GPE pipeline is to 198 //! be considered the 'current' active pipeline. Issuing 199 //! 3D-pipeline-specific commands when the Media pipeline is selected, or 200 //! vice versa, is UNDEFINED. 201 //! 202 //! Issuing 3D-pipeline-specific commands when the GPGPU pipeline is 203 //! selected, or vice versa, is UNDEFINED. 204 //! 205 //! Programming common non pipeline commands (e.g., STATE_BASE_ADDRESS) is 206 //! allowed in all pipeline modes. 207 //! 208 //! Software must ensure all the write caches are flushed through a stalling 209 //! PIPE_CONTROL command followed by another PIPE_CONTROL command to 210 //! invalidate read only caches prior to programming MI_PIPELINE_SELECT 211 //! command to change the Pipeline Select Mode. Example: ... Workload-3Dmode 212 //! PIPE_CONTROL (CS Stall, Depth Cache Flush Enable, Render Target Cache 213 //! Flush Enable, DC Flush Enable) PIPE_CONTROL (Constant Cache Invalidate, 214 //! Texture Cache Invalidate, Instruction Cache Invalidate, State Cache 215 //! invalidate) PIPELINE_SELECT ( GPGPU) 216 //! 217 //! This command must be followed by a PIPE_CONTROL with CS Stall bit 218 //! set. 219 //! 220 struct PIPELINE_SELECT_CMD 221 { 222 union 223 { 224 //!< DWORD 0 225 struct 226 { 227 uint32_t PipelineSelection : __CODEGEN_BITFIELD( 0, 1) ; //!< PIPELINE_SELECTION 228 uint32_t RenderSliceCommonPowerGateEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< RENDER_SLICE_COMMON_POWER_GATE_ENABLE 229 uint32_t RenderSamplerPowerGateEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< RENDER_SAMPLER_POWER_GATE_ENABLE 230 uint32_t MediaSamplerDopClockGateEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 231 uint32_t ForceMediaAwake : __CODEGEN_BITFIELD( 5, 5) ; //!< FORCE_MEDIA_AWAKE 232 uint32_t MediaSamplerPowerClockGateDisable : __CODEGEN_BITFIELD( 6, 6) ; //!< Media Sampler Power Clock Gate Disable 233 uint32_t Reserved7 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 234 uint32_t MaskBits : __CODEGEN_BITFIELD( 8, 15) ; //!< Mask Bits 235 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 236 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 237 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 238 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 239 }; 240 uint32_t Value; 241 } DW0; 242 243 //! \name Local enumerations 244 245 //! \brief PIPELINE_SELECTION 246 //! \details 247 //! Mask bits [9:8] has to be set for HW to look at this field when 248 //! PIPELINE_SELECT command is parsed. Setting only one of the mask bit [9] 249 //! or [8] is illegal. 250 enum PIPELINE_SELECTION 251 { 252 PIPELINE_SELECTION_3D = 0, //!< 3D pipeline is selected 253 PIPELINE_SELECTION_MEDIA = 1, //!< Media pipeline is selected (Includes HD optical disc playback, HD video playback, and generic media workloads) 254 PIPELINE_SELECTION_GPGPU = 2, //!< GPGPU pipeline is selected 255 }; 256 257 //! \brief RENDER_SLICE_COMMON_POWER_GATE_ENABLE 258 //! \details 259 //! Mask bit [10] has to be set for HW to look at this field when 260 //! PIPELINE_SELECT command is parsed. 261 enum RENDER_SLICE_COMMON_POWER_GATE_ENABLE 262 { 263 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render slice common Power Gating. 264 RENDER_SLICE_COMMON_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render slice common Power Gating. 265 }; 266 267 //! \brief RENDER_SAMPLER_POWER_GATE_ENABLE 268 //! \details 269 //! Mask bit [11] has to be set for HW to look at this field when 270 //! PIPELINE_SELECT command is parsed. 271 enum RENDER_SAMPLER_POWER_GATE_ENABLE 272 { 273 RENDER_SAMPLER_POWER_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable render sampler Power Gating. 274 RENDER_SAMPLER_POWER_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable render sampler Power Gating. 275 }; 276 277 //! \brief MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 278 //! \details 279 //! Mask bit [12] has to be set for HW to look at this field when 280 //! PIPELINE_SELECT command is parsed. 281 enum MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE 282 { 283 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_DISABLED = 0, //!< Command Streamer sends message to PM to disable sampler DOP Clock Gating. 284 MEDIA_SAMPLER_DOP_CLOCK_GATE_ENABLE_ENABLED = 1, //!< Command Streamer sends message to PM to enable media sampler DOP Clock Gating. 285 }; 286 287 //! \brief FORCE_MEDIA_AWAKE 288 //! \details 289 //! Mask bit [13] has to be set for HW to look at this field when 290 //! PIPELINE_SELECT command is parsed. 291 //! 292 //! Example for usage model: 293 //! 294 //! <b>RCS Ring Buffer</b>: 295 //! <b>PIPELINE_SELECT (Force Media Awake set to '1')</b> 296 //! MI_SEMPAHORE_SINGAL (Signal context id 0xABC to Render Command 297 //! Streamer) 298 //! <b>PIPELINE_SELECT (Force Media Awake set to '0')</b> 299 //! <b>MI_BATCH_BUFFER_START</b> 300 //! STATE Commands .. 301 //! ………… 302 //! <b>PIPELINE_SELECT (Force Media Awake set to '1')</b> 303 //! MI_LOAD_REGISTER_IMM (Load register 0x23XX in render command 304 //! streamer with data 0xFFF) 305 //! <b>PIPELINE_SELECT (Force Media Awake set to '0')</b> 306 //! ………… 307 //! <b>MI_BATCH_BUFFER_END</b> 308 enum FORCE_MEDIA_AWAKE 309 { 310 FORCE_MEDIA_AWAKE_DISABLED = 0, //!< Command streamer sends message to PM to disable force awake of media engine (next instructions do not require the media engine to be awake). Command streamer waits for acknowledge from PM before parsing the next command. 311 FORCE_MEDIA_AWAKE_ENABLED = 1, //!< Command streamer sends message to PM to force awake media engine (next instructions require media engine awake). Command streamer waits for acknowledge from PM before parsing the next command. 312 }; 313 314 enum _3D_COMMAND_SUB_OPCODE 315 { 316 _3D_COMMAND_SUB_OPCODE_PIPELINESELECT = 4, //!< No additional details 317 }; 318 319 enum _3D_COMMAND_OPCODE 320 { 321 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 322 }; 323 324 enum COMMAND_SUBTYPE 325 { 326 COMMAND_SUBTYPE_GFXPIPESINGLEDW = 1, //!< No additional details 327 }; 328 329 enum COMMAND_TYPE 330 { 331 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 332 }; 333 334 //! \name Initializations 335 336 //! \brief Explicit member initialization function 337 PIPELINE_SELECT_CMD(); 338 339 static const size_t dwSize = 1; 340 static const size_t byteSize = 4; 341 }; 342 343 //! 344 //! \brief STATE_BASE_ADDRESS 345 //! \details 346 //! The STATE_BASE_ADDRESS command sets the base pointers for subsequent 347 //! state, instruction, and media indirect object accesses by the GPE. 348 //! For more information see the Base Address Utilization table in the 349 //! Memory Access Indirection narrative topic. 350 //! 351 //! The following commands must be reissued following any change to the base 352 //! addresses: 3DSTATE_CC_POINTERS 353 //! 3DSTATE_BINDING_TABLE_POINTERS 354 //! 3DSTATE_SAMPLER_STATE_POINTERS 355 //! 3DSTATE_VIEWPORT_STATE_POINTERS 356 //! MEDIA_STATE_POINTERS 357 //! Execution of this command causes a full pipeline flush, thus its use 358 //! should be minimized for higher performance. 359 //! 360 //! SW must always program PIPE_CONTROL with "CS Stall" and "Render Target 361 //! Cache Flush Enable" set before programming STATE_BASE_ADDRESS command 362 //! for GPGPU workloads i.e when pipeline select is GPGPU via 363 //! PIPELINE_SELECT command. This is required to achieve better GPGPU 364 //! preemption latencies in certain workload programming sequences. If 365 //! programming PIPE_CONTROL has performance implications then preemption 366 //! latencies can be traded off against performance by not implementing this 367 //! programming note. 368 //! 369 //! This command must be followed by a PIPE_CONTROL with CS Stall bit 370 //! set., 371 //! 372 struct STATE_BASE_ADDRESS_CMD 373 { 374 union 375 { 376 //!< DWORD 0 377 struct 378 { 379 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 380 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 381 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 382 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 383 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 384 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 385 }; 386 uint32_t Value; 387 } DW0; 388 union 389 { 390 //!< DWORD 1..2 391 struct 392 { 393 uint64_t GeneralStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 394 uint64_t Reserved33 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 395 uint64_t GeneralStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< General State Memory Object Control State 396 uint64_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 397 uint64_t GeneralStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< General State Base Address 398 }; 399 uint32_t Value[2]; 400 } DW1_2; 401 union 402 { 403 //!< DWORD 3 404 struct 405 { 406 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 407 uint32_t StatelessDataPortAccessMemoryObjectControlState : __CODEGEN_BITFIELD(16, 22) ; //!< Stateless Data Port Access Memory Object Control State 408 uint32_t Reserved119 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 409 }; 410 uint32_t Value; 411 } DW3; 412 union 413 { 414 //!< DWORD 4..5 415 struct 416 { 417 uint64_t SurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 418 uint64_t Reserved129 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 419 uint64_t SurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Surface State Memory Object Control State 420 uint64_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 421 uint64_t SurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Surface State Base Address 422 }; 423 uint32_t Value[2]; 424 } DW4_5; 425 union 426 { 427 //!< DWORD 6..7 428 struct 429 { 430 uint64_t DynamicStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 431 uint64_t Reserved193 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 432 uint64_t DynamicStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Dynamic State Memory Object Control State 433 uint64_t Reserved203 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 434 uint64_t DynamicStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Dynamic State Base Address 435 }; 436 uint32_t Value[2]; 437 } DW6_7; 438 union 439 { 440 //!< DWORD 8..9 441 struct 442 { 443 uint64_t IndirectObjectBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 444 uint64_t Reserved257 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 445 uint64_t IndirectObjectMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Indirect Object Memory Object Control State 446 uint64_t Reserved267 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 447 uint64_t IndirectObjectBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Indirect Object Base Address 448 }; 449 uint32_t Value[2]; 450 } DW8_9; 451 union 452 { 453 //!< DWORD 10..11 454 struct 455 { 456 uint64_t InstructionBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 457 uint64_t Reserved321 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 458 uint64_t InstructionMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Instruction Memory Object Control State 459 uint64_t Reserved331 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 460 uint64_t InstructionBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Instruction Base Address 461 }; 462 uint32_t Value[2]; 463 } DW10_11; 464 union 465 { 466 //!< DWORD 12 467 struct 468 { 469 uint32_t GeneralStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 470 uint32_t Reserved385 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 471 uint32_t GeneralStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< General State Buffer Size 472 }; 473 uint32_t Value; 474 } DW12; 475 union 476 { 477 //!< DWORD 13 478 struct 479 { 480 uint32_t DynamicStateBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 481 uint32_t Reserved417 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 482 uint32_t DynamicStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Dynamic State Buffer Size 483 }; 484 uint32_t Value; 485 } DW13; 486 union 487 { 488 //!< DWORD 14 489 struct 490 { 491 uint32_t IndirectObjectBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 492 uint32_t Reserved449 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 493 uint32_t IndirectObjectBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Indirect Object Buffer Size 494 }; 495 uint32_t Value; 496 } DW14; 497 union 498 { 499 //!< DWORD 15 500 struct 501 { 502 uint32_t InstructionBufferSizeModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 503 uint32_t Reserved481 : __CODEGEN_BITFIELD( 1, 11) ; //!< Reserved 504 uint32_t InstructionBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Instruction Buffer Size 505 }; 506 uint32_t Value; 507 } DW15; 508 union 509 { 510 //!< DWORD 16..17 511 struct 512 { 513 uint64_t BindlessSurfaceStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 514 uint64_t Reserved513 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 515 uint64_t BindlessSurfaceStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Bindless Surface State Memory Object Control State 516 uint64_t Reserved523 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 517 uint64_t BindlessSurfaceStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Bindless Surface State Base Address 518 }; 519 uint32_t Value[2]; 520 } DW16_17; 521 union 522 { 523 //!< DWORD 18 524 struct 525 { 526 uint32_t Reserved576 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 527 uint32_t BindlessSurfaceStateSize : __CODEGEN_BITFIELD(12, 31) ; //!< Bindless Surface State Size 528 }; 529 uint32_t Value; 530 } DW18; 531 union 532 { 533 //!< DWORD 19..20 534 struct 535 { 536 uint64_t BindlessSamplerStateBaseAddressModifyEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 537 uint64_t Reserved609 : __CODEGEN_BITFIELD( 1, 3) ; //!< Reserved 538 uint64_t BindlessSamplerStateMemoryObjectControlState : __CODEGEN_BITFIELD( 4, 10) ; //!< Bindless Sampler State Memory Object Control State 539 uint64_t Reserved619 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 540 uint64_t BindlessSamplerStateBaseAddress : __CODEGEN_BITFIELD(12, 63) ; //!< Bindless Sampler State Base Address 541 }; 542 uint32_t Value[2]; 543 } DW19_20; 544 union 545 { 546 //!< DWORD 21 547 struct 548 { 549 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 550 uint32_t BindlessSamplerStateBufferSize : __CODEGEN_BITFIELD(12, 31) ; //!< Bindless Sampler State Buffer Size 551 }; 552 uint32_t Value; 553 } DW21; 554 555 //! \name Local enumerations 556 557 enum _3D_COMMAND_SUB_OPCODE 558 { 559 _3D_COMMAND_SUB_OPCODE_STATEBASEADDRESS = 1, //!< No additional details 560 }; 561 562 enum _3D_COMMAND_OPCODE 563 { 564 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 565 }; 566 567 enum COMMAND_SUBTYPE 568 { 569 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 570 }; 571 572 enum COMMAND_TYPE 573 { 574 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 575 }; 576 577 //! \brief GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 578 //! \details 579 //! <p>The other fields in this DWord and the following DWord are updated 580 //! only when this bit is set.</p> 581 enum GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE 582 { 583 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 584 GENERAL_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 585 }; 586 587 //! \brief SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 588 //! \details 589 //! The other fields in this DWord and the following DWord are updated only 590 //! when this bit is set. 591 enum SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 592 { 593 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 594 SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 595 }; 596 597 //! \brief DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 598 //! \details 599 //! The other fields in this DWord and the following DWord are updated only 600 //! when this bit is set. 601 enum DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE 602 { 603 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 604 DYNAMIC_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 605 }; 606 607 //! \brief INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 608 //! \details 609 //! <p>The other fields in this DWord and the following DWord are updated 610 //! only when this bit is set.</p> 611 enum INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE 612 { 613 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 614 INDIRECT_OBJECT_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 615 }; 616 617 //! \brief INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 618 //! \details 619 //! <p>The other fields in this DWord and the following DWord are updated 620 //! only when this bit is set.</p> 621 enum INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE 622 { 623 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address. 624 INSTRUCTION_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address. 625 }; 626 627 //! \brief GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 628 //! \details 629 //! The bound in this DWord is updated only when this bit is set. 630 enum GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE 631 { 632 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 633 GENERAL_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 634 }; 635 636 //! \brief DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 637 //! \details 638 //! FormatDesc 639 enum DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE 640 { 641 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 642 DYNAMIC_STATE_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 643 }; 644 645 //! \brief INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 646 //! \details 647 //! FormatDesc 648 enum INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE 649 { 650 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 651 INDIRECT_OBJECT_BUFFER_SIZE_MODIFY_ENABLE_ENABLE = 1, //!< Modify the updated bound. 652 }; 653 654 //! \brief INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 655 //! \details 656 //! FormatDesc 657 enum INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE 658 { 659 INSTRUCTION_BUFFER_SIZE_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated bound. 660 }; 661 662 //! \brief BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 663 //! \details 664 //! <p>The other fields in this DWord and the following two DWords are 665 //! updated only when this bit is set.</p> 666 enum BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE 667 { 668 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address 669 BINDLESS_SURFACE_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address 670 }; 671 672 //! \brief BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 673 //! \details 674 //! <p>The other fields in this DWord and the following two DWords are 675 //! updated only when this bit is set.</p> 676 enum BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE 677 { 678 BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE_DISABLE = 0, //!< Ignore the updated address 679 BINDLESS_SAMPLER_STATE_BASE_ADDRESS_MODIFY_ENABLE_ENABLE = 1, //!< Modify the address 680 }; 681 682 //! \name Initializations 683 684 //! \brief Explicit member initialization function 685 STATE_BASE_ADDRESS_CMD(); 686 687 static const size_t dwSize = 22; 688 static const size_t byteSize = 88; 689 }; 690 691 //! 692 //! \brief MEDIA_VFE_STATE 693 //! \details 694 //! A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless the 695 //! only bits that are changed are scoreboard related: Scoreboard Enable, 696 //! Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For these 697 //! scoreboard related states, a MEDIA_STATE_FLUSH is sufficient. 698 //! 699 //! MEDIA_STATE_FLUSH (optional, only if barrier dependency is needed) 700 //! 701 //! MEDIA_INTERFACE_DESCRIPTOR_LOAD (optional) 702 //! 703 //! 704 //! 705 struct MEDIA_VFE_STATE_CMD 706 { 707 union 708 { 709 //!< DWORD 0 710 struct 711 { 712 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 713 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 714 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 715 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 716 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 717 }; 718 uint32_t Value; 719 } DW0; 720 union 721 { 722 //!< DWORD 1 723 struct 724 { 725 uint32_t PerThreadScratchSpace : __CODEGEN_BITFIELD( 0, 3) ; //!< Per Thread Scratch Space 726 uint32_t StackSize : __CODEGEN_BITFIELD( 4, 7) ; //!< Stack Size 727 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 9) ; //!< Reserved 728 uint32_t ScratchSpaceBasePointer : __CODEGEN_BITFIELD(10, 31) ; //!< Scratch Space Base Pointer 729 }; 730 uint32_t Value; 731 } DW1; 732 union 733 { 734 //!< DWORD 2 735 struct 736 { 737 uint32_t ScratchSpaceBasePointerHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Scratch Space Base Pointer High 738 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 739 }; 740 uint32_t Value; 741 } DW2; 742 union 743 { 744 //!< DWORD 3 745 struct 746 { 747 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 748 uint32_t DispatchLoadBalance : __CODEGEN_BITFIELD( 2, 2) ; //!< DISPATCH_LOAD_BALANCE 749 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 5) ; //!< Reserved 750 uint32_t DisableSlice0Subslice2 : __CODEGEN_BITFIELD( 6, 6) ; //!< Disable Slice 0 Subslice 2 751 uint32_t Reserved103 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 752 uint32_t NumberOfUrbEntries : __CODEGEN_BITFIELD( 8, 15) ; //!< Number of URB Entries 753 uint32_t MaximumNumberOfThreads : __CODEGEN_BITFIELD(16, 31) ; //!< Maximum Number of Threads 754 }; 755 uint32_t Value; 756 } DW3; 757 union 758 { 759 //!< DWORD 4 760 struct 761 { 762 uint32_t MaximumNumberOfDualSubslices : __CODEGEN_BITFIELD( 0, 7) ; //!< Maximum Number of Dual-Subslices 763 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 764 }; 765 uint32_t Value; 766 } DW4; 767 union 768 { 769 //!< DWORD 5 770 struct 771 { 772 uint32_t CurbeAllocationSize : __CODEGEN_BITFIELD( 0, 15) ; //!< CURBE Allocation Size 773 uint32_t UrbEntryAllocationSize : __CODEGEN_BITFIELD(16, 31) ; //!< URB Entry Allocation Size 774 }; 775 uint32_t Value; 776 } DW5; 777 union 778 { 779 //!< DWORD 6 780 struct 781 { 782 uint32_t Reserved192 ; //!< Reserved 783 }; 784 uint32_t Value; 785 } DW6; 786 union 787 { 788 //!< DWORD 7 789 struct 790 { 791 uint32_t Reserved224 ; //!< Reserved 792 }; 793 uint32_t Value; 794 } DW7; 795 union 796 { 797 //!< DWORD 8 798 struct 799 { 800 uint32_t Reserved256 ; //!< Reserved 801 }; 802 uint32_t Value; 803 } DW8; 804 805 //! \name Local enumerations 806 807 enum SUBOPCODE 808 { 809 SUBOPCODE_MEDIAVFESTATESUBOP = 0, //!< No additional details 810 }; 811 812 enum MEDIA_COMMAND_OPCODE 813 { 814 MEDIA_COMMAND_OPCODE_MEDIAVFESTATE = 0, //!< No additional details 815 }; 816 817 enum PIPELINE 818 { 819 PIPELINE_MEDIA = 2, //!< No additional details 820 }; 821 822 enum COMMAND_TYPE 823 { 824 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 825 }; 826 827 //! \brief DISPATCH_LOAD_BALANCE 828 //! \details 829 //! This bit determines how media threads are dispatched between the various 830 //! dual subslices. GPGPU threads are not impacted by this bit. 831 enum DISPATCH_LOAD_BALANCE 832 { 833 DISPATCH_LOAD_BALANCE_LEASTLOADED = 0, //!< When this value is used the threads are sent to the least loaded dual subslice of all active dual subslices. If media with groups is being used then each group is kept in the same dual subslice. 834 DISPATCH_LOAD_BALANCE_COLORLSB = 1, //!< When this value is used the threads are split into two groups depending on the LSB of the color value for media threads. One group will be sent to even dual subslices and the other to odd dual subslices. The least loaded active dual subslice available will selected for threads in that group. This allows color to be used to separate workloads with different operations to get better cache coherency.If media with groups is being used then each group is kept in the same dual subslices. 835 }; 836 837 //! \name Initializations 838 839 //! \brief Explicit member initialization function 840 MEDIA_VFE_STATE_CMD(); 841 842 static const size_t dwSize = 9; 843 static const size_t byteSize = 36; 844 }; 845 846 //! 847 //! \brief MEDIA_CURBE_LOAD 848 //! 849 struct MEDIA_CURBE_LOAD_CMD 850 { 851 union 852 { 853 //!< DWORD 0 854 struct 855 { 856 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 857 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 858 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 859 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 860 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 861 }; 862 uint32_t Value; 863 } DW0; 864 union 865 { 866 //!< DWORD 1 867 struct 868 { 869 uint32_t Reserved32 ; //!< Reserved 870 }; 871 uint32_t Value; 872 } DW1; 873 union 874 { 875 //!< DWORD 2 876 struct 877 { 878 uint32_t CurbeTotalDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< CURBE Total Data Length 879 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 880 }; 881 uint32_t Value; 882 } DW2; 883 union 884 { 885 //!< DWORD 3 886 struct 887 { 888 uint32_t CurbeDataStartAddress ; //!< CURBE Data Start Address 889 }; 890 uint32_t Value; 891 } DW3; 892 893 //! \name Local enumerations 894 895 enum SUBOPCODE 896 { 897 SUBOPCODE_MEDIACURBELOADSUBOP = 1, //!< No additional details 898 }; 899 900 enum MEDIA_COMMAND_OPCODE 901 { 902 MEDIA_COMMAND_OPCODE_MEDIACURBELOAD = 0, //!< No additional details 903 }; 904 905 enum PIPELINE 906 { 907 PIPELINE_MEDIA = 2, //!< No additional details 908 }; 909 910 enum COMMAND_TYPE 911 { 912 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 913 }; 914 915 //! \name Initializations 916 917 //! \brief Explicit member initialization function 918 MEDIA_CURBE_LOAD_CMD(); 919 920 static const size_t dwSize = 4; 921 static const size_t byteSize = 16; 922 }; 923 924 //! 925 //! \brief MEDIA_INTERFACE_DESCRIPTOR_LOAD 926 //! \details 927 //! A Media_State_Flush should be used before this command to ensure that 928 //! the temporary Interface Descriptor storage is cleared. 929 //! 930 struct MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD 931 { 932 union 933 { 934 //!< DWORD 0 935 struct 936 { 937 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 938 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 939 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 940 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 941 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 942 }; 943 uint32_t Value; 944 } DW0; 945 union 946 { 947 //!< DWORD 1 948 struct 949 { 950 uint32_t Reserved32 ; //!< Reserved 951 }; 952 uint32_t Value; 953 } DW1; 954 union 955 { 956 //!< DWORD 2 957 struct 958 { 959 uint32_t InterfaceDescriptorTotalLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Interface Descriptor Total Length 960 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 961 }; 962 uint32_t Value; 963 } DW2; 964 union 965 { 966 //!< DWORD 3 967 struct 968 { 969 uint32_t InterfaceDescriptorDataStartAddress ; //!< Interface Descriptor Data Start Address 970 }; 971 uint32_t Value; 972 } DW3; 973 974 //! \name Local enumerations 975 976 enum SUBOPCODE 977 { 978 SUBOPCODE_MEDIAINTERFACEDESCRIPTORLOADSUBOP = 2, //!< No additional details 979 }; 980 981 enum MEDIA_COMMAND_OPCODE 982 { 983 MEDIA_COMMAND_OPCODE_MEDIAINTERFACEDESCRIPTORLOAD = 0, //!< No additional details 984 }; 985 986 enum PIPELINE 987 { 988 PIPELINE_MEDIA = 2, //!< No additional details 989 }; 990 991 enum COMMAND_TYPE 992 { 993 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 994 }; 995 996 //! \name Initializations 997 998 //! \brief Explicit member initialization function 999 MEDIA_INTERFACE_DESCRIPTOR_LOAD_CMD(); 1000 1001 static const size_t dwSize = 4; 1002 static const size_t byteSize = 16; 1003 }; 1004 1005 //! 1006 //! \brief MEDIA_OBJECT_WALKER 1007 //! \details 1008 //! 1009 //! 1010 struct MEDIA_OBJECT_WALKER_CMD 1011 { 1012 union 1013 { 1014 //!< DWORD 0 1015 struct 1016 { 1017 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 14) ; //!< DWORD_LENGTH 1018 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1019 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 1020 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1021 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1022 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1023 }; 1024 uint32_t Value; 1025 } DW0; 1026 union 1027 { 1028 //!< DWORD 1 1029 struct 1030 { 1031 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 1032 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 1033 }; 1034 uint32_t Value; 1035 } DW1; 1036 union 1037 { 1038 //!< DWORD 2 1039 struct 1040 { 1041 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 1042 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 21) ; //!< Reserved 1043 uint32_t MaskedDispatch : __CODEGEN_BITFIELD(22, 23) ; //!< MASKED_DISPATCH 1044 uint32_t ThreadSynchronization : __CODEGEN_BITFIELD(24, 24) ; //!< THREAD_SYNCHRONIZATION 1045 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1046 }; 1047 uint32_t Value; 1048 } DW2; 1049 union 1050 { 1051 //!< DWORD 3 1052 struct 1053 { 1054 uint32_t IndirectDataStartAddress ; //!< Indirect Data Start Address 1055 }; 1056 uint32_t Value; 1057 } DW3; 1058 union 1059 { 1060 //!< DWORD 4 1061 struct 1062 { 1063 uint32_t Reserved128 ; //!< Reserved 1064 }; 1065 uint32_t Value; 1066 } DW4; 1067 union 1068 { 1069 //!< DWORD 5 1070 struct 1071 { 1072 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1073 uint32_t GroupIdLoopSelect : __CODEGEN_BITFIELD( 8, 31) ; //!< GROUP_ID_LOOP_SELECT 1074 }; 1075 uint32_t Value; 1076 } DW5; 1077 union 1078 { 1079 //!< DWORD 6 1080 struct 1081 { 1082 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1083 uint32_t MidLoopUnitX : __CODEGEN_BITFIELD( 8, 9) ; //!< Mid-Loop Unit X 1084 uint32_t Reserved202 : __CODEGEN_BITFIELD(10, 11) ; //!< Reserved 1085 uint32_t LocalMidLoopUnitY : __CODEGEN_BITFIELD(12, 13) ; //!< Local Mid-Loop Unit Y 1086 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1087 uint32_t MiddleLoopExtraSteps : __CODEGEN_BITFIELD(16, 20) ; //!< Middle Loop Extra Steps 1088 uint32_t Reserved213 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 1089 uint32_t ColorCountMinusOne : __CODEGEN_BITFIELD(24, 31) ; //!< Color Count Minus One 1090 }; 1091 uint32_t Value; 1092 } DW6; 1093 union 1094 { 1095 //!< DWORD 7 1096 struct 1097 { 1098 uint32_t LocalLoopExecCount : __CODEGEN_BITFIELD( 0, 11) ; //!< Local Loop Exec Count 1099 uint32_t Reserved236 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1100 uint32_t GlobalLoopExecCount : __CODEGEN_BITFIELD(16, 27) ; //!< Global Loop Exec Count 1101 uint32_t Reserved252 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1102 }; 1103 uint32_t Value; 1104 } DW7; 1105 union 1106 { 1107 //!< DWORD 8 1108 struct 1109 { 1110 uint32_t BlockResolutionX : __CODEGEN_BITFIELD( 0, 10) ; //!< Block Resolution X 1111 uint32_t Reserved267 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1112 uint32_t BlockResolutionY : __CODEGEN_BITFIELD(16, 26) ; //!< Block Resolution Y 1113 uint32_t Reserved283 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1114 }; 1115 uint32_t Value; 1116 } DW8; 1117 union 1118 { 1119 //!< DWORD 9 1120 struct 1121 { 1122 uint32_t LocalStartX : __CODEGEN_BITFIELD( 0, 10) ; //!< Local Start X 1123 uint32_t Reserved299 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1124 uint32_t LocalStartY : __CODEGEN_BITFIELD(16, 26) ; //!< Local Start Y 1125 uint32_t Reserved315 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1126 }; 1127 uint32_t Value; 1128 } DW9; 1129 union 1130 { 1131 //!< DWORD 10 1132 struct 1133 { 1134 uint32_t Reserved320 ; //!< Reserved 1135 }; 1136 uint32_t Value; 1137 } DW10; 1138 union 1139 { 1140 //!< DWORD 11 1141 struct 1142 { 1143 uint32_t LocalOuterLoopStrideX : __CODEGEN_BITFIELD( 0, 11) ; //!< Local Outer Loop Stride X 1144 uint32_t Reserved364 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1145 uint32_t LocalOuterLoopStrideY : __CODEGEN_BITFIELD(16, 27) ; //!< Local Outer Loop Stride Y 1146 uint32_t Reserved380 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1147 }; 1148 uint32_t Value; 1149 } DW11; 1150 union 1151 { 1152 //!< DWORD 12 1153 struct 1154 { 1155 uint32_t LocalInnerLoopUnitX : __CODEGEN_BITFIELD( 0, 11) ; //!< Local Inner Loop Unit X 1156 uint32_t Reserved396 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1157 uint32_t LocalInnerLoopUnitY : __CODEGEN_BITFIELD(16, 27) ; //!< Local Inner Loop Unit Y 1158 uint32_t Reserved412 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1159 }; 1160 uint32_t Value; 1161 } DW12; 1162 union 1163 { 1164 //!< DWORD 13 1165 struct 1166 { 1167 uint32_t GlobalResolutionX : __CODEGEN_BITFIELD( 0, 10) ; //!< Global Resolution X 1168 uint32_t Reserved427 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1169 uint32_t GlobalResolutionY : __CODEGEN_BITFIELD(16, 26) ; //!< Global Resolution Y 1170 uint32_t Reserved443 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1171 }; 1172 uint32_t Value; 1173 } DW13; 1174 union 1175 { 1176 //!< DWORD 14 1177 struct 1178 { 1179 uint32_t GlobalStartX : __CODEGEN_BITFIELD( 0, 11) ; //!< Global Start X 1180 uint32_t Reserved460 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1181 uint32_t GlobalStartY : __CODEGEN_BITFIELD(16, 27) ; //!< Global Start Y 1182 uint32_t Reserved476 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1183 }; 1184 uint32_t Value; 1185 } DW14; 1186 union 1187 { 1188 //!< DWORD 15 1189 struct 1190 { 1191 uint32_t GlobalOuterLoopStrideX : __CODEGEN_BITFIELD( 0, 11) ; //!< Global Outer Loop Stride X 1192 uint32_t Reserved492 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1193 uint32_t GlobalOuterLoopStrideY : __CODEGEN_BITFIELD(16, 27) ; //!< Global Outer Loop Stride Y 1194 uint32_t Reserved508 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1195 }; 1196 uint32_t Value; 1197 } DW15; 1198 union 1199 { 1200 //!< DWORD 16 1201 struct 1202 { 1203 uint32_t GlobalInnerLoopUnitX : __CODEGEN_BITFIELD( 0, 11) ; //!< Global Inner Loop Unit X 1204 uint32_t Reserved524 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1205 uint32_t GlobalInnerLoopUnitY : __CODEGEN_BITFIELD(16, 27) ; //!< Global Inner Loop Unit Y 1206 uint32_t Reserved540 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1207 }; 1208 uint32_t Value; 1209 } DW16; 1210 1211 //! \name Local enumerations 1212 1213 enum SUBOPCODE 1214 { 1215 SUBOPCODE_MEDIAOBJECTWALKERSUBOP = 3, //!< No additional details 1216 }; 1217 1218 enum MEDIA_COMMAND_OPCODE 1219 { 1220 MEDIA_COMMAND_OPCODE_MEDIAOBJECTWALKER = 1, //!< No additional details 1221 }; 1222 1223 enum PIPELINE 1224 { 1225 PIPELINE_MEDIA = 2, //!< No additional details 1226 }; 1227 1228 enum COMMAND_TYPE 1229 { 1230 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1231 }; 1232 1233 //! \brief MASKED_DISPATCH 1234 //! \details 1235 //! Enable the masking of the dispatch of individual threads based on a 1236 //! bitmask read from CURBE, and specifies the pitch of the CURBE surface. 1237 //! If enabled, CURBE will not be used for thread payload. 1238 enum MASKED_DISPATCH 1239 { 1240 MASKED_DISPATCH_UNNAMED0 = 0, //!< Masked Dispatch Disabled 1241 MASKED_DISPATCH_UNNAMED1 = 1, //!< Masked Dispatch with 128-bit pitch in CURBE 1242 MASKED_DISPATCH_UNNAMED2 = 2, //!< Masked Dispatch with 256-bit pitch in CURBE 1243 MASKED_DISPATCH_UNNAMED3 = 3, //!< Masked Dispatch with 512-bit pitch in CURBE 1244 }; 1245 1246 //! \brief THREAD_SYNCHRONIZATION 1247 //! \details 1248 //! This field when set indicates that the dispatch of the thread originated 1249 //! from this command is based on the "spawn root thread" message. 1250 enum THREAD_SYNCHRONIZATION 1251 { 1252 THREAD_SYNCHRONIZATION_NOTHREADSYNCHRONIZATION = 0, //!< No additional details 1253 THREAD_SYNCHRONIZATION_THREADDISPATCHISSYNCHRONIZEDBYTHESPAWNROOTTHREADMESSAGE = 1, //!< No additional details 1254 }; 1255 1256 //! \brief GROUP_ID_LOOP_SELECT 1257 //! \details 1258 //! This bit field chooses which of the nested loops of the walker are used 1259 //! to identify threads which share a group id and therefore a shared 1260 //! barrier and SLM. The programmer must ensure that each group will fit 1261 //! into a single subslice. When barriers are enabled every group must have 1262 //! the same number of threads matching the number specified in the 1263 //! Interface Descriptor. 1264 enum GROUP_ID_LOOP_SELECT 1265 { 1266 GROUP_ID_LOOP_SELECT_NOGROUPS = 0, //!< Groups are not created, barriers and SLM are not allocated 1267 GROUP_ID_LOOP_SELECT_COLORGROUPS = 1, //!< Each complete iteration of the Color loop defines a group, the group id is the concatenation of the Outer global, Inner global, Outer local, Mid local and Inner local loop execution counts. 1268 GROUP_ID_LOOP_SELECT_INNERLOCALGROUPS = 2, //!< Each complete iteration of the Inner local loop and Color loop defines a group, the group id is the concatenation of the Outer global loop to the Mid local loop execution counts. 1269 GROUP_ID_LOOP_SELECT_MIDLOCALGROUPS = 3, //!< Each complete iteration of the Mid local loop and lower loops defines a group, the group id is the concatenation of the Outer global loop to the Outer local loop execution counts. 1270 GROUP_ID_LOOP_SELECT_OUTERLOCALGROUPS = 4, //!< Each complete iteration of the Outer local loop and lower loops defines a group, the group id is the concatenation of the Outer global loop and the Inner global loop execution counts. 1271 GROUP_ID_LOOP_SELECT_INNERGLOBALGROUPS = 5, //!< Each complete iteration of the Inner global loop and lower loops defines a group, the group id is the Outer global loop execution count. 1272 }; 1273 1274 //! \name Initializations 1275 1276 //! \brief Explicit member initialization function 1277 MEDIA_OBJECT_WALKER_CMD(); 1278 1279 static const size_t dwSize = 17; 1280 static const size_t byteSize = 68; 1281 }; 1282 1283 //! 1284 //! \brief GPGPU_WALKER 1285 //! \details 1286 //! If the threads spawned by this command are required to observe memory 1287 //! writes performed by threads spawned from a previous command, software 1288 //! must precede this command with a command that performs a memory flush 1289 //! (e.g., MI_FLUSH). 1290 //! 1291 struct GPGPU_WALKER_CMD 1292 { 1293 union 1294 { 1295 //!< DWORD 0 1296 struct 1297 { 1298 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1299 uint32_t PredicateEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Predicate Enable 1300 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1301 uint32_t IndirectParameterEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Indirect Parameter Enable 1302 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 1303 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 1304 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1305 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1306 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1307 }; 1308 uint32_t Value; 1309 } DW0; 1310 union 1311 { 1312 //!< DWORD 1 1313 struct 1314 { 1315 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 1316 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 1317 }; 1318 uint32_t Value; 1319 } DW1; 1320 union 1321 { 1322 //!< DWORD 2 1323 struct 1324 { 1325 uint32_t IndirectDataLength : __CODEGEN_BITFIELD( 0, 16) ; //!< Indirect Data Length 1326 uint32_t Reserved81 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1327 }; 1328 uint32_t Value; 1329 } DW2; 1330 union 1331 { 1332 //!< DWORD 3 1333 struct 1334 { 1335 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1336 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Indirect Data Start Address 1337 }; 1338 uint32_t Value; 1339 } DW3; 1340 union 1341 { 1342 //!< DWORD 4 1343 struct 1344 { 1345 uint32_t ThreadWidthCounterMaximum : __CODEGEN_BITFIELD( 0, 5) ; //!< Thread Width Counter Maximum 1346 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1347 uint32_t ThreadHeightCounterMaximum : __CODEGEN_BITFIELD( 8, 13) ; //!< Thread Height Counter Maximum 1348 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1349 uint32_t ThreadDepthCounterMaximum : __CODEGEN_BITFIELD(16, 21) ; //!< Thread Depth Counter Maximum 1350 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 29) ; //!< Reserved 1351 uint32_t SimdSize : __CODEGEN_BITFIELD(30, 31) ; //!< SIMD_SIZE 1352 }; 1353 uint32_t Value; 1354 } DW4; 1355 union 1356 { 1357 //!< DWORD 5 1358 struct 1359 { 1360 uint32_t ThreadGroupIdStartingX ; //!< Thread Group ID Starting X 1361 }; 1362 uint32_t Value; 1363 } DW5; 1364 union 1365 { 1366 //!< DWORD 6 1367 struct 1368 { 1369 uint32_t Reserved192 ; //!< Reserved 1370 }; 1371 uint32_t Value; 1372 } DW6; 1373 union 1374 { 1375 //!< DWORD 7 1376 struct 1377 { 1378 uint32_t ThreadGroupIdXDimension ; //!< Thread Group ID X Dimension 1379 }; 1380 uint32_t Value; 1381 } DW7; 1382 union 1383 { 1384 //!< DWORD 8 1385 struct 1386 { 1387 uint32_t ThreadGroupIdStartingY ; //!< Thread Group ID Starting Y 1388 }; 1389 uint32_t Value; 1390 } DW8; 1391 union 1392 { 1393 //!< DWORD 9 1394 struct 1395 { 1396 uint32_t Reserved288 ; //!< Reserved 1397 }; 1398 uint32_t Value; 1399 } DW9; 1400 union 1401 { 1402 //!< DWORD 10 1403 struct 1404 { 1405 uint32_t ThreadGroupIdYDimension ; //!< Thread Group ID Y Dimension 1406 }; 1407 uint32_t Value; 1408 } DW10; 1409 union 1410 { 1411 //!< DWORD 11 1412 struct 1413 { 1414 uint32_t ThreadGroupIdStartingResumeZ ; //!< Thread Group ID Starting/Resume Z 1415 }; 1416 uint32_t Value; 1417 } DW11; 1418 union 1419 { 1420 //!< DWORD 12 1421 struct 1422 { 1423 uint32_t ThreadGroupIdZDimension ; //!< Thread Group ID Z Dimension 1424 }; 1425 uint32_t Value; 1426 } DW12; 1427 union 1428 { 1429 //!< DWORD 13 1430 struct 1431 { 1432 uint32_t RightExecutionMask ; //!< Right Execution Mask 1433 }; 1434 uint32_t Value; 1435 } DW13; 1436 union 1437 { 1438 //!< DWORD 14 1439 struct 1440 { 1441 uint32_t BottomExecutionMask ; //!< Bottom Execution Mask 1442 }; 1443 uint32_t Value; 1444 } DW14; 1445 1446 //! \name Local enumerations 1447 1448 enum SUBOPCODE 1449 { 1450 SUBOPCODE_GPGPUWALKERSUBOP = 5, //!< No additional details 1451 }; 1452 1453 enum MEDIA_COMMAND_OPCODE 1454 { 1455 MEDIA_COMMAND_OPCODE_GPGPUWALKER = 1, //!< No additional details 1456 }; 1457 1458 enum PIPELINE 1459 { 1460 PIPELINE_MEDIA = 2, //!< No additional details 1461 }; 1462 1463 enum COMMAND_TYPE 1464 { 1465 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1466 }; 1467 1468 //! \brief SIMD_SIZE 1469 //! \details 1470 //! This field determines the size of the payload and the number of bits of 1471 //! the execution mask that are expected. The kernel pointed to by the 1472 //! interface descriptor should match the SIMD declared here. 1473 enum SIMD_SIZE 1474 { 1475 SIMD_SIZE_SIMD8 = 0, //!< 8 LSBs of the execution mask are used 1476 SIMD_SIZE_SIMD16 = 1, //!< 16 LSBs used in execution mask 1477 SIMD_SIZE_SIMD32 = 2, //!< 32 bits of execution mask used 1478 }; 1479 1480 //! \name Initializations 1481 1482 //! \brief Explicit member initialization function 1483 GPGPU_WALKER_CMD(); 1484 1485 static const size_t dwSize = 15; 1486 static const size_t byteSize = 60; 1487 }; 1488 1489 //! 1490 //! \brief _3DSTATE_CHROMA_KEY 1491 //! \details 1492 //! The 3DSTATE_CHROMA_KEY instruction is used to program texture 1493 //! color/chroma-key key values. A table containing four set of values is 1494 //! supported. The ChromaKey Index sampler state variable is used to select 1495 //! which table entry is associated with the map. Texture chromakey 1496 //! functions are enabled and controlled via use of the ChromaKey Enable 1497 //! texture sampler state variable.Texture Color Key (keying on a paletted 1498 //! texture index) is not supported. 1499 //! 1500 //! This command must be followed by a PIPE_CONTROL with CS Stall bit 1501 //! set. 1502 //! 1503 struct _3DSTATE_CHROMA_KEY_CMD 1504 { 1505 union 1506 { 1507 //!< DWORD 0 1508 struct 1509 { 1510 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1511 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1512 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1513 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1514 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1515 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1516 }; 1517 uint32_t Value; 1518 } DW0; 1519 union 1520 { 1521 //!< DWORD 1 1522 struct 1523 { 1524 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 1525 uint32_t ChromakeyTableIndex : __CODEGEN_BITFIELD(30, 31) ; //!< ChromaKey Table Index 1526 }; 1527 uint32_t Value; 1528 } DW1; 1529 union 1530 { 1531 //!< DWORD 2 1532 struct 1533 { 1534 uint32_t ChromakeyLowValue ; //!< ChromaKey Low Value 1535 }; 1536 uint32_t Value; 1537 } DW2; 1538 union 1539 { 1540 //!< DWORD 3 1541 struct 1542 { 1543 uint32_t ChromakeyHighValue ; //!< ChromaKey High Value 1544 }; 1545 uint32_t Value; 1546 } DW3; 1547 1548 //! \name Local enumerations 1549 1550 enum _3D_COMMAND_SUB_OPCODE 1551 { 1552 _3D_COMMAND_SUB_OPCODE_3DSTATECHROMAKEY = 4, //!< No additional details 1553 }; 1554 1555 enum _3D_COMMAND_OPCODE 1556 { 1557 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1558 }; 1559 1560 enum COMMAND_SUBTYPE 1561 { 1562 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1563 }; 1564 1565 enum COMMAND_TYPE 1566 { 1567 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1568 }; 1569 1570 //! \name Initializations 1571 1572 //! \brief Explicit member initialization function 1573 _3DSTATE_CHROMA_KEY_CMD(); 1574 1575 static const size_t dwSize = 4; 1576 static const size_t byteSize = 16; 1577 }; 1578 1579 //! 1580 //! \brief _3DSTATE_SAMPLER_PALETTE_LOAD0 1581 //! \details 1582 //! The 3DSTATE_SAMPLER_PALETTE_LOAD0 instruction is used to load 32-bit 1583 //! values into the first texture palette. The texture palette is used 1584 //! whenever a texture with a paletted format (containing "Px [palette0]") 1585 //! is referenced by the sampler. 1586 //! 1587 //! This instruction is used to load all or a subset of the 256 entries of 1588 //! the first palette. Partial loads always start from the first (index 0) 1589 //! entry. 1590 //! 1591 //! This command must be followed by a PIPE_CONTROL with CS Stall bit 1592 //! set. 1593 //! 1594 struct _3DSTATE_SAMPLER_PALETTE_LOAD0_CMD 1595 { 1596 union 1597 { 1598 //!< DWORD 0 1599 struct 1600 { 1601 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWord Length 1602 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1603 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1604 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1605 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1606 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1607 }; 1608 uint32_t Value; 1609 } DW0; 1610 1611 //! \name Local enumerations 1612 1613 enum _3D_COMMAND_SUB_OPCODE 1614 { 1615 _3D_COMMAND_SUB_OPCODE_3DSTATESAMPLERPALETTELOAD0 = 2, //!< No additional details 1616 }; 1617 1618 enum _3D_COMMAND_OPCODE 1619 { 1620 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1621 }; 1622 1623 enum COMMAND_SUBTYPE 1624 { 1625 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1626 }; 1627 1628 enum COMMAND_TYPE 1629 { 1630 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1631 }; 1632 1633 //! \name Initializations 1634 1635 //! \brief Explicit member initialization function 1636 _3DSTATE_SAMPLER_PALETTE_LOAD0_CMD(); 1637 1638 static const size_t dwSize = 1; 1639 static const size_t byteSize = 4; 1640 }; 1641 1642 //! 1643 //! \brief _3DSTATE_SAMPLER_PALETTE_LOAD1 1644 //! \details 1645 //! The 3DSTATE_SAMPLER_PALETTE_LOAD1 instruction is used to load 32-bit 1646 //! values into the second texture palette. The second texture palette is 1647 //! used whenever a texture with a paletted format (containing 1648 //! "Px...[palette1]") is referenced by the sampler.This instruction is used 1649 //! to load all or a subset of the 256 entries of the second palette. 1650 //! Partial loads always start from the first (index 0) entry. 1651 //! 1652 //! This command must be followed by a PIPE_CONTROL with CS Stall bit 1653 //! set. 1654 //! 1655 struct _3DSTATE_SAMPLER_PALETTE_LOAD1_CMD 1656 { 1657 union 1658 { 1659 //!< DWORD 0 1660 struct 1661 { 1662 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1663 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1664 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1665 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1666 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1667 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1668 }; 1669 uint32_t Value; 1670 } DW0; 1671 1672 //! \name Local enumerations 1673 1674 enum _3D_COMMAND_SUB_OPCODE 1675 { 1676 _3D_COMMAND_SUB_OPCODE_3DSTATESAMPLERPALETTELOAD1 = 12, //!< No additional details 1677 }; 1678 1679 enum _3D_COMMAND_OPCODE 1680 { 1681 _3D_COMMAND_OPCODE_3DSTATENONPIPELINED = 1, //!< No additional details 1682 }; 1683 1684 enum COMMAND_SUBTYPE 1685 { 1686 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1687 }; 1688 1689 enum COMMAND_TYPE 1690 { 1691 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1692 }; 1693 1694 //! \name Initializations 1695 1696 //! \brief Explicit member initialization function 1697 _3DSTATE_SAMPLER_PALETTE_LOAD1_CMD(); 1698 1699 static const size_t dwSize = 1; 1700 static const size_t byteSize = 4; 1701 }; 1702 1703 //! 1704 //! \brief PALETTE_ENTRY 1705 //! \details 1706 //! 1707 //! 1708 struct PALETTE_ENTRY_CMD 1709 { 1710 union 1711 { 1712 //!< DWORD 0 1713 struct 1714 { 1715 uint32_t Blue : __CODEGEN_BITFIELD( 0, 7) ; //!< Blue 1716 uint32_t Green : __CODEGEN_BITFIELD( 8, 15) ; //!< Green 1717 uint32_t Red : __CODEGEN_BITFIELD(16, 23) ; //!< Red 1718 uint32_t Alpha : __CODEGEN_BITFIELD(24, 31) ; //!< Alpha 1719 }; 1720 uint32_t Value; 1721 } DW0; 1722 1723 //! \name Local enumerations 1724 1725 //! \name Initializations 1726 1727 //! \brief Explicit member initialization function 1728 PALETTE_ENTRY_CMD(); 1729 1730 static const size_t dwSize = 1; 1731 static const size_t byteSize = 4; 1732 }; 1733 1734 //! 1735 //! \brief STATE_SIP 1736 //! \details 1737 //! The STATE_SIP command specifies the starting instruction location of the 1738 //! System Routine that is shared by all threads in execution. 1739 //! 1740 //! This command must be followed by a PIPE_CONTROL with CS Stall bit 1741 //! set. 1742 //! 1743 struct STATE_SIP_CMD 1744 { 1745 union 1746 { 1747 //!< DWORD 0 1748 struct 1749 { 1750 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1751 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1752 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1753 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1754 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1755 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1756 }; 1757 uint32_t Value; 1758 } DW0; 1759 union 1760 { 1761 //!< DWORD 1..2 1762 struct 1763 { 1764 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 1765 uint64_t SystemInstructionPointer : __CODEGEN_BITFIELD( 4, 63) ; //!< System Instruction Pointer 1766 }; 1767 uint32_t Value[2]; 1768 } DW1_2; 1769 1770 //! \name Local enumerations 1771 1772 enum _3D_COMMAND_SUB_OPCODE 1773 { 1774 _3D_COMMAND_SUB_OPCODE_STATESIP = 2, //!< No additional details 1775 }; 1776 1777 enum _3D_COMMAND_OPCODE 1778 { 1779 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 1780 }; 1781 1782 enum COMMAND_SUBTYPE 1783 { 1784 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 1785 }; 1786 1787 enum COMMAND_TYPE 1788 { 1789 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1790 }; 1791 1792 //! \name Initializations 1793 1794 //! \brief Explicit member initialization function 1795 STATE_SIP_CMD(); 1796 1797 static const size_t dwSize = 3; 1798 static const size_t byteSize = 12; 1799 }; 1800 1801 //! 1802 //! \brief STATE_CSR_BASE_ADDRESS 1803 //! \details 1804 //! The STATE_CSR_BASE_ADDRESS command sets the base pointers for EU and L3 1805 //! to Context Save and Restore EU State and SLM for GPGPU mid-thread 1806 //! preemption and URB for high priority preemption. 1807 //! 1808 //! This command must be programmed with allocated memory to the support the 1809 //! size of the context to be saved and restored during a GPGPU mid-thread 1810 //! preemption or a high priority suspend of a 3D context. 1811 //! 1812 struct STATE_CSR_BASE_ADDRESS_CMD 1813 { 1814 union 1815 { 1816 //!< DWORD 0 1817 struct 1818 { 1819 uint32_t DwordLength : __CODEGEN_BITFIELD(0, 7); //!< DWORD_LENGTH 1820 uint32_t Reserved8 : __CODEGEN_BITFIELD(8, 15); //!< Reserved 1821 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23); //!< _3D_COMMAND_SUB_OPCODE 1822 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26); //!< _3D_COMMAND_OPCODE 1823 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28); //!< COMMAND_SUBTYPE 1824 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31); //!< COMMAND_TYPE 1825 }; 1826 uint32_t Value; 1827 } DW0; 1828 union 1829 { 1830 //!< DWORD 1..2 1831 struct 1832 { 1833 uint64_t Reserved32 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 1834 uint64_t CsrBaseAddress : __CODEGEN_BITFIELD(12, 63); //!< CSR Base Address 1835 }; 1836 uint32_t Value[2]; 1837 } DW1_2; 1838 1839 //! \name Local enumerations 1840 1841 enum _3D_COMMAND_SUB_OPCODE 1842 { 1843 _3D_COMMAND_SUB_OPCODE_STATECSRBASEADDRESS = 4, //!< No additional details 1844 }; 1845 1846 enum _3D_COMMAND_OPCODE 1847 { 1848 _3D_COMMAND_OPCODE_GFXPIPENONPIPELINED = 1, //!< No additional details 1849 }; 1850 1851 enum COMMAND_SUBTYPE 1852 { 1853 COMMAND_SUBTYPE_GFXPIPECOMMON = 0, //!< No additional details 1854 }; 1855 1856 enum COMMAND_TYPE 1857 { 1858 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1859 }; 1860 1861 //! \name Initializations 1862 1863 //! \brief Explicit member initialization function 1864 STATE_CSR_BASE_ADDRESS_CMD(); 1865 1866 static const size_t dwSize = 3; 1867 static const size_t byteSize = 12; 1868 }; 1869 }; 1870 1871 #pragma pack() 1872 1873 #endif // __MHW_RENDER_HWCMD_G11_X_H__