1 /*
2 * Copyright (c) 2014-2017, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_render_g9_X.cpp
24 //! \brief Constructs render engine commands on Gen9-based platforms
25 //! \details Each client facing function both creates a HW command and adds
26 //! that command to a command or batch buffer.
27 //!
28
29 #include "mhw_render_g9_X.h"
30 #include "mhw_render_hwcmd_g9_X.h"
31 #include "mhw_mmio_g9.h"
32
33 static const uint32_t l3CacheCntl2RegisterOffset = L3_CACHE_CNTL2_REG_OFFSET_G9;
34 static const uint32_t l3CacheCntl3RegisterOffset = L3_CACHE_CNTL3_REG_OFFSET_G9;
35 static const uint32_t l3CacheSqc1RegisterOffset = L3_CACHE_SQC_REG_OFFSET_G9;
36
37 // SLM URB DC RO I/S C T
38 // { 0, 248, 8, 256, 0, 0, 0, }, // default for GT1/GT2
39 static const uint32_t l3CacheCntl2RegisterValue = 0x0028003E;
40 static const uint32_t l3CacheCntl3RegisterValue = 0;
41 static const uint32_t l3CacheSqc1RegisterValue = 0x610000;
42
43 //! \brief for BDW GT2 with WA for D0 hang
44 //! SLM URB DC RO Rest
45 //! 256 128 0 0 384 (KB chunks based on GT2)
46 static const uint32_t l3CacheCntlRegisterValueAllocateSlmD0Wa = 0x60000021;
47
AddMediaVfeCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VFE_PARAMS params)48 MOS_STATUS MhwRenderInterfaceG9::AddMediaVfeCmd(
49 PMOS_COMMAND_BUFFER cmdBuffer,
50 PMHW_VFE_PARAMS params)
51 {
52 MHW_FUNCTION_ENTER;
53
54 MHW_MI_CHK_NULL(cmdBuffer);
55 MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
56 MHW_MI_CHK_NULL(params);
57
58 mhw_render_g9_X::MEDIA_VFE_STATE_CMD *cmd =
59 (mhw_render_g9_X::MEDIA_VFE_STATE_CMD*)cmdBuffer->pCmdPtr;
60
61 MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g9_X>::AddMediaVfeCmd(cmdBuffer, params));
62
63 MHW_MI_CHK_NULL(cmd);
64 cmd->DW4.SliceDisable = params->eVfeSliceDisable;
65
66 cmd->DW6.ScoreboardType = params->Scoreboard.ScoreboardType;
67 cmd->DW6.ScoreboardMask = params->Scoreboard.ScoreboardMask;
68 cmd->DW6.ScoreboardEnable = params->Scoreboard.ScoreboardEnable;
69
70 cmd->DW7.Scoreboard0DeltaX = params->Scoreboard.ScoreboardDelta[0].x;
71 cmd->DW7.Scoreboard0DeltaY = params->Scoreboard.ScoreboardDelta[0].y;
72 cmd->DW7.Scoreboard1DeltaX = params->Scoreboard.ScoreboardDelta[1].x;
73 cmd->DW7.Scoreboard1DeltaY = params->Scoreboard.ScoreboardDelta[1].y;
74 cmd->DW7.Scoreboard2DeltaX = params->Scoreboard.ScoreboardDelta[2].x;
75 cmd->DW7.Scoreboard2DeltaY = params->Scoreboard.ScoreboardDelta[2].y;
76 cmd->DW7.Scoreboard3DeltaX = params->Scoreboard.ScoreboardDelta[3].x;
77 cmd->DW7.Scoreboard3DeltaY = params->Scoreboard.ScoreboardDelta[3].y;
78
79 cmd->DW8.Scoreboard4DeltaX = params->Scoreboard.ScoreboardDelta[4].x;
80 cmd->DW8.Scoreboard4DeltaY = params->Scoreboard.ScoreboardDelta[4].y;
81 cmd->DW8.Scoreboard5DeltaX = params->Scoreboard.ScoreboardDelta[5].x;
82 cmd->DW8.Scoreboard5DeltaY = params->Scoreboard.ScoreboardDelta[5].y;
83 cmd->DW8.Scoreboard6DeltaX = params->Scoreboard.ScoreboardDelta[6].x;
84 cmd->DW8.Scoreboard6DeltaY = params->Scoreboard.ScoreboardDelta[6].y;
85 cmd->DW8.Scoreboard7DeltaX = params->Scoreboard.ScoreboardDelta[7].x;
86 cmd->DW8.Scoreboard7DeltaY = params->Scoreboard.ScoreboardDelta[7].y;
87
88 return MOS_STATUS_SUCCESS;
89 }
90
AddPipelineSelectCmd(PMOS_COMMAND_BUFFER cmdBuffer,bool gpGpuPipe)91 MOS_STATUS MhwRenderInterfaceG9::AddPipelineSelectCmd(
92 PMOS_COMMAND_BUFFER cmdBuffer,
93 bool gpGpuPipe)
94 {
95 MHW_FUNCTION_ENTER;
96
97 MHW_MI_CHK_NULL(cmdBuffer);
98 MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
99
100 mhw_render_g9_X::PIPELINE_SELECT_CMD *cmd =
101 (mhw_render_g9_X::PIPELINE_SELECT_CMD*)cmdBuffer->pCmdPtr;
102
103 MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g9_X>::AddPipelineSelectCmd(cmdBuffer, gpGpuPipe));
104
105 MHW_MI_CHK_NULL(cmd);
106 cmd->DW0.MaskBits = 0x13;
107
108 return MOS_STATUS_SUCCESS;
109 }
110
AddMediaObjectWalkerCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_WALKER_PARAMS params)111 MOS_STATUS MhwRenderInterfaceG9::AddMediaObjectWalkerCmd(
112 PMOS_COMMAND_BUFFER cmdBuffer,
113 PMHW_WALKER_PARAMS params)
114 {
115 MHW_FUNCTION_ENTER;
116
117 MHW_MI_CHK_NULL(cmdBuffer);
118 MHW_MI_CHK_NULL(params);
119
120 mhw_render_g9_X::MEDIA_OBJECT_WALKER_CMD *cmd =
121 (mhw_render_g9_X::MEDIA_OBJECT_WALKER_CMD*)cmdBuffer->pCmdPtr;
122
123 MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g9_X>::AddMediaObjectWalkerCmd(cmdBuffer, params));
124
125 MHW_MI_CHK_NULL(cmd);
126 cmd->DW2.UseScoreboard = params->UseScoreboard;
127 cmd->DW5.ScoreboardMask = params->ScoreboardMask;
128
129 return MOS_STATUS_SUCCESS;
130 }
131
AddMediaObject(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer,PMHW_MEDIA_OBJECT_PARAMS params)132 MOS_STATUS MhwRenderInterfaceG9::AddMediaObject(
133 PMOS_COMMAND_BUFFER cmdBuffer,
134 PMHW_BATCH_BUFFER batchBuffer,
135 PMHW_MEDIA_OBJECT_PARAMS params)
136 {
137 MHW_FUNCTION_ENTER;
138
139 MHW_MI_CHK_NULL(params);
140
141 mhw_render_g9_X::MEDIA_OBJECT_CMD *cmd;
142 if (cmdBuffer)
143 {
144 cmd = (mhw_render_g9_X::MEDIA_OBJECT_CMD*)cmdBuffer->pCmdPtr;
145 }
146 else if (batchBuffer)
147 {
148 cmd = (mhw_render_g9_X::MEDIA_OBJECT_CMD*)(batchBuffer->pData + batchBuffer->iCurrent);
149 }
150 else
151 {
152 MHW_ASSERTMESSAGE("No valid buffer to add the command to!");
153 return MOS_STATUS_INVALID_PARAMETER;
154 }
155
156 MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g9_X>::AddMediaObject(cmdBuffer, batchBuffer, params));
157
158 MHW_MI_CHK_NULL(cmd);
159 cmd->DW2.UseScoreboard = params->VfeScoreboard.ScoreboardEnable;
160 cmd->DW4.ScoreboardX = params->VfeScoreboard.Value[0];
161 cmd->DW4.ScoredboardY = params->VfeScoreboard.Value[1];
162 cmd->DW5.ScoreboardMask = params->VfeScoreboard.ScoreboardMask;
163 cmd->DW5.ScoreboardColor = params->VfeScoreboard.ScoreboardColor;
164
165 return MOS_STATUS_SUCCESS;
166 }
167
AddPaletteLoadCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_PALETTE_PARAMS params)168 MOS_STATUS MhwRenderInterfaceG9::AddPaletteLoadCmd(
169 PMOS_COMMAND_BUFFER cmdBuffer,
170 PMHW_PALETTE_PARAMS params)
171 {
172 MHW_FUNCTION_ENTER;
173
174 MHW_MI_CHK_NULL(m_osInterface);
175 MHW_MI_CHK_NULL(cmdBuffer);
176 MHW_MI_CHK_NULL(params);
177 MHW_MI_CHK_NULL(params->pPaletteData);
178
179 if (params->iNumEntries <= 0)
180 {
181 MHW_ASSERTMESSAGE("Invalid number of palette entries.");
182 return MOS_STATUS_INVALID_PARAMETER;
183 }
184
185 // Send Palettes in use
186 if (params->iPaletteID == 0)
187 {
188 mhw_render_g9_X::_3DSTATE_SAMPLER_PALETTE_LOAD0_CMD cmd;
189 // Set size of palette load command
190 cmd.DW0.DwordLength = params->iNumEntries - 1;
191 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
192 }
193 else if (params->iPaletteID == 1)
194 {
195 mhw_render_g9_X::_3DSTATE_SAMPLER_PALETTE_LOAD1_CMD cmd;
196 // Set size of palette load command
197 cmd.DW0.DwordLength = params->iNumEntries - 1;
198 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
199 }
200 else
201 {
202 MHW_ASSERTMESSAGE("Invalid palette ID specified: %d.", params->iPaletteID);
203 return MOS_STATUS_INVALID_PARAMETER;
204 }
205
206 mhw_render_g9_X::PALETTE_ENTRY_CMD entry;
207 uint32_t cmdSize = entry.byteSize * params->iNumEntries;
208
209 // Send palette load command followed by palette data
210 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, params->pPaletteData, cmdSize));
211
212 return MOS_STATUS_SUCCESS;
213 }
214
AddGpgpuCsrBaseAddrCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMOS_RESOURCE csrResource)215 MOS_STATUS MhwRenderInterfaceG9::AddGpgpuCsrBaseAddrCmd(
216 PMOS_COMMAND_BUFFER cmdBuffer,
217 PMOS_RESOURCE csrResource)
218 {
219 MHW_MI_CHK_NULL(m_osInterface);
220 MHW_MI_CHK_NULL(cmdBuffer);
221 MHW_MI_CHK_NULL(csrResource);
222
223 #if (EMUL)
224 MHW_NORMALMESSAGE("GPGPU_CSR_BASE_ADDRESS not supported.");
225 return MOS_STATUS_SUCCESS;
226 #endif
227
228 mhw_render_g9_X::GPGPU_CSR_BASE_ADDRESS_CMD cmd;
229 MHW_RESOURCE_PARAMS resourceParams;
230 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams));
231 resourceParams.presResource = csrResource;
232 resourceParams.pdwCmd = cmd.DW1_2.Value;
233 resourceParams.dwLocationInCmd = 1;
234
235 MHW_MI_CHK_STATUS(AddResourceToCmd(
236 m_osInterface,
237 cmdBuffer,
238 &resourceParams));
239
240 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
241
242 return MOS_STATUS_SUCCESS;
243 }
244
245 //!
246 //! \brief Enables L3 cacheing flag and sets related registers/values
247 //! \details Client facing function to enable L3 cacheing flag and sets related registers/values
248 //! \param PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS cacheSettings
249 //! [in] L3 cache setting struct for render engine
250 //! \return MOS_STATUS
251 //! MOS_STATUS_SUCCESS if success, else fail reason
252 //!
EnableL3Caching(PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS cacheSettings)253 MOS_STATUS MhwRenderInterfaceG9::EnableL3Caching(
254 PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS cacheSettings)
255 {
256 m_l3CacheConfig.dwL3CacheCntlReg2_Register = l3CacheCntl2RegisterOffset;
257 m_l3CacheConfig.dwL3CacheCntlReg3_Register = l3CacheCntl3RegisterOffset;
258 m_l3CacheConfig.dwL3CacheSqcReg1_Register = l3CacheSqc1RegisterOffset;
259 m_l3CacheConfig.dwL3CacheCntlReg_Register = m_l3CacheCntlRegisterOffset;
260
261 if ( cacheSettings )
262 {
263 m_l3CacheConfig.bL3CachingEnabled = true;
264
265 m_l3CacheConfig.dwL3CacheCntlReg2_Setting = cacheSettings->dwCntlReg2;
266 m_l3CacheConfig.dwL3CacheCntlReg3_Setting = cacheSettings->dwCntlReg3;
267 m_l3CacheConfig.dwL3CacheSqcReg1_Setting = cacheSettings->dwSqcReg1;
268 m_l3CacheConfig.dwL3CacheCntlReg_Setting = cacheSettings->dwCntlReg;
269 }
270 else
271 {
272 // L3 Caching enabled by default
273 m_l3CacheConfig.bL3CachingEnabled = m_osInterface->bSimIsActive ? false : true;
274
275 m_l3CacheConfig.dwL3CacheCntlReg2_Setting = l3CacheCntl2RegisterValue;
276 m_l3CacheConfig.dwL3CacheCntlReg3_Setting = l3CacheCntl3RegisterValue;
277 m_l3CacheConfig.dwL3CacheSqcReg1_Setting = l3CacheSqc1RegisterValue;
278 m_l3CacheConfig.dwL3CacheCntlReg_Setting = m_l3CacheCntlRegisterValueDefault;
279 }
280
281 return MOS_STATUS_SUCCESS;
282 }
283
SetL3Cache(PMOS_COMMAND_BUFFER cmdBuffer)284 MOS_STATUS MhwRenderInterfaceG9::SetL3Cache(
285 PMOS_COMMAND_BUFFER cmdBuffer )
286 {
287 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
288
289 MHW_MI_CHK_NULL( cmdBuffer );
290
291 if ( m_l3CacheConfig.bL3CachingEnabled )
292 {
293 MHW_MI_LOAD_REGISTER_IMM_PARAMS loadRegisterParams;
294 MOS_ZeroMemory( &loadRegisterParams, sizeof( loadRegisterParams ) );
295 loadRegisterParams.dwRegister = m_l3CacheConfig.dwL3CacheCntlReg_Register;
296 loadRegisterParams.dwData = m_l3CacheConfig.dwL3CacheCntlReg_Setting;
297 MHW_MI_CHK_STATUS( m_miInterface->AddMiLoadRegisterImmCmd( cmdBuffer, &loadRegisterParams ) );
298 }
299
300 return eStatus;
301 }
302
InitMmioRegisters()303 void MhwRenderInterfaceG9::InitMmioRegisters()
304 {
305 MHW_MI_MMIOREGISTERS *mmioRegisters = &m_mmioRegisters;
306 mmioRegisters->generalPurposeRegister0LoOffset = CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G9;
307 mmioRegisters->generalPurposeRegister0HiOffset = CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G9;
308 mmioRegisters->generalPurposeRegister4LoOffset = CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G9;
309 mmioRegisters->generalPurposeRegister4HiOffset = CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G9;
310 mmioRegisters->generalPurposeRegister11LoOffset = CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G9;
311 mmioRegisters->generalPurposeRegister11HiOffset = CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G9;
312 mmioRegisters->generalPurposeRegister12LoOffset = CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G9;
313 mmioRegisters->generalPurposeRegister12HiOffset = CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G9;
314 }
315