1 /* 2 * Copyright (c) 2015-2020, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_render_g11_X.h 24 //! \brief Defines functions for constructing render engine commands on Gen11-based platforms 25 //! 26 27 #ifndef __MHW_RENDER_G11_X_H__ 28 #define __MHW_RENDER_G11_X_H__ 29 30 #include "mhw_render_generic.h" 31 #include "mhw_render_hwcmd_g11_X.h" 32 #include "mhw_state_heap_g11.h" 33 34 typedef struct MHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G11 : MHW_RENDER_ENGINE_L3_CACHE_SETTINGS 35 { 36 uint32_t dwTcCntlReg = 0; 37 } *PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G11; 38 39 typedef struct MHW_RENDER_ENGINE_L3_CACHE_CONFIG_G11 : MHW_RENDER_ENGINE_L3_CACHE_CONFIG 40 { 41 uint32_t dwL3CacheTcCntlReg_Register = 0; 42 uint32_t dwL3CacheTcCntlReg_Setting = 0; 43 } *PMHW_RENDER_ENGINE_L3_CACHE_CONFIG_G11; 44 45 class MhwRenderInterfaceG11 : public MhwRenderInterfaceGeneric<mhw_render_g11_X> 46 { 47 public: MhwRenderInterfaceG11(MhwMiInterface * miInterface,PMOS_INTERFACE osInterface,MEDIA_SYSTEM_INFO * gtSystemInfo,uint8_t newStateHeapManagerRequested)48 MhwRenderInterfaceG11( 49 MhwMiInterface *miInterface, 50 PMOS_INTERFACE osInterface, 51 MEDIA_SYSTEM_INFO *gtSystemInfo, 52 uint8_t newStateHeapManagerRequested) : 53 MhwRenderInterfaceGeneric(miInterface, osInterface, gtSystemInfo, newStateHeapManagerRequested) 54 { 55 MHW_FUNCTION_ENTER; 56 57 // L3 Cache size per bank = 384 KB. 58 // {SLM, URB, DC, RO(I/S, C, T), L3 Client Pool} 59 // { 0, 64, 0, 0, 320 } 60 m_l3CacheCntlRegisterValueDefault = 0xA0000620; 61 62 InitMmioRegisters(); 63 } 64 ~MhwRenderInterfaceG11()65 virtual ~MhwRenderInterfaceG11() { MHW_FUNCTION_ENTER; } 66 67 MOS_STATUS AddMediaVfeCmd( 68 PMOS_COMMAND_BUFFER cmdBuffer, 69 PMHW_VFE_PARAMS params); 70 71 MOS_STATUS AddPipelineSelectCmd( 72 PMOS_COMMAND_BUFFER cmdBuffer, 73 bool gpGpuPipe); 74 75 MOS_STATUS AddMediaObject( 76 PMOS_COMMAND_BUFFER cmdBuffer, 77 PMHW_BATCH_BUFFER batchBuffer, 78 PMHW_MEDIA_OBJECT_PARAMS params); 79 80 MOS_STATUS AddPaletteLoadCmd( 81 PMOS_COMMAND_BUFFER cmdBuffer, 82 PMHW_PALETTE_PARAMS params); 83 84 MOS_STATUS AddGpgpuCsrBaseAddrCmd( 85 PMOS_COMMAND_BUFFER cmdBuffer, 86 PMOS_RESOURCE csrResource); 87 88 MOS_STATUS EnableL3Caching( 89 PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS cacheSettings); 90 91 MOS_STATUS SetL3Cache( 92 PMOS_COMMAND_BUFFER cmdBuffer ); 93 GetL3CacheConfig()94 MHW_RENDER_ENGINE_L3_CACHE_CONFIG* GetL3CacheConfig() { return &m_l3CacheConfig; } 95 GetMmioRegisters()96 virtual PMHW_MI_MMIOREGISTERS GetMmioRegisters() 97 { 98 return &m_mmioRegisters; 99 } 100 101 //! 102 //! \brief Get AVS sampler state Inc unit 103 //! \details Get AVS sampler state Inc unit 104 //! \return [out] uint32_t 105 //! AVS sampler unit. GetSamplerStateAVSIncUnit()106 virtual uint32_t GetSamplerStateAVSIncUnit() { return MHW_SAMPLER_STATE_AVS_INC_G11; } 107 108 //! 109 //! \brief Get Conv sampler state Inc unit 110 //! \details Get Conv sampler state Inc unit 111 //! \return [out] uint32_t 112 //! Conv sampler unit. GetSamplerStateConvIncUnit()113 virtual uint32_t GetSamplerStateConvIncUnit() { return MHW_SAMPLER_STATE_CONV_INC_G11; } 114 115 //! 116 //! \brief Get the sampler height and width align unit 117 //! \details NV12 format needs the width and height to be a multiple of some unit 118 //! \param [in] bool 119 //! true if AVS sampler, false otherwise 120 //! \param [in, out] uint32_t 121 //! weight align unit 122 //! \param [in, out] uint32_t 123 //! height align unit GetSamplerResolutionAlignUnit(bool isAVSSampler,uint32_t & widthAlignUnit,uint32_t & heightAlignUnit)124 virtual void GetSamplerResolutionAlignUnit(bool isAVSSampler, uint32_t &widthAlignUnit, uint32_t &heightAlignUnit) 125 { 126 // enable 2 plane NV12 when width is not multiple of 2 or height is 127 // not multiple of 4. For AVS sampler, no limitation for 4 alignment. 128 widthAlignUnit = isAVSSampler ? MHW_AVS_SAMPLER_WIDTH_ALIGN_UNIT : MHW_SAMPLER_WIDTH_ALIGN_UNIT_G11; 129 heightAlignUnit = isAVSSampler ? MHW_AVS_SAMPLER_HEIGHT_ALIGN_UNIT : MHW_SAMPLER_HEIGHT_ALIGN_UNIT_G11; 130 } 131 132 protected: 133 MHW_RENDER_ENGINE_L3_CACHE_CONFIG_G11 m_l3CacheConfig; 134 135 uint32_t m_l3CacheTcCntlRegisterOffset = 0xB0A4; 136 uint32_t m_l3CacheTcCntlRegisterValueDefault = 0x0000000D; 137 138 private: 139 //! \brief Mmio registers address 140 MHW_MI_MMIOREGISTERS m_mmioRegisters = {}; 141 void InitMmioRegisters(); 142 }; 143 144 145 146 #endif 147