xref: /aosp_15_r20/external/intel-media-driver/media_driver/agnostic/gen11/hw/mhw_render_g11_X.cpp (revision ba62d9d3abf0e404f2022b4cd7a85e107f48596f)
1 /*
2 * Copyright (c) 2015-2017, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file     mhw_render_g11_X.cpp
24 //! \brief    Constructs render engine commands on Gen11-based platforms
25 //! \details  Each client facing function both creates a HW command and adds
26 //!           that command to a command or batch buffer.
27 //!
28 
29 #include "mhw_render_g11_X.h"
30 #include "mhw_render_hwcmd_g11_X.h"
31 #include "mhw_mmio_g11.h"
32 
AddMediaVfeCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VFE_PARAMS params)33 MOS_STATUS MhwRenderInterfaceG11::AddMediaVfeCmd(
34     PMOS_COMMAND_BUFFER             cmdBuffer,
35     PMHW_VFE_PARAMS                 params)
36 {
37     MHW_FUNCTION_ENTER;
38 
39     MHW_MI_CHK_NULL(cmdBuffer);
40     MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
41     MHW_MI_CHK_NULL(params);
42 
43     mhw_render_g11_X::MEDIA_VFE_STATE_CMD *cmd =
44         (mhw_render_g11_X::MEDIA_VFE_STATE_CMD*)cmdBuffer->pCmdPtr;
45 
46     MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g11_X>::AddMediaVfeCmd(cmdBuffer, params));
47 
48     MHW_MI_CHK_NULL(cmd);
49     cmd->DW4.MaximumNumberOfDualSubslices = params->eVfeSliceDisable;
50 
51     return MOS_STATUS_SUCCESS;
52 }
53 
AddPipelineSelectCmd(PMOS_COMMAND_BUFFER cmdBuffer,bool gpGpuPipe)54 MOS_STATUS MhwRenderInterfaceG11::AddPipelineSelectCmd(
55     PMOS_COMMAND_BUFFER             cmdBuffer,
56     bool                            gpGpuPipe)
57 {
58     MHW_FUNCTION_ENTER;
59 
60     MHW_MI_CHK_NULL(cmdBuffer);
61     MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
62 
63     mhw_render_g11_X::PIPELINE_SELECT_CMD *cmd =
64         (mhw_render_g11_X::PIPELINE_SELECT_CMD*)cmdBuffer->pCmdPtr;
65 
66     MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g11_X>::AddPipelineSelectCmd(cmdBuffer, gpGpuPipe));
67 
68     MHW_MI_CHK_NULL(cmd);
69     cmd->DW0.MaskBits = 0x13;
70 
71     return MOS_STATUS_SUCCESS;
72 }
73 
AddMediaObject(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer,PMHW_MEDIA_OBJECT_PARAMS params)74 MOS_STATUS MhwRenderInterfaceG11::AddMediaObject(
75     PMOS_COMMAND_BUFFER             cmdBuffer,
76     PMHW_BATCH_BUFFER               batchBuffer,
77     PMHW_MEDIA_OBJECT_PARAMS        params)
78 {
79     MHW_FUNCTION_ENTER;
80 
81     MHW_MI_CHK_NULL(params);
82 
83     mhw_render_g11_X::MEDIA_OBJECT_CMD *cmd;
84     if (cmdBuffer)
85     {
86         cmd = (mhw_render_g11_X::MEDIA_OBJECT_CMD*)cmdBuffer->pCmdPtr;
87     }
88     else if (batchBuffer)
89     {
90         cmd = (mhw_render_g11_X::MEDIA_OBJECT_CMD*)(batchBuffer->pData + batchBuffer->iCurrent);
91     }
92     else
93     {
94         MHW_ASSERTMESSAGE("No valid buffer to add the command to!");
95         return MOS_STATUS_INVALID_PARAMETER;
96     }
97 
98     MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g11_X>::AddMediaObject(cmdBuffer, batchBuffer, params));
99 
100     MHW_MI_CHK_NULL(cmd);
101     cmd->DW4.XPosition = params->VfeScoreboard.Value[0];
102     cmd->DW4.YPosition = params->VfeScoreboard.Value[1];
103 
104     return MOS_STATUS_SUCCESS;
105 }
106 
AddPaletteLoadCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_PALETTE_PARAMS params)107 MOS_STATUS MhwRenderInterfaceG11::AddPaletteLoadCmd(
108     PMOS_COMMAND_BUFFER             cmdBuffer,
109     PMHW_PALETTE_PARAMS             params)
110 {
111     MHW_FUNCTION_ENTER;
112 
113     MHW_MI_CHK_NULL(m_osInterface);
114     MHW_MI_CHK_NULL(cmdBuffer);
115     MHW_MI_CHK_NULL(params);
116     MHW_MI_CHK_NULL(params->pPaletteData);
117 
118     if (params->iNumEntries <= 0)
119     {
120         MHW_ASSERTMESSAGE("Invalid number of palette entries.");
121         return MOS_STATUS_INVALID_PARAMETER;
122     }
123 
124     // Send Palettes in use
125     if (params->iPaletteID == 0)
126     {
127         mhw_render_g11_X::_3DSTATE_SAMPLER_PALETTE_LOAD0_CMD cmd;
128         // Set size of palette load command
129         cmd.DW0.DwordLength = params->iNumEntries - 1;
130         MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
131     }
132     else if (params->iPaletteID == 1)
133     {
134         mhw_render_g11_X::_3DSTATE_SAMPLER_PALETTE_LOAD1_CMD cmd;
135         // Set size of palette load command
136         cmd.DW0.DwordLength = params->iNumEntries - 1;
137         MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
138     }
139     else
140     {
141         MHW_ASSERTMESSAGE("Invalid palette ID specified: %d.", params->iPaletteID);
142         return MOS_STATUS_INVALID_PARAMETER;
143     }
144 
145     mhw_render_g11_X::PALETTE_ENTRY_CMD entry;
146     uint32_t cmdSize = entry.byteSize * params->iNumEntries;
147 
148     // Send palette load command followed by palette data
149     MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, params->pPaletteData, cmdSize));
150 
151     return MOS_STATUS_SUCCESS;
152 }
153 
EnableL3Caching(PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS cacheSettings)154 MOS_STATUS MhwRenderInterfaceG11::EnableL3Caching(
155     PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS    cacheSettings )
156 {
157     // L3 Caching enabled by default
158     m_l3CacheConfig.bL3CachingEnabled = true;
159     m_l3CacheConfig.dwL3CacheCntlReg_Register = m_l3CacheCntlRegisterOffset;
160     m_l3CacheConfig.dwL3CacheTcCntlReg_Register = m_l3CacheTcCntlRegisterOffset;
161 
162     if ( cacheSettings )
163     {
164         PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G11 cacheSettingsG11 = dynamic_cast< PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G11 >( cacheSettings );
165         if (cacheSettingsG11 == nullptr)
166         {
167             MHW_ASSERTMESSAGE("Gen11-Specific Params are needed.");
168             return MOS_STATUS_INVALID_PARAMETER;
169         }
170         m_l3CacheConfig.dwL3CacheCntlReg_Setting = cacheSettingsG11->dwCntlReg;
171         m_l3CacheConfig.dwL3CacheTcCntlReg_Setting = cacheSettingsG11->dwTcCntlReg;
172     }
173     else // Use the default setting if regkey is not set
174     {
175         m_l3CacheConfig.dwL3CacheCntlReg_Setting = m_l3CacheCntlRegisterValueDefault;
176         m_l3CacheConfig.dwL3CacheTcCntlReg_Setting = m_l3CacheTcCntlRegisterValueDefault;
177     }
178 
179     return MOS_STATUS_SUCCESS;
180 }
181 
SetL3Cache(PMOS_COMMAND_BUFFER cmdBuffer)182 MOS_STATUS MhwRenderInterfaceG11::SetL3Cache( PMOS_COMMAND_BUFFER cmdBuffer )
183 {
184     MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
185 
186     MHW_MI_CHK_NULL( cmdBuffer );
187 
188     if ( m_l3CacheConfig.bL3CachingEnabled )
189     {
190         MHW_MI_LOAD_REGISTER_IMM_PARAMS loadRegisterParams;
191 
192         if ( m_l3CacheConfig.dwL3CacheCntlReg_Setting != 0 )
193         {
194             MOS_ZeroMemory( &loadRegisterParams, sizeof( loadRegisterParams ) );
195             loadRegisterParams.dwRegister = m_l3CacheConfig.dwL3CacheCntlReg_Register;
196             loadRegisterParams.dwData = m_l3CacheConfig.dwL3CacheCntlReg_Setting;
197             MHW_MI_CHK_STATUS( m_miInterface->AddMiLoadRegisterImmCmd( cmdBuffer, &loadRegisterParams ) );
198         }
199 
200         if ( m_l3CacheConfig.dwL3CacheTcCntlReg_Setting != 0 )
201         {
202             MOS_ZeroMemory( &loadRegisterParams, sizeof( loadRegisterParams ) );
203             loadRegisterParams.dwRegister = m_l3CacheConfig.dwL3CacheTcCntlReg_Register;
204             loadRegisterParams.dwData = m_l3CacheConfig.dwL3CacheTcCntlReg_Setting;
205             MHW_MI_CHK_STATUS( m_miInterface->AddMiLoadRegisterImmCmd( cmdBuffer, &loadRegisterParams ) );
206         }
207     }
208 
209     return eStatus;
210 }
211 
AddGpgpuCsrBaseAddrCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMOS_RESOURCE csrResource)212 MOS_STATUS MhwRenderInterfaceG11::AddGpgpuCsrBaseAddrCmd(
213     PMOS_COMMAND_BUFFER             cmdBuffer,
214     PMOS_RESOURCE                   csrResource)
215 {
216     MHW_MI_CHK_NULL(m_osInterface);
217     MHW_MI_CHK_NULL(cmdBuffer);
218     MHW_MI_CHK_NULL(csrResource);
219 
220 #if (EMUL)
221     MHW_NORMALMESSAGE("GPGPU_CSR_BASE_ADDRESS not supported.");
222     return MOS_STATUS_SUCCESS;
223 #endif
224 
225     mhw_render_g11_X::STATE_CSR_BASE_ADDRESS_CMD cmd;
226     MHW_RESOURCE_PARAMS resourceParams;
227     MOS_ZeroMemory(&resourceParams, sizeof(resourceParams));
228     resourceParams.presResource = csrResource;
229     resourceParams.pdwCmd = (uint32_t *)cmd.DW1_2.Value;
230     resourceParams.dwLocationInCmd = 1;
231 
232     MHW_MI_CHK_STATUS(AddResourceToCmd(
233         m_osInterface,
234         cmdBuffer,
235         &resourceParams));
236 
237     MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
238 
239     return MOS_STATUS_SUCCESS;
240 }
241 
InitMmioRegisters()242 void MhwRenderInterfaceG11::InitMmioRegisters()
243 {
244     MHW_MI_MMIOREGISTERS *mmioRegisters = &m_mmioRegisters;
245     mmioRegisters->generalPurposeRegister0LoOffset  = CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G11;
246     mmioRegisters->generalPurposeRegister0HiOffset  = CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G11;
247     mmioRegisters->generalPurposeRegister4LoOffset  = CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G11;
248     mmioRegisters->generalPurposeRegister4HiOffset  = CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G11;
249     mmioRegisters->generalPurposeRegister11LoOffset = CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G11;
250     mmioRegisters->generalPurposeRegister11HiOffset = CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G11;
251     mmioRegisters->generalPurposeRegister12LoOffset = CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G11;
252     mmioRegisters->generalPurposeRegister12HiOffset = CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G11;
253 }
254