1 /* 2 * Copyright (c) 2015-2018, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mmio_g11.h 24 //! \brief Define the MMIO registers access of Gen11 25 //! \details 26 //! 27 28 29 #ifndef __MHW_MMIO_G11_H__ 30 #define __MHW_MMIO_G11_H__ 31 32 33 // CS register offsets 34 #define CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G11 0x2600 35 #define CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G11 0x2604 36 #define CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G11 0x2620 37 #define CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G11 0x2624 38 #define CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G11 0x2658 39 #define CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G11 0x265C 40 #define CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G11 0x2660 41 #define CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G11 0x2664 42 43 // Vebox register offsets 44 // Used in Commen MI 45 #define GP_REGISTER0_LO_OFFSET_G11 0x1C8600 46 #define GP_REGISTER0_HI_OFFSET_G11 0x1C8604 47 #define GP_REGISTER4_LO_OFFSET_G11 0x1C8620 48 #define GP_REGISTER4_HI_OFFSET_G11 0x1C8624 49 #define GP_REGISTER11_LO_OFFSET_G11 0x1C8658 50 #define GP_REGISTER11_HI_OFFSET_G11 0x1C865C 51 #define GP_REGISTER12_LO_OFFSET_G11 0x1C8660 52 #define GP_REGISTER12_HI_OFFSET_G11 0x1C8664 53 54 //VEBOX 55 #define WATCHDOG_COUNT_CTRL_OFFSET_RCS_G11 0x2178 56 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_RCS_G11 0x217C 57 58 #define WATCHDOG_COUNT_CTRL_OFFSET_VCS0_G11 0x1C0178 59 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_VCS0_G11 0x1C017C 60 61 #define WATCHDOG_COUNT_CTRL_OFFSET_VCS1_G11 0x1C4178 62 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_VCS1_G11 0x1C417C 63 64 #define WATCHDOG_COUNT_CTRL_OFFSET_VECS_G11 0x1C8178 65 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_VECS_G11 0x1C817C 66 67 //VDBOX HCP 68 #define WATCHDOG_COUNT_CTRL_OFFSET_INIT_G11 0x1C0178 69 #define WATCHDOG_COUNT_THRESTHOLD_OFFSET_INIT_G11 0x1C017C 70 #define HCP_DEBUG_FE_STREAM_OUT_SIZE_REG_OFFSET_INIT_G11 0x1C2828 71 #define HCP_ENC_IMAGE_STATUS_MASK_REG_OFFSET_INIT_G11 0x1C28B8 72 #define HCP_ENC_IMAGE_STATUS_CTRL_REG_OFFSET_INIT_G11 0x1C28BC 73 #define HCP_ENC_BIT_STREAM_BYTE_COUNT_FRAME_REG_OFFSET_INIT_G11 0x1C28A0 74 #define HCP_ENC_BIT_STREAM_SE_BIT_COUNT_FRAME_REG_OFFSET_INIT_G11 0x1C28A8 75 #define HCP_ENC_BIT_STREAM_BYTE_COUNT_FRAME_NO_HEADER_REG_OFFSET_INIT_G11 0x1C28A4 76 #define HCP_ENC_QP_STATUS_COUNT_REG_OFFSET_INIT_G11 0x1C28C0 77 #define HCP_ENC_SLICE_COUNT_REG_OFFSET_INIT_G11 0x1C28C8 78 #define HCP_ENC_VDENC_MODE_TIMER_REG_OFFSET_INIT_G11 0x1C28DC 79 #define HCP_VP9_ENC_BITSTREAM_BYTE_COUNT_FRAME_REG_OFFSET_INIT_G11 0x1C28E0 80 #define HCP_VP9_ENC_BITSTREAM_BYTE_COUNT_FRAME_NO_HEADER_REG_OFFSET_INIT_G11 0x1C28E4 81 #define HCP_VP9_ENC_IMAGE_STATUS_MASK_REG_OFFSET_INIT_G11 0x1C28F0 82 #define HCP_VP9_ENC_IMAGE_STATUS_CTRL_REG_OFFSET_INIT_G11 0x1C28F4 83 #define CS_ENGINE_ID_OFFSET_INIT_G11 0x1C008C 84 #define HCP_DEC_STATUS_REG_OFFSET_INIT_G11 0x1C2800 85 #define HCP_CABAC_STATUS_REG_OFFSET_INIT_G11 0x1C2804 86 87 //VDBOX HUC 88 #define HUC_UKERNEL_HDR_INFO_REG_OFFSET_NODE_1_INIT_G11 0x1C2014 89 #define HUC_STATUS_REG_OFFSET_NODE_1_INIT_G11 0x1C2000 90 #define HUC_STATUS2_REG_OFFSET_NODE_1_INIT_G11 0x1C23B0 91 92 //VDBOX MFX register offsets 93 #define GENERAL_PURPOSE_REGISTER0_LO_OFFSET_NODE_1_INIT_G11 0x1C0600 94 #define GENERAL_PURPOSE_REGISTER0_HI_OFFSET_NODE_1_INIT_G11 0x1C0604 95 #define GENERAL_PURPOSE_REGISTER4_LO_OFFSET_NODE_1_INIT_G11 0x1C0620 96 #define GENERAL_PURPOSE_REGISTER4_HI_OFFSET_NODE_1_INIT_G11 0x1C0624 97 #define GENERAL_PURPOSE_REGISTER11_LO_OFFSET_NODE_1_INIT_G11 0x1C0658 98 #define GENERAL_PURPOSE_REGISTER11_HI_OFFSET_NODE_1_INIT_G11 0x1C065C 99 #define GENERAL_PURPOSE_REGISTER12_LO_OFFSET_NODE_1_INIT_G11 0x1C0660 100 #define GENERAL_PURPOSE_REGISTER12_HI_OFFSET_NODE_1_INIT_G11 0x1C0664 101 #define MFC_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G11 0x1C08B4 102 #define MFC_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G11 0x1C08B8 103 #define MFC_AVC_NUM_SLICES_REG_OFFSET_NODE_1_INIT_G11 0x1C0954 104 #define MFC_QP_STATUS_COUNT_OFFSET_NODE_1_INIT_G11 0x1C08BC 105 #define MFX_ERROR_FLAG_REG_OFFSET_NODE_1_INIT_G11 0x1C0800 106 #define MFX_FRAME_CRC_REG_OFFSET_NODE_1_INIT_G11 0x1C0850 107 #define MFX_MB_COUNT_REG_OFFSET_NODE_1_INIT_G11 0x1C0868 108 #define MFC_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_1_INIT_G11 0x1C08A0 109 #define MFC_BITSTREAM_SE_BITCOUNT_FRAME_REG_OFFSET_NODE_1_INIT_G11 0x1C08A4 110 #define MFC_BITSTREAM_BYTECOUNT_SLICE_REG_OFFSET_NODE_1_INIT_G11 0x1C08D0 111 #define MFC_VP8_BITSTREAM_BYTECOUNT_FRAME_REG_OFFSET_NODE_1_INIT_G11 0x1C0908 112 #define MFC_VP8_IMAGE_STATUS_MASK_REG_OFFSET_NODE_1_INIT_G11 0x1C0900 113 #define MFC_VP8_IMAGE_STATUS_CTRL_REG_OFFSET_NODE_1_INIT_G11 0x1C0904 114 #define MFX_VP8_BRC_DQ_INDEX_REG_OFFSET_NODE_1_INIT_G11 0x1C0910 115 #define MFX_VP8_BRC_LOOP_FILTER_REG_OFFSET_NODE_1_INIT_G11 0x1C0914 116 #define MFX_VP8_BRC_CUMULATIVE_DQ_INDEX01_REG_OFFSET_NODE_1_INIT_G11 0x1C0918 117 #define MFX_VP8_BRC_CUMULATIVE_DQ_INDEX23_REG_OFFSET_NODE_1_INIT_G11 0x1C091C 118 #define MFX_VP8_BRC_CUMULATIVE_LOOP_FILTER01_REG_OFFSET_NODE_1_INIT_G11 0x1C0920 119 #define MFX_VP8_BRC_CUMULATIVE_LOOP_FILTER23_REG_OFFSET_NODE_1_INIT_G11 0x1C0924 120 #define MFX_VP8_BRC_CONVERGENCE_STATUS_REG_OFFSET_NODE_1_INIT_G11 0x1C0928 121 122 //VDBOX MFX register initial values 123 #define MFX_LRA0_REG_OFFSET_NODE_1_INIT_G11 0 124 #define MFX_LRA1_REG_OFFSET_NODE_1_INIT_G11 0 125 #define MFX_LRA2_REG_OFFSET_NODE_1_INIT_G11 0 126 127 // CM HAL 128 #define REG_GPR_BASE_G11 CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G11 129 #define REG_TIMESTAMP_BASE_G11 0x2358 130 131 #endif //__MHW_MMIO_G11_H__ 132