1 /* 2 * Copyright (c) 2020-2022, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi_itf.h 24 //! \brief MHW MI interface common base 25 //! \details 26 //! 27 28 #ifndef __MHW_MI_ITF_H__ 29 #define __MHW_MI_ITF_H__ 30 31 #include "mhw_itf.h" 32 #include "mhw_mi_cmdpar.h" 33 #include "mhw_cp_interface.h" 34 #include "media_defs.h" 35 36 #define _MI_CMD_DEF(DEF) \ 37 DEF(MI_SEMAPHORE_WAIT); \ 38 DEF(MI_CONDITIONAL_BATCH_BUFFER_END); \ 39 DEF(PIPE_CONTROL); \ 40 DEF(MI_BATCH_BUFFER_START); \ 41 DEF(MI_SET_PREDICATE); \ 42 DEF(MI_STORE_REGISTER_MEM); \ 43 DEF(MI_LOAD_REGISTER_MEM); \ 44 DEF(MI_LOAD_REGISTER_IMM); \ 45 DEF(MI_LOAD_REGISTER_REG); \ 46 DEF(MI_FORCE_WAKEUP); \ 47 DEF(VD_CONTROL_STATE); \ 48 DEF(MEDIA_STATE_FLUSH); \ 49 DEF(MI_BATCH_BUFFER_END); \ 50 DEF(MI_FLUSH_DW); \ 51 DEF(MI_NOOP); \ 52 DEF(MI_ATOMIC); \ 53 DEF(MI_STORE_DATA_IMM); \ 54 DEF(MI_MATH); \ 55 DEF(MI_COPY_MEM_MEM); \ 56 DEF(MFX_WAIT) 57 namespace mhw 58 { 59 namespace mi 60 { 61 class Itf 62 { 63 public: 64 65 enum CommandsNumberOfAddresses 66 { 67 MFX_WAIT_CMD_NUMBER_OF_ADDRESSES = 0, 68 MI_BATCH_BUFFER_START_CMD_NUMBER_OF_ADDRESSES = 1, 69 MI_STORE_DATA_IMM_CMD_NUMBER_OF_ADDRESSES = 1, 70 MI_FLUSH_DW_CMD_NUMBER_OF_ADDRESSES = 1, 71 MI_CONDITIONAL_BATCH_BUFFER_END_CMD_NUMBER_OF_ADDRESSES = 1, 72 MI_STORE_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, 73 MI_LOAD_REGISTER_MEM_CMD_NUMBER_OF_ADDRESSES = 1, 74 MI_COPY_MEM_MEM_CMD_NUMBER_OF_ADDRESSES = 4, 75 MI_SEMAPHORE_WAIT_CMD_NUMBER_OF_ADDRESSES = 1, 76 MI_ATOMIC_CMD_NUMBER_OF_ADDRESSES = 1 77 }; 78 79 class ParSetting 80 { 81 public: 82 virtual ~ParSetting() = default; 83 84 _MI_CMD_DEF(_MHW_SETPAR_DEF); 85 }; 86 87 virtual ~Itf() = default; 88 89 virtual MOS_STATUS SetWatchdogTimerThreshold(uint32_t frameWidth, uint32_t frameHeight, bool isEncoder, uint32_t codecMode = CODECHAL_STANDARD_MAX) = 0; 90 91 virtual MOS_STATUS SetWatchdogTimerRegisterOffset(MOS_GPU_CONTEXT gpuContext) = 0; 92 93 virtual MOS_STATUS AddWatchdogTimerStartCmd(PMOS_COMMAND_BUFFER cmdBuffer) = 0; 94 95 virtual MOS_STATUS AddWatchdogTimerStopCmd(PMOS_COMMAND_BUFFER cmdBuffer) = 0; 96 97 virtual MOS_STATUS AddMiBatchBufferEnd(PMOS_COMMAND_BUFFER cmdBuffer, PMHW_BATCH_BUFFER batchBuffer) = 0; 98 99 virtual MOS_STATUS AddMiBatchBufferEndOnly(PMOS_COMMAND_BUFFER cmdBuffer, PMHW_BATCH_BUFFER batchBuffer) = 0; 100 101 virtual MOS_STATUS AddBatchBufferEndInsertionFlag(MOS_COMMAND_BUFFER &constructedCmdBuf) = 0; 102 103 virtual MHW_MI_MMIOREGISTERS* GetMmioRegisters() = 0; 104 105 virtual MOS_STATUS SetCpInterface(MhwCpInterface *cpInterface, std::shared_ptr<mhw::mi::Itf> m_miItf) = 0; 106 107 virtual uint32_t GetMmioInterfaces(MHW_MMIO_REGISTER_OPCODE opCode) = 0; 108 109 virtual MOS_STATUS AddProtectedProlog(MOS_COMMAND_BUFFER *cmdBuffer) = 0; 110 111 virtual MOS_STATUS AddVeboxMMIOPrologCmd(PMOS_COMMAND_BUFFER CmdBuffer) = 0; 112 113 virtual MOS_STATUS AddBLTMMIOPrologCmd(PMOS_COMMAND_BUFFER cmdBuffer) = 0; 114 115 _MI_CMD_DEF(_MHW_CMD_ALL_DEF_FOR_ITF); 116 MEDIA_CLASS_DEFINE_END(mhw__mi__Itf) 117 }; 118 } // namespace mi 119 } // namespace mhw 120 121 #endif // __MHW_MI_ITF_H__ 122