1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi_hwcmd_g9_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g9_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_MI_HWCMD_G9_X_H__ 29 #define __MHW_MI_HWCMD_G9_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_mi_g9_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MI_BATCH_BUFFER_END 50 //! \details 51 //! The MI_BATCH_BUFFER_END command is used to terminate the execution of 52 //! commands stored in a batch buffer initiated using a 53 //! MI_BATCH_BUFFER_START command. 54 //! 55 struct MI_BATCH_BUFFER_END_CMD 56 { 57 union 58 { 59 //!< DWORD 0 60 struct 61 { 62 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 22) ; //!< Reserved 63 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 64 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 65 }; 66 uint32_t Value; 67 } DW0; 68 69 //! \name Local enumerations 70 71 enum MI_COMMAND_OPCODE 72 { 73 MI_COMMAND_OPCODE_MIBATCHBUFFEREND = 10, //!< No additional details 74 }; 75 76 enum COMMAND_TYPE 77 { 78 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 79 }; 80 81 //! \name Initializations 82 83 //! \brief Explicit member initialization function 84 MI_BATCH_BUFFER_END_CMD(); 85 86 static const size_t dwSize = 1; 87 static const size_t byteSize = 4; 88 }; 89 90 //! 91 //! \brief MI_NOOP 92 //! \details 93 //! The MI_NOOP command basically performs a "no operation" in the command 94 //! stream and is typically used to pad the command stream (e.g., in order 95 //! to pad out a batch buffer to a QWord boundary). However, there is one 96 //! minor (optional) function this command can perform - a 22-bit value can 97 //! be loaded into the MI NOPID register. This provides a general-purpose 98 //! command stream tagging ("breadcrumb") mechanism (e.g., to provide 99 //! sequencing information for a subsequent breakpoint interrupt). 100 //! 101 struct MI_NOOP_CMD 102 { 103 union 104 { 105 //!< DWORD 0 106 struct 107 { 108 uint32_t IdentificationNumber : __CODEGEN_BITFIELD( 0, 21) ; //!< Identification Number 109 uint32_t IdentificationNumberRegisterWriteEnable : __CODEGEN_BITFIELD(22, 22) ; //!< IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE 110 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 111 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 112 }; 113 uint32_t Value; 114 } DW0; 115 116 //! \name Local enumerations 117 118 //! \brief IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE 119 //! \details 120 //! This field enables the value in the Identification Number field to be 121 //! written into the MI NOPID register. If disabled, that register is 122 //! unmodified - making this command an effective "no operation" function. 123 enum IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE 124 { 125 IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE_WRITETHENOPIDREGISTER = 1, //!< No additional details 126 }; 127 128 enum MI_COMMAND_OPCODE 129 { 130 MI_COMMAND_OPCODE_MINOOP = 0, //!< No additional details 131 }; 132 133 enum COMMAND_TYPE 134 { 135 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 136 }; 137 138 //! \name Initializations 139 140 //! \brief Explicit member initialization function 141 MI_NOOP_CMD(); 142 143 static const size_t dwSize = 1; 144 static const size_t byteSize = 4; 145 }; 146 147 //! 148 //! \brief MI_ARB_CHECK 149 //! \details 150 //! The MI_ARB_CHECK is used to check for a change in arbitration. If 151 //! executed as part of a Ring Buffer the command checks the UHPTR valid bit 152 //! and if set the head of the ring will jump to the value of the head 153 //! pointer programmed in the UHPTR. 154 //! 155 //! This instruction cannot be placed in a batch buffer. 156 //! 157 //! If execlist is enabled, there is a pending execution list and this 158 //! command is parsed, then the command streamer will preempt the current 159 //! context and start executing the new execution list. 160 //! 161 struct MI_ARB_CHECK_CMD 162 { 163 union 164 { 165 //!< DWORD 0 166 struct 167 { 168 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 22) ; //!< Reserved 169 uint32_t MiInstructionOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_INSTRUCTION_OPCODE 170 uint32_t MiInstructionType : __CODEGEN_BITFIELD(29, 31) ; //!< MI_INSTRUCTION_TYPE 171 }; 172 uint32_t Value; 173 } DW0; 174 175 //! \name Local enumerations 176 177 enum MI_INSTRUCTION_OPCODE 178 { 179 MI_INSTRUCTION_OPCODE_MIARBCHECK = 5, //!< No additional details 180 }; 181 182 enum MI_INSTRUCTION_TYPE 183 { 184 MI_INSTRUCTION_TYPE_MIINSTRUCTION = 0, //!< No additional details 185 }; 186 187 //! \name Initializations 188 189 //! \brief Explicit member initialization function 190 MI_ARB_CHECK_CMD(); 191 192 static const size_t dwSize = 1; 193 static const size_t byteSize = 4; 194 }; 195 196 //! 197 //! \brief MI_LOAD_REGISTER_IMM 198 //! \details 199 //! The MI_LOAD_REGISTER_IMM command requests a write of up to a DWord 200 //! constant supplied in the command to the specified Register Offset (i.e., 201 //! offset into Memory-Mapped Register Range). 202 //! Any offset that is to a destination outside of the GT core will allow 203 //! the parser to continue once the cycle is at the GT boundry and not 204 //! destination. Any other address will ensure the destination is updated 205 //! prior to parsing the next command 206 //! 207 //! When executed from a non-privileged batch buffer, MMIO writes are only 208 //! allowed to the registers listed in User Mode Non-Privileged Registers 209 //! for the corresponding engine, any writes targeting the register not 210 //! listed in the User Mode Non-Privileged Register will convert this 211 //! command to a NOOP. 212 //! 213 //! The following addresses should NOT be used for LRIs: 214 //! 215 //! 0x8800 - 0x88FF 216 //! 217 //! >= 0xC0000 218 //! 219 //! 220 //! 221 //! Limited LRI cycles to the Display Engine (0x40000-0xBFFFF) are allowed, 222 //! but must be spaced to allow only one pending at a time. This can be done 223 //! by issuing an SRM to the same address immediately after each LRI. 224 //! 225 struct MI_LOAD_REGISTER_IMM_CMD 226 { 227 union 228 { 229 //!< DWORD 0 230 struct 231 { 232 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 233 uint32_t ByteWriteDisables : __CODEGEN_BITFIELD( 8, 11) ; //!< Byte Write Disables 234 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 22) ; //!< Reserved 235 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 236 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 237 }; 238 uint32_t Value; 239 } DW0; 240 union 241 { 242 //!< DWORD 1 243 struct 244 { 245 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 246 uint32_t RegisterOffset : __CODEGEN_BITFIELD( 2, 22) ; //!< Register Offset 247 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 248 }; 249 uint32_t Value; 250 } DW1; 251 union 252 { 253 //!< DWORD 2 254 struct 255 { 256 uint32_t DataDword ; //!< Data DWord 257 }; 258 uint32_t Value; 259 } DW2; 260 261 //! \name Local enumerations 262 263 enum MI_COMMAND_OPCODE 264 { 265 MI_COMMAND_OPCODE_MILOADREGISTERIMM = 34, //!< No additional details 266 }; 267 268 enum COMMAND_TYPE 269 { 270 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 271 }; 272 273 //! \name Initializations 274 275 //! \brief Explicit member initialization function 276 MI_LOAD_REGISTER_IMM_CMD(); 277 278 static const size_t dwSize = 3; 279 static const size_t byteSize = 12; 280 }; 281 282 //! 283 //! \brief MI_LOAD_REGISTER_MEM 284 //! \details 285 //! The MI_LOAD_REGISTER_MEM command requests from a memory location and 286 //! stores that DWord to a register. 287 //! 288 //! The command temporarily halts commands that will cause cycles down the 289 //! 3D pipeline. 290 //! 291 //! The following addresses should NOT be used for MMIO writes: 292 //! 293 //! 0x8800 - 0x88FF 294 //! 295 //! >= 0xC0000 296 //! 297 //! 298 //! 299 //! Limited MMIO writes cycles to the Display Engine 0x40000-0xBFFFF) are 300 //! allowed, but must be spaced to allow only one pending at a time. This 301 //! can be done by issuing an SRM to the same address immediately after each 302 //! MMIO write. 303 //! 304 //! This command should not be used within a non-privilege batch buffer to 305 //! access global virtual space, doing so will be treated as privilege 306 //! access violation. Refer "User Mode Privilege Command" in 307 //! MI_BATCH_BUFFER_START command section to know HW behavior on 308 //! encountering privilege access violation. 309 //! 310 //! This command is not allowed to update the privilege register range when 311 //! executed from a non-privilege batch buffer. 312 //! 313 struct MI_LOAD_REGISTER_MEM_CMD 314 { 315 union 316 { 317 //!< DWORD 0 318 struct 319 { 320 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 321 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 20) ; //!< Reserved 322 uint32_t AsyncModeEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Async Mode Enable 323 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< Use Global GTT 324 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 325 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 326 }; 327 uint32_t Value; 328 } DW0; 329 union 330 { 331 //!< DWORD 1 332 struct 333 { 334 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 335 uint32_t RegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Register Address 336 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 337 }; 338 uint32_t Value; 339 } DW1; 340 union 341 { 342 //!< DWORD 2..3 343 struct 344 { 345 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 346 uint64_t MemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Memory Address 347 }; 348 uint32_t Value[2]; 349 } DW2_3; 350 351 //! \name Local enumerations 352 353 enum MI_COMMAND_OPCODE 354 { 355 MI_COMMAND_OPCODE_MILOADREGISTERMEM = 41, //!< No additional details 356 }; 357 358 enum COMMAND_TYPE 359 { 360 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 361 }; 362 363 //! \name Initializations 364 365 //! \brief Explicit member initialization function 366 MI_LOAD_REGISTER_MEM_CMD(); 367 368 static const size_t dwSize = 4; 369 static const size_t byteSize = 16; 370 }; 371 372 //! 373 //! \brief MI_LOAD_REGISTER_REG 374 //! \details 375 //! The MI_LOAD_REGISTER_REG command reads from a source register location 376 //! and writes that value to a destination register location. 377 //! Any offset that is to a destination outside of the GT core will allow 378 //! the parser to continue once the cycle is at the GT boundry and not 379 //! destination. Any other address will ensure the destination is updated 380 //! prior to parsing the next command 381 //! 382 //! The command temporarily halts commands that will cause cycles down the 383 //! 3D pipeline. 384 //! 385 //! Destination register with mask implemented (Ex: some 386 //! registers have bits [31:16] as mask bits and bits[15:0] as data) will 387 //! not get updated unless the value read from source register has the bits 388 //! corresponding to the mask bits set. Note that any mask implemented 389 //! register when read returns "0" for the bits corresponding to mask 390 //! location. When the source and destination are mask implemented 391 //! registers, destination register will not get updated with the source 392 //! register contents. 393 //! 394 //! This command is not allowed to update the privilege register range when 395 //! executed from a non-privilege batch buffer. 396 //! 397 struct MI_LOAD_REGISTER_REG_CMD 398 { 399 union 400 { 401 //!< DWORD 0 402 struct 403 { 404 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 405 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 22) ; //!< Reserved 406 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 407 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 408 }; 409 uint32_t Value; 410 } DW0; 411 union 412 { 413 //!< DWORD 1 414 struct 415 { 416 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 417 uint32_t SourceRegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Source Register Address 418 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 419 }; 420 uint32_t Value; 421 } DW1; 422 union 423 { 424 //!< DWORD 2 425 struct 426 { 427 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 428 uint32_t DestinationRegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Destination Register Address 429 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 430 }; 431 uint32_t Value; 432 } DW2; 433 434 //! \name Local enumerations 435 436 enum MI_COMMAND_OPCODE 437 { 438 MI_COMMAND_OPCODE_MILOADREGISTERREG = 42, //!< No additional details 439 }; 440 441 enum COMMAND_TYPE 442 { 443 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 444 }; 445 446 //! \name Initializations 447 448 //! \brief Explicit member initialization function 449 MI_LOAD_REGISTER_REG_CMD(); 450 451 static const size_t dwSize = 3; 452 static const size_t byteSize = 12; 453 }; 454 455 //! 456 //! \brief MI_STORE_REGISTER_MEM 457 //! \details 458 //! The MI_STORE_REGISTER_MEM command requests a register read from a 459 //! specified memory mapped register location in the device and store of 460 //! that DWord to memory. The register address is specified along with the 461 //! command to perform the read. 462 //! 463 //! 464 //! The command temporarily halts command execution. 465 //! 466 //! The memory address for the write is snooped on the host bus. 467 //! 468 //! This command should not be used from within a "non-privilege" batch 469 //! buffer to access global virtual space. doing so will be treated as 470 //! privilege access violation. Refer "User Mode Privilege Command" in 471 //! MI_BATCH_BUFFER_START command section to know HW behavior on 472 //! encountering privilege access violation. This command can be used within 473 //! ring buffers and/or "privilege" batch buffers to access global virtual 474 //! space. 475 //! 476 //! This command will cause undefined data to be written to memory if given 477 //! register addresses for the PGTBL_CTL_0 or FENCE registers. 478 //! 479 struct MI_STORE_REGISTER_MEM_CMD 480 { 481 union 482 { 483 //!< DWORD 0 484 struct 485 { 486 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 487 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 21) ; //!< Reserved 488 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< Use Global GTT 489 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 490 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 491 }; 492 uint32_t Value; 493 } DW0; 494 union 495 { 496 //!< DWORD 1 497 struct 498 { 499 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 500 uint32_t RegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Register Address 501 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 502 }; 503 uint32_t Value; 504 } DW1; 505 union 506 { 507 //!< DWORD 2..3 508 struct 509 { 510 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 511 uint64_t MemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Memory Address 512 }; 513 uint32_t Value[2]; 514 } DW2_3; 515 516 //! \name Local enumerations 517 518 enum MI_COMMAND_OPCODE 519 { 520 MI_COMMAND_OPCODE_MISTOREREGISTERMEM = 36, //!< No additional details 521 }; 522 523 enum COMMAND_TYPE 524 { 525 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 526 }; 527 528 //! \name Initializations 529 530 //! \brief Explicit member initialization function 531 MI_STORE_REGISTER_MEM_CMD(); 532 533 static const size_t dwSize = 4; 534 static const size_t byteSize = 16; 535 }; 536 537 //! 538 //! \brief MI_BATCH_BUFFER_START 539 //! \details 540 //! The MI_BATCH_BUFFER_START command is used to initiate the execution of 541 //! commands stored in a batch buffer. For restrictions on the location of 542 //! batch buffers, see Batch Buffers in the Device Programming Interface 543 //! chapter of MI Functions. The batch buffer can be specified as privileged 544 //! or non-privileged, determining the operations considered valid when 545 //! initiated from within the buffer and any attached (chained) batch 546 //! buffers. See Batch Buffer Protection in the Device Programming Interface 547 //! chapter of MI Functions. 548 //! 549 //! A batch buffer initiated with this command must end either with a 550 //! MI_BATCH_BUFFER_END command or by chaining to another batch buffer with 551 //! an MI_BATCH_BUFFER_START command. 552 //! It is essential that the address location beyond the current page be 553 //! populated inside the GTT. HW performs over-fetch of the command 554 //! addresses and any over-fetch requires a valid TLB entry. A single extra 555 //! page beyond the batch buffer is sufficient. 556 //! 557 //! 558 //! 559 //! SW must ensure to reset the state of the second level batch buffer prior 560 //! to programming second level batch buffer. This must be done by 561 //! programming MI_LOAD_REGISTER_IMM command to program SBB_STATE register 562 //! with 0x0 value prior to programming MI_BATCH_BUFFER_START command for 563 //! the second level batch buffer. SBB_STATE register seleected must be the 564 //! offset belonging to the command streamer on which the second level batch 565 //! buffer will be executed. OR 566 //! 567 //! Above programming is not required if second level batch buffer 568 //! programmed in a given batch buffer chain is always non-privileged OR 569 //! 570 //! Above programming is not required if the second level batch buffer is 571 //! being called from a non-privileged batch buffer. 572 //! 573 //! A batch buffer is treated as non-privileged if the Address Space 574 //! Indicator is set to PPGTT. 575 //! 576 struct MI_BATCH_BUFFER_START_CMD 577 { 578 union 579 { 580 //!< DWORD 0 581 struct 582 { 583 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 584 uint32_t AddressSpaceIndicator : __CODEGEN_BITFIELD( 8, 8) ; //!< ADDRESS_SPACE_INDICATOR 585 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 21) ; //!< Reserved 586 uint32_t SecondLevelBatchBuffer : __CODEGEN_BITFIELD(22, 22) ; //!< SECOND_LEVEL_BATCH_BUFFER 587 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 588 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 589 }; 590 uint32_t Value; 591 } DW0; 592 union 593 { 594 //!< DWORD 1..2 595 struct 596 { 597 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 598 uint64_t BatchBufferStartAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Batch Buffer Start Address 599 }; 600 uint32_t Value[2]; 601 } DW1_2; 602 603 //! \name Local enumerations 604 605 //! \brief ADDRESS_SPACE_INDICATOR 606 //! \details 607 //! <p>Batch buffers accessed via PPGTT are considered as non-privileged. 608 //! Certain operations (e.g., MI_STORE_DATA_IMM commands to GGTT memory) are 609 //! prohibited within non-privileged buffers. More details mentioned in User 610 //! Mode Privileged command section. When MI_BATCH_BUFFER_START command is 611 //! executed from within a batch buffer (i.e., is a "chained" or "second 612 //! level" batch buffer command), the current active batch buffer's "Address 613 //! Space Indicator" and this field determine the "Address Space Indicator" 614 //! of the next buffer in the chain.</p> 615 //! <ul> 616 //! <li>Chained or Second level batch buffer can be in GGTT or PPGTT if the 617 //! parent batch buffer is in GGTT.</li> 618 //! <li>Chained or Second level batch buffer can only be in PPGTT if the 619 //! parent batch buffer is in PPGTT. This is enforced by Hardware.</li> 620 //! </ul> 621 enum ADDRESS_SPACE_INDICATOR 622 { 623 ADDRESS_SPACE_INDICATOR_GGTT = 0, //!< This batch buffer is located in GGTT memory and is privileged. 624 ADDRESS_SPACE_INDICATOR_PPGTT = 1, //!< This batch buffer is located in PPGTT memory and is Non-Privileged. 625 }; 626 627 //! \brief SECOND_LEVEL_BATCH_BUFFER 628 //! \details 629 //! <p>The command streamer contains three storage elements; one for the 630 //! ring head address, one for the batch head address, and one for the 631 //! second level batch head address. When performing batch buffer chaining, 632 //! hardware simply updates the head pointer of the first level batch 633 //! address storage. There is no stack in hardware. When this bit is set, 634 //! hardware uses the 2nd level batch head address storage element. Upon 635 //! MI_BATCH_BUFFER_END, it will automatically return to the first level 636 //! batch buffer address. This allows hardware to mimic a simple 3-level 637 //! stack.</p> 638 enum SECOND_LEVEL_BATCH_BUFFER 639 { 640 SECOND_LEVEL_BATCH_BUFFER_FIRSTLEVELBATCH = 0, //!< Place the batch buffer address in the 1st (traditional) level batch address storage element. 641 SECOND_LEVEL_BATCH_BUFFER_SECONDLEVELBATCH = 1, //!< Place the batch buffer address in the second-level batch address storage element. 642 }; 643 644 enum MI_COMMAND_OPCODE 645 { 646 MI_COMMAND_OPCODE_MIBATCHBUFFERSTART = 49, //!< No additional details 647 }; 648 649 enum COMMAND_TYPE 650 { 651 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 652 }; 653 654 //! \name Initializations 655 656 //! \brief Explicit member initialization function 657 MI_BATCH_BUFFER_START_CMD(); 658 659 static const size_t dwSize = 3; 660 static const size_t byteSize = 12; 661 }; 662 663 //! 664 //! \brief MI_SET_PREDICATE 665 //! \details 666 //! This command sets the Predication Check for the subsequent commands in 667 //! the command buffer except for MI_SET_PREDICATE itself. Render Command 668 //! Streamer NOOPs the following commands based on the PREDICATE_ENABLE from 669 //! MI_SET_PREDICATE, MI_SET_PREDICATE_RESULT and MI_SET_PREDICATE_RESULT_2 670 //! status. Resource Streamer doesn't take any action of parsing 671 //! MI_SET_PREDICATE, this command is similar to any other command which is 672 //! not meant for resource streamer. 673 //! 674 //! Executing MI_SET_PREDICATE command sets PREDICATE_ENABLE bits in MI_MODE 675 //! register, MI_MODE register gets render context save restored. 676 //! 677 //! MI_SET_PREDICATE predication scope must be confined within a Batch 678 //! Buffer to set of commands. 679 //! MI_SET_PREDICATE with Predicate Enable Must always have a 680 //! corresponding MI_SET_PREDICATE with Predicate Disable within the same 681 //! Batch Buffer. 682 //! MI_ARB_CHK command must be programmed outside the Predication Scope of 683 //! MI_SET_PREDICATE. 684 //! MI_SET_PREDICATE Predication Scope must not involve any RC6 triggering 685 //! events. 686 //! 687 //! 688 //! Only the following command(s) can be programmed between the 689 //! MI_SET_PREDICATE command enabled for predication: 3DSTATE_URB_VS 690 //! 3DSTATE_URB_HS 3DSTATE_URB_DS 3DSTATE_URB_GS 691 //! 3DSTATE_PUSH_CONSTANT_ALLOC_VS 3DSTATE_PUSH_CONSTANT_ALLOC_HS 692 //! 3DSTATE_PUSH_CONSTANT_ALLOC_DS 3DSTATE_PUSH_CONSTANT_ALLOC_GS 693 //! 3DSTATE_PUSH_CONSTANT_ALLOC_PS MI_LOAD_REGISTER_IMM MEDIA_VFE_STATE 694 //! MEDIA_OBJECT MEDIA_OBJJECT_WALKER MEDIA_INTERFACE_DESCRIPTOR_LOAD 695 //! 3DSTATE_WM_HZ_OP 696 //! 697 struct MI_SET_PREDICATE_CMD 698 { 699 union 700 { 701 //!< DWORD 0 702 struct 703 { 704 uint32_t PredicateEnable : __CODEGEN_BITFIELD( 0, 3) ; //!< PREDICATE_ENABLE 705 uint32_t Reserved4 : __CODEGEN_BITFIELD( 4, 22) ; //!< Reserved 706 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 707 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 708 }; 709 uint32_t Value; 710 } DW0; 711 712 //! \name Local enumerations 713 714 //! \brief PREDICATE_ENABLE 715 //! \details 716 //! This field sets the predication logic in render command streamer when 717 //! parsed. Predicate Disable is the default mode of operation. 718 enum PREDICATE_ENABLE 719 { 720 PREDICATE_ENABLE_NOOPNEVER = 0, //!< Predication is Disabled and RCS will process commands as usual. 721 PREDICATE_ENABLE_NOOPONRESULT2CLEAR = 1, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT_2 is clear. 722 PREDICATE_ENABLE_NOOPONRESULT2SET = 2, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT_2 is set. 723 PREDICATE_ENABLE_NOOPONRESULTCLEAR = 3, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT is clear. 724 PREDICATE_ENABLE_NOOPONRESULTSET = 4, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT is set. 725 PREDICATE_ENABLE_EXECUTEWHENONESLICEENABLED = 5, //!< Following Commands will be Executed by RCS only when one slice is enabled. 726 PREDICATE_ENABLE_EXECUTEWHENTWOSLICESAREENABLED = 6, //!< Following Commands will be Executed by RCS only when two slices are enabled. 727 PREDICATE_ENABLE_EXECUTEWHENTHREESLICESAREENABLED = 7, //!< Following Commands will be Executed by RCS only when all the three slices are enabled. 728 PREDICATE_ENABLE_NOOPALWAYS = 15, //!< Following Commands will be NOOPED by RCS unconditionally. 729 }; 730 731 enum MI_COMMAND_OPCODE 732 { 733 MI_COMMAND_OPCODE_MISETPREDICATE = 1, //!< No additional details 734 }; 735 736 enum COMMAND_TYPE 737 { 738 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 739 }; 740 741 //! \name Initializations 742 743 //! \brief Explicit member initialization function 744 MI_SET_PREDICATE_CMD(); 745 746 static const size_t dwSize = 1; 747 static const size_t byteSize = 4; 748 }; 749 750 //! 751 //! \brief MI_COPY_MEM_MEM 752 //! \details 753 //! The MI_COPY_MEM_MEM command reads a DWord from memory and stores the 754 //! value of that DWord to back to memory. The source and destination 755 //! addresses are specified in the command. The command temporarily halts 756 //! command execution. 757 //! 758 //! This command should not be used within a "non-privileged" batch buffer 759 //! to access global virtual space; doing so will be treated as privilege 760 //! access violation. Refer to the "User Mode Privilege Command" in 761 //! MI_BATCH_BUFFER_START command section to learn more about HW behavior on 762 //! encountering a privilege access violation. 763 //! 764 //! This command can be used within ring buffers and/or privilege batch 765 //! buffers to access global virtual space. 766 //! 767 struct MI_COPY_MEM_MEM_CMD 768 { 769 union 770 { 771 //!< DWORD 0 772 struct 773 { 774 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 775 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 20) ; //!< Reserved 776 uint32_t UseGlobalGttDestination : __CODEGEN_BITFIELD(21, 21) ; //!< USE_GLOBAL_GTT_DESTINATION 777 uint32_t UseGlobalGttSource : __CODEGEN_BITFIELD(22, 22) ; //!< USE_GLOBAL_GTT_SOURCE 778 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 779 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 780 }; 781 uint32_t Value; 782 } DW0; 783 union 784 { 785 //!< DWORD 1..2 786 struct 787 { 788 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 789 uint64_t DestinationMemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Destination Memory Address 790 }; 791 uint32_t Value[2]; 792 } DW1_2; 793 union 794 { 795 //!< DWORD 3..4 796 struct 797 { 798 uint64_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 799 uint64_t SourceMemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Source Memory Address 800 }; 801 uint32_t Value[2]; 802 } DW3_4; 803 804 //! \name Local enumerations 805 806 //! \brief USE_GLOBAL_GTT_DESTINATION 807 //! \details 808 //! It is allowed for this bit to be set when executing this command from a 809 //! privileged (secure) batch buffer or ring buffer. This bit must be clear 810 //! when programmed from within a non-privileged batch buffer. This bit must 811 //! be 1 if the Per Process GTT Enable bit is clear. 812 enum USE_GLOBAL_GTT_DESTINATION 813 { 814 USE_GLOBAL_GTT_DESTINATION_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 815 USE_GLOBAL_GTT_DESTINATION_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must be executing from a privileged (secure) batch buffer. 816 }; 817 818 //! \brief USE_GLOBAL_GTT_SOURCE 819 //! \details 820 //! It is allowed for this bit to be set when executing this command from a 821 //! privileged (secure) batch buffer or ring buffer. This bit must be clear 822 //! when programmed from within a non-privileged batch buffer. This bit must 823 //! be 1 if the Per Process GTT Enable bit is clear. 824 enum USE_GLOBAL_GTT_SOURCE 825 { 826 USE_GLOBAL_GTT_SOURCE_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 827 USE_GLOBAL_GTT_SOURCE_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must be executing from a privileged (secure) batch buffer. 828 }; 829 830 enum MI_COMMAND_OPCODE 831 { 832 MI_COMMAND_OPCODE_MIMEMTOMEM = 46, //!< No additional details 833 }; 834 835 enum COMMAND_TYPE 836 { 837 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 838 }; 839 840 //! \name Initializations 841 842 //! \brief Explicit member initialization function 843 MI_COPY_MEM_MEM_CMD(); 844 845 static const size_t dwSize = 5; 846 static const size_t byteSize = 20; 847 }; 848 849 //! 850 //! \brief MI_STORE_DATA_IMM 851 //! \details 852 //! The MI_STORE_DATA_IMM command requests a write of the QWord constant 853 //! supplied in the packet to the specified Memory Address. As the write 854 //! targets a System Memory Address, the write operation is coherent with 855 //! the CPU cache (i.e., the processor cache is snooped). 856 //! 857 //! This command supports writing to multiple consecutive dwords or qwords 858 //! memory locations from the starting address. 859 //! 860 //! This command should not be used within a "non-privilege" batch buffer 861 //! to access global virtual space, doing so will be treated as privilege 862 //! access violation. Refer "User Mode Privilege Command" in 863 //! MI_BATCH_BUFFER_START command section to know HW behavior on 864 //! encountering privilege access violation. This command can be used within 865 //! ring buffers and/or privilege batch buffers to access global virtual 866 //! space. 867 //! This command can be used for general software synchronization through 868 //! variables in cacheable memory (i.e., where software does not need to 869 //! poll un-cached memory or device registers). 870 //! This command simply initiates the write operation with command 871 //! execution proceeding normally. Although the write operation is 872 //! guaranteed to complete eventually, there is no mechanism to synchronize 873 //! command execution with the completion (or even initiation) of these 874 //! operations. 875 //! 876 //! 877 //! 878 struct MI_STORE_DATA_IMM_CMD 879 { 880 union 881 { 882 //!< DWORD 0 883 struct 884 { 885 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 9) ; //!< DWORD_LENGTH 886 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 20) ; //!< Reserved 887 uint32_t StoreQword : __CODEGEN_BITFIELD(21, 21) ; //!< Store Qword 888 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< Use Global GTT 889 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 890 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 891 }; 892 uint32_t Value; 893 } DW0; 894 union 895 { 896 //!< DWORD 1..2 897 struct 898 { 899 uint64_t CoreModeEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Core Mode Enable 900 uint64_t Reserved33 : __CODEGEN_BITFIELD( 1, 1) ; //!< Reserved 901 uint64_t Address : __CODEGEN_BITFIELD( 2, 63) ; //!< Address 902 }; 903 uint32_t Value[2]; 904 } DW1_2; 905 union 906 { 907 //!< DWORD 3 908 struct 909 { 910 uint32_t DataDword0 ; //!< Data DWord 0 911 }; 912 uint32_t Value; 913 } DW3; 914 union 915 { 916 //!< DWORD 4 917 struct 918 { 919 uint32_t DataDword1 ; //!< Data DWord 1 920 }; 921 uint32_t Value; 922 } DW4; 923 924 //! \name Local enumerations 925 926 enum MI_COMMAND_OPCODE 927 { 928 MI_COMMAND_OPCODE_MISTOREDATAIMM = 32, //!< No additional details 929 }; 930 931 enum COMMAND_TYPE 932 { 933 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 934 }; 935 936 //! \name Initializations 937 938 //! \brief Explicit member initialization function 939 MI_STORE_DATA_IMM_CMD(); 940 941 static const size_t dwSize = 5; 942 static const size_t byteSize = 20; 943 }; 944 945 //! 946 //! \brief MI_SEMAPHORE_SIGNAL 947 //! \details 948 //! This command is used to signal the target engine stating the memory 949 //! semaphore update occurrence to one of its contexts with Target Context 950 //! ID. MI_SEMPHORE_SIGNAL and MI_SEMAPHORE_WAIT together replace the 951 //! MI_SEMAPHORE_MBOX command on BDW. MI_ATOMIC (non-posted) command will be 952 //! programmed prior to this command to update the semaphore data in memory. 953 //! 954 struct MI_SEMAPHORE_SIGNAL_CMD 955 { 956 union 957 { 958 //!< DWORD 0 959 struct 960 { 961 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 962 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 14) ; //!< Reserved 963 uint32_t TargetEngineSelect : __CODEGEN_BITFIELD(15, 17) ; //!< TARGET_ENGINE_SELECT 964 uint32_t Reserved18 : __CODEGEN_BITFIELD(18, 22) ; //!< Reserved 965 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 966 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 967 }; 968 uint32_t Value; 969 } DW0; 970 union 971 { 972 //!< DWORD 1 973 struct 974 { 975 uint32_t TargetContextId ; //!< Target Context ID 976 }; 977 uint32_t Value; 978 } DW1; 979 980 //! \name Local enumerations 981 982 //! \brief TARGET_ENGINE_SELECT 983 //! \details 984 //! This field selects the target engine to which SIGNAL will be send to. 985 enum TARGET_ENGINE_SELECT 986 { 987 TARGET_ENGINE_SELECT_RCS = 0, //!< No additional details 988 TARGET_ENGINE_SELECT_VCS0 = 1, //!< No additional details 989 TARGET_ENGINE_SELECT_BCS = 2, //!< No additional details 990 TARGET_ENGINE_SELECT_VECS = 3, //!< No additional details 991 TARGET_ENGINE_SELECT_VCS1 = 4, //!< No additional details 992 }; 993 994 enum MI_COMMAND_OPCODE 995 { 996 MI_COMMAND_OPCODE_MISEMAPHORESIGNAL = 27, //!< No additional details 997 }; 998 999 enum COMMAND_TYPE 1000 { 1001 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1002 }; 1003 1004 //! \name Initializations 1005 1006 //! \brief Explicit member initialization function 1007 MI_SEMAPHORE_SIGNAL_CMD(); 1008 1009 static const size_t dwSize = 2; 1010 static const size_t byteSize = 8; 1011 }; 1012 1013 //! 1014 //! \brief MI_SEMAPHORE_WAIT 1015 //! \details 1016 //! This command supports memory based Semaphore WAIT. Memory based 1017 //! semaphores will be used for synchronization between the Producer and the 1018 //! Consumer contexts. Producer and Consumer Contexts could be running on 1019 //! different engines or on the same engine inside GT. Running on the same 1020 //! engine is only possible when execlists are enabled. Producer Context 1021 //! implements a Signal and Consumer context implements a Wait. 1022 //! Command Streamer on parsing this command fetches data from the Semaphore 1023 //! Address mentioned in this command and compares it with the inline 1024 //! Semaphore Data Dword. 1025 //! 1026 //! If comparison passes, the command streamer moves to the next command. 1027 //! 1028 //! When execlists are enabled, if comparison fails Command streamer 1029 //! switches out the context. Context switch can be inhibited by setting 1030 //! "Inhibit Synchronous Context Switch" in CTXT_SR_CTL register. 1031 //! 1032 //! In ring buffer mode of scheduling or Execlist with "Inhibit Synchronous 1033 //! context Switch", if comparison fails, Command Streamer evaluates the 1034 //! Compare Operation based on the Wait Mode until the compare operation is 1035 //! true or Wait is canceled by SW. 1036 //! 1037 //! Exec-List Scheduling: CS generates semaphore wait interrupt to the 1038 //! scheduler when MI_SEMAPHORE_WAIT command is un-successful and when 1039 //! "Inhibit Synchronous Context Switch" is set. Scheduler can use this 1040 //! interrupt to preempt the context waiting on semaphore wait. 1041 //! 1042 //! Ring Buffer Scheduling: CS generates semaphore wait interrupt to the 1043 //! scheduler when MI_SEMAPHORE_WAIT command is un-successful. This is for 1044 //! debug mode 1045 //! 1046 //! 1047 //! 1048 //! MI_SEMPHORE_SIGNAL and MI_SEMAPHORE_WAIT together replace the 1049 //! MI_SEMAPHORE_MBOX command on DevBDW. 1050 //! 1051 //! MI_SEMAPHORE_WAIT command also supports register based Semaphore WAIT. 1052 //! Command Streamer on parsing this command fetches data from the MMIO 1053 //! offset mentioned in this command and compares it with the inline 1054 //! Semaphore Data Dword. This functionality is supported when "Register 1055 //! Poll" bit is set in the command header. In register poll mode of 1056 //! operation "Wait Mode" supported is always Poll mode and no Signal mode 1057 //! is supported. 1058 //! 1059 //! If comparison passes, the command streamer moves to the next command. 1060 //! 1061 //! Unlike in Memory based semaphore, there is no context switch or 1062 //! preemption supported in Register Poll mode of operation. Semaphore wait 1063 //! interrupt is not generated by default on wait un-successful in "Register 1064 //! Poll" mode. However interrupt generation can be enabled by setting debug 1065 //! mode bit "Semaphore Interrupt Enable in Register Poll Mode" in specified 1066 //! register 1067 //! 1068 //! Register Poll mode of Semaphore Wait command operation is privileged and 1069 //! will not be supported from PPGTT batch buffers. 1070 //! 1071 //! HW will not trigger Render DOP CG on semaphore wait unsuccessful in 1072 //! register poll mode of operation. 1073 //! 1074 struct MI_SEMAPHORE_WAIT_CMD 1075 { 1076 union 1077 { 1078 //!< DWORD 0 1079 struct 1080 { 1081 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1082 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 1083 uint32_t CompareOperation : __CODEGEN_BITFIELD(12, 14) ; //!< COMPARE_OPERATION 1084 uint32_t WaitMode : __CODEGEN_BITFIELD(15, 15) ; //!< WAIT_MODE 1085 uint32_t RegisterPollMode : __CODEGEN_BITFIELD(16, 16) ; //!< REGISTER_POLL_MODE 1086 uint32_t Reserved17 : __CODEGEN_BITFIELD(17, 21) ; //!< Reserved 1087 uint32_t MemoryType : __CODEGEN_BITFIELD(22, 22) ; //!< MEMORY_TYPE 1088 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1089 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1090 }; 1091 uint32_t Value; 1092 } DW0; 1093 union 1094 { 1095 //!< DWORD 1 1096 struct 1097 { 1098 uint32_t SemaphoreDataDword ; //!< Semaphore Data Dword 1099 }; 1100 uint32_t Value; 1101 } DW1; 1102 union 1103 { 1104 //!< DWORD 2..3 1105 struct 1106 { 1107 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1108 uint64_t SemaphoreAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Semaphore Address 1109 }; 1110 uint32_t Value[2]; 1111 } DW2_3; 1112 1113 //! \name Local enumerations 1114 1115 //! \brief COMPARE_OPERATION 1116 //! \details 1117 //! This field specifies the operation that will be executed to create the 1118 //! result that will either allow the context to continue or wait. 1119 enum COMPARE_OPERATION 1120 { 1121 COMPARE_OPERATION_SADGREATERTHANSDD = 0, //!< If Indirect fetched data is greater than inline data then continue. 1122 COMPARE_OPERATION_SADGREATERTHANOREQUALSDD = 1, //!< If Indirect fetched data is greater than or equal to inline data then continue. 1123 COMPARE_OPERATION_SADLESSTHANSDD = 2, //!< If Indirect fetched data is less than inline data then continue. 1124 COMPARE_OPERATION_SADLESSTHANOREQUALSDD = 3, //!< If Indirect fetched data is less than or equal to inline data then continue. 1125 COMPARE_OPERATION_SADEQUALSDD = 4, //!< If Indirect fetched data is equalto inline data then continue. 1126 COMPARE_OPERATION_SADNOTEQUALSDD = 5, //!< If Indirect fetched data is not equal to inline data then continue. 1127 }; 1128 1129 //! \brief WAIT_MODE 1130 //! \details 1131 //! This bit specifies the WAIT behavior when the semaphore comparison fails 1132 //! and before the context is switched out. 1133 enum WAIT_MODE 1134 { 1135 WAIT_MODE_SIGNALMODE = 0, //!< In this mode HW will reacquire the semaphore data from memory on receiving SIGNAL with the same Context ID. In ring buffer mode of scheduling Context ID associated with SIGNAL is ignored and always treated as a match. 1136 WAIT_MODE_POLLINGMODE = 1, //!< In this mode HW periodically reads the semaphore data from memory for comparison until it is context switched out. Periodicity will be mentioned in a SEMA_WAIT_POLL register. 1137 }; 1138 1139 //! \brief REGISTER_POLL_MODE 1140 //! \details 1141 //! <p>This field control the seamphore wait behavior of polling from memory 1142 //! vs MMIO register.</p> 1143 enum REGISTER_POLL_MODE 1144 { 1145 REGISTER_POLL_MODE_MEMORYPOLL = 0, //!< In this mode HW will functional as in regular mode and checks for semaphore data in memory. 1146 REGISTER_POLL_MODE_REGISTERPOLL = 1, //!< In this mode HW periodically reads the semaphore data from MMIO register instead of memory for comparison until the condition is satisfied. Periodicity will be mentioned in a SEMA_WAIT_POLL register.When operating in register poll mode, DW2 "Semaphore Address" (bits 22:2) carries the register MMIO offset to be polled.In register poll mode "Memory Type" field of this command are ignored by HW. 1147 }; 1148 1149 //! \brief MEMORY_TYPE 1150 //! \details 1151 //! This bit will be ignored and treated as if clear when executing from a 1152 //! non-privileged batch buffer. It is allowed for this bit to be clear when 1153 //! executing this command from a privileged (secure) batch buffer. This bit 1154 //! <i>must</i> be 1 if the <b>Per Process GTT Enable</b> bit is clear. 1155 enum MEMORY_TYPE 1156 { 1157 MEMORY_TYPE_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 1158 MEMORY_TYPE_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must beexecuting from a privileged (secure) batch buffer. 1159 }; 1160 1161 enum MI_COMMAND_OPCODE 1162 { 1163 MI_COMMAND_OPCODE_MISEMAPHOREWAIT = 28, //!< No additional details 1164 }; 1165 1166 enum COMMAND_TYPE 1167 { 1168 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1169 }; 1170 1171 //! \name Initializations 1172 1173 //! \brief Explicit member initialization function 1174 MI_SEMAPHORE_WAIT_CMD(); 1175 1176 static const size_t dwSize = 4; 1177 static const size_t byteSize = 16; 1178 }; 1179 1180 //! 1181 //! \brief MI_CONDITIONAL_BATCH_BUFFER_END 1182 //! \details 1183 //! The MI_CONDITIONAL_BATCH_BUFFER_END command is used to conditionally 1184 //! terminate the execution of commands stored in a batch buffer initiated 1185 //! using a MI_BATCH_BUFFER_START command. Termination of second level batch 1186 //! buffer due to this command will also terminate the parent/first level 1187 //! batch buffer. 1188 //! 1189 //! 1190 struct MI_CONDITIONAL_BATCH_BUFFER_END_CMD 1191 { 1192 union 1193 { 1194 //!< DWORD 0 1195 struct 1196 { 1197 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1198 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 18) ; //!< Reserved 1199 uint32_t CompareMaskMode : __CODEGEN_BITFIELD(19, 19) ; //!< COMPARE_MASK_MODE 1200 uint32_t Reserved20 : __CODEGEN_BITFIELD(20, 20) ; //!< Reserved 1201 uint32_t CompareSemaphore : __CODEGEN_BITFIELD(21, 21) ; //!< COMPARE_SEMAPHORE 1202 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< USE_GLOBAL_GTT 1203 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1204 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1205 }; 1206 uint32_t Value; 1207 } DW0; 1208 union 1209 { 1210 //!< DWORD 1 1211 struct 1212 { 1213 uint32_t CompareDataDword ; //!< Compare Data Dword 1214 }; 1215 uint32_t Value; 1216 } DW1; 1217 union 1218 { 1219 //!< DWORD 2..3 1220 struct 1221 { 1222 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1223 uint64_t CompareAddress : __CODEGEN_BITFIELD( 3, 63) ; //!< Compare Address 1224 }; 1225 uint32_t Value[2]; 1226 } DW2_3; 1227 1228 //! \name Local enumerations 1229 1230 //! \brief COMPARE_MASK_MODE 1231 //! \details 1232 //! When "Compare Mask Mode" is enabled, "Compare Address" must be qword 1233 //! aligned. 1234 enum COMPARE_MASK_MODE 1235 { 1236 COMPARE_MASK_MODE_COMPAREMASKMODEDISABLED = 0, //!< Compare address points to Dword in memory consisting of Data Dword(DW0). HW will compare Data Dword(DW0) against Semaphore Data Dword. 1237 COMPARE_MASK_MODE_COMPAREMASKMODEENABLED = 1, //!< Compare address points to Qword in memory consisting of compare Mask (DW0) and Data Dword(DW1). HW will do AND operation on Mask(DW0) with Data Dword(DW1) and then compare the result against Semaphore Data Dword. 1238 }; 1239 1240 //! \brief COMPARE_SEMAPHORE 1241 //! \details 1242 //! <p>If set, the value from the Compare Data Dword is compared to the 1243 //! value from the Compare Address in memory. If the value at Compare 1244 //! Address is greater than the Compare Data Dword, execution of current 1245 //! command buffer should continue. If clear, the parser will continue to 1246 //! the next command and not exit the batch buffer.</p> 1247 enum COMPARE_SEMAPHORE 1248 { 1249 COMPARE_SEMAPHORE_UNNAMED0 = 0, //!< No additional details 1250 }; 1251 1252 //! \brief USE_GLOBAL_GTT 1253 //! \details 1254 //! If set, this command will use the global GTT to translate the <b>Compare 1255 //! Address</b> and this command must be executing from a privileged 1256 //! (secure) batch buffer. If clear, the PPGTT will be used to translate the 1257 //! <b>Compare Address</b>. 1258 enum USE_GLOBAL_GTT 1259 { 1260 USE_GLOBAL_GTT_UNNAMED0 = 0, //!< No additional details 1261 }; 1262 1263 enum MI_COMMAND_OPCODE 1264 { 1265 MI_COMMAND_OPCODE_MICONDITIONALBATCHBUFFEREND = 54, //!< No additional details 1266 }; 1267 1268 enum COMMAND_TYPE 1269 { 1270 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1271 }; 1272 1273 //! \name Initializations 1274 1275 //! \brief Explicit member initialization function 1276 MI_CONDITIONAL_BATCH_BUFFER_END_CMD(); 1277 1278 static const size_t dwSize = 4; 1279 static const size_t byteSize = 16; 1280 }; 1281 1282 //! 1283 //! \brief MI_ATOMIC 1284 //! \details 1285 //! MI_ATOMIC is used to carry atomic operation on data in graphics memory. 1286 //! Atomic operations are supported on data granularity of 4B, 8B and 16B. 1287 //! The atomic operation leads to a read-modify-write operation on the data 1288 //! in graphics memory with the option of returning value. The data in 1289 //! graphics memory is modified by doing arithmetic and logical operation 1290 //! with the inline/indirect data provided with the MI_ATOMIC command. 1291 //! Inline/Indirect provided in the command can be one or two operands based 1292 //! on the atomic operation. Ex: Atomic-Compare operation needs two operands 1293 //! while Atomic-Add operation needs single operand and Atomic-increment 1294 //! requires no operand. Refer "Atomics" sub-section under "L3 Cache and 1295 //! URB" section for detailed atomic operations supported. Atomic operations 1296 //! can be enabled to return value by setting "Return Data Control" field in 1297 //! the command, return data is stored to CS_GPR registers. 1298 //! CS_GPR4/5 registers are updated with memory Return Data based on the 1299 //! "Data Size". Each GPR register is qword in size and occupies two MMIO 1300 //! registers. 1301 //! Note: Any references to CS_GPR registers in the command should be 1302 //! understood as the CS_GPR registers belonging to the corresponding 1303 //! engines *CS_GPR registers. 1304 //! 1305 //! 1306 //! Indirect Source Operands: 1307 //! 1308 //! Operand1 is sourced from [CS_GPR1, CS_GPR0] 1309 //! 1310 //! Operand2 is sourced from [CS_GPR3, CS_GPR2] 1311 //! 1312 //! Read return Data is stored in [CS_GPR_5, CS_GPR4] 1313 //! 1314 //! When "Data Size" is DWORD lower dword of CS_GPR4 (Qword) is updated with 1315 //! the dword data returned from memory. When "Data Size" is QWORD only 1316 //! CS_GPR4 (Qword) is updated with the qword data returned from memory. 1317 //! When the data size is OCTWORD CS_GPR4/5 are updated with the OCTWORD 1318 //! data returned from memory. CS_GPR4 is loaded with lower qword returned 1319 //! from memory and CS_GPR5 is loaded with upper qword returned from memory. 1320 //! 1321 //! When Inline Data mode is not set, Dwords 3..10 must not be included as 1322 //! part of the command. Dword Length field in the header must be programmed 1323 //! accordingly. 1324 //! When Inline Data Mode is set, Dwords3..10 must be included based on the 1325 //! Data Size field of the header. Both Operand-1 and Operand-2 dwords must 1326 //! be programmed based on the Data Size field. Operand-2 must be programmed 1327 //! to 0x0 if the atomic operation doesn't require it. Dword Length field in 1328 //! the header must be programmed accordingly. 1329 //! 1330 //! 1331 //! 1332 //! Engines must be IDLE prior to command stream parsing MI_ATOMIC command. 1333 //! MI_FLUSH_DW prior to the MI_ATOMIC command would ensure the engine is 1334 //! IDLE prior to the atomic operation. 1335 //! 1336 struct MI_ATOMIC_CMD 1337 { 1338 union 1339 { 1340 //!< DWORD 0 1341 struct 1342 { 1343 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1344 uint32_t AtomicOpcode : __CODEGEN_BITFIELD( 8, 15) ; //!< ATOMIC OPCODE 1345 uint32_t ReturnDataControl : __CODEGEN_BITFIELD(16, 16) ; //!< Return Data Control 1346 uint32_t CsStall : __CODEGEN_BITFIELD(17, 17) ; //!< CS STALL 1347 uint32_t InlineData : __CODEGEN_BITFIELD(18, 18) ; //!< Inline Data 1348 uint32_t DataSize : __CODEGEN_BITFIELD(19, 20) ; //!< DATA_SIZE 1349 uint32_t Reserved21 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 1350 uint32_t MemoryType : __CODEGEN_BITFIELD(22, 22) ; //!< MEMORY_TYPE 1351 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1352 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1353 }; 1354 uint32_t Value; 1355 } DW0; 1356 union 1357 { 1358 //!< DWORD 1 1359 struct 1360 { 1361 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1362 uint32_t MemoryAddress : __CODEGEN_BITFIELD( 2, 31) ; //!< Memory Address 1363 }; 1364 uint32_t Value; 1365 } DW1; 1366 union 1367 { 1368 //!< DWORD 2 1369 struct 1370 { 1371 uint32_t MemoryAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Memory Address High 1372 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1373 }; 1374 uint32_t Value; 1375 } DW2; 1376 union 1377 { 1378 //!< DWORD 3 1379 struct 1380 { 1381 uint32_t Operand1DataDword0 ; //!< Operand1 Data Dword 0 1382 }; 1383 uint32_t Value; 1384 } DW3; 1385 union 1386 { 1387 //!< DWORD 4 1388 struct 1389 { 1390 uint32_t Operand2DataDword0 ; //!< Operand2 Data Dword 0 1391 }; 1392 uint32_t Value; 1393 } DW4; 1394 union 1395 { 1396 //!< DWORD 5 1397 struct 1398 { 1399 uint32_t Operand1DataDword1 ; //!< Operand1 Data Dword 1 1400 }; 1401 uint32_t Value; 1402 } DW5; 1403 union 1404 { 1405 //!< DWORD 6 1406 struct 1407 { 1408 uint32_t Operand2DataDword1 ; //!< Operand2 Data Dword 1 1409 }; 1410 uint32_t Value; 1411 } DW6; 1412 union 1413 { 1414 //!< DWORD 7 1415 struct 1416 { 1417 uint32_t Operand1DataDword2 ; //!< Operand1 Data Dword 2 1418 }; 1419 uint32_t Value; 1420 } DW7; 1421 union 1422 { 1423 //!< DWORD 8 1424 struct 1425 { 1426 uint32_t Operand2DataDword2 ; //!< Operand2 Data Dword 2 1427 }; 1428 uint32_t Value; 1429 } DW8; 1430 union 1431 { 1432 //!< DWORD 9 1433 struct 1434 { 1435 uint32_t Operand1DataDword3 ; //!< Operand1 Data Dword 3 1436 }; 1437 uint32_t Value; 1438 } DW9; 1439 union 1440 { 1441 //!< DWORD 10 1442 struct 1443 { 1444 uint32_t Operand2DataDword3 ; //!< Operand2 Data Dword 3 1445 }; 1446 uint32_t Value; 1447 } DW10; 1448 1449 //! \name Local enumerations 1450 1451 //! \brief DATA_SIZE 1452 //! \details 1453 //! This field indicates the size of the operand in dword/qword/octword on 1454 //! which atomic operation will be performed. Data size must match with the 1455 //! Atomic Opcode. Operation Data size could be 4B, 8B or 16B 1456 enum DATA_SIZE 1457 { 1458 DATA_SIZE_DWORD = 0, //!< Operand size used by Atomic Operation is DWORD. 1459 DATA_SIZE_QWORD = 1, //!< Operand Size used by Atomic Operation is QWORD. 1460 DATA_SIZE_OCTWORD = 2, //!< Operand Size used by Atomic Operation is OCTWORD. 1461 }; 1462 1463 //! \brief MEMORY_TYPE 1464 //! \details 1465 //! This bit will be ignored and treated as if clear when executing from a 1466 //! non-privileged batch buffer. It is allowed for this bit to be clear when 1467 //! executing this command from a privileged (secure) batch buffer. This bit 1468 //! must be 1 if the <b>Per Process GTT Enable</b> bit is clear. 1469 enum MEMORY_TYPE 1470 { 1471 MEMORY_TYPE_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 1472 MEMORY_TYPE_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must be executing from a privileged (secure) batch buffer. 1473 }; 1474 1475 enum MI_COMMAND_OPCODE 1476 { 1477 MI_COMMAND_OPCODE_MIATOMIC = 47, //!< No additional details 1478 }; 1479 1480 enum COMMAND_TYPE 1481 { 1482 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1483 }; 1484 1485 //! \name Initializations 1486 1487 //! \brief Explicit member initialization function 1488 MI_ATOMIC_CMD(); 1489 1490 static const size_t dwSize = 11; 1491 static const size_t byteSize = 44; 1492 }; 1493 1494 //! 1495 //! \brief MI_MATH 1496 //! \details 1497 //! The MI_MATH command allows software to send instructions to the ALU in 1498 //! the Command Streamer. This command is the means by which the ALU is 1499 //! accessed. ALU instructions form the data payload of the MI_MATH command. 1500 //! An ALU instruction takes one DWord in size. The MI_MATH DWord Length is 1501 //! programmed based on the number of ALU instructions included, limited 1502 //! only by the max DWord Length supported. When the command streamer parses 1503 //! an MI_MATH command, it sends the included ALU instructions to the ALU. 1504 //! The ALU processes any instruction in a single clock. See the ALU section 1505 //! for more details. 1506 //! 1507 struct MI_MATH_CMD 1508 { 1509 union 1510 { 1511 //!< DWORD 0 1512 struct 1513 { 1514 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1515 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 22) ; //!< Reserved 1516 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1517 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1518 }; 1519 uint32_t Value; 1520 } DW0; 1521 1522 //! \name Local enumerations 1523 1524 enum MI_COMMAND_OPCODE 1525 { 1526 MI_COMMAND_OPCODE_MIMATH = 26, //!< No additional details 1527 }; 1528 1529 enum COMMAND_TYPE 1530 { 1531 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1532 }; 1533 1534 //! \name Initializations 1535 1536 //! \brief Explicit member initialization function 1537 MI_MATH_CMD(); 1538 1539 static const size_t dwSize = 1; 1540 static const size_t byteSize = 4; 1541 }; 1542 1543 //! 1544 //! \brief MI_FLUSH_DW 1545 //! \details 1546 //! The MI_FLUSH_DW command is used to perform an internal "flush" 1547 //! operation. The parser pauses on an internal flush until all drawing 1548 //! engines have completed any pending operations. In addition, this command 1549 //! can also be used to:Flush any dirty data to memory. Invalidate the TLB 1550 //! cache inside the hardware Usage note: After this command is completed 1551 //! with a Store DWord enabled, CPU access to graphics memory will be 1552 //! coherent (assuming the Render Cache flush is not inhibited). 1553 //! 1554 struct MI_FLUSH_DW_CMD 1555 { 1556 union 1557 { 1558 //!< DWORD 0 1559 struct 1560 { 1561 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 5) ; //!< DWORD_LENGTH 1562 uint32_t Reserved6 : __CODEGEN_BITFIELD( 6, 6) ; //!< Reserved 1563 uint32_t VideoPipelineCacheInvalidate : __CODEGEN_BITFIELD( 7, 7) ; //!< Video Pipeline Cache invalidate 1564 uint32_t NotifyEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Notify Enable 1565 uint32_t FlushLlc : __CODEGEN_BITFIELD( 9, 9) ; //!< Flush LLC 1566 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 13) ; //!< Reserved 1567 uint32_t PostSyncOperation : __CODEGEN_BITFIELD(14, 15) ; //!< POST_SYNC_OPERATION 1568 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 1569 uint32_t TlbInvalidate : __CODEGEN_BITFIELD(18, 18) ; //!< TLB Invalidate 1570 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 20) ; //!< Reserved 1571 uint32_t StoreDataIndex : __CODEGEN_BITFIELD(21, 21) ; //!< Store Data Index 1572 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 22) ; //!< Reserved 1573 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1574 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1575 }; 1576 uint32_t Value; 1577 } DW0; 1578 union 1579 { 1580 //!< DWORD 1..2 1581 struct 1582 { 1583 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1584 uint64_t DestinationAddressType : __CODEGEN_BITFIELD( 2, 2) ; //!< DESTINATION_ADDRESS_TYPE 1585 uint64_t Address : __CODEGEN_BITFIELD( 3, 47) ; //!< Address 1586 uint64_t Reserved80 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 1587 }; 1588 uint32_t Value[2]; 1589 } DW1_2; 1590 union 1591 { 1592 //!< DWORD 3..4 1593 struct 1594 { 1595 uint64_t ImmediateData ; //!< Immediate Data 1596 }; 1597 uint32_t Value[2]; 1598 } DW3_4; 1599 1600 //! \name Local enumerations 1601 1602 //! \brief POST_SYNC_OPERATION 1603 //! \details 1604 //! BitFieldDesc 1605 enum POST_SYNC_OPERATION 1606 { 1607 POST_SYNC_OPERATION_NOWRITE = 0, //!< No write occurs as a result of this instruction. This can be used to implement a "trap" operation, etc. 1608 POST_SYNC_OPERATION_WRITEIMMEDIATEDATA = 1, //!< HW implicitly detects the Data size to be Qword or Dword to be written to memory based on the command dword length programmed . When Dword Length indicates Qword, Writes the QWord containing Immediate Data Low, High DWs to the Destination Address . When Dword Length indicates Dword, Writes the DWord containing Immediate Data Low to the Destination Address 1609 POST_SYNC_OPERATION_UNNAMED3 = 3, //!< Write the TIMESTAMP register to the Destination Address. The upper 28 bits of the TIMESTAMP register are tied to '0'. 1610 }; 1611 1612 enum MI_COMMAND_OPCODE 1613 { 1614 MI_COMMAND_OPCODE_MIFLUSHDW = 38, //!< No additional details 1615 }; 1616 1617 enum COMMAND_TYPE 1618 { 1619 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1620 }; 1621 1622 //! \brief DESTINATION_ADDRESS_TYPE 1623 //! \details 1624 //! Defines address space of Destination Address 1625 enum DESTINATION_ADDRESS_TYPE 1626 { 1627 DESTINATION_ADDRESS_TYPE_PPGTT = 0, //!< Use PPGTT address space for DW write 1628 DESTINATION_ADDRESS_TYPE_GGTT = 1, //!< Use GGTT address space for DW write 1629 }; 1630 1631 //! \name Initializations 1632 1633 //! \brief Explicit member initialization function 1634 MI_FLUSH_DW_CMD(); 1635 1636 static const size_t dwSize = 5; 1637 static const size_t byteSize = 20; 1638 }; 1639 1640 //! 1641 //! \brief PIPE_CONTROL 1642 //! \details 1643 //! The PIPE_CONTROL command is used to effect the synchronization described 1644 //! above. 1645 //! 1646 struct PIPE_CONTROL_CMD 1647 { 1648 union 1649 { 1650 //!< DWORD 0 1651 struct 1652 { 1653 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1654 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1655 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1656 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1657 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1658 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1659 }; 1660 uint32_t Value; 1661 } DW0; 1662 union 1663 { 1664 //!< DWORD 1 1665 struct 1666 { 1667 uint32_t DepthCacheFlushEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DEPTH_CACHE_FLUSH_ENABLE 1668 uint32_t StallAtPixelScoreboard : __CODEGEN_BITFIELD( 1, 1) ; //!< STALL_AT_PIXEL_SCOREBOARD 1669 uint32_t StateCacheInvalidationEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< State Cache Invalidation Enable 1670 uint32_t ConstantCacheInvalidationEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< Constant Cache Invalidation Enable 1671 uint32_t VfCacheInvalidationEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< VF Cache Invalidation Enable 1672 uint32_t DcFlushEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< DC Flush Enable 1673 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 6) ; //!< Reserved 1674 uint32_t PipeControlFlushEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Pipe Control Flush Enable 1675 uint32_t NotifyEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Notify Enable 1676 uint32_t IndirectStatePointersDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Indirect State Pointers Disable 1677 uint32_t TextureCacheInvalidationEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Texture Cache Invalidation Enable 1678 uint32_t InstructionCacheInvalidateEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Instruction Cache Invalidate Enable 1679 uint32_t RenderTargetCacheFlushEnable : __CODEGEN_BITFIELD(12, 12) ; //!< RENDER_TARGET_CACHE_FLUSH_ENABLE 1680 uint32_t DepthStallEnable : __CODEGEN_BITFIELD(13, 13) ; //!< DEPTH_STALL_ENABLE 1681 uint32_t PostSyncOperation : __CODEGEN_BITFIELD(14, 15) ; //!< POST_SYNC_OPERATION 1682 uint32_t GenericMediaStateClear : __CODEGEN_BITFIELD(16, 16) ; //!< Generic Media State Clear 1683 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 17) ; //!< Reserved 1684 uint32_t TlbInvalidate : __CODEGEN_BITFIELD(18, 18) ; //!< TLB Invalidate 1685 uint32_t GlobalSnapshotCountReset : __CODEGEN_BITFIELD(19, 19) ; //!< GLOBAL_SNAPSHOT_COUNT_RESET 1686 uint32_t CommandStreamerStallEnable : __CODEGEN_BITFIELD(20, 20) ; //!< Command Streamer Stall Enable 1687 uint32_t StoreDataIndex : __CODEGEN_BITFIELD(21, 21) ; //!< Store Data Index 1688 uint32_t Reserved54 : __CODEGEN_BITFIELD(22, 22) ; //!< Reserved 1689 uint32_t LriPostSyncOperation : __CODEGEN_BITFIELD(23, 23) ; //!< LRI_POST_SYNC_OPERATION 1690 uint32_t DestinationAddressType : __CODEGEN_BITFIELD(24, 24) ; //!< DESTINATION_ADDRESS_TYPE 1691 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 25) ; //!< Reserved 1692 uint32_t FlushLlc : __CODEGEN_BITFIELD(26, 26) ; //!< Flush LLC 1693 uint32_t Reserved59 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 1694 }; 1695 uint32_t Value; 1696 } DW1; 1697 union 1698 { 1699 //!< DWORD 2 1700 struct 1701 { 1702 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1703 uint32_t Address : __CODEGEN_BITFIELD( 2, 31) ; //!< Address 1704 }; 1705 uint32_t Value; 1706 } DW2; 1707 union 1708 { 1709 //!< DWORD 3 1710 struct 1711 { 1712 uint32_t AddressHigh ; //!< Address High 1713 }; 1714 uint32_t Value; 1715 } DW3; 1716 union 1717 { 1718 //!< DWORD 4..5 1719 struct 1720 { 1721 uint64_t ImmediateData ; //!< Immediate Data 1722 }; 1723 uint32_t Value[2]; 1724 } DW4_5; 1725 1726 //! \name Local enumerations 1727 1728 enum _3D_COMMAND_SUB_OPCODE 1729 { 1730 _3D_COMMAND_SUB_OPCODE_PIPECONTROL = 0, //!< No additional details 1731 }; 1732 1733 enum _3D_COMMAND_OPCODE 1734 { 1735 _3D_COMMAND_OPCODE_PIPECONTROL = 2, //!< No additional details 1736 }; 1737 1738 enum COMMAND_SUBTYPE 1739 { 1740 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1741 }; 1742 1743 enum COMMAND_TYPE 1744 { 1745 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1746 }; 1747 1748 //! \brief DEPTH_CACHE_FLUSH_ENABLE 1749 //! \details 1750 //! Setting this bit enables flushing (i.e. writing back the dirty lines to 1751 //! memory and invalidating the tags) of depth related caches. This bit 1752 //! applies to HiZ cache, Stencil cache and depth cache. 1753 enum DEPTH_CACHE_FLUSH_ENABLE 1754 { 1755 DEPTH_CACHE_FLUSH_ENABLE_FLUSHDISABLED = 0, //!< Depth relates caches (HiZ, Stencil and Depth) are NOT flushed. 1756 DEPTH_CACHE_FLUSH_ENABLE_FLUSHENABLED = 1, //!< Depth relates caches (HiZ, Stencil and Depth) are flushed. 1757 }; 1758 1759 //! \brief STALL_AT_PIXEL_SCOREBOARD 1760 //! \details 1761 //! Defines the behavior of PIPE_CONTROL command at the pixel scoreboard. 1762 enum STALL_AT_PIXEL_SCOREBOARD 1763 { 1764 STALL_AT_PIXEL_SCOREBOARD_DISABLE = 0, //!< Stall at the pixel scoreboard is disabled. 1765 STALL_AT_PIXEL_SCOREBOARD_ENABLE = 1, //!< Stall at the pixel scoreboard is enabled. 1766 }; 1767 1768 //! \brief RENDER_TARGET_CACHE_FLUSH_ENABLE 1769 //! \details 1770 //! <p>Setting this bit will force Render Cache to be flushed to memory 1771 //! prior to this synchronization point completing. This bit must be set for 1772 //! all write fence sync operations to assure that results from operations 1773 //! initiated prior to this command are visible in memory once software 1774 //! observes this synchronization.</p> 1775 enum RENDER_TARGET_CACHE_FLUSH_ENABLE 1776 { 1777 RENDER_TARGET_CACHE_FLUSH_ENABLE_DISABLEFLUSH = 0, //!< Render Target Cache is NOT flushed. 1778 RENDER_TARGET_CACHE_FLUSH_ENABLE_ENABLEFLUSH = 1, //!< Render Target Cache is flushed. 1779 }; 1780 1781 //! \brief DEPTH_STALL_ENABLE 1782 //! \details 1783 //! <p>This bit must be set when obtaining a "visible pixel" count to 1784 //! preclude the possible inclusion in the PS_DEPTH_COUNT value written to 1785 //! memory of some fraction of pixels from objects initiated after the 1786 //! PIPE_CONTROL command.</p> 1787 enum DEPTH_STALL_ENABLE 1788 { 1789 DEPTH_STALL_ENABLE_DISABLE = 0, //!< 3D pipeline will not stall subsequent primitives at the Depth Test stage. 1790 DEPTH_STALL_ENABLE_ENABLE = 1, //!< 3D pipeline will stall any subsequent primitives at the Depth Test stage until the Sync and Post-Sync operations complete. 1791 }; 1792 1793 //! \brief POST_SYNC_OPERATION 1794 //! \details 1795 //! This field specifies an optional action to be taken upon completion of 1796 //! the synchronization operation. 1797 enum POST_SYNC_OPERATION 1798 { 1799 POST_SYNC_OPERATION_NOWRITE = 0, //!< No write occurs as a result of this instruction. This can be used to implement a "trap" operation, etc. 1800 POST_SYNC_OPERATION_WRITEIMMEDIATEDATA = 1, //!< Write the QWord containing Immediate Data Low, High DWs to the Destination Address 1801 POST_SYNC_OPERATION_WRITEPSDEPTHCOUNT = 2, //!< Write the 64-bit PS_DEPTH_COUNT register to the Destination Address 1802 POST_SYNC_OPERATION_WRITETIMESTAMP = 3, //!< Write the 64-bit TIMESTAMP register(i.e. "Reported Timestamp Count" 0x2358 for render pipe) to the Destination Address. 1803 }; 1804 1805 //! \brief GLOBAL_SNAPSHOT_COUNT_RESET 1806 //! \details 1807 //! <p>This debug mode bit must not be exercised on any product.</p> 1808 enum GLOBAL_SNAPSHOT_COUNT_RESET 1809 { 1810 GLOBAL_SNAPSHOT_COUNT_RESET_DONTRESET = 0, //!< Do not reset the snapshot counts or Statistics Counters. 1811 GLOBAL_SNAPSHOT_COUNT_RESET_RESET = 1, //!< Reset the snapshot count in Gen4 for all the units and reset the Statistics Counters except as noted above. 1812 }; 1813 1814 //! \brief LRI_POST_SYNC_OPERATION 1815 //! \details 1816 //! This bit caues a post sync operation with an LRI (Load Register 1817 //! Immediate) operation. If this bit is set then the Post-Sync Operation 1818 //! field must be cleared. 1819 enum LRI_POST_SYNC_OPERATION 1820 { 1821 LRI_POST_SYNC_OPERATION_NOLRIOPERATION = 0, //!< No LRI operation occurs as a result of this instruction. The Post-Sync Operation field is valid and may be used to specify an operation. 1822 LRI_POST_SYNC_OPERATION_MMIOWRITEIMMEDIATEDATA = 1, //!< Write the DWord contained in Immediate Data Low (DW3) to the MMIO offset specifed in the Address field. 1823 }; 1824 1825 //! \brief DESTINATION_ADDRESS_TYPE 1826 //! \details 1827 //! Defines address space of Destination Address 1828 enum DESTINATION_ADDRESS_TYPE 1829 { 1830 DESTINATION_ADDRESS_TYPE_PPGTT = 0, //!< Use PPGTT address space for DW write 1831 DESTINATION_ADDRESS_TYPE_GGTT = 1, //!< Use GGTT address space for DW write 1832 }; 1833 1834 //! \name Initializations 1835 1836 //! \brief Explicit member initialization function 1837 PIPE_CONTROL_CMD(); 1838 1839 static const size_t dwSize = 6; 1840 static const size_t byteSize = 24; 1841 }; 1842 1843 //! 1844 //! \brief MFX_WAIT 1845 //! \details 1846 //! This command can be considered the same as an MI_NOOP except that the 1847 //! command parser will not parse the next command until the following 1848 //! happens AVC or VC1 BSD mode: The command will stall the parser until 1849 //! completion of the BSD object 1850 //! IT, encoder, and MPEG2 BSD mode: The command will stall the parser 1851 //! until the object package is sent down the pipelineThis command should be 1852 //! used to ensure the preemption enable window occurs during the time the 1853 //! object command is being executed down the pipeline. 1854 //! 1855 //! 1856 struct MFX_WAIT_CMD 1857 { 1858 union 1859 { 1860 //!< DWORD 0 1861 struct 1862 { 1863 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 5) ; //!< DWORD_LENGTH 1864 uint32_t Reserved6 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1865 uint32_t MfxSyncControlFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< MFX Sync Control Flag 1866 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 1867 uint32_t SubOpcode : __CODEGEN_BITFIELD(16, 26) ; //!< SUB_OPCODE 1868 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1869 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1870 }; 1871 uint32_t Value; 1872 } DW0; 1873 1874 //! \name Local enumerations 1875 1876 enum SUB_OPCODE 1877 { 1878 SUB_OPCODE_MFXWAIT = 0, //!< No additional details 1879 }; 1880 1881 enum COMMAND_SUBTYPE 1882 { 1883 COMMAND_SUBTYPE_MFXSINGLEDW = 1, //!< No additional details 1884 }; 1885 1886 enum COMMAND_TYPE 1887 { 1888 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1889 }; 1890 1891 //! \name Initializations 1892 1893 //! \brief Explicit member initialization function 1894 MFX_WAIT_CMD(); 1895 1896 static const size_t dwSize = 1; 1897 static const size_t byteSize = 4; 1898 }; 1899 1900 //! 1901 //! \brief MEDIA_STATE_FLUSH 1902 //! \details 1903 //! This command updates the Message Gateway state. In particular, it 1904 //! updates the state for a selected Interface Descriptor. 1905 //! 1906 //! This command can be considered same as a MI_Flush except that only media 1907 //! parser will get flushed instead of the entire 3D/media render pipeline. 1908 //! The command should be programmed prior to new Media state, curbe and/or 1909 //! interface descriptor commands when switching to a new context or 1910 //! programming new state for the same context. With this command, pipelined 1911 //! state change is allowed for the media pipe. 1912 //! 1913 //! Be cautious when using this command when child_present flag in the media 1914 //! state is enabled. This is because that CURBE state as well as Interface 1915 //! Descriptor state are shared between root threads and child threads. 1916 //! Changing these states while child threads are generated on the fly may 1917 //! cause unexpected behavior. Combining with MI_ARB_ON/OFF command, it is 1918 //! possible to support interruptability with the following command sequence 1919 //! where interrupt may be allowed only when MI_ARB_ON_OFF is ON: 1920 //! 1921 //! <pre>MEDIA_STATE_FLUSH 1922 //! VFE_STATE VFE will hold CS if watermark isn't met 1923 //! MI_ARB_OFF There must be at least one VFE command before this one 1924 //! MEDIA_OBJECT ... MI_ARB_ON</pre> 1925 //! 1926 //! Due to the known HW issue MEDIA_STATE_FLUSH command is not preemptable 1927 //! in GPGPU workloads. This might result in reduced frequency of preempting 1928 //! GPGPU walker in below programming sequence. 1929 //! <pre>State Commands 1930 //! GPGPU_WALKER 1931 //! MEDIA_STATE_FLUSH 1932 //! State Commands 1933 //! GPGPU_WALKER 1934 //! MEDIA_STATE_FLUSH 1935 //! State Commands</pre> 1936 //! 1937 //! MI_ARB_CHK command must be programmed following MEDIA_STATE_FLUSH 1938 //! command. PIPECONTROL ("Command Streamer Stall Enable" set and "Render 1939 //! Target Cache Flush Enable" set) must be programmed prior to 1940 //! MEDIA_STATE_FLUSH command with "Flush to GO" bit set. "Water Mark 1941 //! Required" field must not be set in "MEDIA_STATE_FLUSH" command. 1942 //! 1943 struct MEDIA_STATE_FLUSH_CMD 1944 { 1945 union 1946 { 1947 //!< DWORD 0 1948 struct 1949 { 1950 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 1951 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 1952 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1953 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1954 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1955 }; 1956 uint32_t Value; 1957 } DW0; 1958 union 1959 { 1960 //!< DWORD 1 1961 struct 1962 { 1963 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 1964 uint32_t WatermarkRequired : __CODEGEN_BITFIELD( 6, 6) ; //!< Watermark Required 1965 uint32_t FlushToGo : __CODEGEN_BITFIELD( 7, 7) ; //!< Flush to GO 1966 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 1967 }; 1968 uint32_t Value; 1969 } DW1; 1970 1971 //! \name Local enumerations 1972 1973 enum SUBOPCODE 1974 { 1975 SUBOPCODE_MEDIASTATEFLUSHSUBOP = 4, //!< No additional details 1976 }; 1977 1978 enum MEDIA_COMMAND_OPCODE 1979 { 1980 MEDIA_COMMAND_OPCODE_MEDIASTATEFLUSH = 0, //!< No additional details 1981 }; 1982 1983 enum PIPELINE 1984 { 1985 PIPELINE_MEDIA = 2, //!< No additional details 1986 }; 1987 1988 enum COMMAND_TYPE 1989 { 1990 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1991 }; 1992 1993 //! \name Initializations 1994 1995 //! \brief Explicit member initialization function 1996 MEDIA_STATE_FLUSH_CMD(); 1997 1998 static const size_t dwSize = 2; 1999 static const size_t byteSize = 8; 2000 }; 2001 2002 }; 2003 2004 #pragma pack() 2005 2006 #endif // __MHW_MI_HWCMD_G9_X_H__