1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi_hwcmd_g8_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g8_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_MI_HWCMD_G8_X_H__ 29 #define __MHW_MI_HWCMD_G8_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_mi_g8_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MI_BATCH_BUFFER_END 50 //! \details 51 //! The MI_BATCH_BUFFER_END command is used to terminate the execution of 52 //! commands stored in a batch buffer initiated using a 53 //! MI_BATCH_BUFFER_START command. 54 //! 55 struct MI_BATCH_BUFFER_END_CMD 56 { 57 union 58 { 59 //!< DWORD 0 60 struct 61 { 62 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 22) ; //!< Reserved 63 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 64 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 65 }; 66 uint32_t Value; 67 } DW0; 68 69 //! \name Local enumerations 70 71 enum MI_COMMAND_OPCODE 72 { 73 MI_COMMAND_OPCODE_MIBATCHBUFFEREND = 10, //!< No additional details 74 }; 75 76 enum COMMAND_TYPE 77 { 78 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 79 }; 80 81 //! \name Initializations 82 83 //! \brief Explicit member initialization function 84 MI_BATCH_BUFFER_END_CMD(); 85 86 static const size_t dwSize = 1; 87 static const size_t byteSize = 4; 88 }; 89 90 //! 91 //! \brief MI_NOOP 92 //! \details 93 //! The MI_NOOP command basically performs a "no operation" in the command 94 //! stream and is typically used to pad the command stream (e.g., in order 95 //! to pad out a batch buffer to a QWord boundary). However, there is one 96 //! minor (optional) function this command can perform - a 22-bit value can 97 //! be loaded into the MI NOPID register. This provides a general-purpose 98 //! command stream tagging ("breadcrumb") mechanism (e.g., to provide 99 //! sequencing information for a subsequent breakpoint interrupt). 100 //! 101 struct MI_NOOP_CMD 102 { 103 union 104 { 105 //!< DWORD 0 106 struct 107 { 108 uint32_t IdentificationNumber : __CODEGEN_BITFIELD( 0, 21) ; //!< Identification Number 109 uint32_t IdentificationNumberRegisterWriteEnable : __CODEGEN_BITFIELD(22, 22) ; //!< IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE 110 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 111 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 112 }; 113 uint32_t Value; 114 } DW0; 115 116 //! \name Local enumerations 117 118 //! \brief IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE 119 //! \details 120 //! This field enables the value in the Identification Number field to be 121 //! written into the MI NOPID register. If disabled, that register is 122 //! unmodified - making this command an effective "no operation" function. 123 enum IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE 124 { 125 IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE_WRITETHENOPIDREGISTER = 1, //!< No additional details 126 }; 127 128 enum MI_COMMAND_OPCODE 129 { 130 MI_COMMAND_OPCODE_MINOOP = 0, //!< No additional details 131 }; 132 133 enum COMMAND_TYPE 134 { 135 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 136 }; 137 138 //! \name Initializations 139 140 //! \brief Explicit member initialization function 141 MI_NOOP_CMD(); 142 143 static const size_t dwSize = 1; 144 static const size_t byteSize = 4; 145 }; 146 147 //! 148 //! \brief MI_ARB_CHECK 149 //! \details 150 //! The MI_ARB_CHECK is used to check for a change in arbitration. If 151 //! executed as part of a Ring Buffer the command checks the UHPTR valid bit 152 //! and if set the head of the ring will jump to the value of the head 153 //! pointer programmed in the UHPTR. 154 //! 155 //! This instruction cannot be placed in a batch buffer. 156 //! 157 //! If execlist is enabled, there is a pending execution list and this 158 //! command is parsed, then the command streamer will preempt the current 159 //! context and start executing the new execution list. 160 //! 161 struct MI_ARB_CHECK_CMD 162 { 163 union 164 { 165 //!< DWORD 0 166 struct 167 { 168 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 22) ; //!< Reserved 169 uint32_t MiInstructionOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_INSTRUCTION_OPCODE 170 uint32_t MiInstructionType : __CODEGEN_BITFIELD(29, 31) ; //!< MI_INSTRUCTION_TYPE 171 }; 172 uint32_t Value; 173 } DW0; 174 175 //! \name Local enumerations 176 177 enum MI_INSTRUCTION_OPCODE 178 { 179 MI_INSTRUCTION_OPCODE_MIARBCHECK = 5, //!< No additional details 180 }; 181 182 enum MI_INSTRUCTION_TYPE 183 { 184 MI_INSTRUCTION_TYPE_MIINSTRUCTION = 0, //!< No additional details 185 }; 186 187 //! \name Initializations 188 189 //! \brief Explicit member initialization function 190 MI_ARB_CHECK_CMD(); 191 192 static const size_t dwSize = 1; 193 static const size_t byteSize = 4; 194 }; 195 196 //! 197 //! \brief MI_LOAD_REGISTER_IMM 198 //! \details 199 //! The MI_LOAD_REGISTER_IMM command requests a write of up to a DWord 200 //! constant supplied in the command to the specified Register Offset (i.e., 201 //! offset into Memory-Mapped Register Range). The register is loaded before 202 //! the next command is executed. 203 //! Any offset that is to a destination outside of the GT core will allow 204 //! the parser to continue once the cycle is at the GT boundry and not 205 //! destination. Any other address will ensure the destination is updated 206 //! prior to parsing the next command 207 //! 208 struct MI_LOAD_REGISTER_IMM_CMD 209 { 210 union 211 { 212 //!< DWORD 0 213 struct 214 { 215 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 216 uint32_t ByteWriteDisables : __CODEGEN_BITFIELD( 8, 11) ; //!< Byte Write Disables 217 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 22) ; //!< Reserved 218 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 219 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 220 }; 221 uint32_t Value; 222 } DW0; 223 union 224 { 225 //!< DWORD 1 226 struct 227 { 228 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 229 uint32_t RegisterOffset : __CODEGEN_BITFIELD( 2, 22) ; //!< Register Offset 230 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 231 }; 232 uint32_t Value; 233 } DW1; 234 union 235 { 236 //!< DWORD 2 237 struct 238 { 239 uint32_t DataDword ; //!< Data DWord 240 }; 241 uint32_t Value; 242 } DW2; 243 244 //! \name Local enumerations 245 246 enum MI_COMMAND_OPCODE 247 { 248 MI_COMMAND_OPCODE_MILOADREGISTERIMM = 34, //!< No additional details 249 }; 250 251 enum COMMAND_TYPE 252 { 253 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 254 }; 255 256 //! \name Initializations 257 258 //! \brief Explicit member initialization function 259 MI_LOAD_REGISTER_IMM_CMD(); 260 261 static const size_t dwSize = 3; 262 static const size_t byteSize = 12; 263 }; 264 265 //! 266 //! \brief MI_LOAD_REGISTER_MEM 267 //! \details 268 //! The MI_LOAD_REGISTER_MEM command requests from a memory location and 269 //! stores that DWord to a register. 270 //! 271 //! The command temporarily halts commands that will cause cycles down the 272 //! 3D pipeline. 273 //! 274 //! The following addresses should NOT be used for MMIO writes: 275 //! 276 //! 0x8800 - 0x88FF 277 //! 278 //! >= 0xC0000 279 //! 280 //! 281 //! 282 //! Limited MMIO writes cycles to the Display Engine 0x40000-0xBFFFF) are 283 //! allowed, but must be spaced to allow only one pending at a time. This 284 //! can be done by issuing an SRM to the same address immediately after each 285 //! MMIO write. 286 //! 287 //! Any updates to the memory location exercised by this command must be 288 //! ensured to be coherent in memory prior to programming of this command. 289 //! This must be achieved by programming MI_ATOMIC (write to scratch space) 290 //! with "CS STALL" set prior to programming of this command. 291 //! Example: 292 //! MI_STORE_REGISTE_MEM (0x2288, 0x2CF0_0000) 293 //! ……… 294 //! ……… 295 //! MI_ATOMIC (MOV, Dummy data, Scratch Address) 296 //! MI_LOAD_REGISTER_MEM(0x2288, 0x2CF0_0000) 297 //! 298 //! This command should not be used within a non-privilege batch buffer to 299 //! access global virtual space, doing so will be treated as privilege 300 //! access violation. Refer "User Mode Privilege Command" in 301 //! MI_BATCH_BUFFER_START command section to know HW behavior on 302 //! encountering privilege access violation. 303 //! 304 //! This command is not allowed to update the privilege register range when 305 //! executed from a non-privilege batch buffer. 306 //! 307 //! Writes to the range 0x9400-0x97FF must be either be avoided, or 308 //! serialized with a read (e.g. STORE_REGISTER_MEM) between them. 309 //! 310 struct MI_LOAD_REGISTER_MEM_CMD 311 { 312 union 313 { 314 //!< DWORD 0 315 struct 316 { 317 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 318 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 20) ; //!< Reserved 319 uint32_t AsyncModeEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Async Mode Enable 320 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< Use Global GTT 321 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 322 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 323 }; 324 uint32_t Value; 325 } DW0; 326 union 327 { 328 //!< DWORD 1 329 struct 330 { 331 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 332 uint32_t RegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Register Address 333 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 334 }; 335 uint32_t Value; 336 } DW1; 337 union 338 { 339 //!< DWORD 2..3 340 struct 341 { 342 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 343 uint64_t MemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Memory Address 344 }; 345 uint32_t Value[2]; 346 } DW2_3; 347 348 //! \name Local enumerations 349 350 enum MI_COMMAND_OPCODE 351 { 352 MI_COMMAND_OPCODE_MILOADREGISTERMEM = 41, //!< No additional details 353 }; 354 355 enum COMMAND_TYPE 356 { 357 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 358 }; 359 360 //! \name Initializations 361 362 //! \brief Explicit member initialization function 363 MI_LOAD_REGISTER_MEM_CMD(); 364 365 static const size_t dwSize = 4; 366 static const size_t byteSize = 16; 367 }; 368 369 //! 370 //! \brief MI_LOAD_REGISTER_REG 371 //! \details 372 //! The MI_LOAD_REGISTER_REG command reads from a source register location 373 //! and writes that value to a destination register location. 374 //! Any offset that is to a destination outside of the GT core will allow 375 //! the parser to continue once the cycle is at the GT boundry and not 376 //! destination. Any other address will ensure the destination is updated 377 //! prior to parsing the next command 378 //! 379 //! The command temporarily halts commands that will cause cycles down the 380 //! 3D pipeline. 381 //! 382 //! Destination register with mask implemented (Ex: some 383 //! registers have bits [31:16] as mask bits and bits[15:0] as data) will 384 //! not get updated unless the value read from source register has the bits 385 //! corresponding to the mask bits set. Note that any mask implemented 386 //! register when read returns "0" for the bits corresponding to mask 387 //! location. When the source and destination are mask implemented 388 //! registers, destination register will not get updated with the source 389 //! register contents. 390 //! 391 //! This command is not allowed to update the privilege register range when 392 //! executed from a non-privilege batch buffer. 393 //! 394 //! MI_LOAD_REGISTER_REG must not be used to access registers outside GT 395 //! (MMIO >= 40000h) on BDW-A stepping. 396 //! 397 //! Writes to the range 0x9400-0x97FF must be either be avoided, or 398 //! serialized with a read (e.g. STORE_REGISTER_MEM) between them. 399 //! 400 struct MI_LOAD_REGISTER_REG_CMD 401 { 402 union 403 { 404 //!< DWORD 0 405 struct 406 { 407 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 408 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 22) ; //!< Reserved 409 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 410 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 411 }; 412 uint32_t Value; 413 } DW0; 414 union 415 { 416 //!< DWORD 1 417 struct 418 { 419 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 420 uint32_t SourceRegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Source Register Address 421 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 422 }; 423 uint32_t Value; 424 } DW1; 425 union 426 { 427 //!< DWORD 2 428 struct 429 { 430 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 431 uint32_t DestinationRegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Destination Register Address 432 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 433 }; 434 uint32_t Value; 435 } DW2; 436 437 //! \name Local enumerations 438 439 enum MI_COMMAND_OPCODE 440 { 441 MI_COMMAND_OPCODE_MILOADREGISTERREG = 42, //!< No additional details 442 }; 443 444 enum COMMAND_TYPE 445 { 446 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 447 }; 448 449 //! \name Initializations 450 451 //! \brief Explicit member initialization function 452 MI_LOAD_REGISTER_REG_CMD(); 453 454 static const size_t dwSize = 3; 455 static const size_t byteSize = 12; 456 }; 457 458 //! 459 //! \brief MI_STORE_REGISTER_MEM 460 //! \details 461 //! The MI_STORE_REGISTER_MEM command requests a register read from a 462 //! specified memory mapped register location in the device and store of 463 //! that DWord to memory. The register address is specified along with the 464 //! command to perform the read. 465 //! 466 //! 467 //! The command temporarily halts command execution. 468 //! 469 //! The memory address for the write is snooped on the host bus. 470 //! 471 //! This command should not be used from within a "non-privilege" batch 472 //! buffer to access global virtual space. doing so will be treated as 473 //! privilege access violation. Refer "User Mode Privilege Command" in 474 //! MI_BATCH_BUFFER_START command section to know HW behavior on 475 //! encountering privilege access violation. This command can be used within 476 //! ring buffers and/or "privilege" batch buffers to access global virtual 477 //! space. 478 //! 479 //! This command will cause undefined data to be written to memory if given 480 //! register addresses for the PGTBL_CTL_0 or FENCE registers. 481 //! 482 //! 483 //! 484 //! MI_STORE_REGISTER_MEM must not be used to access registers outside GT 485 //! (MMIO >= 40000h) on BDW-A stepping. 486 //! 487 //! Source: BlitterCS, VideoCS, VideoEnhancementCS 488 //! The source MMIO offset must be limited to any MMIO that is not 489 //! replicated due to multiple slice configurations. If slice zero is 490 //! disabled, then any MMIO read from this command streamer to a register 491 //! replicated in the slice will cause a return value of zero. 492 //! 493 struct MI_STORE_REGISTER_MEM_CMD 494 { 495 union 496 { 497 //!< DWORD 0 498 struct 499 { 500 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 501 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 21) ; //!< Reserved 502 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< Use Global GTT 503 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 504 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 505 }; 506 uint32_t Value; 507 } DW0; 508 union 509 { 510 //!< DWORD 1 511 struct 512 { 513 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 514 uint32_t RegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Register Address 515 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 516 }; 517 uint32_t Value; 518 } DW1; 519 union 520 { 521 //!< DWORD 2..3 522 struct 523 { 524 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 525 uint64_t MemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Memory Address 526 }; 527 uint32_t Value[2]; 528 } DW2_3; 529 530 //! \name Local enumerations 531 532 enum MI_COMMAND_OPCODE 533 { 534 MI_COMMAND_OPCODE_MISTOREREGISTERMEM = 36, //!< No additional details 535 }; 536 537 enum COMMAND_TYPE 538 { 539 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 540 }; 541 542 //! \name Initializations 543 544 //! \brief Explicit member initialization function 545 MI_STORE_REGISTER_MEM_CMD(); 546 547 static const size_t dwSize = 4; 548 static const size_t byteSize = 16; 549 }; 550 551 //! 552 //! \brief MI_BATCH_BUFFER_START 553 //! \details 554 //! The MI_BATCH_BUFFER_START command is used to initiate the execution of 555 //! commands stored in a batch buffer. For restrictions on the location of 556 //! batch buffers, see Batch Buffers in the Device Programming Interface 557 //! chapter of MI Functions.The batch buffer can be specified as secure or 558 //! non-secure, determining the operations considered valid when initiated 559 //! from within the buffer and any attached (chained) batch buffers. See 560 //! Batch Buffer Protection in the Device Programming Interface chapter of 561 //! MI Functions. 562 //! 563 struct MI_BATCH_BUFFER_START_CMD 564 { 565 union 566 { 567 //!< DWORD 0 568 struct 569 { 570 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 571 uint32_t AddressSpaceIndicator : __CODEGEN_BITFIELD( 8, 8) ; //!< ADDRESS_SPACE_INDICATOR 572 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 21) ; //!< Reserved 573 uint32_t SecondLevelBatchBuffer : __CODEGEN_BITFIELD(22, 22) ; //!< _2ND_LEVEL_BATCH_BUFFER 574 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 575 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 576 }; 577 uint32_t Value; 578 } DW0; 579 union 580 { 581 //!< DWORD 1 582 struct 583 { 584 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 585 uint32_t BatchBufferStartAddress : __CODEGEN_BITFIELD( 2, 31) ; //!< Batch Buffer Start Address 586 }; 587 uint32_t Value; 588 } DW1; 589 union 590 { 591 //!< DWORD 2 592 struct 593 { 594 uint32_t BatchBufferStartAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Batch Buffer Start Address High 595 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 596 }; 597 uint32_t Value; 598 } DW2; 599 600 //! \name Local enumerations 601 602 //! \brief ADDRESS_SPACE_INDICATOR 603 //! \details 604 //! <p>Batch buffers accessed via PPGTT are considered as non-privileged. 605 //! Certain operations 606 //! (e.g., MI_STORE_DATA_IMM commands to GGTT memory) are prohibited 607 //! within non-privileged 608 //! buffers. More details mentioned in User Mode Privileged command 609 //! section. When 610 //! MI_BATCH_BUFFER_START command is executed from within a batch 611 //! buffer (i.e., is a "chained" 612 //! or "second level" batch buffer command), the current active batch 613 //! buffer's "Address Space 614 //! Indicator" and this field determine the "Address Space Indicator" 615 //! of the next buffer in the chain.</p> 616 //! <ul> 617 //! <li>Chained or Second level batch buffer can be in GGTT or PPGTT 618 //! if the parent batch buffer is in GGTT.</li> 619 //! <li>Chained or Second level batch buffer can only be in PPGTT if 620 //! the parent batch buffer is in PPGTT. This is enforced by Hardware.</li> 621 //! </ul> 622 enum ADDRESS_SPACE_INDICATOR 623 { 624 ADDRESS_SPACE_INDICATOR_GGTT = 0, //!< This batch buffer is located in GGTT memory and is privileged. 625 ADDRESS_SPACE_INDICATOR_PPGTT = 1, //!< This batch buffer is located in PPGTT memory and is Non-Privileged. 626 }; 627 628 //! \brief _2ND_LEVEL_BATCH_BUFFER 629 //! \details 630 //! The command streamer contains 3 storage elements; 1 for the ring head 631 //! address, 1 for the batch head address, and 1 for the 2nd level batch 632 //! head address. When performing batch buffer chaining, hardware simply 633 //! updates the head pointer of the 1st level batch address storage. There 634 //! is no stack in hardware. When this bit is set, hardware uses the 2nd 635 //! level batch head address storage element. Upon MI_BATCH_BUFFER_END, it 636 //! will automatically return to the 1st (traditional) level batch buffer 637 //! address. this allows hardware to mimic a simple 3 level stack. 638 enum _2ND_LEVEL_BATCH_BUFFER 639 { 640 _2ND_LEVEL_BATCH_BUFFER_1STLEVELBATCH = 0, //!< Place the batch buffer address in the 1st (traditional) level batch address storage element 641 _2ND_LEVEL_BATCH_BUFFER_2NDLEVELBATCH = 1, //!< Place the batch buffer address in the 2nd level batch address storage element 642 }; 643 644 enum MI_COMMAND_OPCODE 645 { 646 MI_COMMAND_OPCODE_MIBATCHBUFFERSTART = 49, //!< No additional details 647 }; 648 649 enum COMMAND_TYPE 650 { 651 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 652 }; 653 654 //! \name Initializations 655 656 //! \brief Explicit member initialization function 657 MI_BATCH_BUFFER_START_CMD(); 658 659 static const size_t dwSize = 3; 660 static const size_t byteSize = 12; 661 }; 662 663 //! 664 //! \brief MI_SET_PREDICATE 665 //! \details 666 //! This command sets the Predication Check for the subsequent commands in 667 //! the command buffer except for MI_SET_PREDICATE itself. Render Command 668 //! Streamer NOOPs the following commands based on the PREDICATE_ENABLE from 669 //! MI_SET_PREDICATE, MI_SET_PREDICATE_RESULT and MI_SET_PREDICATE_RESULT_2 670 //! status. Resource Streamer doesn't take any action of parsing 671 //! MI_SET_PREDICATE, this command is similar to any other command which is 672 //! not meant for resource streamer. 673 //! 674 //! Executing MI_SET_PREDICATE command sets PREDICATE_ENABLE bits in MI_MODE 675 //! register, MI_MODE register gets render context save restored. 676 //! 677 //! MI_SET_PREDICATE predication scope must be confined within a Batch 678 //! Buffer to set of commands. 679 //! MI_SET_PREDICATE with Predicate Enable Must always have a 680 //! corresponding MI_SET_PREDICATE with Predicate Disable within the same 681 //! Batch Buffer. 682 //! MI_ARB_CHK command must be programmed outside the Predication Scope of 683 //! MI_SET_PREDICATE. 684 //! MI_SET_PREDICATE Predication Scope must not involve any RC6 triggering 685 //! events. 686 //! 687 //! 688 //! Only the following command(s) can be programmed between the 689 //! MI_SET_PREDICATE command enabled for predication: 3DSTATE_URB_VS 690 //! 3DSTATE_URB_HS 3DSTATE_URB_DS 3DSTATE_URB_GS 691 //! 3DSTATE_PUSH_CONSTANT_ALLOC_VS 3DSTATE_PUSH_CONSTANT_ALLOC_HS 692 //! 3DSTATE_PUSH_CONSTANT_ALLOC_DS 3DSTATE_PUSH_CONSTANT_ALLOC_GS 693 //! 3DSTATE_PUSH_CONSTANT_ALLOC_PS MI_LOAD_REGISTER_IMM MEDIA_VFE_STATE 694 //! MEDIA_OBJECT MEDIA_OBJJECT_WALKER MEDIA_INTERFACE_DESCRIPTOR_LOAD 695 //! 3DSTATE_WM_HZ_OP 696 //! 697 struct MI_SET_PREDICATE_CMD 698 { 699 union 700 { 701 //!< DWORD 0 702 struct 703 { 704 uint32_t PredicateEnable : __CODEGEN_BITFIELD( 0, 3) ; //!< PREDICATE_ENABLE 705 uint32_t Reserved4 : __CODEGEN_BITFIELD( 4, 22) ; //!< Reserved 706 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 707 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 708 }; 709 uint32_t Value; 710 } DW0; 711 712 //! \name Local enumerations 713 714 //! \brief PREDICATE_ENABLE 715 //! \details 716 //! This field sets the predication logic in render command streamer when 717 //! parsed. Predicate Disable is the default mode of operation. 718 enum PREDICATE_ENABLE 719 { 720 PREDICATE_ENABLE_NOOPNEVER = 0, //!< Predication is Disabled and RCS will process commands as usual. 721 PREDICATE_ENABLE_NOOPONRESULT2CLEAR = 1, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT_2 is clear. 722 PREDICATE_ENABLE_NOOPONRESULT2SET = 2, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT_2 is set. 723 PREDICATE_ENABLE_NOOPONRESULTCLEAR = 3, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT is clear. 724 PREDICATE_ENABLE_NOOPONRESULTSET = 4, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT is set. 725 PREDICATE_ENABLE_EXECUTEWHENONESLICEENABLED = 5, //!< Following Commands will be Executed by RCS only when one slice is enabled. 726 PREDICATE_ENABLE_EXECUTEWHENTWOSLICESAREENABLED = 6, //!< Following Commands will be Executed by RCS only when two slices are enabled. 727 PREDICATE_ENABLE_EXECUTEWHENTHREESLICESAREENABLED = 7, //!< Following Commands will be Executed by RCS only when all the three slices are enabled. 728 PREDICATE_ENABLE_NOOPALWAYS = 15, //!< Following Commands will be NOOPED by RCS unconditionally. 729 }; 730 731 enum MI_COMMAND_OPCODE 732 { 733 MI_COMMAND_OPCODE_MISETPREDICATE = 1, //!< No additional details 734 }; 735 736 enum COMMAND_TYPE 737 { 738 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 739 }; 740 741 //! \name Initializations 742 743 //! \brief Explicit member initialization function 744 MI_SET_PREDICATE_CMD(); 745 746 static const size_t dwSize = 1; 747 static const size_t byteSize = 4; 748 }; 749 750 //! 751 //! \brief MI_COPY_MEM_MEM 752 //! \details 753 //! The MI_COPY_MEM_MEM command reads a DWord from memory and stores the 754 //! value of that DWord to back to memory. The source and destination 755 //! addresses are specified in the command. The command temporarily halts 756 //! command execution. 757 //! 758 //! This command should not be used within a "non-privileged" batch buffer 759 //! to access global virtual space; doing so will be treated as privilege 760 //! access violation. Refer to the "User Mode Privilege Command" in 761 //! MI_BATCH_BUFFER_START command section to learn more about HW behavior on 762 //! encountering a privilege access violation. 763 //! 764 //! This command can be used within ring buffers and/or privilege batch 765 //! buffers to access global virtual space. 766 //! 767 //! This command can cause a hang when run concurrently with a submission of 768 //! an execution list of the same ID and Force Restore is not set in the 769 //! Context Descriptor Format. A sequence of MI_LOAD_REG_MEM and 770 //! MI_STORE_REG_MEM with temporary GPR registers must be used in place of 771 //! this command or all submissions would require Force Restore enabled. 772 //! 773 struct MI_COPY_MEM_MEM_CMD 774 { 775 union 776 { 777 //!< DWORD 0 778 struct 779 { 780 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 781 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 20) ; //!< Reserved 782 uint32_t UseGlobalGttDestination : __CODEGEN_BITFIELD(21, 21) ; //!< USE_GLOBAL_GTT_DESTINATION 783 uint32_t UseGlobalGttSource : __CODEGEN_BITFIELD(22, 22) ; //!< USE_GLOBAL_GTT_SOURCE 784 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 785 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 786 }; 787 uint32_t Value; 788 } DW0; 789 union 790 { 791 //!< DWORD 1..2 792 struct 793 { 794 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 795 uint64_t DestinationMemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Destination Memory Address 796 }; 797 uint32_t Value[2]; 798 } DW1_2; 799 union 800 { 801 //!< DWORD 3..4 802 struct 803 { 804 uint64_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 805 uint64_t SourceMemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Source Memory Address 806 }; 807 uint32_t Value[2]; 808 } DW3_4; 809 810 //! \name Local enumerations 811 812 //! \brief USE_GLOBAL_GTT_DESTINATION 813 //! \details 814 //! It is allowed for this bit to be set when executing this command from a 815 //! privileged (secure) batch buffer or ring buffer. This bit must be clear 816 //! when programmed from within a non-privileged batch buffer. This bit must 817 //! be 1 if the Per Process GTT Enable bit is clear. 818 enum USE_GLOBAL_GTT_DESTINATION 819 { 820 USE_GLOBAL_GTT_DESTINATION_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 821 USE_GLOBAL_GTT_DESTINATION_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must be executing from a privileged (secure) batch buffer. 822 }; 823 824 //! \brief USE_GLOBAL_GTT_SOURCE 825 //! \details 826 //! It is allowed for this bit to be set when executing this command from a 827 //! privileged (secure) batch buffer or ring buffer. This bit must be clear 828 //! when programmed from within a non-privileged batch buffer. This bit must 829 //! be 1 if the Per Process GTT Enable bit is clear. 830 enum USE_GLOBAL_GTT_SOURCE 831 { 832 USE_GLOBAL_GTT_SOURCE_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 833 USE_GLOBAL_GTT_SOURCE_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must be executing from a privileged (secure) batch buffer. 834 }; 835 836 enum MI_COMMAND_OPCODE 837 { 838 MI_COMMAND_OPCODE_MIMEMTOMEM = 46, //!< No additional details 839 }; 840 841 enum COMMAND_TYPE 842 { 843 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 844 }; 845 846 //! \name Initializations 847 848 //! \brief Explicit member initialization function 849 MI_COPY_MEM_MEM_CMD(); 850 851 static const size_t dwSize = 5; 852 static const size_t byteSize = 20; 853 }; 854 855 //! 856 //! \brief MI_STORE_DATA_IMM 857 //! \details 858 //! The MI_STORE_DATA_IMM command requests a write of the QWord or DWord 859 //! constant supplied in the packet to the specified Memory Address. This 860 //! command also supports writing to consecutive dword or qword memory 861 //! locations form the starting address. As the write targets a System 862 //! Memory Address, the write operation is coherent with the CPU cache 863 //! (i.e., the processor cache is snooped). 864 //! 865 //! This command can be used for general software synchronization through 866 //! variables in cacheable memory (i.e., where software does not need to 867 //! poll un-cached memory or device registers). 868 //! 869 //! This command simply initiates the write operation with command execution 870 //! proceeding normally. Although the write operation is guaranteed to 871 //! complete "eventually", there is no mechanism to synchronize command 872 //! execution with the completion (or even initiation) of these operations. 873 //! 874 //! This command should not be used within a non_privilege batch buffer to 875 //! access global virtual space, doing so will be treated as privilege 876 //! access violation. Refer "User Mode Privilege Command" in 877 //! MI_BATCH_BUFFER_START command section to know HW behavior on 878 //! encountering privilege access violation. 879 //! 880 struct MI_STORE_DATA_IMM_CMD 881 { 882 union 883 { 884 //!< DWORD 0 885 struct 886 { 887 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 9) ; //!< DWORD_LENGTH 888 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 20) ; //!< Reserved 889 uint32_t StoreQword : __CODEGEN_BITFIELD(21, 21) ; //!< STORE_QWORD 890 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< Use Global GTT 891 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 892 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 893 }; 894 uint32_t Value; 895 } DW0; 896 union 897 { 898 //!< DWORD 1..2 899 struct 900 { 901 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 902 uint64_t DestinationAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Destination Address 903 }; 904 uint32_t Value[2]; 905 } DW1_2; 906 union 907 { 908 //!< DWORD 3 909 struct 910 { 911 uint32_t DataDword0 ; //!< Data DWord 0 912 }; 913 uint32_t Value; 914 } DW3; 915 union 916 { 917 //!< DWORD 4 918 struct 919 { 920 uint32_t DataDword1 ; //!< Data DWord 1 921 }; 922 uint32_t Value; 923 } DW4; 924 925 //! \name Local enumerations 926 927 enum STORE_QWORD 928 { 929 STORE_QWORD_STOREDWORD = 0, //!< If set, this command generates dword writes to memory. Number of dwords generated depends upon the number of 'Data Dword' programmed in the command. If 'x' number of data dwords are programmed in the command it results in 'x' dword writes to memory. 930 STORE_QWORD_STOREQWORD = 1, //!< If set, this command generates Qword writes to memory, two 'Data Dword' are paired to form a Qword. Number of qwords generated depends upon the number of 'Data Dword' programmed in the command. If 'x' number of data dwords are programmed in the command it results in 'x/2' qword writes to memory. 931 }; 932 933 enum MI_COMMAND_OPCODE 934 { 935 MI_COMMAND_OPCODE_MISTOREDATAIMM = 32, //!< No additional details 936 }; 937 938 enum COMMAND_TYPE 939 { 940 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 941 }; 942 943 //! \name Initializations 944 945 //! \brief Explicit member initialization function 946 MI_STORE_DATA_IMM_CMD(); 947 948 static const size_t dwSize = 5; 949 static const size_t byteSize = 20; 950 }; 951 952 //! 953 //! \brief MI_SEMAPHORE_SIGNAL 954 //! \details 955 //! This command is used to signal the target engine stating the memory 956 //! semaphore update occurrence to one of its contexts with Target Context 957 //! ID. MI_SEMPHORE_SIGNAL and MI_SEMAPHORE_WAIT together replace the 958 //! MI_SEMAPHORE_MBOX command on BDW. MI_ATOMIC (non-posted) command will be 959 //! programmed prior to this command to update the semaphore data in memory. 960 //! 961 //! MI_SEMAPHORE_SIGNAL and MI_SEMAPHORE_WAIT command in signal mode must 962 //! not be enabled. However limited validation can be done for Semaphore 963 //! wait in signal mode with soft reset flows, FLR and idle power saving 964 //! features disabled. 965 //! 966 //! [VideoCS2] Semaphore signal to render command stream from the second 967 //! video command streamer must be replaced with an MI_LOAD_REGISTER_IMM 968 //! with the address of 0x343c with the data value the same as the Target 969 //! Context ID. 970 //! 971 //! [All Command Streamers]: When a semaphore signal is received by a target 972 //! command streamer while context switch is in progress due to semaphore 973 //! wait unsuccessful in signal mode, and the received semaphore signal is 974 //! for the context getting switched out, Command Streamer might not forward 975 //! the semaphore signal to GUC. As a result GUC might see a context with a 976 //! switch reason as Semaphore Wait, for which it may never receive any 977 //! semaphore signal; hence GUC might not schedule the same context forever. 978 //! Since this issue is only applicable when MI_SEMAPHORE_WAIT is used in 979 //! signal mode, SW has to WA this issue by doing one of the below: 980 //! 981 //! SW WA: 982 //! 983 //! 1. Scheduler on encountering a Context Waiting for semaphore signal to 984 //! occur for a long time can assume above scenario could have occurred and 985 //! do one of the below: 986 //! 987 //! a. Evaluate the semaphore wait condition based on the contexts PPHWSP 988 //! semaphore wait details and re-schedule it, if the semaphore wait 989 //! condition is satisfied. 990 //! b. Schedule the context to HW and let HW evaluate the condition and take 991 //! appropriate action. 992 //! 993 //! OR 994 //! 995 //! 996 //! 2. Scheduler not to use MI_SEMAPHORE_WAIT in signal mode. 997 //! 998 //! 999 //! Option 1 is preferred so that limited validation can be done for 1000 //! MI_SEMAPHORE_WAIT in signal mode on stepping's on which this issue is 1001 //! not fixed. 1002 //! 1003 //! Example describing the scenarios causing issue: 1004 //! RCS is executing Context-A. 1005 //! RCS has parsed MI_SEMAPHORE_WAIT in signal mode and has made memory 1006 //! request to fetch the semaphore data. 1007 //! BCS in the meantime update semaphore memory location for Context-A. 1008 //! BCS generates Semaphore Signal with Context ID as Context-A to RCS. 1009 //! RCS receives semaphore signal from BCS for Context-A. 1010 //! RCS receives the memory data and semaphore wait is un-successful (RCS 1011 //! must have sampled memory before BCS has updated the memory) resulting in 1012 //! context switch due to Wait on Semaphore. 1013 //! RCS ignores the semaphore signal received from BCS and also doesn't 1014 //! forward it to GUC. 1015 //! RCS switches out context-A with Wait on Semaphore as context switch 1016 //! reason. 1017 //! GUC process the context switch reason for Context-A, waits for semaphore 1018 //! signal for context-A to reschedule it which it will never receive as RCS 1019 //! has dropped it. 1020 //! 1021 //! [All Command Streamers]: When SW intends to use semaphore signaling 1022 //! between Command streamers, it must avoid lite restores in HW by 1023 //! programming "Force Restore" bit to ‘1’ in context descriptor during 1024 //! context submission, this is required to avoid known HW issue. 1025 //! 1026 struct MI_SEMAPHORE_SIGNAL_CMD 1027 { 1028 union 1029 { 1030 //!< DWORD 0 1031 struct 1032 { 1033 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1034 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 14) ; //!< Reserved 1035 uint32_t TargetEngineSelect : __CODEGEN_BITFIELD(15, 17) ; //!< TARGET_ENGINE_SELECT 1036 uint32_t Reserved18 : __CODEGEN_BITFIELD(18, 22) ; //!< Reserved 1037 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1038 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1039 }; 1040 uint32_t Value; 1041 } DW0; 1042 union 1043 { 1044 //!< DWORD 1 1045 struct 1046 { 1047 uint32_t TargetContextId ; //!< Target Context ID 1048 }; 1049 uint32_t Value; 1050 } DW1; 1051 1052 //! \name Local enumerations 1053 1054 //! \brief TARGET_ENGINE_SELECT 1055 //! \details 1056 //! This field selects the target engine to which SIGNAL will be send to. 1057 enum TARGET_ENGINE_SELECT 1058 { 1059 TARGET_ENGINE_SELECT_RCS = 0, //!< No additional details 1060 TARGET_ENGINE_SELECT_VCS0 = 1, //!< No additional details 1061 TARGET_ENGINE_SELECT_BCS = 2, //!< No additional details 1062 TARGET_ENGINE_SELECT_VECS = 3, //!< No additional details 1063 TARGET_ENGINE_SELECT_VCS1 = 4, //!< No additional details 1064 }; 1065 1066 enum MI_COMMAND_OPCODE 1067 { 1068 MI_COMMAND_OPCODE_MISEMAPHORESIGNAL = 27, //!< No additional details 1069 }; 1070 1071 enum COMMAND_TYPE 1072 { 1073 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1074 }; 1075 1076 //! \name Initializations 1077 1078 //! \brief Explicit member initialization function 1079 MI_SEMAPHORE_SIGNAL_CMD(); 1080 1081 static const size_t dwSize = 2; 1082 static const size_t byteSize = 8; 1083 }; 1084 1085 //! 1086 //! \brief MI_SEMAPHORE_WAIT 1087 //! \details 1088 //! This command supports memory based Semaphore WAIT. Memory based 1089 //! semaphores will be used for synchronization between the Producer and the 1090 //! Consumer contexts. Producer and Consumer Contexts could be running on 1091 //! different engines or on the same engine inside GT. Running on the same 1092 //! engine is only possible when execlists are enabled. Producer Context 1093 //! implements a Signal and Consumer context implements a Wait. 1094 //! Command Streamer on parsing this command fetches data from the Semaphore 1095 //! Address mentioned in this command and compares it with the inline 1096 //! Semaphore Data Dword. 1097 //! 1098 //! If comparison passes, the command streamer moves to the next command. 1099 //! 1100 //! When execlists are enabled, if comparison fails Command streamer 1101 //! switches out the context. Context switch can be inhibited by setting 1102 //! "Inhibit Synchronous Context Switch" in CTXT_SR_CTL register. 1103 //! 1104 //! In ring buffer mode of scheduling or Execlist with "Inhibit Synchronous 1105 //! context Switch", if comparison fails, Command Streamer evaluates the 1106 //! Compare Operation based on the Wait Mode until the compare operation is 1107 //! true or Wait is canceled by SW. 1108 //! 1109 //! Exec-List Scheduling: CS generates semaphore wait interrupt to the 1110 //! scheduler when MI_SEMAPHORE_WAIT command is un-successful and when 1111 //! "Inhibit Synchronous Context Switch" is set. Scheduler can use this 1112 //! interrupt to preempt the context waiting on semaphore wait. 1113 //! 1114 //! Ring Buffer Scheduling: CS generates semaphore wait interrupt to the 1115 //! scheduler when MI_SEMAPHORE_WAIT command is un-successful. This is for 1116 //! debug mode 1117 //! 1118 //! 1119 //! 1120 //! MI_SEMPHORE_SIGNAL and MI_SEMAPHORE_WAIT together replace the 1121 //! MI_SEMAPHORE_MBOX command on DevBDW. 1122 //! 1123 //! [All Command Streamers]:When a semaphore signal is received by a target 1124 //! command streamer while context switch is in progress due to semaphore 1125 //! wait unsuccessful in signal mode, and the received semaphore signal is 1126 //! for the context getting switched out, Command Streamer might not forward 1127 //! the semaphore signal to GUC. As a result GUC might see a context with a 1128 //! switch reason as Semaphore Wait, for which it may never receive any 1129 //! semaphore signal; hence GUC might not schedule the same context forever. 1130 //! Since this issue is only applicable when MI_SEMAPHORE_WAIT is used in 1131 //! signal mode, SW has to WA this issue by doing one of the below: SW Work 1132 //! Around: 1133 //! 1134 //! 1135 //! Scheduler on encountering a Context Waiting for semaphore signal to 1136 //! occur for a long time can assume above scenario could have occurred and 1137 //! do one of the below: 1138 //! 1139 //! <li type="a">Evaluate the semaphore wait condition based on the contexts 1140 //! PPHWSP semaphore wait details and re-schedule it, if the semaphore wait 1141 //! condition is satisfied. b. Schedule the context to HW and let HW 1142 //! evaluate the condition and take appropriate action. OR 1143 //! 1144 //! 1145 //! 2. Scheduler not to use MI_SEMAPHORE_WAIT in signal mode. 1146 //! 1147 //! 1148 //! Option 1 is preferred so that limited validation can be done for 1149 //! MI_SEMAPHORE_WAIT in signal mode on stepping's on which this issue is 1150 //! not fixed. Example describing the scenarios causing issue: RCS is 1151 //! executing Context-A. RCS has parsed MI_SEMAPHORE_WAIT in signal mode and 1152 //! has made memory request to fetch the semaphore data. BCS in the meantime 1153 //! update semaphore memory location for Context-A. BCS generates Semaphore 1154 //! Signal with Context ID as Context-A to RCS. RCS receives semaphore 1155 //! signal from BCS for Context-A. RCS receives the memory data and 1156 //! semaphore wait is un-successful (RCS must have sampled memory before BCS 1157 //! has updated the memory) resulting in context switch due to Wait on 1158 //! Semaphore. RCS ignores the semaphore signal received from BCS and also 1159 //! doesn't forward it to GUC. RCS switches out context-A with Wait on 1160 //! Semaphore as context switch reason. GUC process the context switch 1161 //! reason for Context-A, waits for semaphore signal for context-A to 1162 //! reschedule it which it will never receive as RCS has dropped it. 1163 //! 1164 //! [BlitterCS, VideoCS, VideoEnhancementCS, VideoCS2: Command Streamers 1165 //! Only]: Inhibit Synchronous Context Switch in CTXT_SR_CTL (Bit 3 of 1166 //! register 0x22244 for BCS, 0x12244 for VCS, 0x1A244 for VECS, 0x1C244 for 1167 //! VCS2) register must be set when in Ring mode scheduling. 1168 //! 1169 //! [BlitterCS, VideoCS, VideoEnhancementCS, VideoCS2: Command Streamers 1170 //! Only]: IDLE sequence disable in PSMI_CTRL (Bit 0 of register 0x22050 for 1171 //! BCS, 0x12050 for VCS, 0x1A050 for VECS, 0x1C050 for VCS2) register must 1172 //! be set when in Ring mode scheduling and prior to this command with 1173 //! signal mode in the field Wait Mode is enabled. The IDLE sequence must be 1174 //! re-enabled after the MI_SEMAPHORE_WAIT to allow the engine to go IDLE. 1175 //! 1176 //! [Ring Buffer Mode Of scheduling] [BlitterCS, VideoCS, 1177 //! VideoEnhancementCS, VideoCS2: Command Streamers Only]: HW loses Page 1178 //! Directory (PPGTT) information on becoming IDLE. SW must always program 1179 //! the PD information following MI_SEMAPHORE_WAIT command. This will ensure 1180 //! Page Directory information gets reprogrammed after exiting IDLE flow 1181 //! triggered on MI_SEMAPHORE_WAIT command. Alternatively SW can disable 1182 //! IDLE flows on MI_SEMAPHORE_WAIT by setting "Semaphore Wait Event IDLE 1183 //! Message Disable" bit in "BCS_ECOSKPD" register. 1184 //! 1185 struct MI_SEMAPHORE_WAIT_CMD 1186 { 1187 union 1188 { 1189 //!< DWORD 0 1190 struct 1191 { 1192 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1193 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 1194 uint32_t CompareOperation : __CODEGEN_BITFIELD(12, 14) ; //!< COMPARE_OPERATION 1195 uint32_t WaitMode : __CODEGEN_BITFIELD(15, 15) ; //!< WAIT_MODE 1196 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 21) ; //!< Reserved 1197 uint32_t MemoryType : __CODEGEN_BITFIELD(22, 22) ; //!< MEMORY_TYPE 1198 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1199 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1200 }; 1201 uint32_t Value; 1202 } DW0; 1203 union 1204 { 1205 //!< DWORD 1 1206 struct 1207 { 1208 uint32_t SemaphoreDataDword ; //!< Semaphore Data Dword 1209 }; 1210 uint32_t Value; 1211 } DW1; 1212 union 1213 { 1214 //!< DWORD 2..3 1215 struct 1216 { 1217 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1218 uint64_t SemaphoreAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Semaphore Address 1219 }; 1220 uint32_t Value[2]; 1221 } DW2_3; 1222 1223 //! \name Local enumerations 1224 1225 //! \brief COMPARE_OPERATION 1226 //! \details 1227 //! This field specifies the operation that will be executed to create the 1228 //! result that will either allow the context to continue or wait. 1229 enum COMPARE_OPERATION 1230 { 1231 COMPARE_OPERATION_SADGREATERTHANSDD = 0, //!< If Indirect fetched data is greater than inline data then continue. 1232 COMPARE_OPERATION_SADGREATERTHANOREQUALSDD = 1, //!< If Indirect fetched data is greater than or equal to inline data then continue. 1233 COMPARE_OPERATION_SADLESSTHANSDD = 2, //!< If Indirect fetched data is less than inline data then continue. 1234 COMPARE_OPERATION_SADLESSTHANOREQUALSDD = 3, //!< If Indirect fetched data is less than or equal to inline data then continue. 1235 COMPARE_OPERATION_SADEQUALSDD = 4, //!< If Indirect fetched data is equalto inline data then continue. 1236 COMPARE_OPERATION_SADNOTEQUALSDD = 5, //!< If Indirect fetched data is not equal to inline data then continue. 1237 }; 1238 1239 //! \brief WAIT_MODE 1240 //! \details 1241 //! This bit specifies the WAIT behavior when the semaphore comparison fails 1242 //! and before the context is switched out. 1243 enum WAIT_MODE 1244 { 1245 WAIT_MODE_SIGNALMODE = 0, //!< In this mode HW will reacquire the semaphore data from memory on receiving SIGNAL with the same Context ID. In ring buffer mode of scheduling Context ID associated with SIGNAL is ignored and always treated as a match. 1246 WAIT_MODE_POLLINGMODE = 1, //!< In this mode HW periodically reads the semaphore data from memory for comparison until it is context switched out. Periodicity will be mentioned in a SEMA_WAIT_POLL register. 1247 }; 1248 1249 //! \brief MEMORY_TYPE 1250 //! \details 1251 //! This bit will be ignored and treated as if clear when executing from a 1252 //! non-privileged batch buffer. It is allowed for this bit to be clear when 1253 //! executing this command from a privileged (secure) batch buffer. This bit 1254 //! <i>must</i> be 1 if the <b>Per Process GTT Enable</b> bit is clear. 1255 enum MEMORY_TYPE 1256 { 1257 MEMORY_TYPE_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 1258 MEMORY_TYPE_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must beexecuting from a privileged (secure) batch buffer. 1259 }; 1260 1261 enum MI_COMMAND_OPCODE 1262 { 1263 MI_COMMAND_OPCODE_MISEMAPHOREWAIT = 28, //!< No additional details 1264 }; 1265 1266 enum COMMAND_TYPE 1267 { 1268 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1269 }; 1270 1271 //! \name Initializations 1272 1273 //! \brief Explicit member initialization function 1274 MI_SEMAPHORE_WAIT_CMD(); 1275 1276 static const size_t dwSize = 4; 1277 static const size_t byteSize = 16; 1278 }; 1279 1280 //! 1281 //! \brief MI_CONDITIONAL_BATCH_BUFFER_END 1282 //! \details 1283 //! The MI_CONDITIONAL_BATCH_BUFFER_END command is used to conditionally 1284 //! terminate the execution of commands stored in a batch buffer initiated 1285 //! using a MI_BATCH_BUFFER_START command. Termination of second level batch 1286 //! buffer due to this command will also terminate the parent/first level 1287 //! batch buffer. 1288 //! 1289 //! This command is only valid with a 1st level batch buffer (bit 22 in 1290 //! MI_BATCH_BUFFER_START is set to 0). 1291 //! 1292 struct MI_CONDITIONAL_BATCH_BUFFER_END_CMD 1293 { 1294 union 1295 { 1296 //!< DWORD 0 1297 struct 1298 { 1299 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1300 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 20) ; //!< Reserved 1301 uint32_t CompareSemaphore : __CODEGEN_BITFIELD(21, 21) ; //!< COMPARE_SEMAPHORE 1302 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< USE_GLOBAL_GTT 1303 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1304 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1305 }; 1306 uint32_t Value; 1307 } DW0; 1308 union 1309 { 1310 //!< DWORD 1 1311 struct 1312 { 1313 uint32_t CompareDataDword ; //!< Compare Data Dword 1314 }; 1315 uint32_t Value; 1316 } DW1; 1317 union 1318 { 1319 //!< DWORD 2 1320 struct 1321 { 1322 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1323 uint32_t CompareAddress : __CODEGEN_BITFIELD( 3, 31) ; //!< Compare Address 1324 }; 1325 uint32_t Value; 1326 } DW2; 1327 union 1328 { 1329 //!< DWORD 3 1330 struct 1331 { 1332 uint32_t CompareAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Compare Address High 1333 uint32_t Reserved112 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1334 }; 1335 uint32_t Value; 1336 } DW3; 1337 1338 //! \name Local enumerations 1339 1340 //! \brief COMPARE_SEMAPHORE 1341 //! \details 1342 //! If set, the value from the Compare Data Dword is compared to the value 1343 //! from the Compare Address in memory. If the value at Compare Address is 1344 //! greater than the Compare Data Dword, execution of current command buffer 1345 //! should continue.If clear, no comparison takes place. 1346 enum COMPARE_SEMAPHORE 1347 { 1348 COMPARE_SEMAPHORE_DEFAULTVAUEDESC = 0, //!< No additional details 1349 }; 1350 1351 //! \brief USE_GLOBAL_GTT 1352 //! \details 1353 //! If set, this command will use the global GTT to translate the Compare 1354 //! Address and this command must be executing from a privileged (secure) 1355 //! batch buffer. If clear, the PPGTT will be used to translate the Compare 1356 //! Address. 1357 enum USE_GLOBAL_GTT 1358 { 1359 USE_GLOBAL_GTT_DEFAULTVAUEDESC = 0, //!< No additional details 1360 }; 1361 1362 enum MI_COMMAND_OPCODE 1363 { 1364 MI_COMMAND_OPCODE_MICONDITIONALBATCHBUFFEREND = 54, //!< No additional details 1365 }; 1366 1367 enum COMMAND_TYPE 1368 { 1369 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1370 }; 1371 1372 //! \name Initializations 1373 1374 //! \brief Explicit member initialization function 1375 MI_CONDITIONAL_BATCH_BUFFER_END_CMD(); 1376 1377 static const size_t dwSize = 4; 1378 static const size_t byteSize = 16; 1379 }; 1380 1381 //! 1382 //! \brief MI_ATOMIC 1383 //! \details 1384 //! MI_ATOMIC is used to carry atomic operation on data in graphics memory. 1385 //! Atomic operations are supported on data granularity of 4B, 8B and 16B. 1386 //! The atomic operation leads to a read-modify-write operation on the data 1387 //! in graphics memory with the option of returning value. The data in 1388 //! graphics memory is modified by doing arithmetic and logical operation 1389 //! with the inline/indirect data provided with the MI_ATOMIC command. 1390 //! Inline/Indirect provided in the command can be one or two operands based 1391 //! on the atomic operation. Ex: Atomic-Compare operation needs two operands 1392 //! while Atomic-Add operation needs single operand and Atomic-increment 1393 //! requires no operand. Refer "Atomics" sub-section under "L3 Cache and 1394 //! URB" section for detailed atomic operations supported. Atomic operations 1395 //! can be enabled to return value by setting "Return Data Control" field in 1396 //! the command, return data is stored to CS_GPR registers. 1397 //! CS_GPR4/5 registers are updated with memory Return Data based on the 1398 //! "Data Size". Each GPR register is qword in size and occupies two MMIO 1399 //! registers. 1400 //! Note: Any references to CS_GPR registers in the command should be 1401 //! understood as the CS_GPR registers belonging to the corresponding 1402 //! engines *CS_GPR registers. 1403 //! 1404 //! 1405 //! Indirect Source Operands: 1406 //! 1407 //! Operand1 is sourced from [CS_GPR1, CS_GPR0] 1408 //! 1409 //! Operand2 is sourced from [CS_GPR3, CS_GPR2] 1410 //! 1411 //! Read return Data is stored in [CS_GPR_5, CS_GPR4] 1412 //! 1413 //! When "Data Size" is QWORD or DWORD only CS_GPR4 (Qword) is updated with 1414 //! the qword data returned from memory. When the data size is OCTWORD 1415 //! CS_GPR4/5 are updated with the OCTWORD data returned from memory. 1416 //! CS_GPR4 is loaded with lower qword returned from memory and CS_GPR5 is 1417 //! loaded with upper qword returned from memory. 1418 //! 1419 //! When Inline Data mode is not set, Dwords 3..10 must not be included as 1420 //! part of the command. Dword Length field in the header must be programmed 1421 //! accordingly. 1422 //! When Inline Data Mode is set, Dwords3..10 must be included based on the 1423 //! Data Size field of the header. Both Operand-1 and Operand-2 dwords must 1424 //! be programmed based on the Data Size field. Operand-2 must be programmed 1425 //! to 0x0 if the atomic operation doesn't require it. Dword Length field in 1426 //! the header must be programmed accordingly. 1427 //! 1428 //! 1429 //! 1430 struct MI_ATOMIC_CMD 1431 { 1432 union 1433 { 1434 //!< DWORD 0 1435 struct 1436 { 1437 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1438 uint32_t AtomicOpcode : __CODEGEN_BITFIELD( 8, 15) ; //!< ATOMIC OPCODE 1439 uint32_t ReturnDataControl : __CODEGEN_BITFIELD(16, 16) ; //!< Return Data Control 1440 uint32_t CsStall : __CODEGEN_BITFIELD(17, 17) ; //!< CS STALL 1441 uint32_t InlineData : __CODEGEN_BITFIELD(18, 18) ; //!< Inline Data 1442 uint32_t DataSize : __CODEGEN_BITFIELD(19, 20) ; //!< DATA_SIZE 1443 uint32_t Reserved21 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 1444 uint32_t MemoryType : __CODEGEN_BITFIELD(22, 22) ; //!< MEMORY_TYPE 1445 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1446 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1447 }; 1448 uint32_t Value; 1449 } DW0; 1450 union 1451 { 1452 //!< DWORD 1 1453 struct 1454 { 1455 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1456 uint32_t MemoryAddress : __CODEGEN_BITFIELD( 2, 31) ; //!< Memory Address 1457 }; 1458 uint32_t Value; 1459 } DW1; 1460 union 1461 { 1462 //!< DWORD 2 1463 struct 1464 { 1465 uint32_t MemoryAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Memory Address High 1466 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1467 }; 1468 uint32_t Value; 1469 } DW2; 1470 union 1471 { 1472 //!< DWORD 3 1473 struct 1474 { 1475 uint32_t Operand1DataDword0 ; //!< Operand1 Data Dword 0 1476 }; 1477 uint32_t Value; 1478 } DW3; 1479 union 1480 { 1481 //!< DWORD 4 1482 struct 1483 { 1484 uint32_t Operand2DataDword0 ; //!< Operand2 Data Dword 0 1485 }; 1486 uint32_t Value; 1487 } DW4; 1488 union 1489 { 1490 //!< DWORD 5 1491 struct 1492 { 1493 uint32_t Operand1DataDword1 ; //!< Operand1 Data Dword 1 1494 }; 1495 uint32_t Value; 1496 } DW5; 1497 union 1498 { 1499 //!< DWORD 6 1500 struct 1501 { 1502 uint32_t Operand2DataDword1 ; //!< Operand2 Data Dword 1 1503 }; 1504 uint32_t Value; 1505 } DW6; 1506 union 1507 { 1508 //!< DWORD 7 1509 struct 1510 { 1511 uint32_t Operand1DataDword2 ; //!< Operand1 Data Dword 2 1512 }; 1513 uint32_t Value; 1514 } DW7; 1515 union 1516 { 1517 //!< DWORD 8 1518 struct 1519 { 1520 uint32_t Operand2DataDword2 ; //!< Operand2 Data Dword 2 1521 }; 1522 uint32_t Value; 1523 } DW8; 1524 union 1525 { 1526 //!< DWORD 9 1527 struct 1528 { 1529 uint32_t Operand1DataDword3 ; //!< Operand1 Data Dword 3 1530 }; 1531 uint32_t Value; 1532 } DW9; 1533 union 1534 { 1535 //!< DWORD 10 1536 struct 1537 { 1538 uint32_t Operand2DataDword3 ; //!< Operand2 Data Dword 3 1539 }; 1540 uint32_t Value; 1541 } DW10; 1542 1543 //! \name Local enumerations 1544 1545 //! \brief DATA_SIZE 1546 //! \details 1547 //! This field indicates the size of the operand in dword/qword/octword on 1548 //! which atomic operation will be performed. Data size must match with the 1549 //! Atomic Opcode. Operation Data size could be 4B, 8B or 16B 1550 enum DATA_SIZE 1551 { 1552 DATA_SIZE_DWORD = 0, //!< Operand size used by Atomic Operation is DWORD. 1553 DATA_SIZE_QWORD = 1, //!< Operand Size used by Atomic Operation is QWORD. 1554 DATA_SIZE_OCTWORD = 2, //!< Operand Size used by Atomic Operation is OCTWORD. 1555 }; 1556 1557 //! \brief MEMORY_TYPE 1558 //! \details 1559 //! This bit will be ignored and treated as if clear when executing from a 1560 //! non-privileged batch buffer. It is allowed for this bit to be clear when 1561 //! executing this command from a privileged (secure) batch buffer. This bit 1562 //! must be 1 if the <b>Per Process GTT Enable</b> bit is clear. 1563 enum MEMORY_TYPE 1564 { 1565 MEMORY_TYPE_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 1566 MEMORY_TYPE_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must be executing from a privileged (secure) batch buffer. 1567 }; 1568 1569 enum MI_COMMAND_OPCODE 1570 { 1571 MI_COMMAND_OPCODE_MIATOMIC = 47, //!< No additional details 1572 }; 1573 1574 enum COMMAND_TYPE 1575 { 1576 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1577 }; 1578 1579 //! \name Initializations 1580 1581 //! \brief Explicit member initialization function 1582 MI_ATOMIC_CMD(); 1583 1584 static const size_t dwSize = 11; 1585 static const size_t byteSize = 44; 1586 }; 1587 1588 //! 1589 //! \brief MI_MATH 1590 //! \details 1591 //! The MI_MATH command allows software to send instructions to the ALU in 1592 //! the Command Streamer. This command is the means by which the ALU is 1593 //! accessed. ALU instructions form the data payload of the MI_MATH command. 1594 //! An ALU instruction takes one DWord in size. The MI_MATH DWord Length is 1595 //! programmed based on the number of ALU instructions included, limited 1596 //! only by the max DWord Length supported. When the command streamer parses 1597 //! an MI_MATH command, it sends the included ALU instructions to the ALU. 1598 //! The ALU processes any instruction in a single clock. See the ALU section 1599 //! for more details. 1600 //! 1601 struct MI_MATH_CMD 1602 { 1603 union 1604 { 1605 //!< DWORD 0 1606 struct 1607 { 1608 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1609 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 22) ; //!< Reserved 1610 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1611 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1612 }; 1613 uint32_t Value; 1614 } DW0; 1615 1616 //! \name Local enumerations 1617 1618 enum MI_COMMAND_OPCODE 1619 { 1620 MI_COMMAND_OPCODE_MIMATH = 26, //!< No additional details 1621 }; 1622 1623 enum COMMAND_TYPE 1624 { 1625 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1626 }; 1627 1628 //! \name Initializations 1629 1630 //! \brief Explicit member initialization function 1631 MI_MATH_CMD(); 1632 1633 static const size_t dwSize = 1; 1634 static const size_t byteSize = 4; 1635 }; 1636 1637 //! 1638 //! \brief MI_FLUSH_DW 1639 //! \details 1640 //! The MI_FLUSH_DW command is used to perform an internal "flush" 1641 //! operation. The parser pauses on an internal flush until all drawing 1642 //! engines have completed any pending operations. In addition, this command 1643 //! can also be used to:Flush any dirty data to memory. Invalidate the TLB 1644 //! cache inside the hardware Usage note: After this command is completed 1645 //! with a Store DWord enabled, CPU access to graphics memory will be 1646 //! coherent (assuming the Render Cache flush is not inhibited). 1647 //! 1648 struct MI_FLUSH_DW_CMD 1649 { 1650 union 1651 { 1652 //!< DWORD 0 1653 struct 1654 { 1655 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 5) ; //!< DWORD_LENGTH 1656 uint32_t Reserved6 : __CODEGEN_BITFIELD( 6, 6) ; //!< Content Protection App ID 1657 uint32_t VideoPipelineCacheInvalidate : __CODEGEN_BITFIELD( 7, 7) ; //!< Video Pipeline Cache invalidate 1658 uint32_t NotifyEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Notify Enable 1659 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 13) ; //!< Reserved 1660 uint32_t PostSyncOperation : __CODEGEN_BITFIELD(14, 15) ; //!< POST_SYNC_OPERATION 1661 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 1662 uint32_t TlbInvalidate : __CODEGEN_BITFIELD(18, 18) ; //!< TLB Invalidate 1663 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 20) ; //!< Reserved 1664 uint32_t StoreDataIndex : __CODEGEN_BITFIELD(21, 21) ; //!< Store Data Index 1665 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 22) ; //!< Reserved 1666 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1667 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1668 }; 1669 uint32_t Value; 1670 } DW0; 1671 union 1672 { 1673 //!< DWORD 1..2 1674 struct 1675 { 1676 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1677 uint64_t DestinationAddressType : __CODEGEN_BITFIELD( 2, 2) ; //!< DESTINATION_ADDRESS_TYPE 1678 uint64_t Address : __CODEGEN_BITFIELD( 3, 47) ; //!< Address 1679 uint64_t Reserved80 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 1680 }; 1681 uint32_t Value[2]; 1682 } DW1_2; 1683 union 1684 { 1685 //!< DWORD 3..4 1686 struct 1687 { 1688 uint64_t ImmediateData ; //!< Immediate Data 1689 }; 1690 uint32_t Value[2]; 1691 } DW3_4; 1692 1693 //! \name Local enumerations 1694 1695 //! \brief POST_SYNC_OPERATION 1696 //! \details 1697 //! BitFieldDesc 1698 enum POST_SYNC_OPERATION 1699 { 1700 POST_SYNC_OPERATION_NOWRITE = 0, //!< No write occurs as a result of this instruction. This can be used to implement a "trap" operation, etc. 1701 POST_SYNC_OPERATION_WRITEIMMEDIATEDATA = 1, //!< HW implicitly detects the Data size to be Qword or Dword to be written to memory based on the command dword length programmed . When Dword Length indicates Qword, Writes the QWord containing Immediate Data Low, High DWs to the Destination Address . When Dword Length indicates Dword, Writes the DWord containing Immediate Data Low to the Destination Address 1702 POST_SYNC_OPERATION_UNNAMED3 = 3, //!< Write the TIMESTAMP register to the Destination Address. The upper 28 bits of the TIMESTAMP register are tied to '0'. 1703 }; 1704 1705 enum MI_COMMAND_OPCODE 1706 { 1707 MI_COMMAND_OPCODE_MIFLUSHDW = 38, //!< No additional details 1708 }; 1709 1710 enum COMMAND_TYPE 1711 { 1712 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1713 }; 1714 1715 //! \brief DESTINATION_ADDRESS_TYPE 1716 //! \details 1717 //! Defines address space of Destination Address 1718 enum DESTINATION_ADDRESS_TYPE 1719 { 1720 DESTINATION_ADDRESS_TYPE_PPGTT = 0, //!< Use PPGTT address space for DW write 1721 DESTINATION_ADDRESS_TYPE_GGTT = 1, //!< Use GGTT address space for DW write 1722 }; 1723 1724 //! \name Initializations 1725 1726 //! \brief Explicit member initialization function 1727 MI_FLUSH_DW_CMD(); 1728 1729 static const size_t dwSize = 5; 1730 static const size_t byteSize = 20; 1731 }; 1732 1733 //! 1734 //! \brief PIPE_CONTROL 1735 //! \details 1736 //! The PIPE_CONTROL command is used to effect the synchronization described 1737 //! above. 1738 //! 1739 struct PIPE_CONTROL_CMD 1740 { 1741 union 1742 { 1743 //!< DWORD 0 1744 struct 1745 { 1746 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1747 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1748 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1749 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1750 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1751 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1752 }; 1753 uint32_t Value; 1754 } DW0; 1755 union 1756 { 1757 //!< DWORD 1 1758 struct 1759 { 1760 uint32_t DepthCacheFlushEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DEPTH_CACHE_FLUSH_ENABLE 1761 uint32_t StallAtPixelScoreboard : __CODEGEN_BITFIELD( 1, 1) ; //!< STALL_AT_PIXEL_SCOREBOARD 1762 uint32_t StateCacheInvalidationEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< State Cache Invalidation Enable 1763 uint32_t ConstantCacheInvalidationEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< Constant Cache Invalidation Enable 1764 uint32_t VfCacheInvalidationEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< VF Cache Invalidation Enable 1765 uint32_t DcFlushEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< DC Flush Enable 1766 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 6) ; //!< Reserved 1767 uint32_t PipeControlFlushEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Pipe Control Flush Enable 1768 uint32_t NotifyEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Notify Enable 1769 uint32_t IndirectStatePointersDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Indirect State Pointers Disable 1770 uint32_t TextureCacheInvalidationEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Texture Cache Invalidation Enable 1771 uint32_t InstructionCacheInvalidateEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Instruction Cache Invalidate Enable 1772 uint32_t RenderTargetCacheFlushEnable : __CODEGEN_BITFIELD(12, 12) ; //!< RENDER_TARGET_CACHE_FLUSH_ENABLE 1773 uint32_t DepthStallEnable : __CODEGEN_BITFIELD(13, 13) ; //!< DEPTH_STALL_ENABLE 1774 uint32_t PostSyncOperation : __CODEGEN_BITFIELD(14, 15) ; //!< POST_SYNC_OPERATION 1775 uint32_t GenericMediaStateClear : __CODEGEN_BITFIELD(16, 16) ; //!< Generic Media State Clear 1776 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 17) ; //!< Reserved 1777 uint32_t TlbInvalidate : __CODEGEN_BITFIELD(18, 18) ; //!< TLB Invalidate 1778 uint32_t GlobalSnapshotCountReset : __CODEGEN_BITFIELD(19, 19) ; //!< GLOBAL_SNAPSHOT_COUNT_RESET 1779 uint32_t CommandStreamerStallEnable : __CODEGEN_BITFIELD(20, 20) ; //!< Command Streamer Stall Enable 1780 uint32_t StoreDataIndex : __CODEGEN_BITFIELD(21, 21) ; //!< Store Data Index 1781 uint32_t Reserved54 : __CODEGEN_BITFIELD(22, 22) ; //!< Reserved 1782 uint32_t LriPostSyncOperation : __CODEGEN_BITFIELD(23, 23) ; //!< LRI_POST_SYNC_OPERATION 1783 uint32_t DestinationAddressType : __CODEGEN_BITFIELD(24, 24) ; //!< DESTINATION_ADDRESS_TYPE 1784 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 1785 }; 1786 uint32_t Value; 1787 } DW1; 1788 union 1789 { 1790 //!< DWORD 2 1791 struct 1792 { 1793 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1794 uint32_t Address : __CODEGEN_BITFIELD( 2, 31) ; //!< Address 1795 }; 1796 uint32_t Value; 1797 } DW2; 1798 union 1799 { 1800 //!< DWORD 3 1801 struct 1802 { 1803 uint32_t AddressHigh ; //!< Address High 1804 }; 1805 uint32_t Value; 1806 } DW3; 1807 union 1808 { 1809 //!< DWORD 4..5 1810 struct 1811 { 1812 uint64_t ImmediateData ; //!< Immediate Data 1813 }; 1814 uint32_t Value[2]; 1815 } DW4_5; 1816 1817 //! \name Local enumerations 1818 1819 enum _3D_COMMAND_SUB_OPCODE 1820 { 1821 _3D_COMMAND_SUB_OPCODE_PIPECONTROL = 0, //!< No additional details 1822 }; 1823 1824 enum _3D_COMMAND_OPCODE 1825 { 1826 _3D_COMMAND_OPCODE_PIPECONTROL = 2, //!< No additional details 1827 }; 1828 1829 enum COMMAND_SUBTYPE 1830 { 1831 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1832 }; 1833 1834 enum COMMAND_TYPE 1835 { 1836 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1837 }; 1838 1839 //! \brief DEPTH_CACHE_FLUSH_ENABLE 1840 //! \details 1841 //! Setting this bit enables flushing (i.e. writing back the dirty lines to 1842 //! memory and invalidating the tags) of depth related caches. This bit 1843 //! applies to HiZ cache, Stencil cache and depth cache. 1844 enum DEPTH_CACHE_FLUSH_ENABLE 1845 { 1846 DEPTH_CACHE_FLUSH_ENABLE_FLUSHDISABLED = 0, //!< Depth relates caches (HiZ, Stencil and Depth) are NOT flushed. 1847 DEPTH_CACHE_FLUSH_ENABLE_FLUSHENABLED = 1, //!< Depth relates caches (HiZ, Stencil and Depth) are flushed. 1848 }; 1849 1850 //! \brief STALL_AT_PIXEL_SCOREBOARD 1851 //! \details 1852 //! Defines the behavior of PIPE_CONTROL command at the pixel scoreboard. 1853 enum STALL_AT_PIXEL_SCOREBOARD 1854 { 1855 STALL_AT_PIXEL_SCOREBOARD_DISABLE = 0, //!< Stall at the pixel scoreboard is disabled. 1856 STALL_AT_PIXEL_SCOREBOARD_ENABLE = 1, //!< Stall at the pixel scoreboard is enabled. 1857 }; 1858 1859 //! \brief RENDER_TARGET_CACHE_FLUSH_ENABLE 1860 //! \details 1861 //! <p>Setting this bit will force Render Cache to be flushed to memory 1862 //! prior to this synchronization point completing. This bit must be set for 1863 //! all write fence sync operations to assure that results from operations 1864 //! initiated prior to this command are visible in memory once software 1865 //! observes this synchronization.</p> 1866 enum RENDER_TARGET_CACHE_FLUSH_ENABLE 1867 { 1868 RENDER_TARGET_CACHE_FLUSH_ENABLE_DISABLEFLUSH = 0, //!< Render Target Cache is NOT flushed. 1869 RENDER_TARGET_CACHE_FLUSH_ENABLE_ENABLEFLUSH = 1, //!< Render Target Cache is flushed. 1870 }; 1871 1872 //! \brief DEPTH_STALL_ENABLE 1873 //! \details 1874 //! <p>This bit must be set when obtaining a "visible pixel" count to 1875 //! preclude the possible inclusion in the PS_DEPTH_COUNT value written to 1876 //! memory of some fraction of pixels from objects initiated after the 1877 //! PIPE_CONTROL command.</p> 1878 enum DEPTH_STALL_ENABLE 1879 { 1880 DEPTH_STALL_ENABLE_DISABLE = 0, //!< 3D pipeline will not stall subsequent primitives at the Depth Test stage. 1881 DEPTH_STALL_ENABLE_ENABLE = 1, //!< 3D pipeline will stall any subsequent primitives at the Depth Test stage until the Sync and Post-Sync operations complete. 1882 }; 1883 1884 //! \brief POST_SYNC_OPERATION 1885 //! \details 1886 //! This field specifies an optional action to be taken upon completion of 1887 //! the synchronization operation. 1888 enum POST_SYNC_OPERATION 1889 { 1890 POST_SYNC_OPERATION_NOWRITE = 0, //!< No write occurs as a result of this instruction. This can be used to implement a "trap" operation, etc. 1891 POST_SYNC_OPERATION_WRITEIMMEDIATEDATA = 1, //!< Write the QWord containing Immediate Data Low, High DWs to the Destination Address 1892 POST_SYNC_OPERATION_WRITEPSDEPTHCOUNT = 2, //!< Write the 64-bit PS_DEPTH_COUNT register to the Destination Address 1893 POST_SYNC_OPERATION_WRITETIMESTAMP = 3, //!< Write the 64-bit TIMESTAMP register(i.e. "Reported Timestamp Count" 0x2358 for render pipe) to the Destination Address. 1894 }; 1895 1896 //! \brief GLOBAL_SNAPSHOT_COUNT_RESET 1897 //! \details 1898 //! <p>This debug mode bit must not be exercised on any product.</p> 1899 enum GLOBAL_SNAPSHOT_COUNT_RESET 1900 { 1901 GLOBAL_SNAPSHOT_COUNT_RESET_DONTRESET = 0, //!< Do not reset the snapshot counts or Statistics Counters. 1902 GLOBAL_SNAPSHOT_COUNT_RESET_RESET = 1, //!< Reset the snapshot count in Gen4 for all the units and reset the Statistics Counters except as noted above. 1903 }; 1904 1905 //! \brief LRI_POST_SYNC_OPERATION 1906 //! \details 1907 //! This bit caues a post sync operation with an LRI (Load Register 1908 //! Immediate) operation. If this bit is set then the Post-Sync Operation 1909 //! field must be cleared. 1910 enum LRI_POST_SYNC_OPERATION 1911 { 1912 LRI_POST_SYNC_OPERATION_NOLRIOPERATION = 0, //!< No LRI operation occurs as a result of this instruction. The Post-Sync Operation field is valid and may be used to specify an operation. 1913 LRI_POST_SYNC_OPERATION_MMIOWRITEIMMEDIATEDATA = 1, //!< Write the DWord contained in Immediate Data Low (DW3) to the MMIO offset specifed in the Address field. 1914 }; 1915 1916 //! \brief DESTINATION_ADDRESS_TYPE 1917 //! \details 1918 //! Defines address space of Destination Address 1919 enum DESTINATION_ADDRESS_TYPE 1920 { 1921 DESTINATION_ADDRESS_TYPE_PPGTT = 0, //!< Use PPGTT address space for DW write 1922 DESTINATION_ADDRESS_TYPE_GGTT = 1, //!< Use GGTT address space for DW write 1923 }; 1924 1925 //! \name Initializations 1926 1927 //! \brief Explicit member initialization function 1928 PIPE_CONTROL_CMD(); 1929 1930 static const size_t dwSize = 6; 1931 static const size_t byteSize = 24; 1932 }; 1933 1934 //! 1935 //! \brief MFX_WAIT 1936 //! \details 1937 //! This command can be considered the same as an MI_NOOP except that the 1938 //! command parser will not parse the next command until the following 1939 //! happens AVC or VC1 BSD mode: The command will stall the parser until 1940 //! completion of the BSD object 1941 //! IT, encoder, and MPEG2 BSD mode: The command will stall the parser 1942 //! until the object package is sent down the pipelineThis command should be 1943 //! used to ensure the preemption enable window occurs during the time the 1944 //! object command is being executed down the pipeline. 1945 //! 1946 //! 1947 struct MFX_WAIT_CMD 1948 { 1949 union 1950 { 1951 //!< DWORD 0 1952 struct 1953 { 1954 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 5) ; //!< DWORD_LENGTH 1955 uint32_t Reserved6 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1956 uint32_t MfxSyncControlFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< MFX Sync Control Flag 1957 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 1958 uint32_t SubOpcode : __CODEGEN_BITFIELD(16, 26) ; //!< SUB_OPCODE 1959 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1960 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1961 }; 1962 uint32_t Value; 1963 } DW0; 1964 1965 //! \name Local enumerations 1966 1967 enum SUB_OPCODE 1968 { 1969 SUB_OPCODE_MFXWAIT = 0, //!< No additional details 1970 }; 1971 1972 enum COMMAND_SUBTYPE 1973 { 1974 COMMAND_SUBTYPE_MFXSINGLEDW = 1, //!< No additional details 1975 }; 1976 1977 enum COMMAND_TYPE 1978 { 1979 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1980 }; 1981 1982 //! \name Initializations 1983 1984 //! \brief Explicit member initialization function 1985 MFX_WAIT_CMD(); 1986 1987 static const size_t dwSize = 1; 1988 static const size_t byteSize = 4; 1989 }; 1990 1991 //! 1992 //! \brief MEDIA_STATE_FLUSH 1993 //! \details 1994 //! This command updates the Message Gateway state. In particular, it 1995 //! updates the state for a selected Interface Descriptor. 1996 //! 1997 //! This command can be considered same as a MI_Flush except that only media 1998 //! parser will get flushed instead of the entire 3D/media render pipeline. 1999 //! The command should be programmed prior to new Media state, curbe and/or 2000 //! interface descriptor commands when switching to a new context or 2001 //! programming new state for the same context. With this command, pipelined 2002 //! state change is allowed for the media pipe. 2003 //! 2004 //! Be cautious when using this command when child_present flag in the media 2005 //! state is enabled. This is because that CURBE state as well as Interface 2006 //! Descriptor state are shared between root threads and child threads. 2007 //! Changing these states while child threads are generated on the fly may 2008 //! cause unexpected behavior. Combining with MI_ARB_ON/OFF command, it is 2009 //! possible to support interruptability with the following command sequence 2010 //! where interrupt may be allowed only when MI_ARB_ON_OFF is ON: 2011 //! 2012 //! <pre>MEDIA_STATE_FLUSH 2013 //! VFE_STATE VFE will hold CS if watermark isn't met 2014 //! MI_ARB_OFF There must be at least one VFE command before this one 2015 //! MEDIA_OBJECT ... MI_ARB_ON</pre> 2016 //! 2017 struct MEDIA_STATE_FLUSH_CMD 2018 { 2019 union 2020 { 2021 //!< DWORD 0 2022 struct 2023 { 2024 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 2025 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 2026 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 2027 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2028 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2029 }; 2030 uint32_t Value; 2031 } DW0; 2032 union 2033 { 2034 //!< DWORD 1 2035 struct 2036 { 2037 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 2038 uint32_t WatermarkRequired : __CODEGEN_BITFIELD( 6, 6) ; //!< Watermark Required 2039 uint32_t FlushToGo : __CODEGEN_BITFIELD( 7, 7) ; //!< Flush to GO 2040 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 2041 }; 2042 uint32_t Value; 2043 } DW1; 2044 2045 //! \name Local enumerations 2046 2047 enum SUBOPCODE 2048 { 2049 SUBOPCODE_MEDIASTATEFLUSHSUBOP = 4, //!< No additional details 2050 }; 2051 2052 enum MEDIA_COMMAND_OPCODE 2053 { 2054 MEDIA_COMMAND_OPCODE_MEDIASTATEFLUSH = 0, //!< No additional details 2055 }; 2056 2057 enum PIPELINE 2058 { 2059 PIPELINE_MEDIA = 2, //!< No additional details 2060 }; 2061 2062 enum COMMAND_TYPE 2063 { 2064 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 2065 }; 2066 2067 //! \name Initializations 2068 2069 //! \brief Explicit member initialization function 2070 MEDIA_STATE_FLUSH_CMD(); 2071 2072 static const size_t dwSize = 2; 2073 static const size_t byteSize = 8; 2074 }; 2075 2076 }; 2077 2078 #pragma pack() 2079 2080 #endif // __MHW_MI_HWCMD_G8_X_H__