1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi_hwcmd_g11_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g11_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_MI_HWCMD_G11_X_H__ 29 #define __MHW_MI_HWCMD_G11_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_mi_g11_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MI_BATCH_BUFFER_END 50 //! \details 51 //! The MI_BATCH_BUFFER_END command is used to terminate the execution of 52 //! commands stored in a batch buffer initiated using a 53 //! MI_BATCH_BUFFER_START command. 54 //! 55 struct MI_BATCH_BUFFER_END_CMD 56 { 57 union 58 { 59 //!< DWORD 0 60 struct 61 { 62 uint32_t EndContext : __CODEGEN_BITFIELD( 0, 0) ; //!< End Context 63 uint32_t Reserved1 : __CODEGEN_BITFIELD( 1, 22) ; //!< Reserved 64 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 65 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 66 }; 67 uint32_t Value; 68 } DW0; 69 70 //! \name Local enumerations 71 72 enum MI_COMMAND_OPCODE 73 { 74 MI_COMMAND_OPCODE_MIBATCHBUFFEREND = 10, //!< No additional details 75 }; 76 77 enum COMMAND_TYPE 78 { 79 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 80 }; 81 82 //! \name Initializations 83 84 //! \brief Explicit member initialization function 85 MI_BATCH_BUFFER_END_CMD(); 86 87 static const size_t dwSize = 1; 88 static const size_t byteSize = 4; 89 }; 90 91 //! 92 //! \brief MI_NOOP 93 //! \details 94 //! The MI_NOOP command basically performs a "no operation" in the command 95 //! stream and is typically used to pad the command stream (e.g., in order 96 //! to pad out a batch buffer to a QWord boundary). However, there is one 97 //! minor (optional) function this command can perform - a 22-bit value can 98 //! be loaded into the MI NOPID register. This provides a general-purpose 99 //! command stream tagging ("breadcrumb") mechanism (e.g., to provide 100 //! sequencing information for a subsequent breakpoint interrupt). 101 //! 102 struct MI_NOOP_CMD 103 { 104 union 105 { 106 //!< DWORD 0 107 struct 108 { 109 uint32_t IdentificationNumber : __CODEGEN_BITFIELD( 0, 21) ; //!< Identification Number 110 uint32_t IdentificationNumberRegisterWriteEnable : __CODEGEN_BITFIELD(22, 22) ; //!< IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE 111 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 112 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 113 }; 114 uint32_t Value; 115 } DW0; 116 117 //! \name Local enumerations 118 119 //! \brief IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE 120 //! \details 121 //! This field enables the value in the Identification Number field to be 122 //! written into the MI NOPID register. If disabled, that register is 123 //! unmodified - making this command an effective "no operation" function. 124 enum IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE 125 { 126 IDENTIFICATION_NUMBER_REGISTER_WRITE_ENABLE_WRITETHENOPIDREGISTER = 1, //!< No additional details 127 }; 128 129 enum MI_COMMAND_OPCODE 130 { 131 MI_COMMAND_OPCODE_MINOOP = 0, //!< No additional details 132 }; 133 134 enum COMMAND_TYPE 135 { 136 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 137 }; 138 139 //! \name Initializations 140 141 //! \brief Explicit member initialization function 142 MI_NOOP_CMD(); 143 144 static const size_t dwSize = 1; 145 static const size_t byteSize = 4; 146 }; 147 148 //! 149 //! \brief MI_ARB_CHECK 150 //! \details 151 //! The command allows software to add preemption points in the ring buffer. 152 //! The command streamer will preempt in the case arbitration is enabled, 153 //! there is a pending execution list and this command is currently being 154 //! parsed. 155 //! 156 //! This instruction cannot be placed in a batch buffer. 157 //! 158 struct MI_ARB_CHECK_CMD 159 { 160 union 161 { 162 //!< DWORD 0 163 struct 164 { 165 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 22) ; //!< Reserved 166 uint32_t MiInstructionOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_INSTRUCTION_OPCODE 167 uint32_t MiInstructionType : __CODEGEN_BITFIELD(29, 31) ; //!< MI_INSTRUCTION_TYPE 168 }; 169 uint32_t Value; 170 } DW0; 171 172 //! \name Local enumerations 173 174 enum MI_INSTRUCTION_OPCODE 175 { 176 MI_INSTRUCTION_OPCODE_MIARBCHECK = 5, //!< No additional details 177 }; 178 179 enum MI_INSTRUCTION_TYPE 180 { 181 MI_INSTRUCTION_TYPE_MIINSTRUCTION = 0, //!< No additional details 182 }; 183 184 //! \name Initializations 185 186 //! \brief Explicit member initialization function 187 MI_ARB_CHECK_CMD(); 188 189 static const size_t dwSize = 1; 190 static const size_t byteSize = 4; 191 }; 192 193 //! 194 //! \brief MI_LOAD_REGISTER_IMM 195 //! \details 196 //! The MI_LOAD_REGISTER_IMM command requests a write of up to a DWord 197 //! constant supplied in the command to the specified Register Offset (i.e., 198 //! offset into Memory-Mapped Register Range). 199 //! Any offset that is to a destination outside of the GT core will allow 200 //! the parser to continue once the cycle is at the GT boundry and not 201 //! destination. Any other address will ensure the destination is updated 202 //! prior to parsing the next command 203 //! 204 //! When executed from a non-privileged batch buffer, MMIO writes are only 205 //! allowed to the registers listed in User Mode Non-Privileged Registers 206 //! for the corresponding engine, any writes targeting the register not 207 //! listed in the User Mode Non-Privileged Register will convert this 208 //! command to a NOOP. 209 //! 210 //! The following addresses should NOT be used for LRIs: 211 //! 212 //! 0x8800 - 0x88FF 213 //! 214 //! >= 0xC0000 215 //! 216 //! 217 //! 218 //! Limited LRI cycles to the Display Engine (0x40000-0xBFFFF) are allowed, 219 //! but must be spaced to allow only one pending at a time. This can be done 220 //! by issuing an SRM to the same address immediately after each LRI. 221 //! 222 struct MI_LOAD_REGISTER_IMM_CMD 223 { 224 union 225 { 226 //!< DWORD 0 227 struct 228 { 229 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 230 uint32_t ByteWriteDisables : __CODEGEN_BITFIELD( 8, 11) ; //!< Byte Write Disables 231 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 18) ; //!< Reserved 232 uint32_t AddCsMmioStartOffset : __CODEGEN_BITFIELD(19, 19) ; //!< ADD_CS_MMIO_START_OFFSET 233 uint32_t Reserved20 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 234 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 235 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 236 }; 237 uint32_t Value; 238 } DW0; 239 union 240 { 241 //!< DWORD 1 242 struct 243 { 244 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 245 uint32_t RegisterOffset : __CODEGEN_BITFIELD( 2, 22) ; //!< Register Offset 246 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 247 }; 248 uint32_t Value; 249 } DW1; 250 union 251 { 252 //!< DWORD 2 253 struct 254 { 255 uint32_t DataDword ; //!< Data DWord 256 }; 257 uint32_t Value; 258 } DW2; 259 260 //! \name Local enumerations 261 262 //! \brief ADD_CS_MMIO_START_OFFSET 263 //! \details 264 //! <p>This bit controls the functionality of the "Register Address" field 265 //! in the command.</p> 266 enum ADD_CS_MMIO_START_OFFSET 267 { 268 ADD_CS_MMIO_START_OFFSET_UNNAMED0 = 0, //!< "Register Address" field in the command is absolute and not an offset from the executing command streamer MMIO start offset.. 269 ADD_CS_MMIO_START_OFFSET_UNNAMED1 = 1, //!< "Register Address" field in the command is treated as an offset from the executing Command Streamer’s MMIO start offset. Bits [22:2] of the "Register Address" are considered as dword offset to be added to the MMIO start offset of the corresponding command streamer. However, during context restore bits [11:2] of the "Register Address" are considered as dword offset to be added to the MMIO start offset of the corresponding command streamer. Command executed from Ring Buffer or Batch BufferExample: MI_LOAD_REGISTER_IMMEDIATE, ADD_CS_MMIO_START_OFFSET: true, Data:0xABCD, Register Address: 0x00_2000The above command when executed on RenderCS will result in a write to MMIO offset 0x00_4000 (0x00_2000 + 0x00_2000) instead to 0x00_2000. Note that RenderCS MMIO start offset is 0x2000. Table below shows the result of this command executed by various command streamers.<div> 270 }; 271 272 enum MI_COMMAND_OPCODE 273 { 274 MI_COMMAND_OPCODE_MILOADREGISTERIMM = 34, //!< No additional details 275 }; 276 277 enum COMMAND_TYPE 278 { 279 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 280 }; 281 282 //! \name Initializations 283 284 //! \brief Explicit member initialization function 285 MI_LOAD_REGISTER_IMM_CMD(); 286 287 static const size_t dwSize = 3; 288 static const size_t byteSize = 12; 289 }; 290 291 //! 292 //! \brief MI_LOAD_REGISTER_MEM 293 //! \details 294 //! The MI_LOAD_REGISTER_MEM command requests from a memory location and 295 //! stores that DWord to a register. 296 //! 297 //! The command temporarily halts commands that will cause cycles down the 298 //! 3D pipeline. 299 //! 300 //! The following addresses should NOT be used for MMIO writes: 301 //! 302 //! 0x8800 - 0x88FF 303 //! 304 //! >= 0xC0000 305 //! 306 //! 307 //! 308 //! Limited MMIO writes cycles to the Display Engine 0x40000-0xBFFFF) are 309 //! allowed, but must be spaced to allow only one pending at a time. This 310 //! can be done by issuing an SRM to the same address immediately after each 311 //! MMIO write. 312 //! 313 //! This command should not be used within a non-privilege batch buffer to 314 //! access global virtual space, doing so will be treated as privilege 315 //! access violation. Refer "User Mode Privilege Command" in 316 //! MI_BATCH_BUFFER_START command section to know HW behavior on 317 //! encountering privilege access violation. 318 //! 319 //! This command is not allowed to update the privilege register range when 320 //! executed from a non-privilege batch buffer. 321 //! 322 struct MI_LOAD_REGISTER_MEM_CMD 323 { 324 union 325 { 326 //!< DWORD 0 327 struct 328 { 329 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 330 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 18) ; //!< Reserved 331 uint32_t AddCsMmioStartOffset : __CODEGEN_BITFIELD(19, 19) ; //!< ADD_CS_MMIO_START_OFFSET 332 uint32_t Reserved20 : __CODEGEN_BITFIELD(20, 20) ; //!< Reserved 333 uint32_t AsyncModeEnable : __CODEGEN_BITFIELD(21, 21) ; //!< Async Mode Enable 334 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< Use Global GTT 335 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 336 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 337 }; 338 uint32_t Value; 339 } DW0; 340 union 341 { 342 //!< DWORD 1 343 struct 344 { 345 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 346 uint32_t RegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Register Address 347 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 348 }; 349 uint32_t Value; 350 } DW1; 351 union 352 { 353 //!< DWORD 2..3 354 struct 355 { 356 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 357 uint64_t MemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Memory Address 358 }; 359 uint32_t Value[2]; 360 } DW2_3; 361 362 //! \name Local enumerations 363 364 //! \brief ADD_CS_MMIO_START_OFFSET 365 //! \details 366 //! This bit controls the functionality of the "Register Address" field in 367 //! the command. 368 enum ADD_CS_MMIO_START_OFFSET 369 { 370 ADD_CS_MMIO_START_OFFSET_UNNAMED0 = 0, //!< "Register Address" field in the command is absolute and not an offset from the executing command streamer MMIO start offset. 371 ADD_CS_MMIO_START_OFFSET_UNNAMED1 = 1, //!< "Register Address" field in the command is treated as an offset from the executing Command Streamer’s MMIO start offset.Bits [22:2] of the "Register Address" are considered as dword offset to be added to the MMIO start offset of the corresponding command streamer.Example: MI_LOAD_REGISTER_MEM, ADD_CS_MMIO_START_OFFSET: true, Memory Address:0xABCD, Register Address: 0x1C_0030The above command when executed on RenderCS will result in a write to MMIO offset 0x1C_2030 (0x00_2000 + 0x1C_0030) instead to 0x1C_0030. Note that RenderCS MMIO start offset is 0x2000. 372 }; 373 374 enum MI_COMMAND_OPCODE 375 { 376 MI_COMMAND_OPCODE_MILOADREGISTERMEM = 41, //!< No additional details 377 }; 378 379 enum COMMAND_TYPE 380 { 381 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 382 }; 383 384 //! \name Initializations 385 386 //! \brief Explicit member initialization function 387 MI_LOAD_REGISTER_MEM_CMD(); 388 389 static const size_t dwSize = 4; 390 static const size_t byteSize = 16; 391 }; 392 393 //! 394 //! \brief MI_LOAD_REGISTER_REG 395 //! \details 396 //! The MI_LOAD_REGISTER_REG command reads from a source register location 397 //! and writes that value to a destination register location. 398 //! Any offset that is to a destination outside of the GT core will allow 399 //! the parser to continue once the cycle is at the GT boundry and not 400 //! destination. Any other address will ensure the destination is updated 401 //! prior to parsing the next command 402 //! 403 //! The command temporarily halts commands that will cause cycles down the 404 //! 3D pipeline. 405 //! 406 //! Destination register with mask implemented (Ex: some 407 //! registers have bits [31:16] as mask bits and bits[15:0] as data) will 408 //! not get updated unless the value read from source register has the bits 409 //! corresponding to the mask bits set. Note that any mask implemented 410 //! register when read returns "0" for the bits corresponding to mask 411 //! location. When the source and destination are mask implemented 412 //! registers, destination register will not get updated with the source 413 //! register contents. 414 //! 415 //! This command is not allowed to update the privilege register range when 416 //! executed from a non-privilege batch buffer. 417 //! 418 struct MI_LOAD_REGISTER_REG_CMD 419 { 420 union 421 { 422 //!< DWORD 0 423 struct 424 { 425 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 426 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 17) ; //!< Reserved 427 uint32_t AddCsMmioStartOffsetSource : __CODEGEN_BITFIELD(18, 18) ; //!< ADD_CS_MMIO_START_OFFSET_SOURCE 428 uint32_t AddCsMmioStartOffsetDestination : __CODEGEN_BITFIELD(19, 19) ; //!< ADD_CS_MMIO_START_OFFSET_DESTINATION 429 uint32_t Reserved20 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 430 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 431 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 432 }; 433 uint32_t Value; 434 } DW0; 435 union 436 { 437 //!< DWORD 1 438 struct 439 { 440 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 441 uint32_t SourceRegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Source Register Address 442 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 443 }; 444 uint32_t Value; 445 } DW1; 446 union 447 { 448 //!< DWORD 2 449 struct 450 { 451 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 452 uint32_t DestinationRegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Destination Register Address 453 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 454 }; 455 uint32_t Value; 456 } DW2; 457 458 //! \name Local enumerations 459 460 //! \brief ADD_CS_MMIO_START_OFFSET_SOURCE 461 //! \details 462 //! <p>This bit controls the functionality of the "Register Address Source" 463 //! field in the command.</p> 464 enum ADD_CS_MMIO_START_OFFSET_SOURCE 465 { 466 ADD_CS_MMIO_START_OFFSET_SOURCE_UNNAMED0 = 0, //!< "Register Address" field in the command is absolute and not an offset from the executing command streamer MMIO start offset. 467 ADD_CS_MMIO_START_OFFSET_SOURCE_UNNAMED1 = 1, //!< "Source Register Address" field in the command is treated as an offset from the executing Command Streamer’s MMIO start offset. Bits [22:2] of the "Source Register Address" are considered as dword offset to be added to the MMIO start offset of the corresponding command streamer.Example: MI_LOAD_REGISTER_REGISTER_REG, DEST_ADD_CS_MMIO_START_OFFSET: false, SRC_ADD_CS_MMIO_START_OFFSET:true, Source Register Address:0x1C_0130, Destination Register Address: 0x1C_0030The above command when executed on RenderCS will result in a MMIO read from 0x1C _2130 instead of read from 0x1C_0130 and write to MMIO offset 0x1C_0030. Note that RenderCS MMIO start offset is 0x2000. 468 }; 469 470 //! \brief ADD_CS_MMIO_START_OFFSET_DESTINATION 471 //! \details 472 //! <p>This bit controls the functionality of the "Register Address 473 //! Destination" field in the command.</p> 474 enum ADD_CS_MMIO_START_OFFSET_DESTINATION 475 { 476 ADD_CS_MMIO_START_OFFSET_DESTINATION_UNNAMED0 = 0, //!< "Destination Register Address" field in the command is absolute and not an offset from the executing command streamer MMIO start offset. 477 ADD_CS_MMIO_START_OFFSET_DESTINATION_UNNAMED1 = 1, //!< "Destination Register Address" field in the command is treated as an offset from the executing Command Streamer’s MMIO start offset. Bits [22:2] of the "Destination Register Address" are considered as dword offset to be added to the MMIO start offset of the corresponding command streamer.Example: MI_LOAD_REGISTER_REGISTER_REG, DEST_ADD_CS_MMIO_START_OFFSET: true, SRC_ADD_CS_MMIO_START_OFFSET:true, Source Register Address:0x1C_0130, Destination Register Address: 0x1C_0030The above command when executed on RenderCS will result in a MMIO read from 0x1C_2130 (0x00_2000 + 0x1C_0130) and write to MMIO offset 0x1C_2030 (0x00_2000 + 0x1C_0030) instead of read from 0x1C_0130 and write to 0x1C_0030. Note that RenderCS MMIO start offset is 0x2000. 478 }; 479 480 enum MI_COMMAND_OPCODE 481 { 482 MI_COMMAND_OPCODE_MILOADREGISTERREG = 42, //!< No additional details 483 }; 484 485 enum COMMAND_TYPE 486 { 487 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 488 }; 489 490 //! \name Initializations 491 492 //! \brief Explicit member initialization function 493 MI_LOAD_REGISTER_REG_CMD(); 494 495 static const size_t dwSize = 3; 496 static const size_t byteSize = 12; 497 }; 498 499 //! 500 //! \brief MI_STORE_REGISTER_MEM 501 //! \details 502 //! The MI_STORE_REGISTER_MEM command requests a register read from a 503 //! specified memory mapped register location in the device and store of 504 //! that DWord to memory. The register address is specified along with the 505 //! command to perform the read. 506 //! 507 //! 508 //! The command temporarily halts command execution. 509 //! 510 //! The memory address for the write is snooped on the host bus. 511 //! 512 //! This command should not be used from within a "non-privilege" batch 513 //! buffer to access global virtual space. doing so will be treated as 514 //! privilege access violation. Refer "User Mode Privilege Command" in 515 //! MI_BATCH_BUFFER_START command section to know HW behavior on 516 //! encountering privilege access violation. This command can be used within 517 //! ring buffers and/or "privilege" batch buffers to access global virtual 518 //! space. 519 //! 520 //! This command will cause undefined data to be written to memory if given 521 //! register addresses for the PGTBL_CTL_0 or FENCE registers. 522 //! 523 //! 524 //! 525 struct MI_STORE_REGISTER_MEM_CMD 526 { 527 union 528 { 529 //!< DWORD 0 530 struct 531 { 532 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 533 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 18) ; //!< Reserved 534 uint32_t AddCsMmioStartOffset : __CODEGEN_BITFIELD(19, 19) ; //!< ADD_CS_MMIO_START_OFFSET 535 uint32_t Reserved20 : __CODEGEN_BITFIELD(20, 21) ; //!< Reserved 536 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< Use Global GTT 537 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 538 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 539 }; 540 uint32_t Value; 541 } DW0; 542 union 543 { 544 //!< DWORD 1 545 struct 546 { 547 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 548 uint32_t RegisterAddress : __CODEGEN_BITFIELD( 2, 22) ; //!< Register Address 549 uint32_t Reserved55 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 550 }; 551 uint32_t Value; 552 } DW1; 553 union 554 { 555 //!< DWORD 2..3 556 struct 557 { 558 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 559 uint64_t MemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Memory Address 560 }; 561 uint32_t Value[2]; 562 } DW2_3; 563 564 //! \name Local enumerations 565 566 //! \brief ADD_CS_MMIO_START_OFFSET 567 //! \details 568 //! <p>This bit controls the functionality of the "Register Address" field 569 //! in the command.</p> 570 enum ADD_CS_MMIO_START_OFFSET 571 { 572 ADD_CS_MMIO_START_OFFSET_UNNAMED0 = 0, //!< "Register Address" field in the command is absolute and not an offset from the executing command streamer MMIO start offset. 573 ADD_CS_MMIO_START_OFFSET_UNNAMED1 = 1, //!< "Register Address" field in the command is treated as an offset from the executing Command Streamer’s MMIO start offset. Bits [22:2] of the "Register Address" are considered as dword offset to be added to the MMIO start offset of the corresponding command streamer.Example: MI_STORE_REGISTER_MEM, ADD_CS_MMIO_START_OFFSET: true, Memory Address:0xABCD, Register Address: 0x1C_0030The above command when executed on RenderCS will result in updating the memory address with the content of the MMIO offset 0x1C_2030 (0x00_2000 + 0x1C_0030) instead to 0x1C_0030. Note that RenderCS MMIO start offset is 0x2000. 574 }; 575 576 enum MI_COMMAND_OPCODE 577 { 578 MI_COMMAND_OPCODE_MISTOREREGISTERMEM = 36, //!< No additional details 579 }; 580 581 enum COMMAND_TYPE 582 { 583 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 584 }; 585 586 //! \name Initializations 587 588 //! \brief Explicit member initialization function 589 MI_STORE_REGISTER_MEM_CMD(); 590 591 static const size_t dwSize = 4; 592 static const size_t byteSize = 16; 593 }; 594 595 //! 596 //! \brief MI_BATCH_BUFFER_START 597 //! \details 598 //! The MI_BATCH_BUFFER_START command is used to initiate the execution of 599 //! commands stored in a batch buffer. For restrictions on the location of 600 //! batch buffers, see Batch Buffers in the Device Programming Interface 601 //! chapter of MI Functions. The batch buffer can be specified as privileged 602 //! or non-privileged, determining the operations considered valid when 603 //! initiated from within the buffer and any attached (chained) batch 604 //! buffers. See Batch Buffer Protection in the Device Programming Interface 605 //! chapter of MI Functions. 606 //! 607 //! A batch buffer initiated with this command must end either with a 608 //! MI_BATCH_BUFFER_END command or by chaining to another batch buffer with 609 //! an MI_BATCH_BUFFER_START command. 610 //! It is essential that the address location beyond the current page be 611 //! populated inside the GTT. HW performs over-fetch of the command 612 //! addresses and any over-fetch requires a valid TLB entry. A single extra 613 //! page beyond the batch buffer is sufficient. 614 //! 615 //! 616 //! 617 struct MI_BATCH_BUFFER_START_CMD 618 { 619 union 620 { 621 //!< DWORD 0 622 struct 623 { 624 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 625 uint32_t AddressSpaceIndicator : __CODEGEN_BITFIELD( 8, 8) ; //!< ADDRESS_SPACE_INDICATOR 626 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 21) ; //!< Reserved 627 uint32_t SecondLevelBatchBuffer : __CODEGEN_BITFIELD(22, 22) ; //!< SECOND_LEVEL_BATCH_BUFFER 628 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 629 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 630 }; 631 uint32_t Value; 632 } DW0; 633 union 634 { 635 //!< DWORD 1..2 636 struct 637 { 638 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 639 uint64_t BatchBufferStartAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Batch Buffer Start Address 640 }; 641 uint32_t Value[2]; 642 } DW1_2; 643 644 //! \name Local enumerations 645 646 //! \brief ADDRESS_SPACE_INDICATOR 647 //! \details 648 //! <p>Batch buffers accessed via PPGTT are considered as non-privileged. 649 //! Certain operations (e.g., MI_STORE_DATA_IMM commands to GGTT memory) are 650 //! prohibited within non-privileged buffers. More details mentioned in User 651 //! Mode Privileged command section. When MI_BATCH_BUFFER_START command is 652 //! executed from within a batch buffer (i.e., is a "chained" or "second 653 //! level" batch buffer command), the current active batch buffer's "Address 654 //! Space Indicator" and this field determine the "Address Space Indicator" 655 //! of the next buffer in the chain.</p> 656 //! <ul> 657 //! <li>Chained or Second level batch buffer can be in GGTT or PPGTT if the 658 //! parent batch buffer is in GGTT.</li> 659 //! <li>Chained or Second level batch buffer can only be in PPGTT if the 660 //! parent batch buffer is in PPGTT. This is enforced by Hardware.</li> 661 //! </ul> 662 enum ADDRESS_SPACE_INDICATOR 663 { 664 ADDRESS_SPACE_INDICATOR_GGTT = 0, //!< This batch buffer is located in GGTT memory and is privileged. 665 ADDRESS_SPACE_INDICATOR_PPGTT = 1, //!< This batch buffer is located in PPGTT memory and is Non-Privileged. 666 }; 667 668 //! \brief SECOND_LEVEL_BATCH_BUFFER 669 //! \details 670 //! <p>The command streamer contains three storage elements; one for the 671 //! ring head address, one for the batch head address, and one for the 672 //! second level batch head address. When performing batch buffer chaining, 673 //! hardware simply updates the head pointer of the first level batch 674 //! address storage. There is no stack in hardware. When this bit is set, 675 //! hardware uses the 2nd level batch head address storage element. Upon 676 //! MI_BATCH_BUFFER_END, it will automatically return to the first level 677 //! batch buffer address. This allows hardware to mimic a simple 3-level 678 //! stack.</p> 679 enum SECOND_LEVEL_BATCH_BUFFER 680 { 681 SECOND_LEVEL_BATCH_BUFFER_FIRSTLEVELBATCH = 0, //!< Place the batch buffer address in the 1st (traditional) level batch address storage element. 682 SECOND_LEVEL_BATCH_BUFFER_SECONDLEVELBATCH = 1, //!< Place the batch buffer address in the second-level batch address storage element. 683 }; 684 685 enum MI_COMMAND_OPCODE 686 { 687 MI_COMMAND_OPCODE_MIBATCHBUFFERSTART = 49, //!< No additional details 688 }; 689 690 enum COMMAND_TYPE 691 { 692 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 693 }; 694 695 //! \name Initializations 696 697 //! \brief Explicit member initialization function 698 MI_BATCH_BUFFER_START_CMD(); 699 700 static const size_t dwSize = 3; 701 static const size_t byteSize = 12; 702 }; 703 704 //! 705 //! \brief MI_SET_PREDICATE 706 //! \details 707 //! This command sets the Predication Check for the subsequent commands in 708 //! the command buffer except for MI_SET_PREDICATE itself. Render Command 709 //! Streamer NOOPs the following commands based on the PREDICATE_ENABLE from 710 //! MI_SET_PREDICATE, MI_SET_PREDICATE_RESULT and MI_SET_PREDICATE_RESULT_2 711 //! status. Resource Streamer doesn't take any action of parsing 712 //! MI_SET_PREDICATE, this command is similar to any other command which is 713 //! not meant for resource streamer. 714 //! 715 //! Executing MI_SET_PREDICATE command sets PREDICATE_ENABLE bits in MI_MODE 716 //! register, MI_MODE register gets render context save restored. 717 //! 718 //! MI_SET_PREDICATE predication scope must be confined within a Batch 719 //! Buffer to set of commands. 720 //! MI_SET_PREDICATE with Predicate Enable Must always have a 721 //! corresponding MI_SET_PREDICATE with Predicate Disable within the same 722 //! Batch Buffer. 723 //! MI_ARB_CHK command must be programmed outside the Predication Scope of 724 //! MI_SET_PREDICATE. 725 //! MI_SET_PREDICATE Predication Scope must not involve any RC6 triggering 726 //! events. 727 //! 728 //! 729 //! Only the following command(s) can be programmed between the 730 //! MI_SET_PREDICATE command enabled for predication: 3DSTATE_URB_VS 731 //! 3DSTATE_URB_HS 3DSTATE_URB_DS 3DSTATE_URB_GS 732 //! 3DSTATE_PUSH_CONSTANT_ALLOC_VS 3DSTATE_PUSH_CONSTANT_ALLOC_HS 733 //! 3DSTATE_PUSH_CONSTANT_ALLOC_DS 3DSTATE_PUSH_CONSTANT_ALLOC_GS 734 //! 3DSTATE_PUSH_CONSTANT_ALLOC_PS MI_LOAD_REGISTER_IMM MEDIA_VFE_STATE 735 //! MEDIA_OBJECT MEDIA_OBJJECT_WALKER MEDIA_INTERFACE_DESCRIPTOR_LOAD 736 //! 3DSTATE_WM_HZ_OP MI_STORE_DATA_IMM 737 //! 738 struct MI_SET_PREDICATE_CMD 739 { 740 union 741 { 742 //!< DWORD 0 743 struct 744 { 745 uint32_t PredicateEnable : __CODEGEN_BITFIELD( 0, 3) ; //!< PREDICATE_ENABLE 746 uint32_t Reserved4 : __CODEGEN_BITFIELD( 4, 22) ; //!< Reserved 747 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 748 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 749 }; 750 uint32_t Value; 751 } DW0; 752 753 //! \name Local enumerations 754 755 //! \brief PREDICATE_ENABLE 756 //! \details 757 //! This field sets the predication logic in render command streamer when 758 //! parsed. Predicate Disable is the default mode of operation. 759 enum PREDICATE_ENABLE 760 { 761 PREDICATE_ENABLE_NOOPNEVER = 0, //!< Predication is Disabled and RCS will process commands as usual. 762 PREDICATE_ENABLE_NOOPONRESULT2CLEAR = 1, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT_2 is clear. 763 PREDICATE_ENABLE_NOOPONRESULT2SET = 2, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT_2 is set. 764 PREDICATE_ENABLE_NOOPONRESULTCLEAR = 3, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT is clear. 765 PREDICATE_ENABLE_NOOPONRESULTSET = 4, //!< Following Commands will be NOOPED by RCS only if the MI_PREDICATE_RESULT is set. 766 PREDICATE_ENABLE_NOOPINRENDERCS = 11, //!< When RenderCS parses MI_SET_PREDICATE command with "Predicate Enable" set to "NOOP in RenderCS", RenderCS NOOP’s all the subsequent commands parsed unconditionally until the predication is disabled/modified using MI_SET_PREDICATE command. Other command streamers (non RenderCS) on parsing MI_SET_PREDICATE command with "Predicate Enable" set to "NOOP in RenderCS" don’t take any action and is equivalent to parsing MI_NOOP command. 767 PREDICATE_ENABLE_NOOPINPOSITIONCS = 12, //!< When PositionCS parses MI_SET_PREDICATE command with "Predicate Enable" set to "NOOP in PositionCS", PositionCS NOOP’s all the subsequent commands parsed unconditionally until the predication is disabled/modified using MI_SET_PREDICATE command. Other command streamers (non PositionCS) on parsing MI_SET_PREDICATE command with "Predicate Enable" set to "NOOP in PositionCS" don’t take any action and is equivalent to parsing MI_NOOP command. 768 PREDICATE_ENABLE_NOOPALWAYS = 15, //!< Following Commands will be NOOPED by RCS unconditionally. 769 }; 770 771 enum MI_COMMAND_OPCODE 772 { 773 MI_COMMAND_OPCODE_MISETPREDICATE = 1, //!< No additional details 774 }; 775 776 enum COMMAND_TYPE 777 { 778 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 779 }; 780 781 //! \name Initializations 782 783 //! \brief Explicit member initialization function 784 MI_SET_PREDICATE_CMD(); 785 786 static const size_t dwSize = 1; 787 static const size_t byteSize = 4; 788 }; 789 790 //! 791 //! \brief MI_COPY_MEM_MEM 792 //! \details 793 //! The MI_COPY_MEM_MEM command reads a DWord from memory and stores the 794 //! value of that DWord to back to memory. The source and destination 795 //! addresses are specified in the command. The command temporarily halts 796 //! command execution. 797 //! 798 //! This command should not be used within a "non-privileged" batch buffer 799 //! to access global virtual space; doing so will be treated as privilege 800 //! access violation. Refer to the "User Mode Privilege Command" in 801 //! MI_BATCH_BUFFER_START command section to learn more about HW behavior on 802 //! encountering a privilege access violation. 803 //! 804 //! This command can be used within ring buffers and/or privilege batch 805 //! buffers to access global virtual space. 806 //! 807 struct MI_COPY_MEM_MEM_CMD 808 { 809 union 810 { 811 //!< DWORD 0 812 struct 813 { 814 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 815 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 20) ; //!< Reserved 816 uint32_t UseGlobalGttDestination : __CODEGEN_BITFIELD(21, 21) ; //!< USE_GLOBAL_GTT_DESTINATION 817 uint32_t UseGlobalGttSource : __CODEGEN_BITFIELD(22, 22) ; //!< USE_GLOBAL_GTT_SOURCE 818 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 819 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 820 }; 821 uint32_t Value; 822 } DW0; 823 union 824 { 825 //!< DWORD 1..2 826 struct 827 { 828 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 829 uint64_t DestinationMemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Destination Memory Address 830 }; 831 uint32_t Value[2]; 832 } DW1_2; 833 union 834 { 835 //!< DWORD 3..4 836 struct 837 { 838 uint64_t Reserved96 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 839 uint64_t SourceMemoryAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Source Memory Address 840 }; 841 uint32_t Value[2]; 842 } DW3_4; 843 844 //! \name Local enumerations 845 846 //! \brief USE_GLOBAL_GTT_DESTINATION 847 //! \details 848 //! It is allowed for this bit to be set when executing this command from a 849 //! privileged (secure) batch buffer or ring buffer. This bit must be clear 850 //! when programmed from within a non-privileged batch buffer. This bit must 851 //! be 1 if the Per Process GTT Enable bit is clear. 852 enum USE_GLOBAL_GTT_DESTINATION 853 { 854 USE_GLOBAL_GTT_DESTINATION_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 855 USE_GLOBAL_GTT_DESTINATION_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must be executing from a privileged (secure) batch buffer. 856 }; 857 858 //! \brief USE_GLOBAL_GTT_SOURCE 859 //! \details 860 //! It is allowed for this bit to be set when executing this command from a 861 //! privileged (secure) batch buffer or ring buffer. This bit must be clear 862 //! when programmed from within a non-privileged batch buffer. This bit must 863 //! be 1 if the Per Process GTT Enable bit is clear. 864 enum USE_GLOBAL_GTT_SOURCE 865 { 866 USE_GLOBAL_GTT_SOURCE_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 867 USE_GLOBAL_GTT_SOURCE_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must be executing from a privileged (secure) batch buffer. 868 }; 869 870 enum MI_COMMAND_OPCODE 871 { 872 MI_COMMAND_OPCODE_MIMEMTOMEM = 46, //!< No additional details 873 }; 874 875 enum COMMAND_TYPE 876 { 877 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 878 }; 879 880 //! \name Initializations 881 882 //! \brief Explicit member initialization function 883 MI_COPY_MEM_MEM_CMD(); 884 885 static const size_t dwSize = 5; 886 static const size_t byteSize = 20; 887 }; 888 889 //! 890 //! \brief MI_STORE_DATA_IMM 891 //! \details 892 //! The MI_STORE_DATA_IMM command requests a write of the QWord constant 893 //! supplied in the packet to the specified Memory Address. As the write 894 //! targets a System Memory Address, the write operation is coherent with 895 //! the CPU cache (i.e., the processor cache is snooped). 896 //! 897 //! This command supports writing to multiple consecutive dwords or qwords 898 //! memory locations from the starting address. 899 //! 900 //! This command should not be used within a "non-privilege" batch buffer 901 //! to access global virtual space, doing so will be treated as privilege 902 //! access violation. Refer "User Mode Privilege Command" in 903 //! MI_BATCH_BUFFER_START command section to know HW behavior on 904 //! encountering privilege access violation. This command can be used within 905 //! ring buffers and/or privilege batch buffers to access global virtual 906 //! space. 907 //! This command can be used for general software synchronization through 908 //! variables in cacheable memory (i.e., where software does not need to 909 //! poll un-cached memory or device registers). 910 //! This command simply initiates the write operation with command 911 //! execution proceeding normally. Although the write operation is 912 //! guaranteed to complete eventually, there is no mechanism to synchronize 913 //! command execution with the completion (or even initiation) of these 914 //! operations. 915 //! 916 //! 917 //! 918 struct MI_STORE_DATA_IMM_CMD 919 { 920 union 921 { 922 //!< DWORD 0 923 struct 924 { 925 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 9) ; //!< DWORD_LENGTH 926 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 20) ; //!< Reserved 927 uint32_t StoreQword : __CODEGEN_BITFIELD(21, 21) ; //!< Store Qword 928 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< Use Global GTT 929 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 930 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 931 }; 932 uint32_t Value; 933 } DW0; 934 union 935 { 936 //!< DWORD 1..2 937 struct 938 { 939 uint64_t CoreModeEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Core Mode Enable 940 uint64_t Reserved33 : __CODEGEN_BITFIELD( 1, 1) ; //!< Reserved 941 uint64_t Address : __CODEGEN_BITFIELD( 2, 63) ; //!< Address 942 }; 943 uint32_t Value[2]; 944 } DW1_2; 945 union 946 { 947 //!< DWORD 3 948 struct 949 { 950 uint32_t DataDword0 ; //!< Data DWord 0 951 }; 952 uint32_t Value; 953 } DW3; 954 union 955 { 956 //!< DWORD 4 957 struct 958 { 959 uint32_t DataDword1 ; //!< Data DWord 1 960 }; 961 uint32_t Value; 962 } DW4; 963 964 //! \name Local enumerations 965 966 enum MI_COMMAND_OPCODE 967 { 968 MI_COMMAND_OPCODE_MISTOREDATAIMM = 32, //!< No additional details 969 }; 970 971 enum COMMAND_TYPE 972 { 973 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 974 }; 975 976 //! \name Initializations 977 978 //! \brief Explicit member initialization function 979 MI_STORE_DATA_IMM_CMD(); 980 981 static const size_t dwSize = 5; 982 static const size_t byteSize = 20; 983 }; 984 985 //! 986 //! \brief MI_SEMAPHORE_SIGNAL 987 //! \details 988 //! This command is used to signal the target engine stating the memory 989 //! semaphore update occurrence to one of its contexts with Target Context 990 //! ID. MI_SEMPHORE_SIGNAL and MI_SEMAPHORE_WAIT together replace the 991 //! MI_SEMAPHORE_MBOX command on BDW. MI_ATOMIC (non-posted) command will be 992 //! programmed prior to this command to update the semaphore data in memory. 993 //! 994 //! Bellow programming notes must be followed while programming 995 //! MI_SEMAPHORE_SIGNAL for POCS. MI_SEMAPHOR_SIGNAL command in POCS command 996 //! sequence may be used to signal RCS but not any other command streamer 997 //! (VCS, VECS, BCS). Semaphore signal received by POCS will never be 998 //! forwarded to GUC. Only RCS can semaphore signal POCS and no other 999 //! command streamer must signal POCS. Semaphore signal received by RCS from 1000 //! POCS will never get forwarded to GUC. 1001 //! 1002 //! Post-Sync operation bit must not be set when Target Engine Select is 1003 //! set to RCS. 1004 //! 1005 struct MI_SEMAPHORE_SIGNAL_CMD 1006 { 1007 union 1008 { 1009 //!< DWORD 0 1010 struct 1011 { 1012 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1013 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 14) ; //!< Reserved 1014 uint32_t TargetEngineSelect : __CODEGEN_BITFIELD(15, 18) ; //!< TARGET_ENGINE_SELECT 1015 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 22) ; //!< Reserved 1016 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1017 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1018 }; 1019 uint32_t Value; 1020 } DW0; 1021 union 1022 { 1023 //!< DWORD 1 1024 struct 1025 { 1026 uint32_t TargetContextId ; //!< Target Context ID 1027 }; 1028 uint32_t Value; 1029 } DW1; 1030 1031 //! \name Local enumerations 1032 1033 //! \brief TARGET_ENGINE_SELECT 1034 //! \details 1035 //! This field selects the target engine to which SIGNAL will be send to. 1036 enum TARGET_ENGINE_SELECT 1037 { 1038 TARGET_ENGINE_SELECT_RCS = 0, //!< No additional details 1039 TARGET_ENGINE_SELECT_VCS0 = 1, //!< No additional details 1040 TARGET_ENGINE_SELECT_BCS = 2, //!< No additional details 1041 TARGET_ENGINE_SELECT_VECS = 3, //!< No additional details 1042 TARGET_ENGINE_SELECT_VCS1 = 4, //!< No additional details 1043 TARGET_ENGINE_SELECT_VCS2 = 6, //!< No additional details 1044 TARGET_ENGINE_SELECT_VCS3 = 7, //!< No additional details 1045 TARGET_ENGINE_SELECT_VCS4 = 8, //!< No additional details 1046 TARGET_ENGINE_SELECT_VCS5 = 9, //!< No additional details 1047 TARGET_ENGINE_SELECT_VCS6 = 10, //!< No additional details 1048 TARGET_ENGINE_SELECT_VCS7 = 11, //!< No additional details 1049 TARGET_ENGINE_SELECT_VECS1 = 12, //!< No additional details 1050 TARGET_ENGINE_SELECT_VECS2 = 13, //!< No additional details 1051 TARGET_ENGINE_SELECT_VECS3 = 14, //!< No additional details 1052 }; 1053 1054 enum MI_COMMAND_OPCODE 1055 { 1056 MI_COMMAND_OPCODE_MISEMAPHORESIGNAL = 27, //!< No additional details 1057 }; 1058 1059 enum COMMAND_TYPE 1060 { 1061 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1062 }; 1063 1064 //! \name Initializations 1065 1066 //! \brief Explicit member initialization function 1067 MI_SEMAPHORE_SIGNAL_CMD(); 1068 1069 static const size_t dwSize = 2; 1070 static const size_t byteSize = 8; 1071 }; 1072 1073 //! 1074 //! \brief MI_SEMAPHORE_WAIT 1075 //! \details 1076 //! 1077 //! This command supports memory based Semaphore WAIT. Memory based 1078 //! semaphores will be used for synchronization between the Producer and the 1079 //! Consumer contexts. Producer and Consumer Contexts could be running on 1080 //! different engines or on the same engine inside GT. Producer Context 1081 //! implements a Signal and Consumer context implements a Wait. 1082 //! Command Streamer on parsing this command fetches data from the Semaphore 1083 //! Address mentioned in this command and compares it with the inline 1084 //! Semaphore Data Dword. 1085 //! 1086 //! If comparison passes, the command streamer moves to the next command. 1087 //! 1088 //! If comparison fails Command streamer switches out the context. Context 1089 //! switch can be inhibited by setting "Inhibit Synchronous Context Switch" 1090 //! in CTXT_SR_CTL register. 1091 //! 1092 //! If "Inhibit Synchronous context Switch" is enabled and comparison fails, 1093 //! Command Streamer evaluates the Compare Operation based on the Wait Mode 1094 //! until the compare operation is true or Wait is canceled by SW. 1095 //! 1096 //! CS generates semaphore wait interrupt to the scheduler when 1097 //! MI_SEMAPHORE_WAIT command is un-successful and when "Inhibit Synchronous 1098 //! Context Switch" is set. Scheduler can use this interrupt to preempt the 1099 //! context waiting on semaphore wait. 1100 //! 1101 //! 1102 //! 1103 //! 1104 //! MI_SEMAPHORE_WAIT command also supports register based Semaphore WAIT. 1105 //! Command Streamer on parsing this command fetches data from the MMIO 1106 //! offset mentioned in this command and compares it with the inline 1107 //! Semaphore Data Dword. This functionality is supported when "Register 1108 //! Poll" bit is set in the command header. In register poll mode of 1109 //! operation "Wait Mode" supported is always Poll mode and no Signal mode 1110 //! is supported. 1111 //! 1112 //! If comparison passes, the command streamer moves to the next command. 1113 //! 1114 //! Unlike in Memory based semaphore, there is no context switch on an 1115 //! un-successful semaphore wait in "Register Poll" mode, however preemption 1116 //! is supported on unsuccessful semaphore wait in "Register Poll" mode. 1117 //! Semaphore wait interrupt is not generated by default on wait 1118 //! un-successful in "Register Poll" mode. However interrupt generation can 1119 //! be enabled by setting debug mode bit "Semaphore Interrupt Enable in 1120 //! Register Poll Mode" in specified register. 1121 //! 1122 //! Also unlike in Memory based semaphore, generation of an interrupt for a 1123 //! semaphore wait in "Register Poll" mode is not dependent on the value of 1124 //! bit "Inhibit Synchronous Context Switch" in register "CTXT_SR_CTL" 1125 //! 1126 //! Register Poll mode of Semaphore Wait command operation is non-privileged 1127 //! and will be supported from PPGTT batch buffers. 1128 //! 1129 //! HW will trigger Render DOP CG on semaphore wait unsuccessful by default 1130 //! and can be disabled if not desired by programming "Register 1131 //! Poll Mode Semaphore Wait Event IDLE message Disable" bit in "INSTPM" 1132 //! register. Note that Render DOP CG will not be triggered on register 1133 //! semaphore wait un-successfull from INDIRECT_CTX pointer or 1134 //! BB_PER_CTX_PTR buffers. 1135 //! 1136 //! MI_SEMAPHORE_WAIT command must be always programmed with "Wait Mode" set 1137 //! to "Polling Mode" Or MI_SEMAPHORE_WAIT command with "Wait Mode" set to 1138 //! "Polling Mode" can be programmed when "Semaphore Wait Event IDLE message 1139 //! Disable" bit in "RC_PSMI_CTRL" register is set to disable Idle messaging 1140 //! on unsuccessful MI_SEMPAHORE_WAIT. 1141 //! 1142 struct MI_SEMAPHORE_WAIT_CMD 1143 { 1144 union 1145 { 1146 //!< DWORD 0 1147 struct 1148 { 1149 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1150 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 1151 uint32_t CompareOperation : __CODEGEN_BITFIELD(12, 14) ; //!< COMPARE_OPERATION 1152 uint32_t WaitMode : __CODEGEN_BITFIELD(15, 15) ; //!< WAIT_MODE 1153 uint32_t RegisterPollMode : __CODEGEN_BITFIELD(16, 16) ; //!< REGISTER_POLL_MODE 1154 uint32_t Reserved17 : __CODEGEN_BITFIELD(17, 21) ; //!< Reserved 1155 uint32_t MemoryType : __CODEGEN_BITFIELD(22, 22) ; //!< MEMORY_TYPE 1156 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1157 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1158 }; 1159 uint32_t Value; 1160 } DW0; 1161 union 1162 { 1163 //!< DWORD 1 1164 struct 1165 { 1166 uint32_t SemaphoreDataDword ; //!< Semaphore Data Dword 1167 }; 1168 uint32_t Value; 1169 } DW1; 1170 union 1171 { 1172 //!< DWORD 2..3 1173 struct 1174 { 1175 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1176 uint64_t SemaphoreAddress : __CODEGEN_BITFIELD( 2, 63) ; //!< Semaphore Address 1177 }; 1178 uint32_t Value[2]; 1179 } DW2_3; 1180 1181 //! \name Local enumerations 1182 1183 //! \brief COMPARE_OPERATION 1184 //! \details 1185 //! This field specifies the operation that will be executed to create the 1186 //! result that will either allow the context to continue or wait. 1187 enum COMPARE_OPERATION 1188 { 1189 COMPARE_OPERATION_SADGREATERTHANSDD = 0, //!< If Indirect fetched data is greater than inline data then continue. 1190 COMPARE_OPERATION_SADGREATERTHANOREQUALSDD = 1, //!< If Indirect fetched data is greater than or equal to inline data then continue. 1191 COMPARE_OPERATION_SADLESSTHANSDD = 2, //!< If Indirect fetched data is less than inline data then continue. 1192 COMPARE_OPERATION_SADLESSTHANOREQUALSDD = 3, //!< If Indirect fetched data is less than or equal to inline data then continue. 1193 COMPARE_OPERATION_SADEQUALSDD = 4, //!< If Indirect fetched data is equalto inline data then continue. 1194 COMPARE_OPERATION_SADNOTEQUALSDD = 5, //!< If Indirect fetched data is not equal to inline data then continue. 1195 }; 1196 1197 //! \brief WAIT_MODE 1198 //! \details 1199 //! This bit specifies the WAIT behavior when the semaphore comparison fails 1200 //! and before the context is switched out. 1201 enum WAIT_MODE 1202 { 1203 WAIT_MODE_SIGNALMODE = 0, //!< In this mode HW will reacquire the semaphore data from memory on receiving SIGNAL with the same Context ID. 1204 WAIT_MODE_POLLINGMODE = 1, //!< In this mode HW periodically reads the semaphore data from memory for comparison until it is context switched out. Periodicity will be mentioned in a SEMA_WAIT_POLL register. 1205 }; 1206 1207 //! \brief REGISTER_POLL_MODE 1208 //! \details 1209 //! <p>This field control the seamphore wait behavior of polling from memory 1210 //! vs MMIO register.</p> 1211 enum REGISTER_POLL_MODE 1212 { 1213 REGISTER_POLL_MODE_MEMORYPOLL = 0, //!< In this mode HW will functional as in regular mode and checks for semaphore data in memory. 1214 REGISTER_POLL_MODE_REGISTERPOLL = 1, //!< In this mode HW periodically reads the semaphore data from MMIO register instead of memory for comparison until the condition is satisfied. Periodicity will be mentioned in a SEMA_WAIT_POLL register.When operating in register poll mode, DW2 "Semaphore Address" (bits 22:2) carries the register MMIO offset to be polled.In register poll mode "Memory Type" field of this command are ignored by HW. 1215 }; 1216 1217 //! \brief MEMORY_TYPE 1218 //! \details 1219 //! This bit will be ignored and treated as if clear when executing from a 1220 //! non-privileged batch buffer. It is allowed for this bit to be clear when 1221 //! executing this command from a privileged (secure) batch buffer. This bit 1222 //! <i>must</i> be 1 if the <b>Per Process GTT Enable</b> bit is clear. 1223 enum MEMORY_TYPE 1224 { 1225 MEMORY_TYPE_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 1226 MEMORY_TYPE_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must beexecuting from a privileged (secure) batch buffer. 1227 }; 1228 1229 enum MI_COMMAND_OPCODE 1230 { 1231 MI_COMMAND_OPCODE_MISEMAPHOREWAIT = 28, //!< No additional details 1232 }; 1233 1234 enum COMMAND_TYPE 1235 { 1236 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1237 }; 1238 1239 //! \name Initializations 1240 1241 //! \brief Explicit member initialization function 1242 MI_SEMAPHORE_WAIT_CMD(); 1243 1244 static const size_t dwSize = 4; 1245 static const size_t byteSize = 16; 1246 }; 1247 1248 //! 1249 //! \brief MI_CONDITIONAL_BATCH_BUFFER_END 1250 //! \details 1251 //! The MI_CONDITIONAL_BATCH_BUFFER_END command is used to conditionally 1252 //! terminate the execution of commands stored in a batch buffer initiated 1253 //! using a MI_BATCH_BUFFER_START command. Termination of second level batch 1254 //! buffer due to this command will also terminate the parent/first level 1255 //! batch buffer. 1256 //! 1257 //! 1258 struct MI_CONDITIONAL_BATCH_BUFFER_END_CMD 1259 { 1260 union 1261 { 1262 //!< DWORD 0 1263 struct 1264 { 1265 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1266 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 18) ; //!< Reserved 1267 uint32_t CompareMaskMode : __CODEGEN_BITFIELD(19, 19) ; //!< COMPARE_MASK_MODE 1268 uint32_t Reserved20 : __CODEGEN_BITFIELD(20, 20) ; //!< Reserved 1269 uint32_t CompareSemaphore : __CODEGEN_BITFIELD(21, 21) ; //!< COMPARE_SEMAPHORE 1270 uint32_t UseGlobalGtt : __CODEGEN_BITFIELD(22, 22) ; //!< USE_GLOBAL_GTT 1271 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1272 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1273 }; 1274 uint32_t Value; 1275 } DW0; 1276 union 1277 { 1278 //!< DWORD 1 1279 struct 1280 { 1281 uint32_t CompareDataDword ; //!< Compare Data Dword 1282 }; 1283 uint32_t Value; 1284 } DW1; 1285 union 1286 { 1287 //!< DWORD 2..3 1288 struct 1289 { 1290 uint64_t Reserved64 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1291 uint64_t CompareAddress : __CODEGEN_BITFIELD( 3, 63) ; //!< Compare Address 1292 }; 1293 uint32_t Value[2]; 1294 } DW2_3; 1295 1296 //! \name Local enumerations 1297 1298 //! \brief COMPARE_MASK_MODE 1299 //! \details 1300 //! When "Compare Mask Mode" is enabled, "Compare Address" must be qword 1301 //! aligned. 1302 enum COMPARE_MASK_MODE 1303 { 1304 COMPARE_MASK_MODE_COMPAREMASKMODEDISABLED = 0, //!< Compare address points to Dword in memory consisting of Data Dword(DW0). HW will compare Data Dword(DW0) against Semaphore Data Dword. 1305 COMPARE_MASK_MODE_COMPAREMASKMODEENABLED = 1, //!< Compare address points to Qword in memory consisting of compare Mask (DW0) and Data Dword(DW1). HW will do AND operation on Mask(DW0) with Data Dword(DW1) and then compare the result against Semaphore Data Dword. 1306 }; 1307 1308 //! \brief COMPARE_SEMAPHORE 1309 //! \details 1310 //! <p>If set, the value from the Compare Data Dword is compared to the 1311 //! value from the Compare Address in memory. If the value at Compare 1312 //! Address is greater than the Compare Data Dword, execution of current 1313 //! command buffer should continue. If clear, the parser will continue to 1314 //! the next command and not exit the batch buffer.</p> 1315 enum COMPARE_SEMAPHORE 1316 { 1317 COMPARE_SEMAPHORE_UNNAMED0 = 0, //!< No additional details 1318 }; 1319 1320 //! \brief USE_GLOBAL_GTT 1321 //! \details 1322 //! If set, this command will use the global GTT to translate the <b>Compare 1323 //! Address</b> and this command must be executing from a privileged 1324 //! (secure) batch buffer. If clear, the PPGTT will be used to translate the 1325 //! <b>Compare Address</b>. 1326 enum USE_GLOBAL_GTT 1327 { 1328 USE_GLOBAL_GTT_UNNAMED0 = 0, //!< No additional details 1329 }; 1330 1331 enum MI_COMMAND_OPCODE 1332 { 1333 MI_COMMAND_OPCODE_MICONDITIONALBATCHBUFFEREND = 54, //!< No additional details 1334 }; 1335 1336 enum COMMAND_TYPE 1337 { 1338 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1339 }; 1340 1341 //! \name Initializations 1342 1343 //! \brief Explicit member initialization function 1344 MI_CONDITIONAL_BATCH_BUFFER_END_CMD(); 1345 1346 static const size_t dwSize = 4; 1347 static const size_t byteSize = 16; 1348 }; 1349 1350 //! 1351 //! \brief MI_ATOMIC 1352 //! \details 1353 //! MI_ATOMIC is used to carry atomic operation on data in graphics memory. 1354 //! Atomic operations are supported on data granularity of 4B, 8B and 16B. 1355 //! The atomic operation leads to a read-modify-write operation on the data 1356 //! in graphics memory with the option of returning value. The data in 1357 //! graphics memory is modified by doing arithmetic and logical operation 1358 //! with the inline/indirect data provided with the MI_ATOMIC command. 1359 //! Inline/Indirect provided in the command can be one or two operands based 1360 //! on the atomic operation. Ex: Atomic-Compare operation needs two operands 1361 //! while Atomic-Add operation needs single operand and Atomic-increment 1362 //! requires no operand. Refer "Atomics" sub-section of "L3 Cache and URB" 1363 //! section for detailed atomic operations supported. Atomic 1364 //! operations can be enabled to return value by setting "Return Data 1365 //! Control" field in the command, return data is stored to CS_GPR 1366 //! registers. 1367 //! CS_GPR4/5 registers are updated with memory Return Data based on the 1368 //! "Data Size". Each GPR register is qword in size and occupies two MMIO 1369 //! registers. 1370 //! Note: Any references to CS_GPR registers in the command should be 1371 //! understood as the CS_GPR registers belonging to the corresponding 1372 //! engines *CS_GPR registers. 1373 //! 1374 //! 1375 //! Indirect Source Operands: 1376 //! 1377 //! Operand1 is sourced from [CS_GPR1, CS_GPR0] 1378 //! 1379 //! Operand2 is sourced from [CS_GPR3, CS_GPR2] 1380 //! 1381 //! Read return Data is stored in [CS_GPR_5, CS_GPR4] 1382 //! 1383 //! When "Data Size" is DWORD lower dword of CS_GPR4 (Qword) is updated with 1384 //! the dword data returned from memory. When "Data Size" is QWORD only 1385 //! CS_GPR4 (Qword) is updated with the qword data returned from memory. 1386 //! When the data size is OCTWORD CS_GPR4/5 are updated with the OCTWORD 1387 //! data returned from memory. CS_GPR4 is loaded with lower qword returned 1388 //! from memory and CS_GPR5 is loaded with upper qword returned from memory. 1389 //! 1390 //! When Inline Data mode is not set, Dwords 3..10 must not be included as 1391 //! part of the command. Dword Length field in the header must be programmed 1392 //! accordingly. 1393 //! When Inline Data Mode is set, Dwords3..10 must be included based on the 1394 //! Data Size field of the header. Both Operand-1 and Operand-2 dwords must 1395 //! be programmed based on the Data Size field. Operand-2 must be programmed 1396 //! to 0x0 if the atomic operation doesn't require it. Dword Length field in 1397 //! the header must be programmed accordingly. 1398 //! 1399 //! 1400 //! 1401 struct MI_ATOMIC_CMD 1402 { 1403 union 1404 { 1405 //!< DWORD 0 1406 struct 1407 { 1408 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1409 uint32_t AtomicOpcode : __CODEGEN_BITFIELD( 8, 15) ; //!< ATOMIC OPCODE 1410 uint32_t ReturnDataControl : __CODEGEN_BITFIELD(16, 16) ; //!< Return Data Control 1411 uint32_t CsStall : __CODEGEN_BITFIELD(17, 17) ; //!< CS STALL 1412 uint32_t InlineData : __CODEGEN_BITFIELD(18, 18) ; //!< Inline Data 1413 uint32_t DataSize : __CODEGEN_BITFIELD(19, 20) ; //!< DATA_SIZE 1414 uint32_t Reserved21 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 1415 uint32_t MemoryType : __CODEGEN_BITFIELD(22, 22) ; //!< MEMORY_TYPE 1416 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1417 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1418 }; 1419 uint32_t Value; 1420 } DW0; 1421 union 1422 { 1423 //!< DWORD 1 1424 struct 1425 { 1426 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1427 uint32_t MemoryAddress : __CODEGEN_BITFIELD( 2, 31) ; //!< Memory Address 1428 }; 1429 uint32_t Value; 1430 } DW1; 1431 union 1432 { 1433 //!< DWORD 2 1434 struct 1435 { 1436 uint32_t MemoryAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Memory Address High 1437 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1438 }; 1439 uint32_t Value; 1440 } DW2; 1441 union 1442 { 1443 //!< DWORD 3 1444 struct 1445 { 1446 uint32_t Operand1DataDword0 ; //!< Operand1 Data Dword 0 1447 }; 1448 uint32_t Value; 1449 } DW3; 1450 union 1451 { 1452 //!< DWORD 4 1453 struct 1454 { 1455 uint32_t Operand2DataDword0 ; //!< Operand2 Data Dword 0 1456 }; 1457 uint32_t Value; 1458 } DW4; 1459 union 1460 { 1461 //!< DWORD 5 1462 struct 1463 { 1464 uint32_t Operand1DataDword1 ; //!< Operand1 Data Dword 1 1465 }; 1466 uint32_t Value; 1467 } DW5; 1468 union 1469 { 1470 //!< DWORD 6 1471 struct 1472 { 1473 uint32_t Operand2DataDword1 ; //!< Operand2 Data Dword 1 1474 }; 1475 uint32_t Value; 1476 } DW6; 1477 union 1478 { 1479 //!< DWORD 7 1480 struct 1481 { 1482 uint32_t Operand1DataDword2 ; //!< Operand1 Data Dword 2 1483 }; 1484 uint32_t Value; 1485 } DW7; 1486 union 1487 { 1488 //!< DWORD 8 1489 struct 1490 { 1491 uint32_t Operand2DataDword2 ; //!< Operand2 Data Dword 2 1492 }; 1493 uint32_t Value; 1494 } DW8; 1495 union 1496 { 1497 //!< DWORD 9 1498 struct 1499 { 1500 uint32_t Operand1DataDword3 ; //!< Operand1 Data Dword 3 1501 }; 1502 uint32_t Value; 1503 } DW9; 1504 union 1505 { 1506 //!< DWORD 10 1507 struct 1508 { 1509 uint32_t Operand2DataDword3 ; //!< Operand2 Data Dword 3 1510 }; 1511 uint32_t Value; 1512 } DW10; 1513 1514 //! \name Local enumerations 1515 1516 //! \brief DATA_SIZE 1517 //! \details 1518 //! This field indicates the size of the operand in dword/qword/octword on 1519 //! which atomic operation will be performed. Data size must match with the 1520 //! Atomic Opcode. Operation Data size could be 4B, 8B or 16B 1521 enum DATA_SIZE 1522 { 1523 DATA_SIZE_DWORD = 0, //!< Operand size used by Atomic Operation is DWORD. 1524 DATA_SIZE_QWORD = 1, //!< Operand Size used by Atomic Operation is QWORD. 1525 DATA_SIZE_OCTWORD = 2, //!< Operand Size used by Atomic Operation is OCTWORD. 1526 }; 1527 1528 //! \brief MEMORY_TYPE 1529 //! \details 1530 //! This bit will be ignored and treated as if clear when executing from a 1531 //! non-privileged batch buffer. It is allowed for this bit to be clear when 1532 //! executing this command from a privileged (secure) batch buffer. This bit 1533 //! must be 1 if the <b>Per Process GTT Enable</b> bit is clear. 1534 enum MEMORY_TYPE 1535 { 1536 MEMORY_TYPE_PERPROCESSGRAPHICSADDRESS = 0, //!< No additional details 1537 MEMORY_TYPE_GLOBALGRAPHICSADDRESS = 1, //!< This command will use the global GTT to translate the Address and this command must be executing from a privileged (secure) batch buffer. 1538 }; 1539 1540 enum MI_COMMAND_OPCODE 1541 { 1542 MI_COMMAND_OPCODE_MIATOMIC = 47, //!< No additional details 1543 }; 1544 1545 enum COMMAND_TYPE 1546 { 1547 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1548 }; 1549 1550 //! \name Initializations 1551 1552 //! \brief Explicit member initialization function 1553 MI_ATOMIC_CMD(); 1554 1555 static const size_t dwSize = 11; 1556 static const size_t byteSize = 44; 1557 }; 1558 1559 //! 1560 //! \brief MI_MATH 1561 //! \details 1562 //! The MI_MATH command allows software to send instructions to the ALU in 1563 //! the Command Streamer. This command is the means by which the ALU is 1564 //! accessed. ALU instructions form the data payload of the MI_MATH command. 1565 //! An ALU instruction takes one DWord in size. The MI_MATH DWord Length is 1566 //! programmed based on the number of ALU instructions included, limited 1567 //! only by the max DWord Length supported. When the command streamer parses 1568 //! an MI_MATH command, it sends the included ALU instructions to the ALU. 1569 //! The ALU processes any instruction in a single clock. See the ALU section 1570 //! for more details. 1571 //! 1572 struct MI_MATH_CMD 1573 { 1574 union 1575 { 1576 //!< DWORD 0 1577 struct 1578 { 1579 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1580 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 22) ; //!< Reserved 1581 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1582 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1583 }; 1584 uint32_t Value; 1585 } DW0; 1586 1587 //! \name Local enumerations 1588 1589 enum MI_COMMAND_OPCODE 1590 { 1591 MI_COMMAND_OPCODE_MIMATH = 26, //!< No additional details 1592 }; 1593 1594 enum COMMAND_TYPE 1595 { 1596 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1597 }; 1598 1599 //! \name Initializations 1600 1601 //! \brief Explicit member initialization function 1602 MI_MATH_CMD(); 1603 1604 static const size_t dwSize = 1; 1605 static const size_t byteSize = 4; 1606 }; 1607 1608 //! 1609 //! \brief MI_FLUSH_DW 1610 //! \details 1611 //! The MI_FLUSH_DW command is used to perform an internal "flush" 1612 //! operation. The parser pauses on an internal flush until all drawing 1613 //! engines have completed any pending operations. In addition, this command 1614 //! can also be used to:Flush any dirty data to memory. Invalidate the TLB 1615 //! cache inside the hardware Usage note: After this command is completed 1616 //! with a Store DWord enabled, CPU access to graphics memory will be 1617 //! coherent (assuming the Render Cache flush is not inhibited). 1618 //! 1619 struct MI_FLUSH_DW_CMD 1620 { 1621 union 1622 { 1623 //!< DWORD 0 1624 struct 1625 { 1626 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 5) ; //!< DWORD_LENGTH 1627 uint32_t Reserved6 : __CODEGEN_BITFIELD( 6, 6) ; //!< Reserved 1628 uint32_t VideoPipelineCacheInvalidate : __CODEGEN_BITFIELD( 7, 7) ; //!< Video Pipeline Cache invalidate 1629 uint32_t NotifyEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Notify Enable 1630 uint32_t FlushLlc : __CODEGEN_BITFIELD( 9, 9) ; //!< Flush LLC 1631 uint32_t Reserved10 : __CODEGEN_BITFIELD(10, 13) ; //!< Reserved 1632 uint32_t PostSyncOperation : __CODEGEN_BITFIELD(14, 15) ; //!< POST_SYNC_OPERATION 1633 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 1634 uint32_t TlbInvalidate : __CODEGEN_BITFIELD(18, 18) ; //!< TLB Invalidate 1635 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 20) ; //!< Reserved 1636 uint32_t StoreDataIndex : __CODEGEN_BITFIELD(21, 21) ; //!< Store Data Index 1637 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 22) ; //!< Reserved 1638 uint32_t MiCommandOpcode : __CODEGEN_BITFIELD(23, 28) ; //!< MI_COMMAND_OPCODE 1639 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1640 }; 1641 uint32_t Value; 1642 } DW0; 1643 union 1644 { 1645 //!< DWORD 1..2 1646 struct 1647 { 1648 uint64_t Reserved32 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1649 uint64_t DestinationAddressType : __CODEGEN_BITFIELD( 2, 2) ; //!< DESTINATION_ADDRESS_TYPE 1650 uint64_t Address : __CODEGEN_BITFIELD( 3, 47) ; //!< Address 1651 uint64_t Reserved80 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 1652 }; 1653 uint32_t Value[2]; 1654 } DW1_2; 1655 union 1656 { 1657 //!< DWORD 3..4 1658 struct 1659 { 1660 uint64_t ImmediateData ; //!< Immediate Data 1661 }; 1662 uint32_t Value[2]; 1663 } DW3_4; 1664 1665 //! \name Local enumerations 1666 1667 //! \brief POST_SYNC_OPERATION 1668 //! \details 1669 //! BitFieldDesc 1670 enum POST_SYNC_OPERATION 1671 { 1672 POST_SYNC_OPERATION_NOWRITE = 0, //!< No write occurs as a result of this instruction. This can be used to implement a "trap" operation, etc. 1673 POST_SYNC_OPERATION_WRITEIMMEDIATEDATA = 1, //!< HW implicitly detects the Data size to be Qword or Dword to be written to memory based on the command dword length programmed . When Dword Length indicates Qword, Writes the QWord containing Immediate Data Low, High DWs to the Destination Address . When Dword Length indicates Dword, Writes the DWord containing Immediate Data Low to the Destination Address 1674 POST_SYNC_OPERATION_UNNAMED3 = 3, //!< Write the TIMESTAMP register to the Destination Address. The upper 28 bits of the TIMESTAMP register are tied to '0'. 1675 }; 1676 1677 enum MI_COMMAND_OPCODE 1678 { 1679 MI_COMMAND_OPCODE_MIFLUSHDW = 38, //!< No additional details 1680 }; 1681 1682 enum COMMAND_TYPE 1683 { 1684 COMMAND_TYPE_MICOMMAND = 0, //!< No additional details 1685 }; 1686 1687 //! \brief DESTINATION_ADDRESS_TYPE 1688 //! \details 1689 //! Defines address space of Destination Address 1690 enum DESTINATION_ADDRESS_TYPE 1691 { 1692 DESTINATION_ADDRESS_TYPE_PPGTT = 0, //!< Use PPGTT address space for DW write 1693 DESTINATION_ADDRESS_TYPE_GGTT = 1, //!< Use GGTT address space for DW write 1694 }; 1695 1696 //! \name Initializations 1697 1698 //! \brief Explicit member initialization function 1699 MI_FLUSH_DW_CMD(); 1700 1701 static const size_t dwSize = 5; 1702 static const size_t byteSize = 20; 1703 }; 1704 1705 //! 1706 //! \brief PIPE_CONTROL 1707 //! \details 1708 //! The PIPE_CONTROL command is used to effect the synchronization described 1709 //! above. 1710 //! 1711 //! SW must follow below programming restrictions when 1712 //! programming PIPECONTROL command ifor POCS: 1713 //! 1714 //! 1715 //! Write cache flush bits must not be set (Render Target Cache Flush 1716 //! Enable, DC Flush Enable, Depth Cache Flush Enable ) 1717 //! 1718 //! Post Sync Operations must not be set to "Write PS Depth Count" 1719 //! 1720 //! "Stall at Pixel Scoreboard" must not be set 1721 //! 1722 //! "Notify Enable" must not be set. 1723 //! 1724 //! "Depth Stall Enable" must not be set. 1725 //! 1726 //! "Generic Media State Clear" must not be set. 1727 //! 1728 //! "PSD Sync Enable" must not be set. 1729 //! 1730 struct PIPE_CONTROL_CMD 1731 { 1732 union 1733 { 1734 //!< DWORD 0 1735 struct 1736 { 1737 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 7) ; //!< DWORD_LENGTH 1738 uint32_t Reserved8 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1739 uint32_t Command3DSubOpcode : __CODEGEN_BITFIELD(16, 23) ; //!< _3D_COMMAND_SUB_OPCODE 1740 uint32_t Command3DOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< _3D_COMMAND_OPCODE 1741 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1742 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1743 }; 1744 uint32_t Value; 1745 } DW0; 1746 union 1747 { 1748 //!< DWORD 1 1749 struct 1750 { 1751 uint32_t DepthCacheFlushEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< DEPTH_CACHE_FLUSH_ENABLE 1752 uint32_t StallAtPixelScoreboard : __CODEGEN_BITFIELD( 1, 1) ; //!< STALL_AT_PIXEL_SCOREBOARD 1753 uint32_t StateCacheInvalidationEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< State Cache Invalidation Enable 1754 uint32_t ConstantCacheInvalidationEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< Constant Cache Invalidation Enable 1755 uint32_t VfCacheInvalidationEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< VF Cache Invalidation Enable 1756 uint32_t DcFlushEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< DC Flush Enable 1757 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 6) ; //!< Reserved 1758 uint32_t PipeControlFlushEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Pipe Control Flush Enable 1759 uint32_t NotifyEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Notify Enable 1760 uint32_t IndirectStatePointersDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Indirect State Pointers Disable 1761 uint32_t TextureCacheInvalidationEnable : __CODEGEN_BITFIELD(10, 10) ; //!< Texture Cache Invalidation Enable 1762 uint32_t InstructionCacheInvalidateEnable : __CODEGEN_BITFIELD(11, 11) ; //!< Instruction Cache Invalidate Enable 1763 uint32_t RenderTargetCacheFlushEnable : __CODEGEN_BITFIELD(12, 12) ; //!< RENDER_TARGET_CACHE_FLUSH_ENABLE 1764 uint32_t DepthStallEnable : __CODEGEN_BITFIELD(13, 13) ; //!< DEPTH_STALL_ENABLE 1765 uint32_t PostSyncOperation : __CODEGEN_BITFIELD(14, 15) ; //!< POST_SYNC_OPERATION 1766 uint32_t GenericMediaStateClear : __CODEGEN_BITFIELD(16, 16) ; //!< Generic Media State Clear 1767 uint32_t PsdSyncEnable : __CODEGEN_BITFIELD(17, 17) ; //!< PSD Sync Enable 1768 uint32_t TlbInvalidate : __CODEGEN_BITFIELD(18, 18) ; //!< TLB Invalidate 1769 uint32_t GlobalSnapshotCountReset : __CODEGEN_BITFIELD(19, 19) ; //!< GLOBAL_SNAPSHOT_COUNT_RESET 1770 uint32_t CommandStreamerStallEnable : __CODEGEN_BITFIELD(20, 20) ; //!< Command Streamer Stall Enable 1771 uint32_t StoreDataIndex : __CODEGEN_BITFIELD(21, 21) ; //!< Store Data Index 1772 uint32_t Reserved54 : __CODEGEN_BITFIELD(22, 22) ; //!< Reserved 1773 uint32_t LriPostSyncOperation : __CODEGEN_BITFIELD(23, 23) ; //!< LRI_POST_SYNC_OPERATION 1774 uint32_t DestinationAddressType : __CODEGEN_BITFIELD(24, 24) ; //!< DESTINATION_ADDRESS_TYPE 1775 uint32_t Reserved57 : __CODEGEN_BITFIELD(25, 25) ; //!< Reserved 1776 uint32_t FlushLlc : __CODEGEN_BITFIELD(26, 26) ; //!< Flush LLC 1777 uint32_t Reserved59 : __CODEGEN_BITFIELD(27, 27) ; //!< Reserved 1778 uint32_t TileCacheFlushEnable : __CODEGEN_BITFIELD(28, 28) ; //!< TILE_CACHE_FLUSH_ENABLE 1779 uint32_t Reserved61 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1780 }; 1781 uint32_t Value; 1782 } DW1; 1783 union 1784 { 1785 //!< DWORD 2 1786 struct 1787 { 1788 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 1) ; //!< Reserved 1789 uint32_t Address : __CODEGEN_BITFIELD( 2, 31) ; //!< Address 1790 }; 1791 uint32_t Value; 1792 } DW2; 1793 union 1794 { 1795 //!< DWORD 3 1796 struct 1797 { 1798 uint32_t AddressHigh ; //!< Address High 1799 }; 1800 uint32_t Value; 1801 } DW3; 1802 union 1803 { 1804 //!< DWORD 4..5 1805 struct 1806 { 1807 uint64_t ImmediateData ; //!< Immediate Data 1808 }; 1809 uint32_t Value[2]; 1810 } DW4_5; 1811 1812 //! \name Local enumerations 1813 1814 enum _3D_COMMAND_SUB_OPCODE 1815 { 1816 _3D_COMMAND_SUB_OPCODE_PIPECONTROL = 0, //!< No additional details 1817 }; 1818 1819 enum _3D_COMMAND_OPCODE 1820 { 1821 _3D_COMMAND_OPCODE_PIPECONTROL = 2, //!< No additional details 1822 }; 1823 1824 enum COMMAND_SUBTYPE 1825 { 1826 COMMAND_SUBTYPE_GFXPIPE3D = 3, //!< No additional details 1827 }; 1828 1829 enum COMMAND_TYPE 1830 { 1831 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 1832 }; 1833 1834 //! \brief DEPTH_CACHE_FLUSH_ENABLE 1835 //! \details 1836 //! Setting this bit enables flushing (i.e. writing back the dirty lines to 1837 //! memory and invalidating the tags) of depth related caches. This bit 1838 //! applies to HiZ cache, Stencil cache and depth cache. 1839 enum DEPTH_CACHE_FLUSH_ENABLE 1840 { 1841 DEPTH_CACHE_FLUSH_ENABLE_FLUSHDISABLED = 0, //!< Depth relates caches (HiZ, Stencil and Depth) are NOT flushed. 1842 DEPTH_CACHE_FLUSH_ENABLE_FLUSHENABLED = 1, //!< Depth relates caches (HiZ, Stencil and Depth) are flushed. 1843 }; 1844 1845 //! \brief STALL_AT_PIXEL_SCOREBOARD 1846 //! \details 1847 //! Defines the behavior of PIPE_CONTROL command at the pixel scoreboard. 1848 enum STALL_AT_PIXEL_SCOREBOARD 1849 { 1850 STALL_AT_PIXEL_SCOREBOARD_DISABLE = 0, //!< Stall at the pixel scoreboard is disabled. 1851 STALL_AT_PIXEL_SCOREBOARD_ENABLE = 1, //!< Stall at the pixel scoreboard is enabled. 1852 }; 1853 1854 //! \brief RENDER_TARGET_CACHE_FLUSH_ENABLE 1855 //! \details 1856 //! <p>Setting this bit will force Render Cache to be flushed to memory 1857 //! prior to this synchronization point completing. This bit must be set for 1858 //! all write fence sync operations to assure that results from operations 1859 //! initiated prior to this command are visible in memory once software 1860 //! observes this synchronization.</p> 1861 enum RENDER_TARGET_CACHE_FLUSH_ENABLE 1862 { 1863 RENDER_TARGET_CACHE_FLUSH_ENABLE_DISABLEFLUSH = 0, //!< Render Target Cache is NOT flushed. 1864 RENDER_TARGET_CACHE_FLUSH_ENABLE_ENABLEFLUSH = 1, //!< Render Target Cache is flushed. 1865 }; 1866 1867 //! \brief DEPTH_STALL_ENABLE 1868 //! \details 1869 //! <p>This bit must be set when obtaining a "visible pixel" count to 1870 //! preclude the possible inclusion in the PS_DEPTH_COUNT value written to 1871 //! memory of some fraction of pixels from objects initiated after the 1872 //! PIPE_CONTROL command.</p> 1873 enum DEPTH_STALL_ENABLE 1874 { 1875 DEPTH_STALL_ENABLE_DISABLE = 0, //!< 3D pipeline will not stall subsequent primitives at the Depth Test stage. 1876 DEPTH_STALL_ENABLE_ENABLE = 1, //!< 3D pipeline will stall any subsequent primitives at the Depth Test stage until the Sync and Post-Sync operations complete. 1877 }; 1878 1879 //! \brief POST_SYNC_OPERATION 1880 //! \details 1881 //! This field specifies an optional action to be taken upon completion of 1882 //! the synchronization operation. 1883 enum POST_SYNC_OPERATION 1884 { 1885 POST_SYNC_OPERATION_NOWRITE = 0, //!< No write occurs as a result of this instruction. This can be used to implement a "trap" operation, etc. 1886 POST_SYNC_OPERATION_WRITEIMMEDIATEDATA = 1, //!< Write the QWord containing Immediate Data Low, High DWs to the Destination Address 1887 POST_SYNC_OPERATION_WRITEPSDEPTHCOUNT = 2, //!< Write the 64-bit PS_DEPTH_COUNT register to the Destination Address 1888 POST_SYNC_OPERATION_WRITETIMESTAMP = 3, //!< Write the 64-bit TIMESTAMP register(i.e. "Reported Timestamp Count" 0x2358 for render pipe) to the Destination Address. 1889 }; 1890 1891 //! \brief GLOBAL_SNAPSHOT_COUNT_RESET 1892 //! \details 1893 //! <p>This debug mode bit must not be exercised on any product.</p> 1894 enum GLOBAL_SNAPSHOT_COUNT_RESET 1895 { 1896 GLOBAL_SNAPSHOT_COUNT_RESET_DONTRESET = 0, //!< Do not reset the snapshot counts or Statistics Counters. 1897 GLOBAL_SNAPSHOT_COUNT_RESET_RESET = 1, //!< Reset the snapshot count in Gen4 for all the units and reset the Statistics Counters except as noted above. 1898 }; 1899 1900 //! \brief LRI_POST_SYNC_OPERATION 1901 //! \details 1902 //! This bit caues a post sync operation with an LRI (Load Register 1903 //! Immediate) operation. If this bit is set then the Post-Sync Operation 1904 //! field must be cleared. 1905 enum LRI_POST_SYNC_OPERATION 1906 { 1907 LRI_POST_SYNC_OPERATION_NOLRIOPERATION = 0, //!< No LRI operation occurs as a result of this instruction. The Post-Sync Operation field is valid and may be used to specify an operation. 1908 LRI_POST_SYNC_OPERATION_MMIOWRITEIMMEDIATEDATA = 1, //!< Write the DWord contained in Immediate Data Low (DW3) to the MMIO offset specifed in the Address field. 1909 }; 1910 1911 //! \brief DESTINATION_ADDRESS_TYPE 1912 //! \details 1913 //! Defines address space of Destination Address 1914 enum DESTINATION_ADDRESS_TYPE 1915 { 1916 DESTINATION_ADDRESS_TYPE_PPGTT = 0, //!< Use PPGTT address space for DW write 1917 DESTINATION_ADDRESS_TYPE_GGTT = 1, //!< Use GGTT address space for DW write 1918 }; 1919 1920 //! \brief TILE_CACHE_FLUSH_ENABLE 1921 //! \details 1922 //! <p>Setting this bit will force Tile Cache (contains both color and depth 1923 //! data) to be flushed to memory prior to this synchronization point 1924 //! completing. This bit must be set for all write fence sync operations to 1925 //! assure that results from operations initiated prior to this command are 1926 //! visible in memory once software observes this synchronization.</p> 1927 //! <p></p> 1928 enum TILE_CACHE_FLUSH_ENABLE 1929 { 1930 TILE_CACHE_FLUSH_ENABLE_UNNAMED0 = 0, //!< Tile Cache is not flushed. 1931 TILE_CACHE_FLUSH_ENABLE_UNNAMED1 = 1, //!< Tile cache is flushed. 1932 }; 1933 1934 //! \name Initializations 1935 1936 //! \brief Explicit member initialization function 1937 PIPE_CONTROL_CMD(); 1938 1939 static const size_t dwSize = 6; 1940 static const size_t byteSize = 24; 1941 }; 1942 1943 //! 1944 //! \brief MFX_WAIT 1945 //! \details 1946 //! This command can be considered the same as an MI_NOOP except that the 1947 //! command parser will not parse the next command until the following 1948 //! happens AVC or VC1 BSD mode: The command will stall the parser until 1949 //! completion of the BSD object 1950 //! IT, encoder, and MPEG2 BSD mode: The command will stall the parser 1951 //! until the object package is sent down the pipelineThis command should be 1952 //! used to ensure the preemption enable window occurs during the time the 1953 //! object command is being executed down the pipeline. 1954 //! 1955 //! 1956 struct MFX_WAIT_CMD 1957 { 1958 union 1959 { 1960 //!< DWORD 0 1961 struct 1962 { 1963 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 5) ; //!< DWORD_LENGTH 1964 uint32_t Reserved6 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1965 uint32_t MfxSyncControlFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< MFX Sync Control Flag 1966 uint32_t Reserved9 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 1967 uint32_t SubOpcode : __CODEGEN_BITFIELD(16, 26) ; //!< SUB_OPCODE 1968 uint32_t CommandSubtype : __CODEGEN_BITFIELD(27, 28) ; //!< COMMAND_SUBTYPE 1969 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1970 }; 1971 uint32_t Value; 1972 } DW0; 1973 1974 //! \name Local enumerations 1975 1976 enum SUB_OPCODE 1977 { 1978 SUB_OPCODE_MFXWAIT = 0, //!< No additional details 1979 }; 1980 1981 enum COMMAND_SUBTYPE 1982 { 1983 COMMAND_SUBTYPE_MFXSINGLEDW = 1, //!< No additional details 1984 }; 1985 1986 enum COMMAND_TYPE 1987 { 1988 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1989 }; 1990 1991 //! \name Initializations 1992 1993 //! \brief Explicit member initialization function 1994 MFX_WAIT_CMD(); 1995 1996 static const size_t dwSize = 1; 1997 static const size_t byteSize = 4; 1998 }; 1999 2000 //! 2001 //! \brief MEDIA_STATE_FLUSH 2002 //! \details 2003 //! This command updates the Message Gateway state. In particular, it 2004 //! updates the state for a selected Interface Descriptor. 2005 //! 2006 //! This command can be considered same as a MI_Flush except that only media 2007 //! parser will get flushed instead of the entire 3D/media render pipeline. 2008 //! The command should be programmed prior to new Media state, curbe and/or 2009 //! interface descriptor commands when switching to a new context or 2010 //! programming new state for the same context. With this command, pipelined 2011 //! state change is allowed for the media pipe. 2012 //! 2013 //! Be cautious when using this command when child_present flag in the media 2014 //! state is enabled. This is because that CURBE state as well as Interface 2015 //! Descriptor state are shared between root threads and child threads. 2016 //! Changing these states while child threads are generated on the fly may 2017 //! cause unexpected behavior. Combining with MI_ARB_ON/OFF command, it is 2018 //! possible to support interruptability with the following command sequence 2019 //! where interrupt may be allowed only when MI_ARB_ON_OFF is ON: 2020 //! 2021 //! <pre>MEDIA_STATE_FLUSH 2022 //! VFE_STATE VFE will hold CS if watermark isn't met 2023 //! MI_ARB_OFF There must be at least one VFE command before this one 2024 //! MEDIA_OBJECT ... MI_ARB_ON</pre> 2025 //! 2026 struct MEDIA_STATE_FLUSH_CMD 2027 { 2028 union 2029 { 2030 //!< DWORD 0 2031 struct 2032 { 2033 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 15) ; //!< DWORD_LENGTH 2034 uint32_t Subopcode : __CODEGEN_BITFIELD(16, 23) ; //!< SUBOPCODE 2035 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 2036 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2037 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2038 }; 2039 uint32_t Value; 2040 } DW0; 2041 union 2042 { 2043 //!< DWORD 1 2044 struct 2045 { 2046 uint32_t InterfaceDescriptorOffset : __CODEGEN_BITFIELD( 0, 5) ; //!< Interface Descriptor Offset 2047 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 6) ; //!< Reserved 2048 uint32_t FlushToGo : __CODEGEN_BITFIELD( 7, 7) ; //!< Flush to GO 2049 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 2050 }; 2051 uint32_t Value; 2052 } DW1; 2053 2054 //! \name Local enumerations 2055 2056 enum SUBOPCODE 2057 { 2058 SUBOPCODE_MEDIASTATEFLUSHSUBOP = 4, //!< No additional details 2059 }; 2060 2061 enum MEDIA_COMMAND_OPCODE 2062 { 2063 MEDIA_COMMAND_OPCODE_MEDIASTATEFLUSH = 0, //!< No additional details 2064 }; 2065 2066 enum PIPELINE 2067 { 2068 PIPELINE_MEDIA = 2, //!< No additional details 2069 }; 2070 2071 enum COMMAND_TYPE 2072 { 2073 COMMAND_TYPE_GFXPIPE = 3, //!< No additional details 2074 }; 2075 2076 //! \name Initializations 2077 2078 //! \brief Explicit member initialization function 2079 MEDIA_STATE_FLUSH_CMD(); 2080 2081 static const size_t dwSize = 2; 2082 static const size_t byteSize = 8; 2083 }; 2084 2085 }; 2086 2087 #pragma pack() 2088 2089 #endif // __MHW_MI_HWCMD_G11_X_H__