1 /*
2 * Copyright (c) 2016-2018, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_mi_g11_X.cpp
24 //! \brief Constructs MI commands on Gen11-based platforms
25 //! \details Each client facing function both creates a HW command and adds
26 //! that command to a command or batch buffer.
27 //!
28
29 #include "mhw_mi_g11_X.h"
30 #include "mhw_mi_hwcmd_g11_X.h"
31 #include "mhw_mmio_g11.h"
32
AddMiSemaphoreWaitCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_SEMAPHORE_WAIT_PARAMS params)33 MOS_STATUS MhwMiInterfaceG11::AddMiSemaphoreWaitCmd(
34 PMOS_COMMAND_BUFFER cmdBuffer,
35 PMHW_MI_SEMAPHORE_WAIT_PARAMS params)
36 {
37 MHW_FUNCTION_ENTER;
38
39 MHW_MI_CHK_NULL(cmdBuffer);
40 MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
41 MHW_MI_CHK_NULL(params);
42
43 mhw_mi_g11_X::MI_SEMAPHORE_WAIT_CMD *cmd =
44 (mhw_mi_g11_X::MI_SEMAPHORE_WAIT_CMD*)cmdBuffer->pCmdPtr;
45
46 MHW_MI_CHK_STATUS(MhwMiInterfaceGeneric<mhw_mi_g11_X>::AddMiSemaphoreWaitCmd(cmdBuffer, params));
47
48 cmd->DW0.RegisterPollMode = params->bRegisterPollMode;
49
50 return MOS_STATUS_SUCCESS;
51 }
52
AddMiBatchBufferStartCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer)53 MOS_STATUS MhwMiInterfaceG11::AddMiBatchBufferStartCmd(
54 PMOS_COMMAND_BUFFER cmdBuffer,
55 PMHW_BATCH_BUFFER batchBuffer)
56 {
57 MHW_FUNCTION_ENTER;
58
59 MHW_MI_CHK_NULL(m_osInterface);
60 MHW_MI_CHK_NULL(cmdBuffer);
61 MHW_MI_CHK_NULL(batchBuffer);
62
63 bool vcsEngineUsed =
64 MOS_VCS_ENGINE_USED(m_osInterface->pfnGetGpuContext(m_osInterface));
65
66 mhw_mi_g11_X::MI_BATCH_BUFFER_START_CMD cmd;
67 MHW_RESOURCE_PARAMS resourceParams;
68 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams));
69 resourceParams.presResource = &batchBuffer->OsResource;
70 resourceParams.dwOffset = batchBuffer->dwOffset;
71 resourceParams.pdwCmd = cmd.DW1_2.Value;
72 resourceParams.dwLocationInCmd = 1;
73 resourceParams.dwLsbNum = MHW_COMMON_MI_GENERAL_SHIFT;
74 resourceParams.HwCommandType = vcsEngineUsed ?
75 MOS_MI_BATCH_BUFFER_START : MOS_MI_BATCH_BUFFER_START_RCS;
76
77 MHW_MI_CHK_STATUS(AddResourceToCmd(
78 m_osInterface,
79 cmdBuffer,
80 &resourceParams));
81
82 // Set BB start
83 cmd.DW0.SecondLevelBatchBuffer = true;
84 cmd.DW0.AddressSpaceIndicator = !IsGlobalGttInUse();
85
86 // Send BB start command
87 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
88
89 return MOS_STATUS_SUCCESS;
90 }
91
AddMiConditionalBatchBufferEndCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS params)92 MOS_STATUS MhwMiInterfaceG11::AddMiConditionalBatchBufferEndCmd(
93 PMOS_COMMAND_BUFFER cmdBuffer,
94 PMHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS params)
95 {
96 MHW_FUNCTION_ENTER;
97
98 MHW_MI_CHK_NULL(m_osInterface);
99 MHW_MI_CHK_NULL(cmdBuffer);
100 MHW_MI_CHK_NULL(params);
101 MHW_MI_CHK_NULL(params->presSemaphoreBuffer);
102
103 // Case 1 - Batch buffer condition matches - If this is not present then conditional
104 // batch buffer will exit to ring with terminating CP.
105 // Case 2 - Batch buffer condition DOES NOT match - Although this will disable CP
106 // but after end of conditional batch buffer CP will be re-enabled.
107 MHW_MI_CHK_STATUS(m_cpInterface->AddEpilog(m_osInterface, cmdBuffer));
108
109 mhw_mi_g11_X::MI_CONDITIONAL_BATCH_BUFFER_END_CMD cmd;
110 cmd.DW0.UseGlobalGtt = IsGlobalGttInUse();
111 cmd.DW0.CompareSemaphore = 1; // CompareDataDword is always assumed to be set
112 cmd.DW0.CompareMaskMode = !params->bDisableCompareMask;
113 cmd.DW1.CompareDataDword = params->dwValue;
114
115 MHW_RESOURCE_PARAMS resourceParams;
116 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams));
117 resourceParams.presResource = params->presSemaphoreBuffer;
118 resourceParams.dwOffset = params->dwOffset;
119 resourceParams.pdwCmd = cmd.DW2_3.Value;
120 resourceParams.dwLocationInCmd = 2;
121 resourceParams.dwLsbNum = MHW_COMMON_MI_CONDITIONAL_BATCH_BUFFER_END_SHIFT;
122 resourceParams.HwCommandType = MOS_MI_CONDITIONAL_BATCH_BUFFER_END;
123
124 MHW_MI_CHK_STATUS(AddResourceToCmd(
125 m_osInterface,
126 cmdBuffer,
127 &resourceParams));
128
129 // Send Conditional Batch Buffer End command
130 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
131
132 //Re-enable CP for Case 2
133 MHW_MI_CHK_STATUS(m_cpInterface->AddProlog(m_osInterface, cmdBuffer));
134
135 return MOS_STATUS_SUCCESS;
136 }
137
AddMiStoreRegisterMemCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_STORE_REGISTER_MEM_PARAMS params)138 MOS_STATUS MhwMiInterfaceG11::AddMiStoreRegisterMemCmd(
139 PMOS_COMMAND_BUFFER cmdBuffer,
140 PMHW_MI_STORE_REGISTER_MEM_PARAMS params)
141 {
142 MHW_FUNCTION_ENTER;
143
144 MHW_MI_CHK_NULL(cmdBuffer);
145 MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
146 MHW_MI_CHK_NULL(params);
147
148 mhw_mi_g11_X::MI_STORE_REGISTER_MEM_CMD *cmd =
149 (mhw_mi_g11_X::MI_STORE_REGISTER_MEM_CMD*)cmdBuffer->pCmdPtr;
150
151 MHW_MI_CHK_STATUS(MhwMiInterfaceGeneric<mhw_mi_g11_X>::AddMiStoreRegisterMemCmd(cmdBuffer, params));
152
153 if (IsRelativeMMIO(params->dwRegister))
154 {
155 cmd->DW0.AddCsMmioStartOffset = 1;
156 cmd->DW1.RegisterAddress = params->dwRegister >> 2;
157 }
158
159 return MOS_STATUS_SUCCESS;
160 }
161
AddMiLoadRegisterMemCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_LOAD_REGISTER_MEM_PARAMS params)162 MOS_STATUS MhwMiInterfaceG11::AddMiLoadRegisterMemCmd(
163 PMOS_COMMAND_BUFFER cmdBuffer,
164 PMHW_MI_LOAD_REGISTER_MEM_PARAMS params)
165 {
166 MHW_FUNCTION_ENTER;
167
168 MHW_MI_CHK_NULL(cmdBuffer);
169 MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
170 MHW_MI_CHK_NULL(params);
171
172 mhw_mi_g11_X::MI_LOAD_REGISTER_MEM_CMD *cmd =
173 (mhw_mi_g11_X::MI_LOAD_REGISTER_MEM_CMD*)cmdBuffer->pCmdPtr;
174
175 MHW_MI_CHK_STATUS(MhwMiInterfaceGeneric<mhw_mi_g11_X>::AddMiLoadRegisterMemCmd(cmdBuffer, params));
176
177 if (IsRelativeMMIO(params->dwRegister))
178 {
179 cmd->DW0.AddCsMmioStartOffset = 1;
180 cmd->DW1.RegisterAddress = params->dwRegister >> 2;
181 }
182
183 return MOS_STATUS_SUCCESS;
184 }
185
AddMiLoadRegisterImmCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_LOAD_REGISTER_IMM_PARAMS params)186 MOS_STATUS MhwMiInterfaceG11::AddMiLoadRegisterImmCmd(
187 PMOS_COMMAND_BUFFER cmdBuffer,
188 PMHW_MI_LOAD_REGISTER_IMM_PARAMS params)
189 {
190 MHW_FUNCTION_ENTER;
191
192 MHW_MI_CHK_NULL(cmdBuffer);
193 MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
194 MHW_MI_CHK_NULL(params);
195
196 mhw_mi_g11_X::MI_LOAD_REGISTER_IMM_CMD *cmd =
197 (mhw_mi_g11_X::MI_LOAD_REGISTER_IMM_CMD*)cmdBuffer->pCmdPtr;
198
199 MHW_MI_CHK_STATUS(MhwMiInterfaceGeneric<mhw_mi_g11_X>::AddMiLoadRegisterImmCmd(cmdBuffer, params));
200
201 if (IsRelativeMMIO(params->dwRegister))
202 {
203 cmd->DW0.AddCsMmioStartOffset = 1;
204 cmd->DW1.RegisterOffset = params->dwRegister >> 2;
205 }
206
207 return MOS_STATUS_SUCCESS;
208 }
209
AddMiLoadRegisterRegCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_LOAD_REGISTER_REG_PARAMS params)210 MOS_STATUS MhwMiInterfaceG11::AddMiLoadRegisterRegCmd(
211 PMOS_COMMAND_BUFFER cmdBuffer,
212 PMHW_MI_LOAD_REGISTER_REG_PARAMS params)
213 {
214 MHW_FUNCTION_ENTER;
215
216 MHW_MI_CHK_NULL(cmdBuffer);
217 MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
218 MHW_MI_CHK_NULL(params);
219
220 mhw_mi_g11_X::MI_LOAD_REGISTER_REG_CMD *cmd =
221 (mhw_mi_g11_X::MI_LOAD_REGISTER_REG_CMD*)cmdBuffer->pCmdPtr;
222
223 MHW_MI_CHK_STATUS(MhwMiInterfaceGeneric<mhw_mi_g11_X>::AddMiLoadRegisterRegCmd(cmdBuffer, params));
224
225 if (IsRelativeMMIO(params->dwSrcRegister))
226 {
227 cmd->DW0.AddCsMmioStartOffsetSource = 1;
228 cmd->DW1.SourceRegisterAddress = params->dwSrcRegister >> 2;
229 }
230 if (IsRelativeMMIO(params->dwDstRegister))
231 {
232 cmd->DW0.AddCsMmioStartOffsetDestination = 1;
233 cmd->DW2.DestinationRegisterAddress = params->dwDstRegister >> 2;
234 }
235
236 return MOS_STATUS_SUCCESS;
237 }
238
SetWatchdogTimerThreshold(uint32_t frameWidth,uint32_t frameHeight,bool isEncoder)239 MOS_STATUS MhwMiInterfaceG11::SetWatchdogTimerThreshold(uint32_t frameWidth, uint32_t frameHeight, bool isEncoder)
240 {
241 MHW_FUNCTION_ENTER;
242
243 if (m_osInterface->bMediaReset == false ||
244 m_osInterface->umdMediaResetEnable == false)
245 {
246 return MOS_STATUS_SUCCESS;
247 }
248
249 if (isEncoder)
250 {
251 if ((frameWidth * frameHeight) >= (7680 * 4320))
252 {
253 MediaResetParam.watchdogCountThreshold = MHW_MI_ENCODER_16K_WATCHDOG_THRESHOLD_IN_MS;
254 }
255 else if ((frameWidth * frameHeight) >= (3840 * 2160))
256 {
257 MediaResetParam.watchdogCountThreshold = MHW_MI_ENCODER_8K_WATCHDOG_THRESHOLD_IN_MS;
258 }
259 else if ((frameWidth * frameHeight) >= (1920 * 1080))
260 {
261 MediaResetParam.watchdogCountThreshold = MHW_MI_ENCODER_4K_WATCHDOG_THRESHOLD_IN_MS;
262 }
263 else
264 {
265 MediaResetParam.watchdogCountThreshold = MHW_MI_ENCODER_FHD_WATCHDOG_THRESHOLD_IN_MS;
266 }
267 }
268 else
269 {
270 if ((frameWidth * frameHeight) >= (7680 * 4320))
271 {
272 MediaResetParam.watchdogCountThreshold = MHW_MI_DECODER_16K_WATCHDOG_THRESHOLD_IN_MS;
273 }
274 else
275 {
276 // 60ms should be enough for decoder with resolution smaller than 8k
277 MediaResetParam.watchdogCountThreshold = MHW_MI_DEFAULT_WATCHDOG_THRESHOLD_IN_MS;
278 }
279 }
280
281 GetWatchdogThreshold(m_osInterface);
282
283 return MOS_STATUS_SUCCESS;
284 }
285
SetWatchdogTimerRegisterOffset(MOS_GPU_CONTEXT gpuContext)286 MOS_STATUS MhwMiInterfaceG11::SetWatchdogTimerRegisterOffset(
287 MOS_GPU_CONTEXT gpuContext)
288 {
289 MHW_FUNCTION_ENTER;
290
291 switch (gpuContext)
292 {
293 // RCS
294 case MOS_GPU_CONTEXT_RENDER:
295 case MOS_GPU_CONTEXT_RENDER2:
296 case MOS_GPU_CONTEXT_RENDER3:
297 case MOS_GPU_CONTEXT_RENDER4:
298 MediaResetParam.watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_RCS_G11;
299 MediaResetParam.watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_RCS_G11;
300 break;
301 // VCS0
302 case MOS_GPU_CONTEXT_VIDEO:
303 case MOS_GPU_CONTEXT_VIDEO2:
304 case MOS_GPU_CONTEXT_VIDEO3:
305 case MOS_GPU_CONTEXT_VIDEO4:
306 case MOS_GPU_CONTEXT_VIDEO5:
307 case MOS_GPU_CONTEXT_VIDEO6:
308 case MOS_GPU_CONTEXT_VIDEO7:
309 MediaResetParam.watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_VCS0_G11;
310 MediaResetParam.watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_VCS0_G11;
311 break;
312 // VCS1
313 case MOS_GPU_CONTEXT_VDBOX2_VIDEO:
314 case MOS_GPU_CONTEXT_VDBOX2_VIDEO2:
315 case MOS_GPU_CONTEXT_VDBOX2_VIDEO3:
316 MediaResetParam.watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_VCS1_G11;
317 MediaResetParam.watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_VCS1_G11;
318 break;
319 // VECS
320 case MOS_GPU_CONTEXT_VEBOX:
321 MediaResetParam.watchdogCountCtrlOffset = WATCHDOG_COUNT_CTRL_OFFSET_VECS_G11;
322 MediaResetParam.watchdogCountThresholdOffset = WATCHDOG_COUNT_THRESTHOLD_OFFSET_VECS_G11;
323 break;
324 // Default
325 default:
326 break;
327 }
328
329 return MOS_STATUS_SUCCESS;
330 }
331
AddWatchdogTimerStartCmd(PMOS_COMMAND_BUFFER cmdBuffer)332 MOS_STATUS MhwMiInterfaceG11::AddWatchdogTimerStartCmd(
333 PMOS_COMMAND_BUFFER cmdBuffer)
334 {
335 MOS_GPU_CONTEXT gpuContext;
336
337 MHW_FUNCTION_ENTER;
338
339 if (m_osInterface->bMediaReset == false ||
340 m_osInterface->umdMediaResetEnable == false)
341 {
342 return MOS_STATUS_SUCCESS;
343 }
344
345 MHW_MI_CHK_NULL(cmdBuffer);
346
347 // Set Watchdog Timer Register Offset
348 gpuContext = m_osInterface->pfnGetGpuContext(m_osInterface);
349 MHW_MI_CHK_STATUS(SetWatchdogTimerRegisterOffset(gpuContext));
350
351 // Send Stop before Start is to help recover from incorrect wdt state if previous submission
352 // cause hang and not have a chance to execute the stop cmd in the end of batch buffer.
353 MHW_MI_CHK_STATUS(AddWatchdogTimerStopCmd(cmdBuffer));
354
355 //Configure Watchdog timer Threshold
356 MHW_MI_LOAD_REGISTER_IMM_PARAMS registerImmParams;
357 MOS_ZeroMemory(®isterImmParams, sizeof(registerImmParams));
358 registerImmParams.dwData = MHW_MI_WATCHDOG_COUNTS_PER_MILLISECOND * MediaResetParam.watchdogCountThreshold *
359 (m_osInterface->bSimIsActive ? 2 : 1);
360 registerImmParams.dwRegister = MediaResetParam.watchdogCountThresholdOffset;
361 MHW_MI_CHK_STATUS(AddMiLoadRegisterImmCmd(
362 cmdBuffer,
363 ®isterImmParams));
364
365 MHW_VERBOSEMESSAGE("MediaReset Threshold is %d", MediaResetParam.watchdogCountThreshold * (m_osInterface->bSimIsActive ? 2 : 1));
366
367 //Start Watchdog Timer
368 registerImmParams.dwData = MHW_MI_WATCHDOG_ENABLE_COUNTER;
369 registerImmParams.dwRegister = MediaResetParam.watchdogCountCtrlOffset;
370 MHW_MI_CHK_STATUS(AddMiLoadRegisterImmCmd(
371 cmdBuffer,
372 ®isterImmParams));
373
374 return MOS_STATUS_SUCCESS;
375 }
376
AddWatchdogTimerStopCmd(PMOS_COMMAND_BUFFER cmdBuffer)377 MOS_STATUS MhwMiInterfaceG11::AddWatchdogTimerStopCmd(
378 PMOS_COMMAND_BUFFER cmdBuffer)
379 {
380 MOS_GPU_CONTEXT gpuContext;
381
382 MHW_FUNCTION_ENTER;
383
384 if (m_osInterface->bMediaReset == false ||
385 m_osInterface->umdMediaResetEnable == false)
386 {
387 return MOS_STATUS_SUCCESS;
388 }
389
390 MHW_MI_CHK_NULL(cmdBuffer);
391
392 // Set Watchdog Timer Register Offset
393 gpuContext = m_osInterface->pfnGetGpuContext(m_osInterface);
394 MHW_MI_CHK_STATUS(SetWatchdogTimerRegisterOffset(gpuContext));
395
396 //Stop Watchdog Timer
397 MHW_MI_LOAD_REGISTER_IMM_PARAMS registerImmParams;
398 MOS_ZeroMemory(®isterImmParams, sizeof(registerImmParams));
399 registerImmParams.dwData = MHW_MI_WATCHDOG_DISABLE_COUNTER;
400 registerImmParams.dwRegister = MediaResetParam.watchdogCountCtrlOffset;
401 MHW_MI_CHK_STATUS(AddMiLoadRegisterImmCmd(
402 cmdBuffer,
403 ®isterImmParams));
404
405 return MOS_STATUS_SUCCESS;
406 }
407
InitMmioRegisters()408 void MhwMiInterfaceG11::InitMmioRegisters()
409 {
410 MHW_MI_MMIOREGISTERS *mmioRegisters = &m_mmioRegisters;
411
412 mmioRegisters->generalPurposeRegister0LoOffset = GP_REGISTER0_LO_OFFSET_G11;
413 mmioRegisters->generalPurposeRegister0HiOffset = GP_REGISTER0_HI_OFFSET_G11;
414 mmioRegisters->generalPurposeRegister4LoOffset = GP_REGISTER4_LO_OFFSET_G11;
415 mmioRegisters->generalPurposeRegister4HiOffset = GP_REGISTER4_HI_OFFSET_G11;
416 mmioRegisters->generalPurposeRegister11LoOffset = GP_REGISTER11_LO_OFFSET_G11;
417 mmioRegisters->generalPurposeRegister11HiOffset = GP_REGISTER11_HI_OFFSET_G11;
418 mmioRegisters->generalPurposeRegister12LoOffset = GP_REGISTER12_LO_OFFSET_G11;
419 mmioRegisters->generalPurposeRegister12HiOffset = GP_REGISTER12_HI_OFFSET_G11;
420 }
421
AddMediaStateFlush(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer,PMHW_MEDIA_STATE_FLUSH_PARAM params)422 MOS_STATUS MhwMiInterfaceG11::AddMediaStateFlush(
423 PMOS_COMMAND_BUFFER cmdBuffer,
424 PMHW_BATCH_BUFFER batchBuffer,
425 PMHW_MEDIA_STATE_FLUSH_PARAM params)
426 {
427 MHW_MI_CHK_STATUS(MhwMiInterfaceGeneric<mhw_mi_g11_X>::AddMediaStateFlush(cmdBuffer, batchBuffer, params));
428
429 mhw_mi_g11_X::MEDIA_STATE_FLUSH_CMD cmd;
430
431 if (params != nullptr)
432 {
433 cmd.DW1.FlushToGo = params->bFlushToGo;
434 cmd.DW1.InterfaceDescriptorOffset = params->ui8InterfaceDescriptorOffset;
435 }
436
437 MHW_MI_CHK_STATUS(Mhw_AddCommandCmdOrBB(m_osInterface, cmdBuffer, batchBuffer, &cmd, cmd.byteSize));
438
439 #if (_DEBUG || _RELEASE_INTERNAL)
440 if (batchBuffer)
441 {
442 batchBuffer->iLastCurrent = batchBuffer->iCurrent;
443 }
444 #endif
445
446 return MOS_STATUS_SUCCESS;
447 }
448
SkipMiBatchBufferEndBb(PMHW_BATCH_BUFFER batchBuffer)449 MOS_STATUS MhwMiInterfaceG11::SkipMiBatchBufferEndBb(
450 PMHW_BATCH_BUFFER batchBuffer)
451 {
452 MHW_FUNCTION_ENTER;
453
454 MHW_MI_CHK_STATUS(MhwMiInterfaceGeneric<mhw_mi_g11_X>::SkipMiBatchBufferEndBb(batchBuffer));
455
456 auto waTable = m_osInterface->pfnGetWaTable(m_osInterface);
457 MHW_MI_CHK_NULL(waTable);
458
459 // This WA does not apply for video or other engines, render requirement only
460 bool isRender =
461 MOS_RCS_ENGINE_USED(m_osInterface->pfnGetGpuContext(m_osInterface));
462
463 if (isRender && (MEDIA_IS_WA(waTable, WaMSFWithNoWatermarkTSGHang) ||
464 MEDIA_IS_WA(waTable, WaAddMediaStateFlushCmd)))
465 {
466 mhw_mi_g11_X::MEDIA_STATE_FLUSH_CMD FlushCmd;
467 MHW_MI_CHK_STATUS(Mhw_AddCommandBB(
468 batchBuffer,
469 nullptr,
470 FlushCmd.byteSize));
471 }
472
473 mhw_mi_g11_X::MI_BATCH_BUFFER_END_CMD cmd;
474 MHW_MI_CHK_STATUS(Mhw_AddCommandBB(
475 batchBuffer,
476 nullptr,
477 cmd.byteSize));
478
479 return MOS_STATUS_SUCCESS;
480 }
481
AddMiFlushDwCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_MI_FLUSH_DW_PARAMS params)482 MOS_STATUS MhwMiInterfaceG11::AddMiFlushDwCmd(
483 PMOS_COMMAND_BUFFER cmdBuffer,
484 PMHW_MI_FLUSH_DW_PARAMS params)
485 {
486 MHW_FUNCTION_ENTER;
487
488 MHW_MI_CHK_NULL(m_osInterface);
489 MHW_MI_CHK_STATUS(MhwMiInterfaceGeneric<mhw_mi_g11_X>::AddMiFlushDwCmd(cmdBuffer, params));
490
491 mhw_mi_g11_X::MI_FLUSH_DW_CMD cmd;
492
493 // set the protection bit based on CP status
494 MHW_MI_CHK_STATUS(m_cpInterface->SetProtectionSettingsForMiFlushDw(m_osInterface, &cmd));
495
496 cmd.DW0.VideoPipelineCacheInvalidate = params->bVideoPipelineCacheInvalidate;
497 cmd.DW0.PostSyncOperation = cmd.POST_SYNC_OPERATION_NOWRITE;
498 cmd.DW3_4.Value[0] = params->dwDataDW1;
499
500 if (params->pOsResource)
501 {
502 cmd.DW0.PostSyncOperation = cmd.POST_SYNC_OPERATION_WRITEIMMEDIATEDATA;
503 cmd.DW1_2.DestinationAddressType = UseGlobalGtt.m_vcs;
504
505 MHW_RESOURCE_PARAMS resourceParams;
506 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams));
507 resourceParams.presResource = params->pOsResource;
508 resourceParams.dwOffset = params->dwResourceOffset;
509 resourceParams.pdwCmd = cmd.DW1_2.Value;
510 resourceParams.dwLocationInCmd = 1;
511 resourceParams.dwLsbNum = MHW_COMMON_MI_FLUSH_DW_SHIFT;
512 resourceParams.HwCommandType = MOS_MI_FLUSH_DW;
513 resourceParams.bIsWritable = true;
514
515 MHW_MI_CHK_STATUS(AddResourceToCmd(
516 m_osInterface,
517 cmdBuffer,
518 &resourceParams));
519 }
520
521 if (params->postSyncOperation)
522 {
523 cmd.DW0.PostSyncOperation = params->postSyncOperation;
524 }
525
526 if (params->dwDataDW2 || params->bQWordEnable)
527 {
528 cmd.DW3_4.Value[1] = params->dwDataDW2;
529 }
530 else
531 {
532 cmd.DW0.DwordLength--;
533 }
534
535 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
536
537 return MOS_STATUS_SUCCESS;
538 }