1 /* 2 * Copyright (c) 2020, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_mi_cmdpar.h 24 //! \brief MHW command parameters 25 //! \details 26 //! 27 28 #ifndef __MHW_MI_CMDPAR_H__ 29 #define __MHW_MI_CMDPAR_H__ 30 31 #include "mhw_cmdpar.h" 32 #include "mhw_state_heap.h" 33 #include "mhw_mmio_common.h" 34 35 namespace mhw 36 { 37 namespace mi 38 { 39 40 enum MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION 41 { 42 MHW_MI_SAD_GREATER_THAN_SDD = 0, 43 MHW_MI_SAD_GREATER_THAN_OR_EQUAL_SDD = 1, 44 MHW_MI_SAD_LESS_THAN_SDD = 2, 45 MHW_MI_SAD_LESS_THAN_OR_EQUAL_SDD = 3, 46 MHW_MI_SAD_EQUAL_SDD = 4, 47 MHW_MI_SAD_NOT_EQUAL_SDD = 5, 48 }; 49 50 enum MHW_COMMON_MI_ATOMIC_OPCODE 51 { 52 MHW_MI_ATOMIC_NONE = 0, 53 MHW_MI_ATOMIC_AND = 1, 54 MHW_MI_ATOMIC_OR = 2, 55 MHW_MI_ATOMIC_XOR = 3, 56 MHW_MI_ATOMIC_MOVE = 4, 57 MHW_MI_ATOMIC_INC = 5, 58 MHW_MI_ATOMIC_DEC = 6, 59 MHW_MI_ATOMIC_ADD = 7, 60 MHW_MI_ATOMIC_SUB = 8, 61 MHW_MI_ATOMIC_RSUB = 9, 62 MHW_MI_ATOMIC_IMAX = 10, 63 MHW_MI_ATOMIC_IMIN = 11, 64 MHW_MI_ATOMIC_UMAX = 12, 65 MHW_MI_ATOMIC_UMIN = 13, 66 MHW_MI_ATOMIC_CMP = 14, 67 MHW_MI_ATOMIC_MAX = 15, 68 69 MHW_MI_ATOMIC_DWORD = 0, 70 MHW_MI_ATOMIC_QWORD = 0x20, 71 MHW_MI_ATOMIC_OCTWORD = 0x40, 72 }; 73 74 enum MHW_MI_POST_SYNC_OPERATION 75 { 76 MHW_FLUSH_NOWRITE = 0, 77 MHW_FLUSH_WRITE_IMMEDIATE_DATA = 1, 78 MHW_FLUSH_WRITE_TIMESTAMP_REG = 3 79 }; 80 81 enum MHW_COMMON_MI_ADDRESS_SHIFT 82 { 83 MHW_COMMON_MI_GENERAL_SHIFT = 2, 84 MHW_COMMON_MI_PIPE_CONTROL_SHIFT = 3, 85 MHW_COMMON_MI_FLUSH_DW_SHIFT = 3, 86 MHW_COMMON_MI_STORE_DATA_DW_SHIFT = 2, //when write DW to memory, algin with 4 bytes. 87 MHW_COMMON_MI_STORE_DATA_QW_SHIFT = 3, //when write QW to memory, algin with 8 bytes 88 MHW_COMMON_MI_CONDITIONAL_BATCH_BUFFER_END_SHIFT = 3, 89 }; 90 91 enum MHW_FLUSH_OPERATION 92 { 93 MHW_FLUSH_NONE = 0, // No flush 94 MHW_FLUSH_WRITE_CACHE, // Flush write cache 95 MHW_FLUSH_READ_CACHE, // Flush read cache 96 MHW_FLUSH_CUSTOM // Flush with custom parameters 97 }; 98 99 enum MHW_MMIO_REGISTER_OPCODE 100 { 101 MHW_MMIO_RCS_AUX_TABLE_NONE = 0, 102 MHW_MMIO_RCS_AUX_TABLE_BASE_LOW = 1, 103 MHW_MMIO_RCS_AUX_TABLE_BASE_HIGH = 2, 104 MHW_MMIO_RCS_AUX_TABLE_INVALIDATE = 3, 105 MHW_MMIO_VD0_AUX_TABLE_BASE_LOW = 4, 106 MHW_MMIO_VD0_AUX_TABLE_BASE_HIGH = 5, 107 MHW_MMIO_VD0_AUX_TABLE_INVALIDATE = 6, 108 MHW_MMIO_VD1_AUX_TABLE_BASE_LOW = 7, 109 MHW_MMIO_VD1_AUX_TABLE_BASE_HIGH = 8, 110 MHW_MMIO_VD1_AUX_TABLE_INVALIDATE = 9, 111 MHW_MMIO_VD2_AUX_TABLE_BASE_LOW = 10, 112 MHW_MMIO_VD2_AUX_TABLE_BASE_HIGH = 11, 113 MHW_MMIO_VD2_AUX_TABLE_INVALIDATE = 12, 114 MHW_MMIO_VD3_AUX_TABLE_BASE_LOW = 13, 115 MHW_MMIO_VD3_AUX_TABLE_BASE_HIGH = 14, 116 MHW_MMIO_VD3_AUX_TABLE_INVALIDATE = 15, 117 MHW_MMIO_VE0_AUX_TABLE_BASE_LOW = 16, 118 MHW_MMIO_VE0_AUX_TABLE_BASE_HIGH = 17, 119 MHW_MMIO_VE0_AUX_TABLE_INVALIDATE = 18, 120 MHW_MMIO_VE1_AUX_TABLE_BASE_LOW = 19, 121 MHW_MMIO_VE1_AUX_TABLE_BASE_HIGH = 20, 122 MHW_MMIO_VE1_AUX_TABLE_INVALIDATE = 21, 123 MHW_MMIO_CCS0_AUX_TABLE_BASE_LOW = 22, 124 MHW_MMIO_CCS0_AUX_TABLE_BASE_HIGH = 23, 125 MHW_MMIO_BLT_AUX_TABLE_BASE_LOW = 24, 126 MHW_MMIO_BLT_AUX_TABLE_BASE_HIGH = 25, 127 MHW_MMIO_CCS0_AUX_TABLE_INVALIDATE = 26, 128 }; 129 130 struct MHW_MI_ALU_PARAMS 131 { 132 // DW 0 133 union 134 { 135 struct 136 { 137 uint32_t Operand2 : MOS_BITFIELD_RANGE(0, 9); // Operand-2 138 uint32_t Operand1 : MOS_BITFIELD_RANGE(10, 19); // Operand-1 139 uint32_t AluOpcode : MOS_BITFIELD_RANGE(20, 31); // ALU OPCODE 140 }; 141 uint32_t Value; 142 }; 143 }; 144 145 struct MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS 146 { 147 PMOS_RESOURCE presSemaphoreBuffer = nullptr; 148 uint32_t dwOffset = 0; 149 uint32_t dwValue = 0; 150 bool bDisableCompareMask = false; 151 uint32_t dwParamsType = 0; //reserved 152 }; 153 154 struct MHW_MI_ENHANCED_CONDITIONAL_BATCH_BUFFER_END_PARAMS : public MHW_MI_CONDITIONAL_BATCH_BUFFER_END_PARAMS 155 { 156 bool enableEndCurrentBatchBuffLevel = false; 157 uint32_t compareOperation = 0; 158 enum PARAMS_TYPE 159 { 160 ENHANCED_PARAMS = 1 161 }; 162 }; 163 _MHW_PAR_T(MI_SEMAPHORE_WAIT)164 struct _MHW_PAR_T(MI_SEMAPHORE_WAIT) 165 { 166 PMOS_RESOURCE presSemaphoreMem = nullptr; // Semaphore memory Resource 167 uint32_t dwResourceOffset = 0; 168 bool bRegisterPollMode = false; 169 bool bPollingWaitMode = false; 170 uint32_t dwCompareOperation = 0; 171 uint32_t dwSemaphoreData = 0; 172 MHW_COMMON_MI_SEMAPHORE_COMPARE_OPERATION CompareOperation = {}; 173 }; 174 _MHW_PAR_T(PIPE_CONTROL)175 struct _MHW_PAR_T(PIPE_CONTROL) 176 { 177 PMOS_RESOURCE presDest = nullptr; 178 uint32_t dwResourceOffset = 0; 179 uint32_t dwDataDW1 = 0; 180 uint32_t dwDataDW2 = 0; 181 uint32_t dwFlushMode = 0; 182 uint32_t dwPostSyncOp = 0; 183 bool bDisableCSStall = false; 184 bool bInvalidateStateCache = false; 185 bool bInvalidateConstantCache = false; 186 bool bInvalidateVFECache = false; 187 bool bInvalidateInstructionCache = false; 188 bool bFlushRenderTargetCache = false; 189 bool bTlbInvalidate = false; 190 bool bInvalidateTextureCache = false; 191 bool bGenericMediaStateClear = false; 192 bool bIndirectStatePointersDisable = false; 193 bool bUnTypedDataPortCacheFlush = false; 194 bool bHdcPipelineFlush = false; 195 bool bKernelFenceEnabled = false; 196 bool bPPCFlush = false; 197 }; 198 _MHW_PAR_T(MI_BATCH_BUFFER_START)199 struct _MHW_PAR_T(MI_BATCH_BUFFER_START) 200 { 201 PMOS_RESOURCE presResource = nullptr; 202 bool secondLevelBatchBuffer = true; 203 }; 204 _MHW_PAR_T(MI_CONDITIONAL_BATCH_BUFFER_END)205 struct _MHW_PAR_T(MI_CONDITIONAL_BATCH_BUFFER_END) 206 { 207 PMOS_RESOURCE presSemaphoreBuffer = nullptr; 208 uint32_t dwOffset = 0; 209 uint32_t dwValue = 0; 210 bool bDisableCompareMask = false; 211 uint32_t dwParamsType = 0; //reserved 212 bool enableEndCurrentBatchBuffLevel = false; 213 uint32_t compareOperation = 0; 214 }; 215 _MHW_PAR_T(MI_SET_PREDICATE)216 struct _MHW_PAR_T(MI_SET_PREDICATE) 217 { 218 uint32_t PredicateEnable = 0; // Debug Counter Control 219 }; 220 _MHW_PAR_T(MI_STORE_REGISTER_MEM)221 struct _MHW_PAR_T(MI_STORE_REGISTER_MEM) 222 { 223 PMOS_RESOURCE presStoreBuffer = nullptr; 224 uint32_t dwOffset = 0; 225 uint32_t dwRegister = 0; 226 uint32_t dwOption = 0; 227 }; 228 _MHW_PAR_T(MI_LOAD_REGISTER_MEM)229 struct _MHW_PAR_T(MI_LOAD_REGISTER_MEM) 230 { 231 PMOS_RESOURCE presStoreBuffer = nullptr; 232 uint32_t dwOffset = 0; 233 uint32_t dwRegister = 0; 234 uint32_t dwOption = 0; 235 }; 236 _MHW_PAR_T(MI_LOAD_REGISTER_IMM)237 struct _MHW_PAR_T(MI_LOAD_REGISTER_IMM) 238 { 239 uint32_t dwRegister = 0; 240 uint32_t dwData = 0; 241 }; 242 _MHW_PAR_T(MI_LOAD_REGISTER_REG)243 struct _MHW_PAR_T(MI_LOAD_REGISTER_REG) 244 { 245 uint32_t dwSrcRegister = 0; 246 uint32_t dwDstRegister = 0; 247 }; 248 _MHW_PAR_T(MI_FORCE_WAKEUP)249 struct _MHW_PAR_T(MI_FORCE_WAKEUP) 250 { 251 bool bForceMediaSlice0Awake = false; //!< Force Media-Slice0 Awake 252 bool bForceRenderAwake = false; //!< Force Render Awake 253 bool bForceMediaSlice1Awake = false; //!< Force Media-Slice1 Awake 254 bool bForceMediaSlice2Awake = false; //!< Force Media-Slice2 Awake 255 bool bForceMediaSlice3Awake = false; //!< Force Media-Slice3 Awake 256 bool bHEVCPowerWellControl = false; //!< HEVC Power Well Control 257 bool bMFXPowerWellControl = false; //!< MFX Power Well Control 258 bool bForceMediaSlice0AwakeMask = false; //!< Force Media-Slice0 Awake Mask 259 bool bForceRenderAwakeMask = false; //!< Force Render Awake Mask 260 bool bForceMediaSlice1AwakeMask = false; //!< Force Media-Slice1 Awake Mask 261 bool bForceMediaSlice2AwakeMask = false; //!< Force Media-Slice2 Awake Mask 262 bool bForceMediaSlice3AwakeMask = false; //!< Force Media-Slice3 Awake Mask 263 bool bHEVCPowerWellControlMask = false; //!< HEVC Power Well Control Mask 264 bool bMFXPowerWellControlMask = false; //!< MFX Power Well Control Mask 265 }; 266 _MHW_PAR_T(MEDIA_STATE_FLUSH)267 struct _MHW_PAR_T(MEDIA_STATE_FLUSH) 268 { 269 bool bFlushToGo = false; 270 uint8_t ui8InterfaceDescriptorOffset = 0; 271 }; 272 _MHW_PAR_T(MI_FLUSH_DW)273 struct _MHW_PAR_T(MI_FLUSH_DW) 274 { 275 PMOS_RESOURCE pOsResource = nullptr; // Target OS Resource 276 uint32_t dwResourceOffset = 0; 277 uint32_t dwDataDW1 = 0; // Value to Write 278 uint32_t dwDataDW2 = 0; 279 bool bVideoPipelineCacheInvalidate = false; 280 uint32_t postSyncOperation = 0; 281 uint32_t bQWordEnable = 0; 282 bool bEnablePPCFlush = false; 283 }; 284 _MHW_PAR_T(VD_CONTROL_STATE)285 struct _MHW_PAR_T(VD_CONTROL_STATE) 286 { 287 bool vdencEnabled = false; 288 bool avpEnabled = false; 289 bool initialization = false; 290 bool vdencInitialization = false; 291 bool scalableModePipeLock = false; 292 bool scalableModePipeUnlock = false; 293 bool memoryImplicitFlush = false; 294 }; 295 _MHW_PAR_T(MI_BATCH_BUFFER_END)296 struct _MHW_PAR_T(MI_BATCH_BUFFER_END) 297 { 298 MOS_RESOURCE OsResource = {}; 299 int32_t iRemaining = 0; //!< Remaining space in the BB 300 int32_t iSize = 0; //!< Command buffer size 301 uint32_t count = 0; //!< Actual batch count in this resource. If larger than 1, multiple buffer has equal size and resource size count * size. 302 int32_t iCurrent = 0; //!< Current offset in CB 303 bool bLocked = false; //!< True if locked in memory (pData must be valid) 304 uint8_t *pData = nullptr; //!< Pointer to BB data 305 #if (_DEBUG || _RELEASE_INTERNAL) 306 int32_t iLastCurrent = 0; //!< Save offset in CB (for debug plug-in/out) 307 #endif 308 309 // User defined 310 bool bSecondLevel = false; //!< REMOVE REMOVE 311 uint32_t dwOffset = 0; //!< Offset to the data in the OS resource 312 313 // Batch Buffer synchronization logic 314 bool bBusy = false; //!< Busy flag (clear when Sync Tag is reached) 315 uint32_t dwCmdBufId = 0; //!< Command Buffer ID for the workload 316 PMHW_BATCH_BUFFER pNext = nullptr; //!< Next BB in the sync list 317 PMHW_BATCH_BUFFER pPrev = nullptr; //!< Prev BB in the sync list 318 319 // Batch Buffer Client Private Data 320 uint32_t dwSyncTag = 0; 321 bool bMatch = false; 322 int32_t iPrivateType = 0; //!< Indicates the BB client 323 int32_t iPrivateSize = 0; //!< Size of the current render args 324 void *pPrivateData = nullptr; //!< Pointer to private BB data 325 }; 326 _MHW_PAR_T(MI_NOOP)327 struct _MHW_PAR_T(MI_NOOP) 328 { 329 }; 330 _MHW_PAR_T(MI_ATOMIC)331 struct _MHW_PAR_T(MI_ATOMIC) 332 { 333 PMOS_RESOURCE pOsResource = nullptr; // Target OS Resource 334 uint32_t dwResourceOffset = 0; 335 bool bReturnData = false; 336 bool bInlineData = false; 337 uint32_t dwOperand1Data[4] = {}; // Values to Write 338 uint32_t dwOperand2Data[4] = {}; // Values to Write 339 uint32_t dwDataSize = 0; 340 MHW_COMMON_MI_ATOMIC_OPCODE Operation = {}; 341 }; 342 _MHW_PAR_T(MI_STORE_DATA_IMM)343 struct _MHW_PAR_T(MI_STORE_DATA_IMM) 344 { 345 PMOS_RESOURCE pOsResource = nullptr; // Target OS Resource 346 uint32_t dwResourceOffset = 0; 347 uint32_t dwValue = 0; // Value to Write 348 }; 349 _MHW_PAR_T(MI_MATH)350 struct _MHW_PAR_T(MI_MATH) 351 { 352 MHW_MI_ALU_PARAMS *pAluPayload = nullptr; 353 uint32_t dwNumAluParams = 0; 354 }; 355 _MHW_PAR_T(MI_COPY_MEM_MEM)356 struct _MHW_PAR_T(MI_COPY_MEM_MEM) 357 { 358 PMOS_RESOURCE presSrc = nullptr; 359 uint32_t dwSrcOffset = 0; 360 PMOS_RESOURCE presDst = nullptr; 361 uint32_t dwDstOffset = 0; 362 }; 363 _MHW_PAR_T(MFX_WAIT)364 struct _MHW_PAR_T(MFX_WAIT) 365 { 366 bool iStallVdboxPipeline = false; 367 }; 368 369 370 } // namespace mi 371 } // namespace mhw 372 373 #endif // __MHW_MI_CMDPAR_H__ 374