1 /*
2 * Copyright (c) 2018-2023, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 //!
24 //! \file media_sku_wa_g12.cpp
25 //!
26
27 #include "igfxfmid.h"
28 #include "linux_system_info.h"
29 #include "skuwa_factory.h"
30 #include "linux_skuwa_debug.h"
31 #include "linux_media_skuwa.h"
32 #include "mos_utilities.h"
33 #include "mos_os_specific.h"
34 #include "media_user_setting_specific.h"
35
36 static constexpr uint32_t singleVeboxSubSliceNumMax = 24;
37
38 //extern template class DeviceInfoFactory<GfxDeviceInfo>;
39 typedef DeviceInfoFactory<LinuxDeviceInit> DeviceInit;
40
41 static struct LinuxCodecInfo tglCodecInfo =
42 {
43 .avcDecoding = 1,
44 .mpeg2Decoding = 1,
45 .vp8Decoding = 1,
46 .vc1Decoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
47 .jpegDecoding = 1,
48 .avcEncoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
49 .mpeg2Encoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
50 .hevcDecoding = 1,
51 .hevcEncoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
52 .jpegEncoding = 1,
53 .avcVdenc = 1,
54 .vp9Decoding = 1,
55 .hevc10Decoding = 1,
56 .vp9b10Decoding = 1,
57 .hevc10Encoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
58 .hevc12Encoding = SET_STATUS_BY_FULL_OPEN_SOURCE(1, 0),
59 .vp8Encoding = 0,
60 .hevcVdenc = 1,
61 .vp9Vdenc = 1,
62 .adv0Decoding = 1,
63 .adv1Decoding = 1,
64 };
65
InitTglMediaSku(struct GfxDeviceInfo * devInfo,MediaFeatureTable * skuTable,struct LinuxDriverInfo * drvInfo,MediaUserSettingSharedPtr userSettingPtr)66 static bool InitTglMediaSku(struct GfxDeviceInfo *devInfo,
67 MediaFeatureTable *skuTable,
68 struct LinuxDriverInfo *drvInfo,
69 MediaUserSettingSharedPtr userSettingPtr)
70 {
71 if ((devInfo == nullptr) || (skuTable == nullptr) || (drvInfo == nullptr))
72 {
73 DEVINFO_ERROR("null ptr is passed\n");
74 return false;
75 }
76
77 if (drvInfo->hasBsd)
78 {
79 LinuxCodecInfo *codecInfo = &tglCodecInfo;
80
81 if (devInfo->productFamily == IGFX_TIGERLAKE_LP &&
82 drvInfo->devRev == 0)
83 {
84 codecInfo->adv0Decoding = 0;
85 codecInfo->adv1Decoding = 0;
86 }
87
88 MEDIA_WR_SKU(skuTable, FtrAVCVLDLongDecoding, codecInfo->avcDecoding);
89 MEDIA_WR_SKU(skuTable, FtrMPEG2VLDDecoding, codecInfo->mpeg2Decoding);
90 MEDIA_WR_SKU(skuTable, FtrIntelVP8VLDDecoding, codecInfo->vp8Decoding);
91 MEDIA_WR_SKU(skuTable, FtrVC1VLDDecoding, codecInfo->vc1Decoding);
92 MEDIA_WR_SKU(skuTable, FtrIntelJPEGDecoding, codecInfo->jpegDecoding);
93 MEDIA_WR_SKU(skuTable, FtrEncodeAVC, codecInfo->avcEncoding);
94 MEDIA_WR_SKU(skuTable, FtrEncodeMPEG2, codecInfo->mpeg2Encoding);
95 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMainDecoding, codecInfo->hevcDecoding);
96 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain10Decoding, codecInfo->hevc10Decoding);
97
98 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC, codecInfo->hevcEncoding);
99 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC10bit, codecInfo->hevc10Encoding);
100 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC12bit, codecInfo->hevc12Encoding);
101 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC10bit422, codecInfo->hevc10Encoding);
102 MEDIA_WR_SKU(skuTable, FtrEncodeHEVC12bit422, codecInfo->hevc12Encoding);
103 MEDIA_WR_SKU(skuTable, FtrEncodeJPEG, codecInfo->jpegEncoding);
104 MEDIA_WR_SKU(skuTable, FtrEncodeAVCVdenc, codecInfo->avcVdenc);
105 MEDIA_WR_SKU(skuTable, FtrVP9VLDDecoding, codecInfo->vp9Decoding);
106 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile0Decoding8bit420, codecInfo->vp9Decoding);
107 MEDIA_WR_SKU(skuTable, FtrVP9VLD10bProfile2Decoding, codecInfo->vp9b10Decoding);
108 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile2Decoding, codecInfo->vp9b10Decoding);
109 MEDIA_WR_SKU(skuTable, FtrIntelAV1VLDDecoding8bit420, codecInfo->adv0Decoding);
110 MEDIA_WR_SKU(skuTable, FtrIntelAV1VLDDecoding10bit420, codecInfo->adv1Decoding);
111
112 /* VP8 enc */
113 MEDIA_WR_SKU(skuTable, FtrEncodeVP8, codecInfo->vp8Encoding);
114
115 /* HEVC VDENC */
116 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain, codecInfo->hevcVdenc);
117 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10, codecInfo->hevcVdenc);
118
119 /* Vp9 VDENC */
120 MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc, codecInfo->vp9Vdenc);
121
122 /* HEVC Main8/10bit-422/444 Decoding. Currently it is enabled. */
123 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLD42210bitDecoding, 1);
124 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLD4448bitDecoding, 1);
125 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLD44410bitDecoding, 1);
126
127 /* SFC Histogram Streamout. */
128 MEDIA_WR_SKU(skuTable, FtrSFCHistogramStreamOut, 1);
129
130 /* Subset buffer for realtile decoding. */
131 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDDecodingSubsetBuffer, 1);
132
133 /* HEVC Main8/10bit-420/422/444 Scc Decoding. Currently it is enabled. */
134 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain8bit420SCC, 1);
135 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain10bit420SCC, 1);
136 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain8bit444SCC, 1);
137 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain10bit444SCC, 1);
138
139 /* HEVC VDENC Main8/10 422/444 Encoding. */
140 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain444, codecInfo->hevcVdenc);
141 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain422, 0);
142 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10bit422, 0);
143 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10bit444, codecInfo->hevcVdenc);
144
145 /* HEVC VDENC Main8/10bit-420/422/444 Scc Encoding. */
146 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMainSCC, codecInfo->hevcVdenc);
147 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10bitSCC, codecInfo->hevcVdenc);
148 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain444SCC, codecInfo->hevcVdenc);
149 MEDIA_WR_SKU(skuTable, FtrEncodeHEVCVdencMain10bit444SCC, codecInfo->hevcVdenc);
150
151 /* HEVC 12bit Decoding. Currently it is enabled */
152 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain12bit420Decoding, 1);
153 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain12bit422Decoding, 1);
154 MEDIA_WR_SKU(skuTable, FtrIntelHEVCVLDMain12bit444Decoding, 1);
155
156 /* VP9 8 bit 444 */
157 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile1Decoding8bit444, 1);
158 /* VP9 10 Bit 444*/
159 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile3Decoding10bit444, 1);
160 /* VP9 12 bit 420/444 */
161 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile2Decoding12bit420, 1);
162 MEDIA_WR_SKU(skuTable, FtrIntelVP9VLDProfile3Decoding12bit444, 1);
163
164 /* VP9 VDENC 8Bit 444 */
165 MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc8bit444, codecInfo->vp9Vdenc);
166 /* VP9 VDENC 10Bit 420/444 */
167 MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc10bit420, codecInfo->vp9Vdenc);
168 MEDIA_WR_SKU(skuTable, FtrEncodeVP9Vdenc10bit444, codecInfo->vp9Vdenc);
169 }
170
171 MEDIA_WR_SKU(skuTable, FtrEnableMediaKernels, drvInfo->hasHuc);
172
173 if (devInfo->eGTType == GTTYPE_GT1)
174 {
175 MEDIA_WR_SKU(skuTable, FtrGT1, 1);
176 }
177 else if (devInfo->eGTType == GTTYPE_GT1_5)
178 {
179 MEDIA_WR_SKU(skuTable, FtrGT1_5, 1);
180 }
181 else if (devInfo->eGTType == GTTYPE_GT2)
182 {
183 MEDIA_WR_SKU(skuTable, FtrGT2, 1);
184 }
185 else if (devInfo->eGTType == GTTYPE_GT3)
186 {
187 MEDIA_WR_SKU(skuTable, FtrGT3, 1);
188 }
189 else if (devInfo->eGTType == GTTYPE_GT4)
190 {
191 MEDIA_WR_SKU(skuTable, FtrGT4, 1);
192 }
193 else
194 {
195 /* GT1 is by default */
196 MEDIA_WR_SKU(skuTable, FtrGT1, 1);
197 }
198
199 MEDIA_WR_SKU(skuTable, FtrVERing, drvInfo->hasVebox);
200 MEDIA_WR_SKU(skuTable, FtrPPGTT, drvInfo->hasPpgtt);
201 MEDIA_WR_SKU(skuTable, FtrEDram, devInfo->hasERAM);
202
203 /* Virtual VDBOX ring is used on Gen12 */
204 MEDIA_WR_SKU(skuTable, FtrVcs2, 0);
205
206 MEDIA_WR_SKU(skuTable, FtrSingleVeboxSlice, 1);
207 if (devInfo->SubSliceCount >= singleVeboxSubSliceNumMax)
208 {
209 MEDIA_WR_SKU(skuTable, FtrSingleVeboxSlice, 0);
210 }
211
212 MEDIA_WR_SKU(skuTable, FtrSFCPipe, 1);
213 MEDIA_WR_SKU(skuTable, FtrHCP2SFCPipe, 1);
214 MEDIA_WR_SKU(skuTable, FtrSSEUPowerGating, 1);
215 MEDIA_WR_SKU(skuTable, FtrSSEUPowerGatingControlByUMD, 1);
216
217 MEDIA_WR_SKU(skuTable, FtrPerCtxtPreemptionGranularityControl, 1);
218
219 /* It is disabled by default. It can be enabled based on HW */
220 MEDIA_WR_SKU(skuTable, FtrMemoryCompression, 0);
221 MEDIA_WR_SKU(skuTable, FtrHcpDecMemoryCompression, 0);
222 MEDIA_WR_SKU(skuTable, Ftr10bitDecMemoryCompression, 0);
223
224 MEDIA_WR_SKU(skuTable, FtrRAMode, 1);
225 MEDIA_WR_SKU(skuTable, FtrVpP010Output, 1);
226 MEDIA_WR_SKU(skuTable, FtrVp10BitSupport, 1);
227 MEDIA_WR_SKU(skuTable, FtrVp16BitSupport, 1);
228
229 MEDIA_WR_SKU(skuTable, FtrContextBasedScheduling, 1);
230 MEDIA_WR_SKU(skuTable, FtrSfcScalability, 1);
231
232 MEDIA_WR_SKU(skuTable, FtrTileY, 1);
233
234 bool disableMMC = false;
235 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 1);
236
237 if (drvInfo->devRev <= 2)
238 {
239 // turn off Compression as HW known issue
240 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 0);
241 }
242
243 // Disable MMC for all components if set reg key
244 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
245 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
246 MOS_UserFeature_ReadValue_ID(
247 nullptr,
248 __MEDIA_USER_FEATURE_VALUE_DISABLE_MMC_ID,
249 &userFeatureData,
250 (MOS_CONTEXT_HANDLE)nullptr);
251 if (userFeatureData.bData)
252 {
253 disableMMC = true;
254 }
255
256 if (disableMMC)
257 {
258 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 0);
259 }
260
261 // Force MMC Turn on for all components if set reg key
262 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
263 MOS_UserFeature_ReadValue_ID(
264 nullptr,
265 __MEDIA_USER_FEATURE_VALUE_FORCE_MMC_ON_ID,
266 &userFeatureData,
267 (MOS_CONTEXT_HANDLE)nullptr);
268
269 if (userFeatureData.bData)
270 {
271 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 1);
272 }
273
274 MEDIA_WR_SKU(skuTable, FtrLinearCCS, 1);
275
276 MEDIA_WR_SKU(skuTable, FtrUseSwSwizzling, 1);
277 MEDIA_WR_SKU(skuTable, FtrScalingFirst, 1);
278
279 // Create uncompressible surface by default
280 MEDIA_WR_SKU(skuTable, FtrCompressibleSurfaceDefault, 0);
281
282 bool compressibleSurfaceEnable = false;
283
284 ReadUserSetting(userSettingPtr,
285 compressibleSurfaceEnable,
286 "Enable Compressible Surface Creation",
287 MediaUserSetting::Group::Device);
288
289 #ifdef _MMC_SUPPORTED
290 if (compressibleSurfaceEnable)
291 {
292 MEDIA_WR_SKU(skuTable, FtrCompressibleSurfaceDefault, 1);
293 }
294 #endif
295
296 MEDIA_WR_SKU(skuTable, FtrHDR, 1);
297
298 return true;
299 }
300
InitTglMediaWa(struct GfxDeviceInfo * devInfo,MediaWaTable * waTable,struct LinuxDriverInfo * drvInfo)301 static bool InitTglMediaWa(struct GfxDeviceInfo *devInfo,
302 MediaWaTable *waTable,
303 struct LinuxDriverInfo *drvInfo)
304 {
305 if ((devInfo == nullptr) || (waTable == nullptr) || (drvInfo == nullptr))
306 {
307 DEVINFO_ERROR("null ptr is passed\n");
308 return false;
309 }
310
311 MEDIA_WR_WA(waTable, WaForceGlobalGTT, !drvInfo->hasPpgtt);
312 MEDIA_WR_WA(waTable, WaMidBatchPreemption, 0);
313 MEDIA_WR_WA(waTable, WaArbitraryNumMbsInSlice, 1);
314
315 MEDIA_WR_WA(waTable, WaSuperSliceHeaderPacking, 1);
316
317 MEDIA_WR_WA(waTable, WaSFC270DegreeRotation, 0);
318
319 MEDIA_WR_WA(waTable, WaEnableYV12BugFixInHalfSliceChicken7, 1);
320
321 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
322 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
323 MOS_UserFeature_ReadValue_ID(
324 nullptr,
325 __MEDIA_USER_FEATURE_VALUE_AUX_TABLE_16K_GRANULAR_ID,
326 &userFeatureData,
327 (MOS_CONTEXT_HANDLE)nullptr);
328
329 MEDIA_WR_WA(waTable, WaDummyReference, 1);
330
331 /*software wa to add a dummy workload in front of
332 normal workload per batch buffer*/
333 MEDIA_WR_WA(waTable, Wa_1508208842, 1);
334
335 MEDIA_WR_WA(waTable, Wa16KInputHeightNV12Planar420, 1);
336
337 /*software wa to disable calculate the UV offset by gmmlib
338 CPU blt call will add/remove padding on the platform*/
339 MEDIA_WR_WA(waTable, WaDisableGmmLibOffsetInDeriveImage, 1);
340
341 /*software wa to fix some corner cases of HEVC/VP9 SFC and Scalability*/
342 MEDIA_WR_WA(waTable, Wa_14010222001, 1);
343
344 /*software wa to fix some corner hang cases for Scalability*/
345 MEDIA_WR_WA(waTable, Wa_2209620131, 1);
346
347 /*software wa to prevent error propagation for vertical intra refresh on H264 VDEnc*/
348 MEDIA_WR_WA(waTable, Wa_18011246551, 1);
349
350 MEDIA_WR_WA(waTable, WaDisableVeboxFor8K, 1);
351
352 if (drvInfo->devRev == 0)
353 {
354 /* Turn off MMC for codec, need to remove once turn it on */
355 MEDIA_WR_WA(waTable, WaDisableCodecMmc, 1);
356
357 /* Turn off MMC for VPP, need to remove once turn it on */
358 MEDIA_WR_WA(waTable, WaDisableVPMmc, 1);
359 }
360
361 /*software wa to use frame based decoding for AV1 decode*/
362 MEDIA_WR_WA(waTable, Wa_1409820462, 1);
363
364 /*software wa to use huc copy for init aux table for MFX*/
365 MEDIA_WR_WA(waTable, Wa_22010493002, 1);
366
367 MEDIA_WR_WA(waTable, Wa_Vp9UnalignedHeight, 1);
368 MEDIA_WR_WA(waTable, Wa_AvcUnalignedHeight, 1);
369 MEDIA_WR_WA(waTable, WaDisableSetObjectCapture, 0);
370 return true;
371 }
372
373
374 #ifdef IGFX_GEN12_DG1_SUPPORTED
InitDG1MediaSku(struct GfxDeviceInfo * devInfo,MediaFeatureTable * skuTable,struct LinuxDriverInfo * drvInfo,MediaUserSettingSharedPtr userSettingPtr)375 static bool InitDG1MediaSku(struct GfxDeviceInfo *devInfo,
376 MediaFeatureTable *skuTable,
377 struct LinuxDriverInfo *drvInfo,
378 MediaUserSettingSharedPtr userSettingPtr)
379 {
380 if (!InitTglMediaSku(devInfo, skuTable, drvInfo, userSettingPtr))
381 {
382 return false;
383 }
384 MEDIA_WR_SKU(skuTable, FtrLocalMemory, 1);
385
386 if (drvInfo->devRev > 0)
387 {
388 MEDIA_WR_SKU(skuTable, FtrAV1VLDLSTDecoding, 1);
389 }
390 MEDIA_WR_SKU(skuTable, FtrIntelVP8VLDDecoding, 0);
391
392 bool enableCodecMMC = false;
393 bool enableVPMMC = false;
394
395 // Disable MMC for all components if set reg key
396 MOS_USER_FEATURE_VALUE_DATA userFeatureData;
397 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
398 MOS_UserFeature_ReadValue_ID(
399 nullptr,
400 __VPHAL_ENABLE_MMC_ID,
401 &userFeatureData,
402 (MOS_CONTEXT_HANDLE)nullptr);
403 if (userFeatureData.bData)
404 {
405 enableVPMMC = true;
406 }
407
408 MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData));
409 MOS_UserFeature_ReadValue_ID(
410 nullptr,
411 __MEDIA_USER_FEATURE_VALUE_CODEC_MMC_ENABLE_ID,
412 &userFeatureData,
413 (MOS_CONTEXT_HANDLE)nullptr);
414 if (userFeatureData.bData)
415 {
416 enableCodecMMC = true;
417 }
418
419 if (!enableCodecMMC && !enableVPMMC)
420 {
421 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 0);
422 }
423
424 return true;
425 }
426
InitDG1MediaWa(struct GfxDeviceInfo * devInfo,MediaWaTable * waTable,struct LinuxDriverInfo * drvInfo)427 static bool InitDG1MediaWa(struct GfxDeviceInfo *devInfo,
428 MediaWaTable *waTable,
429 struct LinuxDriverInfo *drvInfo)
430 {
431 if (!InitTglMediaWa(devInfo, waTable, drvInfo))
432 {
433 DEVINFO_ERROR("InitMediaWA failed\n");
434 return false;
435 }
436
437 /* Turn off MMC for codec, need to remove once turn it on */
438 MEDIA_WR_WA(waTable, WaDisableCodecMmc, 1);
439
440 /* Turn off MMC for VPP, need to remove once turn it on */
441 MEDIA_WR_WA(waTable, WaDisableVPMmc, 1);
442
443 /* Enable VPP copy */
444 MEDIA_WR_WA(waTable, WaEnableVPPCopy, 1);
445 return true;
446 }
447
448 static struct LinuxDeviceInit dg1DeviceInit =
449 {
450 .productFamily = IGFX_DG1,
451 .InitMediaFeature = InitDG1MediaSku,
452 .InitMediaWa = InitDG1MediaWa,
453 };
454
455 static bool dg1DeviceRegister = DeviceInfoFactory<LinuxDeviceInit>::
456 RegisterDevice(IGFX_DG1, &dg1DeviceInit);
457
458 #endif
459
460 #ifdef IGFX_GEN12_RKL_SUPPORTED
InitRKLMediaSku(struct GfxDeviceInfo * devInfo,MediaFeatureTable * skuTable,struct LinuxDriverInfo * drvInfo,MediaUserSettingSharedPtr userSettingPtr)461 static bool InitRKLMediaSku(struct GfxDeviceInfo *devInfo,
462 MediaFeatureTable * skuTable,
463 struct LinuxDriverInfo *drvInfo,
464 MediaUserSettingSharedPtr userSettingPtr)
465 {
466 if (!InitTglMediaSku(devInfo, skuTable, drvInfo, userSettingPtr))
467 {
468 return false;
469 }
470
471 if (devInfo->eGTType == GTTYPE_GT0_5)
472 {
473 MEDIA_WR_SKU(skuTable, FtrGT0_5, 1);
474 }
475
476 MEDIA_WR_SKU(skuTable, FtrSfcScalability, 0);
477 MEDIA_WR_SKU(skuTable, FtrIntelVP8VLDDecoding, 0);
478
479 // turn off Compression on RKL as HW known issue
480 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 0);
481 return true;
482 }
483
InitRKLMediaWa(struct GfxDeviceInfo * devInfo,MediaWaTable * waTable,struct LinuxDriverInfo * drvInfo)484 static bool InitRKLMediaWa(struct GfxDeviceInfo *devInfo,
485 MediaWaTable * waTable,
486 struct LinuxDriverInfo * drvInfo)
487 {
488 if (!InitTglMediaWa(devInfo, waTable, drvInfo))
489 {
490 return false;
491 }
492
493 return true;
494 }
495
496 static struct LinuxDeviceInit rklDeviceInit =
497 {
498 .productFamily = IGFX_ROCKETLAKE,
499 .InitMediaFeature = InitRKLMediaSku,
500 .InitMediaWa = InitRKLMediaWa,
501 };
502
503 static bool rklDeviceRegister = DeviceInfoFactory<LinuxDeviceInit>::
504 RegisterDevice(IGFX_ROCKETLAKE, &rklDeviceInit);
505
506 #endif
507
508 #ifdef IGFX_GEN12_ADLS_SUPPORTED
InitAdlsMediaSku(struct GfxDeviceInfo * devInfo,MediaFeatureTable * skuTable,struct LinuxDriverInfo * drvInfo,MediaUserSettingSharedPtr userSettingPtr)509 static bool InitAdlsMediaSku(struct GfxDeviceInfo *devInfo,
510 MediaFeatureTable *skuTable,
511 struct LinuxDriverInfo *drvInfo,
512 MediaUserSettingSharedPtr userSettingPtr)
513 {
514 if (!InitTglMediaSku(devInfo, skuTable, drvInfo, userSettingPtr))
515 {
516 return false;
517 }
518
519 if (devInfo->eGTType == GTTYPE_GT0_5)
520 {
521 MEDIA_WR_SKU(skuTable, FtrGT0_5, 1);
522 }
523
524 MEDIA_WR_SKU(skuTable, FtrAV1VLDLSTDecoding, 1);
525
526 MEDIA_WR_SKU(skuTable, FtrHeight8AlignVE3DLUTDualPipe, 1);
527
528 //Disable VP8 for ADLS
529 MEDIA_WR_SKU(skuTable, FtrIntelVP8VLDDecoding, 0);
530
531 // Disable HEVC 422 Virtual Tile Scalability
532 MEDIA_WR_SKU(skuTable, FtrDecodeHEVC422VTScalaDisable, 1);
533
534 MEDIA_WR_SKU(skuTable, FtrVirtualTileScalabilityDisable, 1);
535 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 1);
536
537 //RPL-S
538 if (drvInfo->devId == 0xA780 ||
539 drvInfo->devId == 0xA781 ||
540 drvInfo->devId == 0xA782 ||
541 drvInfo->devId == 0xA783 ||
542 drvInfo->devId == 0xA788 ||
543 drvInfo->devId == 0xA789 ||
544 drvInfo->devId == 0xA78A ||
545 drvInfo->devId == 0xA78B)
546 {
547 MEDIA_WR_SKU(skuTable, FtrGucSubmission, 1);
548 }
549
550 return true;
551 }
552
InitAdlsMediaWa(struct GfxDeviceInfo * devInfo,MediaWaTable * waTable,struct LinuxDriverInfo * drvInfo)553 static bool InitAdlsMediaWa(struct GfxDeviceInfo* devInfo,
554 MediaWaTable* waTable,
555 struct LinuxDriverInfo* drvInfo)
556 {
557 if (!InitTglMediaWa(devInfo, waTable, drvInfo))
558 {
559 return false;
560 }
561
562 //ADL-S not need this
563 MEDIA_WR_WA(waTable, Wa_1409820462, 0);
564
565 //ADL-S need enable MMC for all stepping
566 MEDIA_WR_WA(waTable, WaDisableCodecMmc, 0);
567 MEDIA_WR_WA(waTable, WaDisableVPMmc, 0);
568 MEDIA_WR_WA(waTable, WaDisableClearCCS, 1);
569
570 return true;
571 }
572
573 static struct LinuxDeviceInit adlsDeviceInit =
574 {
575 .productFamily = IGFX_ALDERLAKE_S,
576 .InitMediaFeature = InitAdlsMediaSku,
577 .InitMediaWa = InitAdlsMediaWa,
578 };
579
580 static bool adlsDeviceRegister = DeviceInfoFactory<LinuxDeviceInit>::
581 RegisterDevice(IGFX_ALDERLAKE_S, &adlsDeviceInit);
582 #endif
583
584
585 #ifdef IGFX_GEN12_ADLP_SUPPORTED
InitAdlpMediaSku(struct GfxDeviceInfo * devInfo,MediaFeatureTable * skuTable,struct LinuxDriverInfo * drvInfo,MediaUserSettingSharedPtr userSettingPtr)586 static bool InitAdlpMediaSku(struct GfxDeviceInfo *devInfo,
587 MediaFeatureTable * skuTable,
588 struct LinuxDriverInfo *drvInfo,
589 MediaUserSettingSharedPtr userSettingPtr)
590 {
591 if (!InitTglMediaSku(devInfo, skuTable, drvInfo, userSettingPtr))
592 {
593 return false;
594 }
595
596 if (devInfo->eGTType == GTTYPE_GT0_5)
597 {
598 MEDIA_WR_SKU(skuTable, FtrGT0_5, 1);
599 }
600
601 MEDIA_WR_SKU(skuTable, FtrAV1VLDLSTDecoding, 1);
602 MEDIA_WR_SKU(skuTable, FtrGucSubmission, 1);
603 MEDIA_WR_SKU(skuTable, FtrDecodeHEVC422VTScalaDisable, 1);
604 MEDIA_WR_SKU(skuTable, FtrVirtualTileScalabilityDisable, 1);
605
606 return true;
607 }
608
InitAdlpMediaWa(struct GfxDeviceInfo * devInfo,MediaWaTable * waTable,struct LinuxDriverInfo * drvInfo)609 static bool InitAdlpMediaWa(struct GfxDeviceInfo *devInfo,
610 MediaWaTable * waTable,
611 struct LinuxDriverInfo * drvInfo)
612 {
613 if (!InitTglMediaWa(devInfo, waTable, drvInfo))
614 {
615 return false;
616 }
617
618 //ADL-P not need this
619 MEDIA_WR_WA(waTable, Wa_1409820462, 0);
620 MEDIA_WR_WA(waTable, WaDisableClearCCS, 1);
621
622 return true;
623 }
624
625 static struct LinuxDeviceInit adlpDeviceInit =
626 {
627 .productFamily = IGFX_ALDERLAKE_P,
628 .InitMediaFeature = InitAdlpMediaSku,
629 .InitMediaWa = InitAdlpMediaWa,
630 };
631
632 static bool adlpDeviceRegister = DeviceInfoFactory<LinuxDeviceInit>::
633 RegisterDevice(IGFX_ALDERLAKE_P, &adlpDeviceInit);
634
635 #endif
636
637 #ifdef IGFX_GEN12_ADLN_SUPPORTED
InitAdlnMediaSku(struct GfxDeviceInfo * devInfo,MediaFeatureTable * skuTable,struct LinuxDriverInfo * drvInfo,MediaUserSettingSharedPtr userSettingPtr)638 static bool InitAdlnMediaSku(struct GfxDeviceInfo *devInfo,
639 MediaFeatureTable * skuTable,
640 struct LinuxDriverInfo *drvInfo,
641 MediaUserSettingSharedPtr userSettingPtr)
642 {
643 if (!InitTglMediaSku(devInfo, skuTable, drvInfo, userSettingPtr))
644 {
645 return false;
646 }
647
648 if (devInfo->eGTType == GTTYPE_GT0_5)
649 {
650 MEDIA_WR_SKU(skuTable, FtrGT0_5, 1);
651 }
652
653 MEDIA_WR_SKU(skuTable, FtrHeight8AlignVE3DLUTDualPipe, 1);
654 MEDIA_WR_SKU(skuTable, FtrAV1VLDLSTDecoding, 1);
655 MEDIA_WR_SKU(skuTable, FtrGucSubmission, 1);
656 MEDIA_WR_SKU(skuTable, FtrDecodeHEVC422VTScalaDisable, 1);
657 MEDIA_WR_SKU(skuTable, FtrE2ECompression, 1);
658
659 return true;
660 }
661
InitAdlnMediaWa(struct GfxDeviceInfo * devInfo,MediaWaTable * waTable,struct LinuxDriverInfo * drvInfo)662 static bool InitAdlnMediaWa(struct GfxDeviceInfo *devInfo,
663 MediaWaTable * waTable,
664 struct LinuxDriverInfo * drvInfo)
665 {
666 if (!InitTglMediaWa(devInfo, waTable, drvInfo))
667 {
668 return false;
669 }
670
671 //ADL-N keeps below setting same as ADL-S/ADL-P
672 MEDIA_WR_WA(waTable, Wa_1409820462, 0);
673
674 //ADL-N need enable MMC for all stepping
675 MEDIA_WR_WA(waTable, WaDisableCodecMmc, 0);
676 MEDIA_WR_WA(waTable, WaDisableVPMmc, 0);
677 MEDIA_WR_WA(waTable, WaDisableClearCCS, 1);
678
679 return true;
680 }
681
682 static struct LinuxDeviceInit adlnDeviceInit =
683 {
684 .productFamily = IGFX_ALDERLAKE_N,
685 .InitMediaFeature = InitAdlnMediaSku,
686 .InitMediaWa = InitAdlnMediaWa,
687 };
688
689 static bool adlnDeviceRegister = DeviceInfoFactory<LinuxDeviceInit>::
690 RegisterDevice(IGFX_ALDERLAKE_N, &adlnDeviceInit);
691
692 #endif
693
694 static struct LinuxDeviceInit tgllpDeviceInit =
695 {
696 .productFamily = IGFX_TIGERLAKE_LP,
697 .InitMediaFeature = InitTglMediaSku,
698 .InitMediaWa = InitTglMediaWa,
699 };
700
701 static bool tgllpDeviceRegister = DeviceInfoFactory<LinuxDeviceInit>::
702 RegisterDevice(IGFX_TIGERLAKE_LP, &tgllpDeviceInit);
703
704
705