1 /*
2 * Copyright (c) 2017-2019, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_vdbox_huc_g12_X.cpp
24 //! \brief Constructs VdBox Huc commands on Gen12-based platforms
25
26 #include "mhw_vdbox_huc_g12_X.h"
27 #include "mhw_vdbox_vdenc_hwcmd_g12_X.h"
28 #include "mhw_mi.h"
29 #include "mhw_mmio_g12.h"
30
InitMmioRegisters()31 void MhwVdboxHucInterfaceG12::InitMmioRegisters()
32 {
33 MmioRegistersHuc *mmioRegisters = &m_mmioRegisters[MHW_VDBOX_NODE_1];
34
35 mmioRegisters->hucUKernelHdrInfoRegOffset = HUC_UKERNEL_HDR_INFO_REG_OFFSET_NODE_1_INIT_G12;
36 mmioRegisters->hucStatusRegOffset = HUC_STATUS_REG_OFFSET_NODE_1_INIT_G12;
37 mmioRegisters->hucStatus2RegOffset = HUC_STATUS2_REG_OFFSET_NODE_1_INIT_G12;
38 mmioRegisters->hucLoadInfoOffset = HUC_LOAD_INFO_REG_OFFSET_G12;
39
40 m_mmioRegisters[MHW_VDBOX_NODE_2] = m_mmioRegisters[MHW_VDBOX_NODE_1];
41 }
42
GetHucStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)43 MOS_STATUS MhwVdboxHucInterfaceG12::GetHucStateCommandSize(
44 uint32_t mode,
45 uint32_t *commandsSize,
46 uint32_t *patchListSize,
47 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
48 {
49 MHW_FUNCTION_ENTER;
50
51 MHW_MI_CHK_NULL(commandsSize);
52 MHW_MI_CHK_NULL(patchListSize);
53
54 MHW_MI_CHK_STATUS((MhwVdboxHucInterfaceGeneric<mhw_vdbox_huc_g12_X, mhw_mi_g12_X>::
55 GetHucStateCommandSize(mode, commandsSize, patchListSize, params)));
56
57 *commandsSize += mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize;
58 *patchListSize += PATCH_LIST_COMMAND(VD_PIPELINE_FLUSH_CMD);
59
60 if(params->uNumVdPipelineFlush)
61 {
62 *commandsSize += params->uNumVdPipelineFlush * mhw_vdbox_vdenc_g12_X::VD_PIPELINE_FLUSH_CMD::byteSize;
63 *patchListSize += params->uNumVdPipelineFlush * PATCH_LIST_COMMAND(VD_PIPELINE_FLUSH_CMD);
64 }
65
66 return MOS_STATUS_SUCCESS;
67 }
68
AddHucPipeModeSelectCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_PIPE_MODE_SELECT_PARAMS * params)69 MOS_STATUS MhwVdboxHucInterfaceG12::AddHucPipeModeSelectCmd(
70 MOS_COMMAND_BUFFER *cmdBuffer,
71 MHW_VDBOX_PIPE_MODE_SELECT_PARAMS *params)
72 {
73 MHW_MI_CHK_NULL(m_osInterface);
74 MHW_MI_CHK_NULL(cmdBuffer);
75 MHW_MI_CHK_NULL(params);
76
77 //for gen 11, we need to add MFX wait for both KIN and VRT before and after HUC Pipemode select...
78 MHW_MI_CHK_STATUS(m_MiInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
79
80 mhw_vdbox_huc_g12_X::HUC_PIPE_MODE_SELECT_CMD cmd;
81
82 if (!params->disableProtectionSetting)
83 {
84 MHW_MI_CHK_STATUS(m_cpInterface->SetProtectionSettingsForHucPipeModeSelect((uint32_t *)&cmd));
85 }
86
87 cmd.DW1.IndirectStreamOutEnable = params->bStreamOutEnabled;
88 cmd.DW2.MediaSoftResetCounterPer1000Clocks = params->dwMediaSoftResetCounterValue;
89
90 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
91
92 //for gen 11, we need to add MFX wait for both KIN and VRT before and after HUC Pipemode select...
93 MHW_MI_CHK_STATUS(m_MiInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
94
95 return MOS_STATUS_SUCCESS;
96 }
97
AddHucImemStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_IMEM_STATE_PARAMS * params)98 MOS_STATUS MhwVdboxHucInterfaceG12::AddHucImemStateCmd(
99 MOS_COMMAND_BUFFER *cmdBuffer,
100 MHW_VDBOX_HUC_IMEM_STATE_PARAMS *params)
101 {
102 MHW_MI_CHK_NULL(m_osInterface);
103 MHW_MI_CHK_NULL(cmdBuffer);
104 MHW_MI_CHK_NULL(params);
105
106 mhw_vdbox_huc_g12_X::HUC_IMEM_STATE_CMD cmd;
107
108 cmd.DW4.HucFirmwareDescriptor = params->dwKernelDescriptor;
109
110 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
111
112 MHW_MI_CHK_STATUS(m_MiInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
113
114 return MOS_STATUS_SUCCESS;
115 }
116
117