1 /*
2 * Copyright (c) 2017-2018, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_vdbox_huc_g11_X.cpp
24 //! \brief Constructs VdBox Huc commands on Gen11-based platforms
25
26 #include "mhw_vdbox_huc_g11_X.h"
27 #include "mhw_vdbox_vdenc_hwcmd_g11_X.h"
28 #include "mhw_mmio_g11.h"
29
InitMmioRegisters()30 void MhwVdboxHucInterfaceG11::InitMmioRegisters()
31 {
32 MmioRegistersHuc *mmioRegisters = &m_mmioRegisters[MHW_VDBOX_NODE_1];
33
34 mmioRegisters->hucUKernelHdrInfoRegOffset = HUC_UKERNEL_HDR_INFO_REG_OFFSET_NODE_1_INIT_G11;
35 mmioRegisters->hucStatusRegOffset = HUC_STATUS_REG_OFFSET_NODE_1_INIT_G11;
36 mmioRegisters->hucStatus2RegOffset = HUC_STATUS2_REG_OFFSET_NODE_1_INIT_G11;
37
38 m_mmioRegisters[MHW_VDBOX_NODE_2] = m_mmioRegisters[MHW_VDBOX_NODE_1];
39 }
40
GetHucStateCommandSize(uint32_t mode,uint32_t * commandsSize,uint32_t * patchListSize,PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)41 MOS_STATUS MhwVdboxHucInterfaceG11::GetHucStateCommandSize(
42 uint32_t mode,
43 uint32_t *commandsSize,
44 uint32_t *patchListSize,
45 PMHW_VDBOX_STATE_CMDSIZE_PARAMS params)
46 {
47 MHW_FUNCTION_ENTER;
48
49 MHW_MI_CHK_NULL(commandsSize);
50 MHW_MI_CHK_NULL(patchListSize);
51
52 MHW_MI_CHK_STATUS((MhwVdboxHucInterfaceGeneric<mhw_vdbox_huc_g11_X, mhw_mi_g11_X>::
53 GetHucStateCommandSize(mode, commandsSize, patchListSize, params)));
54
55 *commandsSize += mhw_vdbox_vdenc_g11_X::VD_PIPELINE_FLUSH_CMD::byteSize;
56 *patchListSize += PATCH_LIST_COMMAND(VD_PIPELINE_FLUSH_CMD);
57
58 return MOS_STATUS_SUCCESS;
59 }
60
AddHucPipeModeSelectCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_PIPE_MODE_SELECT_PARAMS * params)61 MOS_STATUS MhwVdboxHucInterfaceG11::AddHucPipeModeSelectCmd(
62 MOS_COMMAND_BUFFER *cmdBuffer,
63 MHW_VDBOX_PIPE_MODE_SELECT_PARAMS *params)
64 {
65 MHW_MI_CHK_NULL(m_osInterface);
66 MHW_MI_CHK_NULL(cmdBuffer);
67 MHW_MI_CHK_NULL(params);
68
69 //for gen 11, we need to add MFX wait for both KIN and VRT before and after HUC Pipemode select...
70 MHW_MI_CHK_STATUS(m_MiInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
71
72 mhw_vdbox_huc_g11_X::HUC_PIPE_MODE_SELECT_CMD cmd;
73
74 if (!params->disableProtectionSetting)
75 {
76 MHW_MI_CHK_STATUS(m_cpInterface->SetProtectionSettingsForHucPipeModeSelect((uint32_t *)&cmd));
77 }
78
79 cmd.DW1.IndirectStreamOutEnable = params->bStreamOutEnabled;
80 cmd.DW2.MediaSoftResetCounterPer1000Clocks = params->dwMediaSoftResetCounterValue;
81
82 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
83
84 //for gen 11, we need to add MFX wait for both KIN and VRT before and after HUC Pipemode select...
85 MHW_MI_CHK_STATUS(m_MiInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
86
87 return MOS_STATUS_SUCCESS;
88 }
89
AddHucImemStateCmd(MOS_COMMAND_BUFFER * cmdBuffer,MHW_VDBOX_HUC_IMEM_STATE_PARAMS * params)90 MOS_STATUS MhwVdboxHucInterfaceG11::AddHucImemStateCmd(
91 MOS_COMMAND_BUFFER *cmdBuffer,
92 MHW_VDBOX_HUC_IMEM_STATE_PARAMS *params)
93 {
94 MHW_MI_CHK_NULL(m_osInterface);
95 MHW_MI_CHK_NULL(cmdBuffer);
96 MHW_MI_CHK_NULL(params);
97
98 mhw_vdbox_huc_g11_X::HUC_IMEM_STATE_CMD cmd;
99
100 cmd.DW4.HucFirmwareDescriptor = params->dwKernelDescriptor;
101
102 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
103
104 MHW_MI_CHK_STATUS(m_MiInterface->AddMfxWaitCmd(cmdBuffer, nullptr, true));
105
106 return MOS_STATUS_SUCCESS;
107 }
108
109