1 /*
2 * Copyright (c) 2015-2019, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file mhw_render_g12_X.cpp
24 //! \brief Constructs render engine commands on Gen12-based platforms
25 //! \details Each client facing function both creates a HW command and adds
26 //! that command to a command or batch buffer.
27 //!
28
29 #include "mhw_render_g12_X.h"
30 #include "mhw_render_hwcmd_g12_X.h"
31
AddMediaVfeCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_VFE_PARAMS params)32 MOS_STATUS MhwRenderInterfaceG12::AddMediaVfeCmd(
33 PMOS_COMMAND_BUFFER cmdBuffer,
34 PMHW_VFE_PARAMS params)
35 {
36 MHW_FUNCTION_ENTER;
37
38 MHW_MI_CHK_NULL(cmdBuffer);
39 MHW_MI_CHK_NULL(params);
40 mhw_render_g12_X::MEDIA_VFE_STATE_CMD *cmd =
41 (mhw_render_g12_X::MEDIA_VFE_STATE_CMD*)cmdBuffer->pCmdPtr;
42
43 MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g12_X>::AddMediaVfeCmd(cmdBuffer, params));
44
45 MHW_MI_CHK_NULL(cmd);
46 cmd->DW4.MaximumNumberOfDualSubslices = params->eVfeSliceDisable;
47 MHW_VFE_PARAMS_G12 *paramsG12 = dynamic_cast<MHW_VFE_PARAMS_G12 *> (params);
48 if (paramsG12 != nullptr)
49 {
50 cmd->DW3.FusedEuDispatch = paramsG12->bFusedEuDispatch ? false : true; // disabled if DW3.FusedEuDispath = 1
51 }
52 else
53 {
54 MHW_ASSERTMESSAGE("Gen12-Specific VFE Params are needed.");
55 return MOS_STATUS_INVALID_PARAMETER;
56 }
57
58 return MOS_STATUS_SUCCESS;
59 }
60
AddPipelineSelectCmd(PMOS_COMMAND_BUFFER cmdBuffer,bool gpGpuPipe)61 MOS_STATUS MhwRenderInterfaceG12::AddPipelineSelectCmd(
62 PMOS_COMMAND_BUFFER cmdBuffer,
63 bool gpGpuPipe)
64 {
65 MHW_FUNCTION_ENTER;
66
67 MHW_MI_CHK_NULL(cmdBuffer);
68 MHW_MI_CHK_NULL(cmdBuffer->pCmdPtr);
69
70 mhw_render_g12_X::PIPELINE_SELECT_CMD *cmd =
71 (mhw_render_g12_X::PIPELINE_SELECT_CMD*)cmdBuffer->pCmdPtr;
72
73 MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g12_X>::AddPipelineSelectCmd(cmdBuffer, gpGpuPipe));
74
75 MHW_MI_CHK_NULL(cmd);
76 cmd->DW0.MaskBits = 0x13;
77
78 return MOS_STATUS_SUCCESS;
79 }
80
AddMediaObject(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER batchBuffer,PMHW_MEDIA_OBJECT_PARAMS params)81 MOS_STATUS MhwRenderInterfaceG12::AddMediaObject(
82 PMOS_COMMAND_BUFFER cmdBuffer,
83 PMHW_BATCH_BUFFER batchBuffer,
84 PMHW_MEDIA_OBJECT_PARAMS params)
85 {
86 MHW_FUNCTION_ENTER;
87
88 MHW_MI_CHK_NULL(params);
89
90 mhw_render_g12_X::MEDIA_OBJECT_CMD *cmd;
91 if (cmdBuffer)
92 {
93 cmd = (mhw_render_g12_X::MEDIA_OBJECT_CMD*)cmdBuffer->pCmdPtr;
94 }
95 else if (batchBuffer)
96 {
97 cmd = (mhw_render_g12_X::MEDIA_OBJECT_CMD*)(batchBuffer->pData + batchBuffer->iCurrent);
98 }
99 else
100 {
101 MHW_ASSERTMESSAGE("No valid buffer to add the command to!");
102 return MOS_STATUS_INVALID_PARAMETER;
103 }
104
105 MHW_MI_CHK_STATUS(MhwRenderInterfaceGeneric<mhw_render_g12_X>::AddMediaObject(cmdBuffer, batchBuffer, params));
106
107 MHW_MI_CHK_NULL(cmd);
108 cmd->DW4.XPosition = params->VfeScoreboard.Value[0];
109 cmd->DW4.YPosition = params->VfeScoreboard.Value[1];
110
111 return MOS_STATUS_SUCCESS;
112 }
113
AddGpgpuCsrBaseAddrCmd(PMOS_COMMAND_BUFFER cmdBuffer,PMOS_RESOURCE csrResource)114 MOS_STATUS MhwRenderInterfaceG12::AddGpgpuCsrBaseAddrCmd(
115 PMOS_COMMAND_BUFFER cmdBuffer,
116 PMOS_RESOURCE csrResource)
117 {
118 MHW_MI_CHK_NULL(m_osInterface);
119 MHW_MI_CHK_NULL(cmdBuffer);
120 MHW_MI_CHK_NULL(csrResource);
121
122 #if (!EMUL)
123 MHW_NORMALMESSAGE("GPGPU_CSR_BASE_ADDRESS not supported.");
124 return MOS_STATUS_SUCCESS;
125 #endif
126
127 mhw_render_g12_X::GPGPU_CSR_BASE_ADDRESS_CMD cmd;
128 MHW_RESOURCE_PARAMS resourceParams;
129 MOS_ZeroMemory(&resourceParams, sizeof(resourceParams));
130 resourceParams.presResource = csrResource;
131 resourceParams.pdwCmd = cmd.DW1_2.Value;
132 resourceParams.dwLocationInCmd = 1;
133
134 MHW_MI_CHK_STATUS(AddResourceToCmd(
135 m_osInterface,
136 cmdBuffer,
137 &resourceParams));
138
139 MHW_MI_CHK_STATUS(m_osInterface->pfnAddCommand(cmdBuffer, &cmd, cmd.byteSize));
140
141 return MOS_STATUS_SUCCESS;
142 }
143
EnableL3Caching(PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS cacheSettings)144 MOS_STATUS MhwRenderInterfaceG12::EnableL3Caching(
145 PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS cacheSettings )
146 {
147 // L3 Caching enabled by default
148 m_l3CacheConfig.bL3CachingEnabled = true;
149 m_l3CacheConfig.dwRcsL3CacheAllocReg_Register = M_MMIO_RCS_L3ALLOCREG;
150 m_l3CacheConfig.dwRcsL3CacheTcCntlReg_Register = M_MMIO_RCS_TCCNTLREG;
151 m_l3CacheConfig.dwCcs0L3CacheAllocReg_Register = M_MMIO_CCS0_L3ALLOCREG;
152 m_l3CacheConfig.dwCcs0L3CacheTcCntlReg_Register = M_MMIO_CCS0_TCCNTLREG;
153 if (cacheSettings)
154 {
155 PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G12 cacheSettingsG12 = dynamic_cast<PMHW_RENDER_ENGINE_L3_CACHE_SETTINGS_G12>(cacheSettings);
156 if (cacheSettingsG12 == nullptr)
157 {
158 MHW_ASSERTMESSAGE("Gen12-Specific Params are needed.");
159 return MOS_STATUS_INVALID_PARAMETER;
160 }
161 m_l3CacheConfig.dwL3CacheAllocReg_Setting = cacheSettingsG12->dwAllocReg;
162 m_l3CacheConfig.dwL3CacheTcCntlReg_Setting = cacheSettingsG12->dwTcCntlReg;
163 // update default settings is needed from CM HAL call
164 if (cacheSettingsG12->bUpdateDefault)
165 {
166 m_l3CacheAllocRegisterValueDefault = cacheSettingsG12->dwAllocReg;
167 m_l3CacheTcCntlRegisterValueDefault = cacheSettingsG12->dwTcCntlReg;
168 }
169 }
170 else // Use the default setting if regkey is not set
171 {
172 // different default settings after CM HAL call
173 m_l3CacheConfig.dwL3CacheAllocReg_Setting = m_l3CacheAllocRegisterValueDefault;
174 m_l3CacheConfig.dwL3CacheTcCntlReg_Setting = m_l3CacheTcCntlRegisterValueDefault;
175 }
176
177 return MOS_STATUS_SUCCESS;
178 }
179
SetL3Cache(PMOS_COMMAND_BUFFER cmdBuffer)180 MOS_STATUS MhwRenderInterfaceG12::SetL3Cache( PMOS_COMMAND_BUFFER cmdBuffer )
181 {
182 MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
183
184 MHW_MI_CHK_NULL( cmdBuffer );
185
186 if ( m_l3CacheConfig.bL3CachingEnabled )
187 {
188 MHW_MI_LOAD_REGISTER_IMM_PARAMS loadRegisterParams;
189
190 //L3CacheAllocReg_Setting and L3CacheTcCntlReg_Setting
191 if ((m_l3CacheConfig.dwL3CacheAllocReg_Setting != 0) || (m_l3CacheConfig.dwL3CacheTcCntlReg_Setting != 0))
192 {
193 //update L3 AllocReg setting for RCS; CCS L3 AllocReg setting will be dulicated from RCS
194 MOS_ZeroMemory(&loadRegisterParams, sizeof(loadRegisterParams));
195 loadRegisterParams.dwRegister = m_l3CacheConfig.dwRcsL3CacheAllocReg_Register;
196 loadRegisterParams.dwData = m_l3CacheConfig.dwL3CacheAllocReg_Setting;
197 MHW_MI_CHK_STATUS(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &loadRegisterParams));
198
199 //update L3 TcCntlReg setting for RCS; CCS L3 TcCntlReg setting will be dulicated from RCS
200 MOS_ZeroMemory(&loadRegisterParams, sizeof(loadRegisterParams));
201 loadRegisterParams.dwRegister = m_l3CacheConfig.dwRcsL3CacheTcCntlReg_Register;
202 loadRegisterParams.dwData = m_l3CacheConfig.dwL3CacheTcCntlReg_Setting;
203 MHW_MI_CHK_STATUS(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &loadRegisterParams));
204 }
205 }
206
207 return eStatus;
208 }
209
InitMmioRegisters()210 void MhwRenderInterfaceG12::InitMmioRegisters()
211 {
212 MHW_MI_MMIOREGISTERS *mmioRegisters = &m_mmioRegisters;
213 mmioRegisters->generalPurposeRegister0LoOffset = CS_GENERAL_PURPOSE_REGISTER0_LO_OFFSET_G12;
214 mmioRegisters->generalPurposeRegister0HiOffset = CS_GENERAL_PURPOSE_REGISTER0_HI_OFFSET_G12;
215 mmioRegisters->generalPurposeRegister4LoOffset = CS_GENERAL_PURPOSE_REGISTER4_LO_OFFSET_G12;
216 mmioRegisters->generalPurposeRegister4HiOffset = CS_GENERAL_PURPOSE_REGISTER4_HI_OFFSET_G12;
217 mmioRegisters->generalPurposeRegister11LoOffset = CS_GENERAL_PURPOSE_REGISTER11_LO_OFFSET_G12;
218 mmioRegisters->generalPurposeRegister11HiOffset = CS_GENERAL_PURPOSE_REGISTER11_HI_OFFSET_G12;
219 mmioRegisters->generalPurposeRegister12LoOffset = CS_GENERAL_PURPOSE_REGISTER12_LO_OFFSET_G12;
220 mmioRegisters->generalPurposeRegister12HiOffset = CS_GENERAL_PURPOSE_REGISTER12_HI_OFFSET_G12;
221 }
222