xref: /aosp_15_r20/external/coreboot/src/soc/mediatek/mt8183/md_ctrl.c (revision b9411a12aaaa7e1e6a6fb7c5e057f44ee179a49c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 
3 #include <device/mmio.h>
4 #include <soc/addressmap.h>
5 #include <soc/infracfg.h>
6 #include <soc/pll.h>
7 #include <soc/md_ctrl.h>
8 
9 #define TOPCKGEN_CLK_MODE_MD_32K     (1 << 8)
10 #define TOPCKGEN_CLK_MODE_MD_26M     (1 << 9)
11 #define INFRA_MISC2_SRCCLKENA_RELEASE (0xFF)
12 
internal_md_power_down(void)13 static void internal_md_power_down(void)
14 {
15 	/* Gating MD clock */
16 	setbits32(&mtk_topckgen->clk_mode,
17 		TOPCKGEN_CLK_MODE_MD_32K | TOPCKGEN_CLK_MODE_MD_26M);
18 	/* Release SRCCLKENA */
19 	clrbits32(&mt8183_infracfg->infra_misc2,
20 		INFRA_MISC2_SRCCLKENA_RELEASE);
21 }
22 
mtk_md_early_init(void)23 void mtk_md_early_init(void)
24 {
25 	internal_md_power_down();
26 }
27