1 /* 2 * File : ls1c.h 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team 5 * 6 * The license and distribution terms for this file may be 7 * found in the file LICENSE in this distribution or at 8 * http://www.rt-thread.org/license/LICENSE 9 * 10 * Change Logs: 11 * Date Author Notes 12 * 2011-08-08 lgnq first version 13 * 2015-07-06 chinesebear modified for loongson 1c 14 */ 15 16 #ifndef __LS1C_H__ 17 #define __LS1C_H__ 18 19 #include "../common/mipsregs.h" 20 21 #define LS1C_ACPI_IRQ 0 22 #define LS1C_HPET_IRQ 1 23 //#define LS1C_UART0_IRQ 3 // linux����3��v1.4�汾��1c�ֲ�����2�������Σ���ȷ�� 24 #define LS1C_UART1_IRQ 4 25 #define LS1C_UART2_IRQ 5 26 #define LS1C_CAN0_IRQ 6 27 #define LS1C_CAN1_IRQ 7 28 #define LS1C_SPI0_IRQ 8 29 #define LS1C_SPI1_IRQ 9 30 #define LS1C_AC97_IRQ 10 31 #define LS1C_MS_IRQ 11 32 #define LS1C_KB_IRQ 12 33 #define LS1C_DMA0_IRQ 13 34 #define LS1C_DMA1_IRQ 14 35 #define LS1C_DMA2_IRQ 15 36 #define LS1C_NAND_IRQ 16 37 #define LS1C_PWM0_IRQ 17 38 #define LS1C_PWM1_IRQ 18 39 #define LS1C_PWM2_IRQ 19 40 #define LS1C_PWM3_IRQ 20 41 #define LS1C_RTC_INT0_IRQ 21 42 #define LS1C_RTC_INT1_IRQ 22 43 #define LS1C_RTC_INT2_IRQ 23 44 #define LS1C_UART3_IRQ 29 45 #define LS1C_ADC_IRQ 30 46 #define LS1C_SDIO_IRQ 31 47 48 49 #define LS1C_EHCI_IRQ (32+0) 50 #define LS1C_OHCI_IRQ (32+1) 51 #define LS1C_OTG_IRQ (32+2) 52 #define LS1C_MAC_IRQ (32+3) 53 #define LS1C_CAM_IRQ (32+4) 54 #define LS1C_UART4_IRQ (32+5) 55 #define LS1C_UART5_IRQ (32+6) 56 #define LS1C_UART6_IRQ (32+7) 57 #define LS1C_UART7_IRQ (32+8) 58 #define LS1C_UART8_IRQ (32+9) 59 #define LS1C_UART9_IRQ (32+13) 60 #define LS1C_UART10_IRQ (32+14) 61 #define LS1C_UART11_IRQ (32+15) 62 #define LS1C_I2C2_IRQ (32+17) 63 #define LS1C_I2C1_IRQ (32+18) 64 #define LS1C_I2C0_IRQ (32+19) 65 66 67 #define LS1C_GPIO_IRQ 64 68 #define LS1C_GPIO_FIRST_IRQ 64 69 #define LS1C_GPIO_IRQ_COUNT 96 70 #define LS1C_GPIO_LAST_IRQ (LS1C_GPIO_FIRST_IRQ + LS1C_GPIO_IRQ_COUNT-1) 71 72 73 #define LS1C_LAST_IRQ 159 74 #define LS1C_INTREG_BASE 0xbfd01040 75 76 // ��о1c���жϷ�Ϊ���飬ÿ��32�� 77 #define LS1C_NR_IRQS (32*5) 78 79 80 // GPIO��ź��жϺ�֮��Ļ���ת�� 81 #define LS1C_GPIO_TO_IRQ(GPIOn) (LS1C_GPIO_FIRST_IRQ + (GPIOn)) 82 #define LS1C_IRQ_TO_GPIO(IRQn) ((IRQn) - LS1C_GPIO_FIRST_IRQ) 83 84 85 struct ls1c_intc_regs 86 { 87 volatile unsigned int int_isr; 88 volatile unsigned int int_en; 89 volatile unsigned int int_set; 90 volatile unsigned int int_clr; /* offset 0x10*/ 91 volatile unsigned int int_pol; 92 volatile unsigned int int_edge; /* offset 0 */ 93 }; 94 95 struct ls1c_cop_global_regs 96 { 97 volatile unsigned int control; 98 volatile unsigned int rd_inten; 99 volatile unsigned int wr_inten; 100 volatile unsigned int rd_intisr; /* offset 0x10*/ 101 volatile unsigned int wr_intisr; 102 unsigned int unused[11]; 103 } ; 104 105 struct ls1c_cop_channel_regs 106 { 107 volatile unsigned int rd_control; 108 volatile unsigned int rd_src; 109 volatile unsigned int rd_cnt; 110 volatile unsigned int rd_status; /* offset 0x10*/ 111 volatile unsigned int wr_control; 112 volatile unsigned int wr_src; 113 volatile unsigned int wr_cnt; 114 volatile unsigned int wr_status; /* offset 0x10*/ 115 } ; 116 117 struct ls1c_cop_regs 118 { 119 struct ls1c_cop_global_regs global; 120 struct ls1c_cop_channel_regs chan[8][2]; 121 } ; 122 123 #define __REG8(addr) *((volatile unsigned char *)(addr)) 124 #define __REG16(addr) *((volatile unsigned short *)(addr)) 125 #define __REG32(addr) *((volatile unsigned int *)(addr)) 126 127 #define GMAC0_BASE 0xBFE10000 128 #define GMAC0_DMA_BASE 0xBFE11000 129 #define GMAC1_BASE 0xBFE20000 130 #define GMAC1_DMA_BASE 0xBFE21000 131 #define I2C0_BASE 0xBFE58000 132 #define PWM0_BASE 0xBFE5C000 133 #define PWM1_BASE 0xBFE5C010 134 #define PWM2_BASE 0xBFE5C020 135 #define PWM3_BASE 0xBFE5C030 136 #define WDT_BASE 0xBFE5C060 137 #define RTC_BASE 0xBFE64000 138 #define I2C1_BASE 0xBFE68000 139 #define I2C2_BASE 0xBFE70000 140 #define AC97_BASE 0xBFE74000 141 #define NAND_BASE 0xBFE78000 142 #define SPI_BASE 0xBFE80000 143 #define CAN1_BASE 0xBF004300 144 #define CAN0_BASE 0xBF004400 145 146 /* Watch Dog registers */ 147 #define WDT_EN __REG32(WDT_BASE + 0x00) 148 #define WDT_SET __REG32(WDT_BASE + 0x04) 149 #define WDT_TIMER __REG32(WDT_BASE + 0x08) 150 151 #define PLL_FREQ __REG32(0xbfe78030) 152 #define PLL_DIV_PARAM __REG32(0xbfe78034) 153 154 #endif 155 156